Add shodan debug platform definition

Override the memory size definition for debug mode. The default system
configuration matches the HW config

Bug: 258850990
Change-Id: I829124ee5a1bacf661e63e6a88bdf713e6bdd9de

platforms/secure.repl

diff --git a/platforms/secure.repl b/platforms/secure.repl
index 8c64c69..f677e7f 100644
--- a/platforms/secure.repl
+++ b/platforms/secure.repl
@@ -13,20 +13,17 @@
 rom: Memory.MappedMemory @ sysbus 0x00008000
     size: 0x00008000
 
-// RAM_SEC           [‘h1000_0000 - ‘h10FF_FFFF)  16M RAM for Security Core (debugging size)
-// It is larger than what is defined in top_matcha_memory.ld to support debug SW.
-// TODO(hcindyl): override the debug memory config for debug repl.
+// RAM_SEC           [‘h1000_0000 - ‘h1001_FFFF)  128KB RAM for Security Core
 ram_sec: Memory.MappedMemory @ sysbus 0x10000000
-    size: 0x01000000
+    size: 0x20000
 
 // RAM_RET           [‘h4060_0000 - ‘h4060_0FFF)   4KB RAM for debug/retention
 ram_ret_aon: Memory.MappedMemory @ sysbus 0x40600000
     size: 0x1000
 
-// eFLASH            [‘h2000_0000 - ‘h20FF_FFFF)  16M eFlash for Security Core (debugging size)
-// TODO(hcindyl): override the debug memory config for debug repl.
+// eFLASH            [‘h2000_0000 - ‘h200F_FFFF)  1MB eFlash for Security Core
 eflash: Memory.MappedMemory @ sysbus 0x20000000
-    size: 0x01000000
+    size: 0x100000
 
 // UART0             [‘h4000_0000 - ‘h4000_0FFF)   4KB UART0 for Security Core
 uart0: UART.OpenTitan_UART @ sysbus 0x40000000

platforms/shodan-debug.repl

diff --git a/platforms/shodan-debug.repl b/platforms/shodan-debug.repl
new file mode 100644
index 0000000..0a5bf30
--- /dev/null
+++ b/platforms/shodan-debug.repl
@@ -0,0 +1,13 @@
+// A renode platform file used by debug config
+using "sim/config/platforms/shodan.repl"
+
+
+// Override the memory size for debug workloads
+
+// RAM_SEC           [‘h1000_0000 - ‘h1001_FFFF)  16M RAM for Security Core (debugging size)
+ram_sec:
+    size: 0x01000000
+
+// eFLASH            [‘h2000_0000 - ‘h20FF_FFFF)  16MB eFlash for Security Core (debugging size)
+eflash:
+    size: 0x01000000

shodan.resc

diff --git a/shodan.resc b/shodan.resc
index a619c7b..810768a 100644
--- a/shodan.resc
+++ b/shodan.resc
@@ -14,7 +14,9 @@
 include @sim/renode/tools/sel4_extensions/seL4Extensions.cs
 include @sim/config/shodan_infrastructure/AddressRangeStub.cs
 
-machine LoadPlatformDescription @sim/config/platforms/shodan.repl
+$repl_file ?= @sim/config/platforms/shodan.repl
+
+machine LoadPlatformDescription $repl_file
 
 $term_port?=3456
 emulation CreateServerSocketTerminal $term_port "term" false