832f89057660bfbe9dfe0bfba4d5e0897c074a6c - sim/config

commit: 832f89057660bfbe9dfe0bfba4d5e0897c074a6c

[log]
author: Adam Jesionowski <jesionowski@google.com>

Fri Apr 29 12:55:37 2022 -0700
committer: Adam Jesionowski <jesionowski@google.com>

Fri Apr 29 12:55:37 2022 -0700
tree: 6f42d01766c24f14dff1b9cc9334d2b74a1346e6
parent: af1b1ec85e1d0a2e7acde4fea91bd90c585e8390 [diff]

Add Core to SystemBus registration

Core specific memory should have this according to AntMicro.

Change-Id: Ia95e972c62b86faf13178c9f041928f9241c8bbd

shodan_infrastructure/SpringbokRiscV32.cs[diff]

1 file changed

tree: 6f42d01766c24f14dff1b9cc9334d2b74a1346e6

platforms/
shodan_infrastructure/
gdbinit
opentitan-earlgrey-gen.repl
shodan.resc
springbok.resc