)]}'
{
  "commit": "832f89057660bfbe9dfe0bfba4d5e0897c074a6c",
  "tree": "6f42d01766c24f14dff1b9cc9334d2b74a1346e6",
  "parents": [
    "af1b1ec85e1d0a2e7acde4fea91bd90c585e8390"
  ],
  "author": {
    "name": "Adam Jesionowski",
    "email": "jesionowski@google.com",
    "time": "Fri Apr 29 12:55:37 2022 -0700"
  },
  "committer": {
    "name": "Adam Jesionowski",
    "email": "jesionowski@google.com",
    "time": "Fri Apr 29 12:55:37 2022 -0700"
  },
  "message": "Add Core to SystemBus registration\n\nCore specific memory should have this according to AntMicro.\n\nChange-Id: Ia95e972c62b86faf13178c9f041928f9241c8bbd\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "8d348d9a53823d9421d2fb9192c87d34c3ae7d44",
      "old_mode": 33188,
      "old_path": "shodan_infrastructure/SpringbokRiscV32.cs",
      "new_id": "cd69f8aa5d9314812c140fdfc645d5e339476b3b",
      "new_mode": 33188,
      "new_path": "shodan_infrastructure/SpringbokRiscV32.cs"
    }
  ]
}