sencha: match sail clint frequency to cheriot-rtos board config
Cheriot-rtos' sail board config has timer_hz=2000. Match this in the
equivalent renode config so time calculations by the tickless scheduler
work as intended. Leave the sencha clint frequency as-is for now; though
it does not match the sencha.json board config because that breaks the
soundstream demo for some yet-to-be-determined reason. With this change
the cheriot-rtos testbench passes with the tickless scheduler.
Bug: 350801040
Change-Id: Ib459b9731f718e7c949673ab66d4dee7206e200d
diff --git a/platforms/cheriot.repl b/platforms/cheriot.repl
index 9e82f1a..292731d 100644
--- a/platforms/cheriot.repl
+++ b/platforms/cheriot.repl
@@ -32,7 +32,3 @@
numberOfContexts: 1
prioritiesEnabled: false
-smc_clint: IRQControllers.CoreLevelInterruptor @ sysbus 0x02000000
- frequency: 66000000
- [0, 1] ->cpu1@[3, 7]
-
diff --git a/platforms/sail.repl b/platforms/sail.repl
index e723c38..80ddf81 100644
--- a/platforms/sail.repl
+++ b/platforms/sail.repl
@@ -17,5 +17,10 @@
using "sim/config/platforms/cheriot.repl"
+// NB: match timer_hz in cheriot-rtos/sdk/boards/sail.json
+smc_clint: IRQControllers.CoreLevelInterruptor @ sysbus 0x02000000
+ frequency: 2000
+ [0, 1] ->cpu1@[3, 7]
+
uart5: Antmicro.Renode.Peripherals.UART.TrivialUart @ sysbus 0x10000000
diff --git a/platforms/sencha_smc.repl b/platforms/sencha_smc.repl
index 8910567..9a25c28 100644
--- a/platforms/sencha_smc.repl
+++ b/platforms/sencha_smc.repl
@@ -19,10 +19,14 @@
using "sim/config/platforms/cheriot.repl"
-uart5: Antmicro.Renode.Peripherals.UART.TrivialUart @ sysbus 0x54000000
+// NB: match timer_hz in cheriot-rtos/sdk/boards/sencha.json
+smc_clint: IRQControllers.CoreLevelInterruptor @ sysbus 0x02000000
+ frequency: 66000000
+ [0, 1] ->cpu1@[3, 7]
// Control block for the SMC, lets us pause/restart the core at an arbitrary PC.
smc_control: MpactCPU.SmcCheriot_ControlBlock @ sysbus 0x54020000
cpu: cpu1
pc: 0x80000000
+uart5: Antmicro.Renode.Peripherals.UART.TrivialUart @ sysbus 0x54000000
