// ***************************************************
// Secure
// ***************************************************

cpu0: CPU.IbexRiscV32 @ sysbus
    hartId: 0
    cpuType: "rv32imac"
    timeProvider: clint
    allowUnalignedAccesses: true

// ORDER EVERY DEVICE BY ADDRESS FOR SANITY

// ROM               [‘h0000_8000 - ‘h0000_BFFF)  16KB ROM for Security core secure boot code storage
rom: Memory.MappedMemory @ sysbus 0x00008000
    size: 0x00004000

// CLINT             ['h0200_0000 - 'h0200_0FFF)   4KB CLINT (not in design doc mem map)
clint: IRQControllers.CoreLevelInterruptor @ sysbus 0x02000000
    [0,1] -> cpu0@[3,7]
    numberOfTargets: 1
    frequency: 24000000

// RAM_SEC           [‘h1000_0000 - ‘h10FF_FFFF)  16M RAM for Security Core (debugging size)
ram_sec: Memory.MappedMemory @ sysbus 0x10000000
    size: 0x01000000

// RAM_RET           [‘h4060_0000 - ‘h4060_0FFF)   4KB RAM for debug/retention
ram_ret_aon: Memory.MappedMemory @ sysbus 0x40600000
    size: 0x1000

// eFLASH            [‘h2000_0000 - ‘h20FF_FFFF)  16M eFlash for Security Core (debugging size)
eflash: Memory.MappedMemory @ sysbus 0x20000000
    size: 0x01000000

// UART0             [‘h4000_0000 - ‘h4000_0FFF)   4KB UART0 for Security Core
uart0: UART.OpenTitan_UART @ sysbus 0x40000000
    TxWatermarkIRQ -> plic@1
    RxWatermarkIRQ -> plic@2
    TxEmptyIRQ -> plic@3
    RxOverflowIRQ -> plic@4
    RxFrameErrorIRQ -> plic@5
    RxBreakErrorIRQ -> plic@6
    RxTimeoutIRQ -> plic@7
    RxParityErrorIRQ -> plic@8

// UART1             [‘h4001_0000 - ‘h4001_0FFF)   4KB UART1 (Reserved)
uart1: UART.OpenTitan_UART @ sysbus 0x40010000
    TxWatermarkIRQ -> plic@9
    RxWatermarkIRQ -> plic@10
    TxEmptyIRQ -> plic@11
    RxOverflowIRQ -> plic@12
    RxFrameErrorIRQ -> plic@13
    RxBreakErrorIRQ -> plic@14
    RxTimeoutIRQ -> plic@15
    RxParityErrorIRQ -> plic@16

// UART2             [‘h4002_0000 - ‘h4002_0FFF)   4KB UART2 for Vector Core
uart2: UART.OpenTitan_UART @ sysbus 0x40020000
    TxWatermarkIRQ -> plic@17
    RxWatermarkIRQ -> plic@18
    TxEmptyIRQ -> plic@19
    RxOverflowIRQ -> plic@20
    RxFrameErrorIRQ -> plic@21
    RxBreakErrorIRQ -> plic@22
    RxTimeoutIRQ -> plic@23
    RxParityErrorIRQ -> plic@24

// UART3             [‘h4003_0000 - ‘h4003_0FFF)   4KB UART3 (Reserved)
uart3: UART.OpenTitan_UART @ sysbus 0x40030000
    TxWatermarkIRQ -> plic@25
    RxWatermarkIRQ -> plic@26
    TxEmptyIRQ -> plic@27
    RxOverflowIRQ -> plic@28
    RxFrameErrorIRQ -> plic@29
    RxBreakErrorIRQ -> plic@30
    RxTimeoutIRQ -> plic@31
    RxParityErrorIRQ -> plic@32

// GPIO              [‘h4004_0000 - ‘h4004_0FFF)   4KB GPIO
gpio: GPIOPort.OpenTitan_GPIO @ sysbus 0x40040000
    IRQ -> plic@33

// SPI_Device        [‘h4005_0000 - ‘h4005_1FFF)   8KB SPI Device
// SPI_HOST0         [‘h4006_0000 - ‘h4006_0FFF)   4KB SPI HOST 0
// SPI_HOST1         [‘h4007_0000 - ‘h4007_0FFF)   4KB SPI HOST 1

// I2C0              [‘h4008_0000 - ‘h4008_0FFF)   4KB I2C0
i2c0: I2C.OpenTitan_I2C @ sysbus 0x40080000

// I2C1              [‘h4009_0000 - ‘h4009_0FFF)   4KB I2C1
i2c1: I2C.OpenTitan_I2C @ sysbus 0x40090000

// I2C2              [‘h400A_0000 - ‘h400A_0FFF)   4KB I2C2
i2c2: I2C.OpenTitan_I2C @ sysbus 0x400A0000

// PATGEN            [‘h400E_0000 - ‘h400E_0FFF)   4KB PATGEN

// Fake network-port-backed UART for testing in Renode
net_uart: NetUart @ sysbus 0x400F0000
    name: "NetUart"
    port: 31415

// RV_TIMER          [‘h4010_0000 - ‘h4010_0FFF)   4KB RV Timer for Security Core
timer: Timers.OpenTitan_Timer@ sysbus 0x40100000
    frequency: 24000000
    IRQ -> cpu0@7

// USBDEV            [‘h4011_0000 - ‘h4011_0FFF)   4KB USBDEV
// OTP_CTRL          [‘h4013_0000 - ‘h4013_3FFF)  16KB OTP Ctrl
// LC_CTRL           [‘h4014_0000 - ‘h4014_0FFF)   4KB Life Cycle Ctrl
// ALERT_HANDLER     [‘h4015_0000 - ‘h4015_0FFF)   4KB Alert Handler Ctrl

// PWRMGR_AON        [‘h4040_0000 - ‘h4040_0FFF)   4KB Power Manger Control
pwrmgr: Miscellaneous.OpenTitan_PowerManager@ sysbus 0x40400000

// RSTMGR_AON        [‘h4041_0000 - ‘h4041_0FFF)   4KB Reset Manger Control
// CLKMGR_AON        [‘h4042_0000 - ‘h4042_0FFF)   4KB Clock Manger Control
// ADCMGR_AON        [‘h4044_0000 - ‘h4044_0FFF)   4KB ADC

// The OpenTitan bootrom will error out if pinmux registers are locked,
// so we work around that by stubbing out the pinmux range to return
// 0xFFFFFFFF which means "unlocked"

// PINMUX            [‘h4046_0000 - ‘h4046_0FFF)   4KB PINMUX
pinmux_stub : AddressRangeStub @ sysbus 0x40460000
    size: 0x1000
    value: 0xFFFFFFFF

// AON_TIMER         [‘h4047_0000 - ‘h4047_0FFF)   4KB AON_TIMER
// AST               [‘h4048_0000 - ‘h4048_0FFF)   4KB AST
// SENSOR_CTRL       [‘h4049_0000 - ‘h4049_0FFF)   4KB Sensor Ctrl  (Details need to be added for mic/cam interface)
// SRAM_CTRL_RET_AON [‘h4050_0000 - ‘h4050_0FFF)   4KB AON RET_SRAM Ctrl

// Simulated SRAM used to indicate test status to simulator
swteststatus: Miscellaneous.OpenTitan_VerilatorSwTestStatus @ sysbus 0x30000000

// FLASH_CTRL        [‘h4100_0000 - ‘h4100_0FFF)   4KB Flash Control

// RV_PLIC           [‘h4800_0000 - ‘h5000_0000) 128MB RV PLIC
plic: IRQControllers.PlatformLevelInterruptController @ sysbus 0x48000000
    // Numbers on the left (0 ->) index PLIC GetGPIOs.
    //
    // Numbers on the right reference bits in the target MIP.
    // Bit 11 corresponds MEIP and bit 9 to SEIP.
    0 -> cpu0@11
    numberOfSources: 186
    numberOfContexts: 1

// AES               [‘h4110_0000 - ‘h4110_0FFF)   4KB AES Control
// HMAC              [‘h4111_0000 - ‘h4111_0FFF)   4KB HMAC Control
// KMAC              [‘h4112_0000 - ‘h4112_0FFF)   4KB KMAC Control
// OTBN              ['h4113_0000 - 'h4113_FFFF)  64KB OTBN
// KEYMGR            [‘h4114_0000 - ‘h4114_0FFF)   4KB KEY Manager
// CSRNG             [‘h4115_0000 - ‘h4115_0FFF)   4KB CSRNG  (Cryptographically Secure Random Number Generator) Control
// ENTROPY_SRC       [‘h4116_0000 - ‘h4116_0FFF)   4KB ENTROPY SRC control
// EDN0              [‘h4117_0000 - ‘h4117_0FFF)   4KB EDN0
// EDN1              [‘h4118_0000 - ‘h4118_0FFF)   4KB EDN1
// SRAM_CTRL_MAIN    [‘h411C_0000 - ‘h411C_0FFF)   4KB SRAM Control
// ROM_CTRL          [‘h411E_0000 - ‘h411E_0FFF)   4KB ROM Control
// RV_CORE_IBEX      [‘h411F_0000 - ‘h411F_0FFF)   4KB RV Core Ibex

// Flash/MRAM        [‘h4400_0000 - ‘h44FF_FFFF)  16MB External Non-Volatile Memory
// TODO(b/197745020) - temporarily 36M for debug (non-LTO) rust component builds
//                     NB: the last 4M are written with the ELF model
extflash: Memory.MappedMemory @ sysbus 0x44000000
    size: 0x02400000

// Tag memory for debugging
sysbus:
    init:
        Tag <0x40000000 0x1000> "OPENTITAN_EARLGREY_DEV_UART0"
        Tag <0x40010000 0x1000> "OPENTITAN_EARLGREY_DEV_UART1"
        Tag <0x40020000 0x1000> "OPENTITAN_EARLGREY_DEV_UART2"
        Tag <0x40030000 0x1000> "OPENTITAN_EARLGREY_DEV_UART3"
        Tag <0x40040000 0x1000> "OPENTITAN_EARLGREY_DEV_GPIO"
        Tag <0x40050000 0x2000> "OPENTITAN_EARLGREY_DEV_SPI_DEVICE"
        Tag <0x40060000 0x1000> "OPENTITAN_EARLGREY_DEV_SPI_HOST0"
        Tag <0x40070000 0x1000> "OPENTITAN_EARLGREY_DEV_SPI_HOST1"
        Tag <0x40080000 0x1000> "OPENTITAN_EARLGREY_DEV_I2C0"
        Tag <0x40090000 0x1000> "OPENTITAN_EARLGREY_DEV_I2C1"
        Tag <0x400A0000 0x1000> "OPENTITAN_EARLGREY_DEV_I2C2"
        Tag <0x400E0000 0x1000> "OPENTITAN_EARLGREY_DEV_PATTGEN"
        Tag <0x40100000 0x1000> "OPENTITAN_EARLGREY_DEV_RV_TIMER"
        Tag <0x40110000 0x1000> "OPENTITAN_EARLGREY_DEV_USBDEV"
        Tag <0x40130000 0x4000> "OPENTITAN_EARLGREY_DEV_OTP_CTRL"
        Tag <0x40140000 0x1000> "OPENTITAN_EARLGREY_DEV_LC_CTRL"
        Tag <0x40150000 0x1000> "OPENTITAN_EARLGREY_DEV_ALERT_HANDLER"
        Tag <0x40400000 0x1000> "OPENTITAN_EARLGREY_DEV_PWRMGR_AON"
        Tag <0x40410000 0x1000> "OPENTITAN_EARLGREY_DEV_RSTMGR_AON"
        Tag <0x40420000 0x1000> "OPENTITAN_EARLGREY_DEV_CLKMGR_AON"
        Tag <0x40440000 0x1000> "OPENTITAN_EARLGREY_DEV_ADC_CTRL_AON"
        Tag <0x40460000 0x1000> "OPENTITAN_EARLGREY_DEV_PINMUX_AON"
        Tag <0x40470000 0x1000> "OPENTITAN_EARLGREY_DEV_AON_TIMER_AON"
        Tag <0x40480000 0x1000> "OPENTITAN_EARLGREY_DEV_AST"
        Tag <0x40490000 0x1000> "OPENTITAN_EARLGREY_DEV_SENSOR_CTRL_AON"
        Tag <0x40500000 0x1000> "OPENTITAN_EARLGREY_DEV_SRAM_CTRL_RET_AON"
        Tag <0x41000000 0x1000> "OPENTITAN_EARLGREY_DEV_FLASH_CTRL"
        Tag <0x41200000 0x1000> "OPENTITAN_EARLGREY_DEV_RV_DM"
        Tag <0x48000000 0x8000000> "OPENTITAN_EARLGREY_DEV_RV_PLIC"
        Tag <0x41100000 0x1000> "OPENTITAN_EARLGREY_DEV_AES"
        Tag <0x41110000 0x1000> "OPENTITAN_EARLGREY_DEV_HMAC"
        Tag <0x41120000 0x1000> "OPENTITAN_EARLGREY_DEV_KMAC"
        Tag <0x41130000 0x10000> "OPENTITAN_EARLGREY_DEV_OTBN"
        Tag <0x41140000 0x1000> "OPENTITAN_EARLGREY_DEV_KEYMGR"
        Tag <0x41150000 0x1000> "OPENTITAN_EARLGREY_DEV_CSRNG"
        Tag <0x41160000 0x1000> "OPENTITAN_EARLGREY_DEV_ENTROPY"
        Tag <0x41170000 0x1000> "OPENTITAN_EARLGREY_DEV_EDN0"
        Tag <0x41180000 0x1000> "OPENTITAN_EARLGREY_DEV_EDN1"
        Tag <0x411C0000 0x1000> "OPENTITAN_EARLGREY_DEV_SRAM_CTRL"
        Tag <0x411E0000 0x1000> "OPENTITAN_EARLGREY_DEV_ROM_CTRL"
        Tag <0x411F0000 0x1000> "OPENTITAN_EARLGREY_DEV_RV_CORE_IBEX"