| # Copyright 2024 Google LLC |
| # |
| # Licensed under the Apache License, Version 2.0 (the "License"); |
| # you may not use this file except in compliance with the License. |
| # You may obtain a copy of the License at |
| # |
| # http:#www.apache.org/licenses/LICENSE-2.0 |
| # |
| # Unless required by applicable law or agreed to in writing, software |
| # distributed under the License is distributed on an "AS IS" BASIS, |
| # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
| # See the License for the specific language governing permissions and |
| # limitations under the License. |
| |
| # Renode script for testing the 2-core version of the Sencha platform |
| |
| $name?="bancha" |
| |
| using sysbus |
| mach create $name |
| |
| include @sim/config/shodan_infrastructure/MpactCPU.cs |
| EnsureTypeIsLoaded "Antmicro.Renode.Peripherals.MpactCPU.MpactBaseCPU" |
| EnsureTypeIsLoaded "Antmicro.Renode.Peripherals.MpactCPU.MpactPeripheral" |
| include @sim/config/shodan_infrastructure/MpactCheriotCPU.cs |
| EnsureTypeIsLoaded "Antmicro.Renode.Peripherals.MpactCPU.MpactCheriotCPU" |
| EnsureTypeIsLoaded "Antmicro.Renode.Peripherals.CPU.RiscV32" |
| include @sim/config/shodan_infrastructure/KelvinCPU.cs |
| EnsureTypeIsLoaded "Antmicro.Renode.Peripherals.CPU.KelvinCPU" |
| EnsureTypeIsLoaded "Antmicro.Renode.Peripherals.CPU.MlTopControlBlock" |
| #include @sim/config/shodan_infrastructure/SmcCheriotCPU.cs |
| #include @sim/config/shodan_infrastructure/Mailbox.cs |
| include @sim/config/shodan_infrastructure/AddressRangeStub.cs |
| include @sim/config/shodan_infrastructure/MatchaI2S.cs |
| EnsureTypeIsLoaded "Antmicro.Renode.Peripherals.Sound.MatchaI2S" |
| |
| $repl_file ?= @sim/config/platforms/bancha.repl |
| |
| machine LoadPlatformDescription $repl_file |
| |
| $term_port?=3456 |
| emulation CreateServerSocketTerminal $term_port "term" false |
| connector Connect uart5 term |
| |
| showAnalyzer "uart0-analyzer" sysbus.uart0 Antmicro.Renode.Analyzers.LoggingUartAnalyzer |
| showAnalyzer "uart5-analyzer" sysbus.uart5 Antmicro.Renode.Analyzers.LoggingUartAnalyzer |
| |
| # Set the uarts host/virt timestamp format. Options: None, Virtual, Host, Full. |
| uart0-analyzer TimestampFormat None |
| uart5-analyzer TimestampFormat None |
| |
| cpu0 IsHalted true |
| $cheriotLibrary ?= @out/cheriot/sim/librenode_mpact_cheriot.so |
| sysbus.cpu0 CpuLibraryPath $cheriotLibrary |
| |
| # Load the boot rom into the 32k rom at 0x8000 (useVirtualAddress = false, allowLoadsOnlyToMemory = false) |
| # Unlike the OT boot rom where cpu0 starts at the reset vecitor (@0x8080) |
| # the PC is initialized to the ELF entry point. |
| sysbus LoadELF @out/cheriot/bancha/boot_rom.elf false false cpu0 |
| |
| # Override cli_port to enable the command line interface on the specified port. |
| $cli_port?= 0 |
| $wait_for_cli ?= false |
| sysbus.cpu0 CLIPort $cli_port |
| sysbus.cpu0 WaitForCLI $wait_for_cli |
| |
| $tar ?= @out/cheriot/bancha/release/ext_flash.tar |
| $spi_flash_load_address ?= 0x44000000 |
| $sc_bin ?= @out/cheriot/bancha/release/tmp/cheriot-firmware.bin |
| $eflash_address ?= 0x20000000 |
| sysbus LoadBinary $sc_bin $eflash_address |
| sysbus LoadBinary $tar $spi_flash_load_address |
| #sysbus LoadSymbolsFrom $cheriot_elf |
| |
| # If we have a I2S peripheral, setup an audio file that we can use |
| # for sampling data. Note that the format for these files is raw |
| # sample data, left channel followed by right. |
| $i2s_mic_audio_file ?= @sim/config/shodan_infrastructure/test.raw |
| $i2s_speaker_audio_file ?= @/tmp/speaker.raw |
| |
| # Uncomment these lines to enable audio |
| i2s0 InputFile $i2s_mic_audio_file |
| #i2s0 OutputFile $i2s_speaker_audio_file |
| |
| $kelvinLibrary ?= @out/kelvin/sim/librenode_kelvin.so |
| sysbus.cpu2 CpuLibraryPath $kelvinLibrary |
| # Start the vector core at address 0 of its instruction TCM. |
| sysbus.cpu2 PC 0x80000000 |
| # Set the vector core to be less interactive to IO for faster execution |
| $vector_core_mips ?= 1000 |
| sysbus.cpu2 PerformanceInMips $vector_core_mips |
| |
| # NB: model is normally loaded from SPI |
| #$kelvin_bin?=@out/cheriot/sim/kelvin.bin |
| #sysbus LoadBinary $kelvin_bin 0x5A000000 |
| |
| # Start GDB and halt both cores so we can connect GDB before the bootrom has |
| # started. |
| # cpu2 does not support GDB. Please follow docs/KelvinIssDebugging.md to debug |
| # Kelvin programs. |
| $gdb_port?=3333 |
| machine StartGdbServer $gdb_port false cpu0 |
| |
| cpu0 IsHalted true |
| cpu2 IsHalted true |
| |
| # Enable for instruction & memory profiling. Data are written to |
| # $ROOTDIR/cache/renode/mpact_cheriot_renode* (to be fixed). |
| cpu0 SymbolFile @out/cheriot/bancha/boot_rom.elf |
| #cpu0 SymbolFile $cheriot_elf |
| #cpu0 InstProfile true |
| #cpu0 MemProfile true |
