sencha: track hardware memory map
Track the hardware memory map for the SMC. This requires equivalent
changes in the cheriot-rtos board description.
Change-Id: Id137211fa0b89c4140bd4cfefe0809f5e63bfc06
diff --git a/platforms/sencha_smc.repl b/platforms/sencha_smc.repl
index f8487ce..1acf7b1 100644
--- a/platforms/sencha_smc.repl
+++ b/platforms/sencha_smc.repl
@@ -17,12 +17,35 @@
// Sencha SMC is a CHERIoT RISC-V CPU
// ***************************************************
-using "sim/config/platforms/cheriot.repl"
+cpu1: MpactCPU.MpactCheriotCPU @ sysbus
+ id: 1
+ cpuType: "Mpact.Cheriot"
+ endianness: Endianess.LittleEndian
+ memoryBase: 0x50000000
+ memorySize: 0x80000
+ // XXX SWAG
+ revocationMemoryBase: 0x50070000
+ // Use the built-in clint to avoid update latency
+ // NB: beware case, these are properties
+ // NB: clint irq's are preset
+ ClintMMRBase: 0x02000000
+ ClintPeriod: 2000
+
+ram_smc : MpactCPU.MpactPeripheral @ sysbus 0x50000000
+ size: 0x80000
+ baseAddress: 0x50000000
+ mpactCpu: cpu1
+
+smc_plic: IRQControllers.PlatformLevelInterruptController @sysbus 0x60000000
+ 0 -> cpu1@11
+ numberOfSources: 42
+ numberOfContexts: 1
+ prioritiesEnabled: false
// Control block for the SMC, lets us pause/restart the core at an arbitrary PC.
smc_control: MpactCPU.SmcCheriot_ControlBlock @ sysbus 0x54020000
cpu: cpu1
- pc: 0x80000000
+ pc: 0x50000000
uart5: UART.OpenTitan_UART @ sysbus 0x54000000
TxWatermarkIRQ -> smc_plic@1
