diff --git a/platforms/secure.repl b/platforms/secure.repl
index aba132b..efbb488 100644
--- a/platforms/secure.repl
+++ b/platforms/secure.repl
@@ -5,22 +5,17 @@
 cpu0: CPU.IbexRiscV32 @ sysbus
     hartId: 0
     cpuType: "rv32imac"
-    timeProvider: clint
     allowUnalignedAccesses: true
 
 // ORDER EVERY DEVICE BY ADDRESS FOR SANITY
 
-// ROM               [‘h0000_8000 - ‘h0000_BFFF)  16KB ROM for Security core secure boot code storage
+// ROM               [‘h0000_8000 - ‘h0000_FFFF)  32KB ROM for Security core secure boot code storage
 rom: Memory.MappedMemory @ sysbus 0x00008000
-    size: 0x00004000
-
-// CLINT             ['h0200_0000 - 'h0200_0FFF)   4KB CLINT (not in design doc mem map)
-clint: IRQControllers.CoreLevelInterruptor @ sysbus 0x02000000
-    [0,1] -> cpu0@[3,7]
-    numberOfTargets: 1
-    frequency: 24000000
+    size: 0x00008000
 
 // RAM_SEC           [‘h1000_0000 - ‘h10FF_FFFF)  16M RAM for Security Core (debugging size)
+// It is larger than what is defined in top_matcha_memory.ld to support debug SW.
+// TODO(hcindyl): override the debug memory config for debug repl.
 ram_sec: Memory.MappedMemory @ sysbus 0x10000000
     size: 0x01000000
 
@@ -29,6 +24,7 @@
     size: 0x1000
 
 // eFLASH            [‘h2000_0000 - ‘h20FF_FFFF)  16M eFlash for Security Core (debugging size)
+// TODO(hcindyl): override the debug memory config for debug repl.
 eflash: Memory.MappedMemory @ sysbus 0x20000000
     size: 0x01000000
 
@@ -42,6 +38,7 @@
     RxBreakErrorIRQ -> plic@6
     RxTimeoutIRQ -> plic@7
     RxParityErrorIRQ -> plic@8
+    FatalAlert -> alert_handler@0
 
 // UART1             [‘h4001_0000 - ‘h4001_0FFF)   4KB UART1 (Reserved)
 uart1: UART.OpenTitan_UART @ sysbus 0x40010000
@@ -53,6 +50,7 @@
     RxBreakErrorIRQ -> plic@14
     RxTimeoutIRQ -> plic@15
     RxParityErrorIRQ -> plic@16
+    FatalAlert -> alert_handler@1
 
 // UART2             [‘h4002_0000 - ‘h4002_0FFF)   4KB UART2 for Vector Core
 uart2: UART.OpenTitan_UART @ sysbus 0x40020000
@@ -64,6 +62,7 @@
     RxBreakErrorIRQ -> plic@22
     RxTimeoutIRQ -> plic@23
     RxParityErrorIRQ -> plic@24
+    FatalAlert -> alert_handler@2
 
 // UART3             [‘h4003_0000 - ‘h4003_0FFF)   4KB UART3 (Reserved)
 uart3: UART.OpenTitan_UART @ sysbus 0x40030000
@@ -75,42 +74,108 @@
     RxBreakErrorIRQ -> plic@30
     RxTimeoutIRQ -> plic@31
     RxParityErrorIRQ -> plic@32
+    FatalAlert -> alert_handler@3
 
 // GPIO              [‘h4004_0000 - ‘h4004_0FFF)   4KB GPIO
 gpio: GPIOPort.OpenTitan_GPIO @ sysbus 0x40040000
     IRQ -> plic@33
+    FatalAlert -> alert_handler@4
 
 // SPI_Device        [‘h4005_0000 - ‘h4005_1FFF)   8KB SPI Device
+spi_device: SPI.OpenTitan_SpiDevice @ sysbus 0x40050000
+    FatalAlert -> alert_handler@5
+
 // SPI_HOST0         [‘h4006_0000 - ‘h4006_0FFF)   4KB SPI HOST 0
+spi_host0: SPI.OpenTitan_SpiHost@ sysbus 0x40300000
+    FatalAlert -> alert_handler@19
+    Error -> plic@131
+    SpiEvent -> plic@132
+    numberOfCSLines: 32
+
 // SPI_HOST1         [‘h4007_0000 - ‘h4007_0FFF)   4KB SPI HOST 1
+spi_host1: SPI.OpenTitan_SpiHost@ sysbus 0x40310000
+    FatalAlert -> alert_handler@20
+    Error -> plic@133
+    SpiEvent -> plic@134
+    numberOfCSLines: 32
 
 // I2C0              [‘h4008_0000 - ‘h4008_0FFF)   4KB I2C0
 i2c0: I2C.OpenTitan_I2C @ sysbus 0x40080000
+    FatalAlert -> alert_handler@6
 
 // I2C1              [‘h4009_0000 - ‘h4009_0FFF)   4KB I2C1
 i2c1: I2C.OpenTitan_I2C @ sysbus 0x40090000
+    FatalAlert -> alert_handler@7
 
 // I2C2              [‘h400A_0000 - ‘h400A_0FFF)   4KB I2C2
 i2c2: I2C.OpenTitan_I2C @ sysbus 0x400A0000
+    FatalAlert -> alert_handler@8
 
 // PATGEN            [‘h400E_0000 - ‘h400E_0FFF)   4KB PATGEN
 
 // RV_TIMER          [‘h4010_0000 - ‘h4010_0FFF)   4KB RV Timer for Security Core
-// TODO(hcindyl): Use upstream OpenTitan_Timer model
-timer: Timers.OpenTitan2_Timer@ sysbus 0x40100000
+timer: Timers.OpenTitan_Timer@ sysbus 0x40100000
     frequency: 24000000
     IRQ -> cpu0@7
+    FatalAlert -> alert_handler@10
 
 // USBDEV            [‘h4011_0000 - ‘h4011_0FFF)   4KB USBDEV
 // OTP_CTRL          [‘h4013_0000 - ‘h4013_3FFF)  16KB OTP Ctrl
+otp_ctrl: Miscellaneous.OpenTitan_OneTimeProgrammableMemoryController @ sysbus 0x40130000
+    FatalMacroAlert -> alert_handler@11
+    FatalCheckErrorAlert -> alert_handler@12
+    FatalBusAlert -> alert_handler@13
+    FatalPrimitiveOtpAlert -> alert_handler@14
+    RecoverablePrimitiveOtpAlert -> alert_handler@15
+    AValuesChain: "8638C62621EC19E8966416165252225F03B9C97821B7B107381030AB3D20AB124694BF85E417495A"
+    BValuesChain: "E679DF6E77EDDBECDE74B677DFF23AFFC3BFFB79B5FFFD87F930B4FB3F6BFF9A5F97BFD7FCBFE9FF"
+    CValuesChain: "0C1B73141BA20D421FD124302E8F443DE02C272E2CEEC1138DAD07CBD24A18F583A34D51A42A1E702A7E90F05A81D12E"
+    DValuesChain: "3E1FFB763FE3CDD61FF97735BEBF5CFDE5BDB7AFAEFEE19B9FBD9FCFD2EF3CF7CFEFFD53A7EE7FF36BFE92FDFA95F9AE"
+
 // LC_CTRL           [‘h4014_0000 - ‘h4014_0FFF)   4KB Life Cycle Ctrl
+lc_ctrl: Miscellaneous.OpenTitan_LifeCycleController @ sysbus 0x40140000
+    resetManager: rstmgr_aon
+    otpController: otp_ctrl
+    FatalProgAlert -> alert_handler@16
+    FatalStateAlert -> alert_handler@17
+    FatalBusAlert -> alert_handler@18
+    DeviceId: "BF5EA92044DAC540CFD1A00105568DFA97D9C35EA0407D71320B5E0434DB637F"
+    TestExitToken: "000102030405060708090A0B0C0D0E0F"
+    TestUnlockToken: "79DEF38F41A9B895F6BDF341BEADA9B6"
+    RMAToken: "4D89B62D287CB957C2500042306DFD57"
+
 // ALERT_HANDLER     [‘h4015_0000 - ‘h4015_0FFF)   4KB Alert Handler Ctrl
+alert_handler: Miscellaneous.OpenTitan_AlertHandler @ sysbus 0x40150000
+    ClassAInterrupt -> plic@127
+    ClassBInterrupt -> plic@128
+    ClassCInterrupt -> plic@129
+    ClassDInterrupt -> plic@130
 
 // PWRMGR_AON        [‘h4040_0000 - ‘h4040_0FFF)   4KB Power Manger Control
-pwrmgr: Miscellaneous.OpenTitan_PowerManager@ sysbus 0x40400000
+pwrmgr_aon: Miscellaneous.OpenTitan_PowerManager@ sysbus 0x40400000
+    FatalAlert -> alert_handler@22
 
 // RSTMGR_AON        [‘h4041_0000 - ‘h4041_0FFF)   4KB Reset Manger Control
+rstmgr_aon: Miscellaneous.OpenTitan_ResetManager @ sysbus 0x40410000
+    resetPC: 0x00008084
+    FatalAlert -> alert_handler@23
+    FatalConsistencyAlert -> alert_handler@24
+    init:
+        MarkAsSkippedOnLifeCycleReset sysbus.rstmgr_aon
+        MarkAsSkippedOnLifeCycleReset sysbus.pwrmgr_aon
+        MarkAsSkippedOnSystemReset sysbus.rstmgr_aon
+        MarkAsSkippedOnSystemReset sysbus.pwrmgr_aon
+        MarkAsSkippedOnSystemReset sysbus.flash_ctrl
+
 // CLKMGR_AON        [‘h4042_0000 - ‘h4042_0FFF)   4KB Clock Manger Control
+clock_manager: Miscellaneous.OpenTitan_ClockManager @ sysbus 0x40420000
+    otbn: otbn
+
+// SYSRST            ['h4043_0000 - 'h4043_0FFF]   4KB System Reset Control
+sysrst_ctrl: Miscellaneous.OpenTitan_SystemResetControl @ sysbus 0x40430000
+    resetManager: rstmgr_aon
+    FatalFault -> alert_handler@27
+
 // ADCMGR_AON        [‘h4044_0000 - ‘h4044_0FFF)   4KB ADC
 
 // The OpenTitan bootrom will error out if pinmux registers are locked,
@@ -123,36 +188,139 @@
     value: 0xFFFFFFFF
 
 // AON_TIMER         [‘h4047_0000 - ‘h4047_0FFF)   4KB AON_TIMER
+timer_aon: Timers.OpenTitan_AonTimer @ sysbus 0x40470000
+    powerManager: pwrmgr_aon
+    resetManager: rstmgr_aon
+    FatalAlert -> alert_handler@31
+    WakeupTimerExpired -> plic@155
+    WatchdogTimerBark -> plic@156
+
 // AST               [‘h4048_0000 - ‘h4048_0FFF)   4KB AST
 // SENSOR_CTRL       [‘h4049_0000 - ‘h4049_0FFF)   4KB Sensor Ctrl  (Details need to be added for mic/cam interface)
 // SRAM_CTRL_RET_AON [‘h4050_0000 - ‘h4050_0FFF)   4KB AON RET_SRAM Ctrl
 
 // Simulated SRAM used to indicate test status to simulator
-swteststatus: Miscellaneous.OpenTitan_VerilatorSwTestStatus @ sysbus 0x30000000
+swteststatus: Miscellaneous.OpenTitan_VerilatorSwTestStatus @ sysbus 0x411f0080
 
 // FLASH_CTRL        [‘h4100_0000 - ‘h4100_0FFF)   4KB Flash Control
+flash_ctrl: MTD.OpenTitan_FlashController @ sysbus 0x41000000
+    flash: eflash
+    ProgramEmptyIRQ -> plic@159
+    ProgramLevelIRQ -> plic@160
+    ReadFullIRQ -> plic@161
+    ReadLevelIRQ -> plic@162
+    OperationDoneIRQ -> plic@163
+    CorrectableErrorIRQ -> plic@164
+    RecoverableAlert -> alert_handler@35
+    FatalStandardAlert -> alert_handler@36
+    FatalAlert -> alert_handler@37
+    FatalPrimitiveFlashAlert -> alert_handler@38
+    RecoverablePrimitiveFlashAlert -> alert_handler@39
 
 // RV_PLIC           [‘h4800_0000 - ‘h5000_0000) 128MB RV PLIC
-plic: IRQControllers.PlatformLevelInterruptController @ sysbus 0x48000000
+plic: IRQControllers.OpenTitan_PlatformLevelInterruptController @ sysbus 0x48000000
     // Numbers on the left (0 ->) index PLIC GetGPIOs.
     //
     // Numbers on the right reference bits in the target MIP.
     // Bit 11 corresponds MEIP and bit 9 to SEIP.
     0 -> cpu0@11
+    FatalAlert -> alert_handler@41
     numberOfSources: 190
     numberOfContexts: 1
 
 // AES               [‘h4110_0000 - ‘h4110_0FFF)   4KB AES Control
+aes: Miscellaneous.OpenTitan_AES @ sysbus 0x41100000
+    UpdateErrorAlert -> alert_handler@42
+    FatalFaultAlert -> alert_handler@43
+
 // HMAC              [‘h4111_0000 - ‘h4111_0FFF)   4KB HMAC Control
+hmac: Miscellaneous.OpenTitan_HMAC @ sysbus 0x41110000
+    FatalAlert -> alert_handler@44
+
 // KMAC              [‘h4112_0000 - ‘h4112_0FFF)   4KB KMAC Control
+kmac: Miscellaneous.OpenTitan_KMAC @ sysbus 0x41120000
+    KmacDoneIRQ -> plic@168
+    FifoEmptyIRQ -> plic@169
+    KmacErrorIRQ -> plic@170
+    RecoverableAlert -> alert_handler@45
+    FatalAlert -> alert_handler@46
+
 // OTBN              ['h4113_0000 - 'h4113_FFFF)  64KB OTBN
+otbn: Miscellaneous.OpenTitan_BigNumberAccelerator @ sysbus 0x41130000
+    DoneIRQ -> plic@171
+    FatalAlert -> alert_handler@47
+    RecoverableAlert -> alert_handler@48
+
 // KEYMGR            [‘h4114_0000 - ‘h4114_0FFF)   4KB KEY Manager
+keymgr: Miscellaneous.OpenTitan_KeyManager @ sysbus 0x41140000
+    aes: aes
+    kmac: kmac
+    romController: rom_ctrl
+    deviceId: "BF5EA92044DAC540CFD1A00105568DFA97D9C35EA0407D71320B5E0434DB637F"
+    lifeCycleDiversificationConstant: "2F1A43C03DD4FF9B887AB7521CA6CBD8"
+    creatorKey: "9152E32C9380A4BCC3E0AB263581E6B0E8825186E1E445631646E8BEF8C45D47"
+    ownerKey: "FA365DF52DA48CD752FB3A026A8E608F0098CFE5FA9810494829D0CD9479EB78"
+    rootKey: "EFB7EA7EE90093CF4AFFD9AAA2D6C0EC446CFDF5F2D5A0BFD7E2D93EDC63A10256D24A00181DE99E0F690B447A8DDE2A1FFB8BC306707107AA6E2410F15CFC37"
+    softOutputSeed: "3DAAEF20E285FA658FDD1B426C037151B16C8D444C444F396F4479CB795CF94B"
+    hardOutputSeed: "9E409D18381BD5D56821E2985E47997105C4900F255574675985B210E1A968E4"
+    destinationAesSeed: "5E5B35E460FDAF1FF382AB0195E33689D99BCEBF2B79B6839264EDF4DE2B39F3"
+    destinationKmacSeed: "94059891A38BD1D16C763BBD90347E58152D7FCA9938036525AAA3F89E3DE8F1"
+    destinationOtbnSeed: "278645E11D7CAC76310205E19CD3F2ED294A279F3C6D0649A905CC9B10A67A16"
+    destinationNoneSeed: "7A9E0F6E3D591A7FD8C7BA264AF78F28AEE0D28E4D638D95D1806E870336CD96"
+    revisionSeed: "414C190AD0A09D144FFC0C0FEA081CEF945B641F096B9F3E9A494BA35FCFEF0D"
+    creatorIdentitySeed: "FB223E8AB704F249EE3FA822276C45E588ED40CF52C8FAE2D054A71149771822"
+    ownerIntermediateIdentitySeed: "2EC37360E23D4DDA559ADABCF099937FEBBF048FAC328BA1BDEE0CACA987BE4A"
+    ownerIdentitySeed: "4ABF486B16740B20BC32B13FF07A13FF21CE605E0AC019858F73D707CD0EC1D3"
+    OperationDoneIRQ -> plic@172
+    RecoverableAlert -> alert_handler@49
+    FatalAlert -> alert_handler@50
+
 // CSRNG             [‘h4115_0000 - ‘h4115_0FFF)   4KB CSRNG  (Cryptographically Secure Random Number Generator) Control
+csrng: Miscellaneous.OpenTitan_CSRNG @ sysbus 0x41150000
+    entropySource: entropy_src
+    RequestCompletedIRQ -> plic@173
+    EntropyeRequestedIRQ -> plic@174
+    HardwareInstanceIRQ -> plic@175
+    FatalErrorIRQ -> plic@176
+    RecoverableAlert -> alert_handler@51
+    FatalAlert -> alert_handler@52
+
 // ENTROPY_SRC       [‘h4116_0000 - ‘h4116_0FFF)   4KB ENTROPY SRC control
+entropy_src: Miscellaneous.OpenTitan_EntropySource @ sysbus 0x41160000
+    RecoverableAlert -> alert_handler@53
+    FatalAlert -> alert_handler@54
+    EsEntropyValidIRQ -> plic@177
+    EsHealthTestFailedIRQ -> plic@178
+    EsObserveFifoReadyIRQ -> plic@179
+    EsFatalErrIRQ -> plic@180
+
 // EDN0              [‘h4117_0000 - ‘h4117_0FFF)   4KB EDN0
+edn0: Miscellaneous.OpenTitan_EntropyDistributionNetwork @ sysbus 0x41170000
+    cryptoRandomGenerator: csrng
+    RecoverableAlert -> alert_handler@55
+    FatalAlert -> alert_handler@56
+    CommandRequestDone -> plic@181
+    FatalError -> plic@182
+
 // EDN1              [‘h4118_0000 - ‘h4118_0FFF)   4KB EDN1
+edn1: Miscellaneous.OpenTitan_EntropyDistributionNetwork @ sysbus 0x41180000
+    cryptoRandomGenerator: csrng
+    RecoverableAlert -> alert_handler@57
+    FatalAlert -> alert_handler@58
+    CommandRequestDone -> plic@183
+    FatalError -> plic@184
+
 // SRAM_CTRL_MAIN    [‘h411C_0000 - ‘h411C_0FFF)   4KB SRAM Control
+sram_ctrl: MemoryControllers.OpenTitan_SRAMController @ sysbus 0x411c0000
+    FatalError -> alert_handler@59
+
 // ROM_CTRL          [‘h411E_0000 - ‘h411E_0FFF)   4KB ROM Control
+rom_ctrl: MemoryControllers.OpenTitan_ROMController @ sysbus 0x411e0000
+    rom: rom
+    nonce: "D7C90B2B3C3EF8B3"
+    key: "80C4E835FB113AAD6D7DCA2F2C7D9BF2"
+    FatalAlert -> alert_handler@60
+
 // RV_CORE_IBEX      [‘h411F_0000 - ‘h411F_0FFF)   4KB RV Core Ibex
 
 // Flash/MRAM        [‘h4400_0000 - ‘h44FF_FFFF)  16MB External Non-Volatile Memory
diff --git a/platforms/smc.repl b/platforms/smc.repl
index 805e070..e28f711 100644
--- a/platforms/smc.repl
+++ b/platforms/smc.repl
@@ -59,13 +59,13 @@
 
 // RV_TIMER_SMC, timer for Cantrip kernel.
 // TODO(hcindyl): Use upstream OpenTitan_Timer model
-timer_smc: Timers.OpenTitan2_Timer@ sysbus 0x50010000
+timer_smc: Timers.OpenTitan_Timer@ sysbus 0x50010000
     frequency: 24000000
     IRQ -> cpu1@5
 
 // Timer for Cantrip software timer service.
 // TODO(hcindyl): Use upstream OpenTitan_Timer model
-timer_smc_sw: Timers.OpenTitan2_Timer@ sysbus 0x50030000
+timer_smc_sw: Timers.OpenTitan_Timer@ sysbus 0x50030000
     frequency: 24000000
     IRQ -> smc_plic@31
 
diff --git a/shodan.resc b/shodan.resc
index 879994c..a619c7b 100644
--- a/shodan.resc
+++ b/shodan.resc
@@ -10,7 +10,6 @@
 EnsureTypeIsLoaded "Antmicro.Renode.Peripherals.CPU.SpringbokRiscV32"
 EnsureTypeIsLoaded "Antmicro.Renode.Peripherals.CPU.SpringbokRiscV32_ControlBlock"
 include @sim/config/shodan_infrastructure/SmcRiscV32.cs
-include @sim/config/shodan_infrastructure/OpenTitan2_Timer.cs
 include @sim/config/shodan_infrastructure/Mailbox.cs
 include @sim/renode/tools/sel4_extensions/seL4Extensions.cs
 include @sim/config/shodan_infrastructure/AddressRangeStub.cs
diff --git a/shodan_infrastructure/OpenTitan2_Timer.cs b/shodan_infrastructure/OpenTitan2_Timer.cs
deleted file mode 100644
index ac43796..0000000
--- a/shodan_infrastructure/OpenTitan2_Timer.cs
+++ /dev/null
@@ -1,169 +0,0 @@
-//
-// Copyright (c) 2010-2023 Antmicro
-// Copyright (c) 2021 Google LLC
-//
-// This file is licensed under the MIT License.
-// Full license text is available in 'licenses/MIT.txt'.
-//
-using Antmicro.Renode.Core;
-using Antmicro.Renode.Core.Structure.Registers;
-using Antmicro.Renode.Peripherals.Bus;
-
-namespace Antmicro.Renode.Peripherals.Timers
-{
-    // OpenTitan rv_timer has a configurable number of timers and harts/Harts, but this implementation is limited to 1 hart and 1 timer.
-    // It is compliant with the v1.11 RISC-V privilege specification.
-    // The counters are all 64-bit and each timer has a configurable prescaler and step.
-    [AllowedTranslations(AllowedTranslation.ByteToDoubleWord)]
-    public class OpenTitan2_Timer : BasicDoubleWordPeripheral, IKnownSize, IRiscVTimeProvider
-    {
-        public OpenTitan2_Timer(Machine machine, long frequency = 24000000) : base(machine)
-        {
-            IRQ = new GPIO();
-            FatalAlert = new GPIO();
-            underlyingTimer = new ComparingTimer(machine.ClockSource, frequency, this, "timer", workMode: Time.WorkMode.Periodic, eventEnabled: true);
-
-            underlyingTimer.CompareReached += UpdateInterrupts;
-
-            DefineRegisters();
-        }
-
-        public override void Reset()
-        {
-            base.Reset();
-            FatalAlert.Unset();
-
-            underlyingTimer.Reset();
-            UpdateInterrupts();
-        }
-
-        public long Size => 0x120;
-
-        public ulong TimerValue => underlyingTimer.Value;
-
-        public GPIO IRQ { get; }
-        public GPIO FatalAlert { get; }
-
-        private void DefineRegisters()
-        {
-            Registers.AlertTest.Define(this, 0x0)
-                .WithFlag(0, FieldMode.Write, writeCallback: (_, val) => { if(val) FatalAlert.Blink(); }, name: "fatal_fault")
-                .WithReservedBits(1, 31);
-
-            Registers.Control0.Define(this)
-                .WithFlag(0, name: "CONTROL0", writeCallback: (_, val) =>
-                {
-                    underlyingTimer.Enabled = val;
-                    UpdateInterrupts();
-                })
-                .WithReservedBits(1, 31)
-            ;
-
-            Registers.CompareLowHart0.Define(this, 0xFFFFFFFF)
-                 .WithValueField(0, 32, name: "COMPARELOW",
-                    valueProviderCallback: _ => (uint)(underlyingTimer.Compare),
-                    writeCallback: (_, val) =>
-                    {
-                        underlyingTimer.Compare = (underlyingTimer.Compare & 0xFFFFFFFF00000000uL) | val;
-                        UpdateInterrupts();
-                    })
-            ;
-
-            Registers.CompareHighHart0.Define(this, 0xFFFFFFFF)
-                 .WithValueField(0, 32, name: "COMPAREHI",
-                    valueProviderCallback: _ => (uint)(underlyingTimer.Compare >> 32),
-                    writeCallback: (_, val) =>
-                    {
-                        underlyingTimer.Compare = (underlyingTimer.Compare & 0x00000000FFFFFFFFuL) | (((ulong)val) << 32);
-                        UpdateInterrupts();
-                    })
-            ;
-
-            Registers.ConfigurationHart0.Define(this, 0x10000)
-                .WithValueField(0, 12, out prescaler, name: "PRESCALE")
-                .WithValueField(16, 8, out step, name: "STEP")
-                .WithWriteCallback((_, __) => TimerUpdateConfiguration())
-                .WithReservedBits(24, 8)
-            ;
-
-            Registers.ValueLowHart0.Define(this)
-                .WithValueField(0, 32, name: "VALUELOW",
-                    valueProviderCallback: _ => (uint)(underlyingTimer.Value),
-                    writeCallback: (_, val) =>
-                    {
-                        underlyingTimer.Value = (underlyingTimer.Value & 0xFFFFFFFF00000000uL) | val;
-                        UpdateInterrupts();
-                    })
-            ;
-
-            Registers.ValueHighHart0.Define(this)
-                .WithValueField(0, 32, name: "VALUEHI",
-                    valueProviderCallback: _ => (uint)(underlyingTimer.Value >> 32),
-                    writeCallback: (_, val) =>
-                    {
-                        underlyingTimer.Value = (underlyingTimer.Value & 0x00000000FFFFFFFFuL) | (((ulong)val) << 32);
-                        UpdateInterrupts();
-                    })
-            ;
-
-            Registers.InterruptEnableHart0.Define(this)
-                .WithFlag(0, out interruptEnabled, name: "IE")
-                .WithReservedBits(1, 31)
-                .WithWriteCallback((_, __) => UpdateInterrupts())
-            ;
-
-            Registers.InterruptStatusHart0.Define(this)
-                .WithFlag(0, FieldMode.Read, name: "IS", valueProviderCallback: _ => IRQ.IsSet)
-                .WithReservedBits(1, 31)
-                .WithWriteCallback((_, __) => UpdateInterrupts())
-            ;
-
-            Registers.InterruptTestHart0.Define(this)
-                .WithFlag(0, FieldMode.Write, name: "T",
-                    writeCallback: (_, newValue) =>
-                    {
-                        if(newValue)
-                        {
-                            IRQ.Set(true);
-                        }
-                    }
-                )
-            ;
-        }
-
-        private void TimerUpdateConfiguration()
-        {
-            var divider = (uint)(prescaler.Value + 1u);
-            underlyingTimer.Divider = (divider == 0) ? 1 : divider;
-            underlyingTimer.Step = (uint)step.Value;
-        }
-
-        private void UpdateInterrupts()
-        {
-            IRQ.Set(
-                underlyingTimer.Enabled
-                && interruptEnabled.Value
-                && (underlyingTimer.Value >= underlyingTimer.Compare));
-        }
-
-        private IFlagRegisterField interruptEnabled;
-        private IValueRegisterField prescaler;
-        private IValueRegisterField step;
-
-        private readonly ComparingTimer underlyingTimer;
-
-        private enum Registers
-        {
-            AlertTest = 0x0,
-            Control0 = 0x4,
-            ConfigurationHart0 = 0x10c,
-            ValueLowHart0 = 0x110,
-            ValueHighHart0 = 0x114,
-            CompareLowHart0 = 0x118,
-            CompareHighHart0 = 0x11c,
-            InterruptEnableHart0 = 0x100,
-            InterruptStatusHart0 = 0x104,
-            InterruptTestHart0 = 0x108
-        }
-    }
-}