diff --git a/bancha.resc b/bancha.resc
index 8eebc96..c8c4255 100644
--- a/bancha.resc
+++ b/bancha.resc
@@ -53,6 +53,15 @@
 $cheriotLibrary ?= @out/cheriot/sim/librenode_mpact_cheriot.so
 sysbus.cpu0 CpuLibraryPath $cheriotLibrary
 
+# Configure an I$ and a D$.
+# Each configuration is a string of the form:
+#   "size,block_size,associativity,write_allocate"
+# for instance "8k,16,2,false".
+# NB: Statistics are collected only when MemProfile is enabled (see below).
+#sysbus.cpu0 ICache "8k,16,2,false"
+# NB: D$ can be configured but is not implemented yet
+#sysbus.cpu0 DCache "1k,8,1,false"
+
 # Load the boot rom into the 32k rom at 0x8000 (useVirtualAddress = false, allowLoadsOnlyToMemory = false)
 # Unlike the OT boot rom where cpu0 starts at the reset vecitor (@0x8080)
 # the PC is initialized to the ELF entry point.