Add zicsr extension to cpu0/cpu1
- On today's nightly of Renode, we get warning about not having zicsr
extension explicitly enabled.
Change-Id: Icadf0b2c8bda74a8e413993f7b28cc17df06e306
diff --git a/platforms/secure.repl b/platforms/secure.repl
index 108b403..e180afb 100644
--- a/platforms/secure.repl
+++ b/platforms/secure.repl
@@ -4,7 +4,7 @@
cpu0: CPU.IbexRiscV32 @ sysbus
hartId: 0
- cpuType: "rv32imac"
+ cpuType: "rv32imac_zicsr_zifencei"
allowUnalignedAccesses: true
// ORDER EVERY DEVICE BY ADDRESS FOR SANITY
diff --git a/platforms/smc.repl b/platforms/smc.repl
index c9835f9..7095cef 100644
--- a/platforms/smc.repl
+++ b/platforms/smc.repl
@@ -20,7 +20,7 @@
// because it has been Shodan-specific since its initial revision.
cpu1: CPU.RiscV32 @ sysbus
hartId: 1
- cpuType: "rv32imac"
+ cpuType: "rv32imac_zicsr_zifencei"
timeProvider: timer_smc
allowUnalignedAccesses: true
diff --git a/shodan_infrastructure/SpringbokRiscV32.cs b/shodan_infrastructure/SpringbokRiscV32.cs
index 71515a4..2deebde 100644
--- a/shodan_infrastructure/SpringbokRiscV32.cs
+++ b/shodan_infrastructure/SpringbokRiscV32.cs
@@ -27,7 +27,7 @@
uint hartId = 0,
PrivilegeArchitecture privilegeArchitecture = PrivilegeArchitecture.Priv1_11,
Endianess endianness = Endianess.LittleEndian,
- string cpuType = "rv32imfv")
+ string cpuType = "rv32imfv_zicsr")
: base(null, cpuType, machine, hartId, privilegeArchitecture, endianness)
{
RegisterCustomCSRs();
