doc/getting_started/setup_dv.md

## Design Verification Setup in matcha
*Revision 1.1*



### DV Methodology

[Design Verification Methodology in Opentitan](https://docs.opentitan.org/doc/ug/dv_methodology/) has been followed in matcha.

Currently, [VCS](https://www.synopsys.com/verification/simulation/vcs.html) is used as the major simulator for running DV tests in matcha. 

### DV Settings

At the root of shodan repo:

```
export ROOTDIR=`pwd`
export proj_root=$ROOTDir/hw/matcha
export titan_root=$ROOTDIR/hw/opentitan-upstream
export PYTHONPATH=$ROOTDIR/hw/matcha/util:$titan_root/util:$titan_root/util/dvsim:$PYTHONPATH
```


### Run DV tests

```
cd $ROOTDIR/hw/matcha
util/dvsim_match/dvsim.py \
    hw/top_matcha/dv/chip_sim_cfg.hjson \
    -i <test_name>
```

### Generate Debug Messages
Use `-v` option to dump out the debug messages from the simulation. For example:
```
util/dvsim_match/dvsim.py \
    hw/top_matcha/dv/chip_sim_cfg.hjson \
    -i <test_name>
    -v d
```

### Generate Waveform

To dump waveforms from the simulation, use the `-w` or `--waves` option to pass the argument to dvsim.py. For example:
```
util/dvsim_match/dvsim.py \
    hw/top_matcha/dv/chip_sim_cfg.hjson \
    -i <test_name> \
    -w fsdb
```


### Debug with Verdi

To debug with Verdi:

  1. Generate the waveform
  2. Invoke Verdi with the following command:
  ```
    cd ${proj_root}/scratch/<branch>/chip_matcha_asic-sim-vcs/default
  	verdi -dbdir ./simv.daidir
  ```
  3. Load the waveform (fsdb, vcd, etc)
  4. Trace the signals with Verdi


### Run DV tests with bazel in air-gapped environment

[Sparrow HW DV Notes](https://docs.google.com/document/d/10LiU3v8PBc06KkpTVaceIhJqqcdVIvO2GzFaJh7x_bY/edit) describes how to set up the bazel runs on EDACloud.

In an air-gapped environment like EDACloud, DV tests can be invoked from hw/matcha with bazel. Here is the sample bazel command:
```
bazel run //util/dvsim_matcha:dvsim.py \
          --distdir=`pwd` \
          -- hw/top_matcha/dv/chip_sim_cfg.hjson \
          -i chip_sw_uart_tx_rx
```



### Notes
#### Known issues
1. To turn off all the assertions in simulation, add the following lines in tb.sv:
  ```
  initial
  begin
    $assertoff(0, tb.dut);
  end
  ```