doc/getting_started/setup_dv.md

## Design Verification Setup in matcha



### DV Methodology

[Design Verification Methodology in Opentitan](https://docs.opentitan.org/doc/ug/dv_methodology/) has been followed in matcha.

Currently, [VCS](https://www.synopsys.com/verification/simulation/vcs.html) is used as the major simulator for running DV tests in matcha. 

### DV Settings

At the root of shodan repo:

```
export ROOTDIR=`pwd`
export titan_root=$ROOTDIR/hw/opentitan-upstream
export PYTHONPATH=$ROOTDIR/hw/matcha/util:$titan_root/util:$titan_root/util/dvsim:$PYTHONPATH
```


### Run DV tests

```
cd $ROOTDIR/hw/matcha
util/dvsim_match/dvsim.py hw/top_matcha/dv/chip_sim_cfg.hjson -i <test_name>
```


### Generate Waveform

To dump waveforms from the simulation, pass the `--waves` argument to dvsim.py


### Debug with Verdi

To debug with Verdi:

  1. Generate kdb of the current design with `-kdb[=only]` option in VCS runs
  2. Invoke Verdi with the following command:
  ```
  	verdi -dbdir=<path to simv.daidir>
  ```
  3. Load the waveform (fsdb, vcd, etc)
  4. Trace the signals with Verdi

### Notes
#### Known issues
1. To turn off all the assertions in simulation, add the following lines in tb.sv:
  ```
  initial
  begin
    $assertoff(0, tb.dut);
  end
  ```
2. Add the following lines:
  ```
  `define STOP_COND 0
  `define PRINTF_COND 0
  ```
  at the top of the files:
  ```
  hw/top_matcha/ip/ml_top/rtl/kelvin.v
  hw/top_matcha/ip/ml_top/rtl/xbar_sram.v
  ```
  to turn off the $fatal statements and the unwanted debug messages

3. Comment out lines 204-207 in
  ```
  hw/top_matcha/ip/smc/rtl/smc_controller.sv
  ```
  to avoid the unnecessary error messages