| // Copyright 2022 Google LLC. |
| // Licensed under the Apache License, Version 2.0, see LICENSE for details. |
| // SPDX-License-Identifier: Apache-2.0 |
| |
| // UVM Registers auto-generated by `reggen` containing data structure |
| package ml_top_core_ral_pkg; |
| // dep packages |
| import uvm_pkg::*; |
| import dv_base_reg_pkg::*; |
| |
| // macro includes |
| `include "uvm_macros.svh" |
| |
| // Forward declare all register/memory/block classes |
| typedef class ml_top_core_reg_ctrl; |
| typedef class ml_top_core_reg_memory_bank_ctrl; |
| typedef class ml_top_core_reg_error_status; |
| typedef class ml_top_core_reg_init_start; |
| typedef class ml_top_core_reg_init_end; |
| typedef class ml_top_core_reg_init_status; |
| typedef class ml_top_core_reg_block; |
| |
| class ml_top_core_reg_ctrl extends dv_base_reg; |
| // fields |
| rand dv_base_reg_field freeze; |
| rand dv_base_reg_field ml_reset; |
| rand dv_base_reg_field pc_start; |
| |
| `uvm_object_utils(ml_top_core_reg_ctrl) |
| |
| function new(string name = "ml_top_core_reg_ctrl", |
| int unsigned n_bits = 32, |
| int has_coverage = UVM_NO_COVERAGE); |
| super.new(name, n_bits, has_coverage); |
| endfunction : new |
| |
| virtual function void build(csr_excl_item csr_excl = null); |
| // create fields |
| freeze = (dv_base_reg_field:: |
| type_id::create("freeze")); |
| freeze.configure( |
| .parent(this), |
| .size(1), |
| .lsb_pos(0), |
| .access("RW"), |
| .volatile(0), |
| .reset(32'h0), |
| .has_reset(1), |
| .is_rand(1), |
| .individually_accessible(1)); |
| |
| freeze.set_original_access("RW"); |
| |
| ml_reset = (dv_base_reg_field:: |
| type_id::create("ml_reset")); |
| ml_reset.configure( |
| .parent(this), |
| .size(1), |
| .lsb_pos(1), |
| .access("RW"), |
| .volatile(0), |
| .reset(32'h0), |
| .has_reset(1), |
| .is_rand(1), |
| .individually_accessible(1)); |
| |
| ml_reset.set_original_access("RW"); |
| |
| pc_start = (dv_base_reg_field:: |
| type_id::create("pc_start")); |
| pc_start.configure( |
| .parent(this), |
| .size(17), |
| .lsb_pos(2), |
| .access("RW"), |
| .volatile(0), |
| .reset(32'h0), |
| .has_reset(1), |
| .is_rand(1), |
| .individually_accessible(1)); |
| |
| pc_start.set_original_access("RW"); |
| |
| endfunction : build |
| endclass : ml_top_core_reg_ctrl |
| |
| class ml_top_core_reg_memory_bank_ctrl extends dv_base_reg; |
| // fields |
| rand dv_base_reg_field d_mem_enable; |
| |
| `uvm_object_utils(ml_top_core_reg_memory_bank_ctrl) |
| |
| function new(string name = "ml_top_core_reg_memory_bank_ctrl", |
| int unsigned n_bits = 32, |
| int has_coverage = UVM_NO_COVERAGE); |
| super.new(name, n_bits, has_coverage); |
| endfunction : new |
| |
| virtual function void build(csr_excl_item csr_excl = null); |
| d_mem_enable = (dv_base_reg_field:: |
| type_id::create("d_mem_enable")); |
| d_mem_enable.configure( |
| .parent(this), |
| .size(7), |
| .lsb_pos(0), |
| .access("RO"), |
| .volatile(0), |
| .reset(32'hff), |
| .has_reset(1), |
| .is_rand(1), |
| .individually_accessible(1)); |
| |
| d_mem_enable.set_original_access("RO"); |
| |
| endfunction : build |
| endclass : ml_top_core_reg_memory_bank_ctrl |
| |
| class ml_top_core_reg_error_status extends dv_base_reg; |
| // fields |
| rand dv_base_reg_field i_mem_out_of_range; |
| rand dv_base_reg_field d_mem_out_of_range; |
| rand dv_base_reg_field i_mem_disable_access; |
| rand dv_base_reg_field d_mem_disable_access; |
| |
| `uvm_object_utils(ml_top_core_reg_error_status) |
| |
| function new(string name = "ml_top_core_reg_error_status", |
| int unsigned n_bits = 32, |
| int has_coverage = UVM_NO_COVERAGE); |
| super.new(name, n_bits, has_coverage); |
| endfunction : new |
| |
| virtual function void build(csr_excl_item csr_excl = null); |
| // create fields |
| i_mem_out_of_range = (dv_base_reg_field:: |
| type_id::create("i_mem_out_of_range")); |
| i_mem_out_of_range.configure( |
| .parent(this), |
| .size(1), |
| .lsb_pos(0), |
| .access("RC"), |
| .volatile(1), |
| .reset(32'h0), |
| .has_reset(1), |
| .is_rand(1), |
| .individually_accessible(1)); |
| |
| i_mem_out_of_range.set_original_access("RC"); |
| |
| d_mem_out_of_range = (dv_base_reg_field:: |
| type_id::create("d_mem_out_of_range")); |
| d_mem_out_of_range.configure( |
| .parent(this), |
| .size(1), |
| .lsb_pos(1), |
| .access("RC"), |
| .volatile(1), |
| .reset(32'h0), |
| .has_reset(1), |
| .is_rand(1), |
| .individually_accessible(1)); |
| |
| d_mem_out_of_range.set_original_access("RC"); |
| |
| i_mem_disable_access = (dv_base_reg_field:: |
| type_id::create("i_mem_disable_access")); |
| i_mem_disable_access.configure( |
| .parent(this), |
| .size(4), |
| .lsb_pos(2), |
| .access("RC"), |
| .volatile(1), |
| .reset(32'h0), |
| .has_reset(1), |
| .is_rand(1), |
| .individually_accessible(1)); |
| |
| i_mem_disable_access.set_original_access("RC"); |
| |
| d_mem_disable_access = (dv_base_reg_field:: |
| type_id::create("d_mem_disable_access")); |
| d_mem_disable_access.configure( |
| .parent(this), |
| .size(8), |
| .lsb_pos(6), |
| .access("RC"), |
| .volatile(1), |
| .reset(32'h0), |
| .has_reset(1), |
| .is_rand(1), |
| .individually_accessible(1)); |
| |
| d_mem_disable_access.set_original_access("RC"); |
| |
| endfunction : build |
| endclass : ml_top_core_reg_error_status |
| |
| class ml_top_core_reg_init_start extends dv_base_reg; |
| // fields |
| rand dv_base_reg_field address; |
| rand dv_base_reg_field dmem_sel; |
| |
| `uvm_object_utils(ml_top_core_reg_init_start) |
| |
| function new(string name = "ml_top_core_reg_init_start", |
| int unsigned n_bits = 32, |
| int has_coverage = UVM_NO_COVERAGE); |
| super.new(name, n_bits, has_coverage); |
| endfunction : new |
| |
| virtual function void build(csr_excl_item csr_excl = null); |
| // create fields |
| address = (dv_base_reg_field:: |
| type_id::create("address")); |
| address.configure( |
| .parent(this), |
| .size(22), |
| .lsb_pos(0), |
| .access("RW"), |
| .volatile(0), |
| .reset(32'h0), |
| .has_reset(1), |
| .is_rand(1), |
| .individually_accessible(1)); |
| |
| address.set_original_access("RW"); |
| |
| dmem_sel = (dv_base_reg_field:: |
| type_id::create("dmem_sel")); |
| dmem_sel.configure( |
| .parent(this), |
| .size(1), |
| .lsb_pos(22), |
| .access("RW"), |
| .volatile(0), |
| .reset(32'h0), |
| .has_reset(1), |
| .is_rand(1), |
| .individually_accessible(1)); |
| |
| dmem_sel.set_original_access("RW"); |
| |
| endfunction : build |
| endclass : ml_top_core_reg_init_start |
| |
| class ml_top_core_reg_init_end extends dv_base_reg; |
| // fields |
| rand dv_base_reg_field address; |
| rand dv_base_reg_field valid; |
| |
| `uvm_object_utils(ml_top_core_reg_init_end) |
| |
| function new(string name = "ml_top_core_reg_init_end", |
| int unsigned n_bits = 32, |
| int has_coverage = UVM_NO_COVERAGE); |
| super.new(name, n_bits, has_coverage); |
| endfunction : new |
| |
| virtual function void build(csr_excl_item csr_excl = null); |
| // create fields |
| address = (dv_base_reg_field:: |
| type_id::create("address")); |
| address.configure( |
| .parent(this), |
| .size(22), |
| .lsb_pos(0), |
| .access("RW"), |
| .volatile(1), |
| .reset(32'h0), |
| .has_reset(1), |
| .is_rand(1), |
| .individually_accessible(1)); |
| |
| address.set_original_access("RW"); |
| |
| valid = (dv_base_reg_field:: |
| type_id::create("valid")); |
| valid.configure( |
| .parent(this), |
| .size(1), |
| .lsb_pos(22), |
| .access("RW"), |
| .volatile(1), |
| .reset(32'h0), |
| .has_reset(1), |
| .is_rand(1), |
| .individually_accessible(1)); |
| |
| valid.set_original_access("RW"); |
| |
| endfunction : build |
| endclass : ml_top_core_reg_init_end |
| |
| class ml_top_core_reg_init_status extends dv_base_reg; |
| // fields |
| rand dv_base_reg_field init_pending; |
| rand dv_base_reg_field init_done; |
| |
| `uvm_object_utils(ml_top_core_reg_init_status) |
| |
| function new(string name = "ml_top_core_reg_init_status", |
| int unsigned n_bits = 32, |
| int has_coverage = UVM_NO_COVERAGE); |
| super.new(name, n_bits, has_coverage); |
| endfunction : new |
| |
| virtual function void build(csr_excl_item csr_excl = null); |
| // create fields |
| init_pending = (dv_base_reg_field:: |
| type_id::create("init_pending")); |
| init_pending.configure( |
| .parent(this), |
| .size(1), |
| .lsb_pos(0), |
| .access("RO"), |
| .volatile(1), |
| .reset(32'h0), |
| .has_reset(1), |
| .is_rand(1), |
| .individually_accessible(1)); |
| |
| init_pending.set_original_access("RO"); |
| |
| init_done = (dv_base_reg_field:: |
| type_id::create("init_done")); |
| init_done.configure( |
| .parent(this), |
| .size(1), |
| .lsb_pos(1), |
| .access("RC"), |
| .volatile(1), |
| .reset(32'h0), |
| .has_reset(1), |
| .is_rand(1), |
| .individually_accessible(1)); |
| |
| init_done.set_original_access("RC"); |
| |
| endfunction : build |
| endclass : ml_top_core_reg_init_status |
| |
| class ml_top_core_reg_block extends dv_base_reg_block; |
| // registers |
| rand ml_top_core_reg_ctrl ctrl; |
| rand ml_top_core_reg_memory_bank_ctrl memory_bank_ctrl; |
| rand ml_top_core_reg_error_status error_status; |
| rand ml_top_core_reg_init_start init_start; |
| rand ml_top_core_reg_init_end init_end; |
| rand ml_top_core_reg_init_status init_status; |
| |
| `uvm_object_utils(ml_top_core_reg_block) |
| |
| function new(string name = "ml_top_core_reg_block", |
| int has_coverage = UVM_NO_COVERAGE); |
| super.new(name, has_coverage); |
| endfunction : new |
| |
| virtual function void build(uvm_reg_addr_t base_addr, |
| csr_excl_item csr_excl = null); |
| // create default map |
| this.default_map = create_map(.name("default_map"), |
| .base_addr(base_addr), |
| .n_bytes(4), |
| .endian(UVM_LITTLE_ENDIAN)); |
| if (csr_excl == null) begin |
| csr_excl = csr_excl_item::type_id::create("csr_excl"); |
| this.csr_excl = csr_excl; |
| end |
| set_hdl_path_root("tb.dut", "BkdrRegPathRtl"); |
| set_hdl_path_root("tb.dut", "BkdrRegPathRtlCommitted"); |
| set_hdl_path_root("tb.dut", "BkdrRegPathRtlShadow"); |
| // create registers |
| ctrl = (ml_top_core_reg_ctrl:: |
| type_id::create("ctrl")); |
| ctrl.configure(.blk_parent(this)); |
| ctrl.build(csr_excl); |
| default_map.add_reg(.rg(ctrl), |
| .offset(32'h0)); |
| ctrl.add_hdl_path_slice( |
| "u_reg_csr.u_ctrl_freeze.q", |
| 0, 1, 0, "BkdrRegPathRtl"); |
| ctrl.add_hdl_path_slice( |
| "u_reg_csr.u_ctrl_ml_reset.q", |
| 1, 1, 0, "BkdrRegPathRtl"); |
| ctrl.add_hdl_path_slice( |
| "u_reg_csr.u_ctrl_pc_start.q", |
| 2, 17, 0, "BkdrRegPathRtl"); |
| |
| memory_bank_ctrl = (ml_top_core_reg_memory_bank_ctrl:: |
| type_id::create("memory_bank_ctrl")); |
| memory_bank_ctrl.configure(.blk_parent(this)); |
| memory_bank_ctrl.build(csr_excl); |
| default_map.add_reg(.rg(memory_bank_ctrl), |
| .offset(32'h4)); |
| memory_bank_ctrl.add_hdl_path_slice( |
| "u_reg_csr.u_memory_bank_ctrl_d_mem_enable.q", |
| 0, 7, 0, "BkdrRegPathRtl"); |
| |
| error_status = (ml_top_core_reg_error_status:: |
| type_id::create("error_status")); |
| error_status.configure(.blk_parent(this)); |
| error_status.build(csr_excl); |
| default_map.add_reg(.rg(error_status), |
| .offset(32'h8)); |
| error_status.add_hdl_path_slice( |
| "u_reg_csr.u_error_status_i_mem_out_of_range.q", |
| 0, 1, 0, "BkdrRegPathRtl"); |
| error_status.add_hdl_path_slice( |
| "u_reg_csr.u_error_status_d_mem_out_of_range.q", |
| 1, 1, 0, "BkdrRegPathRtl"); |
| error_status.add_hdl_path_slice( |
| "u_reg_csr.u_error_status_i_mem_disable_access.q", |
| 2, 4, 0, "BkdrRegPathRtl"); |
| error_status.add_hdl_path_slice( |
| "u_reg_csr.u_error_status_d_mem_disable_access.q", |
| 6, 8, 0, "BkdrRegPathRtl"); |
| |
| init_start = (ml_top_core_reg_init_start:: |
| type_id::create("init_start")); |
| init_start.configure(.blk_parent(this)); |
| init_start.build(csr_excl); |
| default_map.add_reg(.rg(init_start), |
| .offset(32'hc)); |
| init_start.add_hdl_path_slice( |
| "u_reg_csr.u_init_start_address.q", |
| 0, 22, 0, "BkdrRegPathRtl"); |
| init_start.add_hdl_path_slice( |
| "u_reg_csr.u_init_start_dmem_sel.q", |
| 22, 1, 0, "BkdrRegPathRtl"); |
| |
| init_end = (ml_top_core_reg_init_end:: |
| type_id::create("init_end")); |
| init_end.configure(.blk_parent(this)); |
| init_end.build(csr_excl); |
| default_map.add_reg(.rg(init_end), |
| .offset(32'h10)); |
| init_end.add_hdl_path_slice( |
| "u_reg_csr.u_init_end_address.q", |
| 0, 22, 0, "BkdrRegPathRtl"); |
| init_end.add_hdl_path_slice( |
| "u_reg_csr.u_init_end_valid.q", |
| 22, 1, 0, "BkdrRegPathRtl"); |
| |
| init_status = (ml_top_core_reg_init_status:: |
| type_id::create("init_status")); |
| init_status.configure(.blk_parent(this)); |
| init_status.build(csr_excl); |
| default_map.add_reg(.rg(init_status), |
| .offset(32'h14)); |
| init_status.add_hdl_path_slice( |
| "u_reg_csr.u_init_status_init_pending.q", |
| 0, 1, 0, "BkdrRegPathRtl"); |
| init_status.add_hdl_path_slice( |
| "u_reg_csr.u_init_status_init_done.q", |
| 1, 1, 0, "BkdrRegPathRtl"); |
| |
| |
| endfunction : build |
| endclass : ml_top_core_reg_block |
| |
| endpackage |
| |
