[ml_top] Remove data fault intr completely
Change-Id: Ib70d40db7ad3dc616d043f7bf5d84a0f0642e3d1
diff --git a/hw/top_matcha/ip/ml_top/data/ml_top.hjson b/hw/top_matcha/ip/ml_top/data/ml_top.hjson
index 8061135..6d2bdc6 100644
--- a/hw/top_matcha/ip/ml_top/data/ml_top.hjson
+++ b/hw/top_matcha/ip/ml_top/data/ml_top.hjson
@@ -31,10 +31,6 @@
name: "fault"
desc: "raised if kelvin report fault."
}
- {
- name: "data_fault"
- desc: "raised if windowMMU data memory access faults(reserved)"
- }
],
inter_signal_list: [
diff --git a/hw/top_matcha/ip/ml_top/rtl/ml_top.sv b/hw/top_matcha/ip/ml_top/rtl/ml_top.sv
index 70e3b89..3900a48 100644
--- a/hw/top_matcha/ip/ml_top/rtl/ml_top.sv
+++ b/hw/top_matcha/ip/ml_top/rtl/ml_top.sv
@@ -39,8 +39,7 @@
// Interrupts
output logic intr_host_req_o,
output logic intr_finish_o,
- output logic intr_fault_o,
- output logic intr_data_fault_o
+ output logic intr_fault_o
);
@@ -188,9 +187,6 @@
assign event_finish = core0_finish;
assign event_fault = core0_fault;
- // TODO: Reserved for WinMMU faults. Hardwired to low as placeholder for now.
- assign intr_data_fault_o = 1'b0;
-
// Host Request interrupt
prim_intr_hw #(.Width(1)) intr_host_req (
.clk_i,
diff --git a/hw/top_matcha/ip/ml_top/rtl/ml_top_core_reg_top.sv b/hw/top_matcha/ip/ml_top/rtl/ml_top_core_reg_top.sv
index 81818e1..2f2e3de 100644
--- a/hw/top_matcha/ip/ml_top/rtl/ml_top_core_reg_top.sv
+++ b/hw/top_matcha/ip/ml_top/rtl/ml_top_core_reg_top.sv
@@ -131,8 +131,6 @@
logic intr_state_finish_wd;
logic intr_state_fault_qs;
logic intr_state_fault_wd;
- logic intr_state_data_fault_qs;
- logic intr_state_data_fault_wd;
logic intr_enable_we;
logic intr_enable_host_req_qs;
logic intr_enable_host_req_wd;
@@ -140,13 +138,10 @@
logic intr_enable_finish_wd;
logic intr_enable_fault_qs;
logic intr_enable_fault_wd;
- logic intr_enable_data_fault_qs;
- logic intr_enable_data_fault_wd;
logic intr_test_we;
logic intr_test_host_req_wd;
logic intr_test_finish_wd;
logic intr_test_fault_wd;
- logic intr_test_data_fault_wd;
logic ctrl_we;
logic ctrl_freeze_qs;
logic ctrl_freeze_wd;
@@ -259,32 +254,6 @@
.qs (intr_state_fault_qs)
);
- // F[data_fault]: 3:3
- prim_subreg #(
- .DW (1),
- .SwAccess(prim_subreg_pkg::SwAccessW1C),
- .RESVAL (1'h0)
- ) u_intr_state_data_fault (
- .clk_i (clk_i),
- .rst_ni (rst_ni),
-
- // from register interface
- .we (intr_state_we),
- .wd (intr_state_data_fault_wd),
-
- // from internal hardware
- .de (hw2reg.intr_state.data_fault.de),
- .d (hw2reg.intr_state.data_fault.d),
-
- // to internal hardware
- .qe (),
- .q (reg2hw.intr_state.data_fault.q),
- .ds (),
-
- // to register interface (read)
- .qs (intr_state_data_fault_qs)
- );
-
// R[intr_enable]: V(False)
// F[host_req]: 0:0
@@ -365,36 +334,10 @@
.qs (intr_enable_fault_qs)
);
- // F[data_fault]: 3:3
- prim_subreg #(
- .DW (1),
- .SwAccess(prim_subreg_pkg::SwAccessRW),
- .RESVAL (1'h0)
- ) u_intr_enable_data_fault (
- .clk_i (clk_i),
- .rst_ni (rst_ni),
-
- // from register interface
- .we (intr_enable_we),
- .wd (intr_enable_data_fault_wd),
-
- // from internal hardware
- .de (1'b0),
- .d ('0),
-
- // to internal hardware
- .qe (),
- .q (reg2hw.intr_enable.data_fault.q),
- .ds (),
-
- // to register interface (read)
- .qs (intr_enable_data_fault_qs)
- );
-
// R[intr_test]: V(True)
logic intr_test_qe;
- logic [3:0] intr_test_flds_we;
+ logic [2:0] intr_test_flds_we;
assign intr_test_qe = &intr_test_flds_we;
// F[host_req]: 0:0
prim_subreg_ext #(
@@ -444,22 +387,6 @@
);
assign reg2hw.intr_test.fault.qe = intr_test_qe;
- // F[data_fault]: 3:3
- prim_subreg_ext #(
- .DW (1)
- ) u_intr_test_data_fault (
- .re (1'b0),
- .we (intr_test_we),
- .wd (intr_test_data_fault_wd),
- .d ('0),
- .qre (),
- .qe (intr_test_flds_we[3]),
- .q (reg2hw.intr_test.data_fault.q),
- .ds (),
- .qs ()
- );
- assign reg2hw.intr_test.data_fault.qe = intr_test_qe;
-
// R[ctrl]: V(False)
// F[freeze]: 0:0
@@ -875,8 +802,6 @@
assign intr_state_finish_wd = reg_wdata[1];
assign intr_state_fault_wd = reg_wdata[2];
-
- assign intr_state_data_fault_wd = reg_wdata[3];
assign intr_enable_we = addr_hit[1] & reg_we & !reg_error;
assign intr_enable_host_req_wd = reg_wdata[0];
@@ -884,8 +809,6 @@
assign intr_enable_finish_wd = reg_wdata[1];
assign intr_enable_fault_wd = reg_wdata[2];
-
- assign intr_enable_data_fault_wd = reg_wdata[3];
assign intr_test_we = addr_hit[2] & reg_we & !reg_error;
assign intr_test_host_req_wd = reg_wdata[0];
@@ -893,8 +816,6 @@
assign intr_test_finish_wd = reg_wdata[1];
assign intr_test_fault_wd = reg_wdata[2];
-
- assign intr_test_data_fault_wd = reg_wdata[3];
assign ctrl_we = addr_hit[3] & reg_we & !reg_error;
assign ctrl_freeze_wd = reg_wdata[0];
@@ -947,21 +868,18 @@
reg_rdata_next[0] = intr_state_host_req_qs;
reg_rdata_next[1] = intr_state_finish_qs;
reg_rdata_next[2] = intr_state_fault_qs;
- reg_rdata_next[3] = intr_state_data_fault_qs;
end
addr_hit[1]: begin
reg_rdata_next[0] = intr_enable_host_req_qs;
reg_rdata_next[1] = intr_enable_finish_qs;
reg_rdata_next[2] = intr_enable_fault_qs;
- reg_rdata_next[3] = intr_enable_data_fault_qs;
end
addr_hit[2]: begin
reg_rdata_next[0] = '0;
reg_rdata_next[1] = '0;
reg_rdata_next[2] = '0;
- reg_rdata_next[3] = '0;
end
addr_hit[3]: begin
diff --git a/hw/top_matcha/ip/ml_top/rtl/ml_top_reg_pkg.sv b/hw/top_matcha/ip/ml_top/rtl/ml_top_reg_pkg.sv
index 2e87df2..0540524 100644
--- a/hw/top_matcha/ip/ml_top/rtl/ml_top_reg_pkg.sv
+++ b/hw/top_matcha/ip/ml_top/rtl/ml_top_reg_pkg.sv
@@ -24,9 +24,6 @@
struct packed {
logic q;
} fault;
- struct packed {
- logic q;
- } data_fault;
} ml_top_reg2hw_intr_state_reg_t;
typedef struct packed {
@@ -39,9 +36,6 @@
struct packed {
logic q;
} fault;
- struct packed {
- logic q;
- } data_fault;
} ml_top_reg2hw_intr_enable_reg_t;
typedef struct packed {
@@ -57,10 +51,6 @@
logic q;
logic qe;
} fault;
- struct packed {
- logic q;
- logic qe;
- } data_fault;
} ml_top_reg2hw_intr_test_reg_t;
typedef struct packed {
@@ -125,10 +115,6 @@
logic d;
logic de;
} fault;
- struct packed {
- logic d;
- logic de;
- } data_fault;
} ml_top_hw2reg_intr_state_reg_t;
typedef struct packed {
@@ -166,9 +152,9 @@
// Register -> HW type for core interface
typedef struct packed {
- ml_top_reg2hw_intr_state_reg_t intr_state; // [133:130]
- ml_top_reg2hw_intr_enable_reg_t intr_enable; // [129:126]
- ml_top_reg2hw_intr_test_reg_t intr_test; // [125:118]
+ ml_top_reg2hw_intr_state_reg_t intr_state; // [129:127]
+ ml_top_reg2hw_intr_enable_reg_t intr_enable; // [126:124]
+ ml_top_reg2hw_intr_test_reg_t intr_test; // [123:118]
ml_top_reg2hw_ctrl_reg_t ctrl; // [117:86]
ml_top_reg2hw_memory_bank_ctrl_reg_t memory_bank_ctrl; // [85:54]
ml_top_reg2hw_error_status_reg_t error_status; // [53:45]
@@ -178,7 +164,7 @@
// HW -> register type for core interface
typedef struct packed {
- ml_top_hw2reg_intr_state_reg_t intr_state; // [47:40]
+ ml_top_hw2reg_intr_state_reg_t intr_state; // [45:40]
ml_top_hw2reg_error_status_reg_t error_status; // [39:29]
ml_top_hw2reg_init_end_reg_t init_end; // [28:4]
ml_top_hw2reg_init_status_reg_t init_status; // [3:0]
@@ -196,11 +182,10 @@
parameter logic [CoreAw-1:0] ML_TOP_INIT_STATUS_OFFSET = 6'h 20;
// Reset values for hwext registers and their fields for core interface
- parameter logic [3:0] ML_TOP_INTR_TEST_RESVAL = 4'h 0;
+ parameter logic [2:0] ML_TOP_INTR_TEST_RESVAL = 3'h 0;
parameter logic [0:0] ML_TOP_INTR_TEST_HOST_REQ_RESVAL = 1'h 0;
parameter logic [0:0] ML_TOP_INTR_TEST_FINISH_RESVAL = 1'h 0;
parameter logic [0:0] ML_TOP_INTR_TEST_FAULT_RESVAL = 1'h 0;
- parameter logic [0:0] ML_TOP_INTR_TEST_DATA_FAULT_RESVAL = 1'h 0;
// Register index for core interface
typedef enum int {
diff --git a/hw/top_matcha/ip_autogen/rv_plic_smc/data/rv_plic_smc.hjson b/hw/top_matcha/ip_autogen/rv_plic_smc/data/rv_plic_smc.hjson
index d017015..ed4b9f8 100644
--- a/hw/top_matcha/ip_autogen/rv_plic_smc/data/rv_plic_smc.hjson
+++ b/hw/top_matcha/ip_autogen/rv_plic_smc/data/rv_plic_smc.hjson
@@ -35,7 +35,7 @@
{ name: "NumSrc",
desc: "Number of interrupt sources",
type: "int",
- default: "44",
+ default: "43",
local: "true"
},
{ name: "NumTarget",
@@ -440,14 +440,6 @@
{ bits: "1:0" }
],
}
- { name: "PRIO43",
- desc: "Interrupt Source 43 Priority",
- swaccess: "rw",
- hwaccess: "hro",
- fields: [
- { bits: "1:0" }
- ],
- }
{ skipto: "0x00001000" }
{ multireg: {
name: "IP",
diff --git a/hw/top_matcha/ip_autogen/rv_plic_smc/data/top_matcha_rv_plic_smc.ipconfig.hjson b/hw/top_matcha/ip_autogen/rv_plic_smc/data/top_matcha_rv_plic_smc.ipconfig.hjson
index 07b048b..15b78f9 100644
--- a/hw/top_matcha/ip_autogen/rv_plic_smc/data/top_matcha_rv_plic_smc.ipconfig.hjson
+++ b/hw/top_matcha/ip_autogen/rv_plic_smc/data/top_matcha_rv_plic_smc.ipconfig.hjson
@@ -6,7 +6,7 @@
param_values:
{
prio: 3
- src: 44
+ src: 43
target: 1
module_instance_name: rv_plic_smc
}
diff --git a/hw/top_matcha/ip_autogen/rv_plic_smc/rtl/rv_plic_smc.sv b/hw/top_matcha/ip_autogen/rv_plic_smc/rtl/rv_plic_smc.sv
index ec53602..f668469 100644
--- a/hw/top_matcha/ip_autogen/rv_plic_smc/rtl/rv_plic_smc.sv
+++ b/hw/top_matcha/ip_autogen/rv_plic_smc/rtl/rv_plic_smc.sv
@@ -139,12 +139,11 @@
assign prio[40] = reg2hw.prio40.q;
assign prio[41] = reg2hw.prio41.q;
assign prio[42] = reg2hw.prio42.q;
- assign prio[43] = reg2hw.prio43.q;
//////////////////////
// Interrupt Enable //
//////////////////////
- for (genvar s = 0; s < 44; s++) begin : gen_ie0
+ for (genvar s = 0; s < 43; s++) begin : gen_ie0
assign ie[0][s] = reg2hw.ie0[s].q;
end
@@ -170,7 +169,7 @@
////////
// IP //
////////
- for (genvar s = 0; s < 44; s++) begin : gen_ip
+ for (genvar s = 0; s < 43; s++) begin : gen_ip
assign hw2reg.ip[s].de = 1'b1; // Always write
assign hw2reg.ip[s].d = ip[s];
end
diff --git a/hw/top_matcha/ip_autogen/rv_plic_smc/rtl/rv_plic_smc_reg_pkg.sv b/hw/top_matcha/ip_autogen/rv_plic_smc/rtl/rv_plic_smc_reg_pkg.sv
index b3467b6..0a3227b 100644
--- a/hw/top_matcha/ip_autogen/rv_plic_smc/rtl/rv_plic_smc_reg_pkg.sv
+++ b/hw/top_matcha/ip_autogen/rv_plic_smc/rtl/rv_plic_smc_reg_pkg.sv
@@ -7,7 +7,7 @@
package rv_plic_smc_reg_pkg;
// Param list
- parameter int NumSrc = 44;
+ parameter int NumSrc = 43;
parameter int NumTarget = 1;
parameter int PrioWidth = 2;
parameter int NumAlerts = 1;
@@ -192,10 +192,6 @@
} rv_plic_smc_reg2hw_prio42_reg_t;
typedef struct packed {
- logic [1:0] q;
- } rv_plic_smc_reg2hw_prio43_reg_t;
-
- typedef struct packed {
logic q;
} rv_plic_smc_reg2hw_ie0_mreg_t;
@@ -229,51 +225,50 @@
// Register -> HW type
typedef struct packed {
- rv_plic_smc_reg2hw_prio0_reg_t prio0; // [144:143]
- rv_plic_smc_reg2hw_prio1_reg_t prio1; // [142:141]
- rv_plic_smc_reg2hw_prio2_reg_t prio2; // [140:139]
- rv_plic_smc_reg2hw_prio3_reg_t prio3; // [138:137]
- rv_plic_smc_reg2hw_prio4_reg_t prio4; // [136:135]
- rv_plic_smc_reg2hw_prio5_reg_t prio5; // [134:133]
- rv_plic_smc_reg2hw_prio6_reg_t prio6; // [132:131]
- rv_plic_smc_reg2hw_prio7_reg_t prio7; // [130:129]
- rv_plic_smc_reg2hw_prio8_reg_t prio8; // [128:127]
- rv_plic_smc_reg2hw_prio9_reg_t prio9; // [126:125]
- rv_plic_smc_reg2hw_prio10_reg_t prio10; // [124:123]
- rv_plic_smc_reg2hw_prio11_reg_t prio11; // [122:121]
- rv_plic_smc_reg2hw_prio12_reg_t prio12; // [120:119]
- rv_plic_smc_reg2hw_prio13_reg_t prio13; // [118:117]
- rv_plic_smc_reg2hw_prio14_reg_t prio14; // [116:115]
- rv_plic_smc_reg2hw_prio15_reg_t prio15; // [114:113]
- rv_plic_smc_reg2hw_prio16_reg_t prio16; // [112:111]
- rv_plic_smc_reg2hw_prio17_reg_t prio17; // [110:109]
- rv_plic_smc_reg2hw_prio18_reg_t prio18; // [108:107]
- rv_plic_smc_reg2hw_prio19_reg_t prio19; // [106:105]
- rv_plic_smc_reg2hw_prio20_reg_t prio20; // [104:103]
- rv_plic_smc_reg2hw_prio21_reg_t prio21; // [102:101]
- rv_plic_smc_reg2hw_prio22_reg_t prio22; // [100:99]
- rv_plic_smc_reg2hw_prio23_reg_t prio23; // [98:97]
- rv_plic_smc_reg2hw_prio24_reg_t prio24; // [96:95]
- rv_plic_smc_reg2hw_prio25_reg_t prio25; // [94:93]
- rv_plic_smc_reg2hw_prio26_reg_t prio26; // [92:91]
- rv_plic_smc_reg2hw_prio27_reg_t prio27; // [90:89]
- rv_plic_smc_reg2hw_prio28_reg_t prio28; // [88:87]
- rv_plic_smc_reg2hw_prio29_reg_t prio29; // [86:85]
- rv_plic_smc_reg2hw_prio30_reg_t prio30; // [84:83]
- rv_plic_smc_reg2hw_prio31_reg_t prio31; // [82:81]
- rv_plic_smc_reg2hw_prio32_reg_t prio32; // [80:79]
- rv_plic_smc_reg2hw_prio33_reg_t prio33; // [78:77]
- rv_plic_smc_reg2hw_prio34_reg_t prio34; // [76:75]
- rv_plic_smc_reg2hw_prio35_reg_t prio35; // [74:73]
- rv_plic_smc_reg2hw_prio36_reg_t prio36; // [72:71]
- rv_plic_smc_reg2hw_prio37_reg_t prio37; // [70:69]
- rv_plic_smc_reg2hw_prio38_reg_t prio38; // [68:67]
- rv_plic_smc_reg2hw_prio39_reg_t prio39; // [66:65]
- rv_plic_smc_reg2hw_prio40_reg_t prio40; // [64:63]
- rv_plic_smc_reg2hw_prio41_reg_t prio41; // [62:61]
- rv_plic_smc_reg2hw_prio42_reg_t prio42; // [60:59]
- rv_plic_smc_reg2hw_prio43_reg_t prio43; // [58:57]
- rv_plic_smc_reg2hw_ie0_mreg_t [43:0] ie0; // [56:13]
+ rv_plic_smc_reg2hw_prio0_reg_t prio0; // [141:140]
+ rv_plic_smc_reg2hw_prio1_reg_t prio1; // [139:138]
+ rv_plic_smc_reg2hw_prio2_reg_t prio2; // [137:136]
+ rv_plic_smc_reg2hw_prio3_reg_t prio3; // [135:134]
+ rv_plic_smc_reg2hw_prio4_reg_t prio4; // [133:132]
+ rv_plic_smc_reg2hw_prio5_reg_t prio5; // [131:130]
+ rv_plic_smc_reg2hw_prio6_reg_t prio6; // [129:128]
+ rv_plic_smc_reg2hw_prio7_reg_t prio7; // [127:126]
+ rv_plic_smc_reg2hw_prio8_reg_t prio8; // [125:124]
+ rv_plic_smc_reg2hw_prio9_reg_t prio9; // [123:122]
+ rv_plic_smc_reg2hw_prio10_reg_t prio10; // [121:120]
+ rv_plic_smc_reg2hw_prio11_reg_t prio11; // [119:118]
+ rv_plic_smc_reg2hw_prio12_reg_t prio12; // [117:116]
+ rv_plic_smc_reg2hw_prio13_reg_t prio13; // [115:114]
+ rv_plic_smc_reg2hw_prio14_reg_t prio14; // [113:112]
+ rv_plic_smc_reg2hw_prio15_reg_t prio15; // [111:110]
+ rv_plic_smc_reg2hw_prio16_reg_t prio16; // [109:108]
+ rv_plic_smc_reg2hw_prio17_reg_t prio17; // [107:106]
+ rv_plic_smc_reg2hw_prio18_reg_t prio18; // [105:104]
+ rv_plic_smc_reg2hw_prio19_reg_t prio19; // [103:102]
+ rv_plic_smc_reg2hw_prio20_reg_t prio20; // [101:100]
+ rv_plic_smc_reg2hw_prio21_reg_t prio21; // [99:98]
+ rv_plic_smc_reg2hw_prio22_reg_t prio22; // [97:96]
+ rv_plic_smc_reg2hw_prio23_reg_t prio23; // [95:94]
+ rv_plic_smc_reg2hw_prio24_reg_t prio24; // [93:92]
+ rv_plic_smc_reg2hw_prio25_reg_t prio25; // [91:90]
+ rv_plic_smc_reg2hw_prio26_reg_t prio26; // [89:88]
+ rv_plic_smc_reg2hw_prio27_reg_t prio27; // [87:86]
+ rv_plic_smc_reg2hw_prio28_reg_t prio28; // [85:84]
+ rv_plic_smc_reg2hw_prio29_reg_t prio29; // [83:82]
+ rv_plic_smc_reg2hw_prio30_reg_t prio30; // [81:80]
+ rv_plic_smc_reg2hw_prio31_reg_t prio31; // [79:78]
+ rv_plic_smc_reg2hw_prio32_reg_t prio32; // [77:76]
+ rv_plic_smc_reg2hw_prio33_reg_t prio33; // [75:74]
+ rv_plic_smc_reg2hw_prio34_reg_t prio34; // [73:72]
+ rv_plic_smc_reg2hw_prio35_reg_t prio35; // [71:70]
+ rv_plic_smc_reg2hw_prio36_reg_t prio36; // [69:68]
+ rv_plic_smc_reg2hw_prio37_reg_t prio37; // [67:66]
+ rv_plic_smc_reg2hw_prio38_reg_t prio38; // [65:64]
+ rv_plic_smc_reg2hw_prio39_reg_t prio39; // [63:62]
+ rv_plic_smc_reg2hw_prio40_reg_t prio40; // [61:60]
+ rv_plic_smc_reg2hw_prio41_reg_t prio41; // [59:58]
+ rv_plic_smc_reg2hw_prio42_reg_t prio42; // [57:56]
+ rv_plic_smc_reg2hw_ie0_mreg_t [42:0] ie0; // [55:13]
rv_plic_smc_reg2hw_threshold0_reg_t threshold0; // [12:11]
rv_plic_smc_reg2hw_cc0_reg_t cc0; // [10:3]
rv_plic_smc_reg2hw_msip0_reg_t msip0; // [2:2]
@@ -282,7 +277,7 @@
// HW -> register type
typedef struct packed {
- rv_plic_smc_hw2reg_ip_mreg_t [43:0] ip; // [93:6]
+ rv_plic_smc_hw2reg_ip_mreg_t [42:0] ip; // [91:6]
rv_plic_smc_hw2reg_cc0_reg_t cc0; // [5:0]
} rv_plic_smc_hw2reg_t;
@@ -330,7 +325,6 @@
parameter logic [BlockAw-1:0] RV_PLIC_SMC_PRIO40_OFFSET = 27'h a0;
parameter logic [BlockAw-1:0] RV_PLIC_SMC_PRIO41_OFFSET = 27'h a4;
parameter logic [BlockAw-1:0] RV_PLIC_SMC_PRIO42_OFFSET = 27'h a8;
- parameter logic [BlockAw-1:0] RV_PLIC_SMC_PRIO43_OFFSET = 27'h ac;
parameter logic [BlockAw-1:0] RV_PLIC_SMC_IP_0_OFFSET = 27'h 1000;
parameter logic [BlockAw-1:0] RV_PLIC_SMC_IP_1_OFFSET = 27'h 1004;
parameter logic [BlockAw-1:0] RV_PLIC_SMC_IE0_0_OFFSET = 27'h 2000;
@@ -389,7 +383,6 @@
RV_PLIC_SMC_PRIO40,
RV_PLIC_SMC_PRIO41,
RV_PLIC_SMC_PRIO42,
- RV_PLIC_SMC_PRIO43,
RV_PLIC_SMC_IP_0,
RV_PLIC_SMC_IP_1,
RV_PLIC_SMC_IE0_0,
@@ -401,7 +394,7 @@
} rv_plic_smc_id_e;
// Register width information to check illegal writes
- parameter logic [3:0] RV_PLIC_SMC_PERMIT [52] = '{
+ parameter logic [3:0] RV_PLIC_SMC_PERMIT [51] = '{
4'b 0001, // index[ 0] RV_PLIC_SMC_PRIO0
4'b 0001, // index[ 1] RV_PLIC_SMC_PRIO1
4'b 0001, // index[ 2] RV_PLIC_SMC_PRIO2
@@ -445,15 +438,14 @@
4'b 0001, // index[40] RV_PLIC_SMC_PRIO40
4'b 0001, // index[41] RV_PLIC_SMC_PRIO41
4'b 0001, // index[42] RV_PLIC_SMC_PRIO42
- 4'b 0001, // index[43] RV_PLIC_SMC_PRIO43
- 4'b 1111, // index[44] RV_PLIC_SMC_IP_0
- 4'b 0011, // index[45] RV_PLIC_SMC_IP_1
- 4'b 1111, // index[46] RV_PLIC_SMC_IE0_0
- 4'b 0011, // index[47] RV_PLIC_SMC_IE0_1
- 4'b 0001, // index[48] RV_PLIC_SMC_THRESHOLD0
- 4'b 0001, // index[49] RV_PLIC_SMC_CC0
- 4'b 0001, // index[50] RV_PLIC_SMC_MSIP0
- 4'b 0001 // index[51] RV_PLIC_SMC_ALERT_TEST
+ 4'b 1111, // index[43] RV_PLIC_SMC_IP_0
+ 4'b 0011, // index[44] RV_PLIC_SMC_IP_1
+ 4'b 1111, // index[45] RV_PLIC_SMC_IE0_0
+ 4'b 0011, // index[46] RV_PLIC_SMC_IE0_1
+ 4'b 0001, // index[47] RV_PLIC_SMC_THRESHOLD0
+ 4'b 0001, // index[48] RV_PLIC_SMC_CC0
+ 4'b 0001, // index[49] RV_PLIC_SMC_MSIP0
+ 4'b 0001 // index[50] RV_PLIC_SMC_ALERT_TEST
};
endpackage
diff --git a/hw/top_matcha/ip_autogen/rv_plic_smc/rtl/rv_plic_smc_reg_top.sv b/hw/top_matcha/ip_autogen/rv_plic_smc/rtl/rv_plic_smc_reg_top.sv
index 176cde4..711efb7 100644
--- a/hw/top_matcha/ip_autogen/rv_plic_smc/rtl/rv_plic_smc_reg_top.sv
+++ b/hw/top_matcha/ip_autogen/rv_plic_smc/rtl/rv_plic_smc_reg_top.sv
@@ -55,9 +55,9 @@
// also check for spurious write enables
logic reg_we_err;
- logic [51:0] reg_we_check;
+ logic [50:0] reg_we_check;
prim_reg_we_check #(
- .OneHotWidth(52)
+ .OneHotWidth(51)
) u_prim_reg_we_check (
.clk_i(clk_i),
.rst_ni(rst_ni),
@@ -253,9 +253,6 @@
logic prio42_we;
logic [1:0] prio42_qs;
logic [1:0] prio42_wd;
- logic prio43_we;
- logic [1:0] prio43_qs;
- logic [1:0] prio43_wd;
logic ip_0_p_0_qs;
logic ip_0_p_1_qs;
logic ip_0_p_2_qs;
@@ -299,7 +296,6 @@
logic ip_1_p_40_qs;
logic ip_1_p_41_qs;
logic ip_1_p_42_qs;
- logic ip_1_p_43_qs;
logic ie0_0_we;
logic ie0_0_e_0_qs;
logic ie0_0_e_0_wd;
@@ -388,8 +384,6 @@
logic ie0_1_e_41_wd;
logic ie0_1_e_42_qs;
logic ie0_1_e_42_wd;
- logic ie0_1_e_43_qs;
- logic ie0_1_e_43_wd;
logic threshold0_we;
logic [1:0] threshold0_qs;
logic [1:0] threshold0_wd;
@@ -1565,33 +1559,6 @@
);
- // R[prio43]: V(False)
- prim_subreg #(
- .DW (2),
- .SwAccess(prim_subreg_pkg::SwAccessRW),
- .RESVAL (2'h0)
- ) u_prio43 (
- .clk_i (clk_i),
- .rst_ni (rst_ni),
-
- // from register interface
- .we (prio43_we),
- .wd (prio43_wd),
-
- // from internal hardware
- .de (1'b0),
- .d ('0),
-
- // to internal hardware
- .qe (),
- .q (reg2hw.prio43.q),
- .ds (),
-
- // to register interface (read)
- .qs (prio43_qs)
- );
-
-
// Subregister 0 of Multireg ip
// R[ip_0]: V(False)
// F[p_0]: 0:0
@@ -2715,32 +2682,6 @@
.qs (ip_1_p_42_qs)
);
- // F[p_43]: 11:11
- prim_subreg #(
- .DW (1),
- .SwAccess(prim_subreg_pkg::SwAccessRO),
- .RESVAL (1'h0)
- ) u_ip_1_p_43 (
- .clk_i (clk_i),
- .rst_ni (rst_ni),
-
- // from register interface
- .we (1'b0),
- .wd ('0),
-
- // from internal hardware
- .de (hw2reg.ip[43].de),
- .d (hw2reg.ip[43].d),
-
- // to internal hardware
- .qe (),
- .q (),
- .ds (),
-
- // to register interface (read)
- .qs (ip_1_p_43_qs)
- );
-
// Subregister 0 of Multireg ie0
// R[ie0_0]: V(False)
@@ -3865,32 +3806,6 @@
.qs (ie0_1_e_42_qs)
);
- // F[e_43]: 11:11
- prim_subreg #(
- .DW (1),
- .SwAccess(prim_subreg_pkg::SwAccessRW),
- .RESVAL (1'h0)
- ) u_ie0_1_e_43 (
- .clk_i (clk_i),
- .rst_ni (rst_ni),
-
- // from register interface
- .we (ie0_1_we),
- .wd (ie0_1_e_43_wd),
-
- // from internal hardware
- .de (1'b0),
- .d ('0),
-
- // to internal hardware
- .qe (),
- .q (reg2hw.ie0[43].q),
- .ds (),
-
- // to register interface (read)
- .qs (ie0_1_e_43_qs)
- );
-
// R[threshold0]: V(False)
prim_subreg #(
@@ -3987,7 +3902,7 @@
- logic [51:0] addr_hit;
+ logic [50:0] addr_hit;
always_comb begin
addr_hit = '0;
addr_hit[ 0] = (reg_addr == RV_PLIC_SMC_PRIO0_OFFSET);
@@ -4033,15 +3948,14 @@
addr_hit[40] = (reg_addr == RV_PLIC_SMC_PRIO40_OFFSET);
addr_hit[41] = (reg_addr == RV_PLIC_SMC_PRIO41_OFFSET);
addr_hit[42] = (reg_addr == RV_PLIC_SMC_PRIO42_OFFSET);
- addr_hit[43] = (reg_addr == RV_PLIC_SMC_PRIO43_OFFSET);
- addr_hit[44] = (reg_addr == RV_PLIC_SMC_IP_0_OFFSET);
- addr_hit[45] = (reg_addr == RV_PLIC_SMC_IP_1_OFFSET);
- addr_hit[46] = (reg_addr == RV_PLIC_SMC_IE0_0_OFFSET);
- addr_hit[47] = (reg_addr == RV_PLIC_SMC_IE0_1_OFFSET);
- addr_hit[48] = (reg_addr == RV_PLIC_SMC_THRESHOLD0_OFFSET);
- addr_hit[49] = (reg_addr == RV_PLIC_SMC_CC0_OFFSET);
- addr_hit[50] = (reg_addr == RV_PLIC_SMC_MSIP0_OFFSET);
- addr_hit[51] = (reg_addr == RV_PLIC_SMC_ALERT_TEST_OFFSET);
+ addr_hit[43] = (reg_addr == RV_PLIC_SMC_IP_0_OFFSET);
+ addr_hit[44] = (reg_addr == RV_PLIC_SMC_IP_1_OFFSET);
+ addr_hit[45] = (reg_addr == RV_PLIC_SMC_IE0_0_OFFSET);
+ addr_hit[46] = (reg_addr == RV_PLIC_SMC_IE0_1_OFFSET);
+ addr_hit[47] = (reg_addr == RV_PLIC_SMC_THRESHOLD0_OFFSET);
+ addr_hit[48] = (reg_addr == RV_PLIC_SMC_CC0_OFFSET);
+ addr_hit[49] = (reg_addr == RV_PLIC_SMC_MSIP0_OFFSET);
+ addr_hit[50] = (reg_addr == RV_PLIC_SMC_ALERT_TEST_OFFSET);
end
assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ;
@@ -4099,8 +4013,7 @@
(addr_hit[47] & (|(RV_PLIC_SMC_PERMIT[47] & ~reg_be))) |
(addr_hit[48] & (|(RV_PLIC_SMC_PERMIT[48] & ~reg_be))) |
(addr_hit[49] & (|(RV_PLIC_SMC_PERMIT[49] & ~reg_be))) |
- (addr_hit[50] & (|(RV_PLIC_SMC_PERMIT[50] & ~reg_be))) |
- (addr_hit[51] & (|(RV_PLIC_SMC_PERMIT[51] & ~reg_be)))));
+ (addr_hit[50] & (|(RV_PLIC_SMC_PERMIT[50] & ~reg_be)))));
end
// Generate write-enables
@@ -4233,10 +4146,7 @@
assign prio42_we = addr_hit[42] & reg_we & !reg_error;
assign prio42_wd = reg_wdata[1:0];
- assign prio43_we = addr_hit[43] & reg_we & !reg_error;
-
- assign prio43_wd = reg_wdata[1:0];
- assign ie0_0_we = addr_hit[46] & reg_we & !reg_error;
+ assign ie0_0_we = addr_hit[45] & reg_we & !reg_error;
assign ie0_0_e_0_wd = reg_wdata[0];
@@ -4301,7 +4211,7 @@
assign ie0_0_e_30_wd = reg_wdata[30];
assign ie0_0_e_31_wd = reg_wdata[31];
- assign ie0_1_we = addr_hit[47] & reg_we & !reg_error;
+ assign ie0_1_we = addr_hit[46] & reg_we & !reg_error;
assign ie0_1_e_32_wd = reg_wdata[0];
@@ -4324,19 +4234,17 @@
assign ie0_1_e_41_wd = reg_wdata[9];
assign ie0_1_e_42_wd = reg_wdata[10];
-
- assign ie0_1_e_43_wd = reg_wdata[11];
- assign threshold0_we = addr_hit[48] & reg_we & !reg_error;
+ assign threshold0_we = addr_hit[47] & reg_we & !reg_error;
assign threshold0_wd = reg_wdata[1:0];
- assign cc0_re = addr_hit[49] & reg_re & !reg_error;
- assign cc0_we = addr_hit[49] & reg_we & !reg_error;
+ assign cc0_re = addr_hit[48] & reg_re & !reg_error;
+ assign cc0_we = addr_hit[48] & reg_we & !reg_error;
assign cc0_wd = reg_wdata[5:0];
- assign msip0_we = addr_hit[50] & reg_we & !reg_error;
+ assign msip0_we = addr_hit[49] & reg_we & !reg_error;
assign msip0_wd = reg_wdata[0];
- assign alert_test_we = addr_hit[51] & reg_we & !reg_error;
+ assign alert_test_we = addr_hit[50] & reg_we & !reg_error;
assign alert_test_wd = reg_wdata[0];
@@ -4386,15 +4294,14 @@
reg_we_check[40] = prio40_we;
reg_we_check[41] = prio41_we;
reg_we_check[42] = prio42_we;
- reg_we_check[43] = prio43_we;
+ reg_we_check[43] = 1'b0;
reg_we_check[44] = 1'b0;
- reg_we_check[45] = 1'b0;
- reg_we_check[46] = ie0_0_we;
- reg_we_check[47] = ie0_1_we;
- reg_we_check[48] = threshold0_we;
- reg_we_check[49] = cc0_we;
- reg_we_check[50] = msip0_we;
- reg_we_check[51] = alert_test_we;
+ reg_we_check[45] = ie0_0_we;
+ reg_we_check[46] = ie0_1_we;
+ reg_we_check[47] = threshold0_we;
+ reg_we_check[48] = cc0_we;
+ reg_we_check[49] = msip0_we;
+ reg_we_check[50] = alert_test_we;
end
// Read data return
@@ -4574,10 +4481,6 @@
end
addr_hit[43]: begin
- reg_rdata_next[1:0] = prio43_qs;
- end
-
- addr_hit[44]: begin
reg_rdata_next[0] = ip_0_p_0_qs;
reg_rdata_next[1] = ip_0_p_1_qs;
reg_rdata_next[2] = ip_0_p_2_qs;
@@ -4612,7 +4515,7 @@
reg_rdata_next[31] = ip_0_p_31_qs;
end
- addr_hit[45]: begin
+ addr_hit[44]: begin
reg_rdata_next[0] = ip_1_p_32_qs;
reg_rdata_next[1] = ip_1_p_33_qs;
reg_rdata_next[2] = ip_1_p_34_qs;
@@ -4624,10 +4527,9 @@
reg_rdata_next[8] = ip_1_p_40_qs;
reg_rdata_next[9] = ip_1_p_41_qs;
reg_rdata_next[10] = ip_1_p_42_qs;
- reg_rdata_next[11] = ip_1_p_43_qs;
end
- addr_hit[46]: begin
+ addr_hit[45]: begin
reg_rdata_next[0] = ie0_0_e_0_qs;
reg_rdata_next[1] = ie0_0_e_1_qs;
reg_rdata_next[2] = ie0_0_e_2_qs;
@@ -4662,7 +4564,7 @@
reg_rdata_next[31] = ie0_0_e_31_qs;
end
- addr_hit[47]: begin
+ addr_hit[46]: begin
reg_rdata_next[0] = ie0_1_e_32_qs;
reg_rdata_next[1] = ie0_1_e_33_qs;
reg_rdata_next[2] = ie0_1_e_34_qs;
@@ -4674,22 +4576,21 @@
reg_rdata_next[8] = ie0_1_e_40_qs;
reg_rdata_next[9] = ie0_1_e_41_qs;
reg_rdata_next[10] = ie0_1_e_42_qs;
- reg_rdata_next[11] = ie0_1_e_43_qs;
end
- addr_hit[48]: begin
+ addr_hit[47]: begin
reg_rdata_next[1:0] = threshold0_qs;
end
- addr_hit[49]: begin
+ addr_hit[48]: begin
reg_rdata_next[5:0] = cc0_qs;
end
- addr_hit[50]: begin
+ addr_hit[49]: begin
reg_rdata_next[0] = msip0_qs;
end
- addr_hit[51]: begin
+ addr_hit[50]: begin
reg_rdata_next[0] = '0;
end
diff --git a/hw/top_matcha/rtl/autogen/top_matcha.sv b/hw/top_matcha/rtl/autogen/top_matcha.sv
index 4447ec8..0c21453 100644
--- a/hw/top_matcha/rtl/autogen/top_matcha.sv
+++ b/hw/top_matcha/rtl/autogen/top_matcha.sv
@@ -623,7 +623,7 @@
logic intr_tlul_mailbox_sec_eirq;
// smc_intr_vector for SMC core
- logic [43:0] smc_intr_vector;
+ logic [42:0] smc_intr_vector;
// Interrupt source list for SMC core
logic intr_smc_uart_tx_watermark;
logic intr_smc_uart_rx_watermark;
@@ -660,7 +660,6 @@
logic intr_ml_top_host_req;
logic intr_ml_top_finish;
logic intr_ml_top_fault;
- logic intr_ml_top_data_fault;
logic intr_spi_host2_error;
logic intr_spi_host2_spi_event;
logic intr_rv_timer_smc2_timer_expired_hart0_timer0;
@@ -3244,10 +3243,9 @@
ml_top u_ml_top (
// Interrupt
- .intr_host_req_o (intr_ml_top_host_req),
- .intr_finish_o (intr_ml_top_finish),
- .intr_fault_o (intr_ml_top_fault),
- .intr_data_fault_o (intr_ml_top_data_fault),
+ .intr_host_req_o (intr_ml_top_host_req),
+ .intr_finish_o (intr_ml_top_finish),
+ .intr_fault_o (intr_ml_top_fault),
// Inter-module signals
.isp_cvalid_i(isp_wrapper_isp_cvalid),
@@ -3588,14 +3586,13 @@
// smc core interrupt assignments
assign smc_intr_vector = {
- intr_i2s0_rx_overflow, // IDs [43 +: 1]
- intr_i2s0_tx_empty, // IDs [42 +: 1]
- intr_i2s0_rx_watermark, // IDs [41 +: 1]
- intr_i2s0_tx_watermark, // IDs [40 +: 1]
- intr_rv_timer_smc2_timer_expired_hart0_timer0, // IDs [39 +: 1]
- intr_spi_host2_spi_event, // IDs [38 +: 1]
- intr_spi_host2_error, // IDs [37 +: 1]
- intr_ml_top_data_fault, // IDs [36 +: 1]
+ intr_i2s0_rx_overflow, // IDs [42 +: 1]
+ intr_i2s0_tx_empty, // IDs [41 +: 1]
+ intr_i2s0_rx_watermark, // IDs [40 +: 1]
+ intr_i2s0_tx_watermark, // IDs [39 +: 1]
+ intr_rv_timer_smc2_timer_expired_hart0_timer0, // IDs [38 +: 1]
+ intr_spi_host2_spi_event, // IDs [37 +: 1]
+ intr_spi_host2_error, // IDs [36 +: 1]
intr_ml_top_fault, // IDs [35 +: 1]
intr_ml_top_finish, // IDs [34 +: 1]
intr_ml_top_host_req, // IDs [33 +: 1]
diff --git a/hw/top_matcha/sw/autogen/top_matcha.c b/hw/top_matcha/sw/autogen/top_matcha.c
index 707d22a..48aeda7 100644
--- a/hw/top_matcha/sw/autogen/top_matcha.c
+++ b/hw/top_matcha/sw/autogen/top_matcha.c
@@ -205,7 +205,7 @@
};
const top_matcha_plic_peripheral_smc_t
- top_matcha_plic_interrupt_for_peripheral_smc[44] = {
+ top_matcha_plic_interrupt_for_peripheral_smc[43] = {
[kTopMatchaPlicIrqIdNoneSmc] = kTopMatchaPlicPeripheralUnknownSmc,
[kTopMatchaPlicIrqIdSmcUartTxWatermark] = kTopMatchaPlicPeripheralSmcUart,
[kTopMatchaPlicIrqIdSmcUartRxWatermark] = kTopMatchaPlicPeripheralSmcUart,
@@ -242,7 +242,6 @@
[kTopMatchaPlicIrqIdMlTopHostReq] = kTopMatchaPlicPeripheralMlTop,
[kTopMatchaPlicIrqIdMlTopFinish] = kTopMatchaPlicPeripheralMlTop,
[kTopMatchaPlicIrqIdMlTopFault] = kTopMatchaPlicPeripheralMlTop,
- [kTopMatchaPlicIrqIdMlTopDataFault] = kTopMatchaPlicPeripheralMlTop,
[kTopMatchaPlicIrqIdSpiHost2Error] = kTopMatchaPlicPeripheralSpiHost2,
[kTopMatchaPlicIrqIdSpiHost2SpiEvent] = kTopMatchaPlicPeripheralSpiHost2,
[kTopMatchaPlicIrqIdRvTimerSmc2TimerExpiredHart0Timer0] = kTopMatchaPlicPeripheralRvTimerSmc2,
diff --git a/hw/top_matcha/sw/autogen/top_matcha.h b/hw/top_matcha/sw/autogen/top_matcha.h
index 6f3a7b8..e4770bc 100644
--- a/hw/top_matcha/sw/autogen/top_matcha.h
+++ b/hw/top_matcha/sw/autogen/top_matcha.h
@@ -1589,15 +1589,14 @@
kTopMatchaPlicIrqIdMlTopHostReq = 33, /**< ml_top_host_req */
kTopMatchaPlicIrqIdMlTopFinish = 34, /**< ml_top_finish */
kTopMatchaPlicIrqIdMlTopFault = 35, /**< ml_top_fault */
- kTopMatchaPlicIrqIdMlTopDataFault = 36, /**< ml_top_data_fault */
- kTopMatchaPlicIrqIdSpiHost2Error = 37, /**< spi_host2_error */
- kTopMatchaPlicIrqIdSpiHost2SpiEvent = 38, /**< spi_host2_spi_event */
- kTopMatchaPlicIrqIdRvTimerSmc2TimerExpiredHart0Timer0 = 39, /**< rv_timer_smc2_timer_expired_hart0_timer0 */
- kTopMatchaPlicIrqIdI2s0TxWatermark = 40, /**< i2s0_tx_watermark */
- kTopMatchaPlicIrqIdI2s0RxWatermark = 41, /**< i2s0_rx_watermark */
- kTopMatchaPlicIrqIdI2s0TxEmpty = 42, /**< i2s0_tx_empty */
- kTopMatchaPlicIrqIdI2s0RxOverflow = 43, /**< i2s0_rx_overflow */
- kTopMatchaPlicIrqIdLastSmc = 43, /**< \internal The Last Valid Interrupt ID. */
+ kTopMatchaPlicIrqIdSpiHost2Error = 36, /**< spi_host2_error */
+ kTopMatchaPlicIrqIdSpiHost2SpiEvent = 37, /**< spi_host2_spi_event */
+ kTopMatchaPlicIrqIdRvTimerSmc2TimerExpiredHart0Timer0 = 38, /**< rv_timer_smc2_timer_expired_hart0_timer0 */
+ kTopMatchaPlicIrqIdI2s0TxWatermark = 39, /**< i2s0_tx_watermark */
+ kTopMatchaPlicIrqIdI2s0RxWatermark = 40, /**< i2s0_rx_watermark */
+ kTopMatchaPlicIrqIdI2s0TxEmpty = 41, /**< i2s0_tx_empty */
+ kTopMatchaPlicIrqIdI2s0RxOverflow = 42, /**< i2s0_rx_overflow */
+ kTopMatchaPlicIrqIdLastSmc = 42, /**< \internal The Last Valid Interrupt ID. */
} top_matcha_plic_irq_id_smc_t;
/**
@@ -1610,7 +1609,7 @@
top_matcha_plic_interrupt_for_peripheral[190];
extern const top_matcha_plic_peripheral_smc_t
- top_matcha_plic_interrupt_for_peripheral_smc[44];
+ top_matcha_plic_interrupt_for_peripheral_smc[43];
/**
* PLIC Interrupt Target.
diff --git a/hw/top_matcha/sw/autogen/top_matcha_smc_irq.h b/hw/top_matcha/sw/autogen/top_matcha_smc_irq.h
index 76dc6ae..5d19bd6 100644
--- a/hw/top_matcha/sw/autogen/top_matcha_smc_irq.h
+++ b/hw/top_matcha/sw/autogen/top_matcha_smc_irq.h
@@ -56,15 +56,14 @@
#define TOP_MATCHA_PLIC_IRQ_ID_ML_TOP_HOST_REQ 33 /**< ml_top_host_req */
#define TOP_MATCHA_PLIC_IRQ_ID_ML_TOP_FINISH 34 /**< ml_top_finish */
#define TOP_MATCHA_PLIC_IRQ_ID_ML_TOP_FAULT 35 /**< ml_top_fault */
-#define TOP_MATCHA_PLIC_IRQ_ID_ML_TOP_DATA_FAULT 36 /**< ml_top_data_fault */
-#define TOP_MATCHA_PLIC_IRQ_ID_SPI_HOST2_ERROR 37 /**< spi_host2_error */
-#define TOP_MATCHA_PLIC_IRQ_ID_SPI_HOST2_SPI_EVENT 38 /**< spi_host2_spi_event */
-#define TOP_MATCHA_PLIC_IRQ_ID_RV_TIMER_SMC2_TIMER_EXPIRED_HART0_TIMER0 39 /**< rv_timer_smc2_timer_expired_hart0_timer0 */
-#define TOP_MATCHA_PLIC_IRQ_ID_I2S0_TX_WATERMARK 40 /**< i2s0_tx_watermark */
-#define TOP_MATCHA_PLIC_IRQ_ID_I2S0_RX_WATERMARK 41 /**< i2s0_rx_watermark */
-#define TOP_MATCHA_PLIC_IRQ_ID_I2S0_TX_EMPTY 42 /**< i2s0_tx_empty */
-#define TOP_MATCHA_PLIC_IRQ_ID_I2S0_RX_OVERFLOW 43 /**< i2s0_rx_overflow */
-#define TOP_MATCHA_PLIC_IRQ_ID_LAST_SMC 43 /**< \internal The Last Valid Interrupt ID. */
+#define TOP_MATCHA_PLIC_IRQ_ID_SPI_HOST2_ERROR 36 /**< spi_host2_error */
+#define TOP_MATCHA_PLIC_IRQ_ID_SPI_HOST2_SPI_EVENT 37 /**< spi_host2_spi_event */
+#define TOP_MATCHA_PLIC_IRQ_ID_RV_TIMER_SMC2_TIMER_EXPIRED_HART0_TIMER0 38 /**< rv_timer_smc2_timer_expired_hart0_timer0 */
+#define TOP_MATCHA_PLIC_IRQ_ID_I2S0_TX_WATERMARK 39 /**< i2s0_tx_watermark */
+#define TOP_MATCHA_PLIC_IRQ_ID_I2S0_RX_WATERMARK 40 /**< i2s0_rx_watermark */
+#define TOP_MATCHA_PLIC_IRQ_ID_I2S0_TX_EMPTY 41 /**< i2s0_tx_empty */
+#define TOP_MATCHA_PLIC_IRQ_ID_I2S0_RX_OVERFLOW 42 /**< i2s0_rx_overflow */
+#define TOP_MATCHA_PLIC_IRQ_ID_LAST_SMC 42 /**< \internal The Last Valid Interrupt ID. */
#endif // __ASSEMBLER__
diff --git a/sw/device/lib/dif/autogen/dif_ml_top_autogen.c b/sw/device/lib/dif/autogen/dif_ml_top_autogen.c
index ea05604..16fa868 100644
--- a/sw/device/lib/dif/autogen/dif_ml_top_autogen.c
+++ b/sw/device/lib/dif/autogen/dif_ml_top_autogen.c
@@ -5,9 +5,11 @@
// THIS FILE HAS BEEN GENERATED, DO NOT EDIT MANUALLY. COMMAND:
// util/make_new_dif.py --mode=regen --only=autogen
-#include "sw/device/lib/dif/autogen/dif_ml_top_autogen.h"
#include <stdint.h>
+#include "sw/device/lib/dif/autogen/dif_ml_top_autogen.h"
+#include "sw/device/lib/dif/dif_base.h"
+
#include "ml_top_regs.h" // Generated.
OT_WARN_UNUSED_RESULT
@@ -22,10 +24,7 @@
}
/**
- * Get the corresponding interrupt register bit offset of the IRQ. If the IP's
- * HJSON does NOT have a field "no_auto_intr_regs = true", then the
- * "<ip>_INTR_COMMON_<irq>_BIT" macro can be used. Otherwise, special cases
- * will exist, as templated below.
+ * Get the corresponding interrupt register bit offset of the IRQ.
*/
static bool ml_top_get_irq_bit_index(dif_ml_top_irq_t irq,
bitfield_bit32_index_t *index_out) {
@@ -40,9 +39,6 @@
case kDifMlTopIrqFault:
*index_out = ML_TOP_INTR_COMMON_FAULT_BIT;
break;
- case kDifMlTopIrqDataFault:
- *index_out = ML_TOP_INTR_COMMON_DATA_FAULT_BIT;
- break;
default:
return false;
}
@@ -50,6 +46,26 @@
return true;
}
+static dif_irq_type_t irq_types[] = {
+ kDifIrqTypeEvent,
+ kDifIrqTypeEvent,
+ kDifIrqTypeEvent,
+};
+
+OT_WARN_UNUSED_RESULT
+dif_result_t dif_ml_top_irq_get_type(const dif_ml_top_t *ml_top,
+ dif_ml_top_irq_t irq,
+ dif_irq_type_t *type) {
+
+ if (ml_top == NULL || type == NULL || irq == kDifMlTopIrqFault + 1) {
+ return kDifBadArg;
+ }
+
+ *type = irq_types[irq];
+
+ return kDifOk;
+}
+
OT_WARN_UNUSED_RESULT
dif_result_t
dif_ml_top_irq_get_state(const dif_ml_top_t *ml_top,
@@ -66,6 +82,20 @@
}
OT_WARN_UNUSED_RESULT
+dif_result_t
+dif_ml_top_irq_acknowledge_state(const dif_ml_top_t *ml_top,
+ dif_ml_top_irq_state_snapshot_t snapshot) {
+ if (ml_top == NULL) {
+ return kDifBadArg;
+ }
+
+ mmio_region_write32(ml_top->base_addr, ML_TOP_INTR_STATE_REG_OFFSET,
+ snapshot);
+
+ return kDifOk;
+}
+
+OT_WARN_UNUSED_RESULT
dif_result_t dif_ml_top_irq_is_pending(const dif_ml_top_t *ml_top,
dif_ml_top_irq_t irq, bool *is_pending) {
@@ -123,7 +153,7 @@
OT_WARN_UNUSED_RESULT
dif_result_t dif_ml_top_irq_force(const dif_ml_top_t *ml_top,
- dif_ml_top_irq_t irq) {
+ dif_ml_top_irq_t irq, const bool val) {
if (ml_top == NULL) {
return kDifBadArg;
@@ -134,7 +164,7 @@
return kDifBadArg;
}
- uint32_t intr_test_reg = bitfield_bit32_write(0, index, true);
+ uint32_t intr_test_reg = bitfield_bit32_write(0, index, val);
mmio_region_write32(ml_top->base_addr, ML_TOP_INTR_TEST_REG_OFFSET,
intr_test_reg);
diff --git a/sw/device/lib/dif/autogen/dif_ml_top_autogen.h b/sw/device/lib/dif/autogen/dif_ml_top_autogen.h
index 3405d87..67cb51f 100644
--- a/sw/device/lib/dif/autogen/dif_ml_top_autogen.h
+++ b/sw/device/lib/dif/autogen/dif_ml_top_autogen.h
@@ -64,21 +64,30 @@
* Raised if kelvin report fault.
*/
kDifMlTopIrqFault = 2,
- /**
- * Raised if windowMMU data memory access faults(reserved)
- */
- kDifMlTopIrqDataFault = 3,
} dif_ml_top_irq_t;
/**
* A snapshot of the state of the interrupts for this IP.
*
* This is an opaque type, to be used with the `dif_ml_top_irq_get_state()`
- * function.
+ * and `dif_ml_top_irq_acknowledge_state()` functions.
*/
typedef uint32_t dif_ml_top_irq_state_snapshot_t;
/**
+ * Returns the type of a given interrupt (i.e., event or status) for this IP.
+ *
+ * @param ml_top A ml_top handle.
+ * @param irq An interrupt request.
+ * @param[out] type Out-param for the interrupt type.
+ * @return The result of the operation.
+ */
+OT_WARN_UNUSED_RESULT
+dif_result_t dif_ml_top_irq_get_type(const dif_ml_top_t *ml_top,
+ dif_ml_top_irq_t irq,
+ dif_irq_type_t *type);
+
+/**
* Returns the state of all interrupts (i.e., pending or not) for this IP.
*
* @param ml_top A ml_top handle.
@@ -103,6 +112,19 @@
dif_ml_top_irq_t irq, bool *is_pending);
/**
+ * Acknowledges all interrupts that were pending at the time of the state
+ * snapshot.
+ *
+ * @param ml_top A ml_top handle.
+ * @param snapshot Interrupt state snapshot.
+ * @return The result of the operation.
+ */
+OT_WARN_UNUSED_RESULT
+dif_result_t
+dif_ml_top_irq_acknowledge_state(const dif_ml_top_t *ml_top,
+ dif_ml_top_irq_state_snapshot_t snapshot);
+
+/**
* Acknowledges all interrupts, indicating to the hardware that all
* interrupts have been successfully serviced.
*
@@ -130,11 +152,12 @@
*
* @param ml_top A ml_top handle.
* @param irq An interrupt request.
+ * @param val Value to be set.
* @return The result of the operation.
*/
OT_WARN_UNUSED_RESULT
dif_result_t dif_ml_top_irq_force(const dif_ml_top_t *ml_top,
- dif_ml_top_irq_t irq);
+ dif_ml_top_irq_t irq, const bool val);
/**
* A snapshot of the enablement state of the interrupts for this IP.
diff --git a/sw/device/tests/smc/smc_ml_top_irq_test.c b/sw/device/tests/smc/smc_ml_top_irq_test.c
index 2e4249c..aec2694 100644
--- a/sw/device/tests/smc/smc_ml_top_irq_test.c
+++ b/sw/device/tests/smc/smc_ml_top_irq_test.c
@@ -128,7 +128,7 @@
static void execute_test() {
// Force ML_TOP finish interrupt.
ml_top_finish_handled = false;
- CHECK_DIF_OK(dif_ml_top_irq_force(&ml_top, kDifMlTopIrqFinish));
+ CHECK_DIF_OK(dif_ml_top_irq_force(&ml_top, kDifMlTopIrqFinish, true));
// Check if the IRQ has occured and has been handled appropriately.
if (!ml_top_finish_handled) {
busy_spin_micros(1000);
@@ -136,7 +136,7 @@
CHECK(ml_top_finish_handled, "ML_TOP finish IRQ has not been handled!");
ml_top_fault_handled = false;
- CHECK_DIF_OK(dif_ml_top_irq_force(&ml_top, kDifMlTopIrqFault));
+ CHECK_DIF_OK(dif_ml_top_irq_force(&ml_top, kDifMlTopIrqFault, true));
// Check if the IRQ has occured and has been handled appropriately.
if (!ml_top_fault_handled) {
busy_spin_micros(1000);
