soundstream: cleanups

With an updated toolchain we can eliminate the heap allocations:
- allocate the sample buffer in .bss
- allocate the sample filter buffers on the stack (sized at 4KiB)
- mark the soundstream compartment with CHERIOT_NO_AMBIENT_MALLOC
  now that we no longer use the heap
- replace the one use of CHECK with Debug::Assert

Bug: 330741645

Bypass-Presubmit-Reason: no sencha presubmit tests

Change-Id: I9b6df0a6cca5d12547610623ac0638636fd37ae1
2 files changed
tree: 1ceb814def102899f099ac202c7fd45d9e548de1
  1. doc/
  2. hw/
  3. platforms/
  4. rules/
  5. sw/
  6. third_party/
  7. toolchains/
  8. util/
  9. .bazelrc
  10. .bazelversion
  11. .gitignore
  12. BUILD.bazel
  13. CONTRIBUTING.md
  14. LICENSE
  15. PREUPLOAD.cfg
  16. README.md
  17. WORKSPACE
README.md

Matcha

About the project

Matcha is an open-source reference hardware implementation for Project Open Se Cura, a low-power, secure embedded platform for ambient ML applications.

About this repository

This repository contains hardware (RTL), software, and utilities written as part of the Matcha project.

Documentation

The project contains comprehensive documentation of the SOC, all IPs, and tools.

How to contribute

Have a look at our GettingStarted Guide for guidelines on how to contribute code to this repository.

Licensing

Unless otherwise noted, everything in this repository is covered by the Apache License, Version 2.0 (see LICENSE for full text).

Prerequisites

Development for matcha requires that the necessary tools and prerequisites be installed. See GettingStarted Guide

To setup the build system, run following steps at root of repo:

source build/setup.sh

Install the prerequisites:

m prereqs

Install the tools used for development:

m tools

Code/Repo Structure

<root_dir>/hw/matcha/
    hw/top_matcha/
        BUILD
        cdc/
        data/
        dv/
        formal/
        ip/
        ip_autogen/
        lint/
        rdc/
        rtl/
        sw/
        syn/
        util/
    hw/
        BUILD
        Makefile
    sw/
        BUILD
        device/
    util/
        BUILD
        dvsim_matcha/
        make_new_dif/
        openocd/
        topgen_util/
        topgen_matcha.py

<root_dir>/hw/opentitan_upstream/
<root_dir>/build/
<root_dir>/Manifest/
<root_dir>/Makefile
<root_dir>/GettingStarted.md
<toot_dir>/...

Quick start guide and cheat sheet

For following steps, make sure the above “Prerequisites” steps have been run if the repo is been checked out at the first time.

Build RTL top Level and generate registers, interrupt and address map:

m matcha_hw_generate_all

Build verilator simulation target:

m matcha_hw_verilator_sim

Run matcha verilator test suite

m matcha_hw_verilator_tests

Run FPGA compilation flow for Nexus FPGA board:

m matcha_hw_fpga_nexus

Bazel debug

Run matcha single test with messages to stdout

bazel test --test_output=streamed //sw/device/tests:verilator_mailbox_test

Run matcha test suites

bazel test --test_output=streamed //sw/device/tests:verilator_test_suite

Run FPGA compilation flow for Nexus FPGA board with debug commands:

bazel build -s //hw/bitstream/vivado:fpga_nexus

Simulation logs

Enable tracing on a single test

bazel test --test_output=streamed  --test_timeout=1000000 --test_arg=--trace //sw/device/tests:verilator_cam_ctrl_test

Note: --test_timeout=1000000 sets timeout in seconds. This helps prevent timeout issues then using trace.

Waveform dump and peripheral logs for a test located in:

<root_dir>/hw/matcha/bazel-testlogs/sw/device/tests/<test_name>/test.outputs/output.zip
    sim.fst (if tracing is enabled)
    uart0.log
    smc_uart.log
    spi0.log
    usb0.log

Note: The trace_core_#.log files available in output.zip is currently a TODO item.

The FPGA compiled bitstream and reports (resource utilization, pin assignment, etc) can be found in following directory:

<matcha_root_dir>/bazel-bin/hw/bitstream/vivado/build.fpga_nexus/synth-vivado/google_systems_chip_matcha_nexus_0.1.runs/impl_1/chip_matcha_nexus.bit <matcha_root_dir>/bazel-bin/hw/bitstream/vivado/build.fpga_nexus/synth-vivado/google_systems_chip_matcha_nexus_0.1.runs/impl_1/.rpt <matcha_root_dir>/bazel-bin/hw/bitstream/vivado/build.fpga_nexus/synth-vivado/google_systems_chip_matcha_nexus_0.1.runs/synth_1/.rpt

DV flow

Setup DV flow