Update ml_top for new Kelvin signal naming
- A change in @hw_kelvin converts the memory interface into a Bundle,
which changes the names in the output Verilog. Update our
instantiation of Kelvin in ml_top to accomodate.
Change-Id: Ic97d52da9c5218a5e27fac9e925f6c4da488e696
diff --git a/hw/top_matcha/ip/ml_top/rtl/ml_top.sv b/hw/top_matcha/ip/ml_top/rtl/ml_top.sv
index b70bc3f..cb34bd0 100644
--- a/hw/top_matcha/ip/ml_top/rtl/ml_top.sv
+++ b/hw/top_matcha/ip/ml_top/rtl/ml_top.sv
@@ -136,16 +136,16 @@
.volt_sel (ctrl.volt_sel), // Default 0 for 0.8V memory macros, write 1 for 0.65V.
// SRAM Interface
- .cvalid (core0_cvalid),
- .cready (core0_cready),
- .cwrite (core0_cwrite),
- .caddr (core0_caddr),
- .cid (core0_cid[6:0]),
- .wdata (core0_wdata),
- .wmask (core0_wmask),
- .rvalid (core0_rvalid),
- .rid (core0_rid[6:0]),
- .rdata (core0_rdata),
+ .mem_cvalid (core0_cvalid),
+ .mem_cready (core0_cready),
+ .mem_cwrite (core0_cwrite),
+ .mem_caddr (core0_caddr),
+ .mem_cid (core0_cid[6:0]),
+ .mem_wdata (core0_wdata),
+ .mem_wmask (core0_wmask),
+ .mem_rvalid (core0_rvalid),
+ .mem_rid (core0_rid[6:0]),
+ .mem_rdata (core0_rdata),
.slog_valid (),
.slog_addr (),
