// Copyright 2022 Google LLC.
// Copyright lowRISC contributors.
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0

#include "hw/top_matcha/sw/autogen/top_matcha.h"
#include "sw/device/lib/arch/device.h"
#include "sw/device/lib/dif/dif_rv_plic.h"
#include "sw/device/lib/dif/dif_smc_ctrl.h"
#include "sw/device/lib/dif/dif_tlul_mailbox.h"
#include "sw/device/lib/dif/dif_uart.h"
#include "sw/device/lib/runtime/hart.h"
#include "sw/device/lib/runtime/log.h"
#include "sw/device/lib/runtime/print.h"
#include "sw/device/lib/testing/test_framework/check.h"
#include "sw/device/lib/testing/test_framework/ottf_test_config.h"
#include "sw/device/lib/testing/test_framework/status.h"
#include "sw/device/lib/testing/test_framework/test_util.h"

OTTF_DEFINE_TEST_CONFIG();

static dif_uart_t uart;
static dif_tlul_mailbox_t tlul_mailbox;
static dif_smc_ctrl_t smc_ctrl;
static dif_rv_plic_t plic_sec;

void ottf_external_isr(void) {
  uint32_t rx;
  dif_rv_plic_irq_id_t plic_irq_id;

  LOG_INFO("Woken!");

  // Clear IRQ from the tlul_mailbox and claim it IRQ from the PLIC.
  CHECK_DIF_OK(
      dif_tlul_mailbox_irq_acknowledge(&tlul_mailbox, kDifTlulMailboxIrqRtirq));
  CHECK_DIF_OK(dif_rv_plic_irq_claim(&plic_sec, kTopMatchaPlicTargetIbex0,
                                     &plic_irq_id));

  CHECK_DIF_OK(dif_tlul_mailbox_read_message(&tlul_mailbox, &rx));
  LOG_INFO("Message: %x", rx);
  CHECK(rx == 0xBEEFB0BA,
        "Message from SMC incorrect - expected: 0xBEEFB0BA | actual: %x", rx);

  CHECK_DIF_OK(dif_rv_plic_irq_complete(&plic_sec, kTopMatchaPlicTargetIbex0,
                                        plic_irq_id));

  // End the test in the ISR since we return to wfi afterwards.
  test_status_set(kTestStatusPassed);
}

void _ottf_main(void) {
  // Initialize the UART to enable logging for non-DV simulation platforms.
  if (kDeviceType != kDeviceSimDV) {
    init_uart(TOP_MATCHA_UART0_BASE_ADDR, &uart);
  }

  LOG_INFO("Hello Shodan!");

  test_status_set(kTestStatusInTest);

  uint32_t buf1 = 0xCAFEB0BA;
  uint32_t buf2 = 0xDEADBEEF;

  CHECK_DIF_OK(dif_tlul_mailbox_init(
      mmio_region_from_addr(TOP_MATCHA_TLUL_MAILBOX_SEC_BASE_ADDR),
      &tlul_mailbox));
  CHECK_DIF_OK(dif_tlul_mailbox_irq_set_enabled(
      &tlul_mailbox, kDifTlulMailboxIrqRtirq, kDifToggleEnabled));
  CHECK_DIF_OK(dif_tlul_mailbox_irq_set_enabled(
      &tlul_mailbox, kDifTlulMailboxIrqWtirq, kDifToggleEnabled));
  CHECK_DIF_OK(dif_tlul_mailbox_irq_set_enabled(
      &tlul_mailbox, kDifTlulMailboxIrqEirq, kDifToggleEnabled));

  CHECK_DIF_OK(dif_smc_ctrl_init(
      mmio_region_from_addr(TOP_MATCHA_SMC_CTRL_BASE_ADDR), &smc_ctrl));

  CHECK_DIF_OK(dif_smc_ctrl_set_en(&smc_ctrl));
  LOG_INFO("Set SMC CTRL_EN.");

  CHECK_DIF_OK(dif_rv_plic_init(
      mmio_region_from_addr(TOP_MATCHA_RV_PLIC_BASE_ADDR), &plic_sec));
  CHECK_DIF_OK(dif_rv_plic_irq_set_enabled(
      &plic_sec, kTopMatchaPlicIrqIdTlulMailboxSecRtirq,
      kTopMatchaPlicTargetIbex0, kDifToggleEnabled));
  CHECK_DIF_OK(dif_rv_plic_irq_set_priority(
      &plic_sec, kTopMatchaPlicIrqIdTlulMailboxSecRtirq, 1));

  LOG_INFO("Sending...");
  CHECK_DIF_OK(dif_tlul_mailbox_send_message(&tlul_mailbox, &buf1));
  CHECK_DIF_OK(dif_tlul_mailbox_send_message(&tlul_mailbox, &buf2));

  LOG_INFO("Enable interrupts and sleep.");
  asm volatile("csrs mstatus, %0\n" : : "r"(0x8));
  asm volatile("csrs mie, %0\n" : : "r"(0x800));

  asm volatile("wfi");
}