// Copyright lowRISC contributors.
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0

#include "hw/top_matcha/sw/autogen/top_matcha.h"
#include "sw/device/lib/arch/device.h"
#include "sw/device/lib/dif/dif_uart.h"
#include "sw/device/lib/runtime/hart.h"
#include "sw/device/lib/runtime/log.h"
#include "sw/device/lib/runtime/print.h"
#include "sw/device/lib/testing/test_framework/check.h"
#include "sw/device/lib/testing/test_framework/ottf_test_config.h"
#include "sw/device/lib/testing/test_framework/status.h"
#include "sw/device/lib/testing/test_framework/test_util.h"

OTTF_DEFINE_TEST_CONFIG();

static dif_uart_t uart;

void _ottf_main(void) {
  uint32_t mem_val;

  // Initialize the UART to enable logging for non-DV simulation platforms.
  if (kDeviceType != kDeviceSimDV) {
    init_uart(TOP_MATCHA_UART0_BASE_ADDR, &uart);
  }
  LOG_INFO("Hello Shodan! Let's do memory test!");

  // Start testing SMC SRAM
  test_status_set(kTestStatusInTest);

  mmio_region_t base_addr = mmio_region_from_addr(TOP_MATCHA_RAM_SMC_BASE_ADDR);

  mmio_region_write32(base_addr, 0x0, 0x55aa55aa);
  mem_val = mmio_region_read32(base_addr, 0x0);
  CHECK(mem_val == 0x55aa55aa,
        "ram_smc read out: expected : 0x55aa55aa | actual: %x", mem_val);

  mmio_region_write32(base_addr, 0x4, 0x12345678);
  mem_val = mmio_region_read32(base_addr, 0x4);
  CHECK(mem_val == 0x12345678,
        "ram_smc read out: expected : 0x12345678 | actual: %x", mem_val);

  mmio_region_write32(base_addr, (TOP_MATCHA_RAM_SMC_SIZE_BYTES - 4),
                      0xaa55aa55);
  mem_val = mmio_region_read32(base_addr, (TOP_MATCHA_RAM_SMC_SIZE_BYTES - 4));
  CHECK(mem_val == 0xaa55aa55,
        "ram_smc read out: expected : 0xaa55aa55 | actual: %x", mem_val);

  // Start testing ML_TOP_DMEM
  mmio_region_t ml_dmem_base_addr =
      mmio_region_from_addr(TOP_MATCHA_ML_TOP_DMEM_BASE_ADDR);

  mmio_region_write32(ml_dmem_base_addr, 0x0, 0x55aa55aa);
  mmio_region_write32(ml_dmem_base_addr, 0x4, 0x12345678);
  mmio_region_write32(ml_dmem_base_addr, 0x8, 0x55aa55aa);
  mmio_region_write32(ml_dmem_base_addr, 0xc, 0x12345678);
  mmio_region_write32(ml_dmem_base_addr, 0x10, 0x55aa55aa);
  mmio_region_write32(ml_dmem_base_addr, 0x14, 0x12345678);
  mmio_region_write32(ml_dmem_base_addr, 0x18, 0x55aa55aa);
  mmio_region_write32(ml_dmem_base_addr, 0x1c, 0x12345678);
  mmio_region_write32(ml_dmem_base_addr, 0x20, 0x55aa55aa);
  mmio_region_write32(ml_dmem_base_addr, 0x2c, 0x12345678);

  mem_val = mmio_region_read32(ml_dmem_base_addr, 0x0);
  CHECK(mem_val == 0x55aa55aa,
        "ml_dmem read out: expected : 0x55aa55aa | actual: %x", mem_val);

  mem_val = mmio_region_read32(ml_dmem_base_addr, 0x4);
  CHECK(mem_val == 0x12345678,
        "ml_dmem read out: expected : 0x12345678 | actual: %x", mem_val);

  mem_val = mmio_region_read32(ml_dmem_base_addr, 0x8);
  CHECK(mem_val == 0x55aa55aa,
        "ml_dmem read out: expected : 0x55aa55aa | actual: %x", mem_val);

  mem_val = mmio_region_read32(ml_dmem_base_addr, 0xc);
  CHECK(mem_val == 0x12345678,
        "ml_dmem read out: expected : 0x12345678 | actual: %x", mem_val);

  mem_val = mmio_region_read32(ml_dmem_base_addr, 0x10);
  CHECK(mem_val == 0x55aa55aa,
        "ml_dmem read out: expected : 0x55aa55aa | actual: %x", mem_val);

  mem_val = mmio_region_read32(ml_dmem_base_addr, 0x14);
  CHECK(mem_val == 0x12345678,
        "ml_dmem read out: expected : 0x12345678 | actual: %x", mem_val);

  mem_val = mmio_region_read32(ml_dmem_base_addr, 0x18);
  CHECK(mem_val == 0x55aa55aa,
        "ml_dmem read out: expected : 0x55aa55aa | actual: %x", mem_val);

  mem_val = mmio_region_read32(ml_dmem_base_addr, 0x1c);
  CHECK(mem_val == 0x12345678,
        "ml_dmem read out: expected : 0x12345678 | actual: %x", mem_val);

  mem_val = mmio_region_read32(ml_dmem_base_addr, 0x20);
  CHECK(mem_val == 0x55aa55aa,
        "ml_dmem read out: expected : 0x12345678 | actual: %x", mem_val);

  mem_val = mmio_region_read32(ml_dmem_base_addr, 0x2c);
  CHECK(mem_val == 0x12345678,
        "ml_dmem read out: expected : 0x12345678 | actual: %x", mem_val);

  mmio_region_write32(ml_dmem_base_addr,
                      (TOP_MATCHA_ML_TOP_DMEM_SIZE_BYTES - 32), 0xaa55aa55);
  mem_val = mmio_region_read32(ml_dmem_base_addr,
                               (TOP_MATCHA_ML_TOP_DMEM_SIZE_BYTES - 32));
  CHECK(mem_val == 0xaa55aa55,
        "ml_dmem read out: expected : 0xaa55aa55 | actual: %x", mem_val);

  mmio_region_write32(ml_dmem_base_addr,
                      (TOP_MATCHA_ML_TOP_DMEM_SIZE_BYTES - 4), 0x12345678);
  mem_val = mmio_region_read32(ml_dmem_base_addr,
                               (TOP_MATCHA_ML_TOP_DMEM_SIZE_BYTES - 4));
  CHECK(mem_val == 0x12345678,
        "ml_dmem read out: expected : 0xaa55aa55 | actual: %x", mem_val);

  mmio_region_write32(ml_dmem_base_addr, 0x0, 0x55aa55aa);
  mmio_region_write32(ml_dmem_base_addr, 0x100000, 0x12345678);
  mmio_region_write32(ml_dmem_base_addr, 0x200000, 0xaa55aa55);
  mmio_region_write32(ml_dmem_base_addr, 0x300000, 0x87654321);

  mem_val = mmio_region_read32(ml_dmem_base_addr, 0x0);
  CHECK(mem_val == 0x55aa55aa,
        "ml_dmem read out: expected : 0x55aa55aa | actual: %x", mem_val);

  mem_val = mmio_region_read32(ml_dmem_base_addr, 0x100000);
  CHECK(mem_val == 0x12345678,
        "ml_dmem read out: expected : 0x12345678 | actual: %x", mem_val);

  mem_val = mmio_region_read32(ml_dmem_base_addr, 0x200000);
  CHECK(mem_val == 0xaa55aa55,
        "ml_dmem read out: expected : 0xaa55aa55 | actual: %x", mem_val);

  mem_val = mmio_region_read32(ml_dmem_base_addr, 0x300000);
  CHECK(mem_val == 0x87654321,
        "ml_dmem read out: expected : 0x87654321 | actual: %x", mem_val);

  test_status_set(kTestStatusPassed);
}