diff --git a/hw/bitstream/vivado/BUILD b/hw/bitstream/vivado/BUILD
index 50936ff..5da3217 100644
--- a/hw/bitstream/vivado/BUILD
+++ b/hw/bitstream/vivado/BUILD
@@ -91,7 +91,7 @@
     name = "otp_mmi",
     testonly = True,
     srcs = [":fpga_nexus"],
-    output_group = "opt_mmi",
+    output_group = "otp_mmi",
     tags = ["manual"],
 )
 
diff --git a/hw/top_matcha/dv/chip_sim_cfg.hjson b/hw/top_matcha/dv/chip_sim_cfg.hjson
index 7cec294..3a4964e 100644
--- a/hw/top_matcha/dv/chip_sim_cfg.hjson
+++ b/hw/top_matcha/dv/chip_sim_cfg.hjson
@@ -2086,6 +2086,7 @@
         "chip_sw_pwrmgr_deep_sleep_power_glitch_reset",
         "chip_sw_pwrmgr_normal_sleep_all_wake_ups"
         "chip_sw_pwrmgr_sleep_power_glitch_reset",
+        "chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup",
         "chip_sw_rom_ctrl_integrity_check",
         "chip_sw_rstmgr_smoketest",
         "chip_sw_rstmgr_sw_req",
diff --git a/hw/top_matcha/ip/i2s/rtl/i2s_rx.sv b/hw/top_matcha/ip/i2s/rtl/i2s_rx.sv
index 74ad7a3..d62b762 100644
--- a/hw/top_matcha/ip/i2s/rtl/i2s_rx.sv
+++ b/hw/top_matcha/ip/i2s/rtl/i2s_rx.sv
@@ -88,12 +88,13 @@
     end
   end
 
-  // Bits were clocked on the line falling edge of clock. Latch data in on rising.
+  // Clock in  data in on rising edge.
   always_ff @(posedge sclk_o or negedge rst_ni) begin
     if (!rst_ni) begin
       shift_reg <= '0;
+    end else begin
+      shift_reg <= {shift_reg[WordWidth-2:0], serial_data_i};
     end
-    shift_reg <= {shift_reg[WordWidth-2:0], serial_data_i};
   end
 
 endmodule
diff --git a/hw/top_matcha/ip/ml_top/rtl/kelvin.v b/hw/top_matcha/ip/ml_top/rtl/kelvin.v
index e9ef1b2..9518e6c 100644
--- a/hw/top_matcha/ip/ml_top/rtl/kelvin.v
+++ b/hw/top_matcha/ip/ml_top/rtl/kelvin.v
@@ -1,4 +1,4 @@
-// SHA: fb78d8ccc36939bd88c4d4f55185d283831d14a6
+// SHA: 55e14cfc9047c4e5432d0e3af7ab30e76857d1a1
 module Regfile(
   input         clock,
   input         reset,
@@ -103,6 +103,7 @@
   input         io_writeMask_1_valid,
   input         io_writeMask_2_valid,
   input         io_writeMask_3_valid,
+  input         io_writeMask_4_valid,
   output [31:0] io_scoreboard_regd,
   output [31:0] io_scoreboard_comb
 );
@@ -254,27 +255,28 @@
   reg [31:0] readDataBits_6; // @[Regfile.scala 124:26]
   reg [31:0] readDataBits_7; // @[Regfile.scala 124:26]
   wire  _valid_T_1 = io_writeData_5_valid & io_writeData_5_addr == 5'h1; // @[Regfile.scala 142:43]
-  wire  _valid_T_3 = io_writeData_4_valid & io_writeData_4_addr == 5'h1; // @[Regfile.scala 143:43]
-  wire  _valid_T_6 = ~io_writeMask_3_valid; // @[Regfile.scala 145:23]
-  wire  _valid_T_7 = io_writeData_3_valid & io_writeData_3_addr == 5'h1 & _valid_T_6; // @[Regfile.scala 144:75]
-  wire  _valid_T_10 = ~io_writeMask_2_valid; // @[Regfile.scala 147:23]
-  wire  _valid_T_11 = io_writeData_2_valid & io_writeData_2_addr == 5'h1 & _valid_T_10; // @[Regfile.scala 146:75]
-  wire  _valid_T_14 = ~io_writeMask_1_valid; // @[Regfile.scala 149:23]
-  wire  _valid_T_15 = io_writeData_1_valid & io_writeData_1_addr == 5'h1 & _valid_T_14; // @[Regfile.scala 148:75]
-  wire  _valid_T_17 = io_writeData_0_valid & io_writeData_0_addr == 5'h1; // @[Regfile.scala 150:43]
-  wire [5:0] valid = {_valid_T_1,_valid_T_3,_valid_T_7,_valid_T_11,_valid_T_15,_valid_T_17}; // @[Cat.scala 31:58]
+  wire  _valid_T_4 = ~io_writeMask_4_valid; // @[Regfile.scala 144:23]
+  wire  _valid_T_5 = io_writeData_4_valid & io_writeData_4_addr == 5'h1 & _valid_T_4; // @[Regfile.scala 143:75]
+  wire  _valid_T_8 = ~io_writeMask_3_valid; // @[Regfile.scala 146:23]
+  wire  _valid_T_9 = io_writeData_3_valid & io_writeData_3_addr == 5'h1 & _valid_T_8; // @[Regfile.scala 145:75]
+  wire  _valid_T_12 = ~io_writeMask_2_valid; // @[Regfile.scala 148:23]
+  wire  _valid_T_13 = io_writeData_2_valid & io_writeData_2_addr == 5'h1 & _valid_T_12; // @[Regfile.scala 147:75]
+  wire  _valid_T_16 = ~io_writeMask_1_valid; // @[Regfile.scala 150:23]
+  wire  _valid_T_17 = io_writeData_1_valid & io_writeData_1_addr == 5'h1 & _valid_T_16; // @[Regfile.scala 149:75]
+  wire  _valid_T_19 = io_writeData_0_valid & io_writeData_0_addr == 5'h1; // @[Regfile.scala 151:43]
+  wire [5:0] valid = {_valid_T_1,_valid_T_5,_valid_T_9,_valid_T_13,_valid_T_17,_valid_T_19}; // @[Cat.scala 31:58]
   wire [31:0] _data_T_1 = valid[0] ? io_writeData_0_data : 32'h0; // @[Library.scala 8:8]
   wire [31:0] _data_T_3 = valid[1] ? io_writeData_1_data : 32'h0; // @[Library.scala 8:8]
-  wire [31:0] _data_T_4 = _data_T_1 | _data_T_3; // @[Regfile.scala 153:55]
+  wire [31:0] _data_T_4 = _data_T_1 | _data_T_3; // @[Regfile.scala 154:55]
   wire [31:0] _data_T_6 = valid[2] ? io_writeData_2_data : 32'h0; // @[Library.scala 8:8]
-  wire [31:0] _data_T_7 = _data_T_4 | _data_T_6; // @[Regfile.scala 154:55]
+  wire [31:0] _data_T_7 = _data_T_4 | _data_T_6; // @[Regfile.scala 155:55]
   wire [31:0] _data_T_9 = valid[3] ? io_writeData_3_data : 32'h0; // @[Library.scala 8:8]
-  wire [31:0] _data_T_10 = _data_T_7 | _data_T_9; // @[Regfile.scala 155:55]
+  wire [31:0] _data_T_10 = _data_T_7 | _data_T_9; // @[Regfile.scala 156:55]
   wire [31:0] _data_T_12 = valid[4] ? io_writeData_4_data : 32'h0; // @[Library.scala 8:8]
-  wire [31:0] _data_T_13 = _data_T_10 | _data_T_12; // @[Regfile.scala 156:55]
+  wire [31:0] _data_T_13 = _data_T_10 | _data_T_12; // @[Regfile.scala 157:55]
   wire [31:0] _data_T_15 = valid[5] ? io_writeData_5_data : 32'h0; // @[Library.scala 8:8]
-  wire [31:0] data = _data_T_13 | _data_T_15; // @[Regfile.scala 157:55]
-  wire  writeValid_1 = valid != 6'h0; // @[Regfile.scala 160:28]
+  wire [31:0] data = _data_T_13 | _data_T_15; // @[Regfile.scala 158:55]
+  wire  writeValid_1 = valid != 6'h0; // @[Regfile.scala 161:28]
   wire [1:0] _T_9 = valid[1] + valid[2]; // @[Bitwise.scala 48:55]
   wire [1:0] _GEN_41 = {{1'd0}, valid[0]}; // @[Bitwise.scala 48:55]
   wire [2:0] _T_11 = _GEN_41 + _T_9; // @[Bitwise.scala 48:55]
@@ -282,26 +284,26 @@
   wire [1:0] _GEN_42 = {{1'd0}, valid[3]}; // @[Bitwise.scala 48:55]
   wire [2:0] _T_15 = _GEN_42 + _T_13; // @[Bitwise.scala 48:55]
   wire [2:0] _T_17 = _T_11[1:0] + _T_15[1:0]; // @[Bitwise.scala 48:55]
-  wire  _T_21 = ~reset; // @[Regfile.scala 163:11]
-  wire  _valid_T_21 = io_writeData_5_valid & io_writeData_5_addr == 5'h2; // @[Regfile.scala 142:43]
-  wire  _valid_T_23 = io_writeData_4_valid & io_writeData_4_addr == 5'h2; // @[Regfile.scala 143:43]
-  wire  _valid_T_27 = io_writeData_3_valid & io_writeData_3_addr == 5'h2 & _valid_T_6; // @[Regfile.scala 144:75]
-  wire  _valid_T_31 = io_writeData_2_valid & io_writeData_2_addr == 5'h2 & _valid_T_10; // @[Regfile.scala 146:75]
-  wire  _valid_T_35 = io_writeData_1_valid & io_writeData_1_addr == 5'h2 & _valid_T_14; // @[Regfile.scala 148:75]
-  wire  _valid_T_37 = io_writeData_0_valid & io_writeData_0_addr == 5'h2; // @[Regfile.scala 150:43]
-  wire [5:0] valid_1 = {_valid_T_21,_valid_T_23,_valid_T_27,_valid_T_31,_valid_T_35,_valid_T_37}; // @[Cat.scala 31:58]
+  wire  _T_21 = ~reset; // @[Regfile.scala 164:11]
+  wire  _valid_T_23 = io_writeData_5_valid & io_writeData_5_addr == 5'h2; // @[Regfile.scala 142:43]
+  wire  _valid_T_27 = io_writeData_4_valid & io_writeData_4_addr == 5'h2 & _valid_T_4; // @[Regfile.scala 143:75]
+  wire  _valid_T_31 = io_writeData_3_valid & io_writeData_3_addr == 5'h2 & _valid_T_8; // @[Regfile.scala 145:75]
+  wire  _valid_T_35 = io_writeData_2_valid & io_writeData_2_addr == 5'h2 & _valid_T_12; // @[Regfile.scala 147:75]
+  wire  _valid_T_39 = io_writeData_1_valid & io_writeData_1_addr == 5'h2 & _valid_T_16; // @[Regfile.scala 149:75]
+  wire  _valid_T_41 = io_writeData_0_valid & io_writeData_0_addr == 5'h2; // @[Regfile.scala 151:43]
+  wire [5:0] valid_1 = {_valid_T_23,_valid_T_27,_valid_T_31,_valid_T_35,_valid_T_39,_valid_T_41}; // @[Cat.scala 31:58]
   wire [31:0] _data_T_17 = valid_1[0] ? io_writeData_0_data : 32'h0; // @[Library.scala 8:8]
   wire [31:0] _data_T_19 = valid_1[1] ? io_writeData_1_data : 32'h0; // @[Library.scala 8:8]
-  wire [31:0] _data_T_20 = _data_T_17 | _data_T_19; // @[Regfile.scala 153:55]
+  wire [31:0] _data_T_20 = _data_T_17 | _data_T_19; // @[Regfile.scala 154:55]
   wire [31:0] _data_T_22 = valid_1[2] ? io_writeData_2_data : 32'h0; // @[Library.scala 8:8]
-  wire [31:0] _data_T_23 = _data_T_20 | _data_T_22; // @[Regfile.scala 154:55]
+  wire [31:0] _data_T_23 = _data_T_20 | _data_T_22; // @[Regfile.scala 155:55]
   wire [31:0] _data_T_25 = valid_1[3] ? io_writeData_3_data : 32'h0; // @[Library.scala 8:8]
-  wire [31:0] _data_T_26 = _data_T_23 | _data_T_25; // @[Regfile.scala 155:55]
+  wire [31:0] _data_T_26 = _data_T_23 | _data_T_25; // @[Regfile.scala 156:55]
   wire [31:0] _data_T_28 = valid_1[4] ? io_writeData_4_data : 32'h0; // @[Library.scala 8:8]
-  wire [31:0] _data_T_29 = _data_T_26 | _data_T_28; // @[Regfile.scala 156:55]
+  wire [31:0] _data_T_29 = _data_T_26 | _data_T_28; // @[Regfile.scala 157:55]
   wire [31:0] _data_T_31 = valid_1[5] ? io_writeData_5_data : 32'h0; // @[Library.scala 8:8]
-  wire [31:0] data_1 = _data_T_29 | _data_T_31; // @[Regfile.scala 157:55]
-  wire  writeValid_2 = valid_1 != 6'h0; // @[Regfile.scala 160:28]
+  wire [31:0] data_1 = _data_T_29 | _data_T_31; // @[Regfile.scala 158:55]
+  wire  writeValid_2 = valid_1 != 6'h0; // @[Regfile.scala 161:28]
   wire [1:0] _T_29 = valid_1[1] + valid_1[2]; // @[Bitwise.scala 48:55]
   wire [1:0] _GEN_43 = {{1'd0}, valid_1[0]}; // @[Bitwise.scala 48:55]
   wire [2:0] _T_31 = _GEN_43 + _T_29; // @[Bitwise.scala 48:55]
@@ -309,25 +311,25 @@
   wire [1:0] _GEN_44 = {{1'd0}, valid_1[3]}; // @[Bitwise.scala 48:55]
   wire [2:0] _T_35 = _GEN_44 + _T_33; // @[Bitwise.scala 48:55]
   wire [2:0] _T_37 = _T_31[1:0] + _T_35[1:0]; // @[Bitwise.scala 48:55]
-  wire  _valid_T_41 = io_writeData_5_valid & io_writeData_5_addr == 5'h3; // @[Regfile.scala 142:43]
-  wire  _valid_T_43 = io_writeData_4_valid & io_writeData_4_addr == 5'h3; // @[Regfile.scala 143:43]
-  wire  _valid_T_47 = io_writeData_3_valid & io_writeData_3_addr == 5'h3 & _valid_T_6; // @[Regfile.scala 144:75]
-  wire  _valid_T_51 = io_writeData_2_valid & io_writeData_2_addr == 5'h3 & _valid_T_10; // @[Regfile.scala 146:75]
-  wire  _valid_T_55 = io_writeData_1_valid & io_writeData_1_addr == 5'h3 & _valid_T_14; // @[Regfile.scala 148:75]
-  wire  _valid_T_57 = io_writeData_0_valid & io_writeData_0_addr == 5'h3; // @[Regfile.scala 150:43]
-  wire [5:0] valid_2 = {_valid_T_41,_valid_T_43,_valid_T_47,_valid_T_51,_valid_T_55,_valid_T_57}; // @[Cat.scala 31:58]
+  wire  _valid_T_45 = io_writeData_5_valid & io_writeData_5_addr == 5'h3; // @[Regfile.scala 142:43]
+  wire  _valid_T_49 = io_writeData_4_valid & io_writeData_4_addr == 5'h3 & _valid_T_4; // @[Regfile.scala 143:75]
+  wire  _valid_T_53 = io_writeData_3_valid & io_writeData_3_addr == 5'h3 & _valid_T_8; // @[Regfile.scala 145:75]
+  wire  _valid_T_57 = io_writeData_2_valid & io_writeData_2_addr == 5'h3 & _valid_T_12; // @[Regfile.scala 147:75]
+  wire  _valid_T_61 = io_writeData_1_valid & io_writeData_1_addr == 5'h3 & _valid_T_16; // @[Regfile.scala 149:75]
+  wire  _valid_T_63 = io_writeData_0_valid & io_writeData_0_addr == 5'h3; // @[Regfile.scala 151:43]
+  wire [5:0] valid_2 = {_valid_T_45,_valid_T_49,_valid_T_53,_valid_T_57,_valid_T_61,_valid_T_63}; // @[Cat.scala 31:58]
   wire [31:0] _data_T_33 = valid_2[0] ? io_writeData_0_data : 32'h0; // @[Library.scala 8:8]
   wire [31:0] _data_T_35 = valid_2[1] ? io_writeData_1_data : 32'h0; // @[Library.scala 8:8]
-  wire [31:0] _data_T_36 = _data_T_33 | _data_T_35; // @[Regfile.scala 153:55]
+  wire [31:0] _data_T_36 = _data_T_33 | _data_T_35; // @[Regfile.scala 154:55]
   wire [31:0] _data_T_38 = valid_2[2] ? io_writeData_2_data : 32'h0; // @[Library.scala 8:8]
-  wire [31:0] _data_T_39 = _data_T_36 | _data_T_38; // @[Regfile.scala 154:55]
+  wire [31:0] _data_T_39 = _data_T_36 | _data_T_38; // @[Regfile.scala 155:55]
   wire [31:0] _data_T_41 = valid_2[3] ? io_writeData_3_data : 32'h0; // @[Library.scala 8:8]
-  wire [31:0] _data_T_42 = _data_T_39 | _data_T_41; // @[Regfile.scala 155:55]
+  wire [31:0] _data_T_42 = _data_T_39 | _data_T_41; // @[Regfile.scala 156:55]
   wire [31:0] _data_T_44 = valid_2[4] ? io_writeData_4_data : 32'h0; // @[Library.scala 8:8]
-  wire [31:0] _data_T_45 = _data_T_42 | _data_T_44; // @[Regfile.scala 156:55]
+  wire [31:0] _data_T_45 = _data_T_42 | _data_T_44; // @[Regfile.scala 157:55]
   wire [31:0] _data_T_47 = valid_2[5] ? io_writeData_5_data : 32'h0; // @[Library.scala 8:8]
-  wire [31:0] data_2 = _data_T_45 | _data_T_47; // @[Regfile.scala 157:55]
-  wire  writeValid_3 = valid_2 != 6'h0; // @[Regfile.scala 160:28]
+  wire [31:0] data_2 = _data_T_45 | _data_T_47; // @[Regfile.scala 158:55]
+  wire  writeValid_3 = valid_2 != 6'h0; // @[Regfile.scala 161:28]
   wire [1:0] _T_49 = valid_2[1] + valid_2[2]; // @[Bitwise.scala 48:55]
   wire [1:0] _GEN_45 = {{1'd0}, valid_2[0]}; // @[Bitwise.scala 48:55]
   wire [2:0] _T_51 = _GEN_45 + _T_49; // @[Bitwise.scala 48:55]
@@ -335,25 +337,25 @@
   wire [1:0] _GEN_46 = {{1'd0}, valid_2[3]}; // @[Bitwise.scala 48:55]
   wire [2:0] _T_55 = _GEN_46 + _T_53; // @[Bitwise.scala 48:55]
   wire [2:0] _T_57 = _T_51[1:0] + _T_55[1:0]; // @[Bitwise.scala 48:55]
-  wire  _valid_T_61 = io_writeData_5_valid & io_writeData_5_addr == 5'h4; // @[Regfile.scala 142:43]
-  wire  _valid_T_63 = io_writeData_4_valid & io_writeData_4_addr == 5'h4; // @[Regfile.scala 143:43]
-  wire  _valid_T_67 = io_writeData_3_valid & io_writeData_3_addr == 5'h4 & _valid_T_6; // @[Regfile.scala 144:75]
-  wire  _valid_T_71 = io_writeData_2_valid & io_writeData_2_addr == 5'h4 & _valid_T_10; // @[Regfile.scala 146:75]
-  wire  _valid_T_75 = io_writeData_1_valid & io_writeData_1_addr == 5'h4 & _valid_T_14; // @[Regfile.scala 148:75]
-  wire  _valid_T_77 = io_writeData_0_valid & io_writeData_0_addr == 5'h4; // @[Regfile.scala 150:43]
-  wire [5:0] valid_3 = {_valid_T_61,_valid_T_63,_valid_T_67,_valid_T_71,_valid_T_75,_valid_T_77}; // @[Cat.scala 31:58]
+  wire  _valid_T_67 = io_writeData_5_valid & io_writeData_5_addr == 5'h4; // @[Regfile.scala 142:43]
+  wire  _valid_T_71 = io_writeData_4_valid & io_writeData_4_addr == 5'h4 & _valid_T_4; // @[Regfile.scala 143:75]
+  wire  _valid_T_75 = io_writeData_3_valid & io_writeData_3_addr == 5'h4 & _valid_T_8; // @[Regfile.scala 145:75]
+  wire  _valid_T_79 = io_writeData_2_valid & io_writeData_2_addr == 5'h4 & _valid_T_12; // @[Regfile.scala 147:75]
+  wire  _valid_T_83 = io_writeData_1_valid & io_writeData_1_addr == 5'h4 & _valid_T_16; // @[Regfile.scala 149:75]
+  wire  _valid_T_85 = io_writeData_0_valid & io_writeData_0_addr == 5'h4; // @[Regfile.scala 151:43]
+  wire [5:0] valid_3 = {_valid_T_67,_valid_T_71,_valid_T_75,_valid_T_79,_valid_T_83,_valid_T_85}; // @[Cat.scala 31:58]
   wire [31:0] _data_T_49 = valid_3[0] ? io_writeData_0_data : 32'h0; // @[Library.scala 8:8]
   wire [31:0] _data_T_51 = valid_3[1] ? io_writeData_1_data : 32'h0; // @[Library.scala 8:8]
-  wire [31:0] _data_T_52 = _data_T_49 | _data_T_51; // @[Regfile.scala 153:55]
+  wire [31:0] _data_T_52 = _data_T_49 | _data_T_51; // @[Regfile.scala 154:55]
   wire [31:0] _data_T_54 = valid_3[2] ? io_writeData_2_data : 32'h0; // @[Library.scala 8:8]
-  wire [31:0] _data_T_55 = _data_T_52 | _data_T_54; // @[Regfile.scala 154:55]
+  wire [31:0] _data_T_55 = _data_T_52 | _data_T_54; // @[Regfile.scala 155:55]
   wire [31:0] _data_T_57 = valid_3[3] ? io_writeData_3_data : 32'h0; // @[Library.scala 8:8]
-  wire [31:0] _data_T_58 = _data_T_55 | _data_T_57; // @[Regfile.scala 155:55]
+  wire [31:0] _data_T_58 = _data_T_55 | _data_T_57; // @[Regfile.scala 156:55]
   wire [31:0] _data_T_60 = valid_3[4] ? io_writeData_4_data : 32'h0; // @[Library.scala 8:8]
-  wire [31:0] _data_T_61 = _data_T_58 | _data_T_60; // @[Regfile.scala 156:55]
+  wire [31:0] _data_T_61 = _data_T_58 | _data_T_60; // @[Regfile.scala 157:55]
   wire [31:0] _data_T_63 = valid_3[5] ? io_writeData_5_data : 32'h0; // @[Library.scala 8:8]
-  wire [31:0] data_3 = _data_T_61 | _data_T_63; // @[Regfile.scala 157:55]
-  wire  writeValid_4 = valid_3 != 6'h0; // @[Regfile.scala 160:28]
+  wire [31:0] data_3 = _data_T_61 | _data_T_63; // @[Regfile.scala 158:55]
+  wire  writeValid_4 = valid_3 != 6'h0; // @[Regfile.scala 161:28]
   wire [1:0] _T_69 = valid_3[1] + valid_3[2]; // @[Bitwise.scala 48:55]
   wire [1:0] _GEN_47 = {{1'd0}, valid_3[0]}; // @[Bitwise.scala 48:55]
   wire [2:0] _T_71 = _GEN_47 + _T_69; // @[Bitwise.scala 48:55]
@@ -361,25 +363,25 @@
   wire [1:0] _GEN_48 = {{1'd0}, valid_3[3]}; // @[Bitwise.scala 48:55]
   wire [2:0] _T_75 = _GEN_48 + _T_73; // @[Bitwise.scala 48:55]
   wire [2:0] _T_77 = _T_71[1:0] + _T_75[1:0]; // @[Bitwise.scala 48:55]
-  wire  _valid_T_81 = io_writeData_5_valid & io_writeData_5_addr == 5'h5; // @[Regfile.scala 142:43]
-  wire  _valid_T_83 = io_writeData_4_valid & io_writeData_4_addr == 5'h5; // @[Regfile.scala 143:43]
-  wire  _valid_T_87 = io_writeData_3_valid & io_writeData_3_addr == 5'h5 & _valid_T_6; // @[Regfile.scala 144:75]
-  wire  _valid_T_91 = io_writeData_2_valid & io_writeData_2_addr == 5'h5 & _valid_T_10; // @[Regfile.scala 146:75]
-  wire  _valid_T_95 = io_writeData_1_valid & io_writeData_1_addr == 5'h5 & _valid_T_14; // @[Regfile.scala 148:75]
-  wire  _valid_T_97 = io_writeData_0_valid & io_writeData_0_addr == 5'h5; // @[Regfile.scala 150:43]
-  wire [5:0] valid_4 = {_valid_T_81,_valid_T_83,_valid_T_87,_valid_T_91,_valid_T_95,_valid_T_97}; // @[Cat.scala 31:58]
+  wire  _valid_T_89 = io_writeData_5_valid & io_writeData_5_addr == 5'h5; // @[Regfile.scala 142:43]
+  wire  _valid_T_93 = io_writeData_4_valid & io_writeData_4_addr == 5'h5 & _valid_T_4; // @[Regfile.scala 143:75]
+  wire  _valid_T_97 = io_writeData_3_valid & io_writeData_3_addr == 5'h5 & _valid_T_8; // @[Regfile.scala 145:75]
+  wire  _valid_T_101 = io_writeData_2_valid & io_writeData_2_addr == 5'h5 & _valid_T_12; // @[Regfile.scala 147:75]
+  wire  _valid_T_105 = io_writeData_1_valid & io_writeData_1_addr == 5'h5 & _valid_T_16; // @[Regfile.scala 149:75]
+  wire  _valid_T_107 = io_writeData_0_valid & io_writeData_0_addr == 5'h5; // @[Regfile.scala 151:43]
+  wire [5:0] valid_4 = {_valid_T_89,_valid_T_93,_valid_T_97,_valid_T_101,_valid_T_105,_valid_T_107}; // @[Cat.scala 31:58]
   wire [31:0] _data_T_65 = valid_4[0] ? io_writeData_0_data : 32'h0; // @[Library.scala 8:8]
   wire [31:0] _data_T_67 = valid_4[1] ? io_writeData_1_data : 32'h0; // @[Library.scala 8:8]
-  wire [31:0] _data_T_68 = _data_T_65 | _data_T_67; // @[Regfile.scala 153:55]
+  wire [31:0] _data_T_68 = _data_T_65 | _data_T_67; // @[Regfile.scala 154:55]
   wire [31:0] _data_T_70 = valid_4[2] ? io_writeData_2_data : 32'h0; // @[Library.scala 8:8]
-  wire [31:0] _data_T_71 = _data_T_68 | _data_T_70; // @[Regfile.scala 154:55]
+  wire [31:0] _data_T_71 = _data_T_68 | _data_T_70; // @[Regfile.scala 155:55]
   wire [31:0] _data_T_73 = valid_4[3] ? io_writeData_3_data : 32'h0; // @[Library.scala 8:8]
-  wire [31:0] _data_T_74 = _data_T_71 | _data_T_73; // @[Regfile.scala 155:55]
+  wire [31:0] _data_T_74 = _data_T_71 | _data_T_73; // @[Regfile.scala 156:55]
   wire [31:0] _data_T_76 = valid_4[4] ? io_writeData_4_data : 32'h0; // @[Library.scala 8:8]
-  wire [31:0] _data_T_77 = _data_T_74 | _data_T_76; // @[Regfile.scala 156:55]
+  wire [31:0] _data_T_77 = _data_T_74 | _data_T_76; // @[Regfile.scala 157:55]
   wire [31:0] _data_T_79 = valid_4[5] ? io_writeData_5_data : 32'h0; // @[Library.scala 8:8]
-  wire [31:0] data_4 = _data_T_77 | _data_T_79; // @[Regfile.scala 157:55]
-  wire  writeValid_5 = valid_4 != 6'h0; // @[Regfile.scala 160:28]
+  wire [31:0] data_4 = _data_T_77 | _data_T_79; // @[Regfile.scala 158:55]
+  wire  writeValid_5 = valid_4 != 6'h0; // @[Regfile.scala 161:28]
   wire [1:0] _T_89 = valid_4[1] + valid_4[2]; // @[Bitwise.scala 48:55]
   wire [1:0] _GEN_49 = {{1'd0}, valid_4[0]}; // @[Bitwise.scala 48:55]
   wire [2:0] _T_91 = _GEN_49 + _T_89; // @[Bitwise.scala 48:55]
@@ -387,25 +389,25 @@
   wire [1:0] _GEN_50 = {{1'd0}, valid_4[3]}; // @[Bitwise.scala 48:55]
   wire [2:0] _T_95 = _GEN_50 + _T_93; // @[Bitwise.scala 48:55]
   wire [2:0] _T_97 = _T_91[1:0] + _T_95[1:0]; // @[Bitwise.scala 48:55]
-  wire  _valid_T_101 = io_writeData_5_valid & io_writeData_5_addr == 5'h6; // @[Regfile.scala 142:43]
-  wire  _valid_T_103 = io_writeData_4_valid & io_writeData_4_addr == 5'h6; // @[Regfile.scala 143:43]
-  wire  _valid_T_107 = io_writeData_3_valid & io_writeData_3_addr == 5'h6 & _valid_T_6; // @[Regfile.scala 144:75]
-  wire  _valid_T_111 = io_writeData_2_valid & io_writeData_2_addr == 5'h6 & _valid_T_10; // @[Regfile.scala 146:75]
-  wire  _valid_T_115 = io_writeData_1_valid & io_writeData_1_addr == 5'h6 & _valid_T_14; // @[Regfile.scala 148:75]
-  wire  _valid_T_117 = io_writeData_0_valid & io_writeData_0_addr == 5'h6; // @[Regfile.scala 150:43]
-  wire [5:0] valid_5 = {_valid_T_101,_valid_T_103,_valid_T_107,_valid_T_111,_valid_T_115,_valid_T_117}; // @[Cat.scala 31:58]
+  wire  _valid_T_111 = io_writeData_5_valid & io_writeData_5_addr == 5'h6; // @[Regfile.scala 142:43]
+  wire  _valid_T_115 = io_writeData_4_valid & io_writeData_4_addr == 5'h6 & _valid_T_4; // @[Regfile.scala 143:75]
+  wire  _valid_T_119 = io_writeData_3_valid & io_writeData_3_addr == 5'h6 & _valid_T_8; // @[Regfile.scala 145:75]
+  wire  _valid_T_123 = io_writeData_2_valid & io_writeData_2_addr == 5'h6 & _valid_T_12; // @[Regfile.scala 147:75]
+  wire  _valid_T_127 = io_writeData_1_valid & io_writeData_1_addr == 5'h6 & _valid_T_16; // @[Regfile.scala 149:75]
+  wire  _valid_T_129 = io_writeData_0_valid & io_writeData_0_addr == 5'h6; // @[Regfile.scala 151:43]
+  wire [5:0] valid_5 = {_valid_T_111,_valid_T_115,_valid_T_119,_valid_T_123,_valid_T_127,_valid_T_129}; // @[Cat.scala 31:58]
   wire [31:0] _data_T_81 = valid_5[0] ? io_writeData_0_data : 32'h0; // @[Library.scala 8:8]
   wire [31:0] _data_T_83 = valid_5[1] ? io_writeData_1_data : 32'h0; // @[Library.scala 8:8]
-  wire [31:0] _data_T_84 = _data_T_81 | _data_T_83; // @[Regfile.scala 153:55]
+  wire [31:0] _data_T_84 = _data_T_81 | _data_T_83; // @[Regfile.scala 154:55]
   wire [31:0] _data_T_86 = valid_5[2] ? io_writeData_2_data : 32'h0; // @[Library.scala 8:8]
-  wire [31:0] _data_T_87 = _data_T_84 | _data_T_86; // @[Regfile.scala 154:55]
+  wire [31:0] _data_T_87 = _data_T_84 | _data_T_86; // @[Regfile.scala 155:55]
   wire [31:0] _data_T_89 = valid_5[3] ? io_writeData_3_data : 32'h0; // @[Library.scala 8:8]
-  wire [31:0] _data_T_90 = _data_T_87 | _data_T_89; // @[Regfile.scala 155:55]
+  wire [31:0] _data_T_90 = _data_T_87 | _data_T_89; // @[Regfile.scala 156:55]
   wire [31:0] _data_T_92 = valid_5[4] ? io_writeData_4_data : 32'h0; // @[Library.scala 8:8]
-  wire [31:0] _data_T_93 = _data_T_90 | _data_T_92; // @[Regfile.scala 156:55]
+  wire [31:0] _data_T_93 = _data_T_90 | _data_T_92; // @[Regfile.scala 157:55]
   wire [31:0] _data_T_95 = valid_5[5] ? io_writeData_5_data : 32'h0; // @[Library.scala 8:8]
-  wire [31:0] data_5 = _data_T_93 | _data_T_95; // @[Regfile.scala 157:55]
-  wire  writeValid_6 = valid_5 != 6'h0; // @[Regfile.scala 160:28]
+  wire [31:0] data_5 = _data_T_93 | _data_T_95; // @[Regfile.scala 158:55]
+  wire  writeValid_6 = valid_5 != 6'h0; // @[Regfile.scala 161:28]
   wire [1:0] _T_109 = valid_5[1] + valid_5[2]; // @[Bitwise.scala 48:55]
   wire [1:0] _GEN_51 = {{1'd0}, valid_5[0]}; // @[Bitwise.scala 48:55]
   wire [2:0] _T_111 = _GEN_51 + _T_109; // @[Bitwise.scala 48:55]
@@ -413,25 +415,25 @@
   wire [1:0] _GEN_52 = {{1'd0}, valid_5[3]}; // @[Bitwise.scala 48:55]
   wire [2:0] _T_115 = _GEN_52 + _T_113; // @[Bitwise.scala 48:55]
   wire [2:0] _T_117 = _T_111[1:0] + _T_115[1:0]; // @[Bitwise.scala 48:55]
-  wire  _valid_T_121 = io_writeData_5_valid & io_writeData_5_addr == 5'h7; // @[Regfile.scala 142:43]
-  wire  _valid_T_123 = io_writeData_4_valid & io_writeData_4_addr == 5'h7; // @[Regfile.scala 143:43]
-  wire  _valid_T_127 = io_writeData_3_valid & io_writeData_3_addr == 5'h7 & _valid_T_6; // @[Regfile.scala 144:75]
-  wire  _valid_T_131 = io_writeData_2_valid & io_writeData_2_addr == 5'h7 & _valid_T_10; // @[Regfile.scala 146:75]
-  wire  _valid_T_135 = io_writeData_1_valid & io_writeData_1_addr == 5'h7 & _valid_T_14; // @[Regfile.scala 148:75]
-  wire  _valid_T_137 = io_writeData_0_valid & io_writeData_0_addr == 5'h7; // @[Regfile.scala 150:43]
-  wire [5:0] valid_6 = {_valid_T_121,_valid_T_123,_valid_T_127,_valid_T_131,_valid_T_135,_valid_T_137}; // @[Cat.scala 31:58]
+  wire  _valid_T_133 = io_writeData_5_valid & io_writeData_5_addr == 5'h7; // @[Regfile.scala 142:43]
+  wire  _valid_T_137 = io_writeData_4_valid & io_writeData_4_addr == 5'h7 & _valid_T_4; // @[Regfile.scala 143:75]
+  wire  _valid_T_141 = io_writeData_3_valid & io_writeData_3_addr == 5'h7 & _valid_T_8; // @[Regfile.scala 145:75]
+  wire  _valid_T_145 = io_writeData_2_valid & io_writeData_2_addr == 5'h7 & _valid_T_12; // @[Regfile.scala 147:75]
+  wire  _valid_T_149 = io_writeData_1_valid & io_writeData_1_addr == 5'h7 & _valid_T_16; // @[Regfile.scala 149:75]
+  wire  _valid_T_151 = io_writeData_0_valid & io_writeData_0_addr == 5'h7; // @[Regfile.scala 151:43]
+  wire [5:0] valid_6 = {_valid_T_133,_valid_T_137,_valid_T_141,_valid_T_145,_valid_T_149,_valid_T_151}; // @[Cat.scala 31:58]
   wire [31:0] _data_T_97 = valid_6[0] ? io_writeData_0_data : 32'h0; // @[Library.scala 8:8]
   wire [31:0] _data_T_99 = valid_6[1] ? io_writeData_1_data : 32'h0; // @[Library.scala 8:8]
-  wire [31:0] _data_T_100 = _data_T_97 | _data_T_99; // @[Regfile.scala 153:55]
+  wire [31:0] _data_T_100 = _data_T_97 | _data_T_99; // @[Regfile.scala 154:55]
   wire [31:0] _data_T_102 = valid_6[2] ? io_writeData_2_data : 32'h0; // @[Library.scala 8:8]
-  wire [31:0] _data_T_103 = _data_T_100 | _data_T_102; // @[Regfile.scala 154:55]
+  wire [31:0] _data_T_103 = _data_T_100 | _data_T_102; // @[Regfile.scala 155:55]
   wire [31:0] _data_T_105 = valid_6[3] ? io_writeData_3_data : 32'h0; // @[Library.scala 8:8]
-  wire [31:0] _data_T_106 = _data_T_103 | _data_T_105; // @[Regfile.scala 155:55]
+  wire [31:0] _data_T_106 = _data_T_103 | _data_T_105; // @[Regfile.scala 156:55]
   wire [31:0] _data_T_108 = valid_6[4] ? io_writeData_4_data : 32'h0; // @[Library.scala 8:8]
-  wire [31:0] _data_T_109 = _data_T_106 | _data_T_108; // @[Regfile.scala 156:55]
+  wire [31:0] _data_T_109 = _data_T_106 | _data_T_108; // @[Regfile.scala 157:55]
   wire [31:0] _data_T_111 = valid_6[5] ? io_writeData_5_data : 32'h0; // @[Library.scala 8:8]
-  wire [31:0] data_6 = _data_T_109 | _data_T_111; // @[Regfile.scala 157:55]
-  wire  writeValid_7 = valid_6 != 6'h0; // @[Regfile.scala 160:28]
+  wire [31:0] data_6 = _data_T_109 | _data_T_111; // @[Regfile.scala 158:55]
+  wire  writeValid_7 = valid_6 != 6'h0; // @[Regfile.scala 161:28]
   wire [1:0] _T_129 = valid_6[1] + valid_6[2]; // @[Bitwise.scala 48:55]
   wire [1:0] _GEN_53 = {{1'd0}, valid_6[0]}; // @[Bitwise.scala 48:55]
   wire [2:0] _T_131 = _GEN_53 + _T_129; // @[Bitwise.scala 48:55]
@@ -439,25 +441,25 @@
   wire [1:0] _GEN_54 = {{1'd0}, valid_6[3]}; // @[Bitwise.scala 48:55]
   wire [2:0] _T_135 = _GEN_54 + _T_133; // @[Bitwise.scala 48:55]
   wire [2:0] _T_137 = _T_131[1:0] + _T_135[1:0]; // @[Bitwise.scala 48:55]
-  wire  _valid_T_141 = io_writeData_5_valid & io_writeData_5_addr == 5'h8; // @[Regfile.scala 142:43]
-  wire  _valid_T_143 = io_writeData_4_valid & io_writeData_4_addr == 5'h8; // @[Regfile.scala 143:43]
-  wire  _valid_T_147 = io_writeData_3_valid & io_writeData_3_addr == 5'h8 & _valid_T_6; // @[Regfile.scala 144:75]
-  wire  _valid_T_151 = io_writeData_2_valid & io_writeData_2_addr == 5'h8 & _valid_T_10; // @[Regfile.scala 146:75]
-  wire  _valid_T_155 = io_writeData_1_valid & io_writeData_1_addr == 5'h8 & _valid_T_14; // @[Regfile.scala 148:75]
-  wire  _valid_T_157 = io_writeData_0_valid & io_writeData_0_addr == 5'h8; // @[Regfile.scala 150:43]
-  wire [5:0] valid_7 = {_valid_T_141,_valid_T_143,_valid_T_147,_valid_T_151,_valid_T_155,_valid_T_157}; // @[Cat.scala 31:58]
+  wire  _valid_T_155 = io_writeData_5_valid & io_writeData_5_addr == 5'h8; // @[Regfile.scala 142:43]
+  wire  _valid_T_159 = io_writeData_4_valid & io_writeData_4_addr == 5'h8 & _valid_T_4; // @[Regfile.scala 143:75]
+  wire  _valid_T_163 = io_writeData_3_valid & io_writeData_3_addr == 5'h8 & _valid_T_8; // @[Regfile.scala 145:75]
+  wire  _valid_T_167 = io_writeData_2_valid & io_writeData_2_addr == 5'h8 & _valid_T_12; // @[Regfile.scala 147:75]
+  wire  _valid_T_171 = io_writeData_1_valid & io_writeData_1_addr == 5'h8 & _valid_T_16; // @[Regfile.scala 149:75]
+  wire  _valid_T_173 = io_writeData_0_valid & io_writeData_0_addr == 5'h8; // @[Regfile.scala 151:43]
+  wire [5:0] valid_7 = {_valid_T_155,_valid_T_159,_valid_T_163,_valid_T_167,_valid_T_171,_valid_T_173}; // @[Cat.scala 31:58]
   wire [31:0] _data_T_113 = valid_7[0] ? io_writeData_0_data : 32'h0; // @[Library.scala 8:8]
   wire [31:0] _data_T_115 = valid_7[1] ? io_writeData_1_data : 32'h0; // @[Library.scala 8:8]
-  wire [31:0] _data_T_116 = _data_T_113 | _data_T_115; // @[Regfile.scala 153:55]
+  wire [31:0] _data_T_116 = _data_T_113 | _data_T_115; // @[Regfile.scala 154:55]
   wire [31:0] _data_T_118 = valid_7[2] ? io_writeData_2_data : 32'h0; // @[Library.scala 8:8]
-  wire [31:0] _data_T_119 = _data_T_116 | _data_T_118; // @[Regfile.scala 154:55]
+  wire [31:0] _data_T_119 = _data_T_116 | _data_T_118; // @[Regfile.scala 155:55]
   wire [31:0] _data_T_121 = valid_7[3] ? io_writeData_3_data : 32'h0; // @[Library.scala 8:8]
-  wire [31:0] _data_T_122 = _data_T_119 | _data_T_121; // @[Regfile.scala 155:55]
+  wire [31:0] _data_T_122 = _data_T_119 | _data_T_121; // @[Regfile.scala 156:55]
   wire [31:0] _data_T_124 = valid_7[4] ? io_writeData_4_data : 32'h0; // @[Library.scala 8:8]
-  wire [31:0] _data_T_125 = _data_T_122 | _data_T_124; // @[Regfile.scala 156:55]
+  wire [31:0] _data_T_125 = _data_T_122 | _data_T_124; // @[Regfile.scala 157:55]
   wire [31:0] _data_T_127 = valid_7[5] ? io_writeData_5_data : 32'h0; // @[Library.scala 8:8]
-  wire [31:0] data_7 = _data_T_125 | _data_T_127; // @[Regfile.scala 157:55]
-  wire  writeValid_8 = valid_7 != 6'h0; // @[Regfile.scala 160:28]
+  wire [31:0] data_7 = _data_T_125 | _data_T_127; // @[Regfile.scala 158:55]
+  wire  writeValid_8 = valid_7 != 6'h0; // @[Regfile.scala 161:28]
   wire [1:0] _T_149 = valid_7[1] + valid_7[2]; // @[Bitwise.scala 48:55]
   wire [1:0] _GEN_55 = {{1'd0}, valid_7[0]}; // @[Bitwise.scala 48:55]
   wire [2:0] _T_151 = _GEN_55 + _T_149; // @[Bitwise.scala 48:55]
@@ -465,25 +467,25 @@
   wire [1:0] _GEN_56 = {{1'd0}, valid_7[3]}; // @[Bitwise.scala 48:55]
   wire [2:0] _T_155 = _GEN_56 + _T_153; // @[Bitwise.scala 48:55]
   wire [2:0] _T_157 = _T_151[1:0] + _T_155[1:0]; // @[Bitwise.scala 48:55]
-  wire  _valid_T_161 = io_writeData_5_valid & io_writeData_5_addr == 5'h9; // @[Regfile.scala 142:43]
-  wire  _valid_T_163 = io_writeData_4_valid & io_writeData_4_addr == 5'h9; // @[Regfile.scala 143:43]
-  wire  _valid_T_167 = io_writeData_3_valid & io_writeData_3_addr == 5'h9 & _valid_T_6; // @[Regfile.scala 144:75]
-  wire  _valid_T_171 = io_writeData_2_valid & io_writeData_2_addr == 5'h9 & _valid_T_10; // @[Regfile.scala 146:75]
-  wire  _valid_T_175 = io_writeData_1_valid & io_writeData_1_addr == 5'h9 & _valid_T_14; // @[Regfile.scala 148:75]
-  wire  _valid_T_177 = io_writeData_0_valid & io_writeData_0_addr == 5'h9; // @[Regfile.scala 150:43]
-  wire [5:0] valid_8 = {_valid_T_161,_valid_T_163,_valid_T_167,_valid_T_171,_valid_T_175,_valid_T_177}; // @[Cat.scala 31:58]
+  wire  _valid_T_177 = io_writeData_5_valid & io_writeData_5_addr == 5'h9; // @[Regfile.scala 142:43]
+  wire  _valid_T_181 = io_writeData_4_valid & io_writeData_4_addr == 5'h9 & _valid_T_4; // @[Regfile.scala 143:75]
+  wire  _valid_T_185 = io_writeData_3_valid & io_writeData_3_addr == 5'h9 & _valid_T_8; // @[Regfile.scala 145:75]
+  wire  _valid_T_189 = io_writeData_2_valid & io_writeData_2_addr == 5'h9 & _valid_T_12; // @[Regfile.scala 147:75]
+  wire  _valid_T_193 = io_writeData_1_valid & io_writeData_1_addr == 5'h9 & _valid_T_16; // @[Regfile.scala 149:75]
+  wire  _valid_T_195 = io_writeData_0_valid & io_writeData_0_addr == 5'h9; // @[Regfile.scala 151:43]
+  wire [5:0] valid_8 = {_valid_T_177,_valid_T_181,_valid_T_185,_valid_T_189,_valid_T_193,_valid_T_195}; // @[Cat.scala 31:58]
   wire [31:0] _data_T_129 = valid_8[0] ? io_writeData_0_data : 32'h0; // @[Library.scala 8:8]
   wire [31:0] _data_T_131 = valid_8[1] ? io_writeData_1_data : 32'h0; // @[Library.scala 8:8]
-  wire [31:0] _data_T_132 = _data_T_129 | _data_T_131; // @[Regfile.scala 153:55]
+  wire [31:0] _data_T_132 = _data_T_129 | _data_T_131; // @[Regfile.scala 154:55]
   wire [31:0] _data_T_134 = valid_8[2] ? io_writeData_2_data : 32'h0; // @[Library.scala 8:8]
-  wire [31:0] _data_T_135 = _data_T_132 | _data_T_134; // @[Regfile.scala 154:55]
+  wire [31:0] _data_T_135 = _data_T_132 | _data_T_134; // @[Regfile.scala 155:55]
   wire [31:0] _data_T_137 = valid_8[3] ? io_writeData_3_data : 32'h0; // @[Library.scala 8:8]
-  wire [31:0] _data_T_138 = _data_T_135 | _data_T_137; // @[Regfile.scala 155:55]
+  wire [31:0] _data_T_138 = _data_T_135 | _data_T_137; // @[Regfile.scala 156:55]
   wire [31:0] _data_T_140 = valid_8[4] ? io_writeData_4_data : 32'h0; // @[Library.scala 8:8]
-  wire [31:0] _data_T_141 = _data_T_138 | _data_T_140; // @[Regfile.scala 156:55]
+  wire [31:0] _data_T_141 = _data_T_138 | _data_T_140; // @[Regfile.scala 157:55]
   wire [31:0] _data_T_143 = valid_8[5] ? io_writeData_5_data : 32'h0; // @[Library.scala 8:8]
-  wire [31:0] data_8 = _data_T_141 | _data_T_143; // @[Regfile.scala 157:55]
-  wire  writeValid_9 = valid_8 != 6'h0; // @[Regfile.scala 160:28]
+  wire [31:0] data_8 = _data_T_141 | _data_T_143; // @[Regfile.scala 158:55]
+  wire  writeValid_9 = valid_8 != 6'h0; // @[Regfile.scala 161:28]
   wire [1:0] _T_169 = valid_8[1] + valid_8[2]; // @[Bitwise.scala 48:55]
   wire [1:0] _GEN_57 = {{1'd0}, valid_8[0]}; // @[Bitwise.scala 48:55]
   wire [2:0] _T_171 = _GEN_57 + _T_169; // @[Bitwise.scala 48:55]
@@ -491,25 +493,25 @@
   wire [1:0] _GEN_58 = {{1'd0}, valid_8[3]}; // @[Bitwise.scala 48:55]
   wire [2:0] _T_175 = _GEN_58 + _T_173; // @[Bitwise.scala 48:55]
   wire [2:0] _T_177 = _T_171[1:0] + _T_175[1:0]; // @[Bitwise.scala 48:55]
-  wire  _valid_T_181 = io_writeData_5_valid & io_writeData_5_addr == 5'ha; // @[Regfile.scala 142:43]
-  wire  _valid_T_183 = io_writeData_4_valid & io_writeData_4_addr == 5'ha; // @[Regfile.scala 143:43]
-  wire  _valid_T_187 = io_writeData_3_valid & io_writeData_3_addr == 5'ha & _valid_T_6; // @[Regfile.scala 144:75]
-  wire  _valid_T_191 = io_writeData_2_valid & io_writeData_2_addr == 5'ha & _valid_T_10; // @[Regfile.scala 146:75]
-  wire  _valid_T_195 = io_writeData_1_valid & io_writeData_1_addr == 5'ha & _valid_T_14; // @[Regfile.scala 148:75]
-  wire  _valid_T_197 = io_writeData_0_valid & io_writeData_0_addr == 5'ha; // @[Regfile.scala 150:43]
-  wire [5:0] valid_9 = {_valid_T_181,_valid_T_183,_valid_T_187,_valid_T_191,_valid_T_195,_valid_T_197}; // @[Cat.scala 31:58]
+  wire  _valid_T_199 = io_writeData_5_valid & io_writeData_5_addr == 5'ha; // @[Regfile.scala 142:43]
+  wire  _valid_T_203 = io_writeData_4_valid & io_writeData_4_addr == 5'ha & _valid_T_4; // @[Regfile.scala 143:75]
+  wire  _valid_T_207 = io_writeData_3_valid & io_writeData_3_addr == 5'ha & _valid_T_8; // @[Regfile.scala 145:75]
+  wire  _valid_T_211 = io_writeData_2_valid & io_writeData_2_addr == 5'ha & _valid_T_12; // @[Regfile.scala 147:75]
+  wire  _valid_T_215 = io_writeData_1_valid & io_writeData_1_addr == 5'ha & _valid_T_16; // @[Regfile.scala 149:75]
+  wire  _valid_T_217 = io_writeData_0_valid & io_writeData_0_addr == 5'ha; // @[Regfile.scala 151:43]
+  wire [5:0] valid_9 = {_valid_T_199,_valid_T_203,_valid_T_207,_valid_T_211,_valid_T_215,_valid_T_217}; // @[Cat.scala 31:58]
   wire [31:0] _data_T_145 = valid_9[0] ? io_writeData_0_data : 32'h0; // @[Library.scala 8:8]
   wire [31:0] _data_T_147 = valid_9[1] ? io_writeData_1_data : 32'h0; // @[Library.scala 8:8]
-  wire [31:0] _data_T_148 = _data_T_145 | _data_T_147; // @[Regfile.scala 153:55]
+  wire [31:0] _data_T_148 = _data_T_145 | _data_T_147; // @[Regfile.scala 154:55]
   wire [31:0] _data_T_150 = valid_9[2] ? io_writeData_2_data : 32'h0; // @[Library.scala 8:8]
-  wire [31:0] _data_T_151 = _data_T_148 | _data_T_150; // @[Regfile.scala 154:55]
+  wire [31:0] _data_T_151 = _data_T_148 | _data_T_150; // @[Regfile.scala 155:55]
   wire [31:0] _data_T_153 = valid_9[3] ? io_writeData_3_data : 32'h0; // @[Library.scala 8:8]
-  wire [31:0] _data_T_154 = _data_T_151 | _data_T_153; // @[Regfile.scala 155:55]
+  wire [31:0] _data_T_154 = _data_T_151 | _data_T_153; // @[Regfile.scala 156:55]
   wire [31:0] _data_T_156 = valid_9[4] ? io_writeData_4_data : 32'h0; // @[Library.scala 8:8]
-  wire [31:0] _data_T_157 = _data_T_154 | _data_T_156; // @[Regfile.scala 156:55]
+  wire [31:0] _data_T_157 = _data_T_154 | _data_T_156; // @[Regfile.scala 157:55]
   wire [31:0] _data_T_159 = valid_9[5] ? io_writeData_5_data : 32'h0; // @[Library.scala 8:8]
-  wire [31:0] data_9 = _data_T_157 | _data_T_159; // @[Regfile.scala 157:55]
-  wire  writeValid_10 = valid_9 != 6'h0; // @[Regfile.scala 160:28]
+  wire [31:0] data_9 = _data_T_157 | _data_T_159; // @[Regfile.scala 158:55]
+  wire  writeValid_10 = valid_9 != 6'h0; // @[Regfile.scala 161:28]
   wire [1:0] _T_189 = valid_9[1] + valid_9[2]; // @[Bitwise.scala 48:55]
   wire [1:0] _GEN_59 = {{1'd0}, valid_9[0]}; // @[Bitwise.scala 48:55]
   wire [2:0] _T_191 = _GEN_59 + _T_189; // @[Bitwise.scala 48:55]
@@ -517,25 +519,25 @@
   wire [1:0] _GEN_60 = {{1'd0}, valid_9[3]}; // @[Bitwise.scala 48:55]
   wire [2:0] _T_195 = _GEN_60 + _T_193; // @[Bitwise.scala 48:55]
   wire [2:0] _T_197 = _T_191[1:0] + _T_195[1:0]; // @[Bitwise.scala 48:55]
-  wire  _valid_T_201 = io_writeData_5_valid & io_writeData_5_addr == 5'hb; // @[Regfile.scala 142:43]
-  wire  _valid_T_203 = io_writeData_4_valid & io_writeData_4_addr == 5'hb; // @[Regfile.scala 143:43]
-  wire  _valid_T_207 = io_writeData_3_valid & io_writeData_3_addr == 5'hb & _valid_T_6; // @[Regfile.scala 144:75]
-  wire  _valid_T_211 = io_writeData_2_valid & io_writeData_2_addr == 5'hb & _valid_T_10; // @[Regfile.scala 146:75]
-  wire  _valid_T_215 = io_writeData_1_valid & io_writeData_1_addr == 5'hb & _valid_T_14; // @[Regfile.scala 148:75]
-  wire  _valid_T_217 = io_writeData_0_valid & io_writeData_0_addr == 5'hb; // @[Regfile.scala 150:43]
-  wire [5:0] valid_10 = {_valid_T_201,_valid_T_203,_valid_T_207,_valid_T_211,_valid_T_215,_valid_T_217}; // @[Cat.scala 31:58]
+  wire  _valid_T_221 = io_writeData_5_valid & io_writeData_5_addr == 5'hb; // @[Regfile.scala 142:43]
+  wire  _valid_T_225 = io_writeData_4_valid & io_writeData_4_addr == 5'hb & _valid_T_4; // @[Regfile.scala 143:75]
+  wire  _valid_T_229 = io_writeData_3_valid & io_writeData_3_addr == 5'hb & _valid_T_8; // @[Regfile.scala 145:75]
+  wire  _valid_T_233 = io_writeData_2_valid & io_writeData_2_addr == 5'hb & _valid_T_12; // @[Regfile.scala 147:75]
+  wire  _valid_T_237 = io_writeData_1_valid & io_writeData_1_addr == 5'hb & _valid_T_16; // @[Regfile.scala 149:75]
+  wire  _valid_T_239 = io_writeData_0_valid & io_writeData_0_addr == 5'hb; // @[Regfile.scala 151:43]
+  wire [5:0] valid_10 = {_valid_T_221,_valid_T_225,_valid_T_229,_valid_T_233,_valid_T_237,_valid_T_239}; // @[Cat.scala 31:58]
   wire [31:0] _data_T_161 = valid_10[0] ? io_writeData_0_data : 32'h0; // @[Library.scala 8:8]
   wire [31:0] _data_T_163 = valid_10[1] ? io_writeData_1_data : 32'h0; // @[Library.scala 8:8]
-  wire [31:0] _data_T_164 = _data_T_161 | _data_T_163; // @[Regfile.scala 153:55]
+  wire [31:0] _data_T_164 = _data_T_161 | _data_T_163; // @[Regfile.scala 154:55]
   wire [31:0] _data_T_166 = valid_10[2] ? io_writeData_2_data : 32'h0; // @[Library.scala 8:8]
-  wire [31:0] _data_T_167 = _data_T_164 | _data_T_166; // @[Regfile.scala 154:55]
+  wire [31:0] _data_T_167 = _data_T_164 | _data_T_166; // @[Regfile.scala 155:55]
   wire [31:0] _data_T_169 = valid_10[3] ? io_writeData_3_data : 32'h0; // @[Library.scala 8:8]
-  wire [31:0] _data_T_170 = _data_T_167 | _data_T_169; // @[Regfile.scala 155:55]
+  wire [31:0] _data_T_170 = _data_T_167 | _data_T_169; // @[Regfile.scala 156:55]
   wire [31:0] _data_T_172 = valid_10[4] ? io_writeData_4_data : 32'h0; // @[Library.scala 8:8]
-  wire [31:0] _data_T_173 = _data_T_170 | _data_T_172; // @[Regfile.scala 156:55]
+  wire [31:0] _data_T_173 = _data_T_170 | _data_T_172; // @[Regfile.scala 157:55]
   wire [31:0] _data_T_175 = valid_10[5] ? io_writeData_5_data : 32'h0; // @[Library.scala 8:8]
-  wire [31:0] data_10 = _data_T_173 | _data_T_175; // @[Regfile.scala 157:55]
-  wire  writeValid_11 = valid_10 != 6'h0; // @[Regfile.scala 160:28]
+  wire [31:0] data_10 = _data_T_173 | _data_T_175; // @[Regfile.scala 158:55]
+  wire  writeValid_11 = valid_10 != 6'h0; // @[Regfile.scala 161:28]
   wire [1:0] _T_209 = valid_10[1] + valid_10[2]; // @[Bitwise.scala 48:55]
   wire [1:0] _GEN_61 = {{1'd0}, valid_10[0]}; // @[Bitwise.scala 48:55]
   wire [2:0] _T_211 = _GEN_61 + _T_209; // @[Bitwise.scala 48:55]
@@ -543,25 +545,25 @@
   wire [1:0] _GEN_62 = {{1'd0}, valid_10[3]}; // @[Bitwise.scala 48:55]
   wire [2:0] _T_215 = _GEN_62 + _T_213; // @[Bitwise.scala 48:55]
   wire [2:0] _T_217 = _T_211[1:0] + _T_215[1:0]; // @[Bitwise.scala 48:55]
-  wire  _valid_T_221 = io_writeData_5_valid & io_writeData_5_addr == 5'hc; // @[Regfile.scala 142:43]
-  wire  _valid_T_223 = io_writeData_4_valid & io_writeData_4_addr == 5'hc; // @[Regfile.scala 143:43]
-  wire  _valid_T_227 = io_writeData_3_valid & io_writeData_3_addr == 5'hc & _valid_T_6; // @[Regfile.scala 144:75]
-  wire  _valid_T_231 = io_writeData_2_valid & io_writeData_2_addr == 5'hc & _valid_T_10; // @[Regfile.scala 146:75]
-  wire  _valid_T_235 = io_writeData_1_valid & io_writeData_1_addr == 5'hc & _valid_T_14; // @[Regfile.scala 148:75]
-  wire  _valid_T_237 = io_writeData_0_valid & io_writeData_0_addr == 5'hc; // @[Regfile.scala 150:43]
-  wire [5:0] valid_11 = {_valid_T_221,_valid_T_223,_valid_T_227,_valid_T_231,_valid_T_235,_valid_T_237}; // @[Cat.scala 31:58]
+  wire  _valid_T_243 = io_writeData_5_valid & io_writeData_5_addr == 5'hc; // @[Regfile.scala 142:43]
+  wire  _valid_T_247 = io_writeData_4_valid & io_writeData_4_addr == 5'hc & _valid_T_4; // @[Regfile.scala 143:75]
+  wire  _valid_T_251 = io_writeData_3_valid & io_writeData_3_addr == 5'hc & _valid_T_8; // @[Regfile.scala 145:75]
+  wire  _valid_T_255 = io_writeData_2_valid & io_writeData_2_addr == 5'hc & _valid_T_12; // @[Regfile.scala 147:75]
+  wire  _valid_T_259 = io_writeData_1_valid & io_writeData_1_addr == 5'hc & _valid_T_16; // @[Regfile.scala 149:75]
+  wire  _valid_T_261 = io_writeData_0_valid & io_writeData_0_addr == 5'hc; // @[Regfile.scala 151:43]
+  wire [5:0] valid_11 = {_valid_T_243,_valid_T_247,_valid_T_251,_valid_T_255,_valid_T_259,_valid_T_261}; // @[Cat.scala 31:58]
   wire [31:0] _data_T_177 = valid_11[0] ? io_writeData_0_data : 32'h0; // @[Library.scala 8:8]
   wire [31:0] _data_T_179 = valid_11[1] ? io_writeData_1_data : 32'h0; // @[Library.scala 8:8]
-  wire [31:0] _data_T_180 = _data_T_177 | _data_T_179; // @[Regfile.scala 153:55]
+  wire [31:0] _data_T_180 = _data_T_177 | _data_T_179; // @[Regfile.scala 154:55]
   wire [31:0] _data_T_182 = valid_11[2] ? io_writeData_2_data : 32'h0; // @[Library.scala 8:8]
-  wire [31:0] _data_T_183 = _data_T_180 | _data_T_182; // @[Regfile.scala 154:55]
+  wire [31:0] _data_T_183 = _data_T_180 | _data_T_182; // @[Regfile.scala 155:55]
   wire [31:0] _data_T_185 = valid_11[3] ? io_writeData_3_data : 32'h0; // @[Library.scala 8:8]
-  wire [31:0] _data_T_186 = _data_T_183 | _data_T_185; // @[Regfile.scala 155:55]
+  wire [31:0] _data_T_186 = _data_T_183 | _data_T_185; // @[Regfile.scala 156:55]
   wire [31:0] _data_T_188 = valid_11[4] ? io_writeData_4_data : 32'h0; // @[Library.scala 8:8]
-  wire [31:0] _data_T_189 = _data_T_186 | _data_T_188; // @[Regfile.scala 156:55]
+  wire [31:0] _data_T_189 = _data_T_186 | _data_T_188; // @[Regfile.scala 157:55]
   wire [31:0] _data_T_191 = valid_11[5] ? io_writeData_5_data : 32'h0; // @[Library.scala 8:8]
-  wire [31:0] data_11 = _data_T_189 | _data_T_191; // @[Regfile.scala 157:55]
-  wire  writeValid_12 = valid_11 != 6'h0; // @[Regfile.scala 160:28]
+  wire [31:0] data_11 = _data_T_189 | _data_T_191; // @[Regfile.scala 158:55]
+  wire  writeValid_12 = valid_11 != 6'h0; // @[Regfile.scala 161:28]
   wire [1:0] _T_229 = valid_11[1] + valid_11[2]; // @[Bitwise.scala 48:55]
   wire [1:0] _GEN_63 = {{1'd0}, valid_11[0]}; // @[Bitwise.scala 48:55]
   wire [2:0] _T_231 = _GEN_63 + _T_229; // @[Bitwise.scala 48:55]
@@ -569,25 +571,25 @@
   wire [1:0] _GEN_64 = {{1'd0}, valid_11[3]}; // @[Bitwise.scala 48:55]
   wire [2:0] _T_235 = _GEN_64 + _T_233; // @[Bitwise.scala 48:55]
   wire [2:0] _T_237 = _T_231[1:0] + _T_235[1:0]; // @[Bitwise.scala 48:55]
-  wire  _valid_T_241 = io_writeData_5_valid & io_writeData_5_addr == 5'hd; // @[Regfile.scala 142:43]
-  wire  _valid_T_243 = io_writeData_4_valid & io_writeData_4_addr == 5'hd; // @[Regfile.scala 143:43]
-  wire  _valid_T_247 = io_writeData_3_valid & io_writeData_3_addr == 5'hd & _valid_T_6; // @[Regfile.scala 144:75]
-  wire  _valid_T_251 = io_writeData_2_valid & io_writeData_2_addr == 5'hd & _valid_T_10; // @[Regfile.scala 146:75]
-  wire  _valid_T_255 = io_writeData_1_valid & io_writeData_1_addr == 5'hd & _valid_T_14; // @[Regfile.scala 148:75]
-  wire  _valid_T_257 = io_writeData_0_valid & io_writeData_0_addr == 5'hd; // @[Regfile.scala 150:43]
-  wire [5:0] valid_12 = {_valid_T_241,_valid_T_243,_valid_T_247,_valid_T_251,_valid_T_255,_valid_T_257}; // @[Cat.scala 31:58]
+  wire  _valid_T_265 = io_writeData_5_valid & io_writeData_5_addr == 5'hd; // @[Regfile.scala 142:43]
+  wire  _valid_T_269 = io_writeData_4_valid & io_writeData_4_addr == 5'hd & _valid_T_4; // @[Regfile.scala 143:75]
+  wire  _valid_T_273 = io_writeData_3_valid & io_writeData_3_addr == 5'hd & _valid_T_8; // @[Regfile.scala 145:75]
+  wire  _valid_T_277 = io_writeData_2_valid & io_writeData_2_addr == 5'hd & _valid_T_12; // @[Regfile.scala 147:75]
+  wire  _valid_T_281 = io_writeData_1_valid & io_writeData_1_addr == 5'hd & _valid_T_16; // @[Regfile.scala 149:75]
+  wire  _valid_T_283 = io_writeData_0_valid & io_writeData_0_addr == 5'hd; // @[Regfile.scala 151:43]
+  wire [5:0] valid_12 = {_valid_T_265,_valid_T_269,_valid_T_273,_valid_T_277,_valid_T_281,_valid_T_283}; // @[Cat.scala 31:58]
   wire [31:0] _data_T_193 = valid_12[0] ? io_writeData_0_data : 32'h0; // @[Library.scala 8:8]
   wire [31:0] _data_T_195 = valid_12[1] ? io_writeData_1_data : 32'h0; // @[Library.scala 8:8]
-  wire [31:0] _data_T_196 = _data_T_193 | _data_T_195; // @[Regfile.scala 153:55]
+  wire [31:0] _data_T_196 = _data_T_193 | _data_T_195; // @[Regfile.scala 154:55]
   wire [31:0] _data_T_198 = valid_12[2] ? io_writeData_2_data : 32'h0; // @[Library.scala 8:8]
-  wire [31:0] _data_T_199 = _data_T_196 | _data_T_198; // @[Regfile.scala 154:55]
+  wire [31:0] _data_T_199 = _data_T_196 | _data_T_198; // @[Regfile.scala 155:55]
   wire [31:0] _data_T_201 = valid_12[3] ? io_writeData_3_data : 32'h0; // @[Library.scala 8:8]
-  wire [31:0] _data_T_202 = _data_T_199 | _data_T_201; // @[Regfile.scala 155:55]
+  wire [31:0] _data_T_202 = _data_T_199 | _data_T_201; // @[Regfile.scala 156:55]
   wire [31:0] _data_T_204 = valid_12[4] ? io_writeData_4_data : 32'h0; // @[Library.scala 8:8]
-  wire [31:0] _data_T_205 = _data_T_202 | _data_T_204; // @[Regfile.scala 156:55]
+  wire [31:0] _data_T_205 = _data_T_202 | _data_T_204; // @[Regfile.scala 157:55]
   wire [31:0] _data_T_207 = valid_12[5] ? io_writeData_5_data : 32'h0; // @[Library.scala 8:8]
-  wire [31:0] data_12 = _data_T_205 | _data_T_207; // @[Regfile.scala 157:55]
-  wire  writeValid_13 = valid_12 != 6'h0; // @[Regfile.scala 160:28]
+  wire [31:0] data_12 = _data_T_205 | _data_T_207; // @[Regfile.scala 158:55]
+  wire  writeValid_13 = valid_12 != 6'h0; // @[Regfile.scala 161:28]
   wire [1:0] _T_249 = valid_12[1] + valid_12[2]; // @[Bitwise.scala 48:55]
   wire [1:0] _GEN_65 = {{1'd0}, valid_12[0]}; // @[Bitwise.scala 48:55]
   wire [2:0] _T_251 = _GEN_65 + _T_249; // @[Bitwise.scala 48:55]
@@ -595,25 +597,25 @@
   wire [1:0] _GEN_66 = {{1'd0}, valid_12[3]}; // @[Bitwise.scala 48:55]
   wire [2:0] _T_255 = _GEN_66 + _T_253; // @[Bitwise.scala 48:55]
   wire [2:0] _T_257 = _T_251[1:0] + _T_255[1:0]; // @[Bitwise.scala 48:55]
-  wire  _valid_T_261 = io_writeData_5_valid & io_writeData_5_addr == 5'he; // @[Regfile.scala 142:43]
-  wire  _valid_T_263 = io_writeData_4_valid & io_writeData_4_addr == 5'he; // @[Regfile.scala 143:43]
-  wire  _valid_T_267 = io_writeData_3_valid & io_writeData_3_addr == 5'he & _valid_T_6; // @[Regfile.scala 144:75]
-  wire  _valid_T_271 = io_writeData_2_valid & io_writeData_2_addr == 5'he & _valid_T_10; // @[Regfile.scala 146:75]
-  wire  _valid_T_275 = io_writeData_1_valid & io_writeData_1_addr == 5'he & _valid_T_14; // @[Regfile.scala 148:75]
-  wire  _valid_T_277 = io_writeData_0_valid & io_writeData_0_addr == 5'he; // @[Regfile.scala 150:43]
-  wire [5:0] valid_13 = {_valid_T_261,_valid_T_263,_valid_T_267,_valid_T_271,_valid_T_275,_valid_T_277}; // @[Cat.scala 31:58]
+  wire  _valid_T_287 = io_writeData_5_valid & io_writeData_5_addr == 5'he; // @[Regfile.scala 142:43]
+  wire  _valid_T_291 = io_writeData_4_valid & io_writeData_4_addr == 5'he & _valid_T_4; // @[Regfile.scala 143:75]
+  wire  _valid_T_295 = io_writeData_3_valid & io_writeData_3_addr == 5'he & _valid_T_8; // @[Regfile.scala 145:75]
+  wire  _valid_T_299 = io_writeData_2_valid & io_writeData_2_addr == 5'he & _valid_T_12; // @[Regfile.scala 147:75]
+  wire  _valid_T_303 = io_writeData_1_valid & io_writeData_1_addr == 5'he & _valid_T_16; // @[Regfile.scala 149:75]
+  wire  _valid_T_305 = io_writeData_0_valid & io_writeData_0_addr == 5'he; // @[Regfile.scala 151:43]
+  wire [5:0] valid_13 = {_valid_T_287,_valid_T_291,_valid_T_295,_valid_T_299,_valid_T_303,_valid_T_305}; // @[Cat.scala 31:58]
   wire [31:0] _data_T_209 = valid_13[0] ? io_writeData_0_data : 32'h0; // @[Library.scala 8:8]
   wire [31:0] _data_T_211 = valid_13[1] ? io_writeData_1_data : 32'h0; // @[Library.scala 8:8]
-  wire [31:0] _data_T_212 = _data_T_209 | _data_T_211; // @[Regfile.scala 153:55]
+  wire [31:0] _data_T_212 = _data_T_209 | _data_T_211; // @[Regfile.scala 154:55]
   wire [31:0] _data_T_214 = valid_13[2] ? io_writeData_2_data : 32'h0; // @[Library.scala 8:8]
-  wire [31:0] _data_T_215 = _data_T_212 | _data_T_214; // @[Regfile.scala 154:55]
+  wire [31:0] _data_T_215 = _data_T_212 | _data_T_214; // @[Regfile.scala 155:55]
   wire [31:0] _data_T_217 = valid_13[3] ? io_writeData_3_data : 32'h0; // @[Library.scala 8:8]
-  wire [31:0] _data_T_218 = _data_T_215 | _data_T_217; // @[Regfile.scala 155:55]
+  wire [31:0] _data_T_218 = _data_T_215 | _data_T_217; // @[Regfile.scala 156:55]
   wire [31:0] _data_T_220 = valid_13[4] ? io_writeData_4_data : 32'h0; // @[Library.scala 8:8]
-  wire [31:0] _data_T_221 = _data_T_218 | _data_T_220; // @[Regfile.scala 156:55]
+  wire [31:0] _data_T_221 = _data_T_218 | _data_T_220; // @[Regfile.scala 157:55]
   wire [31:0] _data_T_223 = valid_13[5] ? io_writeData_5_data : 32'h0; // @[Library.scala 8:8]
-  wire [31:0] data_13 = _data_T_221 | _data_T_223; // @[Regfile.scala 157:55]
-  wire  writeValid_14 = valid_13 != 6'h0; // @[Regfile.scala 160:28]
+  wire [31:0] data_13 = _data_T_221 | _data_T_223; // @[Regfile.scala 158:55]
+  wire  writeValid_14 = valid_13 != 6'h0; // @[Regfile.scala 161:28]
   wire [1:0] _T_269 = valid_13[1] + valid_13[2]; // @[Bitwise.scala 48:55]
   wire [1:0] _GEN_67 = {{1'd0}, valid_13[0]}; // @[Bitwise.scala 48:55]
   wire [2:0] _T_271 = _GEN_67 + _T_269; // @[Bitwise.scala 48:55]
@@ -621,25 +623,25 @@
   wire [1:0] _GEN_68 = {{1'd0}, valid_13[3]}; // @[Bitwise.scala 48:55]
   wire [2:0] _T_275 = _GEN_68 + _T_273; // @[Bitwise.scala 48:55]
   wire [2:0] _T_277 = _T_271[1:0] + _T_275[1:0]; // @[Bitwise.scala 48:55]
-  wire  _valid_T_281 = io_writeData_5_valid & io_writeData_5_addr == 5'hf; // @[Regfile.scala 142:43]
-  wire  _valid_T_283 = io_writeData_4_valid & io_writeData_4_addr == 5'hf; // @[Regfile.scala 143:43]
-  wire  _valid_T_287 = io_writeData_3_valid & io_writeData_3_addr == 5'hf & _valid_T_6; // @[Regfile.scala 144:75]
-  wire  _valid_T_291 = io_writeData_2_valid & io_writeData_2_addr == 5'hf & _valid_T_10; // @[Regfile.scala 146:75]
-  wire  _valid_T_295 = io_writeData_1_valid & io_writeData_1_addr == 5'hf & _valid_T_14; // @[Regfile.scala 148:75]
-  wire  _valid_T_297 = io_writeData_0_valid & io_writeData_0_addr == 5'hf; // @[Regfile.scala 150:43]
-  wire [5:0] valid_14 = {_valid_T_281,_valid_T_283,_valid_T_287,_valid_T_291,_valid_T_295,_valid_T_297}; // @[Cat.scala 31:58]
+  wire  _valid_T_309 = io_writeData_5_valid & io_writeData_5_addr == 5'hf; // @[Regfile.scala 142:43]
+  wire  _valid_T_313 = io_writeData_4_valid & io_writeData_4_addr == 5'hf & _valid_T_4; // @[Regfile.scala 143:75]
+  wire  _valid_T_317 = io_writeData_3_valid & io_writeData_3_addr == 5'hf & _valid_T_8; // @[Regfile.scala 145:75]
+  wire  _valid_T_321 = io_writeData_2_valid & io_writeData_2_addr == 5'hf & _valid_T_12; // @[Regfile.scala 147:75]
+  wire  _valid_T_325 = io_writeData_1_valid & io_writeData_1_addr == 5'hf & _valid_T_16; // @[Regfile.scala 149:75]
+  wire  _valid_T_327 = io_writeData_0_valid & io_writeData_0_addr == 5'hf; // @[Regfile.scala 151:43]
+  wire [5:0] valid_14 = {_valid_T_309,_valid_T_313,_valid_T_317,_valid_T_321,_valid_T_325,_valid_T_327}; // @[Cat.scala 31:58]
   wire [31:0] _data_T_225 = valid_14[0] ? io_writeData_0_data : 32'h0; // @[Library.scala 8:8]
   wire [31:0] _data_T_227 = valid_14[1] ? io_writeData_1_data : 32'h0; // @[Library.scala 8:8]
-  wire [31:0] _data_T_228 = _data_T_225 | _data_T_227; // @[Regfile.scala 153:55]
+  wire [31:0] _data_T_228 = _data_T_225 | _data_T_227; // @[Regfile.scala 154:55]
   wire [31:0] _data_T_230 = valid_14[2] ? io_writeData_2_data : 32'h0; // @[Library.scala 8:8]
-  wire [31:0] _data_T_231 = _data_T_228 | _data_T_230; // @[Regfile.scala 154:55]
+  wire [31:0] _data_T_231 = _data_T_228 | _data_T_230; // @[Regfile.scala 155:55]
   wire [31:0] _data_T_233 = valid_14[3] ? io_writeData_3_data : 32'h0; // @[Library.scala 8:8]
-  wire [31:0] _data_T_234 = _data_T_231 | _data_T_233; // @[Regfile.scala 155:55]
+  wire [31:0] _data_T_234 = _data_T_231 | _data_T_233; // @[Regfile.scala 156:55]
   wire [31:0] _data_T_236 = valid_14[4] ? io_writeData_4_data : 32'h0; // @[Library.scala 8:8]
-  wire [31:0] _data_T_237 = _data_T_234 | _data_T_236; // @[Regfile.scala 156:55]
+  wire [31:0] _data_T_237 = _data_T_234 | _data_T_236; // @[Regfile.scala 157:55]
   wire [31:0] _data_T_239 = valid_14[5] ? io_writeData_5_data : 32'h0; // @[Library.scala 8:8]
-  wire [31:0] data_14 = _data_T_237 | _data_T_239; // @[Regfile.scala 157:55]
-  wire  writeValid_15 = valid_14 != 6'h0; // @[Regfile.scala 160:28]
+  wire [31:0] data_14 = _data_T_237 | _data_T_239; // @[Regfile.scala 158:55]
+  wire  writeValid_15 = valid_14 != 6'h0; // @[Regfile.scala 161:28]
   wire [1:0] _T_289 = valid_14[1] + valid_14[2]; // @[Bitwise.scala 48:55]
   wire [1:0] _GEN_69 = {{1'd0}, valid_14[0]}; // @[Bitwise.scala 48:55]
   wire [2:0] _T_291 = _GEN_69 + _T_289; // @[Bitwise.scala 48:55]
@@ -647,25 +649,25 @@
   wire [1:0] _GEN_70 = {{1'd0}, valid_14[3]}; // @[Bitwise.scala 48:55]
   wire [2:0] _T_295 = _GEN_70 + _T_293; // @[Bitwise.scala 48:55]
   wire [2:0] _T_297 = _T_291[1:0] + _T_295[1:0]; // @[Bitwise.scala 48:55]
-  wire  _valid_T_301 = io_writeData_5_valid & io_writeData_5_addr == 5'h10; // @[Regfile.scala 142:43]
-  wire  _valid_T_303 = io_writeData_4_valid & io_writeData_4_addr == 5'h10; // @[Regfile.scala 143:43]
-  wire  _valid_T_307 = io_writeData_3_valid & io_writeData_3_addr == 5'h10 & _valid_T_6; // @[Regfile.scala 144:75]
-  wire  _valid_T_311 = io_writeData_2_valid & io_writeData_2_addr == 5'h10 & _valid_T_10; // @[Regfile.scala 146:75]
-  wire  _valid_T_315 = io_writeData_1_valid & io_writeData_1_addr == 5'h10 & _valid_T_14; // @[Regfile.scala 148:75]
-  wire  _valid_T_317 = io_writeData_0_valid & io_writeData_0_addr == 5'h10; // @[Regfile.scala 150:43]
-  wire [5:0] valid_15 = {_valid_T_301,_valid_T_303,_valid_T_307,_valid_T_311,_valid_T_315,_valid_T_317}; // @[Cat.scala 31:58]
+  wire  _valid_T_331 = io_writeData_5_valid & io_writeData_5_addr == 5'h10; // @[Regfile.scala 142:43]
+  wire  _valid_T_335 = io_writeData_4_valid & io_writeData_4_addr == 5'h10 & _valid_T_4; // @[Regfile.scala 143:75]
+  wire  _valid_T_339 = io_writeData_3_valid & io_writeData_3_addr == 5'h10 & _valid_T_8; // @[Regfile.scala 145:75]
+  wire  _valid_T_343 = io_writeData_2_valid & io_writeData_2_addr == 5'h10 & _valid_T_12; // @[Regfile.scala 147:75]
+  wire  _valid_T_347 = io_writeData_1_valid & io_writeData_1_addr == 5'h10 & _valid_T_16; // @[Regfile.scala 149:75]
+  wire  _valid_T_349 = io_writeData_0_valid & io_writeData_0_addr == 5'h10; // @[Regfile.scala 151:43]
+  wire [5:0] valid_15 = {_valid_T_331,_valid_T_335,_valid_T_339,_valid_T_343,_valid_T_347,_valid_T_349}; // @[Cat.scala 31:58]
   wire [31:0] _data_T_241 = valid_15[0] ? io_writeData_0_data : 32'h0; // @[Library.scala 8:8]
   wire [31:0] _data_T_243 = valid_15[1] ? io_writeData_1_data : 32'h0; // @[Library.scala 8:8]
-  wire [31:0] _data_T_244 = _data_T_241 | _data_T_243; // @[Regfile.scala 153:55]
+  wire [31:0] _data_T_244 = _data_T_241 | _data_T_243; // @[Regfile.scala 154:55]
   wire [31:0] _data_T_246 = valid_15[2] ? io_writeData_2_data : 32'h0; // @[Library.scala 8:8]
-  wire [31:0] _data_T_247 = _data_T_244 | _data_T_246; // @[Regfile.scala 154:55]
+  wire [31:0] _data_T_247 = _data_T_244 | _data_T_246; // @[Regfile.scala 155:55]
   wire [31:0] _data_T_249 = valid_15[3] ? io_writeData_3_data : 32'h0; // @[Library.scala 8:8]
-  wire [31:0] _data_T_250 = _data_T_247 | _data_T_249; // @[Regfile.scala 155:55]
+  wire [31:0] _data_T_250 = _data_T_247 | _data_T_249; // @[Regfile.scala 156:55]
   wire [31:0] _data_T_252 = valid_15[4] ? io_writeData_4_data : 32'h0; // @[Library.scala 8:8]
-  wire [31:0] _data_T_253 = _data_T_250 | _data_T_252; // @[Regfile.scala 156:55]
+  wire [31:0] _data_T_253 = _data_T_250 | _data_T_252; // @[Regfile.scala 157:55]
   wire [31:0] _data_T_255 = valid_15[5] ? io_writeData_5_data : 32'h0; // @[Library.scala 8:8]
-  wire [31:0] data_15 = _data_T_253 | _data_T_255; // @[Regfile.scala 157:55]
-  wire  writeValid_16 = valid_15 != 6'h0; // @[Regfile.scala 160:28]
+  wire [31:0] data_15 = _data_T_253 | _data_T_255; // @[Regfile.scala 158:55]
+  wire  writeValid_16 = valid_15 != 6'h0; // @[Regfile.scala 161:28]
   wire [1:0] _T_309 = valid_15[1] + valid_15[2]; // @[Bitwise.scala 48:55]
   wire [1:0] _GEN_71 = {{1'd0}, valid_15[0]}; // @[Bitwise.scala 48:55]
   wire [2:0] _T_311 = _GEN_71 + _T_309; // @[Bitwise.scala 48:55]
@@ -673,25 +675,25 @@
   wire [1:0] _GEN_72 = {{1'd0}, valid_15[3]}; // @[Bitwise.scala 48:55]
   wire [2:0] _T_315 = _GEN_72 + _T_313; // @[Bitwise.scala 48:55]
   wire [2:0] _T_317 = _T_311[1:0] + _T_315[1:0]; // @[Bitwise.scala 48:55]
-  wire  _valid_T_321 = io_writeData_5_valid & io_writeData_5_addr == 5'h11; // @[Regfile.scala 142:43]
-  wire  _valid_T_323 = io_writeData_4_valid & io_writeData_4_addr == 5'h11; // @[Regfile.scala 143:43]
-  wire  _valid_T_327 = io_writeData_3_valid & io_writeData_3_addr == 5'h11 & _valid_T_6; // @[Regfile.scala 144:75]
-  wire  _valid_T_331 = io_writeData_2_valid & io_writeData_2_addr == 5'h11 & _valid_T_10; // @[Regfile.scala 146:75]
-  wire  _valid_T_335 = io_writeData_1_valid & io_writeData_1_addr == 5'h11 & _valid_T_14; // @[Regfile.scala 148:75]
-  wire  _valid_T_337 = io_writeData_0_valid & io_writeData_0_addr == 5'h11; // @[Regfile.scala 150:43]
-  wire [5:0] valid_16 = {_valid_T_321,_valid_T_323,_valid_T_327,_valid_T_331,_valid_T_335,_valid_T_337}; // @[Cat.scala 31:58]
+  wire  _valid_T_353 = io_writeData_5_valid & io_writeData_5_addr == 5'h11; // @[Regfile.scala 142:43]
+  wire  _valid_T_357 = io_writeData_4_valid & io_writeData_4_addr == 5'h11 & _valid_T_4; // @[Regfile.scala 143:75]
+  wire  _valid_T_361 = io_writeData_3_valid & io_writeData_3_addr == 5'h11 & _valid_T_8; // @[Regfile.scala 145:75]
+  wire  _valid_T_365 = io_writeData_2_valid & io_writeData_2_addr == 5'h11 & _valid_T_12; // @[Regfile.scala 147:75]
+  wire  _valid_T_369 = io_writeData_1_valid & io_writeData_1_addr == 5'h11 & _valid_T_16; // @[Regfile.scala 149:75]
+  wire  _valid_T_371 = io_writeData_0_valid & io_writeData_0_addr == 5'h11; // @[Regfile.scala 151:43]
+  wire [5:0] valid_16 = {_valid_T_353,_valid_T_357,_valid_T_361,_valid_T_365,_valid_T_369,_valid_T_371}; // @[Cat.scala 31:58]
   wire [31:0] _data_T_257 = valid_16[0] ? io_writeData_0_data : 32'h0; // @[Library.scala 8:8]
   wire [31:0] _data_T_259 = valid_16[1] ? io_writeData_1_data : 32'h0; // @[Library.scala 8:8]
-  wire [31:0] _data_T_260 = _data_T_257 | _data_T_259; // @[Regfile.scala 153:55]
+  wire [31:0] _data_T_260 = _data_T_257 | _data_T_259; // @[Regfile.scala 154:55]
   wire [31:0] _data_T_262 = valid_16[2] ? io_writeData_2_data : 32'h0; // @[Library.scala 8:8]
-  wire [31:0] _data_T_263 = _data_T_260 | _data_T_262; // @[Regfile.scala 154:55]
+  wire [31:0] _data_T_263 = _data_T_260 | _data_T_262; // @[Regfile.scala 155:55]
   wire [31:0] _data_T_265 = valid_16[3] ? io_writeData_3_data : 32'h0; // @[Library.scala 8:8]
-  wire [31:0] _data_T_266 = _data_T_263 | _data_T_265; // @[Regfile.scala 155:55]
+  wire [31:0] _data_T_266 = _data_T_263 | _data_T_265; // @[Regfile.scala 156:55]
   wire [31:0] _data_T_268 = valid_16[4] ? io_writeData_4_data : 32'h0; // @[Library.scala 8:8]
-  wire [31:0] _data_T_269 = _data_T_266 | _data_T_268; // @[Regfile.scala 156:55]
+  wire [31:0] _data_T_269 = _data_T_266 | _data_T_268; // @[Regfile.scala 157:55]
   wire [31:0] _data_T_271 = valid_16[5] ? io_writeData_5_data : 32'h0; // @[Library.scala 8:8]
-  wire [31:0] data_16 = _data_T_269 | _data_T_271; // @[Regfile.scala 157:55]
-  wire  writeValid_17 = valid_16 != 6'h0; // @[Regfile.scala 160:28]
+  wire [31:0] data_16 = _data_T_269 | _data_T_271; // @[Regfile.scala 158:55]
+  wire  writeValid_17 = valid_16 != 6'h0; // @[Regfile.scala 161:28]
   wire [1:0] _T_329 = valid_16[1] + valid_16[2]; // @[Bitwise.scala 48:55]
   wire [1:0] _GEN_73 = {{1'd0}, valid_16[0]}; // @[Bitwise.scala 48:55]
   wire [2:0] _T_331 = _GEN_73 + _T_329; // @[Bitwise.scala 48:55]
@@ -699,25 +701,25 @@
   wire [1:0] _GEN_74 = {{1'd0}, valid_16[3]}; // @[Bitwise.scala 48:55]
   wire [2:0] _T_335 = _GEN_74 + _T_333; // @[Bitwise.scala 48:55]
   wire [2:0] _T_337 = _T_331[1:0] + _T_335[1:0]; // @[Bitwise.scala 48:55]
-  wire  _valid_T_341 = io_writeData_5_valid & io_writeData_5_addr == 5'h12; // @[Regfile.scala 142:43]
-  wire  _valid_T_343 = io_writeData_4_valid & io_writeData_4_addr == 5'h12; // @[Regfile.scala 143:43]
-  wire  _valid_T_347 = io_writeData_3_valid & io_writeData_3_addr == 5'h12 & _valid_T_6; // @[Regfile.scala 144:75]
-  wire  _valid_T_351 = io_writeData_2_valid & io_writeData_2_addr == 5'h12 & _valid_T_10; // @[Regfile.scala 146:75]
-  wire  _valid_T_355 = io_writeData_1_valid & io_writeData_1_addr == 5'h12 & _valid_T_14; // @[Regfile.scala 148:75]
-  wire  _valid_T_357 = io_writeData_0_valid & io_writeData_0_addr == 5'h12; // @[Regfile.scala 150:43]
-  wire [5:0] valid_17 = {_valid_T_341,_valid_T_343,_valid_T_347,_valid_T_351,_valid_T_355,_valid_T_357}; // @[Cat.scala 31:58]
+  wire  _valid_T_375 = io_writeData_5_valid & io_writeData_5_addr == 5'h12; // @[Regfile.scala 142:43]
+  wire  _valid_T_379 = io_writeData_4_valid & io_writeData_4_addr == 5'h12 & _valid_T_4; // @[Regfile.scala 143:75]
+  wire  _valid_T_383 = io_writeData_3_valid & io_writeData_3_addr == 5'h12 & _valid_T_8; // @[Regfile.scala 145:75]
+  wire  _valid_T_387 = io_writeData_2_valid & io_writeData_2_addr == 5'h12 & _valid_T_12; // @[Regfile.scala 147:75]
+  wire  _valid_T_391 = io_writeData_1_valid & io_writeData_1_addr == 5'h12 & _valid_T_16; // @[Regfile.scala 149:75]
+  wire  _valid_T_393 = io_writeData_0_valid & io_writeData_0_addr == 5'h12; // @[Regfile.scala 151:43]
+  wire [5:0] valid_17 = {_valid_T_375,_valid_T_379,_valid_T_383,_valid_T_387,_valid_T_391,_valid_T_393}; // @[Cat.scala 31:58]
   wire [31:0] _data_T_273 = valid_17[0] ? io_writeData_0_data : 32'h0; // @[Library.scala 8:8]
   wire [31:0] _data_T_275 = valid_17[1] ? io_writeData_1_data : 32'h0; // @[Library.scala 8:8]
-  wire [31:0] _data_T_276 = _data_T_273 | _data_T_275; // @[Regfile.scala 153:55]
+  wire [31:0] _data_T_276 = _data_T_273 | _data_T_275; // @[Regfile.scala 154:55]
   wire [31:0] _data_T_278 = valid_17[2] ? io_writeData_2_data : 32'h0; // @[Library.scala 8:8]
-  wire [31:0] _data_T_279 = _data_T_276 | _data_T_278; // @[Regfile.scala 154:55]
+  wire [31:0] _data_T_279 = _data_T_276 | _data_T_278; // @[Regfile.scala 155:55]
   wire [31:0] _data_T_281 = valid_17[3] ? io_writeData_3_data : 32'h0; // @[Library.scala 8:8]
-  wire [31:0] _data_T_282 = _data_T_279 | _data_T_281; // @[Regfile.scala 155:55]
+  wire [31:0] _data_T_282 = _data_T_279 | _data_T_281; // @[Regfile.scala 156:55]
   wire [31:0] _data_T_284 = valid_17[4] ? io_writeData_4_data : 32'h0; // @[Library.scala 8:8]
-  wire [31:0] _data_T_285 = _data_T_282 | _data_T_284; // @[Regfile.scala 156:55]
+  wire [31:0] _data_T_285 = _data_T_282 | _data_T_284; // @[Regfile.scala 157:55]
   wire [31:0] _data_T_287 = valid_17[5] ? io_writeData_5_data : 32'h0; // @[Library.scala 8:8]
-  wire [31:0] data_17 = _data_T_285 | _data_T_287; // @[Regfile.scala 157:55]
-  wire  writeValid_18 = valid_17 != 6'h0; // @[Regfile.scala 160:28]
+  wire [31:0] data_17 = _data_T_285 | _data_T_287; // @[Regfile.scala 158:55]
+  wire  writeValid_18 = valid_17 != 6'h0; // @[Regfile.scala 161:28]
   wire [1:0] _T_349 = valid_17[1] + valid_17[2]; // @[Bitwise.scala 48:55]
   wire [1:0] _GEN_75 = {{1'd0}, valid_17[0]}; // @[Bitwise.scala 48:55]
   wire [2:0] _T_351 = _GEN_75 + _T_349; // @[Bitwise.scala 48:55]
@@ -725,25 +727,25 @@
   wire [1:0] _GEN_76 = {{1'd0}, valid_17[3]}; // @[Bitwise.scala 48:55]
   wire [2:0] _T_355 = _GEN_76 + _T_353; // @[Bitwise.scala 48:55]
   wire [2:0] _T_357 = _T_351[1:0] + _T_355[1:0]; // @[Bitwise.scala 48:55]
-  wire  _valid_T_361 = io_writeData_5_valid & io_writeData_5_addr == 5'h13; // @[Regfile.scala 142:43]
-  wire  _valid_T_363 = io_writeData_4_valid & io_writeData_4_addr == 5'h13; // @[Regfile.scala 143:43]
-  wire  _valid_T_367 = io_writeData_3_valid & io_writeData_3_addr == 5'h13 & _valid_T_6; // @[Regfile.scala 144:75]
-  wire  _valid_T_371 = io_writeData_2_valid & io_writeData_2_addr == 5'h13 & _valid_T_10; // @[Regfile.scala 146:75]
-  wire  _valid_T_375 = io_writeData_1_valid & io_writeData_1_addr == 5'h13 & _valid_T_14; // @[Regfile.scala 148:75]
-  wire  _valid_T_377 = io_writeData_0_valid & io_writeData_0_addr == 5'h13; // @[Regfile.scala 150:43]
-  wire [5:0] valid_18 = {_valid_T_361,_valid_T_363,_valid_T_367,_valid_T_371,_valid_T_375,_valid_T_377}; // @[Cat.scala 31:58]
+  wire  _valid_T_397 = io_writeData_5_valid & io_writeData_5_addr == 5'h13; // @[Regfile.scala 142:43]
+  wire  _valid_T_401 = io_writeData_4_valid & io_writeData_4_addr == 5'h13 & _valid_T_4; // @[Regfile.scala 143:75]
+  wire  _valid_T_405 = io_writeData_3_valid & io_writeData_3_addr == 5'h13 & _valid_T_8; // @[Regfile.scala 145:75]
+  wire  _valid_T_409 = io_writeData_2_valid & io_writeData_2_addr == 5'h13 & _valid_T_12; // @[Regfile.scala 147:75]
+  wire  _valid_T_413 = io_writeData_1_valid & io_writeData_1_addr == 5'h13 & _valid_T_16; // @[Regfile.scala 149:75]
+  wire  _valid_T_415 = io_writeData_0_valid & io_writeData_0_addr == 5'h13; // @[Regfile.scala 151:43]
+  wire [5:0] valid_18 = {_valid_T_397,_valid_T_401,_valid_T_405,_valid_T_409,_valid_T_413,_valid_T_415}; // @[Cat.scala 31:58]
   wire [31:0] _data_T_289 = valid_18[0] ? io_writeData_0_data : 32'h0; // @[Library.scala 8:8]
   wire [31:0] _data_T_291 = valid_18[1] ? io_writeData_1_data : 32'h0; // @[Library.scala 8:8]
-  wire [31:0] _data_T_292 = _data_T_289 | _data_T_291; // @[Regfile.scala 153:55]
+  wire [31:0] _data_T_292 = _data_T_289 | _data_T_291; // @[Regfile.scala 154:55]
   wire [31:0] _data_T_294 = valid_18[2] ? io_writeData_2_data : 32'h0; // @[Library.scala 8:8]
-  wire [31:0] _data_T_295 = _data_T_292 | _data_T_294; // @[Regfile.scala 154:55]
+  wire [31:0] _data_T_295 = _data_T_292 | _data_T_294; // @[Regfile.scala 155:55]
   wire [31:0] _data_T_297 = valid_18[3] ? io_writeData_3_data : 32'h0; // @[Library.scala 8:8]
-  wire [31:0] _data_T_298 = _data_T_295 | _data_T_297; // @[Regfile.scala 155:55]
+  wire [31:0] _data_T_298 = _data_T_295 | _data_T_297; // @[Regfile.scala 156:55]
   wire [31:0] _data_T_300 = valid_18[4] ? io_writeData_4_data : 32'h0; // @[Library.scala 8:8]
-  wire [31:0] _data_T_301 = _data_T_298 | _data_T_300; // @[Regfile.scala 156:55]
+  wire [31:0] _data_T_301 = _data_T_298 | _data_T_300; // @[Regfile.scala 157:55]
   wire [31:0] _data_T_303 = valid_18[5] ? io_writeData_5_data : 32'h0; // @[Library.scala 8:8]
-  wire [31:0] data_18 = _data_T_301 | _data_T_303; // @[Regfile.scala 157:55]
-  wire  writeValid_19 = valid_18 != 6'h0; // @[Regfile.scala 160:28]
+  wire [31:0] data_18 = _data_T_301 | _data_T_303; // @[Regfile.scala 158:55]
+  wire  writeValid_19 = valid_18 != 6'h0; // @[Regfile.scala 161:28]
   wire [1:0] _T_369 = valid_18[1] + valid_18[2]; // @[Bitwise.scala 48:55]
   wire [1:0] _GEN_77 = {{1'd0}, valid_18[0]}; // @[Bitwise.scala 48:55]
   wire [2:0] _T_371 = _GEN_77 + _T_369; // @[Bitwise.scala 48:55]
@@ -751,25 +753,25 @@
   wire [1:0] _GEN_78 = {{1'd0}, valid_18[3]}; // @[Bitwise.scala 48:55]
   wire [2:0] _T_375 = _GEN_78 + _T_373; // @[Bitwise.scala 48:55]
   wire [2:0] _T_377 = _T_371[1:0] + _T_375[1:0]; // @[Bitwise.scala 48:55]
-  wire  _valid_T_381 = io_writeData_5_valid & io_writeData_5_addr == 5'h14; // @[Regfile.scala 142:43]
-  wire  _valid_T_383 = io_writeData_4_valid & io_writeData_4_addr == 5'h14; // @[Regfile.scala 143:43]
-  wire  _valid_T_387 = io_writeData_3_valid & io_writeData_3_addr == 5'h14 & _valid_T_6; // @[Regfile.scala 144:75]
-  wire  _valid_T_391 = io_writeData_2_valid & io_writeData_2_addr == 5'h14 & _valid_T_10; // @[Regfile.scala 146:75]
-  wire  _valid_T_395 = io_writeData_1_valid & io_writeData_1_addr == 5'h14 & _valid_T_14; // @[Regfile.scala 148:75]
-  wire  _valid_T_397 = io_writeData_0_valid & io_writeData_0_addr == 5'h14; // @[Regfile.scala 150:43]
-  wire [5:0] valid_19 = {_valid_T_381,_valid_T_383,_valid_T_387,_valid_T_391,_valid_T_395,_valid_T_397}; // @[Cat.scala 31:58]
+  wire  _valid_T_419 = io_writeData_5_valid & io_writeData_5_addr == 5'h14; // @[Regfile.scala 142:43]
+  wire  _valid_T_423 = io_writeData_4_valid & io_writeData_4_addr == 5'h14 & _valid_T_4; // @[Regfile.scala 143:75]
+  wire  _valid_T_427 = io_writeData_3_valid & io_writeData_3_addr == 5'h14 & _valid_T_8; // @[Regfile.scala 145:75]
+  wire  _valid_T_431 = io_writeData_2_valid & io_writeData_2_addr == 5'h14 & _valid_T_12; // @[Regfile.scala 147:75]
+  wire  _valid_T_435 = io_writeData_1_valid & io_writeData_1_addr == 5'h14 & _valid_T_16; // @[Regfile.scala 149:75]
+  wire  _valid_T_437 = io_writeData_0_valid & io_writeData_0_addr == 5'h14; // @[Regfile.scala 151:43]
+  wire [5:0] valid_19 = {_valid_T_419,_valid_T_423,_valid_T_427,_valid_T_431,_valid_T_435,_valid_T_437}; // @[Cat.scala 31:58]
   wire [31:0] _data_T_305 = valid_19[0] ? io_writeData_0_data : 32'h0; // @[Library.scala 8:8]
   wire [31:0] _data_T_307 = valid_19[1] ? io_writeData_1_data : 32'h0; // @[Library.scala 8:8]
-  wire [31:0] _data_T_308 = _data_T_305 | _data_T_307; // @[Regfile.scala 153:55]
+  wire [31:0] _data_T_308 = _data_T_305 | _data_T_307; // @[Regfile.scala 154:55]
   wire [31:0] _data_T_310 = valid_19[2] ? io_writeData_2_data : 32'h0; // @[Library.scala 8:8]
-  wire [31:0] _data_T_311 = _data_T_308 | _data_T_310; // @[Regfile.scala 154:55]
+  wire [31:0] _data_T_311 = _data_T_308 | _data_T_310; // @[Regfile.scala 155:55]
   wire [31:0] _data_T_313 = valid_19[3] ? io_writeData_3_data : 32'h0; // @[Library.scala 8:8]
-  wire [31:0] _data_T_314 = _data_T_311 | _data_T_313; // @[Regfile.scala 155:55]
+  wire [31:0] _data_T_314 = _data_T_311 | _data_T_313; // @[Regfile.scala 156:55]
   wire [31:0] _data_T_316 = valid_19[4] ? io_writeData_4_data : 32'h0; // @[Library.scala 8:8]
-  wire [31:0] _data_T_317 = _data_T_314 | _data_T_316; // @[Regfile.scala 156:55]
+  wire [31:0] _data_T_317 = _data_T_314 | _data_T_316; // @[Regfile.scala 157:55]
   wire [31:0] _data_T_319 = valid_19[5] ? io_writeData_5_data : 32'h0; // @[Library.scala 8:8]
-  wire [31:0] data_19 = _data_T_317 | _data_T_319; // @[Regfile.scala 157:55]
-  wire  writeValid_20 = valid_19 != 6'h0; // @[Regfile.scala 160:28]
+  wire [31:0] data_19 = _data_T_317 | _data_T_319; // @[Regfile.scala 158:55]
+  wire  writeValid_20 = valid_19 != 6'h0; // @[Regfile.scala 161:28]
   wire [1:0] _T_389 = valid_19[1] + valid_19[2]; // @[Bitwise.scala 48:55]
   wire [1:0] _GEN_79 = {{1'd0}, valid_19[0]}; // @[Bitwise.scala 48:55]
   wire [2:0] _T_391 = _GEN_79 + _T_389; // @[Bitwise.scala 48:55]
@@ -777,25 +779,25 @@
   wire [1:0] _GEN_80 = {{1'd0}, valid_19[3]}; // @[Bitwise.scala 48:55]
   wire [2:0] _T_395 = _GEN_80 + _T_393; // @[Bitwise.scala 48:55]
   wire [2:0] _T_397 = _T_391[1:0] + _T_395[1:0]; // @[Bitwise.scala 48:55]
-  wire  _valid_T_401 = io_writeData_5_valid & io_writeData_5_addr == 5'h15; // @[Regfile.scala 142:43]
-  wire  _valid_T_403 = io_writeData_4_valid & io_writeData_4_addr == 5'h15; // @[Regfile.scala 143:43]
-  wire  _valid_T_407 = io_writeData_3_valid & io_writeData_3_addr == 5'h15 & _valid_T_6; // @[Regfile.scala 144:75]
-  wire  _valid_T_411 = io_writeData_2_valid & io_writeData_2_addr == 5'h15 & _valid_T_10; // @[Regfile.scala 146:75]
-  wire  _valid_T_415 = io_writeData_1_valid & io_writeData_1_addr == 5'h15 & _valid_T_14; // @[Regfile.scala 148:75]
-  wire  _valid_T_417 = io_writeData_0_valid & io_writeData_0_addr == 5'h15; // @[Regfile.scala 150:43]
-  wire [5:0] valid_20 = {_valid_T_401,_valid_T_403,_valid_T_407,_valid_T_411,_valid_T_415,_valid_T_417}; // @[Cat.scala 31:58]
+  wire  _valid_T_441 = io_writeData_5_valid & io_writeData_5_addr == 5'h15; // @[Regfile.scala 142:43]
+  wire  _valid_T_445 = io_writeData_4_valid & io_writeData_4_addr == 5'h15 & _valid_T_4; // @[Regfile.scala 143:75]
+  wire  _valid_T_449 = io_writeData_3_valid & io_writeData_3_addr == 5'h15 & _valid_T_8; // @[Regfile.scala 145:75]
+  wire  _valid_T_453 = io_writeData_2_valid & io_writeData_2_addr == 5'h15 & _valid_T_12; // @[Regfile.scala 147:75]
+  wire  _valid_T_457 = io_writeData_1_valid & io_writeData_1_addr == 5'h15 & _valid_T_16; // @[Regfile.scala 149:75]
+  wire  _valid_T_459 = io_writeData_0_valid & io_writeData_0_addr == 5'h15; // @[Regfile.scala 151:43]
+  wire [5:0] valid_20 = {_valid_T_441,_valid_T_445,_valid_T_449,_valid_T_453,_valid_T_457,_valid_T_459}; // @[Cat.scala 31:58]
   wire [31:0] _data_T_321 = valid_20[0] ? io_writeData_0_data : 32'h0; // @[Library.scala 8:8]
   wire [31:0] _data_T_323 = valid_20[1] ? io_writeData_1_data : 32'h0; // @[Library.scala 8:8]
-  wire [31:0] _data_T_324 = _data_T_321 | _data_T_323; // @[Regfile.scala 153:55]
+  wire [31:0] _data_T_324 = _data_T_321 | _data_T_323; // @[Regfile.scala 154:55]
   wire [31:0] _data_T_326 = valid_20[2] ? io_writeData_2_data : 32'h0; // @[Library.scala 8:8]
-  wire [31:0] _data_T_327 = _data_T_324 | _data_T_326; // @[Regfile.scala 154:55]
+  wire [31:0] _data_T_327 = _data_T_324 | _data_T_326; // @[Regfile.scala 155:55]
   wire [31:0] _data_T_329 = valid_20[3] ? io_writeData_3_data : 32'h0; // @[Library.scala 8:8]
-  wire [31:0] _data_T_330 = _data_T_327 | _data_T_329; // @[Regfile.scala 155:55]
+  wire [31:0] _data_T_330 = _data_T_327 | _data_T_329; // @[Regfile.scala 156:55]
   wire [31:0] _data_T_332 = valid_20[4] ? io_writeData_4_data : 32'h0; // @[Library.scala 8:8]
-  wire [31:0] _data_T_333 = _data_T_330 | _data_T_332; // @[Regfile.scala 156:55]
+  wire [31:0] _data_T_333 = _data_T_330 | _data_T_332; // @[Regfile.scala 157:55]
   wire [31:0] _data_T_335 = valid_20[5] ? io_writeData_5_data : 32'h0; // @[Library.scala 8:8]
-  wire [31:0] data_20 = _data_T_333 | _data_T_335; // @[Regfile.scala 157:55]
-  wire  writeValid_21 = valid_20 != 6'h0; // @[Regfile.scala 160:28]
+  wire [31:0] data_20 = _data_T_333 | _data_T_335; // @[Regfile.scala 158:55]
+  wire  writeValid_21 = valid_20 != 6'h0; // @[Regfile.scala 161:28]
   wire [1:0] _T_409 = valid_20[1] + valid_20[2]; // @[Bitwise.scala 48:55]
   wire [1:0] _GEN_81 = {{1'd0}, valid_20[0]}; // @[Bitwise.scala 48:55]
   wire [2:0] _T_411 = _GEN_81 + _T_409; // @[Bitwise.scala 48:55]
@@ -803,25 +805,25 @@
   wire [1:0] _GEN_82 = {{1'd0}, valid_20[3]}; // @[Bitwise.scala 48:55]
   wire [2:0] _T_415 = _GEN_82 + _T_413; // @[Bitwise.scala 48:55]
   wire [2:0] _T_417 = _T_411[1:0] + _T_415[1:0]; // @[Bitwise.scala 48:55]
-  wire  _valid_T_421 = io_writeData_5_valid & io_writeData_5_addr == 5'h16; // @[Regfile.scala 142:43]
-  wire  _valid_T_423 = io_writeData_4_valid & io_writeData_4_addr == 5'h16; // @[Regfile.scala 143:43]
-  wire  _valid_T_427 = io_writeData_3_valid & io_writeData_3_addr == 5'h16 & _valid_T_6; // @[Regfile.scala 144:75]
-  wire  _valid_T_431 = io_writeData_2_valid & io_writeData_2_addr == 5'h16 & _valid_T_10; // @[Regfile.scala 146:75]
-  wire  _valid_T_435 = io_writeData_1_valid & io_writeData_1_addr == 5'h16 & _valid_T_14; // @[Regfile.scala 148:75]
-  wire  _valid_T_437 = io_writeData_0_valid & io_writeData_0_addr == 5'h16; // @[Regfile.scala 150:43]
-  wire [5:0] valid_21 = {_valid_T_421,_valid_T_423,_valid_T_427,_valid_T_431,_valid_T_435,_valid_T_437}; // @[Cat.scala 31:58]
+  wire  _valid_T_463 = io_writeData_5_valid & io_writeData_5_addr == 5'h16; // @[Regfile.scala 142:43]
+  wire  _valid_T_467 = io_writeData_4_valid & io_writeData_4_addr == 5'h16 & _valid_T_4; // @[Regfile.scala 143:75]
+  wire  _valid_T_471 = io_writeData_3_valid & io_writeData_3_addr == 5'h16 & _valid_T_8; // @[Regfile.scala 145:75]
+  wire  _valid_T_475 = io_writeData_2_valid & io_writeData_2_addr == 5'h16 & _valid_T_12; // @[Regfile.scala 147:75]
+  wire  _valid_T_479 = io_writeData_1_valid & io_writeData_1_addr == 5'h16 & _valid_T_16; // @[Regfile.scala 149:75]
+  wire  _valid_T_481 = io_writeData_0_valid & io_writeData_0_addr == 5'h16; // @[Regfile.scala 151:43]
+  wire [5:0] valid_21 = {_valid_T_463,_valid_T_467,_valid_T_471,_valid_T_475,_valid_T_479,_valid_T_481}; // @[Cat.scala 31:58]
   wire [31:0] _data_T_337 = valid_21[0] ? io_writeData_0_data : 32'h0; // @[Library.scala 8:8]
   wire [31:0] _data_T_339 = valid_21[1] ? io_writeData_1_data : 32'h0; // @[Library.scala 8:8]
-  wire [31:0] _data_T_340 = _data_T_337 | _data_T_339; // @[Regfile.scala 153:55]
+  wire [31:0] _data_T_340 = _data_T_337 | _data_T_339; // @[Regfile.scala 154:55]
   wire [31:0] _data_T_342 = valid_21[2] ? io_writeData_2_data : 32'h0; // @[Library.scala 8:8]
-  wire [31:0] _data_T_343 = _data_T_340 | _data_T_342; // @[Regfile.scala 154:55]
+  wire [31:0] _data_T_343 = _data_T_340 | _data_T_342; // @[Regfile.scala 155:55]
   wire [31:0] _data_T_345 = valid_21[3] ? io_writeData_3_data : 32'h0; // @[Library.scala 8:8]
-  wire [31:0] _data_T_346 = _data_T_343 | _data_T_345; // @[Regfile.scala 155:55]
+  wire [31:0] _data_T_346 = _data_T_343 | _data_T_345; // @[Regfile.scala 156:55]
   wire [31:0] _data_T_348 = valid_21[4] ? io_writeData_4_data : 32'h0; // @[Library.scala 8:8]
-  wire [31:0] _data_T_349 = _data_T_346 | _data_T_348; // @[Regfile.scala 156:55]
+  wire [31:0] _data_T_349 = _data_T_346 | _data_T_348; // @[Regfile.scala 157:55]
   wire [31:0] _data_T_351 = valid_21[5] ? io_writeData_5_data : 32'h0; // @[Library.scala 8:8]
-  wire [31:0] data_21 = _data_T_349 | _data_T_351; // @[Regfile.scala 157:55]
-  wire  writeValid_22 = valid_21 != 6'h0; // @[Regfile.scala 160:28]
+  wire [31:0] data_21 = _data_T_349 | _data_T_351; // @[Regfile.scala 158:55]
+  wire  writeValid_22 = valid_21 != 6'h0; // @[Regfile.scala 161:28]
   wire [1:0] _T_429 = valid_21[1] + valid_21[2]; // @[Bitwise.scala 48:55]
   wire [1:0] _GEN_83 = {{1'd0}, valid_21[0]}; // @[Bitwise.scala 48:55]
   wire [2:0] _T_431 = _GEN_83 + _T_429; // @[Bitwise.scala 48:55]
@@ -829,25 +831,25 @@
   wire [1:0] _GEN_84 = {{1'd0}, valid_21[3]}; // @[Bitwise.scala 48:55]
   wire [2:0] _T_435 = _GEN_84 + _T_433; // @[Bitwise.scala 48:55]
   wire [2:0] _T_437 = _T_431[1:0] + _T_435[1:0]; // @[Bitwise.scala 48:55]
-  wire  _valid_T_441 = io_writeData_5_valid & io_writeData_5_addr == 5'h17; // @[Regfile.scala 142:43]
-  wire  _valid_T_443 = io_writeData_4_valid & io_writeData_4_addr == 5'h17; // @[Regfile.scala 143:43]
-  wire  _valid_T_447 = io_writeData_3_valid & io_writeData_3_addr == 5'h17 & _valid_T_6; // @[Regfile.scala 144:75]
-  wire  _valid_T_451 = io_writeData_2_valid & io_writeData_2_addr == 5'h17 & _valid_T_10; // @[Regfile.scala 146:75]
-  wire  _valid_T_455 = io_writeData_1_valid & io_writeData_1_addr == 5'h17 & _valid_T_14; // @[Regfile.scala 148:75]
-  wire  _valid_T_457 = io_writeData_0_valid & io_writeData_0_addr == 5'h17; // @[Regfile.scala 150:43]
-  wire [5:0] valid_22 = {_valid_T_441,_valid_T_443,_valid_T_447,_valid_T_451,_valid_T_455,_valid_T_457}; // @[Cat.scala 31:58]
+  wire  _valid_T_485 = io_writeData_5_valid & io_writeData_5_addr == 5'h17; // @[Regfile.scala 142:43]
+  wire  _valid_T_489 = io_writeData_4_valid & io_writeData_4_addr == 5'h17 & _valid_T_4; // @[Regfile.scala 143:75]
+  wire  _valid_T_493 = io_writeData_3_valid & io_writeData_3_addr == 5'h17 & _valid_T_8; // @[Regfile.scala 145:75]
+  wire  _valid_T_497 = io_writeData_2_valid & io_writeData_2_addr == 5'h17 & _valid_T_12; // @[Regfile.scala 147:75]
+  wire  _valid_T_501 = io_writeData_1_valid & io_writeData_1_addr == 5'h17 & _valid_T_16; // @[Regfile.scala 149:75]
+  wire  _valid_T_503 = io_writeData_0_valid & io_writeData_0_addr == 5'h17; // @[Regfile.scala 151:43]
+  wire [5:0] valid_22 = {_valid_T_485,_valid_T_489,_valid_T_493,_valid_T_497,_valid_T_501,_valid_T_503}; // @[Cat.scala 31:58]
   wire [31:0] _data_T_353 = valid_22[0] ? io_writeData_0_data : 32'h0; // @[Library.scala 8:8]
   wire [31:0] _data_T_355 = valid_22[1] ? io_writeData_1_data : 32'h0; // @[Library.scala 8:8]
-  wire [31:0] _data_T_356 = _data_T_353 | _data_T_355; // @[Regfile.scala 153:55]
+  wire [31:0] _data_T_356 = _data_T_353 | _data_T_355; // @[Regfile.scala 154:55]
   wire [31:0] _data_T_358 = valid_22[2] ? io_writeData_2_data : 32'h0; // @[Library.scala 8:8]
-  wire [31:0] _data_T_359 = _data_T_356 | _data_T_358; // @[Regfile.scala 154:55]
+  wire [31:0] _data_T_359 = _data_T_356 | _data_T_358; // @[Regfile.scala 155:55]
   wire [31:0] _data_T_361 = valid_22[3] ? io_writeData_3_data : 32'h0; // @[Library.scala 8:8]
-  wire [31:0] _data_T_362 = _data_T_359 | _data_T_361; // @[Regfile.scala 155:55]
+  wire [31:0] _data_T_362 = _data_T_359 | _data_T_361; // @[Regfile.scala 156:55]
   wire [31:0] _data_T_364 = valid_22[4] ? io_writeData_4_data : 32'h0; // @[Library.scala 8:8]
-  wire [31:0] _data_T_365 = _data_T_362 | _data_T_364; // @[Regfile.scala 156:55]
+  wire [31:0] _data_T_365 = _data_T_362 | _data_T_364; // @[Regfile.scala 157:55]
   wire [31:0] _data_T_367 = valid_22[5] ? io_writeData_5_data : 32'h0; // @[Library.scala 8:8]
-  wire [31:0] data_22 = _data_T_365 | _data_T_367; // @[Regfile.scala 157:55]
-  wire  writeValid_23 = valid_22 != 6'h0; // @[Regfile.scala 160:28]
+  wire [31:0] data_22 = _data_T_365 | _data_T_367; // @[Regfile.scala 158:55]
+  wire  writeValid_23 = valid_22 != 6'h0; // @[Regfile.scala 161:28]
   wire [1:0] _T_449 = valid_22[1] + valid_22[2]; // @[Bitwise.scala 48:55]
   wire [1:0] _GEN_85 = {{1'd0}, valid_22[0]}; // @[Bitwise.scala 48:55]
   wire [2:0] _T_451 = _GEN_85 + _T_449; // @[Bitwise.scala 48:55]
@@ -855,25 +857,25 @@
   wire [1:0] _GEN_86 = {{1'd0}, valid_22[3]}; // @[Bitwise.scala 48:55]
   wire [2:0] _T_455 = _GEN_86 + _T_453; // @[Bitwise.scala 48:55]
   wire [2:0] _T_457 = _T_451[1:0] + _T_455[1:0]; // @[Bitwise.scala 48:55]
-  wire  _valid_T_461 = io_writeData_5_valid & io_writeData_5_addr == 5'h18; // @[Regfile.scala 142:43]
-  wire  _valid_T_463 = io_writeData_4_valid & io_writeData_4_addr == 5'h18; // @[Regfile.scala 143:43]
-  wire  _valid_T_467 = io_writeData_3_valid & io_writeData_3_addr == 5'h18 & _valid_T_6; // @[Regfile.scala 144:75]
-  wire  _valid_T_471 = io_writeData_2_valid & io_writeData_2_addr == 5'h18 & _valid_T_10; // @[Regfile.scala 146:75]
-  wire  _valid_T_475 = io_writeData_1_valid & io_writeData_1_addr == 5'h18 & _valid_T_14; // @[Regfile.scala 148:75]
-  wire  _valid_T_477 = io_writeData_0_valid & io_writeData_0_addr == 5'h18; // @[Regfile.scala 150:43]
-  wire [5:0] valid_23 = {_valid_T_461,_valid_T_463,_valid_T_467,_valid_T_471,_valid_T_475,_valid_T_477}; // @[Cat.scala 31:58]
+  wire  _valid_T_507 = io_writeData_5_valid & io_writeData_5_addr == 5'h18; // @[Regfile.scala 142:43]
+  wire  _valid_T_511 = io_writeData_4_valid & io_writeData_4_addr == 5'h18 & _valid_T_4; // @[Regfile.scala 143:75]
+  wire  _valid_T_515 = io_writeData_3_valid & io_writeData_3_addr == 5'h18 & _valid_T_8; // @[Regfile.scala 145:75]
+  wire  _valid_T_519 = io_writeData_2_valid & io_writeData_2_addr == 5'h18 & _valid_T_12; // @[Regfile.scala 147:75]
+  wire  _valid_T_523 = io_writeData_1_valid & io_writeData_1_addr == 5'h18 & _valid_T_16; // @[Regfile.scala 149:75]
+  wire  _valid_T_525 = io_writeData_0_valid & io_writeData_0_addr == 5'h18; // @[Regfile.scala 151:43]
+  wire [5:0] valid_23 = {_valid_T_507,_valid_T_511,_valid_T_515,_valid_T_519,_valid_T_523,_valid_T_525}; // @[Cat.scala 31:58]
   wire [31:0] _data_T_369 = valid_23[0] ? io_writeData_0_data : 32'h0; // @[Library.scala 8:8]
   wire [31:0] _data_T_371 = valid_23[1] ? io_writeData_1_data : 32'h0; // @[Library.scala 8:8]
-  wire [31:0] _data_T_372 = _data_T_369 | _data_T_371; // @[Regfile.scala 153:55]
+  wire [31:0] _data_T_372 = _data_T_369 | _data_T_371; // @[Regfile.scala 154:55]
   wire [31:0] _data_T_374 = valid_23[2] ? io_writeData_2_data : 32'h0; // @[Library.scala 8:8]
-  wire [31:0] _data_T_375 = _data_T_372 | _data_T_374; // @[Regfile.scala 154:55]
+  wire [31:0] _data_T_375 = _data_T_372 | _data_T_374; // @[Regfile.scala 155:55]
   wire [31:0] _data_T_377 = valid_23[3] ? io_writeData_3_data : 32'h0; // @[Library.scala 8:8]
-  wire [31:0] _data_T_378 = _data_T_375 | _data_T_377; // @[Regfile.scala 155:55]
+  wire [31:0] _data_T_378 = _data_T_375 | _data_T_377; // @[Regfile.scala 156:55]
   wire [31:0] _data_T_380 = valid_23[4] ? io_writeData_4_data : 32'h0; // @[Library.scala 8:8]
-  wire [31:0] _data_T_381 = _data_T_378 | _data_T_380; // @[Regfile.scala 156:55]
+  wire [31:0] _data_T_381 = _data_T_378 | _data_T_380; // @[Regfile.scala 157:55]
   wire [31:0] _data_T_383 = valid_23[5] ? io_writeData_5_data : 32'h0; // @[Library.scala 8:8]
-  wire [31:0] data_23 = _data_T_381 | _data_T_383; // @[Regfile.scala 157:55]
-  wire  writeValid_24 = valid_23 != 6'h0; // @[Regfile.scala 160:28]
+  wire [31:0] data_23 = _data_T_381 | _data_T_383; // @[Regfile.scala 158:55]
+  wire  writeValid_24 = valid_23 != 6'h0; // @[Regfile.scala 161:28]
   wire [1:0] _T_469 = valid_23[1] + valid_23[2]; // @[Bitwise.scala 48:55]
   wire [1:0] _GEN_87 = {{1'd0}, valid_23[0]}; // @[Bitwise.scala 48:55]
   wire [2:0] _T_471 = _GEN_87 + _T_469; // @[Bitwise.scala 48:55]
@@ -881,25 +883,25 @@
   wire [1:0] _GEN_88 = {{1'd0}, valid_23[3]}; // @[Bitwise.scala 48:55]
   wire [2:0] _T_475 = _GEN_88 + _T_473; // @[Bitwise.scala 48:55]
   wire [2:0] _T_477 = _T_471[1:0] + _T_475[1:0]; // @[Bitwise.scala 48:55]
-  wire  _valid_T_481 = io_writeData_5_valid & io_writeData_5_addr == 5'h19; // @[Regfile.scala 142:43]
-  wire  _valid_T_483 = io_writeData_4_valid & io_writeData_4_addr == 5'h19; // @[Regfile.scala 143:43]
-  wire  _valid_T_487 = io_writeData_3_valid & io_writeData_3_addr == 5'h19 & _valid_T_6; // @[Regfile.scala 144:75]
-  wire  _valid_T_491 = io_writeData_2_valid & io_writeData_2_addr == 5'h19 & _valid_T_10; // @[Regfile.scala 146:75]
-  wire  _valid_T_495 = io_writeData_1_valid & io_writeData_1_addr == 5'h19 & _valid_T_14; // @[Regfile.scala 148:75]
-  wire  _valid_T_497 = io_writeData_0_valid & io_writeData_0_addr == 5'h19; // @[Regfile.scala 150:43]
-  wire [5:0] valid_24 = {_valid_T_481,_valid_T_483,_valid_T_487,_valid_T_491,_valid_T_495,_valid_T_497}; // @[Cat.scala 31:58]
+  wire  _valid_T_529 = io_writeData_5_valid & io_writeData_5_addr == 5'h19; // @[Regfile.scala 142:43]
+  wire  _valid_T_533 = io_writeData_4_valid & io_writeData_4_addr == 5'h19 & _valid_T_4; // @[Regfile.scala 143:75]
+  wire  _valid_T_537 = io_writeData_3_valid & io_writeData_3_addr == 5'h19 & _valid_T_8; // @[Regfile.scala 145:75]
+  wire  _valid_T_541 = io_writeData_2_valid & io_writeData_2_addr == 5'h19 & _valid_T_12; // @[Regfile.scala 147:75]
+  wire  _valid_T_545 = io_writeData_1_valid & io_writeData_1_addr == 5'h19 & _valid_T_16; // @[Regfile.scala 149:75]
+  wire  _valid_T_547 = io_writeData_0_valid & io_writeData_0_addr == 5'h19; // @[Regfile.scala 151:43]
+  wire [5:0] valid_24 = {_valid_T_529,_valid_T_533,_valid_T_537,_valid_T_541,_valid_T_545,_valid_T_547}; // @[Cat.scala 31:58]
   wire [31:0] _data_T_385 = valid_24[0] ? io_writeData_0_data : 32'h0; // @[Library.scala 8:8]
   wire [31:0] _data_T_387 = valid_24[1] ? io_writeData_1_data : 32'h0; // @[Library.scala 8:8]
-  wire [31:0] _data_T_388 = _data_T_385 | _data_T_387; // @[Regfile.scala 153:55]
+  wire [31:0] _data_T_388 = _data_T_385 | _data_T_387; // @[Regfile.scala 154:55]
   wire [31:0] _data_T_390 = valid_24[2] ? io_writeData_2_data : 32'h0; // @[Library.scala 8:8]
-  wire [31:0] _data_T_391 = _data_T_388 | _data_T_390; // @[Regfile.scala 154:55]
+  wire [31:0] _data_T_391 = _data_T_388 | _data_T_390; // @[Regfile.scala 155:55]
   wire [31:0] _data_T_393 = valid_24[3] ? io_writeData_3_data : 32'h0; // @[Library.scala 8:8]
-  wire [31:0] _data_T_394 = _data_T_391 | _data_T_393; // @[Regfile.scala 155:55]
+  wire [31:0] _data_T_394 = _data_T_391 | _data_T_393; // @[Regfile.scala 156:55]
   wire [31:0] _data_T_396 = valid_24[4] ? io_writeData_4_data : 32'h0; // @[Library.scala 8:8]
-  wire [31:0] _data_T_397 = _data_T_394 | _data_T_396; // @[Regfile.scala 156:55]
+  wire [31:0] _data_T_397 = _data_T_394 | _data_T_396; // @[Regfile.scala 157:55]
   wire [31:0] _data_T_399 = valid_24[5] ? io_writeData_5_data : 32'h0; // @[Library.scala 8:8]
-  wire [31:0] data_24 = _data_T_397 | _data_T_399; // @[Regfile.scala 157:55]
-  wire  writeValid_25 = valid_24 != 6'h0; // @[Regfile.scala 160:28]
+  wire [31:0] data_24 = _data_T_397 | _data_T_399; // @[Regfile.scala 158:55]
+  wire  writeValid_25 = valid_24 != 6'h0; // @[Regfile.scala 161:28]
   wire [1:0] _T_489 = valid_24[1] + valid_24[2]; // @[Bitwise.scala 48:55]
   wire [1:0] _GEN_89 = {{1'd0}, valid_24[0]}; // @[Bitwise.scala 48:55]
   wire [2:0] _T_491 = _GEN_89 + _T_489; // @[Bitwise.scala 48:55]
@@ -907,25 +909,25 @@
   wire [1:0] _GEN_90 = {{1'd0}, valid_24[3]}; // @[Bitwise.scala 48:55]
   wire [2:0] _T_495 = _GEN_90 + _T_493; // @[Bitwise.scala 48:55]
   wire [2:0] _T_497 = _T_491[1:0] + _T_495[1:0]; // @[Bitwise.scala 48:55]
-  wire  _valid_T_501 = io_writeData_5_valid & io_writeData_5_addr == 5'h1a; // @[Regfile.scala 142:43]
-  wire  _valid_T_503 = io_writeData_4_valid & io_writeData_4_addr == 5'h1a; // @[Regfile.scala 143:43]
-  wire  _valid_T_507 = io_writeData_3_valid & io_writeData_3_addr == 5'h1a & _valid_T_6; // @[Regfile.scala 144:75]
-  wire  _valid_T_511 = io_writeData_2_valid & io_writeData_2_addr == 5'h1a & _valid_T_10; // @[Regfile.scala 146:75]
-  wire  _valid_T_515 = io_writeData_1_valid & io_writeData_1_addr == 5'h1a & _valid_T_14; // @[Regfile.scala 148:75]
-  wire  _valid_T_517 = io_writeData_0_valid & io_writeData_0_addr == 5'h1a; // @[Regfile.scala 150:43]
-  wire [5:0] valid_25 = {_valid_T_501,_valid_T_503,_valid_T_507,_valid_T_511,_valid_T_515,_valid_T_517}; // @[Cat.scala 31:58]
+  wire  _valid_T_551 = io_writeData_5_valid & io_writeData_5_addr == 5'h1a; // @[Regfile.scala 142:43]
+  wire  _valid_T_555 = io_writeData_4_valid & io_writeData_4_addr == 5'h1a & _valid_T_4; // @[Regfile.scala 143:75]
+  wire  _valid_T_559 = io_writeData_3_valid & io_writeData_3_addr == 5'h1a & _valid_T_8; // @[Regfile.scala 145:75]
+  wire  _valid_T_563 = io_writeData_2_valid & io_writeData_2_addr == 5'h1a & _valid_T_12; // @[Regfile.scala 147:75]
+  wire  _valid_T_567 = io_writeData_1_valid & io_writeData_1_addr == 5'h1a & _valid_T_16; // @[Regfile.scala 149:75]
+  wire  _valid_T_569 = io_writeData_0_valid & io_writeData_0_addr == 5'h1a; // @[Regfile.scala 151:43]
+  wire [5:0] valid_25 = {_valid_T_551,_valid_T_555,_valid_T_559,_valid_T_563,_valid_T_567,_valid_T_569}; // @[Cat.scala 31:58]
   wire [31:0] _data_T_401 = valid_25[0] ? io_writeData_0_data : 32'h0; // @[Library.scala 8:8]
   wire [31:0] _data_T_403 = valid_25[1] ? io_writeData_1_data : 32'h0; // @[Library.scala 8:8]
-  wire [31:0] _data_T_404 = _data_T_401 | _data_T_403; // @[Regfile.scala 153:55]
+  wire [31:0] _data_T_404 = _data_T_401 | _data_T_403; // @[Regfile.scala 154:55]
   wire [31:0] _data_T_406 = valid_25[2] ? io_writeData_2_data : 32'h0; // @[Library.scala 8:8]
-  wire [31:0] _data_T_407 = _data_T_404 | _data_T_406; // @[Regfile.scala 154:55]
+  wire [31:0] _data_T_407 = _data_T_404 | _data_T_406; // @[Regfile.scala 155:55]
   wire [31:0] _data_T_409 = valid_25[3] ? io_writeData_3_data : 32'h0; // @[Library.scala 8:8]
-  wire [31:0] _data_T_410 = _data_T_407 | _data_T_409; // @[Regfile.scala 155:55]
+  wire [31:0] _data_T_410 = _data_T_407 | _data_T_409; // @[Regfile.scala 156:55]
   wire [31:0] _data_T_412 = valid_25[4] ? io_writeData_4_data : 32'h0; // @[Library.scala 8:8]
-  wire [31:0] _data_T_413 = _data_T_410 | _data_T_412; // @[Regfile.scala 156:55]
+  wire [31:0] _data_T_413 = _data_T_410 | _data_T_412; // @[Regfile.scala 157:55]
   wire [31:0] _data_T_415 = valid_25[5] ? io_writeData_5_data : 32'h0; // @[Library.scala 8:8]
-  wire [31:0] data_25 = _data_T_413 | _data_T_415; // @[Regfile.scala 157:55]
-  wire  writeValid_26 = valid_25 != 6'h0; // @[Regfile.scala 160:28]
+  wire [31:0] data_25 = _data_T_413 | _data_T_415; // @[Regfile.scala 158:55]
+  wire  writeValid_26 = valid_25 != 6'h0; // @[Regfile.scala 161:28]
   wire [1:0] _T_509 = valid_25[1] + valid_25[2]; // @[Bitwise.scala 48:55]
   wire [1:0] _GEN_91 = {{1'd0}, valid_25[0]}; // @[Bitwise.scala 48:55]
   wire [2:0] _T_511 = _GEN_91 + _T_509; // @[Bitwise.scala 48:55]
@@ -933,25 +935,25 @@
   wire [1:0] _GEN_92 = {{1'd0}, valid_25[3]}; // @[Bitwise.scala 48:55]
   wire [2:0] _T_515 = _GEN_92 + _T_513; // @[Bitwise.scala 48:55]
   wire [2:0] _T_517 = _T_511[1:0] + _T_515[1:0]; // @[Bitwise.scala 48:55]
-  wire  _valid_T_521 = io_writeData_5_valid & io_writeData_5_addr == 5'h1b; // @[Regfile.scala 142:43]
-  wire  _valid_T_523 = io_writeData_4_valid & io_writeData_4_addr == 5'h1b; // @[Regfile.scala 143:43]
-  wire  _valid_T_527 = io_writeData_3_valid & io_writeData_3_addr == 5'h1b & _valid_T_6; // @[Regfile.scala 144:75]
-  wire  _valid_T_531 = io_writeData_2_valid & io_writeData_2_addr == 5'h1b & _valid_T_10; // @[Regfile.scala 146:75]
-  wire  _valid_T_535 = io_writeData_1_valid & io_writeData_1_addr == 5'h1b & _valid_T_14; // @[Regfile.scala 148:75]
-  wire  _valid_T_537 = io_writeData_0_valid & io_writeData_0_addr == 5'h1b; // @[Regfile.scala 150:43]
-  wire [5:0] valid_26 = {_valid_T_521,_valid_T_523,_valid_T_527,_valid_T_531,_valid_T_535,_valid_T_537}; // @[Cat.scala 31:58]
+  wire  _valid_T_573 = io_writeData_5_valid & io_writeData_5_addr == 5'h1b; // @[Regfile.scala 142:43]
+  wire  _valid_T_577 = io_writeData_4_valid & io_writeData_4_addr == 5'h1b & _valid_T_4; // @[Regfile.scala 143:75]
+  wire  _valid_T_581 = io_writeData_3_valid & io_writeData_3_addr == 5'h1b & _valid_T_8; // @[Regfile.scala 145:75]
+  wire  _valid_T_585 = io_writeData_2_valid & io_writeData_2_addr == 5'h1b & _valid_T_12; // @[Regfile.scala 147:75]
+  wire  _valid_T_589 = io_writeData_1_valid & io_writeData_1_addr == 5'h1b & _valid_T_16; // @[Regfile.scala 149:75]
+  wire  _valid_T_591 = io_writeData_0_valid & io_writeData_0_addr == 5'h1b; // @[Regfile.scala 151:43]
+  wire [5:0] valid_26 = {_valid_T_573,_valid_T_577,_valid_T_581,_valid_T_585,_valid_T_589,_valid_T_591}; // @[Cat.scala 31:58]
   wire [31:0] _data_T_417 = valid_26[0] ? io_writeData_0_data : 32'h0; // @[Library.scala 8:8]
   wire [31:0] _data_T_419 = valid_26[1] ? io_writeData_1_data : 32'h0; // @[Library.scala 8:8]
-  wire [31:0] _data_T_420 = _data_T_417 | _data_T_419; // @[Regfile.scala 153:55]
+  wire [31:0] _data_T_420 = _data_T_417 | _data_T_419; // @[Regfile.scala 154:55]
   wire [31:0] _data_T_422 = valid_26[2] ? io_writeData_2_data : 32'h0; // @[Library.scala 8:8]
-  wire [31:0] _data_T_423 = _data_T_420 | _data_T_422; // @[Regfile.scala 154:55]
+  wire [31:0] _data_T_423 = _data_T_420 | _data_T_422; // @[Regfile.scala 155:55]
   wire [31:0] _data_T_425 = valid_26[3] ? io_writeData_3_data : 32'h0; // @[Library.scala 8:8]
-  wire [31:0] _data_T_426 = _data_T_423 | _data_T_425; // @[Regfile.scala 155:55]
+  wire [31:0] _data_T_426 = _data_T_423 | _data_T_425; // @[Regfile.scala 156:55]
   wire [31:0] _data_T_428 = valid_26[4] ? io_writeData_4_data : 32'h0; // @[Library.scala 8:8]
-  wire [31:0] _data_T_429 = _data_T_426 | _data_T_428; // @[Regfile.scala 156:55]
+  wire [31:0] _data_T_429 = _data_T_426 | _data_T_428; // @[Regfile.scala 157:55]
   wire [31:0] _data_T_431 = valid_26[5] ? io_writeData_5_data : 32'h0; // @[Library.scala 8:8]
-  wire [31:0] data_26 = _data_T_429 | _data_T_431; // @[Regfile.scala 157:55]
-  wire  writeValid_27 = valid_26 != 6'h0; // @[Regfile.scala 160:28]
+  wire [31:0] data_26 = _data_T_429 | _data_T_431; // @[Regfile.scala 158:55]
+  wire  writeValid_27 = valid_26 != 6'h0; // @[Regfile.scala 161:28]
   wire [1:0] _T_529 = valid_26[1] + valid_26[2]; // @[Bitwise.scala 48:55]
   wire [1:0] _GEN_93 = {{1'd0}, valid_26[0]}; // @[Bitwise.scala 48:55]
   wire [2:0] _T_531 = _GEN_93 + _T_529; // @[Bitwise.scala 48:55]
@@ -959,25 +961,25 @@
   wire [1:0] _GEN_94 = {{1'd0}, valid_26[3]}; // @[Bitwise.scala 48:55]
   wire [2:0] _T_535 = _GEN_94 + _T_533; // @[Bitwise.scala 48:55]
   wire [2:0] _T_537 = _T_531[1:0] + _T_535[1:0]; // @[Bitwise.scala 48:55]
-  wire  _valid_T_541 = io_writeData_5_valid & io_writeData_5_addr == 5'h1c; // @[Regfile.scala 142:43]
-  wire  _valid_T_543 = io_writeData_4_valid & io_writeData_4_addr == 5'h1c; // @[Regfile.scala 143:43]
-  wire  _valid_T_547 = io_writeData_3_valid & io_writeData_3_addr == 5'h1c & _valid_T_6; // @[Regfile.scala 144:75]
-  wire  _valid_T_551 = io_writeData_2_valid & io_writeData_2_addr == 5'h1c & _valid_T_10; // @[Regfile.scala 146:75]
-  wire  _valid_T_555 = io_writeData_1_valid & io_writeData_1_addr == 5'h1c & _valid_T_14; // @[Regfile.scala 148:75]
-  wire  _valid_T_557 = io_writeData_0_valid & io_writeData_0_addr == 5'h1c; // @[Regfile.scala 150:43]
-  wire [5:0] valid_27 = {_valid_T_541,_valid_T_543,_valid_T_547,_valid_T_551,_valid_T_555,_valid_T_557}; // @[Cat.scala 31:58]
+  wire  _valid_T_595 = io_writeData_5_valid & io_writeData_5_addr == 5'h1c; // @[Regfile.scala 142:43]
+  wire  _valid_T_599 = io_writeData_4_valid & io_writeData_4_addr == 5'h1c & _valid_T_4; // @[Regfile.scala 143:75]
+  wire  _valid_T_603 = io_writeData_3_valid & io_writeData_3_addr == 5'h1c & _valid_T_8; // @[Regfile.scala 145:75]
+  wire  _valid_T_607 = io_writeData_2_valid & io_writeData_2_addr == 5'h1c & _valid_T_12; // @[Regfile.scala 147:75]
+  wire  _valid_T_611 = io_writeData_1_valid & io_writeData_1_addr == 5'h1c & _valid_T_16; // @[Regfile.scala 149:75]
+  wire  _valid_T_613 = io_writeData_0_valid & io_writeData_0_addr == 5'h1c; // @[Regfile.scala 151:43]
+  wire [5:0] valid_27 = {_valid_T_595,_valid_T_599,_valid_T_603,_valid_T_607,_valid_T_611,_valid_T_613}; // @[Cat.scala 31:58]
   wire [31:0] _data_T_433 = valid_27[0] ? io_writeData_0_data : 32'h0; // @[Library.scala 8:8]
   wire [31:0] _data_T_435 = valid_27[1] ? io_writeData_1_data : 32'h0; // @[Library.scala 8:8]
-  wire [31:0] _data_T_436 = _data_T_433 | _data_T_435; // @[Regfile.scala 153:55]
+  wire [31:0] _data_T_436 = _data_T_433 | _data_T_435; // @[Regfile.scala 154:55]
   wire [31:0] _data_T_438 = valid_27[2] ? io_writeData_2_data : 32'h0; // @[Library.scala 8:8]
-  wire [31:0] _data_T_439 = _data_T_436 | _data_T_438; // @[Regfile.scala 154:55]
+  wire [31:0] _data_T_439 = _data_T_436 | _data_T_438; // @[Regfile.scala 155:55]
   wire [31:0] _data_T_441 = valid_27[3] ? io_writeData_3_data : 32'h0; // @[Library.scala 8:8]
-  wire [31:0] _data_T_442 = _data_T_439 | _data_T_441; // @[Regfile.scala 155:55]
+  wire [31:0] _data_T_442 = _data_T_439 | _data_T_441; // @[Regfile.scala 156:55]
   wire [31:0] _data_T_444 = valid_27[4] ? io_writeData_4_data : 32'h0; // @[Library.scala 8:8]
-  wire [31:0] _data_T_445 = _data_T_442 | _data_T_444; // @[Regfile.scala 156:55]
+  wire [31:0] _data_T_445 = _data_T_442 | _data_T_444; // @[Regfile.scala 157:55]
   wire [31:0] _data_T_447 = valid_27[5] ? io_writeData_5_data : 32'h0; // @[Library.scala 8:8]
-  wire [31:0] data_27 = _data_T_445 | _data_T_447; // @[Regfile.scala 157:55]
-  wire  writeValid_28 = valid_27 != 6'h0; // @[Regfile.scala 160:28]
+  wire [31:0] data_27 = _data_T_445 | _data_T_447; // @[Regfile.scala 158:55]
+  wire  writeValid_28 = valid_27 != 6'h0; // @[Regfile.scala 161:28]
   wire [1:0] _T_549 = valid_27[1] + valid_27[2]; // @[Bitwise.scala 48:55]
   wire [1:0] _GEN_95 = {{1'd0}, valid_27[0]}; // @[Bitwise.scala 48:55]
   wire [2:0] _T_551 = _GEN_95 + _T_549; // @[Bitwise.scala 48:55]
@@ -985,25 +987,25 @@
   wire [1:0] _GEN_96 = {{1'd0}, valid_27[3]}; // @[Bitwise.scala 48:55]
   wire [2:0] _T_555 = _GEN_96 + _T_553; // @[Bitwise.scala 48:55]
   wire [2:0] _T_557 = _T_551[1:0] + _T_555[1:0]; // @[Bitwise.scala 48:55]
-  wire  _valid_T_561 = io_writeData_5_valid & io_writeData_5_addr == 5'h1d; // @[Regfile.scala 142:43]
-  wire  _valid_T_563 = io_writeData_4_valid & io_writeData_4_addr == 5'h1d; // @[Regfile.scala 143:43]
-  wire  _valid_T_567 = io_writeData_3_valid & io_writeData_3_addr == 5'h1d & _valid_T_6; // @[Regfile.scala 144:75]
-  wire  _valid_T_571 = io_writeData_2_valid & io_writeData_2_addr == 5'h1d & _valid_T_10; // @[Regfile.scala 146:75]
-  wire  _valid_T_575 = io_writeData_1_valid & io_writeData_1_addr == 5'h1d & _valid_T_14; // @[Regfile.scala 148:75]
-  wire  _valid_T_577 = io_writeData_0_valid & io_writeData_0_addr == 5'h1d; // @[Regfile.scala 150:43]
-  wire [5:0] valid_28 = {_valid_T_561,_valid_T_563,_valid_T_567,_valid_T_571,_valid_T_575,_valid_T_577}; // @[Cat.scala 31:58]
+  wire  _valid_T_617 = io_writeData_5_valid & io_writeData_5_addr == 5'h1d; // @[Regfile.scala 142:43]
+  wire  _valid_T_621 = io_writeData_4_valid & io_writeData_4_addr == 5'h1d & _valid_T_4; // @[Regfile.scala 143:75]
+  wire  _valid_T_625 = io_writeData_3_valid & io_writeData_3_addr == 5'h1d & _valid_T_8; // @[Regfile.scala 145:75]
+  wire  _valid_T_629 = io_writeData_2_valid & io_writeData_2_addr == 5'h1d & _valid_T_12; // @[Regfile.scala 147:75]
+  wire  _valid_T_633 = io_writeData_1_valid & io_writeData_1_addr == 5'h1d & _valid_T_16; // @[Regfile.scala 149:75]
+  wire  _valid_T_635 = io_writeData_0_valid & io_writeData_0_addr == 5'h1d; // @[Regfile.scala 151:43]
+  wire [5:0] valid_28 = {_valid_T_617,_valid_T_621,_valid_T_625,_valid_T_629,_valid_T_633,_valid_T_635}; // @[Cat.scala 31:58]
   wire [31:0] _data_T_449 = valid_28[0] ? io_writeData_0_data : 32'h0; // @[Library.scala 8:8]
   wire [31:0] _data_T_451 = valid_28[1] ? io_writeData_1_data : 32'h0; // @[Library.scala 8:8]
-  wire [31:0] _data_T_452 = _data_T_449 | _data_T_451; // @[Regfile.scala 153:55]
+  wire [31:0] _data_T_452 = _data_T_449 | _data_T_451; // @[Regfile.scala 154:55]
   wire [31:0] _data_T_454 = valid_28[2] ? io_writeData_2_data : 32'h0; // @[Library.scala 8:8]
-  wire [31:0] _data_T_455 = _data_T_452 | _data_T_454; // @[Regfile.scala 154:55]
+  wire [31:0] _data_T_455 = _data_T_452 | _data_T_454; // @[Regfile.scala 155:55]
   wire [31:0] _data_T_457 = valid_28[3] ? io_writeData_3_data : 32'h0; // @[Library.scala 8:8]
-  wire [31:0] _data_T_458 = _data_T_455 | _data_T_457; // @[Regfile.scala 155:55]
+  wire [31:0] _data_T_458 = _data_T_455 | _data_T_457; // @[Regfile.scala 156:55]
   wire [31:0] _data_T_460 = valid_28[4] ? io_writeData_4_data : 32'h0; // @[Library.scala 8:8]
-  wire [31:0] _data_T_461 = _data_T_458 | _data_T_460; // @[Regfile.scala 156:55]
+  wire [31:0] _data_T_461 = _data_T_458 | _data_T_460; // @[Regfile.scala 157:55]
   wire [31:0] _data_T_463 = valid_28[5] ? io_writeData_5_data : 32'h0; // @[Library.scala 8:8]
-  wire [31:0] data_28 = _data_T_461 | _data_T_463; // @[Regfile.scala 157:55]
-  wire  writeValid_29 = valid_28 != 6'h0; // @[Regfile.scala 160:28]
+  wire [31:0] data_28 = _data_T_461 | _data_T_463; // @[Regfile.scala 158:55]
+  wire  writeValid_29 = valid_28 != 6'h0; // @[Regfile.scala 161:28]
   wire [1:0] _T_569 = valid_28[1] + valid_28[2]; // @[Bitwise.scala 48:55]
   wire [1:0] _GEN_97 = {{1'd0}, valid_28[0]}; // @[Bitwise.scala 48:55]
   wire [2:0] _T_571 = _GEN_97 + _T_569; // @[Bitwise.scala 48:55]
@@ -1011,25 +1013,25 @@
   wire [1:0] _GEN_98 = {{1'd0}, valid_28[3]}; // @[Bitwise.scala 48:55]
   wire [2:0] _T_575 = _GEN_98 + _T_573; // @[Bitwise.scala 48:55]
   wire [2:0] _T_577 = _T_571[1:0] + _T_575[1:0]; // @[Bitwise.scala 48:55]
-  wire  _valid_T_581 = io_writeData_5_valid & io_writeData_5_addr == 5'h1e; // @[Regfile.scala 142:43]
-  wire  _valid_T_583 = io_writeData_4_valid & io_writeData_4_addr == 5'h1e; // @[Regfile.scala 143:43]
-  wire  _valid_T_587 = io_writeData_3_valid & io_writeData_3_addr == 5'h1e & _valid_T_6; // @[Regfile.scala 144:75]
-  wire  _valid_T_591 = io_writeData_2_valid & io_writeData_2_addr == 5'h1e & _valid_T_10; // @[Regfile.scala 146:75]
-  wire  _valid_T_595 = io_writeData_1_valid & io_writeData_1_addr == 5'h1e & _valid_T_14; // @[Regfile.scala 148:75]
-  wire  _valid_T_597 = io_writeData_0_valid & io_writeData_0_addr == 5'h1e; // @[Regfile.scala 150:43]
-  wire [5:0] valid_29 = {_valid_T_581,_valid_T_583,_valid_T_587,_valid_T_591,_valid_T_595,_valid_T_597}; // @[Cat.scala 31:58]
+  wire  _valid_T_639 = io_writeData_5_valid & io_writeData_5_addr == 5'h1e; // @[Regfile.scala 142:43]
+  wire  _valid_T_643 = io_writeData_4_valid & io_writeData_4_addr == 5'h1e & _valid_T_4; // @[Regfile.scala 143:75]
+  wire  _valid_T_647 = io_writeData_3_valid & io_writeData_3_addr == 5'h1e & _valid_T_8; // @[Regfile.scala 145:75]
+  wire  _valid_T_651 = io_writeData_2_valid & io_writeData_2_addr == 5'h1e & _valid_T_12; // @[Regfile.scala 147:75]
+  wire  _valid_T_655 = io_writeData_1_valid & io_writeData_1_addr == 5'h1e & _valid_T_16; // @[Regfile.scala 149:75]
+  wire  _valid_T_657 = io_writeData_0_valid & io_writeData_0_addr == 5'h1e; // @[Regfile.scala 151:43]
+  wire [5:0] valid_29 = {_valid_T_639,_valid_T_643,_valid_T_647,_valid_T_651,_valid_T_655,_valid_T_657}; // @[Cat.scala 31:58]
   wire [31:0] _data_T_465 = valid_29[0] ? io_writeData_0_data : 32'h0; // @[Library.scala 8:8]
   wire [31:0] _data_T_467 = valid_29[1] ? io_writeData_1_data : 32'h0; // @[Library.scala 8:8]
-  wire [31:0] _data_T_468 = _data_T_465 | _data_T_467; // @[Regfile.scala 153:55]
+  wire [31:0] _data_T_468 = _data_T_465 | _data_T_467; // @[Regfile.scala 154:55]
   wire [31:0] _data_T_470 = valid_29[2] ? io_writeData_2_data : 32'h0; // @[Library.scala 8:8]
-  wire [31:0] _data_T_471 = _data_T_468 | _data_T_470; // @[Regfile.scala 154:55]
+  wire [31:0] _data_T_471 = _data_T_468 | _data_T_470; // @[Regfile.scala 155:55]
   wire [31:0] _data_T_473 = valid_29[3] ? io_writeData_3_data : 32'h0; // @[Library.scala 8:8]
-  wire [31:0] _data_T_474 = _data_T_471 | _data_T_473; // @[Regfile.scala 155:55]
+  wire [31:0] _data_T_474 = _data_T_471 | _data_T_473; // @[Regfile.scala 156:55]
   wire [31:0] _data_T_476 = valid_29[4] ? io_writeData_4_data : 32'h0; // @[Library.scala 8:8]
-  wire [31:0] _data_T_477 = _data_T_474 | _data_T_476; // @[Regfile.scala 156:55]
+  wire [31:0] _data_T_477 = _data_T_474 | _data_T_476; // @[Regfile.scala 157:55]
   wire [31:0] _data_T_479 = valid_29[5] ? io_writeData_5_data : 32'h0; // @[Library.scala 8:8]
-  wire [31:0] data_29 = _data_T_477 | _data_T_479; // @[Regfile.scala 157:55]
-  wire  writeValid_30 = valid_29 != 6'h0; // @[Regfile.scala 160:28]
+  wire [31:0] data_29 = _data_T_477 | _data_T_479; // @[Regfile.scala 158:55]
+  wire  writeValid_30 = valid_29 != 6'h0; // @[Regfile.scala 161:28]
   wire [1:0] _T_589 = valid_29[1] + valid_29[2]; // @[Bitwise.scala 48:55]
   wire [1:0] _GEN_99 = {{1'd0}, valid_29[0]}; // @[Bitwise.scala 48:55]
   wire [2:0] _T_591 = _GEN_99 + _T_589; // @[Bitwise.scala 48:55]
@@ -1037,25 +1039,25 @@
   wire [1:0] _GEN_100 = {{1'd0}, valid_29[3]}; // @[Bitwise.scala 48:55]
   wire [2:0] _T_595 = _GEN_100 + _T_593; // @[Bitwise.scala 48:55]
   wire [2:0] _T_597 = _T_591[1:0] + _T_595[1:0]; // @[Bitwise.scala 48:55]
-  wire  _valid_T_601 = io_writeData_5_valid & io_writeData_5_addr == 5'h1f; // @[Regfile.scala 142:43]
-  wire  _valid_T_603 = io_writeData_4_valid & io_writeData_4_addr == 5'h1f; // @[Regfile.scala 143:43]
-  wire  _valid_T_607 = io_writeData_3_valid & io_writeData_3_addr == 5'h1f & _valid_T_6; // @[Regfile.scala 144:75]
-  wire  _valid_T_611 = io_writeData_2_valid & io_writeData_2_addr == 5'h1f & _valid_T_10; // @[Regfile.scala 146:75]
-  wire  _valid_T_615 = io_writeData_1_valid & io_writeData_1_addr == 5'h1f & _valid_T_14; // @[Regfile.scala 148:75]
-  wire  _valid_T_617 = io_writeData_0_valid & io_writeData_0_addr == 5'h1f; // @[Regfile.scala 150:43]
-  wire [5:0] valid_30 = {_valid_T_601,_valid_T_603,_valid_T_607,_valid_T_611,_valid_T_615,_valid_T_617}; // @[Cat.scala 31:58]
+  wire  _valid_T_661 = io_writeData_5_valid & io_writeData_5_addr == 5'h1f; // @[Regfile.scala 142:43]
+  wire  _valid_T_665 = io_writeData_4_valid & io_writeData_4_addr == 5'h1f & _valid_T_4; // @[Regfile.scala 143:75]
+  wire  _valid_T_669 = io_writeData_3_valid & io_writeData_3_addr == 5'h1f & _valid_T_8; // @[Regfile.scala 145:75]
+  wire  _valid_T_673 = io_writeData_2_valid & io_writeData_2_addr == 5'h1f & _valid_T_12; // @[Regfile.scala 147:75]
+  wire  _valid_T_677 = io_writeData_1_valid & io_writeData_1_addr == 5'h1f & _valid_T_16; // @[Regfile.scala 149:75]
+  wire  _valid_T_679 = io_writeData_0_valid & io_writeData_0_addr == 5'h1f; // @[Regfile.scala 151:43]
+  wire [5:0] valid_30 = {_valid_T_661,_valid_T_665,_valid_T_669,_valid_T_673,_valid_T_677,_valid_T_679}; // @[Cat.scala 31:58]
   wire [31:0] _data_T_481 = valid_30[0] ? io_writeData_0_data : 32'h0; // @[Library.scala 8:8]
   wire [31:0] _data_T_483 = valid_30[1] ? io_writeData_1_data : 32'h0; // @[Library.scala 8:8]
-  wire [31:0] _data_T_484 = _data_T_481 | _data_T_483; // @[Regfile.scala 153:55]
+  wire [31:0] _data_T_484 = _data_T_481 | _data_T_483; // @[Regfile.scala 154:55]
   wire [31:0] _data_T_486 = valid_30[2] ? io_writeData_2_data : 32'h0; // @[Library.scala 8:8]
-  wire [31:0] _data_T_487 = _data_T_484 | _data_T_486; // @[Regfile.scala 154:55]
+  wire [31:0] _data_T_487 = _data_T_484 | _data_T_486; // @[Regfile.scala 155:55]
   wire [31:0] _data_T_489 = valid_30[3] ? io_writeData_3_data : 32'h0; // @[Library.scala 8:8]
-  wire [31:0] _data_T_490 = _data_T_487 | _data_T_489; // @[Regfile.scala 155:55]
+  wire [31:0] _data_T_490 = _data_T_487 | _data_T_489; // @[Regfile.scala 156:55]
   wire [31:0] _data_T_492 = valid_30[4] ? io_writeData_4_data : 32'h0; // @[Library.scala 8:8]
-  wire [31:0] _data_T_493 = _data_T_490 | _data_T_492; // @[Regfile.scala 156:55]
+  wire [31:0] _data_T_493 = _data_T_490 | _data_T_492; // @[Regfile.scala 157:55]
   wire [31:0] _data_T_495 = valid_30[5] ? io_writeData_5_data : 32'h0; // @[Library.scala 8:8]
-  wire [31:0] data_30 = _data_T_493 | _data_T_495; // @[Regfile.scala 157:55]
-  wire  writeValid_31 = valid_30 != 6'h0; // @[Regfile.scala 160:28]
+  wire [31:0] data_30 = _data_T_493 | _data_T_495; // @[Regfile.scala 158:55]
+  wire  writeValid_31 = valid_30 != 6'h0; // @[Regfile.scala 161:28]
   wire [1:0] _T_609 = valid_30[1] + valid_30[2]; // @[Bitwise.scala 48:55]
   wire [1:0] _GEN_101 = {{1'd0}, valid_30[0]}; // @[Bitwise.scala 48:55]
   wire [2:0] _T_611 = _GEN_101 + _T_609; // @[Bitwise.scala 48:55]
@@ -1248,7 +1250,7 @@
   wire [31:0] wdata_0_value_4_0 = wdata_0_value_3_0 | wdata_0_value_3_1; // @[Library.scala 115:37]
   wire [31:0] wdata_0_value_4_1 = wdata_0_value_3_2 | wdata_0_value_3_3; // @[Library.scala 115:37]
   wire [31:0] wdata_0_value_5_0 = wdata_0_value_4_0 | wdata_0_value_4_1; // @[Library.scala 115:37]
-  wire [31:0] rwdata_0 = write_value_5_0 ? wdata_0_value_5_0 : rdata_0_value_5_0; // @[Regfile.scala 183:21]
+  wire [31:0] rwdata_0 = write_value_5_0 ? wdata_0_value_5_0 : rdata_0_value_5_0; // @[Regfile.scala 184:21]
   wire  write_value_6_0 = 5'h0 == io_readAddr_1_addr; // @[Library.scala 101:27]
   wire  write_value_6_1 = 5'h1 == io_readAddr_1_addr & writeValid_1; // @[Library.scala 101:22]
   wire  write_value_6_2 = 5'h2 == io_readAddr_1_addr & writeValid_2; // @[Library.scala 101:22]
@@ -1434,7 +1436,7 @@
   wire [31:0] wdata_1_value_4_0 = wdata_1_value_3_0 | wdata_1_value_3_1; // @[Library.scala 115:37]
   wire [31:0] wdata_1_value_4_1 = wdata_1_value_3_2 | wdata_1_value_3_3; // @[Library.scala 115:37]
   wire [31:0] wdata_1_value_5_0 = wdata_1_value_4_0 | wdata_1_value_4_1; // @[Library.scala 115:37]
-  wire [31:0] rwdata_1 = write_value_11_0 ? wdata_1_value_5_0 : rdata_1_value_5_0; // @[Regfile.scala 183:21]
+  wire [31:0] rwdata_1 = write_value_11_0 ? wdata_1_value_5_0 : rdata_1_value_5_0; // @[Regfile.scala 184:21]
   wire  write_value_12_0 = 5'h0 == io_readAddr_2_addr; // @[Library.scala 101:27]
   wire  write_value_12_1 = 5'h1 == io_readAddr_2_addr & writeValid_1; // @[Library.scala 101:22]
   wire  write_value_12_2 = 5'h2 == io_readAddr_2_addr & writeValid_2; // @[Library.scala 101:22]
@@ -1620,7 +1622,7 @@
   wire [31:0] wdata_2_value_4_0 = wdata_2_value_3_0 | wdata_2_value_3_1; // @[Library.scala 115:37]
   wire [31:0] wdata_2_value_4_1 = wdata_2_value_3_2 | wdata_2_value_3_3; // @[Library.scala 115:37]
   wire [31:0] wdata_2_value_5_0 = wdata_2_value_4_0 | wdata_2_value_4_1; // @[Library.scala 115:37]
-  wire [31:0] rwdata_2 = write_value_17_0 ? wdata_2_value_5_0 : rdata_2_value_5_0; // @[Regfile.scala 183:21]
+  wire [31:0] rwdata_2 = write_value_17_0 ? wdata_2_value_5_0 : rdata_2_value_5_0; // @[Regfile.scala 184:21]
   wire  write_value_18_0 = 5'h0 == io_readAddr_3_addr; // @[Library.scala 101:27]
   wire  write_value_18_1 = 5'h1 == io_readAddr_3_addr & writeValid_1; // @[Library.scala 101:22]
   wire  write_value_18_2 = 5'h2 == io_readAddr_3_addr & writeValid_2; // @[Library.scala 101:22]
@@ -1806,7 +1808,7 @@
   wire [31:0] wdata_3_value_4_0 = wdata_3_value_3_0 | wdata_3_value_3_1; // @[Library.scala 115:37]
   wire [31:0] wdata_3_value_4_1 = wdata_3_value_3_2 | wdata_3_value_3_3; // @[Library.scala 115:37]
   wire [31:0] wdata_3_value_5_0 = wdata_3_value_4_0 | wdata_3_value_4_1; // @[Library.scala 115:37]
-  wire [31:0] rwdata_3 = write_value_23_0 ? wdata_3_value_5_0 : rdata_3_value_5_0; // @[Regfile.scala 183:21]
+  wire [31:0] rwdata_3 = write_value_23_0 ? wdata_3_value_5_0 : rdata_3_value_5_0; // @[Regfile.scala 184:21]
   wire  write_value_24_0 = 5'h0 == io_readAddr_4_addr; // @[Library.scala 101:27]
   wire  write_value_24_1 = 5'h1 == io_readAddr_4_addr & writeValid_1; // @[Library.scala 101:22]
   wire  write_value_24_2 = 5'h2 == io_readAddr_4_addr & writeValid_2; // @[Library.scala 101:22]
@@ -1992,7 +1994,7 @@
   wire [31:0] wdata_4_value_4_0 = wdata_4_value_3_0 | wdata_4_value_3_1; // @[Library.scala 115:37]
   wire [31:0] wdata_4_value_4_1 = wdata_4_value_3_2 | wdata_4_value_3_3; // @[Library.scala 115:37]
   wire [31:0] wdata_4_value_5_0 = wdata_4_value_4_0 | wdata_4_value_4_1; // @[Library.scala 115:37]
-  wire [31:0] rwdata_4 = write_value_29_0 ? wdata_4_value_5_0 : rdata_4_value_5_0; // @[Regfile.scala 183:21]
+  wire [31:0] rwdata_4 = write_value_29_0 ? wdata_4_value_5_0 : rdata_4_value_5_0; // @[Regfile.scala 184:21]
   wire  write_value_30_0 = 5'h0 == io_readAddr_5_addr; // @[Library.scala 101:27]
   wire  write_value_30_1 = 5'h1 == io_readAddr_5_addr & writeValid_1; // @[Library.scala 101:22]
   wire  write_value_30_2 = 5'h2 == io_readAddr_5_addr & writeValid_2; // @[Library.scala 101:22]
@@ -2178,7 +2180,7 @@
   wire [31:0] wdata_5_value_4_0 = wdata_5_value_3_0 | wdata_5_value_3_1; // @[Library.scala 115:37]
   wire [31:0] wdata_5_value_4_1 = wdata_5_value_3_2 | wdata_5_value_3_3; // @[Library.scala 115:37]
   wire [31:0] wdata_5_value_5_0 = wdata_5_value_4_0 | wdata_5_value_4_1; // @[Library.scala 115:37]
-  wire [31:0] rwdata_5 = write_value_35_0 ? wdata_5_value_5_0 : rdata_5_value_5_0; // @[Regfile.scala 183:21]
+  wire [31:0] rwdata_5 = write_value_35_0 ? wdata_5_value_5_0 : rdata_5_value_5_0; // @[Regfile.scala 184:21]
   wire  write_value_36_0 = 5'h0 == io_readAddr_6_addr; // @[Library.scala 101:27]
   wire  write_value_36_1 = 5'h1 == io_readAddr_6_addr & writeValid_1; // @[Library.scala 101:22]
   wire  write_value_36_2 = 5'h2 == io_readAddr_6_addr & writeValid_2; // @[Library.scala 101:22]
@@ -2364,7 +2366,7 @@
   wire [31:0] wdata_6_value_4_0 = wdata_6_value_3_0 | wdata_6_value_3_1; // @[Library.scala 115:37]
   wire [31:0] wdata_6_value_4_1 = wdata_6_value_3_2 | wdata_6_value_3_3; // @[Library.scala 115:37]
   wire [31:0] wdata_6_value_5_0 = wdata_6_value_4_0 | wdata_6_value_4_1; // @[Library.scala 115:37]
-  wire [31:0] rwdata_6 = write_value_41_0 ? wdata_6_value_5_0 : rdata_6_value_5_0; // @[Regfile.scala 183:21]
+  wire [31:0] rwdata_6 = write_value_41_0 ? wdata_6_value_5_0 : rdata_6_value_5_0; // @[Regfile.scala 184:21]
   wire  write_value_42_0 = 5'h0 == io_readAddr_7_addr; // @[Library.scala 101:27]
   wire  write_value_42_1 = 5'h1 == io_readAddr_7_addr & writeValid_1; // @[Library.scala 101:22]
   wire  write_value_42_2 = 5'h2 == io_readAddr_7_addr & writeValid_2; // @[Library.scala 101:22]
@@ -2550,86 +2552,86 @@
   wire [31:0] wdata_7_value_4_0 = wdata_7_value_3_0 | wdata_7_value_3_1; // @[Library.scala 115:37]
   wire [31:0] wdata_7_value_4_1 = wdata_7_value_3_2 | wdata_7_value_3_3; // @[Library.scala 115:37]
   wire [31:0] wdata_7_value_5_0 = wdata_7_value_4_0 | wdata_7_value_4_1; // @[Library.scala 115:37]
-  wire [31:0] rwdata_7 = write_value_47_0 ? wdata_7_value_5_0 : rdata_7_value_5_0; // @[Regfile.scala 183:21]
-  wire  nxtReadDataReady = io_readAddr_0_valid | io_readSet_0_valid; // @[Regfile.scala 190:49]
-  wire  nxtReadDataReady_1 = io_readAddr_1_valid | io_readSet_1_valid; // @[Regfile.scala 190:49]
-  wire  nxtReadDataReady_2 = io_readAddr_2_valid | io_readSet_2_valid; // @[Regfile.scala 190:49]
-  wire  nxtReadDataReady_3 = io_readAddr_3_valid | io_readSet_3_valid; // @[Regfile.scala 190:49]
-  wire  nxtReadDataReady_4 = io_readAddr_4_valid | io_readSet_4_valid; // @[Regfile.scala 190:49]
-  wire  nxtReadDataReady_5 = io_readAddr_5_valid | io_readSet_5_valid; // @[Regfile.scala 190:49]
-  wire  nxtReadDataReady_6 = io_readAddr_6_valid | io_readSet_6_valid; // @[Regfile.scala 190:49]
-  wire  nxtReadDataReady_7 = io_readAddr_7_valid | io_readSet_7_valid; // @[Regfile.scala 190:49]
-  wire [31:0] _busAddr_0_T_1 = rdata_0_value_5_0 + io_busAddr_0_immed; // @[Regfile.scala 208:57]
-  wire [31:0] _busAddr_0_T_2 = io_busAddr_0_immen ? _busAddr_0_T_1 : rdata_0_value_5_0; // @[Regfile.scala 208:22]
-  wire [31:0] _busAddr_1_T_1 = rdata_2_value_5_0 + io_busAddr_1_immed; // @[Regfile.scala 208:57]
-  wire [31:0] _busAddr_2_T_1 = rdata_4_value_5_0 + io_busAddr_2_immed; // @[Regfile.scala 208:57]
-  wire [31:0] _busAddr_3_T_1 = rdata_6_value_5_0 + io_busAddr_3_immed; // @[Regfile.scala 208:57]
-  reg  write_fail; // @[Regfile.scala 238:31]
-  wire  _write_fail_T_1 = io_writeData_0_addr == io_writeData_1_addr; // @[Regfile.scala 240:42]
-  wire  _write_fail_T_2 = io_writeData_0_valid & io_writeData_1_valid & _write_fail_T_1; // @[Regfile.scala 239:68]
-  wire  _write_fail_T_3 = io_writeData_0_addr != 5'h0; // @[Regfile.scala 241:42]
-  reg  write_fail_1; // @[Regfile.scala 238:31]
-  wire  _write_fail_T_6 = io_writeData_0_addr == io_writeData_2_addr; // @[Regfile.scala 240:42]
-  wire  _write_fail_T_7 = io_writeData_0_valid & io_writeData_2_valid & _write_fail_T_6; // @[Regfile.scala 239:68]
-  reg  write_fail_2; // @[Regfile.scala 238:31]
-  wire  _write_fail_T_11 = io_writeData_0_addr == io_writeData_3_addr; // @[Regfile.scala 240:42]
-  wire  _write_fail_T_12 = io_writeData_0_valid & io_writeData_3_valid & _write_fail_T_11; // @[Regfile.scala 239:68]
-  reg  write_fail_3; // @[Regfile.scala 238:31]
-  wire  _write_fail_T_16 = io_writeData_0_addr == io_writeData_4_addr; // @[Regfile.scala 240:42]
-  wire  _write_fail_T_17 = io_writeData_0_valid & io_writeData_4_valid & _write_fail_T_16; // @[Regfile.scala 239:68]
-  reg  write_fail_4; // @[Regfile.scala 238:31]
-  wire  _write_fail_T_21 = io_writeData_0_addr == io_writeData_5_addr; // @[Regfile.scala 240:42]
-  wire  _write_fail_T_22 = io_writeData_0_valid & io_writeData_5_valid & _write_fail_T_21; // @[Regfile.scala 239:68]
-  reg  write_fail_5; // @[Regfile.scala 238:31]
-  wire  _write_fail_T_26 = io_writeData_1_addr == io_writeData_2_addr; // @[Regfile.scala 240:42]
-  wire  _write_fail_T_27 = io_writeData_1_valid & io_writeData_2_valid & _write_fail_T_26; // @[Regfile.scala 239:68]
-  wire  _write_fail_T_28 = io_writeData_1_addr != 5'h0; // @[Regfile.scala 241:42]
-  reg  write_fail_6; // @[Regfile.scala 238:31]
-  wire  _write_fail_T_31 = io_writeData_1_addr == io_writeData_3_addr; // @[Regfile.scala 240:42]
-  wire  _write_fail_T_32 = io_writeData_1_valid & io_writeData_3_valid & _write_fail_T_31; // @[Regfile.scala 239:68]
-  reg  write_fail_7; // @[Regfile.scala 238:31]
-  wire  _write_fail_T_36 = io_writeData_1_addr == io_writeData_4_addr; // @[Regfile.scala 240:42]
-  wire  _write_fail_T_37 = io_writeData_1_valid & io_writeData_4_valid & _write_fail_T_36; // @[Regfile.scala 239:68]
-  reg  write_fail_8; // @[Regfile.scala 238:31]
-  wire  _write_fail_T_41 = io_writeData_1_addr == io_writeData_5_addr; // @[Regfile.scala 240:42]
-  wire  _write_fail_T_42 = io_writeData_1_valid & io_writeData_5_valid & _write_fail_T_41; // @[Regfile.scala 239:68]
-  reg  write_fail_9; // @[Regfile.scala 238:31]
-  wire  _write_fail_T_46 = io_writeData_2_addr == io_writeData_3_addr; // @[Regfile.scala 240:42]
-  wire  _write_fail_T_47 = io_writeData_2_valid & io_writeData_3_valid & _write_fail_T_46; // @[Regfile.scala 239:68]
-  wire  _write_fail_T_48 = io_writeData_2_addr != 5'h0; // @[Regfile.scala 241:42]
-  reg  write_fail_10; // @[Regfile.scala 238:31]
-  wire  _write_fail_T_51 = io_writeData_2_addr == io_writeData_4_addr; // @[Regfile.scala 240:42]
-  wire  _write_fail_T_52 = io_writeData_2_valid & io_writeData_4_valid & _write_fail_T_51; // @[Regfile.scala 239:68]
-  reg  write_fail_11; // @[Regfile.scala 238:31]
-  wire  _write_fail_T_56 = io_writeData_2_addr == io_writeData_5_addr; // @[Regfile.scala 240:42]
-  wire  _write_fail_T_57 = io_writeData_2_valid & io_writeData_5_valid & _write_fail_T_56; // @[Regfile.scala 239:68]
-  reg  write_fail_12; // @[Regfile.scala 238:31]
-  wire  _write_fail_T_61 = io_writeData_3_addr == io_writeData_4_addr; // @[Regfile.scala 240:42]
-  wire  _write_fail_T_62 = io_writeData_3_valid & io_writeData_4_valid & _write_fail_T_61; // @[Regfile.scala 239:68]
-  wire  _write_fail_T_63 = io_writeData_3_addr != 5'h0; // @[Regfile.scala 241:42]
-  reg  write_fail_13; // @[Regfile.scala 238:31]
-  wire  _write_fail_T_66 = io_writeData_3_addr == io_writeData_5_addr; // @[Regfile.scala 240:42]
-  wire  _write_fail_T_67 = io_writeData_3_valid & io_writeData_5_valid & _write_fail_T_66; // @[Regfile.scala 239:68]
-  reg  write_fail_14; // @[Regfile.scala 238:31]
-  wire  _write_fail_T_71 = io_writeData_4_addr == io_writeData_5_addr; // @[Regfile.scala 240:42]
-  wire  _write_fail_T_72 = io_writeData_4_valid & io_writeData_5_valid & _write_fail_T_71; // @[Regfile.scala 239:68]
-  wire  _write_fail_T_73 = io_writeData_4_addr != 5'h0; // @[Regfile.scala 241:42]
-  reg  scoreboard_error; // @[Regfile.scala 246:33]
-  wire [31:0] _scoreboard_error_T = scoreboard & scoreboard_clr; // @[Regfile.scala 247:35]
-  assign io_target_0_data = io_busAddr_0_bypass ? rwdata_0 : _busAddr_0_T_2; // @[Regfile.scala 207:22]
-  assign io_target_1_data = io_busAddr_1_bypass ? rwdata_2 : _busAddr_1_T_1; // @[Regfile.scala 207:22]
-  assign io_target_2_data = io_busAddr_2_bypass ? rwdata_4 : _busAddr_2_T_1; // @[Regfile.scala 207:22]
-  assign io_target_3_data = io_busAddr_3_bypass ? rwdata_6 : _busAddr_3_T_1; // @[Regfile.scala 207:22]
-  assign io_linkPort_valid = ~scoreboard[1]; // @[Regfile.scala 225:24]
-  assign io_linkPort_value = regfile_1; // @[Regfile.scala 226:21]
-  assign io_busPort_addr_0 = io_busAddr_0_bypass ? rwdata_0 : _busAddr_0_T_2; // @[Regfile.scala 207:22]
-  assign io_busPort_addr_1 = io_busAddr_1_bypass ? rwdata_2 : _busAddr_1_T_1; // @[Regfile.scala 207:22]
-  assign io_busPort_addr_2 = io_busAddr_2_bypass ? rwdata_4 : _busAddr_2_T_1; // @[Regfile.scala 207:22]
-  assign io_busPort_addr_3 = io_busAddr_3_bypass ? rwdata_6 : _busAddr_3_T_1; // @[Regfile.scala 207:22]
-  assign io_busPort_data_0 = io_readSet_1_valid ? io_readSet_1_value : rwdata_1; // @[Regfile.scala 194:30]
-  assign io_busPort_data_1 = io_readSet_3_valid ? io_readSet_3_value : rwdata_3; // @[Regfile.scala 194:30]
-  assign io_busPort_data_2 = io_readSet_5_valid ? io_readSet_5_value : rwdata_5; // @[Regfile.scala 194:30]
-  assign io_busPort_data_3 = io_readSet_7_valid ? io_readSet_7_value : rwdata_7; // @[Regfile.scala 194:30]
+  wire [31:0] rwdata_7 = write_value_47_0 ? wdata_7_value_5_0 : rdata_7_value_5_0; // @[Regfile.scala 184:21]
+  wire  nxtReadDataReady = io_readAddr_0_valid | io_readSet_0_valid; // @[Regfile.scala 191:49]
+  wire  nxtReadDataReady_1 = io_readAddr_1_valid | io_readSet_1_valid; // @[Regfile.scala 191:49]
+  wire  nxtReadDataReady_2 = io_readAddr_2_valid | io_readSet_2_valid; // @[Regfile.scala 191:49]
+  wire  nxtReadDataReady_3 = io_readAddr_3_valid | io_readSet_3_valid; // @[Regfile.scala 191:49]
+  wire  nxtReadDataReady_4 = io_readAddr_4_valid | io_readSet_4_valid; // @[Regfile.scala 191:49]
+  wire  nxtReadDataReady_5 = io_readAddr_5_valid | io_readSet_5_valid; // @[Regfile.scala 191:49]
+  wire  nxtReadDataReady_6 = io_readAddr_6_valid | io_readSet_6_valid; // @[Regfile.scala 191:49]
+  wire  nxtReadDataReady_7 = io_readAddr_7_valid | io_readSet_7_valid; // @[Regfile.scala 191:49]
+  wire [31:0] _busAddr_0_T_1 = rdata_0_value_5_0 + io_busAddr_0_immed; // @[Regfile.scala 209:57]
+  wire [31:0] _busAddr_0_T_2 = io_busAddr_0_immen ? _busAddr_0_T_1 : rdata_0_value_5_0; // @[Regfile.scala 209:22]
+  wire [31:0] _busAddr_1_T_1 = rdata_2_value_5_0 + io_busAddr_1_immed; // @[Regfile.scala 209:57]
+  wire [31:0] _busAddr_2_T_1 = rdata_4_value_5_0 + io_busAddr_2_immed; // @[Regfile.scala 209:57]
+  wire [31:0] _busAddr_3_T_1 = rdata_6_value_5_0 + io_busAddr_3_immed; // @[Regfile.scala 209:57]
+  reg  write_fail; // @[Regfile.scala 239:31]
+  wire  _write_fail_T_1 = io_writeData_0_addr == io_writeData_1_addr; // @[Regfile.scala 241:42]
+  wire  _write_fail_T_2 = io_writeData_0_valid & io_writeData_1_valid & _write_fail_T_1; // @[Regfile.scala 240:68]
+  wire  _write_fail_T_3 = io_writeData_0_addr != 5'h0; // @[Regfile.scala 242:42]
+  reg  write_fail_1; // @[Regfile.scala 239:31]
+  wire  _write_fail_T_6 = io_writeData_0_addr == io_writeData_2_addr; // @[Regfile.scala 241:42]
+  wire  _write_fail_T_7 = io_writeData_0_valid & io_writeData_2_valid & _write_fail_T_6; // @[Regfile.scala 240:68]
+  reg  write_fail_2; // @[Regfile.scala 239:31]
+  wire  _write_fail_T_11 = io_writeData_0_addr == io_writeData_3_addr; // @[Regfile.scala 241:42]
+  wire  _write_fail_T_12 = io_writeData_0_valid & io_writeData_3_valid & _write_fail_T_11; // @[Regfile.scala 240:68]
+  reg  write_fail_3; // @[Regfile.scala 239:31]
+  wire  _write_fail_T_16 = io_writeData_0_addr == io_writeData_4_addr; // @[Regfile.scala 241:42]
+  wire  _write_fail_T_17 = io_writeData_0_valid & io_writeData_4_valid & _write_fail_T_16; // @[Regfile.scala 240:68]
+  reg  write_fail_4; // @[Regfile.scala 239:31]
+  wire  _write_fail_T_21 = io_writeData_0_addr == io_writeData_5_addr; // @[Regfile.scala 241:42]
+  wire  _write_fail_T_22 = io_writeData_0_valid & io_writeData_5_valid & _write_fail_T_21; // @[Regfile.scala 240:68]
+  reg  write_fail_5; // @[Regfile.scala 239:31]
+  wire  _write_fail_T_26 = io_writeData_1_addr == io_writeData_2_addr; // @[Regfile.scala 241:42]
+  wire  _write_fail_T_27 = io_writeData_1_valid & io_writeData_2_valid & _write_fail_T_26; // @[Regfile.scala 240:68]
+  wire  _write_fail_T_28 = io_writeData_1_addr != 5'h0; // @[Regfile.scala 242:42]
+  reg  write_fail_6; // @[Regfile.scala 239:31]
+  wire  _write_fail_T_31 = io_writeData_1_addr == io_writeData_3_addr; // @[Regfile.scala 241:42]
+  wire  _write_fail_T_32 = io_writeData_1_valid & io_writeData_3_valid & _write_fail_T_31; // @[Regfile.scala 240:68]
+  reg  write_fail_7; // @[Regfile.scala 239:31]
+  wire  _write_fail_T_36 = io_writeData_1_addr == io_writeData_4_addr; // @[Regfile.scala 241:42]
+  wire  _write_fail_T_37 = io_writeData_1_valid & io_writeData_4_valid & _write_fail_T_36; // @[Regfile.scala 240:68]
+  reg  write_fail_8; // @[Regfile.scala 239:31]
+  wire  _write_fail_T_41 = io_writeData_1_addr == io_writeData_5_addr; // @[Regfile.scala 241:42]
+  wire  _write_fail_T_42 = io_writeData_1_valid & io_writeData_5_valid & _write_fail_T_41; // @[Regfile.scala 240:68]
+  reg  write_fail_9; // @[Regfile.scala 239:31]
+  wire  _write_fail_T_46 = io_writeData_2_addr == io_writeData_3_addr; // @[Regfile.scala 241:42]
+  wire  _write_fail_T_47 = io_writeData_2_valid & io_writeData_3_valid & _write_fail_T_46; // @[Regfile.scala 240:68]
+  wire  _write_fail_T_48 = io_writeData_2_addr != 5'h0; // @[Regfile.scala 242:42]
+  reg  write_fail_10; // @[Regfile.scala 239:31]
+  wire  _write_fail_T_51 = io_writeData_2_addr == io_writeData_4_addr; // @[Regfile.scala 241:42]
+  wire  _write_fail_T_52 = io_writeData_2_valid & io_writeData_4_valid & _write_fail_T_51; // @[Regfile.scala 240:68]
+  reg  write_fail_11; // @[Regfile.scala 239:31]
+  wire  _write_fail_T_56 = io_writeData_2_addr == io_writeData_5_addr; // @[Regfile.scala 241:42]
+  wire  _write_fail_T_57 = io_writeData_2_valid & io_writeData_5_valid & _write_fail_T_56; // @[Regfile.scala 240:68]
+  reg  write_fail_12; // @[Regfile.scala 239:31]
+  wire  _write_fail_T_61 = io_writeData_3_addr == io_writeData_4_addr; // @[Regfile.scala 241:42]
+  wire  _write_fail_T_62 = io_writeData_3_valid & io_writeData_4_valid & _write_fail_T_61; // @[Regfile.scala 240:68]
+  wire  _write_fail_T_63 = io_writeData_3_addr != 5'h0; // @[Regfile.scala 242:42]
+  reg  write_fail_13; // @[Regfile.scala 239:31]
+  wire  _write_fail_T_66 = io_writeData_3_addr == io_writeData_5_addr; // @[Regfile.scala 241:42]
+  wire  _write_fail_T_67 = io_writeData_3_valid & io_writeData_5_valid & _write_fail_T_66; // @[Regfile.scala 240:68]
+  reg  write_fail_14; // @[Regfile.scala 239:31]
+  wire  _write_fail_T_71 = io_writeData_4_addr == io_writeData_5_addr; // @[Regfile.scala 241:42]
+  wire  _write_fail_T_72 = io_writeData_4_valid & io_writeData_5_valid & _write_fail_T_71; // @[Regfile.scala 240:68]
+  wire  _write_fail_T_73 = io_writeData_4_addr != 5'h0; // @[Regfile.scala 242:42]
+  reg  scoreboard_error; // @[Regfile.scala 247:33]
+  wire [31:0] _scoreboard_error_T = scoreboard & scoreboard_clr; // @[Regfile.scala 248:35]
+  assign io_target_0_data = io_busAddr_0_bypass ? rwdata_0 : _busAddr_0_T_2; // @[Regfile.scala 208:22]
+  assign io_target_1_data = io_busAddr_1_bypass ? rwdata_2 : _busAddr_1_T_1; // @[Regfile.scala 208:22]
+  assign io_target_2_data = io_busAddr_2_bypass ? rwdata_4 : _busAddr_2_T_1; // @[Regfile.scala 208:22]
+  assign io_target_3_data = io_busAddr_3_bypass ? rwdata_6 : _busAddr_3_T_1; // @[Regfile.scala 208:22]
+  assign io_linkPort_valid = ~scoreboard[1]; // @[Regfile.scala 226:24]
+  assign io_linkPort_value = regfile_1; // @[Regfile.scala 227:21]
+  assign io_busPort_addr_0 = io_busAddr_0_bypass ? rwdata_0 : _busAddr_0_T_2; // @[Regfile.scala 208:22]
+  assign io_busPort_addr_1 = io_busAddr_1_bypass ? rwdata_2 : _busAddr_1_T_1; // @[Regfile.scala 208:22]
+  assign io_busPort_addr_2 = io_busAddr_2_bypass ? rwdata_4 : _busAddr_2_T_1; // @[Regfile.scala 208:22]
+  assign io_busPort_addr_3 = io_busAddr_3_bypass ? rwdata_6 : _busAddr_3_T_1; // @[Regfile.scala 208:22]
+  assign io_busPort_data_0 = io_readSet_1_valid ? io_readSet_1_value : rwdata_1; // @[Regfile.scala 195:30]
+  assign io_busPort_data_1 = io_readSet_3_valid ? io_readSet_3_value : rwdata_3; // @[Regfile.scala 195:30]
+  assign io_busPort_data_2 = io_readSet_5_valid ? io_readSet_5_value : rwdata_5; // @[Regfile.scala 195:30]
+  assign io_busPort_data_3 = io_readSet_7_valid ? io_readSet_7_value : rwdata_7; // @[Regfile.scala 195:30]
   assign io_readData_0_valid = readDataReady_0; // @[Regfile.scala 128:26]
   assign io_readData_0_data = readDataBits_0; // @[Regfile.scala 129:26]
   assign io_readData_1_valid = readDataReady_1; // @[Regfile.scala 128:26]
@@ -2649,166 +2651,166 @@
   assign io_scoreboard_regd = scoreboard; // @[Regfile.scala 117:22]
   assign io_scoreboard_comb = scoreboard & _nxtScoreboard_T; // @[Regfile.scala 118:36]
   always @(posedge clock) begin
-    if (writeValid_1) begin // @[Regfile.scala 167:26]
-      regfile_1 <= data; // @[Regfile.scala 168:18]
+    if (writeValid_1) begin // @[Regfile.scala 168:26]
+      regfile_1 <= data; // @[Regfile.scala 169:18]
     end
-    if (writeValid_2) begin // @[Regfile.scala 167:26]
-      regfile_2 <= data_1; // @[Regfile.scala 168:18]
+    if (writeValid_2) begin // @[Regfile.scala 168:26]
+      regfile_2 <= data_1; // @[Regfile.scala 169:18]
     end
-    if (writeValid_3) begin // @[Regfile.scala 167:26]
-      regfile_3 <= data_2; // @[Regfile.scala 168:18]
+    if (writeValid_3) begin // @[Regfile.scala 168:26]
+      regfile_3 <= data_2; // @[Regfile.scala 169:18]
     end
-    if (writeValid_4) begin // @[Regfile.scala 167:26]
-      regfile_4 <= data_3; // @[Regfile.scala 168:18]
+    if (writeValid_4) begin // @[Regfile.scala 168:26]
+      regfile_4 <= data_3; // @[Regfile.scala 169:18]
     end
-    if (writeValid_5) begin // @[Regfile.scala 167:26]
-      regfile_5 <= data_4; // @[Regfile.scala 168:18]
+    if (writeValid_5) begin // @[Regfile.scala 168:26]
+      regfile_5 <= data_4; // @[Regfile.scala 169:18]
     end
-    if (writeValid_6) begin // @[Regfile.scala 167:26]
-      regfile_6 <= data_5; // @[Regfile.scala 168:18]
+    if (writeValid_6) begin // @[Regfile.scala 168:26]
+      regfile_6 <= data_5; // @[Regfile.scala 169:18]
     end
-    if (writeValid_7) begin // @[Regfile.scala 167:26]
-      regfile_7 <= data_6; // @[Regfile.scala 168:18]
+    if (writeValid_7) begin // @[Regfile.scala 168:26]
+      regfile_7 <= data_6; // @[Regfile.scala 169:18]
     end
-    if (writeValid_8) begin // @[Regfile.scala 167:26]
-      regfile_8 <= data_7; // @[Regfile.scala 168:18]
+    if (writeValid_8) begin // @[Regfile.scala 168:26]
+      regfile_8 <= data_7; // @[Regfile.scala 169:18]
     end
-    if (writeValid_9) begin // @[Regfile.scala 167:26]
-      regfile_9 <= data_8; // @[Regfile.scala 168:18]
+    if (writeValid_9) begin // @[Regfile.scala 168:26]
+      regfile_9 <= data_8; // @[Regfile.scala 169:18]
     end
-    if (writeValid_10) begin // @[Regfile.scala 167:26]
-      regfile_10 <= data_9; // @[Regfile.scala 168:18]
+    if (writeValid_10) begin // @[Regfile.scala 168:26]
+      regfile_10 <= data_9; // @[Regfile.scala 169:18]
     end
-    if (writeValid_11) begin // @[Regfile.scala 167:26]
-      regfile_11 <= data_10; // @[Regfile.scala 168:18]
+    if (writeValid_11) begin // @[Regfile.scala 168:26]
+      regfile_11 <= data_10; // @[Regfile.scala 169:18]
     end
-    if (writeValid_12) begin // @[Regfile.scala 167:26]
-      regfile_12 <= data_11; // @[Regfile.scala 168:18]
+    if (writeValid_12) begin // @[Regfile.scala 168:26]
+      regfile_12 <= data_11; // @[Regfile.scala 169:18]
     end
-    if (writeValid_13) begin // @[Regfile.scala 167:26]
-      regfile_13 <= data_12; // @[Regfile.scala 168:18]
+    if (writeValid_13) begin // @[Regfile.scala 168:26]
+      regfile_13 <= data_12; // @[Regfile.scala 169:18]
     end
-    if (writeValid_14) begin // @[Regfile.scala 167:26]
-      regfile_14 <= data_13; // @[Regfile.scala 168:18]
+    if (writeValid_14) begin // @[Regfile.scala 168:26]
+      regfile_14 <= data_13; // @[Regfile.scala 169:18]
     end
-    if (writeValid_15) begin // @[Regfile.scala 167:26]
-      regfile_15 <= data_14; // @[Regfile.scala 168:18]
+    if (writeValid_15) begin // @[Regfile.scala 168:26]
+      regfile_15 <= data_14; // @[Regfile.scala 169:18]
     end
-    if (writeValid_16) begin // @[Regfile.scala 167:26]
-      regfile_16 <= data_15; // @[Regfile.scala 168:18]
+    if (writeValid_16) begin // @[Regfile.scala 168:26]
+      regfile_16 <= data_15; // @[Regfile.scala 169:18]
     end
-    if (writeValid_17) begin // @[Regfile.scala 167:26]
-      regfile_17 <= data_16; // @[Regfile.scala 168:18]
+    if (writeValid_17) begin // @[Regfile.scala 168:26]
+      regfile_17 <= data_16; // @[Regfile.scala 169:18]
     end
-    if (writeValid_18) begin // @[Regfile.scala 167:26]
-      regfile_18 <= data_17; // @[Regfile.scala 168:18]
+    if (writeValid_18) begin // @[Regfile.scala 168:26]
+      regfile_18 <= data_17; // @[Regfile.scala 169:18]
     end
-    if (writeValid_19) begin // @[Regfile.scala 167:26]
-      regfile_19 <= data_18; // @[Regfile.scala 168:18]
+    if (writeValid_19) begin // @[Regfile.scala 168:26]
+      regfile_19 <= data_18; // @[Regfile.scala 169:18]
     end
-    if (writeValid_20) begin // @[Regfile.scala 167:26]
-      regfile_20 <= data_19; // @[Regfile.scala 168:18]
+    if (writeValid_20) begin // @[Regfile.scala 168:26]
+      regfile_20 <= data_19; // @[Regfile.scala 169:18]
     end
-    if (writeValid_21) begin // @[Regfile.scala 167:26]
-      regfile_21 <= data_20; // @[Regfile.scala 168:18]
+    if (writeValid_21) begin // @[Regfile.scala 168:26]
+      regfile_21 <= data_20; // @[Regfile.scala 169:18]
     end
-    if (writeValid_22) begin // @[Regfile.scala 167:26]
-      regfile_22 <= data_21; // @[Regfile.scala 168:18]
+    if (writeValid_22) begin // @[Regfile.scala 168:26]
+      regfile_22 <= data_21; // @[Regfile.scala 169:18]
     end
-    if (writeValid_23) begin // @[Regfile.scala 167:26]
-      regfile_23 <= data_22; // @[Regfile.scala 168:18]
+    if (writeValid_23) begin // @[Regfile.scala 168:26]
+      regfile_23 <= data_22; // @[Regfile.scala 169:18]
     end
-    if (writeValid_24) begin // @[Regfile.scala 167:26]
-      regfile_24 <= data_23; // @[Regfile.scala 168:18]
+    if (writeValid_24) begin // @[Regfile.scala 168:26]
+      regfile_24 <= data_23; // @[Regfile.scala 169:18]
     end
-    if (writeValid_25) begin // @[Regfile.scala 167:26]
-      regfile_25 <= data_24; // @[Regfile.scala 168:18]
+    if (writeValid_25) begin // @[Regfile.scala 168:26]
+      regfile_25 <= data_24; // @[Regfile.scala 169:18]
     end
-    if (writeValid_26) begin // @[Regfile.scala 167:26]
-      regfile_26 <= data_25; // @[Regfile.scala 168:18]
+    if (writeValid_26) begin // @[Regfile.scala 168:26]
+      regfile_26 <= data_25; // @[Regfile.scala 169:18]
     end
-    if (writeValid_27) begin // @[Regfile.scala 167:26]
-      regfile_27 <= data_26; // @[Regfile.scala 168:18]
+    if (writeValid_27) begin // @[Regfile.scala 168:26]
+      regfile_27 <= data_26; // @[Regfile.scala 169:18]
     end
-    if (writeValid_28) begin // @[Regfile.scala 167:26]
-      regfile_28 <= data_27; // @[Regfile.scala 168:18]
+    if (writeValid_28) begin // @[Regfile.scala 168:26]
+      regfile_28 <= data_27; // @[Regfile.scala 169:18]
     end
-    if (writeValid_29) begin // @[Regfile.scala 167:26]
-      regfile_29 <= data_28; // @[Regfile.scala 168:18]
+    if (writeValid_29) begin // @[Regfile.scala 168:26]
+      regfile_29 <= data_28; // @[Regfile.scala 169:18]
     end
-    if (writeValid_30) begin // @[Regfile.scala 167:26]
-      regfile_30 <= data_29; // @[Regfile.scala 168:18]
+    if (writeValid_30) begin // @[Regfile.scala 168:26]
+      regfile_30 <= data_29; // @[Regfile.scala 169:18]
     end
-    if (writeValid_31) begin // @[Regfile.scala 167:26]
-      regfile_31 <= data_30; // @[Regfile.scala 168:18]
+    if (writeValid_31) begin // @[Regfile.scala 168:26]
+      regfile_31 <= data_30; // @[Regfile.scala 169:18]
     end
-    if (nxtReadDataReady) begin // @[Regfile.scala 196:29]
-      if (io_readSet_0_valid) begin // @[Regfile.scala 194:30]
+    if (nxtReadDataReady) begin // @[Regfile.scala 197:29]
+      if (io_readSet_0_valid) begin // @[Regfile.scala 195:30]
         readDataBits_0 <= io_readSet_0_value;
-      end else if (write_value_5_0) begin // @[Regfile.scala 183:21]
+      end else if (write_value_5_0) begin // @[Regfile.scala 184:21]
         readDataBits_0 <= wdata_0_value_5_0;
       end else begin
         readDataBits_0 <= rdata_0_value_5_0;
       end
     end
-    if (nxtReadDataReady_1) begin // @[Regfile.scala 196:29]
-      if (io_readSet_1_valid) begin // @[Regfile.scala 194:30]
+    if (nxtReadDataReady_1) begin // @[Regfile.scala 197:29]
+      if (io_readSet_1_valid) begin // @[Regfile.scala 195:30]
         readDataBits_1 <= io_readSet_1_value;
-      end else if (write_value_11_0) begin // @[Regfile.scala 183:21]
+      end else if (write_value_11_0) begin // @[Regfile.scala 184:21]
         readDataBits_1 <= wdata_1_value_5_0;
       end else begin
         readDataBits_1 <= rdata_1_value_5_0;
       end
     end
-    if (nxtReadDataReady_2) begin // @[Regfile.scala 196:29]
-      if (io_readSet_2_valid) begin // @[Regfile.scala 194:30]
+    if (nxtReadDataReady_2) begin // @[Regfile.scala 197:29]
+      if (io_readSet_2_valid) begin // @[Regfile.scala 195:30]
         readDataBits_2 <= io_readSet_2_value;
-      end else if (write_value_17_0) begin // @[Regfile.scala 183:21]
+      end else if (write_value_17_0) begin // @[Regfile.scala 184:21]
         readDataBits_2 <= wdata_2_value_5_0;
       end else begin
         readDataBits_2 <= rdata_2_value_5_0;
       end
     end
-    if (nxtReadDataReady_3) begin // @[Regfile.scala 196:29]
-      if (io_readSet_3_valid) begin // @[Regfile.scala 194:30]
+    if (nxtReadDataReady_3) begin // @[Regfile.scala 197:29]
+      if (io_readSet_3_valid) begin // @[Regfile.scala 195:30]
         readDataBits_3 <= io_readSet_3_value;
-      end else if (write_value_23_0) begin // @[Regfile.scala 183:21]
+      end else if (write_value_23_0) begin // @[Regfile.scala 184:21]
         readDataBits_3 <= wdata_3_value_5_0;
       end else begin
         readDataBits_3 <= rdata_3_value_5_0;
       end
     end
-    if (nxtReadDataReady_4) begin // @[Regfile.scala 196:29]
-      if (io_readSet_4_valid) begin // @[Regfile.scala 194:30]
+    if (nxtReadDataReady_4) begin // @[Regfile.scala 197:29]
+      if (io_readSet_4_valid) begin // @[Regfile.scala 195:30]
         readDataBits_4 <= io_readSet_4_value;
-      end else if (write_value_29_0) begin // @[Regfile.scala 183:21]
+      end else if (write_value_29_0) begin // @[Regfile.scala 184:21]
         readDataBits_4 <= wdata_4_value_5_0;
       end else begin
         readDataBits_4 <= rdata_4_value_5_0;
       end
     end
-    if (nxtReadDataReady_5) begin // @[Regfile.scala 196:29]
-      if (io_readSet_5_valid) begin // @[Regfile.scala 194:30]
+    if (nxtReadDataReady_5) begin // @[Regfile.scala 197:29]
+      if (io_readSet_5_valid) begin // @[Regfile.scala 195:30]
         readDataBits_5 <= io_readSet_5_value;
-      end else if (write_value_35_0) begin // @[Regfile.scala 183:21]
+      end else if (write_value_35_0) begin // @[Regfile.scala 184:21]
         readDataBits_5 <= wdata_5_value_5_0;
       end else begin
         readDataBits_5 <= rdata_5_value_5_0;
       end
     end
-    if (nxtReadDataReady_6) begin // @[Regfile.scala 196:29]
-      if (io_readSet_6_valid) begin // @[Regfile.scala 194:30]
+    if (nxtReadDataReady_6) begin // @[Regfile.scala 197:29]
+      if (io_readSet_6_valid) begin // @[Regfile.scala 195:30]
         readDataBits_6 <= io_readSet_6_value;
-      end else if (write_value_41_0) begin // @[Regfile.scala 183:21]
+      end else if (write_value_41_0) begin // @[Regfile.scala 184:21]
         readDataBits_6 <= wdata_6_value_5_0;
       end else begin
         readDataBits_6 <= rdata_6_value_5_0;
       end
     end
-    if (nxtReadDataReady_7) begin // @[Regfile.scala 196:29]
-      if (io_readSet_7_valid) begin // @[Regfile.scala 194:30]
+    if (nxtReadDataReady_7) begin // @[Regfile.scala 197:29]
+      if (io_readSet_7_valid) begin // @[Regfile.scala 195:30]
         readDataBits_7 <= io_readSet_7_value;
-      end else if (write_value_47_0) begin // @[Regfile.scala 183:21]
+      end else if (write_value_47_0) begin // @[Regfile.scala 184:21]
         readDataBits_7 <= wdata_7_value_5_0;
       end else begin
         readDataBits_7 <= rdata_7_value_5_0;
@@ -2819,7 +2821,7 @@
       if (`STOP_COND) begin
     `endif
         if (~reset & ~(_T_17 <= 3'h1)) begin
-          $fatal; // @[Regfile.scala 163:11]
+          $fatal; // @[Regfile.scala 164:11]
         end
     `ifdef STOP_COND
       end
@@ -2830,7 +2832,7 @@
       if (`PRINTF_COND) begin
     `endif
         if (~reset & ~(_T_17 <= 3'h1)) begin
-          $fwrite(32'h80000002,"Assertion failed\n    at Regfile.scala:163 assert(PopCount(valid) <= 1.U)\n"); // @[Regfile.scala 163:11]
+          $fwrite(32'h80000002,"Assertion failed\n    at Regfile.scala:164 assert(PopCount(valid) <= 1.U)\n"); // @[Regfile.scala 164:11]
         end
     `ifdef PRINTF_COND
       end
@@ -2841,7 +2843,7 @@
       if (`STOP_COND) begin
     `endif
         if (~reset & ~(_T_37 <= 3'h1)) begin
-          $fatal; // @[Regfile.scala 163:11]
+          $fatal; // @[Regfile.scala 164:11]
         end
     `ifdef STOP_COND
       end
@@ -2852,7 +2854,7 @@
       if (`PRINTF_COND) begin
     `endif
         if (~reset & ~(_T_37 <= 3'h1)) begin
-          $fwrite(32'h80000002,"Assertion failed\n    at Regfile.scala:163 assert(PopCount(valid) <= 1.U)\n"); // @[Regfile.scala 163:11]
+          $fwrite(32'h80000002,"Assertion failed\n    at Regfile.scala:164 assert(PopCount(valid) <= 1.U)\n"); // @[Regfile.scala 164:11]
         end
     `ifdef PRINTF_COND
       end
@@ -2863,7 +2865,7 @@
       if (`STOP_COND) begin
     `endif
         if (~reset & ~(_T_57 <= 3'h1)) begin
-          $fatal; // @[Regfile.scala 163:11]
+          $fatal; // @[Regfile.scala 164:11]
         end
     `ifdef STOP_COND
       end
@@ -2874,7 +2876,7 @@
       if (`PRINTF_COND) begin
     `endif
         if (~reset & ~(_T_57 <= 3'h1)) begin
-          $fwrite(32'h80000002,"Assertion failed\n    at Regfile.scala:163 assert(PopCount(valid) <= 1.U)\n"); // @[Regfile.scala 163:11]
+          $fwrite(32'h80000002,"Assertion failed\n    at Regfile.scala:164 assert(PopCount(valid) <= 1.U)\n"); // @[Regfile.scala 164:11]
         end
     `ifdef PRINTF_COND
       end
@@ -2885,7 +2887,7 @@
       if (`STOP_COND) begin
     `endif
         if (~reset & ~(_T_77 <= 3'h1)) begin
-          $fatal; // @[Regfile.scala 163:11]
+          $fatal; // @[Regfile.scala 164:11]
         end
     `ifdef STOP_COND
       end
@@ -2896,7 +2898,7 @@
       if (`PRINTF_COND) begin
     `endif
         if (~reset & ~(_T_77 <= 3'h1)) begin
-          $fwrite(32'h80000002,"Assertion failed\n    at Regfile.scala:163 assert(PopCount(valid) <= 1.U)\n"); // @[Regfile.scala 163:11]
+          $fwrite(32'h80000002,"Assertion failed\n    at Regfile.scala:164 assert(PopCount(valid) <= 1.U)\n"); // @[Regfile.scala 164:11]
         end
     `ifdef PRINTF_COND
       end
@@ -2907,7 +2909,7 @@
       if (`STOP_COND) begin
     `endif
         if (~reset & ~(_T_97 <= 3'h1)) begin
-          $fatal; // @[Regfile.scala 163:11]
+          $fatal; // @[Regfile.scala 164:11]
         end
     `ifdef STOP_COND
       end
@@ -2918,7 +2920,7 @@
       if (`PRINTF_COND) begin
     `endif
         if (~reset & ~(_T_97 <= 3'h1)) begin
-          $fwrite(32'h80000002,"Assertion failed\n    at Regfile.scala:163 assert(PopCount(valid) <= 1.U)\n"); // @[Regfile.scala 163:11]
+          $fwrite(32'h80000002,"Assertion failed\n    at Regfile.scala:164 assert(PopCount(valid) <= 1.U)\n"); // @[Regfile.scala 164:11]
         end
     `ifdef PRINTF_COND
       end
@@ -2929,7 +2931,7 @@
       if (`STOP_COND) begin
     `endif
         if (~reset & ~(_T_117 <= 3'h1)) begin
-          $fatal; // @[Regfile.scala 163:11]
+          $fatal; // @[Regfile.scala 164:11]
         end
     `ifdef STOP_COND
       end
@@ -2940,7 +2942,7 @@
       if (`PRINTF_COND) begin
     `endif
         if (~reset & ~(_T_117 <= 3'h1)) begin
-          $fwrite(32'h80000002,"Assertion failed\n    at Regfile.scala:163 assert(PopCount(valid) <= 1.U)\n"); // @[Regfile.scala 163:11]
+          $fwrite(32'h80000002,"Assertion failed\n    at Regfile.scala:164 assert(PopCount(valid) <= 1.U)\n"); // @[Regfile.scala 164:11]
         end
     `ifdef PRINTF_COND
       end
@@ -2951,7 +2953,7 @@
       if (`STOP_COND) begin
     `endif
         if (~reset & ~(_T_137 <= 3'h1)) begin
-          $fatal; // @[Regfile.scala 163:11]
+          $fatal; // @[Regfile.scala 164:11]
         end
     `ifdef STOP_COND
       end
@@ -2962,7 +2964,7 @@
       if (`PRINTF_COND) begin
     `endif
         if (~reset & ~(_T_137 <= 3'h1)) begin
-          $fwrite(32'h80000002,"Assertion failed\n    at Regfile.scala:163 assert(PopCount(valid) <= 1.U)\n"); // @[Regfile.scala 163:11]
+          $fwrite(32'h80000002,"Assertion failed\n    at Regfile.scala:164 assert(PopCount(valid) <= 1.U)\n"); // @[Regfile.scala 164:11]
         end
     `ifdef PRINTF_COND
       end
@@ -2973,7 +2975,7 @@
       if (`STOP_COND) begin
     `endif
         if (~reset & ~(_T_157 <= 3'h1)) begin
-          $fatal; // @[Regfile.scala 163:11]
+          $fatal; // @[Regfile.scala 164:11]
         end
     `ifdef STOP_COND
       end
@@ -2984,7 +2986,7 @@
       if (`PRINTF_COND) begin
     `endif
         if (~reset & ~(_T_157 <= 3'h1)) begin
-          $fwrite(32'h80000002,"Assertion failed\n    at Regfile.scala:163 assert(PopCount(valid) <= 1.U)\n"); // @[Regfile.scala 163:11]
+          $fwrite(32'h80000002,"Assertion failed\n    at Regfile.scala:164 assert(PopCount(valid) <= 1.U)\n"); // @[Regfile.scala 164:11]
         end
     `ifdef PRINTF_COND
       end
@@ -2995,7 +2997,7 @@
       if (`STOP_COND) begin
     `endif
         if (~reset & ~(_T_177 <= 3'h1)) begin
-          $fatal; // @[Regfile.scala 163:11]
+          $fatal; // @[Regfile.scala 164:11]
         end
     `ifdef STOP_COND
       end
@@ -3006,7 +3008,7 @@
       if (`PRINTF_COND) begin
     `endif
         if (~reset & ~(_T_177 <= 3'h1)) begin
-          $fwrite(32'h80000002,"Assertion failed\n    at Regfile.scala:163 assert(PopCount(valid) <= 1.U)\n"); // @[Regfile.scala 163:11]
+          $fwrite(32'h80000002,"Assertion failed\n    at Regfile.scala:164 assert(PopCount(valid) <= 1.U)\n"); // @[Regfile.scala 164:11]
         end
     `ifdef PRINTF_COND
       end
@@ -3017,7 +3019,7 @@
       if (`STOP_COND) begin
     `endif
         if (~reset & ~(_T_197 <= 3'h1)) begin
-          $fatal; // @[Regfile.scala 163:11]
+          $fatal; // @[Regfile.scala 164:11]
         end
     `ifdef STOP_COND
       end
@@ -3028,7 +3030,7 @@
       if (`PRINTF_COND) begin
     `endif
         if (~reset & ~(_T_197 <= 3'h1)) begin
-          $fwrite(32'h80000002,"Assertion failed\n    at Regfile.scala:163 assert(PopCount(valid) <= 1.U)\n"); // @[Regfile.scala 163:11]
+          $fwrite(32'h80000002,"Assertion failed\n    at Regfile.scala:164 assert(PopCount(valid) <= 1.U)\n"); // @[Regfile.scala 164:11]
         end
     `ifdef PRINTF_COND
       end
@@ -3039,7 +3041,7 @@
       if (`STOP_COND) begin
     `endif
         if (~reset & ~(_T_217 <= 3'h1)) begin
-          $fatal; // @[Regfile.scala 163:11]
+          $fatal; // @[Regfile.scala 164:11]
         end
     `ifdef STOP_COND
       end
@@ -3050,7 +3052,7 @@
       if (`PRINTF_COND) begin
     `endif
         if (~reset & ~(_T_217 <= 3'h1)) begin
-          $fwrite(32'h80000002,"Assertion failed\n    at Regfile.scala:163 assert(PopCount(valid) <= 1.U)\n"); // @[Regfile.scala 163:11]
+          $fwrite(32'h80000002,"Assertion failed\n    at Regfile.scala:164 assert(PopCount(valid) <= 1.U)\n"); // @[Regfile.scala 164:11]
         end
     `ifdef PRINTF_COND
       end
@@ -3061,7 +3063,7 @@
       if (`STOP_COND) begin
     `endif
         if (~reset & ~(_T_237 <= 3'h1)) begin
-          $fatal; // @[Regfile.scala 163:11]
+          $fatal; // @[Regfile.scala 164:11]
         end
     `ifdef STOP_COND
       end
@@ -3072,7 +3074,7 @@
       if (`PRINTF_COND) begin
     `endif
         if (~reset & ~(_T_237 <= 3'h1)) begin
-          $fwrite(32'h80000002,"Assertion failed\n    at Regfile.scala:163 assert(PopCount(valid) <= 1.U)\n"); // @[Regfile.scala 163:11]
+          $fwrite(32'h80000002,"Assertion failed\n    at Regfile.scala:164 assert(PopCount(valid) <= 1.U)\n"); // @[Regfile.scala 164:11]
         end
     `ifdef PRINTF_COND
       end
@@ -3083,7 +3085,7 @@
       if (`STOP_COND) begin
     `endif
         if (~reset & ~(_T_257 <= 3'h1)) begin
-          $fatal; // @[Regfile.scala 163:11]
+          $fatal; // @[Regfile.scala 164:11]
         end
     `ifdef STOP_COND
       end
@@ -3094,7 +3096,7 @@
       if (`PRINTF_COND) begin
     `endif
         if (~reset & ~(_T_257 <= 3'h1)) begin
-          $fwrite(32'h80000002,"Assertion failed\n    at Regfile.scala:163 assert(PopCount(valid) <= 1.U)\n"); // @[Regfile.scala 163:11]
+          $fwrite(32'h80000002,"Assertion failed\n    at Regfile.scala:164 assert(PopCount(valid) <= 1.U)\n"); // @[Regfile.scala 164:11]
         end
     `ifdef PRINTF_COND
       end
@@ -3105,7 +3107,7 @@
       if (`STOP_COND) begin
     `endif
         if (~reset & ~(_T_277 <= 3'h1)) begin
-          $fatal; // @[Regfile.scala 163:11]
+          $fatal; // @[Regfile.scala 164:11]
         end
     `ifdef STOP_COND
       end
@@ -3116,7 +3118,7 @@
       if (`PRINTF_COND) begin
     `endif
         if (~reset & ~(_T_277 <= 3'h1)) begin
-          $fwrite(32'h80000002,"Assertion failed\n    at Regfile.scala:163 assert(PopCount(valid) <= 1.U)\n"); // @[Regfile.scala 163:11]
+          $fwrite(32'h80000002,"Assertion failed\n    at Regfile.scala:164 assert(PopCount(valid) <= 1.U)\n"); // @[Regfile.scala 164:11]
         end
     `ifdef PRINTF_COND
       end
@@ -3127,7 +3129,7 @@
       if (`STOP_COND) begin
     `endif
         if (~reset & ~(_T_297 <= 3'h1)) begin
-          $fatal; // @[Regfile.scala 163:11]
+          $fatal; // @[Regfile.scala 164:11]
         end
     `ifdef STOP_COND
       end
@@ -3138,7 +3140,7 @@
       if (`PRINTF_COND) begin
     `endif
         if (~reset & ~(_T_297 <= 3'h1)) begin
-          $fwrite(32'h80000002,"Assertion failed\n    at Regfile.scala:163 assert(PopCount(valid) <= 1.U)\n"); // @[Regfile.scala 163:11]
+          $fwrite(32'h80000002,"Assertion failed\n    at Regfile.scala:164 assert(PopCount(valid) <= 1.U)\n"); // @[Regfile.scala 164:11]
         end
     `ifdef PRINTF_COND
       end
@@ -3149,7 +3151,7 @@
       if (`STOP_COND) begin
     `endif
         if (~reset & ~(_T_317 <= 3'h1)) begin
-          $fatal; // @[Regfile.scala 163:11]
+          $fatal; // @[Regfile.scala 164:11]
         end
     `ifdef STOP_COND
       end
@@ -3160,7 +3162,7 @@
       if (`PRINTF_COND) begin
     `endif
         if (~reset & ~(_T_317 <= 3'h1)) begin
-          $fwrite(32'h80000002,"Assertion failed\n    at Regfile.scala:163 assert(PopCount(valid) <= 1.U)\n"); // @[Regfile.scala 163:11]
+          $fwrite(32'h80000002,"Assertion failed\n    at Regfile.scala:164 assert(PopCount(valid) <= 1.U)\n"); // @[Regfile.scala 164:11]
         end
     `ifdef PRINTF_COND
       end
@@ -3171,7 +3173,7 @@
       if (`STOP_COND) begin
     `endif
         if (~reset & ~(_T_337 <= 3'h1)) begin
-          $fatal; // @[Regfile.scala 163:11]
+          $fatal; // @[Regfile.scala 164:11]
         end
     `ifdef STOP_COND
       end
@@ -3182,7 +3184,7 @@
       if (`PRINTF_COND) begin
     `endif
         if (~reset & ~(_T_337 <= 3'h1)) begin
-          $fwrite(32'h80000002,"Assertion failed\n    at Regfile.scala:163 assert(PopCount(valid) <= 1.U)\n"); // @[Regfile.scala 163:11]
+          $fwrite(32'h80000002,"Assertion failed\n    at Regfile.scala:164 assert(PopCount(valid) <= 1.U)\n"); // @[Regfile.scala 164:11]
         end
     `ifdef PRINTF_COND
       end
@@ -3193,7 +3195,7 @@
       if (`STOP_COND) begin
     `endif
         if (~reset & ~(_T_357 <= 3'h1)) begin
-          $fatal; // @[Regfile.scala 163:11]
+          $fatal; // @[Regfile.scala 164:11]
         end
     `ifdef STOP_COND
       end
@@ -3204,7 +3206,7 @@
       if (`PRINTF_COND) begin
     `endif
         if (~reset & ~(_T_357 <= 3'h1)) begin
-          $fwrite(32'h80000002,"Assertion failed\n    at Regfile.scala:163 assert(PopCount(valid) <= 1.U)\n"); // @[Regfile.scala 163:11]
+          $fwrite(32'h80000002,"Assertion failed\n    at Regfile.scala:164 assert(PopCount(valid) <= 1.U)\n"); // @[Regfile.scala 164:11]
         end
     `ifdef PRINTF_COND
       end
@@ -3215,7 +3217,7 @@
       if (`STOP_COND) begin
     `endif
         if (~reset & ~(_T_377 <= 3'h1)) begin
-          $fatal; // @[Regfile.scala 163:11]
+          $fatal; // @[Regfile.scala 164:11]
         end
     `ifdef STOP_COND
       end
@@ -3226,7 +3228,7 @@
       if (`PRINTF_COND) begin
     `endif
         if (~reset & ~(_T_377 <= 3'h1)) begin
-          $fwrite(32'h80000002,"Assertion failed\n    at Regfile.scala:163 assert(PopCount(valid) <= 1.U)\n"); // @[Regfile.scala 163:11]
+          $fwrite(32'h80000002,"Assertion failed\n    at Regfile.scala:164 assert(PopCount(valid) <= 1.U)\n"); // @[Regfile.scala 164:11]
         end
     `ifdef PRINTF_COND
       end
@@ -3237,7 +3239,7 @@
       if (`STOP_COND) begin
     `endif
         if (~reset & ~(_T_397 <= 3'h1)) begin
-          $fatal; // @[Regfile.scala 163:11]
+          $fatal; // @[Regfile.scala 164:11]
         end
     `ifdef STOP_COND
       end
@@ -3248,7 +3250,7 @@
       if (`PRINTF_COND) begin
     `endif
         if (~reset & ~(_T_397 <= 3'h1)) begin
-          $fwrite(32'h80000002,"Assertion failed\n    at Regfile.scala:163 assert(PopCount(valid) <= 1.U)\n"); // @[Regfile.scala 163:11]
+          $fwrite(32'h80000002,"Assertion failed\n    at Regfile.scala:164 assert(PopCount(valid) <= 1.U)\n"); // @[Regfile.scala 164:11]
         end
     `ifdef PRINTF_COND
       end
@@ -3259,7 +3261,7 @@
       if (`STOP_COND) begin
     `endif
         if (~reset & ~(_T_417 <= 3'h1)) begin
-          $fatal; // @[Regfile.scala 163:11]
+          $fatal; // @[Regfile.scala 164:11]
         end
     `ifdef STOP_COND
       end
@@ -3270,7 +3272,7 @@
       if (`PRINTF_COND) begin
     `endif
         if (~reset & ~(_T_417 <= 3'h1)) begin
-          $fwrite(32'h80000002,"Assertion failed\n    at Regfile.scala:163 assert(PopCount(valid) <= 1.U)\n"); // @[Regfile.scala 163:11]
+          $fwrite(32'h80000002,"Assertion failed\n    at Regfile.scala:164 assert(PopCount(valid) <= 1.U)\n"); // @[Regfile.scala 164:11]
         end
     `ifdef PRINTF_COND
       end
@@ -3281,7 +3283,7 @@
       if (`STOP_COND) begin
     `endif
         if (~reset & ~(_T_437 <= 3'h1)) begin
-          $fatal; // @[Regfile.scala 163:11]
+          $fatal; // @[Regfile.scala 164:11]
         end
     `ifdef STOP_COND
       end
@@ -3292,7 +3294,7 @@
       if (`PRINTF_COND) begin
     `endif
         if (~reset & ~(_T_437 <= 3'h1)) begin
-          $fwrite(32'h80000002,"Assertion failed\n    at Regfile.scala:163 assert(PopCount(valid) <= 1.U)\n"); // @[Regfile.scala 163:11]
+          $fwrite(32'h80000002,"Assertion failed\n    at Regfile.scala:164 assert(PopCount(valid) <= 1.U)\n"); // @[Regfile.scala 164:11]
         end
     `ifdef PRINTF_COND
       end
@@ -3303,7 +3305,7 @@
       if (`STOP_COND) begin
     `endif
         if (~reset & ~(_T_457 <= 3'h1)) begin
-          $fatal; // @[Regfile.scala 163:11]
+          $fatal; // @[Regfile.scala 164:11]
         end
     `ifdef STOP_COND
       end
@@ -3314,7 +3316,7 @@
       if (`PRINTF_COND) begin
     `endif
         if (~reset & ~(_T_457 <= 3'h1)) begin
-          $fwrite(32'h80000002,"Assertion failed\n    at Regfile.scala:163 assert(PopCount(valid) <= 1.U)\n"); // @[Regfile.scala 163:11]
+          $fwrite(32'h80000002,"Assertion failed\n    at Regfile.scala:164 assert(PopCount(valid) <= 1.U)\n"); // @[Regfile.scala 164:11]
         end
     `ifdef PRINTF_COND
       end
@@ -3325,7 +3327,7 @@
       if (`STOP_COND) begin
     `endif
         if (~reset & ~(_T_477 <= 3'h1)) begin
-          $fatal; // @[Regfile.scala 163:11]
+          $fatal; // @[Regfile.scala 164:11]
         end
     `ifdef STOP_COND
       end
@@ -3336,7 +3338,7 @@
       if (`PRINTF_COND) begin
     `endif
         if (~reset & ~(_T_477 <= 3'h1)) begin
-          $fwrite(32'h80000002,"Assertion failed\n    at Regfile.scala:163 assert(PopCount(valid) <= 1.U)\n"); // @[Regfile.scala 163:11]
+          $fwrite(32'h80000002,"Assertion failed\n    at Regfile.scala:164 assert(PopCount(valid) <= 1.U)\n"); // @[Regfile.scala 164:11]
         end
     `ifdef PRINTF_COND
       end
@@ -3347,7 +3349,7 @@
       if (`STOP_COND) begin
     `endif
         if (~reset & ~(_T_497 <= 3'h1)) begin
-          $fatal; // @[Regfile.scala 163:11]
+          $fatal; // @[Regfile.scala 164:11]
         end
     `ifdef STOP_COND
       end
@@ -3358,7 +3360,7 @@
       if (`PRINTF_COND) begin
     `endif
         if (~reset & ~(_T_497 <= 3'h1)) begin
-          $fwrite(32'h80000002,"Assertion failed\n    at Regfile.scala:163 assert(PopCount(valid) <= 1.U)\n"); // @[Regfile.scala 163:11]
+          $fwrite(32'h80000002,"Assertion failed\n    at Regfile.scala:164 assert(PopCount(valid) <= 1.U)\n"); // @[Regfile.scala 164:11]
         end
     `ifdef PRINTF_COND
       end
@@ -3369,7 +3371,7 @@
       if (`STOP_COND) begin
     `endif
         if (~reset & ~(_T_517 <= 3'h1)) begin
-          $fatal; // @[Regfile.scala 163:11]
+          $fatal; // @[Regfile.scala 164:11]
         end
     `ifdef STOP_COND
       end
@@ -3380,7 +3382,7 @@
       if (`PRINTF_COND) begin
     `endif
         if (~reset & ~(_T_517 <= 3'h1)) begin
-          $fwrite(32'h80000002,"Assertion failed\n    at Regfile.scala:163 assert(PopCount(valid) <= 1.U)\n"); // @[Regfile.scala 163:11]
+          $fwrite(32'h80000002,"Assertion failed\n    at Regfile.scala:164 assert(PopCount(valid) <= 1.U)\n"); // @[Regfile.scala 164:11]
         end
     `ifdef PRINTF_COND
       end
@@ -3391,7 +3393,7 @@
       if (`STOP_COND) begin
     `endif
         if (~reset & ~(_T_537 <= 3'h1)) begin
-          $fatal; // @[Regfile.scala 163:11]
+          $fatal; // @[Regfile.scala 164:11]
         end
     `ifdef STOP_COND
       end
@@ -3402,7 +3404,7 @@
       if (`PRINTF_COND) begin
     `endif
         if (~reset & ~(_T_537 <= 3'h1)) begin
-          $fwrite(32'h80000002,"Assertion failed\n    at Regfile.scala:163 assert(PopCount(valid) <= 1.U)\n"); // @[Regfile.scala 163:11]
+          $fwrite(32'h80000002,"Assertion failed\n    at Regfile.scala:164 assert(PopCount(valid) <= 1.U)\n"); // @[Regfile.scala 164:11]
         end
     `ifdef PRINTF_COND
       end
@@ -3413,7 +3415,7 @@
       if (`STOP_COND) begin
     `endif
         if (~reset & ~(_T_557 <= 3'h1)) begin
-          $fatal; // @[Regfile.scala 163:11]
+          $fatal; // @[Regfile.scala 164:11]
         end
     `ifdef STOP_COND
       end
@@ -3424,7 +3426,7 @@
       if (`PRINTF_COND) begin
     `endif
         if (~reset & ~(_T_557 <= 3'h1)) begin
-          $fwrite(32'h80000002,"Assertion failed\n    at Regfile.scala:163 assert(PopCount(valid) <= 1.U)\n"); // @[Regfile.scala 163:11]
+          $fwrite(32'h80000002,"Assertion failed\n    at Regfile.scala:164 assert(PopCount(valid) <= 1.U)\n"); // @[Regfile.scala 164:11]
         end
     `ifdef PRINTF_COND
       end
@@ -3435,7 +3437,7 @@
       if (`STOP_COND) begin
     `endif
         if (~reset & ~(_T_577 <= 3'h1)) begin
-          $fatal; // @[Regfile.scala 163:11]
+          $fatal; // @[Regfile.scala 164:11]
         end
     `ifdef STOP_COND
       end
@@ -3446,7 +3448,7 @@
       if (`PRINTF_COND) begin
     `endif
         if (~reset & ~(_T_577 <= 3'h1)) begin
-          $fwrite(32'h80000002,"Assertion failed\n    at Regfile.scala:163 assert(PopCount(valid) <= 1.U)\n"); // @[Regfile.scala 163:11]
+          $fwrite(32'h80000002,"Assertion failed\n    at Regfile.scala:164 assert(PopCount(valid) <= 1.U)\n"); // @[Regfile.scala 164:11]
         end
     `ifdef PRINTF_COND
       end
@@ -3457,7 +3459,7 @@
       if (`STOP_COND) begin
     `endif
         if (~reset & ~(_T_597 <= 3'h1)) begin
-          $fatal; // @[Regfile.scala 163:11]
+          $fatal; // @[Regfile.scala 164:11]
         end
     `ifdef STOP_COND
       end
@@ -3468,7 +3470,7 @@
       if (`PRINTF_COND) begin
     `endif
         if (~reset & ~(_T_597 <= 3'h1)) begin
-          $fwrite(32'h80000002,"Assertion failed\n    at Regfile.scala:163 assert(PopCount(valid) <= 1.U)\n"); // @[Regfile.scala 163:11]
+          $fwrite(32'h80000002,"Assertion failed\n    at Regfile.scala:164 assert(PopCount(valid) <= 1.U)\n"); // @[Regfile.scala 164:11]
         end
     `ifdef PRINTF_COND
       end
@@ -3479,7 +3481,7 @@
       if (`STOP_COND) begin
     `endif
         if (~reset & ~(_T_617 <= 3'h1)) begin
-          $fatal; // @[Regfile.scala 163:11]
+          $fatal; // @[Regfile.scala 164:11]
         end
     `ifdef STOP_COND
       end
@@ -3490,7 +3492,7 @@
       if (`PRINTF_COND) begin
     `endif
         if (~reset & ~(_T_617 <= 3'h1)) begin
-          $fwrite(32'h80000002,"Assertion failed\n    at Regfile.scala:163 assert(PopCount(valid) <= 1.U)\n"); // @[Regfile.scala 163:11]
+          $fwrite(32'h80000002,"Assertion failed\n    at Regfile.scala:164 assert(PopCount(valid) <= 1.U)\n"); // @[Regfile.scala 164:11]
         end
     `ifdef PRINTF_COND
       end
@@ -3501,7 +3503,7 @@
       if (`STOP_COND) begin
     `endif
         if (_T_21 & ~(~write_fail)) begin
-          $fatal; // @[Regfile.scala 242:13]
+          $fatal; // @[Regfile.scala 243:13]
         end
     `ifdef STOP_COND
       end
@@ -3512,7 +3514,7 @@
       if (`PRINTF_COND) begin
     `endif
         if (_T_21 & ~(~write_fail)) begin
-          $fwrite(32'h80000002,"Assertion failed\n    at Regfile.scala:242 assert(!write_fail)\n"); // @[Regfile.scala 242:13]
+          $fwrite(32'h80000002,"Assertion failed\n    at Regfile.scala:243 assert(!write_fail)\n"); // @[Regfile.scala 243:13]
         end
     `ifdef PRINTF_COND
       end
@@ -3523,7 +3525,7 @@
       if (`STOP_COND) begin
     `endif
         if (_T_21 & ~(~write_fail_1)) begin
-          $fatal; // @[Regfile.scala 242:13]
+          $fatal; // @[Regfile.scala 243:13]
         end
     `ifdef STOP_COND
       end
@@ -3534,7 +3536,7 @@
       if (`PRINTF_COND) begin
     `endif
         if (_T_21 & ~(~write_fail_1)) begin
-          $fwrite(32'h80000002,"Assertion failed\n    at Regfile.scala:242 assert(!write_fail)\n"); // @[Regfile.scala 242:13]
+          $fwrite(32'h80000002,"Assertion failed\n    at Regfile.scala:243 assert(!write_fail)\n"); // @[Regfile.scala 243:13]
         end
     `ifdef PRINTF_COND
       end
@@ -3545,7 +3547,7 @@
       if (`STOP_COND) begin
     `endif
         if (_T_21 & ~(~write_fail_2)) begin
-          $fatal; // @[Regfile.scala 242:13]
+          $fatal; // @[Regfile.scala 243:13]
         end
     `ifdef STOP_COND
       end
@@ -3556,7 +3558,7 @@
       if (`PRINTF_COND) begin
     `endif
         if (_T_21 & ~(~write_fail_2)) begin
-          $fwrite(32'h80000002,"Assertion failed\n    at Regfile.scala:242 assert(!write_fail)\n"); // @[Regfile.scala 242:13]
+          $fwrite(32'h80000002,"Assertion failed\n    at Regfile.scala:243 assert(!write_fail)\n"); // @[Regfile.scala 243:13]
         end
     `ifdef PRINTF_COND
       end
@@ -3567,7 +3569,7 @@
       if (`STOP_COND) begin
     `endif
         if (_T_21 & ~(~write_fail_3)) begin
-          $fatal; // @[Regfile.scala 242:13]
+          $fatal; // @[Regfile.scala 243:13]
         end
     `ifdef STOP_COND
       end
@@ -3578,7 +3580,7 @@
       if (`PRINTF_COND) begin
     `endif
         if (_T_21 & ~(~write_fail_3)) begin
-          $fwrite(32'h80000002,"Assertion failed\n    at Regfile.scala:242 assert(!write_fail)\n"); // @[Regfile.scala 242:13]
+          $fwrite(32'h80000002,"Assertion failed\n    at Regfile.scala:243 assert(!write_fail)\n"); // @[Regfile.scala 243:13]
         end
     `ifdef PRINTF_COND
       end
@@ -3589,7 +3591,7 @@
       if (`STOP_COND) begin
     `endif
         if (_T_21 & ~(~write_fail_4)) begin
-          $fatal; // @[Regfile.scala 242:13]
+          $fatal; // @[Regfile.scala 243:13]
         end
     `ifdef STOP_COND
       end
@@ -3600,7 +3602,7 @@
       if (`PRINTF_COND) begin
     `endif
         if (_T_21 & ~(~write_fail_4)) begin
-          $fwrite(32'h80000002,"Assertion failed\n    at Regfile.scala:242 assert(!write_fail)\n"); // @[Regfile.scala 242:13]
+          $fwrite(32'h80000002,"Assertion failed\n    at Regfile.scala:243 assert(!write_fail)\n"); // @[Regfile.scala 243:13]
         end
     `ifdef PRINTF_COND
       end
@@ -3611,7 +3613,7 @@
       if (`STOP_COND) begin
     `endif
         if (_T_21 & ~(~write_fail_5)) begin
-          $fatal; // @[Regfile.scala 242:13]
+          $fatal; // @[Regfile.scala 243:13]
         end
     `ifdef STOP_COND
       end
@@ -3622,7 +3624,7 @@
       if (`PRINTF_COND) begin
     `endif
         if (_T_21 & ~(~write_fail_5)) begin
-          $fwrite(32'h80000002,"Assertion failed\n    at Regfile.scala:242 assert(!write_fail)\n"); // @[Regfile.scala 242:13]
+          $fwrite(32'h80000002,"Assertion failed\n    at Regfile.scala:243 assert(!write_fail)\n"); // @[Regfile.scala 243:13]
         end
     `ifdef PRINTF_COND
       end
@@ -3633,7 +3635,7 @@
       if (`STOP_COND) begin
     `endif
         if (_T_21 & ~(~write_fail_6)) begin
-          $fatal; // @[Regfile.scala 242:13]
+          $fatal; // @[Regfile.scala 243:13]
         end
     `ifdef STOP_COND
       end
@@ -3644,7 +3646,7 @@
       if (`PRINTF_COND) begin
     `endif
         if (_T_21 & ~(~write_fail_6)) begin
-          $fwrite(32'h80000002,"Assertion failed\n    at Regfile.scala:242 assert(!write_fail)\n"); // @[Regfile.scala 242:13]
+          $fwrite(32'h80000002,"Assertion failed\n    at Regfile.scala:243 assert(!write_fail)\n"); // @[Regfile.scala 243:13]
         end
     `ifdef PRINTF_COND
       end
@@ -3655,7 +3657,7 @@
       if (`STOP_COND) begin
     `endif
         if (_T_21 & ~(~write_fail_7)) begin
-          $fatal; // @[Regfile.scala 242:13]
+          $fatal; // @[Regfile.scala 243:13]
         end
     `ifdef STOP_COND
       end
@@ -3666,7 +3668,7 @@
       if (`PRINTF_COND) begin
     `endif
         if (_T_21 & ~(~write_fail_7)) begin
-          $fwrite(32'h80000002,"Assertion failed\n    at Regfile.scala:242 assert(!write_fail)\n"); // @[Regfile.scala 242:13]
+          $fwrite(32'h80000002,"Assertion failed\n    at Regfile.scala:243 assert(!write_fail)\n"); // @[Regfile.scala 243:13]
         end
     `ifdef PRINTF_COND
       end
@@ -3677,7 +3679,7 @@
       if (`STOP_COND) begin
     `endif
         if (_T_21 & ~(~write_fail_8)) begin
-          $fatal; // @[Regfile.scala 242:13]
+          $fatal; // @[Regfile.scala 243:13]
         end
     `ifdef STOP_COND
       end
@@ -3688,7 +3690,7 @@
       if (`PRINTF_COND) begin
     `endif
         if (_T_21 & ~(~write_fail_8)) begin
-          $fwrite(32'h80000002,"Assertion failed\n    at Regfile.scala:242 assert(!write_fail)\n"); // @[Regfile.scala 242:13]
+          $fwrite(32'h80000002,"Assertion failed\n    at Regfile.scala:243 assert(!write_fail)\n"); // @[Regfile.scala 243:13]
         end
     `ifdef PRINTF_COND
       end
@@ -3699,7 +3701,7 @@
       if (`STOP_COND) begin
     `endif
         if (_T_21 & ~(~write_fail_9)) begin
-          $fatal; // @[Regfile.scala 242:13]
+          $fatal; // @[Regfile.scala 243:13]
         end
     `ifdef STOP_COND
       end
@@ -3710,7 +3712,7 @@
       if (`PRINTF_COND) begin
     `endif
         if (_T_21 & ~(~write_fail_9)) begin
-          $fwrite(32'h80000002,"Assertion failed\n    at Regfile.scala:242 assert(!write_fail)\n"); // @[Regfile.scala 242:13]
+          $fwrite(32'h80000002,"Assertion failed\n    at Regfile.scala:243 assert(!write_fail)\n"); // @[Regfile.scala 243:13]
         end
     `ifdef PRINTF_COND
       end
@@ -3721,7 +3723,7 @@
       if (`STOP_COND) begin
     `endif
         if (_T_21 & ~(~write_fail_10)) begin
-          $fatal; // @[Regfile.scala 242:13]
+          $fatal; // @[Regfile.scala 243:13]
         end
     `ifdef STOP_COND
       end
@@ -3732,7 +3734,7 @@
       if (`PRINTF_COND) begin
     `endif
         if (_T_21 & ~(~write_fail_10)) begin
-          $fwrite(32'h80000002,"Assertion failed\n    at Regfile.scala:242 assert(!write_fail)\n"); // @[Regfile.scala 242:13]
+          $fwrite(32'h80000002,"Assertion failed\n    at Regfile.scala:243 assert(!write_fail)\n"); // @[Regfile.scala 243:13]
         end
     `ifdef PRINTF_COND
       end
@@ -3743,7 +3745,7 @@
       if (`STOP_COND) begin
     `endif
         if (_T_21 & ~(~write_fail_11)) begin
-          $fatal; // @[Regfile.scala 242:13]
+          $fatal; // @[Regfile.scala 243:13]
         end
     `ifdef STOP_COND
       end
@@ -3754,7 +3756,7 @@
       if (`PRINTF_COND) begin
     `endif
         if (_T_21 & ~(~write_fail_11)) begin
-          $fwrite(32'h80000002,"Assertion failed\n    at Regfile.scala:242 assert(!write_fail)\n"); // @[Regfile.scala 242:13]
+          $fwrite(32'h80000002,"Assertion failed\n    at Regfile.scala:243 assert(!write_fail)\n"); // @[Regfile.scala 243:13]
         end
     `ifdef PRINTF_COND
       end
@@ -3765,7 +3767,7 @@
       if (`STOP_COND) begin
     `endif
         if (_T_21 & ~(~write_fail_12)) begin
-          $fatal; // @[Regfile.scala 242:13]
+          $fatal; // @[Regfile.scala 243:13]
         end
     `ifdef STOP_COND
       end
@@ -3776,7 +3778,7 @@
       if (`PRINTF_COND) begin
     `endif
         if (_T_21 & ~(~write_fail_12)) begin
-          $fwrite(32'h80000002,"Assertion failed\n    at Regfile.scala:242 assert(!write_fail)\n"); // @[Regfile.scala 242:13]
+          $fwrite(32'h80000002,"Assertion failed\n    at Regfile.scala:243 assert(!write_fail)\n"); // @[Regfile.scala 243:13]
         end
     `ifdef PRINTF_COND
       end
@@ -3787,7 +3789,7 @@
       if (`STOP_COND) begin
     `endif
         if (_T_21 & ~(~write_fail_13)) begin
-          $fatal; // @[Regfile.scala 242:13]
+          $fatal; // @[Regfile.scala 243:13]
         end
     `ifdef STOP_COND
       end
@@ -3798,7 +3800,7 @@
       if (`PRINTF_COND) begin
     `endif
         if (_T_21 & ~(~write_fail_13)) begin
-          $fwrite(32'h80000002,"Assertion failed\n    at Regfile.scala:242 assert(!write_fail)\n"); // @[Regfile.scala 242:13]
+          $fwrite(32'h80000002,"Assertion failed\n    at Regfile.scala:243 assert(!write_fail)\n"); // @[Regfile.scala 243:13]
         end
     `ifdef PRINTF_COND
       end
@@ -3809,7 +3811,7 @@
       if (`STOP_COND) begin
     `endif
         if (_T_21 & ~(~write_fail_14)) begin
-          $fatal; // @[Regfile.scala 242:13]
+          $fatal; // @[Regfile.scala 243:13]
         end
     `ifdef STOP_COND
       end
@@ -3820,7 +3822,7 @@
       if (`PRINTF_COND) begin
     `endif
         if (_T_21 & ~(~write_fail_14)) begin
-          $fwrite(32'h80000002,"Assertion failed\n    at Regfile.scala:242 assert(!write_fail)\n"); // @[Regfile.scala 242:13]
+          $fwrite(32'h80000002,"Assertion failed\n    at Regfile.scala:243 assert(!write_fail)\n"); // @[Regfile.scala 243:13]
         end
     `ifdef PRINTF_COND
       end
@@ -3831,7 +3833,7 @@
       if (`STOP_COND) begin
     `endif
         if (_T_21 & ~(~scoreboard_error)) begin
-          $fatal; // @[Regfile.scala 248:9]
+          $fatal; // @[Regfile.scala 249:9]
         end
     `ifdef STOP_COND
       end
@@ -3842,7 +3844,7 @@
       if (`PRINTF_COND) begin
     `endif
         if (_T_21 & ~(~scoreboard_error)) begin
-          $fwrite(32'h80000002,"Assertion failed\n    at Regfile.scala:248 assert(!scoreboard_error)\n"); // @[Regfile.scala 248:9]
+          $fwrite(32'h80000002,"Assertion failed\n    at Regfile.scala:249 assert(!scoreboard_error)\n"); // @[Regfile.scala 249:9]
         end
     `ifdef PRINTF_COND
       end
@@ -3857,168 +3859,168 @@
     end
   end
   always @(posedge clock or posedge reset) begin
-    if (reset) begin // @[Regfile.scala 190:49]
+    if (reset) begin // @[Regfile.scala 191:49]
       readDataReady_0 <= 1'h0;
     end else begin
       readDataReady_0 <= io_readAddr_0_valid | io_readSet_0_valid;
     end
   end
   always @(posedge clock or posedge reset) begin
-    if (reset) begin // @[Regfile.scala 190:49]
+    if (reset) begin // @[Regfile.scala 191:49]
       readDataReady_1 <= 1'h0;
     end else begin
       readDataReady_1 <= io_readAddr_1_valid | io_readSet_1_valid;
     end
   end
   always @(posedge clock or posedge reset) begin
-    if (reset) begin // @[Regfile.scala 190:49]
+    if (reset) begin // @[Regfile.scala 191:49]
       readDataReady_2 <= 1'h0;
     end else begin
       readDataReady_2 <= io_readAddr_2_valid | io_readSet_2_valid;
     end
   end
   always @(posedge clock or posedge reset) begin
-    if (reset) begin // @[Regfile.scala 190:49]
+    if (reset) begin // @[Regfile.scala 191:49]
       readDataReady_3 <= 1'h0;
     end else begin
       readDataReady_3 <= io_readAddr_3_valid | io_readSet_3_valid;
     end
   end
   always @(posedge clock or posedge reset) begin
-    if (reset) begin // @[Regfile.scala 190:49]
+    if (reset) begin // @[Regfile.scala 191:49]
       readDataReady_4 <= 1'h0;
     end else begin
       readDataReady_4 <= io_readAddr_4_valid | io_readSet_4_valid;
     end
   end
   always @(posedge clock or posedge reset) begin
-    if (reset) begin // @[Regfile.scala 190:49]
+    if (reset) begin // @[Regfile.scala 191:49]
       readDataReady_5 <= 1'h0;
     end else begin
       readDataReady_5 <= io_readAddr_5_valid | io_readSet_5_valid;
     end
   end
   always @(posedge clock or posedge reset) begin
-    if (reset) begin // @[Regfile.scala 190:49]
+    if (reset) begin // @[Regfile.scala 191:49]
       readDataReady_6 <= 1'h0;
     end else begin
       readDataReady_6 <= io_readAddr_6_valid | io_readSet_6_valid;
     end
   end
   always @(posedge clock or posedge reset) begin
-    if (reset) begin // @[Regfile.scala 190:49]
+    if (reset) begin // @[Regfile.scala 191:49]
       readDataReady_7 <= 1'h0;
     end else begin
       readDataReady_7 <= io_readAddr_7_valid | io_readSet_7_valid;
     end
   end
   always @(posedge clock or posedge reset) begin
-    if (reset) begin // @[Regfile.scala 240:67]
+    if (reset) begin // @[Regfile.scala 241:67]
       write_fail <= 1'h0;
     end else begin
       write_fail <= _write_fail_T_2 & _write_fail_T_3;
     end
   end
   always @(posedge clock or posedge reset) begin
-    if (reset) begin // @[Regfile.scala 240:67]
+    if (reset) begin // @[Regfile.scala 241:67]
       write_fail_1 <= 1'h0;
     end else begin
       write_fail_1 <= _write_fail_T_7 & _write_fail_T_3;
     end
   end
   always @(posedge clock or posedge reset) begin
-    if (reset) begin // @[Regfile.scala 240:67]
+    if (reset) begin // @[Regfile.scala 241:67]
       write_fail_2 <= 1'h0;
     end else begin
       write_fail_2 <= _write_fail_T_12 & _write_fail_T_3;
     end
   end
   always @(posedge clock or posedge reset) begin
-    if (reset) begin // @[Regfile.scala 240:67]
+    if (reset) begin // @[Regfile.scala 241:67]
       write_fail_3 <= 1'h0;
     end else begin
       write_fail_3 <= _write_fail_T_17 & _write_fail_T_3;
     end
   end
   always @(posedge clock or posedge reset) begin
-    if (reset) begin // @[Regfile.scala 240:67]
+    if (reset) begin // @[Regfile.scala 241:67]
       write_fail_4 <= 1'h0;
     end else begin
       write_fail_4 <= _write_fail_T_22 & _write_fail_T_3;
     end
   end
   always @(posedge clock or posedge reset) begin
-    if (reset) begin // @[Regfile.scala 240:67]
+    if (reset) begin // @[Regfile.scala 241:67]
       write_fail_5 <= 1'h0;
     end else begin
       write_fail_5 <= _write_fail_T_27 & _write_fail_T_28;
     end
   end
   always @(posedge clock or posedge reset) begin
-    if (reset) begin // @[Regfile.scala 240:67]
+    if (reset) begin // @[Regfile.scala 241:67]
       write_fail_6 <= 1'h0;
     end else begin
       write_fail_6 <= _write_fail_T_32 & _write_fail_T_28;
     end
   end
   always @(posedge clock or posedge reset) begin
-    if (reset) begin // @[Regfile.scala 240:67]
+    if (reset) begin // @[Regfile.scala 241:67]
       write_fail_7 <= 1'h0;
     end else begin
       write_fail_7 <= _write_fail_T_37 & _write_fail_T_28;
     end
   end
   always @(posedge clock or posedge reset) begin
-    if (reset) begin // @[Regfile.scala 240:67]
+    if (reset) begin // @[Regfile.scala 241:67]
       write_fail_8 <= 1'h0;
     end else begin
       write_fail_8 <= _write_fail_T_42 & _write_fail_T_28;
     end
   end
   always @(posedge clock or posedge reset) begin
-    if (reset) begin // @[Regfile.scala 240:67]
+    if (reset) begin // @[Regfile.scala 241:67]
       write_fail_9 <= 1'h0;
     end else begin
       write_fail_9 <= _write_fail_T_47 & _write_fail_T_48;
     end
   end
   always @(posedge clock or posedge reset) begin
-    if (reset) begin // @[Regfile.scala 240:67]
+    if (reset) begin // @[Regfile.scala 241:67]
       write_fail_10 <= 1'h0;
     end else begin
       write_fail_10 <= _write_fail_T_52 & _write_fail_T_48;
     end
   end
   always @(posedge clock or posedge reset) begin
-    if (reset) begin // @[Regfile.scala 240:67]
+    if (reset) begin // @[Regfile.scala 241:67]
       write_fail_11 <= 1'h0;
     end else begin
       write_fail_11 <= _write_fail_T_57 & _write_fail_T_48;
     end
   end
   always @(posedge clock or posedge reset) begin
-    if (reset) begin // @[Regfile.scala 240:67]
+    if (reset) begin // @[Regfile.scala 241:67]
       write_fail_12 <= 1'h0;
     end else begin
       write_fail_12 <= _write_fail_T_62 & _write_fail_T_63;
     end
   end
   always @(posedge clock or posedge reset) begin
-    if (reset) begin // @[Regfile.scala 240:67]
+    if (reset) begin // @[Regfile.scala 241:67]
       write_fail_13 <= 1'h0;
     end else begin
       write_fail_13 <= _write_fail_T_67 & _write_fail_T_63;
     end
   end
   always @(posedge clock or posedge reset) begin
-    if (reset) begin // @[Regfile.scala 240:67]
+    if (reset) begin // @[Regfile.scala 241:67]
       write_fail_14 <= 1'h0;
     end else begin
       write_fail_14 <= _write_fail_T_72 & _write_fail_T_73;
     end
   end
   always @(posedge clock or posedge reset) begin
-    if (reset) begin // @[Regfile.scala 247:53]
+    if (reset) begin // @[Regfile.scala 248:53]
       scoreboard_error <= 1'h0;
     end else begin
       scoreboard_error <= _scoreboard_error_T != scoreboard_clr;
@@ -4740,155 +4742,155 @@
   wire [21:0] l0tag1_value_5_0 = l0tag1_value_4_0 | l0tag1_value_4_1; // @[Library.scala 115:37]
   wire  match0 = l0valid0 & instTag0 == l0tag0_value_5_0; // @[Fetch.scala 105:25]
   wire  match1 = l0valid1 & instTag1 == l0tag1_value_5_0; // @[Fetch.scala 106:25]
-  wire  jal_bit = instBits_0[31]; // @[Library.scala 316:23]
-  wire  jal_bit_1 = instBits_0[30]; // @[Library.scala 316:23]
-  wire  jal_bit_2 = instBits_0[29]; // @[Library.scala 316:23]
-  wire  jal_bit_3 = instBits_0[28]; // @[Library.scala 316:23]
-  wire  jal_bit_4 = instBits_0[27]; // @[Library.scala 316:23]
-  wire  jal_bit_5 = instBits_0[26]; // @[Library.scala 316:23]
-  wire  jal_bit_6 = instBits_0[25]; // @[Library.scala 316:23]
-  wire  jal_bit_7 = instBits_0[24]; // @[Library.scala 316:23]
-  wire  jal_bit_8 = instBits_0[23]; // @[Library.scala 316:23]
-  wire  jal_bit_9 = instBits_0[22]; // @[Library.scala 316:23]
-  wire  jal_bit_10 = instBits_0[21]; // @[Library.scala 316:23]
-  wire  jal_bit_11 = instBits_0[20]; // @[Library.scala 316:23]
-  wire  jal_bit_12 = instBits_0[19]; // @[Library.scala 316:23]
-  wire  jal_bit_13 = instBits_0[18]; // @[Library.scala 316:23]
-  wire  jal_bit_14 = instBits_0[17]; // @[Library.scala 316:23]
-  wire  jal_bit_15 = instBits_0[16]; // @[Library.scala 316:23]
-  wire  jal_bit_16 = instBits_0[15]; // @[Library.scala 316:23]
-  wire  jal_bit_17 = instBits_0[14]; // @[Library.scala 316:23]
-  wire  jal_bit_18 = instBits_0[13]; // @[Library.scala 316:23]
-  wire  jal_bit_19 = instBits_0[12]; // @[Library.scala 316:23]
-  wire  jal_bit_20 = instBits_0[11]; // @[Library.scala 316:23]
-  wire  jal_bit_21 = instBits_0[10]; // @[Library.scala 316:23]
-  wire  jal_bit_22 = instBits_0[9]; // @[Library.scala 316:23]
-  wire  jal_bit_23 = instBits_0[8]; // @[Library.scala 316:23]
-  wire  jal_bit_24 = instBits_0[7]; // @[Library.scala 316:23]
-  wire  jal_bit_25 = instBits_0[6]; // @[Library.scala 313:23]
-  wire  jal_bit_26 = instBits_0[5]; // @[Library.scala 313:23]
-  wire  _jal_T_1 = jal_bit_25 & jal_bit_26; // @[Library.scala 314:48]
-  wire  jal_bit_27 = ~instBits_0[4]; // @[Library.scala 310:19]
-  wire  _jal_T_2 = _jal_T_1 & jal_bit_27; // @[Library.scala 311:48]
-  wire  jal_bit_28 = instBits_0[3]; // @[Library.scala 313:23]
-  wire  jal_bit_29 = instBits_0[2]; // @[Library.scala 313:23]
-  wire  jal_bit_30 = instBits_0[1]; // @[Library.scala 313:23]
-  wire  jal_bit_31 = instBits_0[0]; // @[Library.scala 313:23]
-  wire  preBranchTaken0 = _jal_T_2 & jal_bit_28 & jal_bit_29 & jal_bit_30 & jal_bit_31; // @[Library.scala 314:48]
+  wire  jal_bit = instBits_0[31]; // @[Library.scala 318:23]
+  wire  jal_bit_1 = instBits_0[30]; // @[Library.scala 318:23]
+  wire  jal_bit_2 = instBits_0[29]; // @[Library.scala 318:23]
+  wire  jal_bit_3 = instBits_0[28]; // @[Library.scala 318:23]
+  wire  jal_bit_4 = instBits_0[27]; // @[Library.scala 318:23]
+  wire  jal_bit_5 = instBits_0[26]; // @[Library.scala 318:23]
+  wire  jal_bit_6 = instBits_0[25]; // @[Library.scala 318:23]
+  wire  jal_bit_7 = instBits_0[24]; // @[Library.scala 318:23]
+  wire  jal_bit_8 = instBits_0[23]; // @[Library.scala 318:23]
+  wire  jal_bit_9 = instBits_0[22]; // @[Library.scala 318:23]
+  wire  jal_bit_10 = instBits_0[21]; // @[Library.scala 318:23]
+  wire  jal_bit_11 = instBits_0[20]; // @[Library.scala 318:23]
+  wire  jal_bit_12 = instBits_0[19]; // @[Library.scala 318:23]
+  wire  jal_bit_13 = instBits_0[18]; // @[Library.scala 318:23]
+  wire  jal_bit_14 = instBits_0[17]; // @[Library.scala 318:23]
+  wire  jal_bit_15 = instBits_0[16]; // @[Library.scala 318:23]
+  wire  jal_bit_16 = instBits_0[15]; // @[Library.scala 318:23]
+  wire  jal_bit_17 = instBits_0[14]; // @[Library.scala 318:23]
+  wire  jal_bit_18 = instBits_0[13]; // @[Library.scala 318:23]
+  wire  jal_bit_19 = instBits_0[12]; // @[Library.scala 318:23]
+  wire  jal_bit_20 = instBits_0[11]; // @[Library.scala 318:23]
+  wire  jal_bit_21 = instBits_0[10]; // @[Library.scala 318:23]
+  wire  jal_bit_22 = instBits_0[9]; // @[Library.scala 318:23]
+  wire  jal_bit_23 = instBits_0[8]; // @[Library.scala 318:23]
+  wire  jal_bit_24 = instBits_0[7]; // @[Library.scala 318:23]
+  wire  jal_bit_25 = instBits_0[6]; // @[Library.scala 315:23]
+  wire  jal_bit_26 = instBits_0[5]; // @[Library.scala 315:23]
+  wire  _jal_T_1 = jal_bit_25 & jal_bit_26; // @[Library.scala 316:48]
+  wire  jal_bit_27 = ~instBits_0[4]; // @[Library.scala 312:19]
+  wire  _jal_T_2 = _jal_T_1 & jal_bit_27; // @[Library.scala 313:48]
+  wire  jal_bit_28 = instBits_0[3]; // @[Library.scala 315:23]
+  wire  jal_bit_29 = instBits_0[2]; // @[Library.scala 315:23]
+  wire  jal_bit_30 = instBits_0[1]; // @[Library.scala 315:23]
+  wire  jal_bit_31 = instBits_0[0]; // @[Library.scala 315:23]
+  wire  preBranchTaken0 = _jal_T_2 & jal_bit_28 & jal_bit_29 & jal_bit_30 & jal_bit_31; // @[Library.scala 316:48]
   wire [11:0] _immed_T_2 = jal_bit ? 12'hfff : 12'h0; // @[Bitwise.scala 74:12]
   wire [31:0] immed = {_immed_T_2,instBits_0[19:12],jal_bit_11,instBits_0[30:21],1'h0}; // @[Cat.scala 31:58]
   wire [31:0] preBranchTarget0 = instAddr_0 + immed; // @[Fetch.scala 114:23]
-  wire  jal_bit_32 = instBits_1[31]; // @[Library.scala 316:23]
-  wire  jal_bit_33 = instBits_1[30]; // @[Library.scala 316:23]
-  wire  jal_bit_34 = instBits_1[29]; // @[Library.scala 316:23]
-  wire  jal_bit_35 = instBits_1[28]; // @[Library.scala 316:23]
-  wire  jal_bit_36 = instBits_1[27]; // @[Library.scala 316:23]
-  wire  jal_bit_37 = instBits_1[26]; // @[Library.scala 316:23]
-  wire  jal_bit_38 = instBits_1[25]; // @[Library.scala 316:23]
-  wire  jal_bit_39 = instBits_1[24]; // @[Library.scala 316:23]
-  wire  jal_bit_40 = instBits_1[23]; // @[Library.scala 316:23]
-  wire  jal_bit_41 = instBits_1[22]; // @[Library.scala 316:23]
-  wire  jal_bit_42 = instBits_1[21]; // @[Library.scala 316:23]
-  wire  jal_bit_43 = instBits_1[20]; // @[Library.scala 316:23]
-  wire  jal_bit_44 = instBits_1[19]; // @[Library.scala 316:23]
-  wire  jal_bit_45 = instBits_1[18]; // @[Library.scala 316:23]
-  wire  jal_bit_46 = instBits_1[17]; // @[Library.scala 316:23]
-  wire  jal_bit_47 = instBits_1[16]; // @[Library.scala 316:23]
-  wire  jal_bit_48 = instBits_1[15]; // @[Library.scala 316:23]
-  wire  jal_bit_49 = instBits_1[14]; // @[Library.scala 316:23]
-  wire  jal_bit_50 = instBits_1[13]; // @[Library.scala 316:23]
-  wire  jal_bit_51 = instBits_1[12]; // @[Library.scala 316:23]
-  wire  jal_bit_52 = instBits_1[11]; // @[Library.scala 316:23]
-  wire  jal_bit_53 = instBits_1[10]; // @[Library.scala 316:23]
-  wire  jal_bit_54 = instBits_1[9]; // @[Library.scala 316:23]
-  wire  jal_bit_55 = instBits_1[8]; // @[Library.scala 316:23]
-  wire  jal_bit_56 = instBits_1[7]; // @[Library.scala 316:23]
-  wire  jal_bit_57 = instBits_1[6]; // @[Library.scala 313:23]
-  wire  jal_bit_58 = instBits_1[5]; // @[Library.scala 313:23]
-  wire  _jal_T_7 = jal_bit_57 & jal_bit_58; // @[Library.scala 314:48]
-  wire  jal_bit_59 = ~instBits_1[4]; // @[Library.scala 310:19]
-  wire  _jal_T_8 = _jal_T_7 & jal_bit_59; // @[Library.scala 311:48]
-  wire  jal_bit_60 = instBits_1[3]; // @[Library.scala 313:23]
-  wire  jal_bit_61 = instBits_1[2]; // @[Library.scala 313:23]
-  wire  jal_bit_62 = instBits_1[1]; // @[Library.scala 313:23]
-  wire  jal_bit_63 = instBits_1[0]; // @[Library.scala 313:23]
-  wire  preBranchTaken1 = _jal_T_8 & jal_bit_60 & jal_bit_61 & jal_bit_62 & jal_bit_63; // @[Library.scala 314:48]
+  wire  jal_bit_32 = instBits_1[31]; // @[Library.scala 318:23]
+  wire  jal_bit_33 = instBits_1[30]; // @[Library.scala 318:23]
+  wire  jal_bit_34 = instBits_1[29]; // @[Library.scala 318:23]
+  wire  jal_bit_35 = instBits_1[28]; // @[Library.scala 318:23]
+  wire  jal_bit_36 = instBits_1[27]; // @[Library.scala 318:23]
+  wire  jal_bit_37 = instBits_1[26]; // @[Library.scala 318:23]
+  wire  jal_bit_38 = instBits_1[25]; // @[Library.scala 318:23]
+  wire  jal_bit_39 = instBits_1[24]; // @[Library.scala 318:23]
+  wire  jal_bit_40 = instBits_1[23]; // @[Library.scala 318:23]
+  wire  jal_bit_41 = instBits_1[22]; // @[Library.scala 318:23]
+  wire  jal_bit_42 = instBits_1[21]; // @[Library.scala 318:23]
+  wire  jal_bit_43 = instBits_1[20]; // @[Library.scala 318:23]
+  wire  jal_bit_44 = instBits_1[19]; // @[Library.scala 318:23]
+  wire  jal_bit_45 = instBits_1[18]; // @[Library.scala 318:23]
+  wire  jal_bit_46 = instBits_1[17]; // @[Library.scala 318:23]
+  wire  jal_bit_47 = instBits_1[16]; // @[Library.scala 318:23]
+  wire  jal_bit_48 = instBits_1[15]; // @[Library.scala 318:23]
+  wire  jal_bit_49 = instBits_1[14]; // @[Library.scala 318:23]
+  wire  jal_bit_50 = instBits_1[13]; // @[Library.scala 318:23]
+  wire  jal_bit_51 = instBits_1[12]; // @[Library.scala 318:23]
+  wire  jal_bit_52 = instBits_1[11]; // @[Library.scala 318:23]
+  wire  jal_bit_53 = instBits_1[10]; // @[Library.scala 318:23]
+  wire  jal_bit_54 = instBits_1[9]; // @[Library.scala 318:23]
+  wire  jal_bit_55 = instBits_1[8]; // @[Library.scala 318:23]
+  wire  jal_bit_56 = instBits_1[7]; // @[Library.scala 318:23]
+  wire  jal_bit_57 = instBits_1[6]; // @[Library.scala 315:23]
+  wire  jal_bit_58 = instBits_1[5]; // @[Library.scala 315:23]
+  wire  _jal_T_7 = jal_bit_57 & jal_bit_58; // @[Library.scala 316:48]
+  wire  jal_bit_59 = ~instBits_1[4]; // @[Library.scala 312:19]
+  wire  _jal_T_8 = _jal_T_7 & jal_bit_59; // @[Library.scala 313:48]
+  wire  jal_bit_60 = instBits_1[3]; // @[Library.scala 315:23]
+  wire  jal_bit_61 = instBits_1[2]; // @[Library.scala 315:23]
+  wire  jal_bit_62 = instBits_1[1]; // @[Library.scala 315:23]
+  wire  jal_bit_63 = instBits_1[0]; // @[Library.scala 315:23]
+  wire  preBranchTaken1 = _jal_T_8 & jal_bit_60 & jal_bit_61 & jal_bit_62 & jal_bit_63; // @[Library.scala 316:48]
   wire [11:0] _immed_T_8 = jal_bit_32 ? 12'hfff : 12'h0; // @[Bitwise.scala 74:12]
   wire [31:0] immed_1 = {_immed_T_8,instBits_1[19:12],jal_bit_43,instBits_1[30:21],1'h0}; // @[Cat.scala 31:58]
   wire [31:0] preBranchTarget1 = instAddr_1 + immed_1; // @[Fetch.scala 114:23]
-  wire  jal_bit_64 = instBits_2[31]; // @[Library.scala 316:23]
-  wire  jal_bit_65 = instBits_2[30]; // @[Library.scala 316:23]
-  wire  jal_bit_66 = instBits_2[29]; // @[Library.scala 316:23]
-  wire  jal_bit_67 = instBits_2[28]; // @[Library.scala 316:23]
-  wire  jal_bit_68 = instBits_2[27]; // @[Library.scala 316:23]
-  wire  jal_bit_69 = instBits_2[26]; // @[Library.scala 316:23]
-  wire  jal_bit_70 = instBits_2[25]; // @[Library.scala 316:23]
-  wire  jal_bit_71 = instBits_2[24]; // @[Library.scala 316:23]
-  wire  jal_bit_72 = instBits_2[23]; // @[Library.scala 316:23]
-  wire  jal_bit_73 = instBits_2[22]; // @[Library.scala 316:23]
-  wire  jal_bit_74 = instBits_2[21]; // @[Library.scala 316:23]
-  wire  jal_bit_75 = instBits_2[20]; // @[Library.scala 316:23]
-  wire  jal_bit_76 = instBits_2[19]; // @[Library.scala 316:23]
-  wire  jal_bit_77 = instBits_2[18]; // @[Library.scala 316:23]
-  wire  jal_bit_78 = instBits_2[17]; // @[Library.scala 316:23]
-  wire  jal_bit_79 = instBits_2[16]; // @[Library.scala 316:23]
-  wire  jal_bit_80 = instBits_2[15]; // @[Library.scala 316:23]
-  wire  jal_bit_81 = instBits_2[14]; // @[Library.scala 316:23]
-  wire  jal_bit_82 = instBits_2[13]; // @[Library.scala 316:23]
-  wire  jal_bit_83 = instBits_2[12]; // @[Library.scala 316:23]
-  wire  jal_bit_84 = instBits_2[11]; // @[Library.scala 316:23]
-  wire  jal_bit_85 = instBits_2[10]; // @[Library.scala 316:23]
-  wire  jal_bit_86 = instBits_2[9]; // @[Library.scala 316:23]
-  wire  jal_bit_87 = instBits_2[8]; // @[Library.scala 316:23]
-  wire  jal_bit_88 = instBits_2[7]; // @[Library.scala 316:23]
-  wire  jal_bit_89 = instBits_2[6]; // @[Library.scala 313:23]
-  wire  jal_bit_90 = instBits_2[5]; // @[Library.scala 313:23]
-  wire  _jal_T_13 = jal_bit_89 & jal_bit_90; // @[Library.scala 314:48]
-  wire  jal_bit_91 = ~instBits_2[4]; // @[Library.scala 310:19]
-  wire  _jal_T_14 = _jal_T_13 & jal_bit_91; // @[Library.scala 311:48]
-  wire  jal_bit_92 = instBits_2[3]; // @[Library.scala 313:23]
-  wire  jal_bit_93 = instBits_2[2]; // @[Library.scala 313:23]
-  wire  jal_bit_94 = instBits_2[1]; // @[Library.scala 313:23]
-  wire  jal_bit_95 = instBits_2[0]; // @[Library.scala 313:23]
-  wire  preBranchTaken2 = _jal_T_14 & jal_bit_92 & jal_bit_93 & jal_bit_94 & jal_bit_95; // @[Library.scala 314:48]
+  wire  jal_bit_64 = instBits_2[31]; // @[Library.scala 318:23]
+  wire  jal_bit_65 = instBits_2[30]; // @[Library.scala 318:23]
+  wire  jal_bit_66 = instBits_2[29]; // @[Library.scala 318:23]
+  wire  jal_bit_67 = instBits_2[28]; // @[Library.scala 318:23]
+  wire  jal_bit_68 = instBits_2[27]; // @[Library.scala 318:23]
+  wire  jal_bit_69 = instBits_2[26]; // @[Library.scala 318:23]
+  wire  jal_bit_70 = instBits_2[25]; // @[Library.scala 318:23]
+  wire  jal_bit_71 = instBits_2[24]; // @[Library.scala 318:23]
+  wire  jal_bit_72 = instBits_2[23]; // @[Library.scala 318:23]
+  wire  jal_bit_73 = instBits_2[22]; // @[Library.scala 318:23]
+  wire  jal_bit_74 = instBits_2[21]; // @[Library.scala 318:23]
+  wire  jal_bit_75 = instBits_2[20]; // @[Library.scala 318:23]
+  wire  jal_bit_76 = instBits_2[19]; // @[Library.scala 318:23]
+  wire  jal_bit_77 = instBits_2[18]; // @[Library.scala 318:23]
+  wire  jal_bit_78 = instBits_2[17]; // @[Library.scala 318:23]
+  wire  jal_bit_79 = instBits_2[16]; // @[Library.scala 318:23]
+  wire  jal_bit_80 = instBits_2[15]; // @[Library.scala 318:23]
+  wire  jal_bit_81 = instBits_2[14]; // @[Library.scala 318:23]
+  wire  jal_bit_82 = instBits_2[13]; // @[Library.scala 318:23]
+  wire  jal_bit_83 = instBits_2[12]; // @[Library.scala 318:23]
+  wire  jal_bit_84 = instBits_2[11]; // @[Library.scala 318:23]
+  wire  jal_bit_85 = instBits_2[10]; // @[Library.scala 318:23]
+  wire  jal_bit_86 = instBits_2[9]; // @[Library.scala 318:23]
+  wire  jal_bit_87 = instBits_2[8]; // @[Library.scala 318:23]
+  wire  jal_bit_88 = instBits_2[7]; // @[Library.scala 318:23]
+  wire  jal_bit_89 = instBits_2[6]; // @[Library.scala 315:23]
+  wire  jal_bit_90 = instBits_2[5]; // @[Library.scala 315:23]
+  wire  _jal_T_13 = jal_bit_89 & jal_bit_90; // @[Library.scala 316:48]
+  wire  jal_bit_91 = ~instBits_2[4]; // @[Library.scala 312:19]
+  wire  _jal_T_14 = _jal_T_13 & jal_bit_91; // @[Library.scala 313:48]
+  wire  jal_bit_92 = instBits_2[3]; // @[Library.scala 315:23]
+  wire  jal_bit_93 = instBits_2[2]; // @[Library.scala 315:23]
+  wire  jal_bit_94 = instBits_2[1]; // @[Library.scala 315:23]
+  wire  jal_bit_95 = instBits_2[0]; // @[Library.scala 315:23]
+  wire  preBranchTaken2 = _jal_T_14 & jal_bit_92 & jal_bit_93 & jal_bit_94 & jal_bit_95; // @[Library.scala 316:48]
   wire [11:0] _immed_T_14 = jal_bit_64 ? 12'hfff : 12'h0; // @[Bitwise.scala 74:12]
   wire [31:0] immed_2 = {_immed_T_14,instBits_2[19:12],jal_bit_75,instBits_2[30:21],1'h0}; // @[Cat.scala 31:58]
   wire [31:0] preBranchTarget2 = instAddr_2 + immed_2; // @[Fetch.scala 114:23]
-  wire  jal_bit_96 = instBits_3[31]; // @[Library.scala 316:23]
-  wire  jal_bit_97 = instBits_3[30]; // @[Library.scala 316:23]
-  wire  jal_bit_98 = instBits_3[29]; // @[Library.scala 316:23]
-  wire  jal_bit_99 = instBits_3[28]; // @[Library.scala 316:23]
-  wire  jal_bit_100 = instBits_3[27]; // @[Library.scala 316:23]
-  wire  jal_bit_101 = instBits_3[26]; // @[Library.scala 316:23]
-  wire  jal_bit_102 = instBits_3[25]; // @[Library.scala 316:23]
-  wire  jal_bit_103 = instBits_3[24]; // @[Library.scala 316:23]
-  wire  jal_bit_104 = instBits_3[23]; // @[Library.scala 316:23]
-  wire  jal_bit_105 = instBits_3[22]; // @[Library.scala 316:23]
-  wire  jal_bit_106 = instBits_3[21]; // @[Library.scala 316:23]
-  wire  jal_bit_107 = instBits_3[20]; // @[Library.scala 316:23]
-  wire  jal_bit_108 = instBits_3[19]; // @[Library.scala 316:23]
-  wire  jal_bit_109 = instBits_3[18]; // @[Library.scala 316:23]
-  wire  jal_bit_110 = instBits_3[17]; // @[Library.scala 316:23]
-  wire  jal_bit_111 = instBits_3[16]; // @[Library.scala 316:23]
-  wire  jal_bit_112 = instBits_3[15]; // @[Library.scala 316:23]
-  wire  jal_bit_113 = instBits_3[14]; // @[Library.scala 316:23]
-  wire  jal_bit_114 = instBits_3[13]; // @[Library.scala 316:23]
-  wire  jal_bit_115 = instBits_3[12]; // @[Library.scala 316:23]
-  wire  jal_bit_116 = instBits_3[11]; // @[Library.scala 316:23]
-  wire  jal_bit_117 = instBits_3[10]; // @[Library.scala 316:23]
-  wire  jal_bit_118 = instBits_3[9]; // @[Library.scala 316:23]
-  wire  jal_bit_119 = instBits_3[8]; // @[Library.scala 316:23]
-  wire  jal_bit_120 = instBits_3[7]; // @[Library.scala 316:23]
-  wire  jal_bit_121 = instBits_3[6]; // @[Library.scala 313:23]
-  wire  jal_bit_122 = instBits_3[5]; // @[Library.scala 313:23]
-  wire  _jal_T_19 = jal_bit_121 & jal_bit_122; // @[Library.scala 314:48]
-  wire  jal_bit_123 = ~instBits_3[4]; // @[Library.scala 310:19]
-  wire  _jal_T_20 = _jal_T_19 & jal_bit_123; // @[Library.scala 311:48]
-  wire  jal_bit_124 = instBits_3[3]; // @[Library.scala 313:23]
-  wire  jal_bit_125 = instBits_3[2]; // @[Library.scala 313:23]
-  wire  jal_bit_126 = instBits_3[1]; // @[Library.scala 313:23]
-  wire  jal_bit_127 = instBits_3[0]; // @[Library.scala 313:23]
-  wire  preBranchTaken3 = _jal_T_20 & jal_bit_124 & jal_bit_125 & jal_bit_126 & jal_bit_127; // @[Library.scala 314:48]
+  wire  jal_bit_96 = instBits_3[31]; // @[Library.scala 318:23]
+  wire  jal_bit_97 = instBits_3[30]; // @[Library.scala 318:23]
+  wire  jal_bit_98 = instBits_3[29]; // @[Library.scala 318:23]
+  wire  jal_bit_99 = instBits_3[28]; // @[Library.scala 318:23]
+  wire  jal_bit_100 = instBits_3[27]; // @[Library.scala 318:23]
+  wire  jal_bit_101 = instBits_3[26]; // @[Library.scala 318:23]
+  wire  jal_bit_102 = instBits_3[25]; // @[Library.scala 318:23]
+  wire  jal_bit_103 = instBits_3[24]; // @[Library.scala 318:23]
+  wire  jal_bit_104 = instBits_3[23]; // @[Library.scala 318:23]
+  wire  jal_bit_105 = instBits_3[22]; // @[Library.scala 318:23]
+  wire  jal_bit_106 = instBits_3[21]; // @[Library.scala 318:23]
+  wire  jal_bit_107 = instBits_3[20]; // @[Library.scala 318:23]
+  wire  jal_bit_108 = instBits_3[19]; // @[Library.scala 318:23]
+  wire  jal_bit_109 = instBits_3[18]; // @[Library.scala 318:23]
+  wire  jal_bit_110 = instBits_3[17]; // @[Library.scala 318:23]
+  wire  jal_bit_111 = instBits_3[16]; // @[Library.scala 318:23]
+  wire  jal_bit_112 = instBits_3[15]; // @[Library.scala 318:23]
+  wire  jal_bit_113 = instBits_3[14]; // @[Library.scala 318:23]
+  wire  jal_bit_114 = instBits_3[13]; // @[Library.scala 318:23]
+  wire  jal_bit_115 = instBits_3[12]; // @[Library.scala 318:23]
+  wire  jal_bit_116 = instBits_3[11]; // @[Library.scala 318:23]
+  wire  jal_bit_117 = instBits_3[10]; // @[Library.scala 318:23]
+  wire  jal_bit_118 = instBits_3[9]; // @[Library.scala 318:23]
+  wire  jal_bit_119 = instBits_3[8]; // @[Library.scala 318:23]
+  wire  jal_bit_120 = instBits_3[7]; // @[Library.scala 318:23]
+  wire  jal_bit_121 = instBits_3[6]; // @[Library.scala 315:23]
+  wire  jal_bit_122 = instBits_3[5]; // @[Library.scala 315:23]
+  wire  _jal_T_19 = jal_bit_121 & jal_bit_122; // @[Library.scala 316:48]
+  wire  jal_bit_123 = ~instBits_3[4]; // @[Library.scala 312:19]
+  wire  _jal_T_20 = _jal_T_19 & jal_bit_123; // @[Library.scala 313:48]
+  wire  jal_bit_124 = instBits_3[3]; // @[Library.scala 315:23]
+  wire  jal_bit_125 = instBits_3[2]; // @[Library.scala 315:23]
+  wire  jal_bit_126 = instBits_3[1]; // @[Library.scala 315:23]
+  wire  jal_bit_127 = instBits_3[0]; // @[Library.scala 315:23]
+  wire  preBranchTaken3 = _jal_T_20 & jal_bit_124 & jal_bit_125 & jal_bit_126 & jal_bit_127; // @[Library.scala 316:48]
   wire [11:0] _immed_T_20 = jal_bit_96 ? 12'hfff : 12'h0; // @[Bitwise.scala 74:12]
   wire [31:0] immed_3 = {_immed_T_20,instBits_3[19:12],jal_bit_107,instBits_3[30:21],1'h0}; // @[Cat.scala 31:58]
   wire [31:0] preBranchTarget3 = instAddr_3 + immed_3; // @[Fetch.scala 114:23]
@@ -5489,43 +5491,43 @@
   wire [31:0] nxtInstBits_14 = nxtInstBits1[223:192]; // @[Fetch.scala 308:39]
   wire [31:0] nxtInstBits_7 = nxtInstBits0[255:224]; // @[Fetch.scala 307:39]
   wire [31:0] nxtInstBits_15 = nxtInstBits1[255:224]; // @[Fetch.scala 308:39]
-  wire  ret_bit = ~jal_bit; // @[Library.scala 310:19]
-  wire  ret_bit_1 = ~jal_bit_1; // @[Library.scala 310:19]
-  wire  ret_bit_2 = ~jal_bit_2; // @[Library.scala 310:19]
-  wire  ret_bit_3 = ~jal_bit_3; // @[Library.scala 310:19]
-  wire  ret_bit_4 = ~jal_bit_4; // @[Library.scala 310:19]
-  wire  ret_bit_5 = ~jal_bit_5; // @[Library.scala 310:19]
-  wire  ret_bit_6 = ~jal_bit_6; // @[Library.scala 310:19]
-  wire  ret_bit_7 = ~jal_bit_7; // @[Library.scala 310:19]
-  wire  ret_bit_8 = ~jal_bit_8; // @[Library.scala 310:19]
-  wire  ret_bit_9 = ~jal_bit_9; // @[Library.scala 310:19]
-  wire  ret_bit_10 = ~jal_bit_10; // @[Library.scala 310:19]
-  wire  ret_bit_11 = ~jal_bit_11; // @[Library.scala 310:19]
-  wire  ret_bit_12 = ~jal_bit_12; // @[Library.scala 310:19]
-  wire  ret_bit_13 = ~jal_bit_13; // @[Library.scala 310:19]
-  wire  ret_bit_14 = ~jal_bit_14; // @[Library.scala 310:19]
-  wire  ret_bit_15 = ~jal_bit_15; // @[Library.scala 310:19]
+  wire  ret_bit = ~jal_bit; // @[Library.scala 312:19]
+  wire  ret_bit_1 = ~jal_bit_1; // @[Library.scala 312:19]
+  wire  ret_bit_2 = ~jal_bit_2; // @[Library.scala 312:19]
+  wire  ret_bit_3 = ~jal_bit_3; // @[Library.scala 312:19]
+  wire  ret_bit_4 = ~jal_bit_4; // @[Library.scala 312:19]
+  wire  ret_bit_5 = ~jal_bit_5; // @[Library.scala 312:19]
+  wire  ret_bit_6 = ~jal_bit_6; // @[Library.scala 312:19]
+  wire  ret_bit_7 = ~jal_bit_7; // @[Library.scala 312:19]
+  wire  ret_bit_8 = ~jal_bit_8; // @[Library.scala 312:19]
+  wire  ret_bit_9 = ~jal_bit_9; // @[Library.scala 312:19]
+  wire  ret_bit_10 = ~jal_bit_10; // @[Library.scala 312:19]
+  wire  ret_bit_11 = ~jal_bit_11; // @[Library.scala 312:19]
+  wire  ret_bit_12 = ~jal_bit_12; // @[Library.scala 312:19]
+  wire  ret_bit_13 = ~jal_bit_13; // @[Library.scala 312:19]
+  wire  ret_bit_14 = ~jal_bit_14; // @[Library.scala 312:19]
+  wire  ret_bit_15 = ~jal_bit_15; // @[Library.scala 312:19]
   wire  _ret_T_15 = ret_bit & ret_bit_1 & ret_bit_2 & ret_bit_3 & ret_bit_4 & ret_bit_5 & ret_bit_6 & ret_bit_7 &
-    ret_bit_8 & ret_bit_9 & ret_bit_10 & ret_bit_11 & ret_bit_12 & ret_bit_13 & ret_bit_14 & ret_bit_15; // @[Library.scala 311:48]
-  wire  _ret_T_16 = _ret_T_15 & jal_bit_16; // @[Library.scala 314:48]
-  wire  ret_bit_17 = ~jal_bit_17; // @[Library.scala 310:19]
-  wire  ret_bit_18 = ~jal_bit_18; // @[Library.scala 310:19]
-  wire  ret_bit_19 = ~jal_bit_19; // @[Library.scala 310:19]
-  wire  ret_bit_20 = ~jal_bit_20; // @[Library.scala 310:19]
-  wire  ret_bit_21 = ~jal_bit_21; // @[Library.scala 310:19]
-  wire  ret_bit_22 = ~jal_bit_22; // @[Library.scala 310:19]
-  wire  ret_bit_23 = ~jal_bit_23; // @[Library.scala 310:19]
-  wire  ret_bit_24 = ~jal_bit_24; // @[Library.scala 310:19]
+    ret_bit_8 & ret_bit_9 & ret_bit_10 & ret_bit_11 & ret_bit_12 & ret_bit_13 & ret_bit_14 & ret_bit_15; // @[Library.scala 313:48]
+  wire  _ret_T_16 = _ret_T_15 & jal_bit_16; // @[Library.scala 316:48]
+  wire  ret_bit_17 = ~jal_bit_17; // @[Library.scala 312:19]
+  wire  ret_bit_18 = ~jal_bit_18; // @[Library.scala 312:19]
+  wire  ret_bit_19 = ~jal_bit_19; // @[Library.scala 312:19]
+  wire  ret_bit_20 = ~jal_bit_20; // @[Library.scala 312:19]
+  wire  ret_bit_21 = ~jal_bit_21; // @[Library.scala 312:19]
+  wire  ret_bit_22 = ~jal_bit_22; // @[Library.scala 312:19]
+  wire  ret_bit_23 = ~jal_bit_23; // @[Library.scala 312:19]
+  wire  ret_bit_24 = ~jal_bit_24; // @[Library.scala 312:19]
   wire  _ret_T_24 = _ret_T_16 & ret_bit_17 & ret_bit_18 & ret_bit_19 & ret_bit_20 & ret_bit_21 & ret_bit_22 & ret_bit_23
-     & ret_bit_24; // @[Library.scala 311:48]
-  wire  _ret_T_26 = _ret_T_24 & jal_bit_25 & jal_bit_26; // @[Library.scala 314:48]
-  wire  ret_bit_28 = ~jal_bit_28; // @[Library.scala 310:19]
-  wire  _ret_T_28 = _ret_T_26 & jal_bit_27 & ret_bit_28; // @[Library.scala 311:48]
-  wire  _ret_T_31 = _ret_T_28 & jal_bit_29 & jal_bit_30 & jal_bit_31; // @[Library.scala 314:48]
+     & ret_bit_24; // @[Library.scala 313:48]
+  wire  _ret_T_26 = _ret_T_24 & jal_bit_25 & jal_bit_26; // @[Library.scala 316:48]
+  wire  ret_bit_28 = ~jal_bit_28; // @[Library.scala 312:19]
+  wire  _ret_T_28 = _ret_T_26 & jal_bit_27 & ret_bit_28; // @[Library.scala 313:48]
+  wire  _ret_T_31 = _ret_T_28 & jal_bit_29 & jal_bit_30 & jal_bit_31; // @[Library.scala 316:48]
   wire  ret = _ret_T_31 & io_linkPort_valid; // @[Fetch.scala 401:70]
-  wire  bxx_bit_29 = ~jal_bit_29; // @[Library.scala 310:19]
-  wire  _bxx_T_4 = _jal_T_1 & jal_bit_27 & ret_bit_28 & bxx_bit_29; // @[Library.scala 311:48]
-  wire  _bxx_T_6 = _bxx_T_4 & jal_bit_30 & jal_bit_31; // @[Library.scala 314:48]
+  wire  bxx_bit_29 = ~jal_bit_29; // @[Library.scala 312:19]
+  wire  _bxx_T_4 = _jal_T_1 & jal_bit_27 & ret_bit_28 & bxx_bit_29; // @[Library.scala 313:48]
+  wire  _bxx_T_6 = _bxx_T_4 & jal_bit_30 & jal_bit_31; // @[Library.scala 316:48]
   wire  _bxx_T_8 = _bxx_T_6 & jal_bit; // @[Fetch.scala 403:71]
   wire  bxx = _bxx_T_8 & instBits_0[14:13] != 2'h1; // @[Fetch.scala 404:24]
   wire [19:0] _immbxx_T_2 = jal_bit ? 20'hfffff : 20'h0; // @[Bitwise.scala 74:12]
@@ -5534,43 +5536,43 @@
   wire [31:0] _target_T_5 = instAddr_0 + immed_4; // @[Fetch.scala 408:51]
   wire [31:0] brchTargetDe0 = ret ? io_linkPort_value : _target_T_5; // @[Fetch.scala 408:21]
   wire  brchTakenDe0 = preBranchTaken0 | ret | bxx; // @[Fetch.scala 409:17]
-  wire  ret_bit_32 = ~jal_bit_32; // @[Library.scala 310:19]
-  wire  ret_bit_33 = ~jal_bit_33; // @[Library.scala 310:19]
-  wire  ret_bit_34 = ~jal_bit_34; // @[Library.scala 310:19]
-  wire  ret_bit_35 = ~jal_bit_35; // @[Library.scala 310:19]
-  wire  ret_bit_36 = ~jal_bit_36; // @[Library.scala 310:19]
-  wire  ret_bit_37 = ~jal_bit_37; // @[Library.scala 310:19]
-  wire  ret_bit_38 = ~jal_bit_38; // @[Library.scala 310:19]
-  wire  ret_bit_39 = ~jal_bit_39; // @[Library.scala 310:19]
-  wire  ret_bit_40 = ~jal_bit_40; // @[Library.scala 310:19]
-  wire  ret_bit_41 = ~jal_bit_41; // @[Library.scala 310:19]
-  wire  ret_bit_42 = ~jal_bit_42; // @[Library.scala 310:19]
-  wire  ret_bit_43 = ~jal_bit_43; // @[Library.scala 310:19]
-  wire  ret_bit_44 = ~jal_bit_44; // @[Library.scala 310:19]
-  wire  ret_bit_45 = ~jal_bit_45; // @[Library.scala 310:19]
-  wire  ret_bit_46 = ~jal_bit_46; // @[Library.scala 310:19]
-  wire  ret_bit_47 = ~jal_bit_47; // @[Library.scala 310:19]
+  wire  ret_bit_32 = ~jal_bit_32; // @[Library.scala 312:19]
+  wire  ret_bit_33 = ~jal_bit_33; // @[Library.scala 312:19]
+  wire  ret_bit_34 = ~jal_bit_34; // @[Library.scala 312:19]
+  wire  ret_bit_35 = ~jal_bit_35; // @[Library.scala 312:19]
+  wire  ret_bit_36 = ~jal_bit_36; // @[Library.scala 312:19]
+  wire  ret_bit_37 = ~jal_bit_37; // @[Library.scala 312:19]
+  wire  ret_bit_38 = ~jal_bit_38; // @[Library.scala 312:19]
+  wire  ret_bit_39 = ~jal_bit_39; // @[Library.scala 312:19]
+  wire  ret_bit_40 = ~jal_bit_40; // @[Library.scala 312:19]
+  wire  ret_bit_41 = ~jal_bit_41; // @[Library.scala 312:19]
+  wire  ret_bit_42 = ~jal_bit_42; // @[Library.scala 312:19]
+  wire  ret_bit_43 = ~jal_bit_43; // @[Library.scala 312:19]
+  wire  ret_bit_44 = ~jal_bit_44; // @[Library.scala 312:19]
+  wire  ret_bit_45 = ~jal_bit_45; // @[Library.scala 312:19]
+  wire  ret_bit_46 = ~jal_bit_46; // @[Library.scala 312:19]
+  wire  ret_bit_47 = ~jal_bit_47; // @[Library.scala 312:19]
   wire  _ret_T_47 = ret_bit_32 & ret_bit_33 & ret_bit_34 & ret_bit_35 & ret_bit_36 & ret_bit_37 & ret_bit_38 &
-    ret_bit_39 & ret_bit_40 & ret_bit_41 & ret_bit_42 & ret_bit_43 & ret_bit_44 & ret_bit_45 & ret_bit_46 & ret_bit_47; // @[Library.scala 311:48]
-  wire  _ret_T_48 = _ret_T_47 & jal_bit_48; // @[Library.scala 314:48]
-  wire  ret_bit_49 = ~jal_bit_49; // @[Library.scala 310:19]
-  wire  ret_bit_50 = ~jal_bit_50; // @[Library.scala 310:19]
-  wire  ret_bit_51 = ~jal_bit_51; // @[Library.scala 310:19]
-  wire  ret_bit_52 = ~jal_bit_52; // @[Library.scala 310:19]
-  wire  ret_bit_53 = ~jal_bit_53; // @[Library.scala 310:19]
-  wire  ret_bit_54 = ~jal_bit_54; // @[Library.scala 310:19]
-  wire  ret_bit_55 = ~jal_bit_55; // @[Library.scala 310:19]
-  wire  ret_bit_56 = ~jal_bit_56; // @[Library.scala 310:19]
+    ret_bit_39 & ret_bit_40 & ret_bit_41 & ret_bit_42 & ret_bit_43 & ret_bit_44 & ret_bit_45 & ret_bit_46 & ret_bit_47; // @[Library.scala 313:48]
+  wire  _ret_T_48 = _ret_T_47 & jal_bit_48; // @[Library.scala 316:48]
+  wire  ret_bit_49 = ~jal_bit_49; // @[Library.scala 312:19]
+  wire  ret_bit_50 = ~jal_bit_50; // @[Library.scala 312:19]
+  wire  ret_bit_51 = ~jal_bit_51; // @[Library.scala 312:19]
+  wire  ret_bit_52 = ~jal_bit_52; // @[Library.scala 312:19]
+  wire  ret_bit_53 = ~jal_bit_53; // @[Library.scala 312:19]
+  wire  ret_bit_54 = ~jal_bit_54; // @[Library.scala 312:19]
+  wire  ret_bit_55 = ~jal_bit_55; // @[Library.scala 312:19]
+  wire  ret_bit_56 = ~jal_bit_56; // @[Library.scala 312:19]
   wire  _ret_T_56 = _ret_T_48 & ret_bit_49 & ret_bit_50 & ret_bit_51 & ret_bit_52 & ret_bit_53 & ret_bit_54 & ret_bit_55
-     & ret_bit_56; // @[Library.scala 311:48]
-  wire  _ret_T_58 = _ret_T_56 & jal_bit_57 & jal_bit_58; // @[Library.scala 314:48]
-  wire  ret_bit_60 = ~jal_bit_60; // @[Library.scala 310:19]
-  wire  _ret_T_60 = _ret_T_58 & jal_bit_59 & ret_bit_60; // @[Library.scala 311:48]
-  wire  _ret_T_63 = _ret_T_60 & jal_bit_61 & jal_bit_62 & jal_bit_63; // @[Library.scala 314:48]
+     & ret_bit_56; // @[Library.scala 313:48]
+  wire  _ret_T_58 = _ret_T_56 & jal_bit_57 & jal_bit_58; // @[Library.scala 316:48]
+  wire  ret_bit_60 = ~jal_bit_60; // @[Library.scala 312:19]
+  wire  _ret_T_60 = _ret_T_58 & jal_bit_59 & ret_bit_60; // @[Library.scala 313:48]
+  wire  _ret_T_63 = _ret_T_60 & jal_bit_61 & jal_bit_62 & jal_bit_63; // @[Library.scala 316:48]
   wire  ret_1 = _ret_T_63 & io_linkPort_valid; // @[Fetch.scala 401:70]
-  wire  bxx_bit_61 = ~jal_bit_61; // @[Library.scala 310:19]
-  wire  _bxx_T_15 = _jal_T_7 & jal_bit_59 & ret_bit_60 & bxx_bit_61; // @[Library.scala 311:48]
-  wire  _bxx_T_17 = _bxx_T_15 & jal_bit_62 & jal_bit_63; // @[Library.scala 314:48]
+  wire  bxx_bit_61 = ~jal_bit_61; // @[Library.scala 312:19]
+  wire  _bxx_T_15 = _jal_T_7 & jal_bit_59 & ret_bit_60 & bxx_bit_61; // @[Library.scala 313:48]
+  wire  _bxx_T_17 = _bxx_T_15 & jal_bit_62 & jal_bit_63; // @[Library.scala 316:48]
   wire  _bxx_T_19 = _bxx_T_17 & jal_bit_32; // @[Fetch.scala 403:71]
   wire  bxx_1 = _bxx_T_19 & instBits_1[14:13] != 2'h1; // @[Fetch.scala 404:24]
   wire [19:0] _immbxx_T_8 = jal_bit_32 ? 20'hfffff : 20'h0; // @[Bitwise.scala 74:12]
@@ -5579,43 +5581,43 @@
   wire [31:0] _target_T_7 = instAddr_1 + immed_5; // @[Fetch.scala 408:51]
   wire [31:0] brchTargetDe1 = ret_1 ? io_linkPort_value : _target_T_7; // @[Fetch.scala 408:21]
   wire  brchTakenDe1 = preBranchTaken1 | ret_1 | bxx_1; // @[Fetch.scala 409:17]
-  wire  ret_bit_64 = ~jal_bit_64; // @[Library.scala 310:19]
-  wire  ret_bit_65 = ~jal_bit_65; // @[Library.scala 310:19]
-  wire  ret_bit_66 = ~jal_bit_66; // @[Library.scala 310:19]
-  wire  ret_bit_67 = ~jal_bit_67; // @[Library.scala 310:19]
-  wire  ret_bit_68 = ~jal_bit_68; // @[Library.scala 310:19]
-  wire  ret_bit_69 = ~jal_bit_69; // @[Library.scala 310:19]
-  wire  ret_bit_70 = ~jal_bit_70; // @[Library.scala 310:19]
-  wire  ret_bit_71 = ~jal_bit_71; // @[Library.scala 310:19]
-  wire  ret_bit_72 = ~jal_bit_72; // @[Library.scala 310:19]
-  wire  ret_bit_73 = ~jal_bit_73; // @[Library.scala 310:19]
-  wire  ret_bit_74 = ~jal_bit_74; // @[Library.scala 310:19]
-  wire  ret_bit_75 = ~jal_bit_75; // @[Library.scala 310:19]
-  wire  ret_bit_76 = ~jal_bit_76; // @[Library.scala 310:19]
-  wire  ret_bit_77 = ~jal_bit_77; // @[Library.scala 310:19]
-  wire  ret_bit_78 = ~jal_bit_78; // @[Library.scala 310:19]
-  wire  ret_bit_79 = ~jal_bit_79; // @[Library.scala 310:19]
+  wire  ret_bit_64 = ~jal_bit_64; // @[Library.scala 312:19]
+  wire  ret_bit_65 = ~jal_bit_65; // @[Library.scala 312:19]
+  wire  ret_bit_66 = ~jal_bit_66; // @[Library.scala 312:19]
+  wire  ret_bit_67 = ~jal_bit_67; // @[Library.scala 312:19]
+  wire  ret_bit_68 = ~jal_bit_68; // @[Library.scala 312:19]
+  wire  ret_bit_69 = ~jal_bit_69; // @[Library.scala 312:19]
+  wire  ret_bit_70 = ~jal_bit_70; // @[Library.scala 312:19]
+  wire  ret_bit_71 = ~jal_bit_71; // @[Library.scala 312:19]
+  wire  ret_bit_72 = ~jal_bit_72; // @[Library.scala 312:19]
+  wire  ret_bit_73 = ~jal_bit_73; // @[Library.scala 312:19]
+  wire  ret_bit_74 = ~jal_bit_74; // @[Library.scala 312:19]
+  wire  ret_bit_75 = ~jal_bit_75; // @[Library.scala 312:19]
+  wire  ret_bit_76 = ~jal_bit_76; // @[Library.scala 312:19]
+  wire  ret_bit_77 = ~jal_bit_77; // @[Library.scala 312:19]
+  wire  ret_bit_78 = ~jal_bit_78; // @[Library.scala 312:19]
+  wire  ret_bit_79 = ~jal_bit_79; // @[Library.scala 312:19]
   wire  _ret_T_79 = ret_bit_64 & ret_bit_65 & ret_bit_66 & ret_bit_67 & ret_bit_68 & ret_bit_69 & ret_bit_70 &
-    ret_bit_71 & ret_bit_72 & ret_bit_73 & ret_bit_74 & ret_bit_75 & ret_bit_76 & ret_bit_77 & ret_bit_78 & ret_bit_79; // @[Library.scala 311:48]
-  wire  _ret_T_80 = _ret_T_79 & jal_bit_80; // @[Library.scala 314:48]
-  wire  ret_bit_81 = ~jal_bit_81; // @[Library.scala 310:19]
-  wire  ret_bit_82 = ~jal_bit_82; // @[Library.scala 310:19]
-  wire  ret_bit_83 = ~jal_bit_83; // @[Library.scala 310:19]
-  wire  ret_bit_84 = ~jal_bit_84; // @[Library.scala 310:19]
-  wire  ret_bit_85 = ~jal_bit_85; // @[Library.scala 310:19]
-  wire  ret_bit_86 = ~jal_bit_86; // @[Library.scala 310:19]
-  wire  ret_bit_87 = ~jal_bit_87; // @[Library.scala 310:19]
-  wire  ret_bit_88 = ~jal_bit_88; // @[Library.scala 310:19]
+    ret_bit_71 & ret_bit_72 & ret_bit_73 & ret_bit_74 & ret_bit_75 & ret_bit_76 & ret_bit_77 & ret_bit_78 & ret_bit_79; // @[Library.scala 313:48]
+  wire  _ret_T_80 = _ret_T_79 & jal_bit_80; // @[Library.scala 316:48]
+  wire  ret_bit_81 = ~jal_bit_81; // @[Library.scala 312:19]
+  wire  ret_bit_82 = ~jal_bit_82; // @[Library.scala 312:19]
+  wire  ret_bit_83 = ~jal_bit_83; // @[Library.scala 312:19]
+  wire  ret_bit_84 = ~jal_bit_84; // @[Library.scala 312:19]
+  wire  ret_bit_85 = ~jal_bit_85; // @[Library.scala 312:19]
+  wire  ret_bit_86 = ~jal_bit_86; // @[Library.scala 312:19]
+  wire  ret_bit_87 = ~jal_bit_87; // @[Library.scala 312:19]
+  wire  ret_bit_88 = ~jal_bit_88; // @[Library.scala 312:19]
   wire  _ret_T_88 = _ret_T_80 & ret_bit_81 & ret_bit_82 & ret_bit_83 & ret_bit_84 & ret_bit_85 & ret_bit_86 & ret_bit_87
-     & ret_bit_88; // @[Library.scala 311:48]
-  wire  _ret_T_90 = _ret_T_88 & jal_bit_89 & jal_bit_90; // @[Library.scala 314:48]
-  wire  ret_bit_92 = ~jal_bit_92; // @[Library.scala 310:19]
-  wire  _ret_T_92 = _ret_T_90 & jal_bit_91 & ret_bit_92; // @[Library.scala 311:48]
-  wire  _ret_T_95 = _ret_T_92 & jal_bit_93 & jal_bit_94 & jal_bit_95; // @[Library.scala 314:48]
+     & ret_bit_88; // @[Library.scala 313:48]
+  wire  _ret_T_90 = _ret_T_88 & jal_bit_89 & jal_bit_90; // @[Library.scala 316:48]
+  wire  ret_bit_92 = ~jal_bit_92; // @[Library.scala 312:19]
+  wire  _ret_T_92 = _ret_T_90 & jal_bit_91 & ret_bit_92; // @[Library.scala 313:48]
+  wire  _ret_T_95 = _ret_T_92 & jal_bit_93 & jal_bit_94 & jal_bit_95; // @[Library.scala 316:48]
   wire  ret_2 = _ret_T_95 & io_linkPort_valid; // @[Fetch.scala 401:70]
-  wire  bxx_bit_93 = ~jal_bit_93; // @[Library.scala 310:19]
-  wire  _bxx_T_26 = _jal_T_13 & jal_bit_91 & ret_bit_92 & bxx_bit_93; // @[Library.scala 311:48]
-  wire  _bxx_T_28 = _bxx_T_26 & jal_bit_94 & jal_bit_95; // @[Library.scala 314:48]
+  wire  bxx_bit_93 = ~jal_bit_93; // @[Library.scala 312:19]
+  wire  _bxx_T_26 = _jal_T_13 & jal_bit_91 & ret_bit_92 & bxx_bit_93; // @[Library.scala 313:48]
+  wire  _bxx_T_28 = _bxx_T_26 & jal_bit_94 & jal_bit_95; // @[Library.scala 316:48]
   wire  _bxx_T_30 = _bxx_T_28 & jal_bit_64; // @[Fetch.scala 403:71]
   wire  bxx_2 = _bxx_T_30 & instBits_2[14:13] != 2'h1; // @[Fetch.scala 404:24]
   wire [19:0] _immbxx_T_14 = jal_bit_64 ? 20'hfffff : 20'h0; // @[Bitwise.scala 74:12]
@@ -5624,44 +5626,44 @@
   wire [31:0] _target_T_9 = instAddr_2 + immed_6; // @[Fetch.scala 408:51]
   wire [31:0] brchTargetDe2 = ret_2 ? io_linkPort_value : _target_T_9; // @[Fetch.scala 408:21]
   wire  brchTakenDe2 = preBranchTaken2 | ret_2 | bxx_2; // @[Fetch.scala 409:17]
-  wire  ret_bit_96 = ~jal_bit_96; // @[Library.scala 310:19]
-  wire  ret_bit_97 = ~jal_bit_97; // @[Library.scala 310:19]
-  wire  ret_bit_98 = ~jal_bit_98; // @[Library.scala 310:19]
-  wire  ret_bit_99 = ~jal_bit_99; // @[Library.scala 310:19]
-  wire  ret_bit_100 = ~jal_bit_100; // @[Library.scala 310:19]
-  wire  ret_bit_101 = ~jal_bit_101; // @[Library.scala 310:19]
-  wire  ret_bit_102 = ~jal_bit_102; // @[Library.scala 310:19]
-  wire  ret_bit_103 = ~jal_bit_103; // @[Library.scala 310:19]
-  wire  ret_bit_104 = ~jal_bit_104; // @[Library.scala 310:19]
-  wire  ret_bit_105 = ~jal_bit_105; // @[Library.scala 310:19]
-  wire  ret_bit_106 = ~jal_bit_106; // @[Library.scala 310:19]
-  wire  ret_bit_107 = ~jal_bit_107; // @[Library.scala 310:19]
-  wire  ret_bit_108 = ~jal_bit_108; // @[Library.scala 310:19]
-  wire  ret_bit_109 = ~jal_bit_109; // @[Library.scala 310:19]
-  wire  ret_bit_110 = ~jal_bit_110; // @[Library.scala 310:19]
-  wire  ret_bit_111 = ~jal_bit_111; // @[Library.scala 310:19]
+  wire  ret_bit_96 = ~jal_bit_96; // @[Library.scala 312:19]
+  wire  ret_bit_97 = ~jal_bit_97; // @[Library.scala 312:19]
+  wire  ret_bit_98 = ~jal_bit_98; // @[Library.scala 312:19]
+  wire  ret_bit_99 = ~jal_bit_99; // @[Library.scala 312:19]
+  wire  ret_bit_100 = ~jal_bit_100; // @[Library.scala 312:19]
+  wire  ret_bit_101 = ~jal_bit_101; // @[Library.scala 312:19]
+  wire  ret_bit_102 = ~jal_bit_102; // @[Library.scala 312:19]
+  wire  ret_bit_103 = ~jal_bit_103; // @[Library.scala 312:19]
+  wire  ret_bit_104 = ~jal_bit_104; // @[Library.scala 312:19]
+  wire  ret_bit_105 = ~jal_bit_105; // @[Library.scala 312:19]
+  wire  ret_bit_106 = ~jal_bit_106; // @[Library.scala 312:19]
+  wire  ret_bit_107 = ~jal_bit_107; // @[Library.scala 312:19]
+  wire  ret_bit_108 = ~jal_bit_108; // @[Library.scala 312:19]
+  wire  ret_bit_109 = ~jal_bit_109; // @[Library.scala 312:19]
+  wire  ret_bit_110 = ~jal_bit_110; // @[Library.scala 312:19]
+  wire  ret_bit_111 = ~jal_bit_111; // @[Library.scala 312:19]
   wire  _ret_T_111 = ret_bit_96 & ret_bit_97 & ret_bit_98 & ret_bit_99 & ret_bit_100 & ret_bit_101 & ret_bit_102 &
     ret_bit_103 & ret_bit_104 & ret_bit_105 & ret_bit_106 & ret_bit_107 & ret_bit_108 & ret_bit_109 & ret_bit_110 &
-    ret_bit_111; // @[Library.scala 311:48]
-  wire  _ret_T_112 = _ret_T_111 & jal_bit_112; // @[Library.scala 314:48]
-  wire  ret_bit_113 = ~jal_bit_113; // @[Library.scala 310:19]
-  wire  ret_bit_114 = ~jal_bit_114; // @[Library.scala 310:19]
-  wire  ret_bit_115 = ~jal_bit_115; // @[Library.scala 310:19]
-  wire  ret_bit_116 = ~jal_bit_116; // @[Library.scala 310:19]
-  wire  ret_bit_117 = ~jal_bit_117; // @[Library.scala 310:19]
-  wire  ret_bit_118 = ~jal_bit_118; // @[Library.scala 310:19]
-  wire  ret_bit_119 = ~jal_bit_119; // @[Library.scala 310:19]
-  wire  ret_bit_120 = ~jal_bit_120; // @[Library.scala 310:19]
+    ret_bit_111; // @[Library.scala 313:48]
+  wire  _ret_T_112 = _ret_T_111 & jal_bit_112; // @[Library.scala 316:48]
+  wire  ret_bit_113 = ~jal_bit_113; // @[Library.scala 312:19]
+  wire  ret_bit_114 = ~jal_bit_114; // @[Library.scala 312:19]
+  wire  ret_bit_115 = ~jal_bit_115; // @[Library.scala 312:19]
+  wire  ret_bit_116 = ~jal_bit_116; // @[Library.scala 312:19]
+  wire  ret_bit_117 = ~jal_bit_117; // @[Library.scala 312:19]
+  wire  ret_bit_118 = ~jal_bit_118; // @[Library.scala 312:19]
+  wire  ret_bit_119 = ~jal_bit_119; // @[Library.scala 312:19]
+  wire  ret_bit_120 = ~jal_bit_120; // @[Library.scala 312:19]
   wire  _ret_T_120 = _ret_T_112 & ret_bit_113 & ret_bit_114 & ret_bit_115 & ret_bit_116 & ret_bit_117 & ret_bit_118 &
-    ret_bit_119 & ret_bit_120; // @[Library.scala 311:48]
-  wire  _ret_T_122 = _ret_T_120 & jal_bit_121 & jal_bit_122; // @[Library.scala 314:48]
-  wire  ret_bit_124 = ~jal_bit_124; // @[Library.scala 310:19]
-  wire  _ret_T_124 = _ret_T_122 & jal_bit_123 & ret_bit_124; // @[Library.scala 311:48]
-  wire  _ret_T_127 = _ret_T_124 & jal_bit_125 & jal_bit_126 & jal_bit_127; // @[Library.scala 314:48]
+    ret_bit_119 & ret_bit_120; // @[Library.scala 313:48]
+  wire  _ret_T_122 = _ret_T_120 & jal_bit_121 & jal_bit_122; // @[Library.scala 316:48]
+  wire  ret_bit_124 = ~jal_bit_124; // @[Library.scala 312:19]
+  wire  _ret_T_124 = _ret_T_122 & jal_bit_123 & ret_bit_124; // @[Library.scala 313:48]
+  wire  _ret_T_127 = _ret_T_124 & jal_bit_125 & jal_bit_126 & jal_bit_127; // @[Library.scala 316:48]
   wire  ret_3 = _ret_T_127 & io_linkPort_valid; // @[Fetch.scala 401:70]
-  wire  bxx_bit_125 = ~jal_bit_125; // @[Library.scala 310:19]
-  wire  _bxx_T_37 = _jal_T_19 & jal_bit_123 & ret_bit_124 & bxx_bit_125; // @[Library.scala 311:48]
-  wire  _bxx_T_39 = _bxx_T_37 & jal_bit_126 & jal_bit_127; // @[Library.scala 314:48]
+  wire  bxx_bit_125 = ~jal_bit_125; // @[Library.scala 312:19]
+  wire  _bxx_T_37 = _jal_T_19 & jal_bit_123 & ret_bit_124 & bxx_bit_125; // @[Library.scala 313:48]
+  wire  _bxx_T_39 = _bxx_T_37 & jal_bit_126 & jal_bit_127; // @[Library.scala 316:48]
   wire  _bxx_T_41 = _bxx_T_39 & jal_bit_96; // @[Fetch.scala 403:71]
   wire  bxx_3 = _bxx_T_41 & instBits_3[14:13] != 2'h1; // @[Fetch.scala 404:24]
   wire [19:0] _immbxx_T_20 = jal_bit_96 ? 20'hfffff : 20'h0; // @[Bitwise.scala 74:12]
@@ -7591,33 +7593,6 @@
   output        io_divu,
   output        io_rem,
   output        io_remu,
-  output        io_flw,
-  output        io_fsw,
-  output        io_fmadd,
-  output        io_fmsub,
-  output        io_fnmsub,
-  output        io_fnmadd,
-  output        io_fadd,
-  output        io_fsub,
-  output        io_fmul,
-  output        io_fdiv,
-  output        io_fsqrt,
-  output        io_fsgnj,
-  output        io_fsgnjn,
-  output        io_fsgnjx,
-  output        io_fmin,
-  output        io_fmax,
-  output        io_fcvtws,
-  output        io_fcvtwus,
-  output        io_fmvxw,
-  output        io_feq,
-  output        io_flt,
-  output        io_fle,
-  output        io_fclass,
-  output        io_fcvtsw,
-  output        io_fcvtswu,
-  output        io_fmvwx,
-  output        io_clb,
   output        io_clz,
   output        io_ctz,
   output        io_pcnt,
@@ -7630,7 +7605,6 @@
   output        io_vld,
   output        io_vst,
   output        io_viop,
-  output        io_vfop,
   output        io_ebreak,
   output        io_ecall,
   output        io_eexit,
@@ -7654,592 +7628,428 @@
   wire [4:0] io_immbr_lo = {io_inst[11:8],1'h0}; // @[Cat.scala 31:58]
   wire [26:0] io_immbr_hi = {_io_imm12_T_2,io_inst[7],io_inst[30:25]}; // @[Cat.scala 31:58]
   wire [26:0] io_immst_hi = {_io_imm12_T_2,io_inst[31:25]}; // @[Cat.scala 31:58]
-  wire  io_lui_bit_1 = io_inst[30]; // @[Library.scala 316:23]
-  wire  io_lui_bit_2 = io_inst[29]; // @[Library.scala 316:23]
-  wire  io_lui_bit_3 = io_inst[28]; // @[Library.scala 316:23]
-  wire  io_lui_bit_4 = io_inst[27]; // @[Library.scala 316:23]
-  wire  io_lui_bit_5 = io_inst[26]; // @[Library.scala 316:23]
-  wire  io_lui_bit_6 = io_inst[25]; // @[Library.scala 316:23]
-  wire  io_lui_bit_7 = io_inst[24]; // @[Library.scala 316:23]
-  wire  io_lui_bit_8 = io_inst[23]; // @[Library.scala 316:23]
-  wire  io_lui_bit_9 = io_inst[22]; // @[Library.scala 316:23]
-  wire  io_lui_bit_10 = io_inst[21]; // @[Library.scala 316:23]
-  wire  io_lui_bit_12 = io_inst[19]; // @[Library.scala 316:23]
-  wire  io_lui_bit_13 = io_inst[18]; // @[Library.scala 316:23]
-  wire  io_lui_bit_14 = io_inst[17]; // @[Library.scala 316:23]
-  wire  io_lui_bit_15 = io_inst[16]; // @[Library.scala 316:23]
-  wire  io_lui_bit_16 = io_inst[15]; // @[Library.scala 316:23]
-  wire  io_lui_bit_17 = io_inst[14]; // @[Library.scala 316:23]
-  wire  io_lui_bit_18 = io_inst[13]; // @[Library.scala 316:23]
-  wire  io_lui_bit_19 = io_inst[12]; // @[Library.scala 316:23]
-  wire  io_lui_bit_20 = io_inst[11]; // @[Library.scala 316:23]
-  wire  io_lui_bit_21 = io_inst[10]; // @[Library.scala 316:23]
-  wire  io_lui_bit_22 = io_inst[9]; // @[Library.scala 316:23]
-  wire  io_lui_bit_23 = io_inst[8]; // @[Library.scala 316:23]
-  wire  io_lui_bit_25 = ~io_inst[6]; // @[Library.scala 310:19]
-  wire  io_lui_bit_26 = io_inst[5]; // @[Library.scala 313:23]
-  wire  io_lui_bit_27 = io_inst[4]; // @[Library.scala 313:23]
-  wire  _io_lui_T_2 = io_lui_bit_25 & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 314:48]
-  wire  io_lui_bit_28 = ~io_inst[3]; // @[Library.scala 310:19]
-  wire  _io_lui_T_3 = _io_lui_T_2 & io_lui_bit_28; // @[Library.scala 311:48]
-  wire  io_lui_bit_29 = io_inst[2]; // @[Library.scala 313:23]
-  wire  io_lui_bit_30 = io_inst[1]; // @[Library.scala 313:23]
-  wire  io_lui_bit_31 = io_inst[0]; // @[Library.scala 313:23]
-  wire  io_auipc_bit_26 = ~io_lui_bit_26; // @[Library.scala 310:19]
-  wire  _io_auipc_T_1 = io_lui_bit_25 & io_auipc_bit_26; // @[Library.scala 311:48]
-  wire  _io_auipc_T_2 = _io_auipc_T_1 & io_lui_bit_27; // @[Library.scala 314:48]
-  wire  _io_auipc_T_3 = _io_auipc_T_2 & io_lui_bit_28; // @[Library.scala 311:48]
-  wire  _io_jal_T_1 = io_inst[6] & io_lui_bit_26; // @[Library.scala 314:48]
-  wire  io_jal_bit_27 = ~io_lui_bit_27; // @[Library.scala 310:19]
-  wire  _io_jal_T_2 = _io_jal_T_1 & io_jal_bit_27; // @[Library.scala 311:48]
-  wire  io_jalr_bit_17 = ~io_lui_bit_17; // @[Library.scala 310:19]
-  wire  io_jalr_bit_18 = ~io_lui_bit_18; // @[Library.scala 310:19]
-  wire  _io_jalr_T_1 = io_jalr_bit_17 & io_jalr_bit_18; // @[Library.scala 311:48]
-  wire  io_jalr_bit_19 = ~io_lui_bit_19; // @[Library.scala 310:19]
-  wire  _io_jalr_T_2 = io_jalr_bit_17 & io_jalr_bit_18 & io_jalr_bit_19; // @[Library.scala 311:48]
-  wire  _io_jalr_T_4 = _io_jalr_T_2 & io_inst[6] & io_lui_bit_26; // @[Library.scala 314:48]
-  wire  _io_jalr_T_6 = _io_jalr_T_4 & io_jal_bit_27 & io_lui_bit_28; // @[Library.scala 311:48]
-  wire  io_beq_bit_29 = ~io_lui_bit_29; // @[Library.scala 310:19]
-  wire  _io_beq_T_7 = _io_jalr_T_4 & io_jal_bit_27 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 311:48]
-  wire  _io_bne_T_2 = _io_jalr_T_1 & io_lui_bit_19; // @[Library.scala 314:48]
-  wire  _io_bne_T_4 = _io_jalr_T_1 & io_lui_bit_19 & io_inst[6] & io_lui_bit_26; // @[Library.scala 314:48]
-  wire  _io_bne_T_7 = _io_bne_T_4 & io_jal_bit_27 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 311:48]
-  wire  _io_blt_T_1 = io_lui_bit_17 & io_jalr_bit_18; // @[Library.scala 311:48]
-  wire  _io_blt_T_2 = io_lui_bit_17 & io_jalr_bit_18 & io_jalr_bit_19; // @[Library.scala 311:48]
-  wire  _io_blt_T_4 = _io_blt_T_2 & io_inst[6] & io_lui_bit_26; // @[Library.scala 314:48]
-  wire  _io_blt_T_7 = _io_blt_T_4 & io_jal_bit_27 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 311:48]
-  wire  _io_bge_T_2 = _io_blt_T_1 & io_lui_bit_19; // @[Library.scala 314:48]
-  wire  _io_bge_T_4 = _io_blt_T_1 & io_lui_bit_19 & io_inst[6] & io_lui_bit_26; // @[Library.scala 314:48]
-  wire  _io_bge_T_7 = _io_bge_T_4 & io_jal_bit_27 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 311:48]
-  wire  _io_bltu_T_1 = io_lui_bit_17 & io_lui_bit_18; // @[Library.scala 314:48]
-  wire  _io_bltu_T_2 = _io_bltu_T_1 & io_jalr_bit_19; // @[Library.scala 311:48]
-  wire  _io_bltu_T_4 = _io_bltu_T_2 & io_inst[6] & io_lui_bit_26; // @[Library.scala 314:48]
-  wire  _io_bltu_T_7 = _io_bltu_T_4 & io_jal_bit_27 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 311:48]
-  wire  _io_bgeu_T_2 = io_lui_bit_17 & io_lui_bit_18 & io_lui_bit_19; // @[Library.scala 314:48]
-  wire  _io_bgeu_T_4 = io_lui_bit_17 & io_lui_bit_18 & io_lui_bit_19 & io_inst[6] & io_lui_bit_26; // @[Library.scala 314:48]
-  wire  _io_bgeu_T_7 = _io_bgeu_T_4 & io_jal_bit_27 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 311:48]
-  wire  _io_csrrw_T_4 = io_jalr_bit_18 & io_lui_bit_19 & io_inst[6] & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 314:48]
-  wire  _io_csrrw_T_6 = _io_csrrw_T_4 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 311:48]
-  wire  _io_csrrs_T_1 = io_lui_bit_18 & io_jalr_bit_19; // @[Library.scala 311:48]
-  wire  _io_csrrs_T_4 = _io_csrrs_T_1 & io_inst[6] & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 314:48]
-  wire  _io_csrrs_T_6 = _io_csrrs_T_4 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 311:48]
-  wire  _io_csrrc_T_4 = io_lui_bit_18 & io_lui_bit_19 & io_inst[6] & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 314:48]
-  wire  _io_csrrc_T_6 = _io_csrrc_T_4 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 311:48]
-  wire  _io_lb_T_3 = io_jalr_bit_17 & io_jalr_bit_18 & io_jalr_bit_19 & io_lui_bit_25; // @[Library.scala 311:48]
-  wire  _io_lb_T_4 = io_jalr_bit_17 & io_jalr_bit_18 & io_jalr_bit_19 & io_lui_bit_25 & io_auipc_bit_26; // @[Library.scala 311:48]
+  wire  io_lui_bit_1 = io_inst[30]; // @[Library.scala 318:23]
+  wire  io_lui_bit_2 = io_inst[29]; // @[Library.scala 318:23]
+  wire  io_lui_bit_3 = io_inst[28]; // @[Library.scala 318:23]
+  wire  io_lui_bit_4 = io_inst[27]; // @[Library.scala 318:23]
+  wire  io_lui_bit_5 = io_inst[26]; // @[Library.scala 318:23]
+  wire  io_lui_bit_6 = io_inst[25]; // @[Library.scala 318:23]
+  wire  io_lui_bit_7 = io_inst[24]; // @[Library.scala 318:23]
+  wire  io_lui_bit_8 = io_inst[23]; // @[Library.scala 318:23]
+  wire  io_lui_bit_9 = io_inst[22]; // @[Library.scala 318:23]
+  wire  io_lui_bit_10 = io_inst[21]; // @[Library.scala 318:23]
+  wire  io_lui_bit_12 = io_inst[19]; // @[Library.scala 318:23]
+  wire  io_lui_bit_13 = io_inst[18]; // @[Library.scala 318:23]
+  wire  io_lui_bit_14 = io_inst[17]; // @[Library.scala 318:23]
+  wire  io_lui_bit_15 = io_inst[16]; // @[Library.scala 318:23]
+  wire  io_lui_bit_16 = io_inst[15]; // @[Library.scala 318:23]
+  wire  io_lui_bit_17 = io_inst[14]; // @[Library.scala 318:23]
+  wire  io_lui_bit_18 = io_inst[13]; // @[Library.scala 318:23]
+  wire  io_lui_bit_19 = io_inst[12]; // @[Library.scala 318:23]
+  wire  io_lui_bit_20 = io_inst[11]; // @[Library.scala 318:23]
+  wire  io_lui_bit_21 = io_inst[10]; // @[Library.scala 318:23]
+  wire  io_lui_bit_22 = io_inst[9]; // @[Library.scala 318:23]
+  wire  io_lui_bit_23 = io_inst[8]; // @[Library.scala 318:23]
+  wire  io_lui_bit_25 = ~io_inst[6]; // @[Library.scala 312:19]
+  wire  io_lui_bit_26 = io_inst[5]; // @[Library.scala 315:23]
+  wire  io_lui_bit_27 = io_inst[4]; // @[Library.scala 315:23]
+  wire  _io_lui_T_2 = io_lui_bit_25 & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 316:48]
+  wire  io_lui_bit_28 = ~io_inst[3]; // @[Library.scala 312:19]
+  wire  _io_lui_T_3 = _io_lui_T_2 & io_lui_bit_28; // @[Library.scala 313:48]
+  wire  io_lui_bit_29 = io_inst[2]; // @[Library.scala 315:23]
+  wire  io_lui_bit_30 = io_inst[1]; // @[Library.scala 315:23]
+  wire  io_lui_bit_31 = io_inst[0]; // @[Library.scala 315:23]
+  wire  io_auipc_bit_26 = ~io_lui_bit_26; // @[Library.scala 312:19]
+  wire  _io_auipc_T_1 = io_lui_bit_25 & io_auipc_bit_26; // @[Library.scala 313:48]
+  wire  _io_auipc_T_2 = _io_auipc_T_1 & io_lui_bit_27; // @[Library.scala 316:48]
+  wire  _io_auipc_T_3 = _io_auipc_T_2 & io_lui_bit_28; // @[Library.scala 313:48]
+  wire  _io_jal_T_1 = io_inst[6] & io_lui_bit_26; // @[Library.scala 316:48]
+  wire  io_jal_bit_27 = ~io_lui_bit_27; // @[Library.scala 312:19]
+  wire  _io_jal_T_2 = _io_jal_T_1 & io_jal_bit_27; // @[Library.scala 313:48]
+  wire  io_jalr_bit_17 = ~io_lui_bit_17; // @[Library.scala 312:19]
+  wire  io_jalr_bit_18 = ~io_lui_bit_18; // @[Library.scala 312:19]
+  wire  _io_jalr_T_1 = io_jalr_bit_17 & io_jalr_bit_18; // @[Library.scala 313:48]
+  wire  io_jalr_bit_19 = ~io_lui_bit_19; // @[Library.scala 312:19]
+  wire  _io_jalr_T_2 = io_jalr_bit_17 & io_jalr_bit_18 & io_jalr_bit_19; // @[Library.scala 313:48]
+  wire  _io_jalr_T_4 = _io_jalr_T_2 & io_inst[6] & io_lui_bit_26; // @[Library.scala 316:48]
+  wire  _io_jalr_T_6 = _io_jalr_T_4 & io_jal_bit_27 & io_lui_bit_28; // @[Library.scala 313:48]
+  wire  io_beq_bit_29 = ~io_lui_bit_29; // @[Library.scala 312:19]
+  wire  _io_beq_T_7 = _io_jalr_T_4 & io_jal_bit_27 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 313:48]
+  wire  _io_bne_T_2 = _io_jalr_T_1 & io_lui_bit_19; // @[Library.scala 316:48]
+  wire  _io_bne_T_4 = _io_jalr_T_1 & io_lui_bit_19 & io_inst[6] & io_lui_bit_26; // @[Library.scala 316:48]
+  wire  _io_bne_T_7 = _io_bne_T_4 & io_jal_bit_27 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 313:48]
+  wire  _io_blt_T_1 = io_lui_bit_17 & io_jalr_bit_18; // @[Library.scala 313:48]
+  wire  _io_blt_T_2 = io_lui_bit_17 & io_jalr_bit_18 & io_jalr_bit_19; // @[Library.scala 313:48]
+  wire  _io_blt_T_4 = _io_blt_T_2 & io_inst[6] & io_lui_bit_26; // @[Library.scala 316:48]
+  wire  _io_blt_T_7 = _io_blt_T_4 & io_jal_bit_27 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 313:48]
+  wire  _io_bge_T_2 = _io_blt_T_1 & io_lui_bit_19; // @[Library.scala 316:48]
+  wire  _io_bge_T_4 = _io_blt_T_1 & io_lui_bit_19 & io_inst[6] & io_lui_bit_26; // @[Library.scala 316:48]
+  wire  _io_bge_T_7 = _io_bge_T_4 & io_jal_bit_27 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 313:48]
+  wire  _io_bltu_T_1 = io_lui_bit_17 & io_lui_bit_18; // @[Library.scala 316:48]
+  wire  _io_bltu_T_2 = _io_bltu_T_1 & io_jalr_bit_19; // @[Library.scala 313:48]
+  wire  _io_bltu_T_4 = _io_bltu_T_2 & io_inst[6] & io_lui_bit_26; // @[Library.scala 316:48]
+  wire  _io_bltu_T_7 = _io_bltu_T_4 & io_jal_bit_27 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 313:48]
+  wire  _io_bgeu_T_2 = io_lui_bit_17 & io_lui_bit_18 & io_lui_bit_19; // @[Library.scala 316:48]
+  wire  _io_bgeu_T_4 = io_lui_bit_17 & io_lui_bit_18 & io_lui_bit_19 & io_inst[6] & io_lui_bit_26; // @[Library.scala 316:48]
+  wire  _io_bgeu_T_7 = _io_bgeu_T_4 & io_jal_bit_27 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 313:48]
+  wire  _io_csrrw_T_4 = io_jalr_bit_18 & io_lui_bit_19 & io_inst[6] & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 316:48]
+  wire  _io_csrrw_T_6 = _io_csrrw_T_4 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 313:48]
+  wire  _io_csrrs_T_1 = io_lui_bit_18 & io_jalr_bit_19; // @[Library.scala 313:48]
+  wire  _io_csrrs_T_4 = _io_csrrs_T_1 & io_inst[6] & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 316:48]
+  wire  _io_csrrs_T_6 = _io_csrrs_T_4 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 313:48]
+  wire  _io_csrrc_T_4 = io_lui_bit_18 & io_lui_bit_19 & io_inst[6] & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 316:48]
+  wire  _io_csrrc_T_6 = _io_csrrc_T_4 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 313:48]
+  wire  _io_lb_T_3 = io_jalr_bit_17 & io_jalr_bit_18 & io_jalr_bit_19 & io_lui_bit_25; // @[Library.scala 313:48]
+  wire  _io_lb_T_4 = io_jalr_bit_17 & io_jalr_bit_18 & io_jalr_bit_19 & io_lui_bit_25 & io_auipc_bit_26; // @[Library.scala 313:48]
   wire  _io_lb_T_7 = io_jalr_bit_17 & io_jalr_bit_18 & io_jalr_bit_19 & io_lui_bit_25 & io_auipc_bit_26 & io_jal_bit_27
-     & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 311:48]
-  wire  _io_lh_T_3 = _io_bne_T_2 & io_lui_bit_25; // @[Library.scala 311:48]
-  wire  _io_lh_T_7 = _io_bne_T_2 & io_lui_bit_25 & io_auipc_bit_26 & io_jal_bit_27 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 311:48]
-  wire  _io_lw_T_1 = io_jalr_bit_17 & io_lui_bit_18; // @[Library.scala 314:48]
-  wire  _io_lw_T_3 = _io_lw_T_1 & io_jalr_bit_19 & io_lui_bit_25; // @[Library.scala 311:48]
-  wire  _io_lw_T_4 = _io_lw_T_1 & io_jalr_bit_19 & io_lui_bit_25 & io_auipc_bit_26; // @[Library.scala 311:48]
-  wire  _io_lw_T_6 = _io_lw_T_1 & io_jalr_bit_19 & io_lui_bit_25 & io_auipc_bit_26 & io_jal_bit_27 & io_lui_bit_28; // @[Library.scala 311:48]
+     & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 313:48]
+  wire  _io_lh_T_3 = _io_bne_T_2 & io_lui_bit_25; // @[Library.scala 313:48]
+  wire  _io_lh_T_7 = _io_bne_T_2 & io_lui_bit_25 & io_auipc_bit_26 & io_jal_bit_27 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 313:48]
+  wire  _io_lw_T_1 = io_jalr_bit_17 & io_lui_bit_18; // @[Library.scala 316:48]
+  wire  _io_lw_T_3 = _io_lw_T_1 & io_jalr_bit_19 & io_lui_bit_25; // @[Library.scala 313:48]
+  wire  _io_lw_T_4 = _io_lw_T_1 & io_jalr_bit_19 & io_lui_bit_25 & io_auipc_bit_26; // @[Library.scala 313:48]
   wire  _io_lw_T_7 = _io_lw_T_1 & io_jalr_bit_19 & io_lui_bit_25 & io_auipc_bit_26 & io_jal_bit_27 & io_lui_bit_28 &
-    io_beq_bit_29; // @[Library.scala 311:48]
-  wire  _io_lbu_T_4 = io_lui_bit_17 & io_jalr_bit_18 & io_jalr_bit_19 & io_lui_bit_25 & io_auipc_bit_26; // @[Library.scala 311:48]
+    io_beq_bit_29; // @[Library.scala 313:48]
+  wire  _io_lbu_T_4 = io_lui_bit_17 & io_jalr_bit_18 & io_jalr_bit_19 & io_lui_bit_25 & io_auipc_bit_26; // @[Library.scala 313:48]
   wire  _io_lbu_T_7 = io_lui_bit_17 & io_jalr_bit_18 & io_jalr_bit_19 & io_lui_bit_25 & io_auipc_bit_26 & io_jal_bit_27
-     & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 311:48]
-  wire  _io_lhu_T_7 = _io_bge_T_2 & io_lui_bit_25 & io_auipc_bit_26 & io_jal_bit_27 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 311:48]
-  wire  _io_sb_T_4 = _io_lb_T_3 & io_lui_bit_26; // @[Library.scala 314:48]
-  wire  _io_sb_T_7 = _io_sb_T_4 & io_jal_bit_27 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 311:48]
-  wire  _io_sh_T_4 = _io_lh_T_3 & io_lui_bit_26; // @[Library.scala 314:48]
-  wire  _io_sh_T_7 = _io_sh_T_4 & io_jal_bit_27 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 311:48]
-  wire  _io_sw_T_4 = _io_lw_T_3 & io_lui_bit_26; // @[Library.scala 314:48]
-  wire  _io_sw_T_6 = _io_sw_T_4 & io_jal_bit_27 & io_lui_bit_28; // @[Library.scala 311:48]
-  wire  _io_sw_T_7 = _io_sw_T_4 & io_jal_bit_27 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 311:48]
-  wire  io_fence_bit = ~io_inst[31]; // @[Library.scala 310:19]
-  wire  io_fence_bit_1 = ~io_lui_bit_1; // @[Library.scala 310:19]
-  wire  _io_fence_T_1 = io_fence_bit & io_fence_bit_1; // @[Library.scala 311:48]
-  wire  io_fence_bit_2 = ~io_lui_bit_2; // @[Library.scala 310:19]
-  wire  _io_fence_T_2 = io_fence_bit & io_fence_bit_1 & io_fence_bit_2; // @[Library.scala 311:48]
-  wire  io_fence_bit_3 = ~io_lui_bit_3; // @[Library.scala 310:19]
-  wire  _io_fence_T_3 = io_fence_bit & io_fence_bit_1 & io_fence_bit_2 & io_fence_bit_3; // @[Library.scala 311:48]
-  wire  io_fence_bit_12 = ~io_lui_bit_12; // @[Library.scala 310:19]
-  wire  io_fence_bit_13 = ~io_lui_bit_13; // @[Library.scala 310:19]
-  wire  io_fence_bit_14 = ~io_lui_bit_14; // @[Library.scala 310:19]
-  wire  io_fence_bit_15 = ~io_lui_bit_15; // @[Library.scala 310:19]
-  wire  io_fence_bit_16 = ~io_lui_bit_16; // @[Library.scala 310:19]
-  wire  io_fence_bit_20 = ~io_lui_bit_20; // @[Library.scala 310:19]
-  wire  io_fence_bit_21 = ~io_lui_bit_21; // @[Library.scala 310:19]
-  wire  io_fence_bit_22 = ~io_lui_bit_22; // @[Library.scala 310:19]
-  wire  io_fence_bit_23 = ~io_lui_bit_23; // @[Library.scala 310:19]
-  wire  io_fence_bit_24 = ~io_inst[7]; // @[Library.scala 310:19]
+     & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 313:48]
+  wire  _io_lhu_T_7 = _io_bge_T_2 & io_lui_bit_25 & io_auipc_bit_26 & io_jal_bit_27 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 313:48]
+  wire  _io_sb_T_4 = _io_lb_T_3 & io_lui_bit_26; // @[Library.scala 316:48]
+  wire  _io_sb_T_7 = _io_sb_T_4 & io_jal_bit_27 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 313:48]
+  wire  _io_sh_T_4 = _io_lh_T_3 & io_lui_bit_26; // @[Library.scala 316:48]
+  wire  _io_sh_T_7 = _io_sh_T_4 & io_jal_bit_27 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 313:48]
+  wire  _io_sw_T_4 = _io_lw_T_3 & io_lui_bit_26; // @[Library.scala 316:48]
+  wire  _io_sw_T_7 = _io_sw_T_4 & io_jal_bit_27 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 313:48]
+  wire  io_fence_bit = ~io_inst[31]; // @[Library.scala 312:19]
+  wire  io_fence_bit_1 = ~io_lui_bit_1; // @[Library.scala 312:19]
+  wire  _io_fence_T_1 = io_fence_bit & io_fence_bit_1; // @[Library.scala 313:48]
+  wire  io_fence_bit_2 = ~io_lui_bit_2; // @[Library.scala 312:19]
+  wire  _io_fence_T_2 = io_fence_bit & io_fence_bit_1 & io_fence_bit_2; // @[Library.scala 313:48]
+  wire  io_fence_bit_3 = ~io_lui_bit_3; // @[Library.scala 312:19]
+  wire  _io_fence_T_3 = io_fence_bit & io_fence_bit_1 & io_fence_bit_2 & io_fence_bit_3; // @[Library.scala 313:48]
+  wire  io_fence_bit_12 = ~io_lui_bit_12; // @[Library.scala 312:19]
+  wire  io_fence_bit_13 = ~io_lui_bit_13; // @[Library.scala 312:19]
+  wire  io_fence_bit_14 = ~io_lui_bit_14; // @[Library.scala 312:19]
+  wire  io_fence_bit_15 = ~io_lui_bit_15; // @[Library.scala 312:19]
+  wire  io_fence_bit_16 = ~io_lui_bit_16; // @[Library.scala 312:19]
+  wire  io_fence_bit_20 = ~io_lui_bit_20; // @[Library.scala 312:19]
+  wire  io_fence_bit_21 = ~io_lui_bit_21; // @[Library.scala 312:19]
+  wire  io_fence_bit_22 = ~io_lui_bit_22; // @[Library.scala 312:19]
+  wire  io_fence_bit_23 = ~io_lui_bit_23; // @[Library.scala 312:19]
+  wire  io_fence_bit_24 = ~io_inst[7]; // @[Library.scala 312:19]
   wire  _io_fence_T_19 = io_fence_bit & io_fence_bit_1 & io_fence_bit_2 & io_fence_bit_3 & io_fence_bit_12 &
     io_fence_bit_13 & io_fence_bit_14 & io_fence_bit_15 & io_fence_bit_16 & io_jalr_bit_17 & io_jalr_bit_18 &
     io_jalr_bit_19 & io_fence_bit_20 & io_fence_bit_21 & io_fence_bit_22 & io_fence_bit_23 & io_fence_bit_24 &
-    io_lui_bit_25 & io_auipc_bit_26 & io_jal_bit_27; // @[Library.scala 311:48]
-  wire  _io_addi_T_5 = _io_lb_T_4 & io_lui_bit_27; // @[Library.scala 314:48]
-  wire  _io_addi_T_7 = _io_addi_T_5 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 311:48]
-  wire  _io_slti_T_5 = _io_lw_T_4 & io_lui_bit_27; // @[Library.scala 314:48]
-  wire  _io_slti_T_7 = _io_slti_T_5 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 311:48]
-  wire  _io_sltiu_T_2 = io_jalr_bit_17 & io_lui_bit_18 & io_lui_bit_19; // @[Library.scala 314:48]
-  wire  _io_sltiu_T_4 = _io_sltiu_T_2 & io_lui_bit_25 & io_auipc_bit_26; // @[Library.scala 311:48]
-  wire  _io_sltiu_T_5 = _io_sltiu_T_4 & io_lui_bit_27; // @[Library.scala 314:48]
-  wire  _io_sltiu_T_7 = _io_sltiu_T_5 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 311:48]
-  wire  _io_xori_T_5 = _io_lbu_T_4 & io_lui_bit_27; // @[Library.scala 314:48]
-  wire  _io_xori_T_7 = _io_xori_T_5 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 311:48]
-  wire  _io_ori_T_4 = _io_bltu_T_1 & io_jalr_bit_19 & io_lui_bit_25 & io_auipc_bit_26; // @[Library.scala 311:48]
-  wire  _io_ori_T_5 = _io_ori_T_4 & io_lui_bit_27; // @[Library.scala 314:48]
-  wire  _io_ori_T_7 = _io_ori_T_5 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 311:48]
-  wire  _io_andi_T_4 = _io_bgeu_T_2 & io_lui_bit_25 & io_auipc_bit_26; // @[Library.scala 311:48]
-  wire  _io_andi_T_5 = _io_andi_T_4 & io_lui_bit_27; // @[Library.scala 314:48]
-  wire  _io_andi_T_7 = _io_andi_T_5 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 311:48]
-  wire  io_slli_bit_4 = ~io_lui_bit_4; // @[Library.scala 310:19]
-  wire  _io_slli_T_4 = io_fence_bit & io_fence_bit_1 & io_fence_bit_2 & io_fence_bit_3 & io_slli_bit_4; // @[Library.scala 311:48]
-  wire  io_slli_bit_5 = ~io_lui_bit_5; // @[Library.scala 310:19]
-  wire  _io_slli_T_5 = io_fence_bit & io_fence_bit_1 & io_fence_bit_2 & io_fence_bit_3 & io_slli_bit_4 & io_slli_bit_5; // @[Library.scala 311:48]
-  wire  io_slli_bit_6 = ~io_lui_bit_6; // @[Library.scala 310:19]
+    io_lui_bit_25 & io_auipc_bit_26 & io_jal_bit_27; // @[Library.scala 313:48]
+  wire  _io_addi_T_5 = _io_lb_T_4 & io_lui_bit_27; // @[Library.scala 316:48]
+  wire  _io_addi_T_7 = _io_addi_T_5 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 313:48]
+  wire  _io_slti_T_5 = _io_lw_T_4 & io_lui_bit_27; // @[Library.scala 316:48]
+  wire  _io_slti_T_7 = _io_slti_T_5 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 313:48]
+  wire  _io_sltiu_T_2 = io_jalr_bit_17 & io_lui_bit_18 & io_lui_bit_19; // @[Library.scala 316:48]
+  wire  _io_sltiu_T_4 = _io_sltiu_T_2 & io_lui_bit_25 & io_auipc_bit_26; // @[Library.scala 313:48]
+  wire  _io_sltiu_T_5 = _io_sltiu_T_4 & io_lui_bit_27; // @[Library.scala 316:48]
+  wire  _io_sltiu_T_7 = _io_sltiu_T_5 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 313:48]
+  wire  _io_xori_T_5 = _io_lbu_T_4 & io_lui_bit_27; // @[Library.scala 316:48]
+  wire  _io_xori_T_7 = _io_xori_T_5 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 313:48]
+  wire  _io_ori_T_4 = _io_bltu_T_1 & io_jalr_bit_19 & io_lui_bit_25 & io_auipc_bit_26; // @[Library.scala 313:48]
+  wire  _io_ori_T_5 = _io_ori_T_4 & io_lui_bit_27; // @[Library.scala 316:48]
+  wire  _io_ori_T_7 = _io_ori_T_5 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 313:48]
+  wire  _io_andi_T_4 = _io_bgeu_T_2 & io_lui_bit_25 & io_auipc_bit_26; // @[Library.scala 313:48]
+  wire  _io_andi_T_5 = _io_andi_T_4 & io_lui_bit_27; // @[Library.scala 316:48]
+  wire  _io_andi_T_7 = _io_andi_T_5 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 313:48]
+  wire  io_slli_bit_4 = ~io_lui_bit_4; // @[Library.scala 312:19]
+  wire  _io_slli_T_4 = io_fence_bit & io_fence_bit_1 & io_fence_bit_2 & io_fence_bit_3 & io_slli_bit_4; // @[Library.scala 313:48]
+  wire  io_slli_bit_5 = ~io_lui_bit_5; // @[Library.scala 312:19]
+  wire  _io_slli_T_5 = io_fence_bit & io_fence_bit_1 & io_fence_bit_2 & io_fence_bit_3 & io_slli_bit_4 & io_slli_bit_5; // @[Library.scala 313:48]
+  wire  io_slli_bit_6 = ~io_lui_bit_6; // @[Library.scala 312:19]
   wire  _io_slli_T_6 = io_fence_bit & io_fence_bit_1 & io_fence_bit_2 & io_fence_bit_3 & io_slli_bit_4 & io_slli_bit_5
-     & io_slli_bit_6; // @[Library.scala 311:48]
+     & io_slli_bit_6; // @[Library.scala 313:48]
   wire  _io_slli_T_7 = io_fence_bit & io_fence_bit_1 & io_fence_bit_2 & io_fence_bit_3 & io_slli_bit_4 & io_slli_bit_5
-     & io_slli_bit_6 & io_jalr_bit_17; // @[Library.scala 311:48]
+     & io_slli_bit_6 & io_jalr_bit_17; // @[Library.scala 313:48]
   wire  _io_slli_T_8 = io_fence_bit & io_fence_bit_1 & io_fence_bit_2 & io_fence_bit_3 & io_slli_bit_4 & io_slli_bit_5
-     & io_slli_bit_6 & io_jalr_bit_17 & io_jalr_bit_18; // @[Library.scala 311:48]
-  wire  _io_slli_T_9 = _io_slli_T_8 & io_lui_bit_19; // @[Library.scala 314:48]
-  wire  _io_slli_T_10 = _io_slli_T_9 & io_lui_bit_25; // @[Library.scala 311:48]
-  wire  _io_slli_T_11 = _io_slli_T_9 & io_lui_bit_25 & io_auipc_bit_26; // @[Library.scala 311:48]
-  wire  _io_slli_T_12 = _io_slli_T_11 & io_lui_bit_27; // @[Library.scala 314:48]
-  wire  _io_slli_T_14 = _io_slli_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 311:48]
-  wire  _io_srli_T_7 = _io_slli_T_6 & io_lui_bit_17; // @[Library.scala 314:48]
-  wire  _io_srli_T_8 = _io_srli_T_7 & io_jalr_bit_18; // @[Library.scala 311:48]
-  wire  _io_srli_T_9 = _io_srli_T_8 & io_lui_bit_19; // @[Library.scala 314:48]
-  wire  _io_srli_T_10 = _io_srli_T_9 & io_lui_bit_25; // @[Library.scala 311:48]
-  wire  _io_srli_T_11 = _io_srli_T_9 & io_lui_bit_25 & io_auipc_bit_26; // @[Library.scala 311:48]
-  wire  _io_srli_T_12 = _io_srli_T_11 & io_lui_bit_27; // @[Library.scala 314:48]
-  wire  _io_srli_T_14 = _io_srli_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 311:48]
-  wire  _io_srai_T_1 = io_fence_bit & io_lui_bit_1; // @[Library.scala 314:48]
-  wire  _io_srai_T_2 = _io_srai_T_1 & io_fence_bit_2; // @[Library.scala 311:48]
-  wire  _io_srai_T_6 = _io_srai_T_1 & io_fence_bit_2 & io_fence_bit_3 & io_slli_bit_4 & io_slli_bit_5 & io_slli_bit_6; // @[Library.scala 311:48]
-  wire  _io_srai_T_7 = _io_srai_T_6 & io_lui_bit_17; // @[Library.scala 314:48]
-  wire  _io_srai_T_8 = _io_srai_T_7 & io_jalr_bit_18; // @[Library.scala 311:48]
-  wire  _io_srai_T_9 = _io_srai_T_8 & io_lui_bit_19; // @[Library.scala 314:48]
-  wire  _io_srai_T_10 = _io_srai_T_9 & io_lui_bit_25; // @[Library.scala 311:48]
-  wire  _io_srai_T_11 = _io_srai_T_9 & io_lui_bit_25 & io_auipc_bit_26; // @[Library.scala 311:48]
-  wire  _io_srai_T_12 = _io_srai_T_11 & io_lui_bit_27; // @[Library.scala 314:48]
-  wire  _io_srai_T_14 = _io_srai_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 311:48]
+     & io_slli_bit_6 & io_jalr_bit_17 & io_jalr_bit_18; // @[Library.scala 313:48]
+  wire  _io_slli_T_9 = _io_slli_T_8 & io_lui_bit_19; // @[Library.scala 316:48]
+  wire  _io_slli_T_10 = _io_slli_T_9 & io_lui_bit_25; // @[Library.scala 313:48]
+  wire  _io_slli_T_11 = _io_slli_T_9 & io_lui_bit_25 & io_auipc_bit_26; // @[Library.scala 313:48]
+  wire  _io_slli_T_12 = _io_slli_T_11 & io_lui_bit_27; // @[Library.scala 316:48]
+  wire  _io_slli_T_14 = _io_slli_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 313:48]
+  wire  _io_srli_T_7 = _io_slli_T_6 & io_lui_bit_17; // @[Library.scala 316:48]
+  wire  _io_srli_T_8 = _io_srli_T_7 & io_jalr_bit_18; // @[Library.scala 313:48]
+  wire  _io_srli_T_9 = _io_srli_T_8 & io_lui_bit_19; // @[Library.scala 316:48]
+  wire  _io_srli_T_10 = _io_srli_T_9 & io_lui_bit_25; // @[Library.scala 313:48]
+  wire  _io_srli_T_11 = _io_srli_T_9 & io_lui_bit_25 & io_auipc_bit_26; // @[Library.scala 313:48]
+  wire  _io_srli_T_12 = _io_srli_T_11 & io_lui_bit_27; // @[Library.scala 316:48]
+  wire  _io_srli_T_14 = _io_srli_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 313:48]
+  wire  _io_srai_T_1 = io_fence_bit & io_lui_bit_1; // @[Library.scala 316:48]
+  wire  _io_srai_T_2 = _io_srai_T_1 & io_fence_bit_2; // @[Library.scala 313:48]
+  wire  _io_srai_T_6 = _io_srai_T_1 & io_fence_bit_2 & io_fence_bit_3 & io_slli_bit_4 & io_slli_bit_5 & io_slli_bit_6; // @[Library.scala 313:48]
+  wire  _io_srai_T_7 = _io_srai_T_6 & io_lui_bit_17; // @[Library.scala 316:48]
+  wire  _io_srai_T_8 = _io_srai_T_7 & io_jalr_bit_18; // @[Library.scala 313:48]
+  wire  _io_srai_T_9 = _io_srai_T_8 & io_lui_bit_19; // @[Library.scala 316:48]
+  wire  _io_srai_T_10 = _io_srai_T_9 & io_lui_bit_25; // @[Library.scala 313:48]
+  wire  _io_srai_T_11 = _io_srai_T_9 & io_lui_bit_25 & io_auipc_bit_26; // @[Library.scala 313:48]
+  wire  _io_srai_T_12 = _io_srai_T_11 & io_lui_bit_27; // @[Library.scala 316:48]
+  wire  _io_srai_T_14 = _io_srai_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 313:48]
   wire  _io_add_T_10 = io_fence_bit & io_fence_bit_1 & io_fence_bit_2 & io_fence_bit_3 & io_slli_bit_4 & io_slli_bit_5
-     & io_slli_bit_6 & io_jalr_bit_17 & io_jalr_bit_18 & io_jalr_bit_19 & io_lui_bit_25; // @[Library.scala 311:48]
-  wire  _io_add_T_12 = _io_add_T_10 & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 314:48]
-  wire  _io_add_T_14 = _io_add_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 311:48]
+     & io_slli_bit_6 & io_jalr_bit_17 & io_jalr_bit_18 & io_jalr_bit_19 & io_lui_bit_25; // @[Library.scala 313:48]
+  wire  _io_add_T_12 = _io_add_T_10 & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 316:48]
+  wire  _io_add_T_14 = _io_add_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 313:48]
   wire  _io_sub_T_10 = _io_srai_T_1 & io_fence_bit_2 & io_fence_bit_3 & io_slli_bit_4 & io_slli_bit_5 & io_slli_bit_6 &
-    io_jalr_bit_17 & io_jalr_bit_18 & io_jalr_bit_19 & io_lui_bit_25; // @[Library.scala 311:48]
-  wire  _io_sub_T_12 = _io_sub_T_10 & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 314:48]
-  wire  _io_sub_T_14 = _io_sub_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 311:48]
-  wire  _io_slt_T_8 = _io_slli_T_7 & io_lui_bit_18; // @[Library.scala 314:48]
-  wire  _io_slt_T_10 = _io_slt_T_8 & io_jalr_bit_19 & io_lui_bit_25; // @[Library.scala 311:48]
-  wire  _io_slt_T_12 = _io_slt_T_10 & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 314:48]
-  wire  _io_slt_T_14 = _io_slt_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 311:48]
-  wire  _io_sltu_T_9 = _io_slli_T_7 & io_lui_bit_18 & io_lui_bit_19; // @[Library.scala 314:48]
-  wire  _io_sltu_T_10 = _io_sltu_T_9 & io_lui_bit_25; // @[Library.scala 311:48]
-  wire  _io_sltu_T_12 = _io_sltu_T_10 & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 314:48]
-  wire  _io_sltu_T_14 = _io_sltu_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 311:48]
-  wire  _io_xor_T_10 = _io_srli_T_7 & io_jalr_bit_18 & io_jalr_bit_19 & io_lui_bit_25; // @[Library.scala 311:48]
-  wire  _io_xor_T_12 = _io_xor_T_10 & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 314:48]
-  wire  _io_xor_T_14 = _io_xor_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 311:48]
-  wire  _io_or_T_8 = _io_slli_T_6 & io_lui_bit_17 & io_lui_bit_18; // @[Library.scala 314:48]
-  wire  _io_or_T_10 = _io_or_T_8 & io_jalr_bit_19 & io_lui_bit_25; // @[Library.scala 311:48]
-  wire  _io_or_T_12 = _io_or_T_10 & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 314:48]
-  wire  _io_or_T_14 = _io_or_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 311:48]
-  wire  _io_and_T_9 = _io_slli_T_6 & io_lui_bit_17 & io_lui_bit_18 & io_lui_bit_19; // @[Library.scala 314:48]
-  wire  _io_and_T_10 = _io_and_T_9 & io_lui_bit_25; // @[Library.scala 311:48]
-  wire  _io_and_T_12 = _io_and_T_10 & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 314:48]
-  wire  _io_and_T_14 = _io_and_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 311:48]
-  wire  _io_sll_T_12 = _io_slli_T_10 & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 314:48]
-  wire  _io_sll_T_14 = _io_sll_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 311:48]
-  wire  _io_srl_T_12 = _io_srli_T_10 & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 314:48]
-  wire  _io_srl_T_14 = _io_srl_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 311:48]
-  wire  _io_sra_T_12 = _io_srai_T_10 & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 314:48]
-  wire  _io_sra_T_14 = _io_sra_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 311:48]
-  wire  _io_mul_T_6 = _io_slli_T_5 & io_lui_bit_6; // @[Library.scala 314:48]
-  wire  _io_mul_T_7 = _io_mul_T_6 & io_jalr_bit_17; // @[Library.scala 311:48]
-  wire  _io_mul_T_8 = _io_mul_T_6 & io_jalr_bit_17 & io_jalr_bit_18; // @[Library.scala 311:48]
-  wire  _io_mul_T_10 = _io_mul_T_6 & io_jalr_bit_17 & io_jalr_bit_18 & io_jalr_bit_19 & io_lui_bit_25; // @[Library.scala 311:48]
-  wire  _io_mul_T_12 = _io_mul_T_10 & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 314:48]
-  wire  _io_mul_T_14 = _io_mul_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 311:48]
-  wire  _io_mulh_T_9 = _io_mul_T_8 & io_lui_bit_19; // @[Library.scala 314:48]
-  wire  _io_mulh_T_10 = _io_mulh_T_9 & io_lui_bit_25; // @[Library.scala 311:48]
-  wire  _io_mulh_T_12 = _io_mulh_T_10 & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 314:48]
-  wire  _io_mulh_T_14 = _io_mulh_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 311:48]
-  wire  _io_mulhsu_T_8 = _io_mul_T_7 & io_lui_bit_18; // @[Library.scala 314:48]
-  wire  _io_mulhsu_T_10 = _io_mulhsu_T_8 & io_jalr_bit_19 & io_lui_bit_25; // @[Library.scala 311:48]
-  wire  _io_mulhsu_T_12 = _io_mulhsu_T_10 & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 314:48]
-  wire  _io_mulhsu_T_14 = _io_mulhsu_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 311:48]
-  wire  _io_mulhu_T_9 = _io_mul_T_7 & io_lui_bit_18 & io_lui_bit_19; // @[Library.scala 314:48]
-  wire  _io_mulhu_T_10 = _io_mulhu_T_9 & io_lui_bit_25; // @[Library.scala 311:48]
-  wire  _io_mulhu_T_12 = _io_mulhu_T_10 & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 314:48]
-  wire  _io_mulhu_T_14 = _io_mulhu_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 311:48]
-  wire  _io_mulhr_T_2 = _io_fence_T_1 & io_lui_bit_2; // @[Library.scala 314:48]
-  wire  _io_mulhr_T_3 = _io_mulhr_T_2 & io_fence_bit_3; // @[Library.scala 311:48]
-  wire  _io_mulhr_T_4 = _io_mulhr_T_2 & io_fence_bit_3 & io_slli_bit_4; // @[Library.scala 311:48]
-  wire  _io_mulhr_T_5 = _io_mulhr_T_2 & io_fence_bit_3 & io_slli_bit_4 & io_slli_bit_5; // @[Library.scala 311:48]
-  wire  _io_mulhr_T_6 = _io_mulhr_T_5 & io_lui_bit_6; // @[Library.scala 314:48]
-  wire  _io_mulhr_T_7 = _io_mulhr_T_6 & io_jalr_bit_17; // @[Library.scala 311:48]
-  wire  _io_mulhr_T_8 = _io_mulhr_T_6 & io_jalr_bit_17 & io_jalr_bit_18; // @[Library.scala 311:48]
-  wire  _io_mulhr_T_9 = _io_mulhr_T_8 & io_lui_bit_19; // @[Library.scala 314:48]
-  wire  _io_mulhr_T_10 = _io_mulhr_T_9 & io_lui_bit_25; // @[Library.scala 311:48]
-  wire  _io_mulhr_T_12 = _io_mulhr_T_10 & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 314:48]
-  wire  _io_mulhr_T_14 = _io_mulhr_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 311:48]
-  wire  _io_mulhsur_T_8 = _io_mulhr_T_7 & io_lui_bit_18; // @[Library.scala 314:48]
-  wire  _io_mulhsur_T_10 = _io_mulhsur_T_8 & io_jalr_bit_19 & io_lui_bit_25; // @[Library.scala 311:48]
-  wire  _io_mulhsur_T_12 = _io_mulhsur_T_10 & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 314:48]
-  wire  _io_mulhsur_T_14 = _io_mulhsur_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 311:48]
-  wire  _io_mulhur_T_9 = _io_mulhr_T_7 & io_lui_bit_18 & io_lui_bit_19; // @[Library.scala 314:48]
-  wire  _io_mulhur_T_10 = _io_mulhur_T_9 & io_lui_bit_25; // @[Library.scala 311:48]
-  wire  _io_mulhur_T_12 = _io_mulhur_T_10 & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 314:48]
-  wire  _io_mulhur_T_14 = _io_mulhur_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 311:48]
-  wire  _io_dmulh_T_5 = _io_slli_T_4 & io_lui_bit_5; // @[Library.scala 314:48]
-  wire  _io_dmulh_T_8 = _io_dmulh_T_5 & io_slli_bit_6 & io_jalr_bit_17 & io_jalr_bit_18; // @[Library.scala 311:48]
-  wire  _io_dmulh_T_9 = _io_dmulh_T_8 & io_lui_bit_19; // @[Library.scala 314:48]
-  wire  _io_dmulh_T_10 = _io_dmulh_T_9 & io_lui_bit_25; // @[Library.scala 311:48]
-  wire  _io_dmulh_T_12 = _io_dmulh_T_10 & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 314:48]
-  wire  _io_dmulh_T_14 = _io_dmulh_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 311:48]
-  wire  _io_dmulhr_T_5 = _io_mulhr_T_4 & io_lui_bit_5; // @[Library.scala 314:48]
-  wire  _io_dmulhr_T_8 = _io_dmulhr_T_5 & io_slli_bit_6 & io_jalr_bit_17 & io_jalr_bit_18; // @[Library.scala 311:48]
-  wire  _io_dmulhr_T_9 = _io_dmulhr_T_8 & io_lui_bit_19; // @[Library.scala 314:48]
-  wire  _io_dmulhr_T_10 = _io_dmulhr_T_9 & io_lui_bit_25; // @[Library.scala 311:48]
-  wire  _io_dmulhr_T_12 = _io_dmulhr_T_10 & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 314:48]
-  wire  _io_dmulhr_T_14 = _io_dmulhr_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 311:48]
-  wire  _io_div_T_7 = _io_slli_T_5 & io_lui_bit_6 & io_lui_bit_17; // @[Library.scala 314:48]
-  wire  _io_div_T_8 = _io_div_T_7 & io_jalr_bit_18; // @[Library.scala 311:48]
-  wire  _io_div_T_10 = _io_div_T_7 & io_jalr_bit_18 & io_jalr_bit_19 & io_lui_bit_25; // @[Library.scala 311:48]
-  wire  _io_div_T_12 = _io_div_T_10 & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 314:48]
-  wire  _io_div_T_14 = _io_div_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 311:48]
-  wire  _io_divu_T_9 = _io_div_T_8 & io_lui_bit_19; // @[Library.scala 314:48]
-  wire  _io_divu_T_10 = _io_divu_T_9 & io_lui_bit_25; // @[Library.scala 311:48]
-  wire  _io_divu_T_12 = _io_divu_T_10 & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 314:48]
-  wire  _io_divu_T_14 = _io_divu_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 311:48]
-  wire  _io_rem_T_8 = _io_slli_T_5 & io_lui_bit_6 & io_lui_bit_17 & io_lui_bit_18; // @[Library.scala 314:48]
-  wire  _io_rem_T_10 = _io_rem_T_8 & io_jalr_bit_19 & io_lui_bit_25; // @[Library.scala 311:48]
-  wire  _io_rem_T_12 = _io_rem_T_10 & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 314:48]
-  wire  _io_rem_T_14 = _io_rem_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 311:48]
-  wire  _io_remu_T_9 = _io_slli_T_5 & io_lui_bit_6 & io_lui_bit_17 & io_lui_bit_18 & io_lui_bit_19; // @[Library.scala 314:48]
-  wire  _io_remu_T_10 = _io_remu_T_9 & io_lui_bit_25; // @[Library.scala 311:48]
-  wire  _io_remu_T_12 = _io_remu_T_10 & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 314:48]
-  wire  _io_remu_T_14 = _io_remu_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 311:48]
-  wire  _io_fmadd_T_1 = io_slli_bit_5 & io_slli_bit_6; // @[Library.scala 311:48]
-  wire  _io_fmadd_T_2 = _io_fmadd_T_1 & io_inst[6]; // @[Library.scala 314:48]
-  wire  _io_fmadd_T_4 = _io_fmadd_T_2 & io_auipc_bit_26 & io_jal_bit_27; // @[Library.scala 311:48]
-  wire  _io_fmadd_T_5 = _io_fmadd_T_2 & io_auipc_bit_26 & io_jal_bit_27 & io_lui_bit_28; // @[Library.scala 311:48]
-  wire  _io_fmadd_T_6 = _io_fmadd_T_2 & io_auipc_bit_26 & io_jal_bit_27 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 311:48]
-  wire  _io_fnmsub_T_5 = _io_fmadd_T_4 & io_inst[3]; // @[Library.scala 314:48]
-  wire  _io_fnmsub_T_6 = _io_fnmsub_T_5 & io_beq_bit_29; // @[Library.scala 311:48]
-  wire  _io_fadd_T_7 = _io_slli_T_6 & io_inst[6]; // @[Library.scala 314:48]
-  wire  _io_fadd_T_8 = _io_fadd_T_7 & io_auipc_bit_26; // @[Library.scala 311:48]
-  wire  _io_fadd_T_9 = _io_fadd_T_8 & io_lui_bit_27; // @[Library.scala 314:48]
-  wire  _io_fadd_T_11 = _io_fadd_T_9 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 311:48]
-  wire  _io_fsub_T_4 = _io_fence_T_3 & io_lui_bit_4; // @[Library.scala 314:48]
-  wire  _io_fsub_T_5 = _io_fsub_T_4 & io_slli_bit_5; // @[Library.scala 311:48]
-  wire  _io_fsub_T_6 = _io_fsub_T_4 & io_slli_bit_5 & io_slli_bit_6; // @[Library.scala 311:48]
-  wire  _io_fsub_T_7 = _io_fsub_T_6 & io_inst[6]; // @[Library.scala 314:48]
-  wire  _io_fsub_T_8 = _io_fsub_T_7 & io_auipc_bit_26; // @[Library.scala 311:48]
-  wire  _io_fsub_T_9 = _io_fsub_T_8 & io_lui_bit_27; // @[Library.scala 314:48]
-  wire  _io_fsub_T_11 = _io_fsub_T_9 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 311:48]
-  wire  _io_fmul_T_3 = _io_fence_T_2 & io_lui_bit_3; // @[Library.scala 314:48]
-  wire  _io_fmul_T_6 = _io_fmul_T_3 & io_slli_bit_4 & io_slli_bit_5 & io_slli_bit_6; // @[Library.scala 311:48]
-  wire  _io_fmul_T_7 = _io_fmul_T_6 & io_inst[6]; // @[Library.scala 314:48]
-  wire  _io_fmul_T_8 = _io_fmul_T_7 & io_auipc_bit_26; // @[Library.scala 311:48]
-  wire  _io_fmul_T_9 = _io_fmul_T_8 & io_lui_bit_27; // @[Library.scala 314:48]
-  wire  _io_fmul_T_11 = _io_fmul_T_9 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 311:48]
-  wire  _io_fdiv_T_4 = _io_fence_T_2 & io_lui_bit_3 & io_lui_bit_4; // @[Library.scala 314:48]
-  wire  _io_fdiv_T_6 = _io_fdiv_T_4 & io_slli_bit_5 & io_slli_bit_6; // @[Library.scala 311:48]
-  wire  _io_fdiv_T_7 = _io_fdiv_T_6 & io_inst[6]; // @[Library.scala 314:48]
-  wire  _io_fdiv_T_8 = _io_fdiv_T_7 & io_auipc_bit_26; // @[Library.scala 311:48]
-  wire  _io_fdiv_T_9 = _io_fdiv_T_8 & io_lui_bit_27; // @[Library.scala 314:48]
-  wire  _io_fdiv_T_11 = _io_fdiv_T_9 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 311:48]
-  wire  _io_fsqrt_T_3 = _io_srai_T_2 & io_lui_bit_3; // @[Library.scala 314:48]
-  wire  _io_fsqrt_T_4 = _io_srai_T_2 & io_lui_bit_3 & io_lui_bit_4; // @[Library.scala 314:48]
-  wire  _io_fsqrt_T_6 = _io_fsqrt_T_4 & io_slli_bit_5 & io_slli_bit_6; // @[Library.scala 311:48]
-  wire  _io_fsqrt_T_7 = _io_fsqrt_T_6 & io_inst[6]; // @[Library.scala 314:48]
-  wire  _io_fsqrt_T_8 = _io_fsqrt_T_7 & io_auipc_bit_26; // @[Library.scala 311:48]
-  wire  _io_fsqrt_T_9 = _io_fsqrt_T_8 & io_lui_bit_27; // @[Library.scala 314:48]
-  wire  _io_fsqrt_T_11 = _io_fsqrt_T_9 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 311:48]
-  wire  _io_fsgnj_T_7 = _io_mulhr_T_2 & io_fence_bit_3 & io_slli_bit_4 & io_slli_bit_5 & io_slli_bit_6 & io_jalr_bit_17; // @[Library.scala 311:48]
-  wire  _io_fsgnj_T_8 = _io_mulhr_T_2 & io_fence_bit_3 & io_slli_bit_4 & io_slli_bit_5 & io_slli_bit_6 & io_jalr_bit_17
-     & io_jalr_bit_18; // @[Library.scala 311:48]
-  wire  _io_fsgnj_T_9 = _io_mulhr_T_2 & io_fence_bit_3 & io_slli_bit_4 & io_slli_bit_5 & io_slli_bit_6 & io_jalr_bit_17
-     & io_jalr_bit_18 & io_jalr_bit_19; // @[Library.scala 311:48]
-  wire  _io_fsgnj_T_10 = _io_fsgnj_T_9 & io_inst[6]; // @[Library.scala 314:48]
-  wire  _io_fsgnj_T_11 = _io_fsgnj_T_10 & io_auipc_bit_26; // @[Library.scala 311:48]
-  wire  _io_fsgnj_T_12 = _io_fsgnj_T_11 & io_lui_bit_27; // @[Library.scala 314:48]
-  wire  _io_fsgnj_T_14 = _io_fsgnj_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 311:48]
-  wire  _io_fsgnjn_T_10 = _io_fsgnj_T_8 & io_lui_bit_19 & io_inst[6]; // @[Library.scala 314:48]
-  wire  _io_fsgnjn_T_11 = _io_fsgnjn_T_10 & io_auipc_bit_26; // @[Library.scala 311:48]
-  wire  _io_fsgnjn_T_12 = _io_fsgnjn_T_11 & io_lui_bit_27; // @[Library.scala 314:48]
-  wire  _io_fsgnjn_T_14 = _io_fsgnjn_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 311:48]
-  wire  _io_fsgnjx_T_8 = _io_fsgnj_T_7 & io_lui_bit_18; // @[Library.scala 314:48]
-  wire  _io_fsgnjx_T_9 = _io_fsgnjx_T_8 & io_jalr_bit_19; // @[Library.scala 311:48]
-  wire  _io_fsgnjx_T_10 = _io_fsgnjx_T_9 & io_inst[6]; // @[Library.scala 314:48]
-  wire  _io_fsgnjx_T_11 = _io_fsgnjx_T_10 & io_auipc_bit_26; // @[Library.scala 311:48]
-  wire  _io_fsgnjx_T_12 = _io_fsgnjx_T_11 & io_lui_bit_27; // @[Library.scala 314:48]
-  wire  _io_fsgnjx_T_14 = _io_fsgnjx_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 311:48]
-  wire  _io_fmin_T_4 = _io_mulhr_T_3 & io_lui_bit_4; // @[Library.scala 314:48]
-  wire  _io_fmin_T_8 = _io_fmin_T_4 & io_slli_bit_5 & io_slli_bit_6 & io_jalr_bit_17 & io_jalr_bit_18; // @[Library.scala 311:48]
-  wire  _io_fmin_T_9 = _io_fmin_T_4 & io_slli_bit_5 & io_slli_bit_6 & io_jalr_bit_17 & io_jalr_bit_18 & io_jalr_bit_19; // @[Library.scala 311:48]
-  wire  _io_fmin_T_10 = _io_fmin_T_9 & io_inst[6]; // @[Library.scala 314:48]
-  wire  _io_fmin_T_11 = _io_fmin_T_10 & io_auipc_bit_26; // @[Library.scala 311:48]
-  wire  _io_fmin_T_12 = _io_fmin_T_11 & io_lui_bit_27; // @[Library.scala 314:48]
-  wire  _io_fmin_T_14 = _io_fmin_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 311:48]
-  wire  _io_fmax_T_10 = _io_fmin_T_8 & io_lui_bit_19 & io_inst[6]; // @[Library.scala 314:48]
-  wire  _io_fmax_T_11 = _io_fmax_T_10 & io_auipc_bit_26; // @[Library.scala 311:48]
-  wire  _io_fmax_T_12 = _io_fmax_T_11 & io_lui_bit_27; // @[Library.scala 314:48]
-  wire  _io_fmax_T_14 = _io_fmax_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 311:48]
-  wire  _io_fcvtws_T_1 = io_inst[31] & io_lui_bit_1; // @[Library.scala 314:48]
-  wire  _io_fcvtws_T_2 = _io_fcvtws_T_1 & io_fence_bit_2; // @[Library.scala 311:48]
-  wire  io_fcvtws_bit_7 = ~io_lui_bit_7; // @[Library.scala 310:19]
-  wire  io_fcvtws_bit_8 = ~io_lui_bit_8; // @[Library.scala 310:19]
-  wire  io_fcvtws_bit_9 = ~io_lui_bit_9; // @[Library.scala 310:19]
-  wire  io_fcvtws_bit_10 = ~io_lui_bit_10; // @[Library.scala 310:19]
-  wire  _io_fcvtws_T_10 = _io_fcvtws_T_1 & io_fence_bit_2 & io_fence_bit_3 & io_slli_bit_4 & io_slli_bit_5 &
-    io_slli_bit_6 & io_fcvtws_bit_7 & io_fcvtws_bit_8 & io_fcvtws_bit_9 & io_fcvtws_bit_10; // @[Library.scala 311:48]
-  wire  io_fcvtws_bit_11 = ~io_inst[20]; // @[Library.scala 310:19]
-  wire  _io_fcvtws_T_11 = _io_fcvtws_T_1 & io_fence_bit_2 & io_fence_bit_3 & io_slli_bit_4 & io_slli_bit_5 &
-    io_slli_bit_6 & io_fcvtws_bit_7 & io_fcvtws_bit_8 & io_fcvtws_bit_9 & io_fcvtws_bit_10 & io_fcvtws_bit_11; // @[Library.scala 311:48]
-  wire  _io_fcvtws_T_12 = _io_fcvtws_T_11 & io_inst[6]; // @[Library.scala 314:48]
-  wire  _io_fcvtws_T_13 = _io_fcvtws_T_12 & io_auipc_bit_26; // @[Library.scala 311:48]
-  wire  _io_fcvtws_T_14 = _io_fcvtws_T_13 & io_lui_bit_27; // @[Library.scala 314:48]
-  wire  _io_fcvtws_T_16 = _io_fcvtws_T_14 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 311:48]
-  wire  _io_fcvtwus_T_12 = _io_fcvtws_T_10 & io_inst[20] & io_inst[6]; // @[Library.scala 314:48]
-  wire  _io_fcvtwus_T_13 = _io_fcvtwus_T_12 & io_auipc_bit_26; // @[Library.scala 311:48]
-  wire  _io_fcvtwus_T_14 = _io_fcvtwus_T_13 & io_lui_bit_27; // @[Library.scala 314:48]
-  wire  _io_fcvtwus_T_16 = _io_fcvtwus_T_14 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 311:48]
-  wire  _io_fmvxw_T_2 = io_inst[31] & io_lui_bit_1 & io_lui_bit_2; // @[Library.scala 314:48]
-  wire  _io_fmvxw_T_13 = _io_fmvxw_T_2 & io_fence_bit_3 & io_slli_bit_4 & io_slli_bit_5 & io_slli_bit_6 &
-    io_fcvtws_bit_7 & io_fcvtws_bit_8 & io_fcvtws_bit_9 & io_fcvtws_bit_10 & io_fcvtws_bit_11 & io_jalr_bit_17 &
-    io_jalr_bit_18; // @[Library.scala 311:48]
-  wire  _io_fmvxw_T_14 = _io_fmvxw_T_2 & io_fence_bit_3 & io_slli_bit_4 & io_slli_bit_5 & io_slli_bit_6 &
-    io_fcvtws_bit_7 & io_fcvtws_bit_8 & io_fcvtws_bit_9 & io_fcvtws_bit_10 & io_fcvtws_bit_11 & io_jalr_bit_17 &
-    io_jalr_bit_18 & io_jalr_bit_19; // @[Library.scala 311:48]
-  wire  _io_fmvxw_T_15 = _io_fmvxw_T_14 & io_inst[6]; // @[Library.scala 314:48]
-  wire  _io_fmvxw_T_16 = _io_fmvxw_T_15 & io_auipc_bit_26; // @[Library.scala 311:48]
-  wire  _io_fmvxw_T_17 = _io_fmvxw_T_16 & io_lui_bit_27; // @[Library.scala 314:48]
-  wire  _io_fmvxw_T_19 = _io_fmvxw_T_17 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 311:48]
-  wire  _io_feq_T_1 = io_inst[31] & io_fence_bit_1; // @[Library.scala 311:48]
-  wire  _io_feq_T_2 = _io_feq_T_1 & io_lui_bit_2; // @[Library.scala 314:48]
-  wire  _io_feq_T_7 = _io_feq_T_2 & io_fence_bit_3 & io_slli_bit_4 & io_slli_bit_5 & io_slli_bit_6 & io_jalr_bit_17; // @[Library.scala 311:48]
-  wire  _io_feq_T_8 = _io_feq_T_7 & io_lui_bit_18; // @[Library.scala 314:48]
-  wire  _io_feq_T_9 = _io_feq_T_8 & io_jalr_bit_19; // @[Library.scala 311:48]
-  wire  _io_feq_T_10 = _io_feq_T_9 & io_inst[6]; // @[Library.scala 314:48]
-  wire  _io_feq_T_11 = _io_feq_T_10 & io_auipc_bit_26; // @[Library.scala 311:48]
-  wire  _io_feq_T_12 = _io_feq_T_11 & io_lui_bit_27; // @[Library.scala 314:48]
-  wire  _io_feq_T_14 = _io_feq_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 311:48]
-  wire  _io_flt_T_8 = _io_feq_T_2 & io_fence_bit_3 & io_slli_bit_4 & io_slli_bit_5 & io_slli_bit_6 & io_jalr_bit_17 &
-    io_jalr_bit_18; // @[Library.scala 311:48]
-  wire  _io_flt_T_10 = _io_flt_T_8 & io_lui_bit_19 & io_inst[6]; // @[Library.scala 314:48]
-  wire  _io_flt_T_11 = _io_flt_T_10 & io_auipc_bit_26; // @[Library.scala 311:48]
-  wire  _io_flt_T_12 = _io_flt_T_11 & io_lui_bit_27; // @[Library.scala 314:48]
-  wire  _io_flt_T_14 = _io_flt_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 311:48]
-  wire  _io_fle_T_9 = _io_feq_T_2 & io_fence_bit_3 & io_slli_bit_4 & io_slli_bit_5 & io_slli_bit_6 & io_jalr_bit_17 &
-    io_jalr_bit_18 & io_jalr_bit_19; // @[Library.scala 311:48]
-  wire  _io_fle_T_10 = _io_fle_T_9 & io_inst[6]; // @[Library.scala 314:48]
-  wire  _io_fle_T_11 = _io_fle_T_10 & io_auipc_bit_26; // @[Library.scala 311:48]
-  wire  _io_fle_T_12 = _io_fle_T_11 & io_lui_bit_27; // @[Library.scala 314:48]
-  wire  _io_fle_T_14 = _io_fle_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 311:48]
-  wire  _io_fclass_T_15 = _io_fmvxw_T_13 & io_lui_bit_19 & io_inst[6]; // @[Library.scala 314:48]
-  wire  _io_fclass_T_16 = _io_fclass_T_15 & io_auipc_bit_26; // @[Library.scala 311:48]
-  wire  _io_fclass_T_17 = _io_fclass_T_16 & io_lui_bit_27; // @[Library.scala 314:48]
-  wire  _io_fclass_T_19 = _io_fclass_T_17 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 311:48]
-  wire  _io_fcvtsw_T_3 = _io_fcvtws_T_2 & io_lui_bit_3; // @[Library.scala 314:48]
-  wire  _io_fcvtsw_T_10 = _io_fcvtsw_T_3 & io_slli_bit_4 & io_slli_bit_5 & io_slli_bit_6 & io_fcvtws_bit_7 &
-    io_fcvtws_bit_8 & io_fcvtws_bit_9 & io_fcvtws_bit_10; // @[Library.scala 311:48]
-  wire  _io_fcvtsw_T_11 = _io_fcvtsw_T_3 & io_slli_bit_4 & io_slli_bit_5 & io_slli_bit_6 & io_fcvtws_bit_7 &
-    io_fcvtws_bit_8 & io_fcvtws_bit_9 & io_fcvtws_bit_10 & io_fcvtws_bit_11; // @[Library.scala 311:48]
-  wire  _io_fcvtsw_T_12 = _io_fcvtsw_T_11 & io_inst[6]; // @[Library.scala 314:48]
-  wire  _io_fcvtsw_T_13 = _io_fcvtsw_T_12 & io_auipc_bit_26; // @[Library.scala 311:48]
-  wire  _io_fcvtsw_T_14 = _io_fcvtsw_T_13 & io_lui_bit_27; // @[Library.scala 314:48]
-  wire  _io_fcvtsw_T_16 = _io_fcvtsw_T_14 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 311:48]
-  wire  _io_fcvtswu_T_12 = _io_fcvtsw_T_10 & io_inst[20] & io_inst[6]; // @[Library.scala 314:48]
-  wire  _io_fcvtswu_T_13 = _io_fcvtswu_T_12 & io_auipc_bit_26; // @[Library.scala 311:48]
-  wire  _io_fcvtswu_T_14 = _io_fcvtswu_T_13 & io_lui_bit_27; // @[Library.scala 314:48]
-  wire  _io_fcvtswu_T_16 = _io_fcvtswu_T_14 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 311:48]
-  wire  _io_fmvwx_T_3 = io_inst[31] & io_lui_bit_1 & io_lui_bit_2 & io_lui_bit_3; // @[Library.scala 314:48]
-  wire  _io_fmvwx_T_14 = _io_fmvwx_T_3 & io_slli_bit_4 & io_slli_bit_5 & io_slli_bit_6 & io_fcvtws_bit_7 &
-    io_fcvtws_bit_8 & io_fcvtws_bit_9 & io_fcvtws_bit_10 & io_fcvtws_bit_11 & io_jalr_bit_17 & io_jalr_bit_18 &
-    io_jalr_bit_19; // @[Library.scala 311:48]
-  wire  _io_fmvwx_T_15 = _io_fmvwx_T_14 & io_inst[6]; // @[Library.scala 314:48]
-  wire  _io_fmvwx_T_16 = _io_fmvwx_T_15 & io_auipc_bit_26; // @[Library.scala 311:48]
-  wire  _io_fmvwx_T_17 = _io_fmvwx_T_16 & io_lui_bit_27; // @[Library.scala 314:48]
-  wire  _io_fmvwx_T_19 = _io_fmvwx_T_17 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 311:48]
-  wire  _io_clb_T_2 = io_fence_bit & io_lui_bit_1 & io_lui_bit_2; // @[Library.scala 314:48]
-  wire  _io_clb_T_7 = _io_clb_T_2 & io_fence_bit_3 & io_slli_bit_4 & io_slli_bit_5 & io_slli_bit_6 & io_fcvtws_bit_7; // @[Library.scala 311:48]
-  wire  _io_clb_T_8 = _io_clb_T_7 & io_lui_bit_8; // @[Library.scala 314:48]
-  wire  _io_clb_T_13 = _io_clb_T_8 & io_fcvtws_bit_9 & io_fcvtws_bit_10 & io_fcvtws_bit_11 & io_jalr_bit_17 &
-    io_jalr_bit_18; // @[Library.scala 311:48]
-  wire  _io_clb_T_14 = _io_clb_T_13 & io_lui_bit_19; // @[Library.scala 314:48]
-  wire  _io_clb_T_16 = _io_clb_T_14 & io_lui_bit_25 & io_auipc_bit_26; // @[Library.scala 311:48]
-  wire  _io_clb_T_17 = _io_clb_T_16 & io_lui_bit_27; // @[Library.scala 314:48]
-  wire  _io_clb_T_19 = _io_clb_T_17 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 311:48]
-  wire  _io_clz_T_9 = _io_clb_T_2 & io_fence_bit_3 & io_slli_bit_4 & io_slli_bit_5 & io_slli_bit_6 & io_fcvtws_bit_7 &
-    io_fcvtws_bit_8 & io_fcvtws_bit_9; // @[Library.scala 311:48]
-  wire  _io_clz_T_10 = _io_clb_T_2 & io_fence_bit_3 & io_slli_bit_4 & io_slli_bit_5 & io_slli_bit_6 & io_fcvtws_bit_7 &
-    io_fcvtws_bit_8 & io_fcvtws_bit_9 & io_fcvtws_bit_10; // @[Library.scala 311:48]
-  wire  _io_clz_T_13 = _io_clb_T_2 & io_fence_bit_3 & io_slli_bit_4 & io_slli_bit_5 & io_slli_bit_6 & io_fcvtws_bit_7 &
-    io_fcvtws_bit_8 & io_fcvtws_bit_9 & io_fcvtws_bit_10 & io_fcvtws_bit_11 & io_jalr_bit_17 & io_jalr_bit_18; // @[Library.scala 311:48]
-  wire  _io_clz_T_14 = _io_clz_T_13 & io_lui_bit_19; // @[Library.scala 314:48]
-  wire  _io_clz_T_16 = _io_clz_T_14 & io_lui_bit_25 & io_auipc_bit_26; // @[Library.scala 311:48]
-  wire  _io_clz_T_17 = _io_clz_T_16 & io_lui_bit_27; // @[Library.scala 314:48]
-  wire  _io_clz_T_19 = _io_clz_T_17 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 311:48]
-  wire  _io_ctz_T_11 = _io_clz_T_10 & io_inst[20]; // @[Library.scala 314:48]
-  wire  _io_ctz_T_13 = _io_ctz_T_11 & io_jalr_bit_17 & io_jalr_bit_18; // @[Library.scala 311:48]
-  wire  _io_ctz_T_14 = _io_ctz_T_13 & io_lui_bit_19; // @[Library.scala 314:48]
-  wire  _io_ctz_T_16 = _io_ctz_T_14 & io_lui_bit_25 & io_auipc_bit_26; // @[Library.scala 311:48]
-  wire  _io_ctz_T_17 = _io_ctz_T_16 & io_lui_bit_27; // @[Library.scala 314:48]
-  wire  _io_ctz_T_19 = _io_ctz_T_17 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 311:48]
-  wire  _io_pcnt_T_10 = _io_clz_T_9 & io_lui_bit_10; // @[Library.scala 314:48]
-  wire  _io_pcnt_T_13 = _io_pcnt_T_10 & io_fcvtws_bit_11 & io_jalr_bit_17 & io_jalr_bit_18; // @[Library.scala 311:48]
-  wire  _io_pcnt_T_14 = _io_pcnt_T_13 & io_lui_bit_19; // @[Library.scala 314:48]
-  wire  _io_pcnt_T_16 = _io_pcnt_T_14 & io_lui_bit_25 & io_auipc_bit_26; // @[Library.scala 311:48]
-  wire  _io_pcnt_T_17 = _io_pcnt_T_16 & io_lui_bit_27; // @[Library.scala 314:48]
-  wire  _io_pcnt_T_19 = _io_pcnt_T_17 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 311:48]
-  wire  _io_min_T_7 = _io_fsub_T_5 & io_lui_bit_6 & io_lui_bit_17; // @[Library.scala 314:48]
-  wire  _io_min_T_8 = _io_min_T_7 & io_jalr_bit_18; // @[Library.scala 311:48]
-  wire  _io_min_T_10 = _io_min_T_7 & io_jalr_bit_18 & io_jalr_bit_19 & io_lui_bit_25; // @[Library.scala 311:48]
-  wire  _io_min_T_12 = _io_min_T_10 & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 314:48]
-  wire  _io_min_T_14 = _io_min_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 311:48]
-  wire  _io_minu_T_8 = _io_fsub_T_5 & io_lui_bit_6 & io_lui_bit_17 & io_lui_bit_18; // @[Library.scala 314:48]
-  wire  _io_minu_T_10 = _io_minu_T_8 & io_jalr_bit_19 & io_lui_bit_25; // @[Library.scala 311:48]
-  wire  _io_minu_T_12 = _io_minu_T_10 & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 314:48]
-  wire  _io_minu_T_14 = _io_minu_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 311:48]
-  wire  _io_max_T_9 = _io_min_T_8 & io_lui_bit_19; // @[Library.scala 314:48]
-  wire  _io_max_T_10 = _io_max_T_9 & io_lui_bit_25; // @[Library.scala 311:48]
-  wire  _io_max_T_12 = _io_max_T_10 & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 314:48]
-  wire  _io_max_T_14 = _io_max_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 311:48]
-  wire  _io_maxu_T_9 = _io_fsub_T_5 & io_lui_bit_6 & io_lui_bit_17 & io_lui_bit_18 & io_lui_bit_19; // @[Library.scala 314:48]
-  wire  _io_maxu_T_10 = _io_maxu_T_9 & io_lui_bit_25; // @[Library.scala 311:48]
-  wire  _io_maxu_T_12 = _io_maxu_T_10 & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 314:48]
-  wire  _io_maxu_T_14 = _io_maxu_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 311:48]
-  wire  _slog_T_4 = io_fence_bit & io_lui_bit_1 & io_lui_bit_2 & io_lui_bit_3 & io_lui_bit_4; // @[Library.scala 314:48]
-  wire  _slog_T_17 = _slog_T_4 & io_slli_bit_5 & io_slli_bit_6 & io_fcvtws_bit_7 & io_fcvtws_bit_8 & io_fcvtws_bit_9 &
-    io_fcvtws_bit_10 & io_fcvtws_bit_11 & io_jalr_bit_17 & io_fence_bit_20 & io_fence_bit_21 & io_fence_bit_22 &
-    io_fence_bit_23 & io_fence_bit_24; // @[Library.scala 311:48]
-  wire  _slog_T_20 = _slog_T_17 & io_inst[6] & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 314:48]
-  wire  _slog_T_21 = _slog_T_20 & io_lui_bit_28; // @[Library.scala 311:48]
-  wire  _io_getvl_T_6 = _io_fmul_T_3 & io_jalr_bit_17 & io_jalr_bit_18 & io_jalr_bit_19; // @[Library.scala 311:48]
-  wire  _io_getvl_T_9 = _io_getvl_T_6 & io_inst[6] & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 314:48]
-  wire  _io_getvl_T_10 = _io_getvl_T_9 & io_lui_bit_28; // @[Library.scala 311:48]
-  wire  _io_getvl_T_13 = _io_getvl_T_10 & io_lui_bit_29 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 314:48]
-  wire  _io_getvl_T_15 = io_inst[26:25] != 2'h3; // @[Decode.scala 688:89]
-  wire  _io_getvl_T_20 = io_inst[19:15] != 5'h0; // @[Decode.scala 688:132]
-  wire  _io_getmaxvl_T_16 = _io_fmul_T_3 & io_fcvtws_bit_7 & io_fcvtws_bit_8 & io_fcvtws_bit_9 & io_fcvtws_bit_10 &
-    io_fcvtws_bit_11 & io_fence_bit_12 & io_fence_bit_13 & io_fence_bit_14 & io_fence_bit_15 & io_fence_bit_16 &
-    io_jalr_bit_17 & io_jalr_bit_18 & io_jalr_bit_19; // @[Library.scala 311:48]
-  wire  _io_getmaxvl_T_19 = _io_getmaxvl_T_16 & io_inst[6] & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 314:48]
-  wire  _io_getmaxvl_T_20 = _io_getmaxvl_T_19 & io_lui_bit_28; // @[Library.scala 311:48]
-  wire  _io_getmaxvl_T_23 = _io_getmaxvl_T_20 & io_lui_bit_29 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 314:48]
-  wire  _io_vld_T_4 = io_fence_bit & io_fence_bit_1 & io_fence_bit_2 & io_slli_bit_6 & io_jalr_bit_17; // @[Library.scala 311:48]
-  wire  _io_vst_T_4 = _io_mulhr_T_2 & io_slli_bit_6 & io_jalr_bit_17; // @[Library.scala 311:48]
-  wire  _io_vst_T_9 = _io_vst_T_4 & io_lui_bit_27 & io_inst[3] & io_lui_bit_29 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 314:48]
-  wire  _io_vst_T_14 = _io_clb_T_2 & io_slli_bit_6 & io_jalr_bit_17; // @[Library.scala 311:48]
-  wire  _io_vst_T_19 = _io_vst_T_14 & io_lui_bit_27 & io_inst[3] & io_lui_bit_29 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 314:48]
-  wire  _vconv_T_17 = _io_fsqrt_T_3 & io_slli_bit_4 & io_slli_bit_5 & io_slli_bit_6 & io_fcvtws_bit_7 & io_fcvtws_bit_8
-     & io_fcvtws_bit_9 & io_fcvtws_bit_10 & io_fcvtws_bit_11 & io_fence_bit_12 & io_fence_bit_13 & io_fence_bit_14 &
-    io_fence_bit_15 & io_fence_bit_16 & io_jalr_bit_17; // @[Library.scala 311:48]
-  wire  vconv = _vconv_T_17 & io_lui_bit_27 & io_inst[3] & io_lui_bit_29 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 314:48]
+    io_jalr_bit_17 & io_jalr_bit_18 & io_jalr_bit_19 & io_lui_bit_25; // @[Library.scala 313:48]
+  wire  _io_sub_T_12 = _io_sub_T_10 & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 316:48]
+  wire  _io_sub_T_14 = _io_sub_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 313:48]
+  wire  _io_slt_T_8 = _io_slli_T_7 & io_lui_bit_18; // @[Library.scala 316:48]
+  wire  _io_slt_T_10 = _io_slt_T_8 & io_jalr_bit_19 & io_lui_bit_25; // @[Library.scala 313:48]
+  wire  _io_slt_T_12 = _io_slt_T_10 & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 316:48]
+  wire  _io_slt_T_14 = _io_slt_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 313:48]
+  wire  _io_sltu_T_9 = _io_slli_T_7 & io_lui_bit_18 & io_lui_bit_19; // @[Library.scala 316:48]
+  wire  _io_sltu_T_10 = _io_sltu_T_9 & io_lui_bit_25; // @[Library.scala 313:48]
+  wire  _io_sltu_T_12 = _io_sltu_T_10 & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 316:48]
+  wire  _io_sltu_T_14 = _io_sltu_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 313:48]
+  wire  _io_xor_T_10 = _io_srli_T_7 & io_jalr_bit_18 & io_jalr_bit_19 & io_lui_bit_25; // @[Library.scala 313:48]
+  wire  _io_xor_T_12 = _io_xor_T_10 & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 316:48]
+  wire  _io_xor_T_14 = _io_xor_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 313:48]
+  wire  _io_or_T_8 = _io_slli_T_6 & io_lui_bit_17 & io_lui_bit_18; // @[Library.scala 316:48]
+  wire  _io_or_T_10 = _io_or_T_8 & io_jalr_bit_19 & io_lui_bit_25; // @[Library.scala 313:48]
+  wire  _io_or_T_12 = _io_or_T_10 & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 316:48]
+  wire  _io_or_T_14 = _io_or_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 313:48]
+  wire  _io_and_T_9 = _io_slli_T_6 & io_lui_bit_17 & io_lui_bit_18 & io_lui_bit_19; // @[Library.scala 316:48]
+  wire  _io_and_T_10 = _io_and_T_9 & io_lui_bit_25; // @[Library.scala 313:48]
+  wire  _io_and_T_12 = _io_and_T_10 & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 316:48]
+  wire  _io_and_T_14 = _io_and_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 313:48]
+  wire  _io_sll_T_12 = _io_slli_T_10 & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 316:48]
+  wire  _io_sll_T_14 = _io_sll_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 313:48]
+  wire  _io_srl_T_12 = _io_srli_T_10 & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 316:48]
+  wire  _io_srl_T_14 = _io_srl_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 313:48]
+  wire  _io_sra_T_12 = _io_srai_T_10 & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 316:48]
+  wire  _io_sra_T_14 = _io_sra_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 313:48]
+  wire  _io_mul_T_6 = _io_slli_T_5 & io_lui_bit_6; // @[Library.scala 316:48]
+  wire  _io_mul_T_7 = _io_mul_T_6 & io_jalr_bit_17; // @[Library.scala 313:48]
+  wire  _io_mul_T_8 = _io_mul_T_6 & io_jalr_bit_17 & io_jalr_bit_18; // @[Library.scala 313:48]
+  wire  _io_mul_T_10 = _io_mul_T_6 & io_jalr_bit_17 & io_jalr_bit_18 & io_jalr_bit_19 & io_lui_bit_25; // @[Library.scala 313:48]
+  wire  _io_mul_T_12 = _io_mul_T_10 & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 316:48]
+  wire  _io_mul_T_14 = _io_mul_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 313:48]
+  wire  _io_mulh_T_9 = _io_mul_T_8 & io_lui_bit_19; // @[Library.scala 316:48]
+  wire  _io_mulh_T_10 = _io_mulh_T_9 & io_lui_bit_25; // @[Library.scala 313:48]
+  wire  _io_mulh_T_12 = _io_mulh_T_10 & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 316:48]
+  wire  _io_mulh_T_14 = _io_mulh_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 313:48]
+  wire  _io_mulhsu_T_8 = _io_mul_T_7 & io_lui_bit_18; // @[Library.scala 316:48]
+  wire  _io_mulhsu_T_10 = _io_mulhsu_T_8 & io_jalr_bit_19 & io_lui_bit_25; // @[Library.scala 313:48]
+  wire  _io_mulhsu_T_12 = _io_mulhsu_T_10 & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 316:48]
+  wire  _io_mulhsu_T_14 = _io_mulhsu_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 313:48]
+  wire  _io_mulhu_T_9 = _io_mul_T_7 & io_lui_bit_18 & io_lui_bit_19; // @[Library.scala 316:48]
+  wire  _io_mulhu_T_10 = _io_mulhu_T_9 & io_lui_bit_25; // @[Library.scala 313:48]
+  wire  _io_mulhu_T_12 = _io_mulhu_T_10 & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 316:48]
+  wire  _io_mulhu_T_14 = _io_mulhu_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 313:48]
+  wire  _io_mulhr_T_2 = _io_fence_T_1 & io_lui_bit_2; // @[Library.scala 316:48]
+  wire  _io_mulhr_T_4 = _io_mulhr_T_2 & io_fence_bit_3 & io_slli_bit_4; // @[Library.scala 313:48]
+  wire  _io_mulhr_T_5 = _io_mulhr_T_2 & io_fence_bit_3 & io_slli_bit_4 & io_slli_bit_5; // @[Library.scala 313:48]
+  wire  _io_mulhr_T_6 = _io_mulhr_T_5 & io_lui_bit_6; // @[Library.scala 316:48]
+  wire  _io_mulhr_T_7 = _io_mulhr_T_6 & io_jalr_bit_17; // @[Library.scala 313:48]
+  wire  _io_mulhr_T_8 = _io_mulhr_T_6 & io_jalr_bit_17 & io_jalr_bit_18; // @[Library.scala 313:48]
+  wire  _io_mulhr_T_9 = _io_mulhr_T_8 & io_lui_bit_19; // @[Library.scala 316:48]
+  wire  _io_mulhr_T_10 = _io_mulhr_T_9 & io_lui_bit_25; // @[Library.scala 313:48]
+  wire  _io_mulhr_T_12 = _io_mulhr_T_10 & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 316:48]
+  wire  _io_mulhr_T_14 = _io_mulhr_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 313:48]
+  wire  _io_mulhsur_T_8 = _io_mulhr_T_7 & io_lui_bit_18; // @[Library.scala 316:48]
+  wire  _io_mulhsur_T_10 = _io_mulhsur_T_8 & io_jalr_bit_19 & io_lui_bit_25; // @[Library.scala 313:48]
+  wire  _io_mulhsur_T_12 = _io_mulhsur_T_10 & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 316:48]
+  wire  _io_mulhsur_T_14 = _io_mulhsur_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 313:48]
+  wire  _io_mulhur_T_9 = _io_mulhr_T_7 & io_lui_bit_18 & io_lui_bit_19; // @[Library.scala 316:48]
+  wire  _io_mulhur_T_10 = _io_mulhur_T_9 & io_lui_bit_25; // @[Library.scala 313:48]
+  wire  _io_mulhur_T_12 = _io_mulhur_T_10 & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 316:48]
+  wire  _io_mulhur_T_14 = _io_mulhur_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 313:48]
+  wire  _io_dmulh_T_5 = _io_slli_T_4 & io_lui_bit_5; // @[Library.scala 316:48]
+  wire  _io_dmulh_T_8 = _io_dmulh_T_5 & io_slli_bit_6 & io_jalr_bit_17 & io_jalr_bit_18; // @[Library.scala 313:48]
+  wire  _io_dmulh_T_9 = _io_dmulh_T_8 & io_lui_bit_19; // @[Library.scala 316:48]
+  wire  _io_dmulh_T_10 = _io_dmulh_T_9 & io_lui_bit_25; // @[Library.scala 313:48]
+  wire  _io_dmulh_T_12 = _io_dmulh_T_10 & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 316:48]
+  wire  _io_dmulh_T_14 = _io_dmulh_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 313:48]
+  wire  _io_dmulhr_T_5 = _io_mulhr_T_4 & io_lui_bit_5; // @[Library.scala 316:48]
+  wire  _io_dmulhr_T_8 = _io_dmulhr_T_5 & io_slli_bit_6 & io_jalr_bit_17 & io_jalr_bit_18; // @[Library.scala 313:48]
+  wire  _io_dmulhr_T_9 = _io_dmulhr_T_8 & io_lui_bit_19; // @[Library.scala 316:48]
+  wire  _io_dmulhr_T_10 = _io_dmulhr_T_9 & io_lui_bit_25; // @[Library.scala 313:48]
+  wire  _io_dmulhr_T_12 = _io_dmulhr_T_10 & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 316:48]
+  wire  _io_dmulhr_T_14 = _io_dmulhr_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 313:48]
+  wire  _io_div_T_7 = _io_slli_T_5 & io_lui_bit_6 & io_lui_bit_17; // @[Library.scala 316:48]
+  wire  _io_div_T_8 = _io_div_T_7 & io_jalr_bit_18; // @[Library.scala 313:48]
+  wire  _io_div_T_10 = _io_div_T_7 & io_jalr_bit_18 & io_jalr_bit_19 & io_lui_bit_25; // @[Library.scala 313:48]
+  wire  _io_div_T_12 = _io_div_T_10 & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 316:48]
+  wire  _io_div_T_14 = _io_div_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 313:48]
+  wire  _io_divu_T_9 = _io_div_T_8 & io_lui_bit_19; // @[Library.scala 316:48]
+  wire  _io_divu_T_10 = _io_divu_T_9 & io_lui_bit_25; // @[Library.scala 313:48]
+  wire  _io_divu_T_12 = _io_divu_T_10 & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 316:48]
+  wire  _io_divu_T_14 = _io_divu_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 313:48]
+  wire  _io_rem_T_8 = _io_slli_T_5 & io_lui_bit_6 & io_lui_bit_17 & io_lui_bit_18; // @[Library.scala 316:48]
+  wire  _io_rem_T_10 = _io_rem_T_8 & io_jalr_bit_19 & io_lui_bit_25; // @[Library.scala 313:48]
+  wire  _io_rem_T_12 = _io_rem_T_10 & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 316:48]
+  wire  _io_rem_T_14 = _io_rem_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 313:48]
+  wire  _io_remu_T_9 = _io_slli_T_5 & io_lui_bit_6 & io_lui_bit_17 & io_lui_bit_18 & io_lui_bit_19; // @[Library.scala 316:48]
+  wire  _io_remu_T_10 = _io_remu_T_9 & io_lui_bit_25; // @[Library.scala 313:48]
+  wire  _io_remu_T_12 = _io_remu_T_10 & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 316:48]
+  wire  _io_remu_T_14 = _io_remu_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 313:48]
+  wire  _io_clz_T_2 = io_fence_bit & io_lui_bit_1 & io_lui_bit_2; // @[Library.scala 316:48]
+  wire  io_clz_bit_7 = ~io_lui_bit_7; // @[Library.scala 312:19]
+  wire  io_clz_bit_8 = ~io_lui_bit_8; // @[Library.scala 312:19]
+  wire  io_clz_bit_9 = ~io_lui_bit_9; // @[Library.scala 312:19]
+  wire  _io_clz_T_9 = _io_clz_T_2 & io_fence_bit_3 & io_slli_bit_4 & io_slli_bit_5 & io_slli_bit_6 & io_clz_bit_7 &
+    io_clz_bit_8 & io_clz_bit_9; // @[Library.scala 313:48]
+  wire  io_clz_bit_10 = ~io_lui_bit_10; // @[Library.scala 312:19]
+  wire  _io_clz_T_10 = _io_clz_T_2 & io_fence_bit_3 & io_slli_bit_4 & io_slli_bit_5 & io_slli_bit_6 & io_clz_bit_7 &
+    io_clz_bit_8 & io_clz_bit_9 & io_clz_bit_10; // @[Library.scala 313:48]
+  wire  io_clz_bit_11 = ~io_inst[20]; // @[Library.scala 312:19]
+  wire  _io_clz_T_13 = _io_clz_T_2 & io_fence_bit_3 & io_slli_bit_4 & io_slli_bit_5 & io_slli_bit_6 & io_clz_bit_7 &
+    io_clz_bit_8 & io_clz_bit_9 & io_clz_bit_10 & io_clz_bit_11 & io_jalr_bit_17 & io_jalr_bit_18; // @[Library.scala 313:48]
+  wire  _io_clz_T_14 = _io_clz_T_13 & io_lui_bit_19; // @[Library.scala 316:48]
+  wire  _io_clz_T_16 = _io_clz_T_14 & io_lui_bit_25 & io_auipc_bit_26; // @[Library.scala 313:48]
+  wire  _io_clz_T_17 = _io_clz_T_16 & io_lui_bit_27; // @[Library.scala 316:48]
+  wire  _io_clz_T_19 = _io_clz_T_17 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 313:48]
+  wire  _io_ctz_T_11 = _io_clz_T_10 & io_inst[20]; // @[Library.scala 316:48]
+  wire  _io_ctz_T_13 = _io_ctz_T_11 & io_jalr_bit_17 & io_jalr_bit_18; // @[Library.scala 313:48]
+  wire  _io_ctz_T_14 = _io_ctz_T_13 & io_lui_bit_19; // @[Library.scala 316:48]
+  wire  _io_ctz_T_16 = _io_ctz_T_14 & io_lui_bit_25 & io_auipc_bit_26; // @[Library.scala 313:48]
+  wire  _io_ctz_T_17 = _io_ctz_T_16 & io_lui_bit_27; // @[Library.scala 316:48]
+  wire  _io_ctz_T_19 = _io_ctz_T_17 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 313:48]
+  wire  _io_pcnt_T_10 = _io_clz_T_9 & io_lui_bit_10; // @[Library.scala 316:48]
+  wire  _io_pcnt_T_13 = _io_pcnt_T_10 & io_clz_bit_11 & io_jalr_bit_17 & io_jalr_bit_18; // @[Library.scala 313:48]
+  wire  _io_pcnt_T_14 = _io_pcnt_T_13 & io_lui_bit_19; // @[Library.scala 316:48]
+  wire  _io_pcnt_T_16 = _io_pcnt_T_14 & io_lui_bit_25 & io_auipc_bit_26; // @[Library.scala 313:48]
+  wire  _io_pcnt_T_17 = _io_pcnt_T_16 & io_lui_bit_27; // @[Library.scala 316:48]
+  wire  _io_pcnt_T_19 = _io_pcnt_T_17 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 313:48]
+  wire  _io_min_T_4 = _io_fence_T_3 & io_lui_bit_4; // @[Library.scala 316:48]
+  wire  _io_min_T_5 = _io_min_T_4 & io_slli_bit_5; // @[Library.scala 313:48]
+  wire  _io_min_T_7 = _io_min_T_5 & io_lui_bit_6 & io_lui_bit_17; // @[Library.scala 316:48]
+  wire  _io_min_T_8 = _io_min_T_7 & io_jalr_bit_18; // @[Library.scala 313:48]
+  wire  _io_min_T_10 = _io_min_T_7 & io_jalr_bit_18 & io_jalr_bit_19 & io_lui_bit_25; // @[Library.scala 313:48]
+  wire  _io_min_T_12 = _io_min_T_10 & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 316:48]
+  wire  _io_min_T_14 = _io_min_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 313:48]
+  wire  _io_minu_T_9 = _io_min_T_8 & io_lui_bit_19; // @[Library.scala 316:48]
+  wire  _io_minu_T_10 = _io_minu_T_9 & io_lui_bit_25; // @[Library.scala 313:48]
+  wire  _io_minu_T_12 = _io_minu_T_10 & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 316:48]
+  wire  _io_minu_T_14 = _io_minu_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 313:48]
+  wire  _io_max_T_8 = _io_min_T_5 & io_lui_bit_6 & io_lui_bit_17 & io_lui_bit_18; // @[Library.scala 316:48]
+  wire  _io_max_T_10 = _io_max_T_8 & io_jalr_bit_19 & io_lui_bit_25; // @[Library.scala 313:48]
+  wire  _io_max_T_12 = _io_max_T_10 & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 316:48]
+  wire  _io_max_T_14 = _io_max_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 313:48]
+  wire  _io_maxu_T_9 = _io_min_T_5 & io_lui_bit_6 & io_lui_bit_17 & io_lui_bit_18 & io_lui_bit_19; // @[Library.scala 316:48]
+  wire  _io_maxu_T_10 = _io_maxu_T_9 & io_lui_bit_25; // @[Library.scala 313:48]
+  wire  _io_maxu_T_12 = _io_maxu_T_10 & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 316:48]
+  wire  _io_maxu_T_14 = _io_maxu_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 313:48]
+  wire  _slog_T_4 = io_fence_bit & io_lui_bit_1 & io_lui_bit_2 & io_lui_bit_3 & io_lui_bit_4; // @[Library.scala 316:48]
+  wire  _slog_T_17 = _slog_T_4 & io_slli_bit_5 & io_slli_bit_6 & io_clz_bit_7 & io_clz_bit_8 & io_clz_bit_9 &
+    io_clz_bit_10 & io_clz_bit_11 & io_jalr_bit_17 & io_fence_bit_20 & io_fence_bit_21 & io_fence_bit_22 &
+    io_fence_bit_23 & io_fence_bit_24; // @[Library.scala 313:48]
+  wire  _slog_T_20 = _slog_T_17 & io_inst[6] & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 316:48]
+  wire  _slog_T_21 = _slog_T_20 & io_lui_bit_28; // @[Library.scala 313:48]
+  wire  _io_getvl_T_3 = _io_fence_T_2 & io_lui_bit_3; // @[Library.scala 316:48]
+  wire  _io_getvl_T_6 = _io_getvl_T_3 & io_jalr_bit_17 & io_jalr_bit_18 & io_jalr_bit_19; // @[Library.scala 313:48]
+  wire  _io_getvl_T_9 = _io_getvl_T_6 & io_inst[6] & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 316:48]
+  wire  _io_getvl_T_10 = _io_getvl_T_9 & io_lui_bit_28; // @[Library.scala 313:48]
+  wire  _io_getvl_T_13 = _io_getvl_T_10 & io_lui_bit_29 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 316:48]
+  wire  _io_getvl_T_15 = io_inst[26:25] != 2'h3; // @[Decode.scala 565:89]
+  wire  _io_getvl_T_20 = io_inst[19:15] != 5'h0; // @[Decode.scala 565:132]
+  wire  _io_getmaxvl_T_16 = _io_getvl_T_3 & io_clz_bit_7 & io_clz_bit_8 & io_clz_bit_9 & io_clz_bit_10 & io_clz_bit_11
+     & io_fence_bit_12 & io_fence_bit_13 & io_fence_bit_14 & io_fence_bit_15 & io_fence_bit_16 & io_jalr_bit_17 &
+    io_jalr_bit_18 & io_jalr_bit_19; // @[Library.scala 313:48]
+  wire  _io_getmaxvl_T_19 = _io_getmaxvl_T_16 & io_inst[6] & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 316:48]
+  wire  _io_getmaxvl_T_20 = _io_getmaxvl_T_19 & io_lui_bit_28; // @[Library.scala 313:48]
+  wire  _io_getmaxvl_T_23 = _io_getmaxvl_T_20 & io_lui_bit_29 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 316:48]
+  wire  _io_vld_T_4 = io_fence_bit & io_fence_bit_1 & io_fence_bit_2 & io_slli_bit_6 & io_jalr_bit_17; // @[Library.scala 313:48]
+  wire  _io_vst_T_4 = _io_mulhr_T_2 & io_slli_bit_6 & io_jalr_bit_17; // @[Library.scala 313:48]
+  wire  _io_vst_T_9 = _io_vst_T_4 & io_lui_bit_27 & io_inst[3] & io_lui_bit_29 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 316:48]
+  wire  _io_vst_T_14 = _io_clz_T_2 & io_slli_bit_6 & io_jalr_bit_17; // @[Library.scala 313:48]
+  wire  _io_vst_T_19 = _io_vst_T_14 & io_lui_bit_27 & io_inst[3] & io_lui_bit_29 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 316:48]
+  wire  _vconv_T_3 = _io_srai_T_2 & io_lui_bit_3; // @[Library.scala 316:48]
+  wire  _vconv_T_17 = _vconv_T_3 & io_slli_bit_4 & io_slli_bit_5 & io_slli_bit_6 & io_clz_bit_7 & io_clz_bit_8 &
+    io_clz_bit_9 & io_clz_bit_10 & io_clz_bit_11 & io_fence_bit_12 & io_fence_bit_13 & io_fence_bit_14 & io_fence_bit_15
+     & io_fence_bit_16 & io_jalr_bit_17; // @[Library.scala 313:48]
+  wire  vconv = _vconv_T_17 & io_lui_bit_27 & io_inst[3] & io_lui_bit_29 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 316:48]
   wire  _vdup_T_11 = _io_srai_T_1 & io_fence_bit_2 & io_fence_bit_3 & io_slli_bit_4 & io_slli_bit_6 & io_fence_bit_12 &
-    io_fence_bit_13 & io_fence_bit_14 & io_fence_bit_15 & io_fence_bit_16 & io_jalr_bit_17; // @[Library.scala 311:48]
-  wire  _vdup_T_16 = _vdup_T_11 & io_lui_bit_27 & io_inst[3] & io_lui_bit_29 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 314:48]
-  wire  vdup = _vdup_T_16 & io_inst[13:12] <= 2'h2; // @[Decode.scala 701:72]
-  wire  vdupi = vdup & io_slli_bit_5; // @[Decode.scala 702:20]
-  wire  vdupf = vdup & io_lui_bit_5; // @[Decode.scala 703:20]
-  wire  _vfma_T_1 = ~io_lui_bit_31; // @[Decode.scala 706:21]
-  wire  vfma = ~io_lui_bit_31 & io_inst[4:2] == 3'h5; // @[Decode.scala 706:29]
-  wire  _vfma4_T_1 = io_inst[1:0] == 2'h1; // @[Decode.scala 707:23]
-  wire [3:0] _vfma4_T_4 = {io_inst[13:12],io_inst[4:3]}; // @[Cat.scala 31:58]
-  wire  vfma4 = io_inst[1:0] == 2'h1 & _vfma4_T_4 == 4'h0; // @[Decode.scala 707:31]
-  wire  _io_viop_T_7 = _vfma4_T_1 & ~vfma4; // @[Decode.scala 712:30]
-  wire  _io_viop_T_8 = _vfma_T_1 & ~vfma | _io_viop_T_7; // @[Decode.scala 711:37]
-  wire  _io_viop_T_9 = _io_viop_T_8 | vconv; // @[Decode.scala 712:40]
+    io_fence_bit_13 & io_fence_bit_14 & io_fence_bit_15 & io_fence_bit_16 & io_jalr_bit_17; // @[Library.scala 313:48]
+  wire  _vdup_T_16 = _vdup_T_11 & io_lui_bit_27 & io_inst[3] & io_lui_bit_29 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 316:48]
+  wire  vdup = _vdup_T_16 & io_inst[13:12] <= 2'h2; // @[Decode.scala 578:72]
+  wire  vdupi = vdup & io_slli_bit_5; // @[Decode.scala 579:20]
+  wire  _io_viop_T_3 = io_inst[1:0] == 2'h1; // @[Decode.scala 583:22]
+  wire  _io_viop_T_4 = ~io_lui_bit_31 | _io_viop_T_3; // @[Decode.scala 582:28]
+  wire  _io_viop_T_5 = _io_viop_T_4 | vconv; // @[Decode.scala 583:30]
   wire  _io_ebreak_T_10 = io_fence_bit & io_fence_bit_1 & io_fence_bit_2 & io_fence_bit_3 & io_slli_bit_4 &
-    io_slli_bit_5 & io_slli_bit_6 & io_fcvtws_bit_7 & io_fcvtws_bit_8 & io_fcvtws_bit_9 & io_fcvtws_bit_10; // @[Library.scala 311:48]
-  wire  _io_ebreak_T_11 = _io_ebreak_T_10 & io_inst[20]; // @[Library.scala 314:48]
+    io_slli_bit_5 & io_slli_bit_6 & io_clz_bit_7 & io_clz_bit_8 & io_clz_bit_9 & io_clz_bit_10; // @[Library.scala 313:48]
+  wire  _io_ebreak_T_11 = _io_ebreak_T_10 & io_inst[20]; // @[Library.scala 316:48]
   wire  _io_ebreak_T_24 = _io_ebreak_T_11 & io_fence_bit_12 & io_fence_bit_13 & io_fence_bit_14 & io_fence_bit_15 &
     io_fence_bit_16 & io_jalr_bit_17 & io_jalr_bit_18 & io_jalr_bit_19 & io_fence_bit_20 & io_fence_bit_21 &
-    io_fence_bit_22 & io_fence_bit_23 & io_fence_bit_24; // @[Library.scala 311:48]
-  wire  _io_ebreak_T_27 = _io_ebreak_T_24 & io_inst[6] & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 314:48]
-  wire  _io_ebreak_T_29 = _io_ebreak_T_27 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 311:48]
+    io_fence_bit_22 & io_fence_bit_23 & io_fence_bit_24; // @[Library.scala 313:48]
+  wire  _io_ebreak_T_27 = _io_ebreak_T_24 & io_inst[6] & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 316:48]
+  wire  _io_ebreak_T_29 = _io_ebreak_T_27 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 313:48]
   wire  _io_ecall_T_18 = io_fence_bit & io_fence_bit_1 & io_fence_bit_2 & io_fence_bit_3 & io_slli_bit_4 & io_slli_bit_5
-     & io_slli_bit_6 & io_fcvtws_bit_7 & io_fcvtws_bit_8 & io_fcvtws_bit_9 & io_fcvtws_bit_10 & io_fcvtws_bit_11 &
-    io_fence_bit_12 & io_fence_bit_13 & io_fence_bit_14 & io_fence_bit_15 & io_fence_bit_16 & io_jalr_bit_17 &
-    io_jalr_bit_18; // @[Library.scala 311:48]
+     & io_slli_bit_6 & io_clz_bit_7 & io_clz_bit_8 & io_clz_bit_9 & io_clz_bit_10 & io_clz_bit_11 & io_fence_bit_12 &
+    io_fence_bit_13 & io_fence_bit_14 & io_fence_bit_15 & io_fence_bit_16 & io_jalr_bit_17 & io_jalr_bit_18; // @[Library.scala 313:48]
   wire  _io_ecall_T_24 = io_fence_bit & io_fence_bit_1 & io_fence_bit_2 & io_fence_bit_3 & io_slli_bit_4 & io_slli_bit_5
-     & io_slli_bit_6 & io_fcvtws_bit_7 & io_fcvtws_bit_8 & io_fcvtws_bit_9 & io_fcvtws_bit_10 & io_fcvtws_bit_11 &
+     & io_slli_bit_6 & io_clz_bit_7 & io_clz_bit_8 & io_clz_bit_9 & io_clz_bit_10 & io_clz_bit_11 & io_fence_bit_12 &
+    io_fence_bit_13 & io_fence_bit_14 & io_fence_bit_15 & io_fence_bit_16 & io_jalr_bit_17 & io_jalr_bit_18 &
+    io_jalr_bit_19 & io_fence_bit_20 & io_fence_bit_21 & io_fence_bit_22 & io_fence_bit_23 & io_fence_bit_24; // @[Library.scala 313:48]
+  wire  _io_ecall_T_27 = _io_ecall_T_24 & io_inst[6] & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 316:48]
+  wire  _io_ecall_T_29 = _io_ecall_T_27 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 313:48]
+  wire  _io_eexit_T_24 = _io_mul_T_6 & io_clz_bit_7 & io_clz_bit_8 & io_clz_bit_9 & io_clz_bit_10 & io_clz_bit_11 &
     io_fence_bit_12 & io_fence_bit_13 & io_fence_bit_14 & io_fence_bit_15 & io_fence_bit_16 & io_jalr_bit_17 &
     io_jalr_bit_18 & io_jalr_bit_19 & io_fence_bit_20 & io_fence_bit_21 & io_fence_bit_22 & io_fence_bit_23 &
-    io_fence_bit_24; // @[Library.scala 311:48]
-  wire  _io_ecall_T_27 = _io_ecall_T_24 & io_inst[6] & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 314:48]
-  wire  _io_ecall_T_29 = _io_ecall_T_27 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 311:48]
-  wire  _io_eexit_T_24 = _io_mul_T_6 & io_fcvtws_bit_7 & io_fcvtws_bit_8 & io_fcvtws_bit_9 & io_fcvtws_bit_10 &
-    io_fcvtws_bit_11 & io_fence_bit_12 & io_fence_bit_13 & io_fence_bit_14 & io_fence_bit_15 & io_fence_bit_16 &
+    io_fence_bit_24; // @[Library.scala 313:48]
+  wire  _io_eexit_T_27 = _io_eexit_T_24 & io_inst[6] & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 316:48]
+  wire  _io_eexit_T_29 = _io_eexit_T_27 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 313:48]
+  wire  _io_eyield_T_24 = _io_dmulh_T_5 & io_slli_bit_6 & io_clz_bit_7 & io_clz_bit_8 & io_clz_bit_9 & io_clz_bit_10 &
+    io_clz_bit_11 & io_fence_bit_12 & io_fence_bit_13 & io_fence_bit_14 & io_fence_bit_15 & io_fence_bit_16 &
     io_jalr_bit_17 & io_jalr_bit_18 & io_jalr_bit_19 & io_fence_bit_20 & io_fence_bit_21 & io_fence_bit_22 &
-    io_fence_bit_23 & io_fence_bit_24; // @[Library.scala 311:48]
-  wire  _io_eexit_T_27 = _io_eexit_T_24 & io_inst[6] & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 314:48]
-  wire  _io_eexit_T_29 = _io_eexit_T_27 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 311:48]
-  wire  _io_eyield_T_24 = _io_dmulh_T_5 & io_slli_bit_6 & io_fcvtws_bit_7 & io_fcvtws_bit_8 & io_fcvtws_bit_9 &
-    io_fcvtws_bit_10 & io_fcvtws_bit_11 & io_fence_bit_12 & io_fence_bit_13 & io_fence_bit_14 & io_fence_bit_15 &
+    io_fence_bit_23 & io_fence_bit_24; // @[Library.scala 313:48]
+  wire  _io_eyield_T_27 = _io_eyield_T_24 & io_inst[6] & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 316:48]
+  wire  _io_eyield_T_29 = _io_eyield_T_27 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 313:48]
+  wire  _io_ectxsw_T_6 = _io_slli_T_4 & io_lui_bit_5 & io_lui_bit_6; // @[Library.scala 316:48]
+  wire  _io_ectxsw_T_24 = _io_ectxsw_T_6 & io_clz_bit_7 & io_clz_bit_8 & io_clz_bit_9 & io_clz_bit_10 & io_clz_bit_11 &
+    io_fence_bit_12 & io_fence_bit_13 & io_fence_bit_14 & io_fence_bit_15 & io_fence_bit_16 & io_jalr_bit_17 &
+    io_jalr_bit_18 & io_jalr_bit_19 & io_fence_bit_20 & io_fence_bit_21 & io_fence_bit_22 & io_fence_bit_23 &
+    io_fence_bit_24; // @[Library.scala 313:48]
+  wire  _io_ectxsw_T_27 = _io_ectxsw_T_24 & io_inst[6] & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 316:48]
+  wire  _io_ectxsw_T_29 = _io_ectxsw_T_27 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 313:48]
+  wire  _io_mpause_T_24 = _io_min_T_4 & io_slli_bit_5 & io_slli_bit_6 & io_clz_bit_7 & io_clz_bit_8 & io_clz_bit_9 &
+    io_clz_bit_10 & io_clz_bit_11 & io_fence_bit_12 & io_fence_bit_13 & io_fence_bit_14 & io_fence_bit_15 &
     io_fence_bit_16 & io_jalr_bit_17 & io_jalr_bit_18 & io_jalr_bit_19 & io_fence_bit_20 & io_fence_bit_21 &
-    io_fence_bit_22 & io_fence_bit_23 & io_fence_bit_24; // @[Library.scala 311:48]
-  wire  _io_eyield_T_27 = _io_eyield_T_24 & io_inst[6] & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 314:48]
-  wire  _io_eyield_T_29 = _io_eyield_T_27 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 311:48]
-  wire  _io_ectxsw_T_6 = _io_slli_T_4 & io_lui_bit_5 & io_lui_bit_6; // @[Library.scala 314:48]
-  wire  _io_ectxsw_T_24 = _io_ectxsw_T_6 & io_fcvtws_bit_7 & io_fcvtws_bit_8 & io_fcvtws_bit_9 & io_fcvtws_bit_10 &
-    io_fcvtws_bit_11 & io_fence_bit_12 & io_fence_bit_13 & io_fence_bit_14 & io_fence_bit_15 & io_fence_bit_16 &
-    io_jalr_bit_17 & io_jalr_bit_18 & io_jalr_bit_19 & io_fence_bit_20 & io_fence_bit_21 & io_fence_bit_22 &
-    io_fence_bit_23 & io_fence_bit_24; // @[Library.scala 311:48]
-  wire  _io_ectxsw_T_27 = _io_ectxsw_T_24 & io_inst[6] & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 314:48]
-  wire  _io_ectxsw_T_29 = _io_ectxsw_T_27 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 311:48]
-  wire  _io_mpause_T_24 = _io_fsub_T_4 & io_slli_bit_5 & io_slli_bit_6 & io_fcvtws_bit_7 & io_fcvtws_bit_8 &
-    io_fcvtws_bit_9 & io_fcvtws_bit_10 & io_fcvtws_bit_11 & io_fence_bit_12 & io_fence_bit_13 & io_fence_bit_14 &
+    io_fence_bit_22 & io_fence_bit_23 & io_fence_bit_24; // @[Library.scala 313:48]
+  wire  _io_mpause_T_27 = _io_mpause_T_24 & io_inst[6] & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 316:48]
+  wire  _io_mpause_T_29 = _io_mpause_T_27 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 313:48]
+  wire  _io_mret_T_3 = _io_fence_T_1 & io_lui_bit_2 & io_lui_bit_3; // @[Library.scala 316:48]
+  wire  _io_mret_T_9 = _io_mret_T_3 & io_slli_bit_4 & io_slli_bit_5 & io_slli_bit_6 & io_clz_bit_7 & io_clz_bit_8 &
+    io_clz_bit_9; // @[Library.scala 313:48]
+  wire  _io_mret_T_10 = _io_mret_T_9 & io_lui_bit_10; // @[Library.scala 316:48]
+  wire  _io_mret_T_24 = _io_mret_T_10 & io_clz_bit_11 & io_fence_bit_12 & io_fence_bit_13 & io_fence_bit_14 &
     io_fence_bit_15 & io_fence_bit_16 & io_jalr_bit_17 & io_jalr_bit_18 & io_jalr_bit_19 & io_fence_bit_20 &
-    io_fence_bit_21 & io_fence_bit_22 & io_fence_bit_23 & io_fence_bit_24; // @[Library.scala 311:48]
-  wire  _io_mpause_T_27 = _io_mpause_T_24 & io_inst[6] & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 314:48]
-  wire  _io_mpause_T_29 = _io_mpause_T_27 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 311:48]
-  wire  _io_mret_T_3 = _io_fence_T_1 & io_lui_bit_2 & io_lui_bit_3; // @[Library.scala 314:48]
-  wire  _io_mret_T_9 = _io_mret_T_3 & io_slli_bit_4 & io_slli_bit_5 & io_slli_bit_6 & io_fcvtws_bit_7 & io_fcvtws_bit_8
-     & io_fcvtws_bit_9; // @[Library.scala 311:48]
-  wire  _io_mret_T_10 = _io_mret_T_9 & io_lui_bit_10; // @[Library.scala 314:48]
-  wire  _io_mret_T_24 = _io_mret_T_10 & io_fcvtws_bit_11 & io_fence_bit_12 & io_fence_bit_13 & io_fence_bit_14 &
-    io_fence_bit_15 & io_fence_bit_16 & io_jalr_bit_17 & io_jalr_bit_18 & io_jalr_bit_19 & io_fence_bit_20 &
-    io_fence_bit_21 & io_fence_bit_22 & io_fence_bit_23 & io_fence_bit_24; // @[Library.scala 311:48]
-  wire  _io_mret_T_27 = _io_mret_T_24 & io_inst[6] & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 314:48]
-  wire  _io_mret_T_29 = _io_mret_T_27 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 311:48]
-  wire  _io_fencei_T_19 = _io_ecall_T_18 & io_lui_bit_19; // @[Library.scala 314:48]
+    io_fence_bit_21 & io_fence_bit_22 & io_fence_bit_23 & io_fence_bit_24; // @[Library.scala 313:48]
+  wire  _io_mret_T_27 = _io_mret_T_24 & io_inst[6] & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 316:48]
+  wire  _io_mret_T_29 = _io_mret_T_27 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 313:48]
+  wire  _io_fencei_T_19 = _io_ecall_T_18 & io_lui_bit_19; // @[Library.scala 316:48]
   wire  _io_fencei_T_27 = _io_fencei_T_19 & io_fence_bit_20 & io_fence_bit_21 & io_fence_bit_22 & io_fence_bit_23 &
-    io_fence_bit_24 & io_lui_bit_25 & io_auipc_bit_26 & io_jal_bit_27; // @[Library.scala 311:48]
-  wire  _io_flushat_T_16 = _io_mulhr_T_2 & io_fence_bit_3 & io_fcvtws_bit_7 & io_fcvtws_bit_8 & io_fcvtws_bit_9 &
-    io_fcvtws_bit_10 & io_fcvtws_bit_11 & io_jalr_bit_17 & io_jalr_bit_18 & io_jalr_bit_19 & io_fence_bit_20 &
-    io_fence_bit_21 & io_fence_bit_22 & io_fence_bit_23 & io_fence_bit_24; // @[Library.scala 311:48]
-  wire  _io_flushat_T_19 = _io_flushat_T_16 & io_inst[6] & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 314:48]
-  wire  _io_flushat_T_20 = _io_flushat_T_19 & io_lui_bit_28; // @[Library.scala 311:48]
-  wire  _io_flushat_T_23 = _io_flushat_T_20 & io_lui_bit_29 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 314:48]
-  wire  _io_flushall_T_21 = _io_mulhr_T_2 & io_fence_bit_3 & io_fcvtws_bit_7 & io_fcvtws_bit_8 & io_fcvtws_bit_9 &
-    io_fcvtws_bit_10 & io_fcvtws_bit_11 & io_fence_bit_12 & io_fence_bit_13 & io_fence_bit_14 & io_fence_bit_15 &
-    io_fence_bit_16 & io_jalr_bit_17 & io_jalr_bit_18 & io_jalr_bit_19 & io_fence_bit_20 & io_fence_bit_21 &
-    io_fence_bit_22 & io_fence_bit_23 & io_fence_bit_24; // @[Library.scala 311:48]
-  wire  _io_flushall_T_24 = _io_flushall_T_21 & io_inst[6] & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 314:48]
-  wire  _io_flushall_T_25 = _io_flushall_T_24 & io_lui_bit_28; // @[Library.scala 311:48]
-  wire [5:0] decoded_lo_lo_lo_lo = {io_mpause,io_mret,io_fencei,io_flushat,io_flushall,io_slog}; // @[Cat.scala 31:58]
-  wire [12:0] decoded_lo_lo_lo = {io_getvl,io_getmaxvl,io_ebreak,io_ecall,io_eexit,io_eyield,io_ectxsw,
-    decoded_lo_lo_lo_lo}; // @[Cat.scala 31:58]
-  wire [5:0] decoded_lo_lo_hi_lo = {io_max,io_maxu,io_viop,io_vfop,io_vld,io_vst}; // @[Cat.scala 31:58]
-  wire [25:0] decoded_lo_lo = {io_fmvwx,io_clb,io_clz,io_ctz,io_pcnt,io_min,io_minu,decoded_lo_lo_hi_lo,decoded_lo_lo_lo
-    }; // @[Cat.scala 31:58]
-  wire [5:0] decoded_lo_hi_lo_lo = {io_feq,io_flt,io_fle,io_fclass,io_fcvtsw,io_fcvtswu}; // @[Cat.scala 31:58]
-  wire [12:0] decoded_lo_hi_lo = {io_fsgnjn,io_fsgnjx,io_fmin,io_fmax,io_fcvtws,io_fcvtwus,io_fmvxw,decoded_lo_hi_lo_lo}
+    io_fence_bit_24 & io_lui_bit_25 & io_auipc_bit_26 & io_jal_bit_27; // @[Library.scala 313:48]
+  wire  _io_flushat_T_16 = _io_mulhr_T_2 & io_fence_bit_3 & io_clz_bit_7 & io_clz_bit_8 & io_clz_bit_9 & io_clz_bit_10
+     & io_clz_bit_11 & io_jalr_bit_17 & io_jalr_bit_18 & io_jalr_bit_19 & io_fence_bit_20 & io_fence_bit_21 &
+    io_fence_bit_22 & io_fence_bit_23 & io_fence_bit_24; // @[Library.scala 313:48]
+  wire  _io_flushat_T_19 = _io_flushat_T_16 & io_inst[6] & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 316:48]
+  wire  _io_flushat_T_20 = _io_flushat_T_19 & io_lui_bit_28; // @[Library.scala 313:48]
+  wire  _io_flushat_T_23 = _io_flushat_T_20 & io_lui_bit_29 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 316:48]
+  wire  _io_flushall_T_21 = _io_mulhr_T_2 & io_fence_bit_3 & io_clz_bit_7 & io_clz_bit_8 & io_clz_bit_9 & io_clz_bit_10
+     & io_clz_bit_11 & io_fence_bit_12 & io_fence_bit_13 & io_fence_bit_14 & io_fence_bit_15 & io_fence_bit_16 &
+    io_jalr_bit_17 & io_jalr_bit_18 & io_jalr_bit_19 & io_fence_bit_20 & io_fence_bit_21 & io_fence_bit_22 &
+    io_fence_bit_23 & io_fence_bit_24; // @[Library.scala 313:48]
+  wire  _io_flushall_T_24 = _io_flushall_T_21 & io_inst[6] & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 316:48]
+  wire  _io_flushall_T_25 = _io_flushall_T_24 & io_lui_bit_28; // @[Library.scala 313:48]
+  wire [9:0] decoded_lo_lo_hi = {io_minu,io_max,io_maxu,io_viop,io_vld,io_vst,io_getvl,io_getmaxvl,io_ebreak,io_ecall}; // @[Cat.scala 31:58]
+  wire [18:0] decoded_lo_lo = {decoded_lo_lo_hi,io_eexit,io_eyield,io_ectxsw,io_mpause,io_mret,io_fencei,io_flushat,
+    io_flushall,io_slog}; // @[Cat.scala 31:58]
+  wire [9:0] decoded_lo_hi_hi = {io_srl,io_sra,io_mul,io_mulh,io_mulhsu,io_mulhu,io_mulhr,io_mulhsur,io_mulhur,io_dmulh}
     ; // @[Cat.scala 31:58]
-  wire [5:0] decoded_lo_hi_hi_lo = {io_fadd,io_fsub,io_fmul,io_fdiv,io_fsqrt,io_fsgnj}; // @[Cat.scala 31:58]
-  wire [51:0] decoded_lo = {io_remu,io_flw,io_fsw,io_fmadd,io_fmsub,io_fnmsub,io_fnmadd,decoded_lo_hi_hi_lo,
-    decoded_lo_hi_lo,decoded_lo_lo}; // @[Cat.scala 31:58]
-  wire [5:0] decoded_hi_lo_lo_lo = {io_mulhur,io_dmulh,io_dmulhr,io_div,io_divu,io_rem}; // @[Cat.scala 31:58]
-  wire [12:0] decoded_hi_lo_lo = {io_sra,io_mul,io_mulh,io_mulhsu,io_mulhu,io_mulhr,io_mulhsur,decoded_hi_lo_lo_lo}; // @[Cat.scala 31:58]
-  wire [5:0] decoded_hi_lo_hi_lo = {io_and,io_slli,io_srli,io_srai,io_sll,io_srl}; // @[Cat.scala 31:58]
-  wire [25:0] decoded_hi_lo = {io_andi,io_add,io_sub,io_slt,io_sltu,io_xor,io_or,decoded_hi_lo_hi_lo,decoded_hi_lo_lo}; // @[Cat.scala 31:58]
-  wire [5:0] decoded_hi_hi_lo_lo = {io_fence,io_addi,io_slti,io_sltiu,io_xori,io_ori}; // @[Cat.scala 31:58]
-  wire [12:0] decoded_hi_hi_lo = {io_lh,io_lw,io_lbu,io_lhu,io_sb,io_sh,io_sw,decoded_hi_hi_lo_lo}; // @[Cat.scala 31:58]
-  wire [6:0] decoded_hi_hi_hi_lo = {io_bge,io_bltu,io_bgeu,io_csrrw,io_csrrs,io_csrrc,io_lb}; // @[Cat.scala 31:58]
-  wire [52:0] decoded_hi = {io_lui,io_auipc,io_jal,io_jalr,io_beq,io_bne,io_blt,decoded_hi_hi_hi_lo,decoded_hi_hi_lo,
-    decoded_hi_lo}; // @[Cat.scala 31:58]
-  wire [104:0] decoded = {decoded_hi,decoded_lo}; // @[Cat.scala 31:58]
-  wire  io_undef_value__52 = decoded[104]; // @[Library.scala 182:26]
+  wire [18:0] decoded_lo_hi = {decoded_lo_hi_hi,io_dmulhr,io_div,io_divu,io_rem,io_remu,io_clz,io_ctz,io_pcnt,io_min}; // @[Cat.scala 31:58]
+  wire [9:0] decoded_hi_lo_hi = {io_sw,io_fence,io_addi,io_slti,io_sltiu,io_xori,io_ori,io_andi,io_add,io_sub}; // @[Cat.scala 31:58]
+  wire [18:0] decoded_hi_lo = {decoded_hi_lo_hi,io_slt,io_sltu,io_xor,io_or,io_and,io_slli,io_srli,io_srai,io_sll}; // @[Cat.scala 31:58]
+  wire [9:0] decoded_hi_hi_lo = {io_csrrw,io_csrrs,io_csrrc,io_lb,io_lh,io_lw,io_lbu,io_lhu,io_sb,io_sh}; // @[Cat.scala 31:58]
+  wire [9:0] decoded_hi_hi_hi = {io_lui,io_auipc,io_jal,io_jalr,io_beq,io_bne,io_blt,io_bge,io_bltu,io_bgeu}; // @[Cat.scala 31:58]
+  wire [76:0] decoded = {decoded_hi_hi_hi,decoded_hi_hi_lo,decoded_hi_lo,decoded_lo_hi,decoded_lo_lo}; // @[Cat.scala 31:58]
+  wire  io_undef_value__38 = decoded[76]; // @[Library.scala 182:26]
   wire  io_undef_value__0 = decoded[0] | decoded[1]; // @[Library.scala 194:39]
   wire  io_undef_value__1 = decoded[2] | decoded[3]; // @[Library.scala 194:39]
   wire  io_undef_value__2 = decoded[4] | decoded[5]; // @[Library.scala 194:39]
@@ -8278,20 +8088,6 @@
   wire  io_undef_value__35 = decoded[70] | decoded[71]; // @[Library.scala 194:39]
   wire  io_undef_value__36 = decoded[72] | decoded[73]; // @[Library.scala 194:39]
   wire  io_undef_value__37 = decoded[74] | decoded[75]; // @[Library.scala 194:39]
-  wire  io_undef_value__38 = decoded[76] | decoded[77]; // @[Library.scala 194:39]
-  wire  io_undef_value__39 = decoded[78] | decoded[79]; // @[Library.scala 194:39]
-  wire  io_undef_value__40 = decoded[80] | decoded[81]; // @[Library.scala 194:39]
-  wire  io_undef_value__41 = decoded[82] | decoded[83]; // @[Library.scala 194:39]
-  wire  io_undef_value__42 = decoded[84] | decoded[85]; // @[Library.scala 194:39]
-  wire  io_undef_value__43 = decoded[86] | decoded[87]; // @[Library.scala 194:39]
-  wire  io_undef_value__44 = decoded[88] | decoded[89]; // @[Library.scala 194:39]
-  wire  io_undef_value__45 = decoded[90] | decoded[91]; // @[Library.scala 194:39]
-  wire  io_undef_value__46 = decoded[92] | decoded[93]; // @[Library.scala 194:39]
-  wire  io_undef_value__47 = decoded[94] | decoded[95]; // @[Library.scala 194:39]
-  wire  io_undef_value__48 = decoded[96] | decoded[97]; // @[Library.scala 194:39]
-  wire  io_undef_value__49 = decoded[98] | decoded[99]; // @[Library.scala 194:39]
-  wire  io_undef_value__50 = decoded[100] | decoded[101]; // @[Library.scala 194:39]
-  wire  io_undef_value__51 = decoded[102] | decoded[103]; // @[Library.scala 194:39]
   wire  io_undef_value_1_0 = io_undef_value__0 | io_undef_value__1; // @[Library.scala 194:39]
   wire  io_undef_value_1_1 = io_undef_value__2 | io_undef_value__3; // @[Library.scala 194:39]
   wire  io_undef_value_1_2 = io_undef_value__4 | io_undef_value__5; // @[Library.scala 194:39]
@@ -8311,13 +8107,6 @@
   wire  io_undef_value_1_16 = io_undef_value__32 | io_undef_value__33; // @[Library.scala 194:39]
   wire  io_undef_value_1_17 = io_undef_value__34 | io_undef_value__35; // @[Library.scala 194:39]
   wire  io_undef_value_1_18 = io_undef_value__36 | io_undef_value__37; // @[Library.scala 194:39]
-  wire  io_undef_value_1_19 = io_undef_value__38 | io_undef_value__39; // @[Library.scala 194:39]
-  wire  io_undef_value_1_20 = io_undef_value__40 | io_undef_value__41; // @[Library.scala 194:39]
-  wire  io_undef_value_1_21 = io_undef_value__42 | io_undef_value__43; // @[Library.scala 194:39]
-  wire  io_undef_value_1_22 = io_undef_value__44 | io_undef_value__45; // @[Library.scala 194:39]
-  wire  io_undef_value_1_23 = io_undef_value__46 | io_undef_value__47; // @[Library.scala 194:39]
-  wire  io_undef_value_1_24 = io_undef_value__48 | io_undef_value__49; // @[Library.scala 194:39]
-  wire  io_undef_value_1_25 = io_undef_value__50 | io_undef_value__51; // @[Library.scala 194:39]
   wire  io_undef_value_2_0 = io_undef_value_1_0 | io_undef_value_1_1; // @[Library.scala 194:39]
   wire  io_undef_value_2_1 = io_undef_value_1_2 | io_undef_value_1_3; // @[Library.scala 194:39]
   wire  io_undef_value_2_2 = io_undef_value_1_4 | io_undef_value_1_5; // @[Library.scala 194:39]
@@ -8327,283 +8116,201 @@
   wire  io_undef_value_2_6 = io_undef_value_1_12 | io_undef_value_1_13; // @[Library.scala 194:39]
   wire  io_undef_value_2_7 = io_undef_value_1_14 | io_undef_value_1_15; // @[Library.scala 194:39]
   wire  io_undef_value_2_8 = io_undef_value_1_16 | io_undef_value_1_17; // @[Library.scala 194:39]
-  wire  io_undef_value_2_9 = io_undef_value_1_18 | io_undef_value_1_19; // @[Library.scala 194:39]
-  wire  io_undef_value_2_10 = io_undef_value_1_20 | io_undef_value_1_21; // @[Library.scala 194:39]
-  wire  io_undef_value_2_11 = io_undef_value_1_22 | io_undef_value_1_23; // @[Library.scala 194:39]
-  wire  io_undef_value_2_12 = io_undef_value_1_24 | io_undef_value_1_25; // @[Library.scala 194:39]
+  wire  io_undef_value_2_9 = io_undef_value_1_18 | io_undef_value__38; // @[Library.scala 194:39]
   wire  io_undef_value_3_0 = io_undef_value_2_0 | io_undef_value_2_1; // @[Library.scala 194:39]
   wire  io_undef_value_3_1 = io_undef_value_2_2 | io_undef_value_2_3; // @[Library.scala 194:39]
   wire  io_undef_value_3_2 = io_undef_value_2_4 | io_undef_value_2_5; // @[Library.scala 194:39]
   wire  io_undef_value_3_3 = io_undef_value_2_6 | io_undef_value_2_7; // @[Library.scala 194:39]
   wire  io_undef_value_3_4 = io_undef_value_2_8 | io_undef_value_2_9; // @[Library.scala 194:39]
-  wire  io_undef_value_3_5 = io_undef_value_2_10 | io_undef_value_2_11; // @[Library.scala 194:39]
-  wire  io_undef_value_3_6 = io_undef_value_2_12 | io_undef_value__52; // @[Library.scala 194:39]
   wire  io_undef_value_4_0 = io_undef_value_3_0 | io_undef_value_3_1; // @[Library.scala 194:39]
   wire  io_undef_value_4_1 = io_undef_value_3_2 | io_undef_value_3_3; // @[Library.scala 194:39]
-  wire  io_undef_value_4_2 = io_undef_value_3_4 | io_undef_value_3_5; // @[Library.scala 194:39]
   wire  io_undef_value_5_0 = io_undef_value_4_0 | io_undef_value_4_1; // @[Library.scala 194:39]
-  wire  io_undef_value_5_1 = io_undef_value_4_2 | io_undef_value_3_6; // @[Library.scala 194:39]
-  wire  io_undef_value_6_0 = io_undef_value_5_0 | io_undef_value_5_1; // @[Library.scala 194:39]
-  reg  onehot_failed; // @[Decode.scala 813:30]
-  wire  _T_2 = ~reset; // @[Decode.scala 814:9]
-  wire [1:0] _onehot_decode_T_105 = decoded[1] + decoded[2]; // @[Bitwise.scala 48:55]
-  wire [1:0] _GEN_1 = {{1'd0}, decoded[0]}; // @[Bitwise.scala 48:55]
-  wire [2:0] _onehot_decode_T_107 = _GEN_1 + _onehot_decode_T_105; // @[Bitwise.scala 48:55]
-  wire [1:0] _onehot_decode_T_109 = decoded[4] + decoded[5]; // @[Bitwise.scala 48:55]
-  wire [1:0] _GEN_2 = {{1'd0}, decoded[3]}; // @[Bitwise.scala 48:55]
-  wire [2:0] _onehot_decode_T_111 = _GEN_2 + _onehot_decode_T_109; // @[Bitwise.scala 48:55]
-  wire [2:0] _onehot_decode_T_113 = _onehot_decode_T_107[1:0] + _onehot_decode_T_111[1:0]; // @[Bitwise.scala 48:55]
-  wire [1:0] _onehot_decode_T_115 = decoded[7] + decoded[8]; // @[Bitwise.scala 48:55]
-  wire [1:0] _GEN_3 = {{1'd0}, decoded[6]}; // @[Bitwise.scala 48:55]
-  wire [2:0] _onehot_decode_T_117 = _GEN_3 + _onehot_decode_T_115; // @[Bitwise.scala 48:55]
-  wire [1:0] _onehot_decode_T_119 = decoded[9] + decoded[10]; // @[Bitwise.scala 48:55]
-  wire [1:0] _onehot_decode_T_121 = decoded[11] + decoded[12]; // @[Bitwise.scala 48:55]
-  wire [2:0] _onehot_decode_T_123 = _onehot_decode_T_119 + _onehot_decode_T_121; // @[Bitwise.scala 48:55]
-  wire [2:0] _GEN_4 = {{1'd0}, _onehot_decode_T_117[1:0]}; // @[Bitwise.scala 48:55]
-  wire [3:0] _onehot_decode_T_125 = _GEN_4 + _onehot_decode_T_123; // @[Bitwise.scala 48:55]
-  wire [3:0] _onehot_decode_T_127 = _onehot_decode_T_113 + _onehot_decode_T_125[2:0]; // @[Bitwise.scala 48:55]
-  wire [1:0] _onehot_decode_T_129 = decoded[14] + decoded[15]; // @[Bitwise.scala 48:55]
-  wire [1:0] _GEN_5 = {{1'd0}, decoded[13]}; // @[Bitwise.scala 48:55]
-  wire [2:0] _onehot_decode_T_131 = _GEN_5 + _onehot_decode_T_129; // @[Bitwise.scala 48:55]
-  wire [1:0] _onehot_decode_T_133 = decoded[17] + decoded[18]; // @[Bitwise.scala 48:55]
-  wire [1:0] _GEN_6 = {{1'd0}, decoded[16]}; // @[Bitwise.scala 48:55]
-  wire [2:0] _onehot_decode_T_135 = _GEN_6 + _onehot_decode_T_133; // @[Bitwise.scala 48:55]
-  wire [2:0] _onehot_decode_T_137 = _onehot_decode_T_131[1:0] + _onehot_decode_T_135[1:0]; // @[Bitwise.scala 48:55]
-  wire [1:0] _onehot_decode_T_139 = decoded[20] + decoded[21]; // @[Bitwise.scala 48:55]
-  wire [1:0] _GEN_7 = {{1'd0}, decoded[19]}; // @[Bitwise.scala 48:55]
-  wire [2:0] _onehot_decode_T_141 = _GEN_7 + _onehot_decode_T_139; // @[Bitwise.scala 48:55]
-  wire [1:0] _onehot_decode_T_143 = decoded[22] + decoded[23]; // @[Bitwise.scala 48:55]
-  wire [1:0] _onehot_decode_T_145 = decoded[24] + decoded[25]; // @[Bitwise.scala 48:55]
-  wire [2:0] _onehot_decode_T_147 = _onehot_decode_T_143 + _onehot_decode_T_145; // @[Bitwise.scala 48:55]
-  wire [2:0] _GEN_8 = {{1'd0}, _onehot_decode_T_141[1:0]}; // @[Bitwise.scala 48:55]
-  wire [3:0] _onehot_decode_T_149 = _GEN_8 + _onehot_decode_T_147; // @[Bitwise.scala 48:55]
-  wire [3:0] _onehot_decode_T_151 = _onehot_decode_T_137 + _onehot_decode_T_149[2:0]; // @[Bitwise.scala 48:55]
-  wire [4:0] _onehot_decode_T_153 = _onehot_decode_T_127 + _onehot_decode_T_151; // @[Bitwise.scala 48:55]
-  wire [1:0] _onehot_decode_T_155 = decoded[27] + decoded[28]; // @[Bitwise.scala 48:55]
-  wire [1:0] _GEN_9 = {{1'd0}, decoded[26]}; // @[Bitwise.scala 48:55]
-  wire [2:0] _onehot_decode_T_157 = _GEN_9 + _onehot_decode_T_155; // @[Bitwise.scala 48:55]
-  wire [1:0] _onehot_decode_T_159 = decoded[30] + decoded[31]; // @[Bitwise.scala 48:55]
-  wire [1:0] _GEN_10 = {{1'd0}, decoded[29]}; // @[Bitwise.scala 48:55]
-  wire [2:0] _onehot_decode_T_161 = _GEN_10 + _onehot_decode_T_159; // @[Bitwise.scala 48:55]
-  wire [2:0] _onehot_decode_T_163 = _onehot_decode_T_157[1:0] + _onehot_decode_T_161[1:0]; // @[Bitwise.scala 48:55]
-  wire [1:0] _onehot_decode_T_165 = decoded[33] + decoded[34]; // @[Bitwise.scala 48:55]
-  wire [1:0] _GEN_11 = {{1'd0}, decoded[32]}; // @[Bitwise.scala 48:55]
-  wire [2:0] _onehot_decode_T_167 = _GEN_11 + _onehot_decode_T_165; // @[Bitwise.scala 48:55]
-  wire [1:0] _onehot_decode_T_169 = decoded[35] + decoded[36]; // @[Bitwise.scala 48:55]
-  wire [1:0] _onehot_decode_T_171 = decoded[37] + decoded[38]; // @[Bitwise.scala 48:55]
-  wire [2:0] _onehot_decode_T_173 = _onehot_decode_T_169 + _onehot_decode_T_171; // @[Bitwise.scala 48:55]
-  wire [2:0] _GEN_12 = {{1'd0}, _onehot_decode_T_167[1:0]}; // @[Bitwise.scala 48:55]
-  wire [3:0] _onehot_decode_T_175 = _GEN_12 + _onehot_decode_T_173; // @[Bitwise.scala 48:55]
-  wire [3:0] _onehot_decode_T_177 = _onehot_decode_T_163 + _onehot_decode_T_175[2:0]; // @[Bitwise.scala 48:55]
-  wire [1:0] _onehot_decode_T_179 = decoded[40] + decoded[41]; // @[Bitwise.scala 48:55]
-  wire [1:0] _GEN_13 = {{1'd0}, decoded[39]}; // @[Bitwise.scala 48:55]
-  wire [2:0] _onehot_decode_T_181 = _GEN_13 + _onehot_decode_T_179; // @[Bitwise.scala 48:55]
-  wire [1:0] _onehot_decode_T_183 = decoded[43] + decoded[44]; // @[Bitwise.scala 48:55]
-  wire [1:0] _GEN_14 = {{1'd0}, decoded[42]}; // @[Bitwise.scala 48:55]
-  wire [2:0] _onehot_decode_T_185 = _GEN_14 + _onehot_decode_T_183; // @[Bitwise.scala 48:55]
-  wire [2:0] _onehot_decode_T_187 = _onehot_decode_T_181[1:0] + _onehot_decode_T_185[1:0]; // @[Bitwise.scala 48:55]
-  wire [1:0] _onehot_decode_T_189 = decoded[46] + decoded[47]; // @[Bitwise.scala 48:55]
-  wire [1:0] _GEN_15 = {{1'd0}, decoded[45]}; // @[Bitwise.scala 48:55]
-  wire [2:0] _onehot_decode_T_191 = _GEN_15 + _onehot_decode_T_189; // @[Bitwise.scala 48:55]
-  wire [1:0] _onehot_decode_T_193 = decoded[48] + decoded[49]; // @[Bitwise.scala 48:55]
-  wire [1:0] _onehot_decode_T_195 = decoded[50] + decoded[51]; // @[Bitwise.scala 48:55]
-  wire [2:0] _onehot_decode_T_197 = _onehot_decode_T_193 + _onehot_decode_T_195; // @[Bitwise.scala 48:55]
-  wire [2:0] _GEN_16 = {{1'd0}, _onehot_decode_T_191[1:0]}; // @[Bitwise.scala 48:55]
-  wire [3:0] _onehot_decode_T_199 = _GEN_16 + _onehot_decode_T_197; // @[Bitwise.scala 48:55]
-  wire [3:0] _onehot_decode_T_201 = _onehot_decode_T_187 + _onehot_decode_T_199[2:0]; // @[Bitwise.scala 48:55]
-  wire [4:0] _onehot_decode_T_203 = _onehot_decode_T_177 + _onehot_decode_T_201; // @[Bitwise.scala 48:55]
-  wire [5:0] _onehot_decode_T_205 = _onehot_decode_T_153 + _onehot_decode_T_203; // @[Bitwise.scala 48:55]
-  wire [1:0] _onehot_decode_T_207 = decoded[53] + decoded[54]; // @[Bitwise.scala 48:55]
-  wire [1:0] _GEN_17 = {{1'd0}, decoded[52]}; // @[Bitwise.scala 48:55]
-  wire [2:0] _onehot_decode_T_209 = _GEN_17 + _onehot_decode_T_207; // @[Bitwise.scala 48:55]
-  wire [1:0] _onehot_decode_T_211 = decoded[56] + decoded[57]; // @[Bitwise.scala 48:55]
-  wire [1:0] _GEN_18 = {{1'd0}, decoded[55]}; // @[Bitwise.scala 48:55]
-  wire [2:0] _onehot_decode_T_213 = _GEN_18 + _onehot_decode_T_211; // @[Bitwise.scala 48:55]
-  wire [2:0] _onehot_decode_T_215 = _onehot_decode_T_209[1:0] + _onehot_decode_T_213[1:0]; // @[Bitwise.scala 48:55]
-  wire [1:0] _onehot_decode_T_217 = decoded[59] + decoded[60]; // @[Bitwise.scala 48:55]
-  wire [1:0] _GEN_19 = {{1'd0}, decoded[58]}; // @[Bitwise.scala 48:55]
-  wire [2:0] _onehot_decode_T_219 = _GEN_19 + _onehot_decode_T_217; // @[Bitwise.scala 48:55]
-  wire [1:0] _onehot_decode_T_221 = decoded[61] + decoded[62]; // @[Bitwise.scala 48:55]
-  wire [1:0] _onehot_decode_T_223 = decoded[63] + decoded[64]; // @[Bitwise.scala 48:55]
-  wire [2:0] _onehot_decode_T_225 = _onehot_decode_T_221 + _onehot_decode_T_223; // @[Bitwise.scala 48:55]
-  wire [2:0] _GEN_20 = {{1'd0}, _onehot_decode_T_219[1:0]}; // @[Bitwise.scala 48:55]
-  wire [3:0] _onehot_decode_T_227 = _GEN_20 + _onehot_decode_T_225; // @[Bitwise.scala 48:55]
-  wire [3:0] _onehot_decode_T_229 = _onehot_decode_T_215 + _onehot_decode_T_227[2:0]; // @[Bitwise.scala 48:55]
-  wire [1:0] _onehot_decode_T_231 = decoded[66] + decoded[67]; // @[Bitwise.scala 48:55]
-  wire [1:0] _GEN_21 = {{1'd0}, decoded[65]}; // @[Bitwise.scala 48:55]
-  wire [2:0] _onehot_decode_T_233 = _GEN_21 + _onehot_decode_T_231; // @[Bitwise.scala 48:55]
-  wire [1:0] _onehot_decode_T_235 = decoded[69] + decoded[70]; // @[Bitwise.scala 48:55]
-  wire [1:0] _GEN_22 = {{1'd0}, decoded[68]}; // @[Bitwise.scala 48:55]
-  wire [2:0] _onehot_decode_T_237 = _GEN_22 + _onehot_decode_T_235; // @[Bitwise.scala 48:55]
-  wire [2:0] _onehot_decode_T_239 = _onehot_decode_T_233[1:0] + _onehot_decode_T_237[1:0]; // @[Bitwise.scala 48:55]
-  wire [1:0] _onehot_decode_T_241 = decoded[72] + decoded[73]; // @[Bitwise.scala 48:55]
-  wire [1:0] _GEN_23 = {{1'd0}, decoded[71]}; // @[Bitwise.scala 48:55]
-  wire [2:0] _onehot_decode_T_243 = _GEN_23 + _onehot_decode_T_241; // @[Bitwise.scala 48:55]
-  wire [1:0] _onehot_decode_T_245 = decoded[74] + decoded[75]; // @[Bitwise.scala 48:55]
-  wire [1:0] _onehot_decode_T_247 = decoded[76] + decoded[77]; // @[Bitwise.scala 48:55]
-  wire [2:0] _onehot_decode_T_249 = _onehot_decode_T_245 + _onehot_decode_T_247; // @[Bitwise.scala 48:55]
-  wire [2:0] _GEN_24 = {{1'd0}, _onehot_decode_T_243[1:0]}; // @[Bitwise.scala 48:55]
-  wire [3:0] _onehot_decode_T_251 = _GEN_24 + _onehot_decode_T_249; // @[Bitwise.scala 48:55]
-  wire [3:0] _onehot_decode_T_253 = _onehot_decode_T_239 + _onehot_decode_T_251[2:0]; // @[Bitwise.scala 48:55]
-  wire [4:0] _onehot_decode_T_255 = _onehot_decode_T_229 + _onehot_decode_T_253; // @[Bitwise.scala 48:55]
-  wire [1:0] _onehot_decode_T_257 = decoded[79] + decoded[80]; // @[Bitwise.scala 48:55]
-  wire [1:0] _GEN_25 = {{1'd0}, decoded[78]}; // @[Bitwise.scala 48:55]
-  wire [2:0] _onehot_decode_T_259 = _GEN_25 + _onehot_decode_T_257; // @[Bitwise.scala 48:55]
-  wire [1:0] _onehot_decode_T_261 = decoded[82] + decoded[83]; // @[Bitwise.scala 48:55]
-  wire [1:0] _GEN_26 = {{1'd0}, decoded[81]}; // @[Bitwise.scala 48:55]
-  wire [2:0] _onehot_decode_T_263 = _GEN_26 + _onehot_decode_T_261; // @[Bitwise.scala 48:55]
-  wire [2:0] _onehot_decode_T_265 = _onehot_decode_T_259[1:0] + _onehot_decode_T_263[1:0]; // @[Bitwise.scala 48:55]
-  wire [1:0] _onehot_decode_T_267 = decoded[85] + decoded[86]; // @[Bitwise.scala 48:55]
-  wire [1:0] _GEN_27 = {{1'd0}, decoded[84]}; // @[Bitwise.scala 48:55]
-  wire [2:0] _onehot_decode_T_269 = _GEN_27 + _onehot_decode_T_267; // @[Bitwise.scala 48:55]
-  wire [1:0] _onehot_decode_T_271 = decoded[87] + decoded[88]; // @[Bitwise.scala 48:55]
-  wire [1:0] _onehot_decode_T_273 = decoded[89] + decoded[90]; // @[Bitwise.scala 48:55]
-  wire [2:0] _onehot_decode_T_275 = _onehot_decode_T_271 + _onehot_decode_T_273; // @[Bitwise.scala 48:55]
-  wire [2:0] _GEN_28 = {{1'd0}, _onehot_decode_T_269[1:0]}; // @[Bitwise.scala 48:55]
-  wire [3:0] _onehot_decode_T_277 = _GEN_28 + _onehot_decode_T_275; // @[Bitwise.scala 48:55]
-  wire [3:0] _onehot_decode_T_279 = _onehot_decode_T_265 + _onehot_decode_T_277[2:0]; // @[Bitwise.scala 48:55]
-  wire [1:0] _onehot_decode_T_281 = decoded[92] + decoded[93]; // @[Bitwise.scala 48:55]
-  wire [1:0] _GEN_29 = {{1'd0}, decoded[91]}; // @[Bitwise.scala 48:55]
-  wire [2:0] _onehot_decode_T_283 = _GEN_29 + _onehot_decode_T_281; // @[Bitwise.scala 48:55]
-  wire [1:0] _onehot_decode_T_285 = decoded[94] + decoded[95]; // @[Bitwise.scala 48:55]
-  wire [1:0] _onehot_decode_T_287 = decoded[96] + decoded[97]; // @[Bitwise.scala 48:55]
-  wire [2:0] _onehot_decode_T_289 = _onehot_decode_T_285 + _onehot_decode_T_287; // @[Bitwise.scala 48:55]
-  wire [2:0] _GEN_30 = {{1'd0}, _onehot_decode_T_283[1:0]}; // @[Bitwise.scala 48:55]
-  wire [3:0] _onehot_decode_T_291 = _GEN_30 + _onehot_decode_T_289; // @[Bitwise.scala 48:55]
-  wire [1:0] _onehot_decode_T_293 = decoded[99] + decoded[100]; // @[Bitwise.scala 48:55]
-  wire [1:0] _GEN_31 = {{1'd0}, decoded[98]}; // @[Bitwise.scala 48:55]
-  wire [2:0] _onehot_decode_T_295 = _GEN_31 + _onehot_decode_T_293; // @[Bitwise.scala 48:55]
-  wire [1:0] _onehot_decode_T_297 = decoded[101] + decoded[102]; // @[Bitwise.scala 48:55]
-  wire [1:0] _onehot_decode_T_299 = decoded[103] + io_undef_value__52; // @[Bitwise.scala 48:55]
-  wire [2:0] _onehot_decode_T_301 = _onehot_decode_T_297 + _onehot_decode_T_299; // @[Bitwise.scala 48:55]
-  wire [2:0] _GEN_32 = {{1'd0}, _onehot_decode_T_295[1:0]}; // @[Bitwise.scala 48:55]
-  wire [3:0] _onehot_decode_T_303 = _GEN_32 + _onehot_decode_T_301; // @[Bitwise.scala 48:55]
-  wire [3:0] _onehot_decode_T_305 = _onehot_decode_T_291[2:0] + _onehot_decode_T_303[2:0]; // @[Bitwise.scala 48:55]
-  wire [4:0] _onehot_decode_T_307 = _onehot_decode_T_279 + _onehot_decode_T_305; // @[Bitwise.scala 48:55]
-  wire [5:0] _onehot_decode_T_309 = _onehot_decode_T_255 + _onehot_decode_T_307; // @[Bitwise.scala 48:55]
-  wire [6:0] onehot_decode = _onehot_decode_T_205 + _onehot_decode_T_309; // @[Bitwise.scala 48:55]
-  wire [6:0] _GEN_33 = {{6'd0}, io_undef}; // @[Decode.scala 817:24]
-  wire [6:0] _T_5 = onehot_decode + _GEN_33; // @[Decode.scala 817:24]
-  wire  _T_6 = _T_5 != 7'h1; // @[Decode.scala 817:36]
+  wire  io_undef_value_6_0 = io_undef_value_5_0 | io_undef_value_3_4; // @[Library.scala 194:39]
+  reg  onehot_failed; // @[Decode.scala 651:30]
+  wire  _T_2 = ~reset; // @[Decode.scala 652:9]
+  wire [1:0] _onehot_decode_T_77 = decoded[0] + decoded[1]; // @[Bitwise.scala 48:55]
+  wire [1:0] _onehot_decode_T_79 = decoded[2] + decoded[3]; // @[Bitwise.scala 48:55]
+  wire [2:0] _onehot_decode_T_81 = _onehot_decode_T_77 + _onehot_decode_T_79; // @[Bitwise.scala 48:55]
+  wire [1:0] _onehot_decode_T_83 = decoded[4] + decoded[5]; // @[Bitwise.scala 48:55]
+  wire [1:0] _onehot_decode_T_85 = decoded[7] + decoded[8]; // @[Bitwise.scala 48:55]
+  wire [1:0] _GEN_1 = {{1'd0}, decoded[6]}; // @[Bitwise.scala 48:55]
+  wire [2:0] _onehot_decode_T_87 = _GEN_1 + _onehot_decode_T_85; // @[Bitwise.scala 48:55]
+  wire [2:0] _onehot_decode_T_89 = _onehot_decode_T_83 + _onehot_decode_T_87[1:0]; // @[Bitwise.scala 48:55]
+  wire [3:0] _onehot_decode_T_91 = _onehot_decode_T_81 + _onehot_decode_T_89; // @[Bitwise.scala 48:55]
+  wire [1:0] _onehot_decode_T_93 = decoded[9] + decoded[10]; // @[Bitwise.scala 48:55]
+  wire [1:0] _onehot_decode_T_95 = decoded[12] + decoded[13]; // @[Bitwise.scala 48:55]
+  wire [1:0] _GEN_2 = {{1'd0}, decoded[11]}; // @[Bitwise.scala 48:55]
+  wire [2:0] _onehot_decode_T_97 = _GEN_2 + _onehot_decode_T_95; // @[Bitwise.scala 48:55]
+  wire [2:0] _onehot_decode_T_99 = _onehot_decode_T_93 + _onehot_decode_T_97[1:0]; // @[Bitwise.scala 48:55]
+  wire [1:0] _onehot_decode_T_101 = decoded[14] + decoded[15]; // @[Bitwise.scala 48:55]
+  wire [1:0] _onehot_decode_T_103 = decoded[17] + decoded[18]; // @[Bitwise.scala 48:55]
+  wire [1:0] _GEN_3 = {{1'd0}, decoded[16]}; // @[Bitwise.scala 48:55]
+  wire [2:0] _onehot_decode_T_105 = _GEN_3 + _onehot_decode_T_103; // @[Bitwise.scala 48:55]
+  wire [2:0] _onehot_decode_T_107 = _onehot_decode_T_101 + _onehot_decode_T_105[1:0]; // @[Bitwise.scala 48:55]
+  wire [3:0] _onehot_decode_T_109 = _onehot_decode_T_99 + _onehot_decode_T_107; // @[Bitwise.scala 48:55]
+  wire [4:0] _onehot_decode_T_111 = _onehot_decode_T_91 + _onehot_decode_T_109; // @[Bitwise.scala 48:55]
+  wire [1:0] _onehot_decode_T_113 = decoded[19] + decoded[20]; // @[Bitwise.scala 48:55]
+  wire [1:0] _onehot_decode_T_115 = decoded[21] + decoded[22]; // @[Bitwise.scala 48:55]
+  wire [2:0] _onehot_decode_T_117 = _onehot_decode_T_113 + _onehot_decode_T_115; // @[Bitwise.scala 48:55]
+  wire [1:0] _onehot_decode_T_119 = decoded[23] + decoded[24]; // @[Bitwise.scala 48:55]
+  wire [1:0] _onehot_decode_T_121 = decoded[26] + decoded[27]; // @[Bitwise.scala 48:55]
+  wire [1:0] _GEN_4 = {{1'd0}, decoded[25]}; // @[Bitwise.scala 48:55]
+  wire [2:0] _onehot_decode_T_123 = _GEN_4 + _onehot_decode_T_121; // @[Bitwise.scala 48:55]
+  wire [2:0] _onehot_decode_T_125 = _onehot_decode_T_119 + _onehot_decode_T_123[1:0]; // @[Bitwise.scala 48:55]
+  wire [3:0] _onehot_decode_T_127 = _onehot_decode_T_117 + _onehot_decode_T_125; // @[Bitwise.scala 48:55]
+  wire [1:0] _onehot_decode_T_129 = decoded[28] + decoded[29]; // @[Bitwise.scala 48:55]
+  wire [1:0] _onehot_decode_T_131 = decoded[31] + decoded[32]; // @[Bitwise.scala 48:55]
+  wire [1:0] _GEN_5 = {{1'd0}, decoded[30]}; // @[Bitwise.scala 48:55]
+  wire [2:0] _onehot_decode_T_133 = _GEN_5 + _onehot_decode_T_131; // @[Bitwise.scala 48:55]
+  wire [2:0] _onehot_decode_T_135 = _onehot_decode_T_129 + _onehot_decode_T_133[1:0]; // @[Bitwise.scala 48:55]
+  wire [1:0] _onehot_decode_T_137 = decoded[33] + decoded[34]; // @[Bitwise.scala 48:55]
+  wire [1:0] _onehot_decode_T_139 = decoded[36] + decoded[37]; // @[Bitwise.scala 48:55]
+  wire [1:0] _GEN_6 = {{1'd0}, decoded[35]}; // @[Bitwise.scala 48:55]
+  wire [2:0] _onehot_decode_T_141 = _GEN_6 + _onehot_decode_T_139; // @[Bitwise.scala 48:55]
+  wire [2:0] _onehot_decode_T_143 = _onehot_decode_T_137 + _onehot_decode_T_141[1:0]; // @[Bitwise.scala 48:55]
+  wire [3:0] _onehot_decode_T_145 = _onehot_decode_T_135 + _onehot_decode_T_143; // @[Bitwise.scala 48:55]
+  wire [4:0] _onehot_decode_T_147 = _onehot_decode_T_127 + _onehot_decode_T_145; // @[Bitwise.scala 48:55]
+  wire [5:0] _onehot_decode_T_149 = _onehot_decode_T_111 + _onehot_decode_T_147; // @[Bitwise.scala 48:55]
+  wire [1:0] _onehot_decode_T_151 = decoded[38] + decoded[39]; // @[Bitwise.scala 48:55]
+  wire [1:0] _onehot_decode_T_153 = decoded[40] + decoded[41]; // @[Bitwise.scala 48:55]
+  wire [2:0] _onehot_decode_T_155 = _onehot_decode_T_151 + _onehot_decode_T_153; // @[Bitwise.scala 48:55]
+  wire [1:0] _onehot_decode_T_157 = decoded[42] + decoded[43]; // @[Bitwise.scala 48:55]
+  wire [1:0] _onehot_decode_T_159 = decoded[45] + decoded[46]; // @[Bitwise.scala 48:55]
+  wire [1:0] _GEN_7 = {{1'd0}, decoded[44]}; // @[Bitwise.scala 48:55]
+  wire [2:0] _onehot_decode_T_161 = _GEN_7 + _onehot_decode_T_159; // @[Bitwise.scala 48:55]
+  wire [2:0] _onehot_decode_T_163 = _onehot_decode_T_157 + _onehot_decode_T_161[1:0]; // @[Bitwise.scala 48:55]
+  wire [3:0] _onehot_decode_T_165 = _onehot_decode_T_155 + _onehot_decode_T_163; // @[Bitwise.scala 48:55]
+  wire [1:0] _onehot_decode_T_167 = decoded[47] + decoded[48]; // @[Bitwise.scala 48:55]
+  wire [1:0] _onehot_decode_T_169 = decoded[50] + decoded[51]; // @[Bitwise.scala 48:55]
+  wire [1:0] _GEN_8 = {{1'd0}, decoded[49]}; // @[Bitwise.scala 48:55]
+  wire [2:0] _onehot_decode_T_171 = _GEN_8 + _onehot_decode_T_169; // @[Bitwise.scala 48:55]
+  wire [2:0] _onehot_decode_T_173 = _onehot_decode_T_167 + _onehot_decode_T_171[1:0]; // @[Bitwise.scala 48:55]
+  wire [1:0] _onehot_decode_T_175 = decoded[52] + decoded[53]; // @[Bitwise.scala 48:55]
+  wire [1:0] _onehot_decode_T_177 = decoded[55] + decoded[56]; // @[Bitwise.scala 48:55]
+  wire [1:0] _GEN_9 = {{1'd0}, decoded[54]}; // @[Bitwise.scala 48:55]
+  wire [2:0] _onehot_decode_T_179 = _GEN_9 + _onehot_decode_T_177; // @[Bitwise.scala 48:55]
+  wire [2:0] _onehot_decode_T_181 = _onehot_decode_T_175 + _onehot_decode_T_179[1:0]; // @[Bitwise.scala 48:55]
+  wire [3:0] _onehot_decode_T_183 = _onehot_decode_T_173 + _onehot_decode_T_181; // @[Bitwise.scala 48:55]
+  wire [4:0] _onehot_decode_T_185 = _onehot_decode_T_165 + _onehot_decode_T_183; // @[Bitwise.scala 48:55]
+  wire [1:0] _onehot_decode_T_187 = decoded[57] + decoded[58]; // @[Bitwise.scala 48:55]
+  wire [1:0] _onehot_decode_T_189 = decoded[60] + decoded[61]; // @[Bitwise.scala 48:55]
+  wire [1:0] _GEN_10 = {{1'd0}, decoded[59]}; // @[Bitwise.scala 48:55]
+  wire [2:0] _onehot_decode_T_191 = _GEN_10 + _onehot_decode_T_189; // @[Bitwise.scala 48:55]
+  wire [2:0] _onehot_decode_T_193 = _onehot_decode_T_187 + _onehot_decode_T_191[1:0]; // @[Bitwise.scala 48:55]
+  wire [1:0] _onehot_decode_T_195 = decoded[62] + decoded[63]; // @[Bitwise.scala 48:55]
+  wire [1:0] _onehot_decode_T_197 = decoded[65] + decoded[66]; // @[Bitwise.scala 48:55]
+  wire [1:0] _GEN_11 = {{1'd0}, decoded[64]}; // @[Bitwise.scala 48:55]
+  wire [2:0] _onehot_decode_T_199 = _GEN_11 + _onehot_decode_T_197; // @[Bitwise.scala 48:55]
+  wire [2:0] _onehot_decode_T_201 = _onehot_decode_T_195 + _onehot_decode_T_199[1:0]; // @[Bitwise.scala 48:55]
+  wire [3:0] _onehot_decode_T_203 = _onehot_decode_T_193 + _onehot_decode_T_201; // @[Bitwise.scala 48:55]
+  wire [1:0] _onehot_decode_T_205 = decoded[67] + decoded[68]; // @[Bitwise.scala 48:55]
+  wire [1:0] _onehot_decode_T_207 = decoded[70] + decoded[71]; // @[Bitwise.scala 48:55]
+  wire [1:0] _GEN_12 = {{1'd0}, decoded[69]}; // @[Bitwise.scala 48:55]
+  wire [2:0] _onehot_decode_T_209 = _GEN_12 + _onehot_decode_T_207; // @[Bitwise.scala 48:55]
+  wire [2:0] _onehot_decode_T_211 = _onehot_decode_T_205 + _onehot_decode_T_209[1:0]; // @[Bitwise.scala 48:55]
+  wire [1:0] _onehot_decode_T_213 = decoded[72] + decoded[73]; // @[Bitwise.scala 48:55]
+  wire [1:0] _onehot_decode_T_215 = decoded[75] + io_undef_value__38; // @[Bitwise.scala 48:55]
+  wire [1:0] _GEN_13 = {{1'd0}, decoded[74]}; // @[Bitwise.scala 48:55]
+  wire [2:0] _onehot_decode_T_217 = _GEN_13 + _onehot_decode_T_215; // @[Bitwise.scala 48:55]
+  wire [2:0] _onehot_decode_T_219 = _onehot_decode_T_213 + _onehot_decode_T_217[1:0]; // @[Bitwise.scala 48:55]
+  wire [3:0] _onehot_decode_T_221 = _onehot_decode_T_211 + _onehot_decode_T_219; // @[Bitwise.scala 48:55]
+  wire [4:0] _onehot_decode_T_223 = _onehot_decode_T_203 + _onehot_decode_T_221; // @[Bitwise.scala 48:55]
+  wire [5:0] _onehot_decode_T_225 = _onehot_decode_T_185 + _onehot_decode_T_223; // @[Bitwise.scala 48:55]
+  wire [6:0] onehot_decode = _onehot_decode_T_149 + _onehot_decode_T_225; // @[Bitwise.scala 48:55]
+  wire [6:0] _GEN_14 = {{6'd0}, io_undef}; // @[Decode.scala 655:24]
+  wire [6:0] _T_5 = onehot_decode + _GEN_14; // @[Decode.scala 655:24]
+  wire  _T_6 = _T_5 != 7'h1; // @[Decode.scala 655:36]
   assign io_imm12 = {_io_imm12_T_2,io_inst[31:20]}; // @[Cat.scala 31:58]
   assign io_imm20 = {io_inst[31:12],12'h0}; // @[Cat.scala 31:58]
   assign io_immjal = {io_immjal_hi,io_immjal_lo}; // @[Cat.scala 31:58]
   assign io_immbr = {io_immbr_hi,io_immbr_lo}; // @[Cat.scala 31:58]
-  assign io_immcsr = {{27'd0}, io_inst[19:15]}; // @[Decode.scala 585:13]
+  assign io_immcsr = {{27'd0}, io_inst[19:15]}; // @[Decode.scala 491:13]
   assign io_immst = {io_immst_hi,io_inst[11:7]}; // @[Cat.scala 31:58]
-  assign io_lui = _io_lui_T_3 & io_lui_bit_29 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 314:48]
-  assign io_auipc = _io_auipc_T_3 & io_lui_bit_29 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 314:48]
-  assign io_jal = _io_jal_T_2 & io_inst[3] & io_lui_bit_29 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 314:48]
-  assign io_jalr = _io_jalr_T_6 & io_lui_bit_29 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 314:48]
-  assign io_beq = _io_beq_T_7 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 314:48]
-  assign io_bne = _io_bne_T_7 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 314:48]
-  assign io_blt = _io_blt_T_7 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 314:48]
-  assign io_bge = _io_bge_T_7 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 314:48]
-  assign io_bltu = _io_bltu_T_7 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 314:48]
-  assign io_bgeu = _io_bgeu_T_7 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 314:48]
-  assign io_csrrw = _io_csrrw_T_6 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 314:48]
-  assign io_csrrs = _io_csrrs_T_6 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 314:48]
-  assign io_csrrc = _io_csrrc_T_6 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 314:48]
-  assign io_lb = _io_lb_T_7 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 314:48]
-  assign io_lh = _io_lh_T_7 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 314:48]
-  assign io_lw = _io_lw_T_7 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 314:48]
-  assign io_lbu = _io_lbu_T_7 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 314:48]
-  assign io_lhu = _io_lhu_T_7 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 314:48]
-  assign io_sb = _io_sb_T_7 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 314:48]
-  assign io_sh = _io_sh_T_7 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 314:48]
-  assign io_sw = _io_sw_T_7 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 314:48]
-  assign io_fence = _io_fence_T_19 & io_inst[3] & io_lui_bit_29 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 314:48]
-  assign io_addi = _io_addi_T_7 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 314:48]
-  assign io_slti = _io_slti_T_7 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 314:48]
-  assign io_sltiu = _io_sltiu_T_7 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 314:48]
-  assign io_xori = _io_xori_T_7 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 314:48]
-  assign io_ori = _io_ori_T_7 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 314:48]
-  assign io_andi = _io_andi_T_7 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 314:48]
-  assign io_slli = _io_slli_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 314:48]
-  assign io_srli = _io_srli_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 314:48]
-  assign io_srai = _io_srai_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 314:48]
-  assign io_add = _io_add_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 314:48]
-  assign io_sub = _io_sub_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 314:48]
-  assign io_slt = _io_slt_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 314:48]
-  assign io_sltu = _io_sltu_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 314:48]
-  assign io_xor = _io_xor_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 314:48]
-  assign io_or = _io_or_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 314:48]
-  assign io_and = _io_and_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 314:48]
-  assign io_sll = _io_sll_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 314:48]
-  assign io_srl = _io_srl_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 314:48]
-  assign io_sra = _io_sra_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 314:48]
-  assign io_mul = _io_mul_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 314:48]
-  assign io_mulh = _io_mulh_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 314:48]
-  assign io_mulhsu = _io_mulhsu_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 314:48]
-  assign io_mulhu = _io_mulhu_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 314:48]
-  assign io_mulhr = _io_mulhr_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 314:48]
-  assign io_mulhsur = _io_mulhsur_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 314:48]
-  assign io_mulhur = _io_mulhur_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 314:48]
-  assign io_dmulh = _io_dmulh_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 314:48]
-  assign io_dmulhr = _io_dmulhr_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 314:48]
-  assign io_div = _io_div_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 314:48]
-  assign io_divu = _io_divu_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 314:48]
-  assign io_rem = _io_rem_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 314:48]
-  assign io_remu = _io_remu_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 314:48]
-  assign io_flw = _io_lw_T_6 & io_lui_bit_29 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 314:48]
-  assign io_fsw = _io_sw_T_6 & io_lui_bit_29 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 314:48]
-  assign io_fmadd = _io_fmadd_T_6 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 314:48]
-  assign io_fmsub = _io_fmadd_T_5 & io_lui_bit_29 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 314:48]
-  assign io_fnmsub = _io_fnmsub_T_6 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 314:48]
-  assign io_fnmadd = _io_fmadd_T_4 & io_inst[3] & io_lui_bit_29 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 314:48]
-  assign io_fadd = _io_fadd_T_11 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 314:48]
-  assign io_fsub = _io_fsub_T_11 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 314:48]
-  assign io_fmul = _io_fmul_T_11 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 314:48]
-  assign io_fdiv = _io_fdiv_T_11 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 314:48]
-  assign io_fsqrt = _io_fsqrt_T_11 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 314:48]
-  assign io_fsgnj = _io_fsgnj_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 314:48]
-  assign io_fsgnjn = _io_fsgnjn_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 314:48]
-  assign io_fsgnjx = _io_fsgnjx_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 314:48]
-  assign io_fmin = _io_fmin_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 314:48]
-  assign io_fmax = _io_fmax_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 314:48]
-  assign io_fcvtws = _io_fcvtws_T_16 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 314:48]
-  assign io_fcvtwus = _io_fcvtwus_T_16 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 314:48]
-  assign io_fmvxw = _io_fmvxw_T_19 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 314:48]
-  assign io_feq = _io_feq_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 314:48]
-  assign io_flt = _io_flt_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 314:48]
-  assign io_fle = _io_fle_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 314:48]
-  assign io_fclass = _io_fclass_T_19 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 314:48]
-  assign io_fcvtsw = _io_fcvtsw_T_16 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 314:48]
-  assign io_fcvtswu = _io_fcvtswu_T_16 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 314:48]
-  assign io_fmvwx = _io_fmvwx_T_19 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 314:48]
-  assign io_clb = _io_clb_T_19 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 314:48]
-  assign io_clz = _io_clz_T_19 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 314:48]
-  assign io_ctz = _io_ctz_T_19 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 314:48]
-  assign io_pcnt = _io_pcnt_T_19 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 314:48]
-  assign io_min = _io_min_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 314:48]
-  assign io_minu = _io_minu_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 314:48]
-  assign io_max = _io_max_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 314:48]
-  assign io_maxu = _io_maxu_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 314:48]
-  assign io_getvl = _io_getvl_T_13 & io_inst[26:25] != 2'h3 & (io_inst[24:20] != 5'h0 | io_inst[19:15] != 5'h0); // @[Decode.scala 688:97]
-  assign io_getmaxvl = _io_getmaxvl_T_23 & _io_getvl_T_15; // @[Decode.scala 689:76]
-  assign io_vld = _io_vld_T_4 & io_lui_bit_27 & io_inst[3] & io_lui_bit_29 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 314:48]
-  assign io_vst = _io_vst_T_9 | _io_vst_T_19; // @[Decode.scala 694:71]
-  assign io_viop = _io_viop_T_9 | vdupi; // @[Decode.scala 713:20]
-  assign io_vfop = vfma | vfma4 | vdupf; // @[Decode.scala 708:28]
-  assign io_ebreak = _io_ebreak_T_29 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 314:48]
-  assign io_ecall = _io_ecall_T_29 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 314:48]
-  assign io_eexit = _io_eexit_T_29 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 314:48]
-  assign io_eyield = _io_eyield_T_29 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 314:48]
-  assign io_ectxsw = _io_ectxsw_T_29 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 314:48]
-  assign io_mpause = _io_mpause_T_29 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 314:48]
-  assign io_mret = _io_mret_T_29 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 314:48]
-  assign io_undef = ~io_undef_value_6_0; // @[Decode.scala 810:15]
-  assign io_fencei = _io_fencei_T_27 & io_inst[3] & io_lui_bit_29 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 314:48]
-  assign io_flushat = _io_flushat_T_23 & _io_getvl_T_20; // @[Decode.scala 726:76]
-  assign io_flushall = _io_flushall_T_25 & io_lui_bit_29 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 314:48]
-  assign io_slog = _slog_T_21 & io_lui_bit_29 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 314:48]
+  assign io_lui = _io_lui_T_3 & io_lui_bit_29 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 316:48]
+  assign io_auipc = _io_auipc_T_3 & io_lui_bit_29 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 316:48]
+  assign io_jal = _io_jal_T_2 & io_inst[3] & io_lui_bit_29 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 316:48]
+  assign io_jalr = _io_jalr_T_6 & io_lui_bit_29 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 316:48]
+  assign io_beq = _io_beq_T_7 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 316:48]
+  assign io_bne = _io_bne_T_7 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 316:48]
+  assign io_blt = _io_blt_T_7 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 316:48]
+  assign io_bge = _io_bge_T_7 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 316:48]
+  assign io_bltu = _io_bltu_T_7 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 316:48]
+  assign io_bgeu = _io_bgeu_T_7 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 316:48]
+  assign io_csrrw = _io_csrrw_T_6 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 316:48]
+  assign io_csrrs = _io_csrrs_T_6 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 316:48]
+  assign io_csrrc = _io_csrrc_T_6 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 316:48]
+  assign io_lb = _io_lb_T_7 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 316:48]
+  assign io_lh = _io_lh_T_7 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 316:48]
+  assign io_lw = _io_lw_T_7 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 316:48]
+  assign io_lbu = _io_lbu_T_7 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 316:48]
+  assign io_lhu = _io_lhu_T_7 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 316:48]
+  assign io_sb = _io_sb_T_7 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 316:48]
+  assign io_sh = _io_sh_T_7 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 316:48]
+  assign io_sw = _io_sw_T_7 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 316:48]
+  assign io_fence = _io_fence_T_19 & io_inst[3] & io_lui_bit_29 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 316:48]
+  assign io_addi = _io_addi_T_7 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 316:48]
+  assign io_slti = _io_slti_T_7 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 316:48]
+  assign io_sltiu = _io_sltiu_T_7 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 316:48]
+  assign io_xori = _io_xori_T_7 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 316:48]
+  assign io_ori = _io_ori_T_7 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 316:48]
+  assign io_andi = _io_andi_T_7 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 316:48]
+  assign io_slli = _io_slli_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 316:48]
+  assign io_srli = _io_srli_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 316:48]
+  assign io_srai = _io_srai_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 316:48]
+  assign io_add = _io_add_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 316:48]
+  assign io_sub = _io_sub_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 316:48]
+  assign io_slt = _io_slt_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 316:48]
+  assign io_sltu = _io_sltu_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 316:48]
+  assign io_xor = _io_xor_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 316:48]
+  assign io_or = _io_or_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 316:48]
+  assign io_and = _io_and_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 316:48]
+  assign io_sll = _io_sll_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 316:48]
+  assign io_srl = _io_srl_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 316:48]
+  assign io_sra = _io_sra_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 316:48]
+  assign io_mul = _io_mul_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 316:48]
+  assign io_mulh = _io_mulh_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 316:48]
+  assign io_mulhsu = _io_mulhsu_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 316:48]
+  assign io_mulhu = _io_mulhu_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 316:48]
+  assign io_mulhr = _io_mulhr_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 316:48]
+  assign io_mulhsur = _io_mulhsur_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 316:48]
+  assign io_mulhur = _io_mulhur_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 316:48]
+  assign io_dmulh = _io_dmulh_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 316:48]
+  assign io_dmulhr = _io_dmulhr_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 316:48]
+  assign io_div = _io_div_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 316:48]
+  assign io_divu = _io_divu_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 316:48]
+  assign io_rem = _io_rem_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 316:48]
+  assign io_remu = _io_remu_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 316:48]
+  assign io_clz = _io_clz_T_19 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 316:48]
+  assign io_ctz = _io_ctz_T_19 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 316:48]
+  assign io_pcnt = _io_pcnt_T_19 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 316:48]
+  assign io_min = _io_min_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 316:48]
+  assign io_minu = _io_minu_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 316:48]
+  assign io_max = _io_max_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 316:48]
+  assign io_maxu = _io_maxu_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 316:48]
+  assign io_getvl = _io_getvl_T_13 & io_inst[26:25] != 2'h3 & (io_inst[24:20] != 5'h0 | io_inst[19:15] != 5'h0); // @[Decode.scala 565:97]
+  assign io_getmaxvl = _io_getmaxvl_T_23 & _io_getvl_T_15; // @[Decode.scala 566:76]
+  assign io_vld = _io_vld_T_4 & io_lui_bit_27 & io_inst[3] & io_lui_bit_29 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 316:48]
+  assign io_vst = _io_vst_T_9 | _io_vst_T_19; // @[Decode.scala 571:71]
+  assign io_viop = _io_viop_T_5 | vdupi; // @[Decode.scala 584:20]
+  assign io_ebreak = _io_ebreak_T_29 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 316:48]
+  assign io_ecall = _io_ecall_T_29 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 316:48]
+  assign io_eexit = _io_eexit_T_29 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 316:48]
+  assign io_eyield = _io_eyield_T_29 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 316:48]
+  assign io_ectxsw = _io_ectxsw_T_29 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 316:48]
+  assign io_mpause = _io_mpause_T_29 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 316:48]
+  assign io_mret = _io_mret_T_29 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 316:48]
+  assign io_undef = ~io_undef_value_6_0; // @[Decode.scala 648:15]
+  assign io_fencei = _io_fencei_T_27 & io_inst[3] & io_lui_bit_29 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 316:48]
+  assign io_flushat = _io_flushat_T_23 & _io_getvl_T_20; // @[Decode.scala 597:76]
+  assign io_flushall = _io_flushall_T_25 & io_lui_bit_29 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 316:48]
+  assign io_slog = _slog_T_21 & io_lui_bit_29 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 316:48]
   always @(posedge clock) begin
     `ifndef SYNTHESIS
     `ifdef STOP_COND
       if (`STOP_COND) begin
     `endif
         if (~reset & ~(~onehot_failed)) begin
-          $fatal; // @[Decode.scala 814:9]
+          $fatal; // @[Decode.scala 652:9]
         end
     `ifdef STOP_COND
       end
@@ -8614,7 +8321,7 @@
       if (`PRINTF_COND) begin
     `endif
         if (~reset & ~(~onehot_failed)) begin
-          $fwrite(32'h80000002,"Assertion failed\n    at Decode.scala:814 assert(!onehot_failed)\n"); // @[Decode.scala 814:9]
+          $fwrite(32'h80000002,"Assertion failed\n    at Decode.scala:652 assert(!onehot_failed)\n"); // @[Decode.scala 652:9]
         end
     `ifdef PRINTF_COND
       end
@@ -8626,7 +8333,7 @@
     `endif
         if (_T_6 & _T_2) begin
           $fwrite(32'h80000002,"[FAIL] decode  inst=%x  addr=%x  decoded=0b%b  pipeline=%d\n",io_inst,io_addr,decoded,1'h0
-            ); // @[Decode.scala 819:11]
+            ); // @[Decode.scala 657:11]
         end
     `ifdef PRINTF_COND
       end
@@ -8634,10 +8341,10 @@
     `endif // SYNTHESIS
   end
   always @(posedge clock or posedge reset) begin
-    if (reset) begin // @[Decode.scala 817:45]
-      onehot_failed <= 1'h0; // @[Decode.scala 818:19]
+    if (reset) begin // @[Decode.scala 655:45]
+      onehot_failed <= 1'h0; // @[Decode.scala 656:19]
     end else begin
-      onehot_failed <= _T_5 != 7'h1 | onehot_failed; // @[Decode.scala 813:30]
+      onehot_failed <= _T_5 != 7'h1 | onehot_failed; // @[Decode.scala 651:30]
     end
   end
 // Register and memory initialization
@@ -8701,7 +8408,6 @@
   input  [31:0] io_scoreboard_regd,
   input  [31:0] io_scoreboard_comb,
   output [31:0] io_scoreboard_spec,
-  input  [31:0] io_fscoreboard,
   input         io_mactive,
   output        io_rs1Read_valid,
   output [4:0]  io_rs1Read_addr,
@@ -8718,7 +8424,7 @@
   output [31:0] io_busRead_immed,
   output        io_alu_valid,
   output [4:0]  io_alu_addr,
-  output [18:0] io_alu_op,
+  output [17:0] io_alu_op,
   output        io_bru_valid,
   output        io_bru_fwd,
   output [16:0] io_bru_op,
@@ -8732,7 +8438,7 @@
   output        io_lsu_valid,
   input         io_lsu_ready,
   output [4:0]  io_lsu_addr,
-  output [13:0] io_lsu_op,
+  output [11:0] io_lsu_op,
   output        io_mlu_valid,
   output [4:0]  io_mlu_addr,
   output [8:0]  io_mlu_op,
@@ -8740,19 +8446,11 @@
   input         io_dvu_ready,
   output [4:0]  io_dvu_addr,
   output [3:0]  io_dvu_op,
-  output        io_fpu_valid,
-  output [4:0]  io_fpu_raddr_0,
-  output [4:0]  io_fpu_raddr_1,
-  output [4:0]  io_fpu_raddr_2,
-  output [4:0]  io_fpu_waddr,
-  output [26:0] io_fpu_op,
-  input         io_fpu_busyFDiv,
-  input         io_fpu_busyFSqrt,
   output        io_vinst_valid,
   input         io_vinst_ready,
   output [4:0]  io_vinst_addr,
   output [31:0] io_vinst_inst,
-  output [5:0]  io_vinst_op,
+  output [4:0]  io_vinst_op,
   input         io_branchTaken,
   input         io_interlock,
   output        io_serializeOut_mul,
@@ -8760,194 +8458,137 @@
   output        io_serializeOut_brcond,
   output        io_slog
 );
-  wire  d_clock; // @[Decode.scala 91:17]
-  wire  d_reset; // @[Decode.scala 91:17]
-  wire [31:0] d_io_addr; // @[Decode.scala 91:17]
-  wire [31:0] d_io_inst; // @[Decode.scala 91:17]
-  wire [31:0] d_io_imm12; // @[Decode.scala 91:17]
-  wire [31:0] d_io_imm20; // @[Decode.scala 91:17]
-  wire [31:0] d_io_immjal; // @[Decode.scala 91:17]
-  wire [31:0] d_io_immbr; // @[Decode.scala 91:17]
-  wire [31:0] d_io_immcsr; // @[Decode.scala 91:17]
-  wire [31:0] d_io_immst; // @[Decode.scala 91:17]
-  wire  d_io_lui; // @[Decode.scala 91:17]
-  wire  d_io_auipc; // @[Decode.scala 91:17]
-  wire  d_io_jal; // @[Decode.scala 91:17]
-  wire  d_io_jalr; // @[Decode.scala 91:17]
-  wire  d_io_beq; // @[Decode.scala 91:17]
-  wire  d_io_bne; // @[Decode.scala 91:17]
-  wire  d_io_blt; // @[Decode.scala 91:17]
-  wire  d_io_bge; // @[Decode.scala 91:17]
-  wire  d_io_bltu; // @[Decode.scala 91:17]
-  wire  d_io_bgeu; // @[Decode.scala 91:17]
-  wire  d_io_csrrw; // @[Decode.scala 91:17]
-  wire  d_io_csrrs; // @[Decode.scala 91:17]
-  wire  d_io_csrrc; // @[Decode.scala 91:17]
-  wire  d_io_lb; // @[Decode.scala 91:17]
-  wire  d_io_lh; // @[Decode.scala 91:17]
-  wire  d_io_lw; // @[Decode.scala 91:17]
-  wire  d_io_lbu; // @[Decode.scala 91:17]
-  wire  d_io_lhu; // @[Decode.scala 91:17]
-  wire  d_io_sb; // @[Decode.scala 91:17]
-  wire  d_io_sh; // @[Decode.scala 91:17]
-  wire  d_io_sw; // @[Decode.scala 91:17]
-  wire  d_io_fence; // @[Decode.scala 91:17]
-  wire  d_io_addi; // @[Decode.scala 91:17]
-  wire  d_io_slti; // @[Decode.scala 91:17]
-  wire  d_io_sltiu; // @[Decode.scala 91:17]
-  wire  d_io_xori; // @[Decode.scala 91:17]
-  wire  d_io_ori; // @[Decode.scala 91:17]
-  wire  d_io_andi; // @[Decode.scala 91:17]
-  wire  d_io_slli; // @[Decode.scala 91:17]
-  wire  d_io_srli; // @[Decode.scala 91:17]
-  wire  d_io_srai; // @[Decode.scala 91:17]
-  wire  d_io_add; // @[Decode.scala 91:17]
-  wire  d_io_sub; // @[Decode.scala 91:17]
-  wire  d_io_slt; // @[Decode.scala 91:17]
-  wire  d_io_sltu; // @[Decode.scala 91:17]
-  wire  d_io_xor; // @[Decode.scala 91:17]
-  wire  d_io_or; // @[Decode.scala 91:17]
-  wire  d_io_and; // @[Decode.scala 91:17]
-  wire  d_io_sll; // @[Decode.scala 91:17]
-  wire  d_io_srl; // @[Decode.scala 91:17]
-  wire  d_io_sra; // @[Decode.scala 91:17]
-  wire  d_io_mul; // @[Decode.scala 91:17]
-  wire  d_io_mulh; // @[Decode.scala 91:17]
-  wire  d_io_mulhsu; // @[Decode.scala 91:17]
-  wire  d_io_mulhu; // @[Decode.scala 91:17]
-  wire  d_io_mulhr; // @[Decode.scala 91:17]
-  wire  d_io_mulhsur; // @[Decode.scala 91:17]
-  wire  d_io_mulhur; // @[Decode.scala 91:17]
-  wire  d_io_dmulh; // @[Decode.scala 91:17]
-  wire  d_io_dmulhr; // @[Decode.scala 91:17]
-  wire  d_io_div; // @[Decode.scala 91:17]
-  wire  d_io_divu; // @[Decode.scala 91:17]
-  wire  d_io_rem; // @[Decode.scala 91:17]
-  wire  d_io_remu; // @[Decode.scala 91:17]
-  wire  d_io_flw; // @[Decode.scala 91:17]
-  wire  d_io_fsw; // @[Decode.scala 91:17]
-  wire  d_io_fmadd; // @[Decode.scala 91:17]
-  wire  d_io_fmsub; // @[Decode.scala 91:17]
-  wire  d_io_fnmsub; // @[Decode.scala 91:17]
-  wire  d_io_fnmadd; // @[Decode.scala 91:17]
-  wire  d_io_fadd; // @[Decode.scala 91:17]
-  wire  d_io_fsub; // @[Decode.scala 91:17]
-  wire  d_io_fmul; // @[Decode.scala 91:17]
-  wire  d_io_fdiv; // @[Decode.scala 91:17]
-  wire  d_io_fsqrt; // @[Decode.scala 91:17]
-  wire  d_io_fsgnj; // @[Decode.scala 91:17]
-  wire  d_io_fsgnjn; // @[Decode.scala 91:17]
-  wire  d_io_fsgnjx; // @[Decode.scala 91:17]
-  wire  d_io_fmin; // @[Decode.scala 91:17]
-  wire  d_io_fmax; // @[Decode.scala 91:17]
-  wire  d_io_fcvtws; // @[Decode.scala 91:17]
-  wire  d_io_fcvtwus; // @[Decode.scala 91:17]
-  wire  d_io_fmvxw; // @[Decode.scala 91:17]
-  wire  d_io_feq; // @[Decode.scala 91:17]
-  wire  d_io_flt; // @[Decode.scala 91:17]
-  wire  d_io_fle; // @[Decode.scala 91:17]
-  wire  d_io_fclass; // @[Decode.scala 91:17]
-  wire  d_io_fcvtsw; // @[Decode.scala 91:17]
-  wire  d_io_fcvtswu; // @[Decode.scala 91:17]
-  wire  d_io_fmvwx; // @[Decode.scala 91:17]
-  wire  d_io_clb; // @[Decode.scala 91:17]
-  wire  d_io_clz; // @[Decode.scala 91:17]
-  wire  d_io_ctz; // @[Decode.scala 91:17]
-  wire  d_io_pcnt; // @[Decode.scala 91:17]
-  wire  d_io_min; // @[Decode.scala 91:17]
-  wire  d_io_minu; // @[Decode.scala 91:17]
-  wire  d_io_max; // @[Decode.scala 91:17]
-  wire  d_io_maxu; // @[Decode.scala 91:17]
-  wire  d_io_getvl; // @[Decode.scala 91:17]
-  wire  d_io_getmaxvl; // @[Decode.scala 91:17]
-  wire  d_io_vld; // @[Decode.scala 91:17]
-  wire  d_io_vst; // @[Decode.scala 91:17]
-  wire  d_io_viop; // @[Decode.scala 91:17]
-  wire  d_io_vfop; // @[Decode.scala 91:17]
-  wire  d_io_ebreak; // @[Decode.scala 91:17]
-  wire  d_io_ecall; // @[Decode.scala 91:17]
-  wire  d_io_eexit; // @[Decode.scala 91:17]
-  wire  d_io_eyield; // @[Decode.scala 91:17]
-  wire  d_io_ectxsw; // @[Decode.scala 91:17]
-  wire  d_io_mpause; // @[Decode.scala 91:17]
-  wire  d_io_mret; // @[Decode.scala 91:17]
-  wire  d_io_undef; // @[Decode.scala 91:17]
-  wire  d_io_fencei; // @[Decode.scala 91:17]
-  wire  d_io_flushat; // @[Decode.scala 91:17]
-  wire  d_io_flushall; // @[Decode.scala 91:17]
-  wire  d_io_slog; // @[Decode.scala 91:17]
-  wire  decodeEn = io_inst_valid & io_inst_ready & ~io_branchTaken; // @[Decode.scala 88:49]
-  wire  vldst = d_io_vld | d_io_vst; // @[Decode.scala 95:24]
-  wire  vldst_wb = vldst & io_inst_inst[28]; // @[Decode.scala 96:24]
-  wire [4:0] rdAddr = vldst ? io_inst_inst[19:15] : io_inst_inst[11:7]; // @[Decode.scala 98:20]
-  wire [4:0] rs2Addr = io_inst_inst[24:20]; // @[Decode.scala 100:29]
-  wire [4:0] rs3Addr = io_inst_inst[31:27]; // @[Decode.scala 101:29]
-  wire  _isAluImm_T_3 = d_io_addi | d_io_slti | d_io_sltiu | d_io_xori | d_io_ori; // @[Decode.scala 103:68]
-  wire  isAluImm = _isAluImm_T_3 | d_io_andi | d_io_slli | d_io_srli | d_io_srai; // @[Decode.scala 104:66]
-  wire  _isAluReg_T_4 = d_io_add | d_io_sub | d_io_slt | d_io_sltu | d_io_xor | d_io_or; // @[Decode.scala 106:76]
-  wire  isAluReg = _isAluReg_T_4 | d_io_and | d_io_sll | d_io_srl | d_io_sra; // @[Decode.scala 107:62]
-  wire  isAlu1Bit = d_io_clb | d_io_clz | d_io_ctz | d_io_pcnt; // @[Decode.scala 109:52]
-  wire  isAlu2Bit = d_io_min | d_io_minu | d_io_max | d_io_maxu; // @[Decode.scala 110:53]
-  wire  _isCondBr_T_3 = d_io_beq | d_io_bne | d_io_blt | d_io_bge | d_io_bltu; // @[Decode.scala 112:63]
-  wire  isCondBr = _isCondBr_T_3 | d_io_bgeu; // @[Decode.scala 113:28]
-  wire  isCsr = d_io_csrrw | d_io_csrrs | d_io_csrrc; // @[Decode.scala 115:40]
-  wire  isCsrImm = isCsr & io_inst_inst[14]; // @[Decode.scala 116:24]
-  wire  isCsrReg = isCsr & ~io_inst_inst[14]; // @[Decode.scala 117:24]
-  wire  isLoad = d_io_lb | d_io_lh | d_io_lw | d_io_lbu | d_io_lhu; // @[Decode.scala 119:58]
-  wire  isStore = d_io_sb | d_io_sh | d_io_sw; // @[Decode.scala 120:36]
-  wire  isLsu = isLoad | isStore | d_io_flw | d_io_fsw | d_io_vld | d_io_vst | d_io_flushat | d_io_flushall; // @[Decode.scala 121:97]
+  wire  d_clock; // @[Decode.scala 87:17]
+  wire  d_reset; // @[Decode.scala 87:17]
+  wire [31:0] d_io_addr; // @[Decode.scala 87:17]
+  wire [31:0] d_io_inst; // @[Decode.scala 87:17]
+  wire [31:0] d_io_imm12; // @[Decode.scala 87:17]
+  wire [31:0] d_io_imm20; // @[Decode.scala 87:17]
+  wire [31:0] d_io_immjal; // @[Decode.scala 87:17]
+  wire [31:0] d_io_immbr; // @[Decode.scala 87:17]
+  wire [31:0] d_io_immcsr; // @[Decode.scala 87:17]
+  wire [31:0] d_io_immst; // @[Decode.scala 87:17]
+  wire  d_io_lui; // @[Decode.scala 87:17]
+  wire  d_io_auipc; // @[Decode.scala 87:17]
+  wire  d_io_jal; // @[Decode.scala 87:17]
+  wire  d_io_jalr; // @[Decode.scala 87:17]
+  wire  d_io_beq; // @[Decode.scala 87:17]
+  wire  d_io_bne; // @[Decode.scala 87:17]
+  wire  d_io_blt; // @[Decode.scala 87:17]
+  wire  d_io_bge; // @[Decode.scala 87:17]
+  wire  d_io_bltu; // @[Decode.scala 87:17]
+  wire  d_io_bgeu; // @[Decode.scala 87:17]
+  wire  d_io_csrrw; // @[Decode.scala 87:17]
+  wire  d_io_csrrs; // @[Decode.scala 87:17]
+  wire  d_io_csrrc; // @[Decode.scala 87:17]
+  wire  d_io_lb; // @[Decode.scala 87:17]
+  wire  d_io_lh; // @[Decode.scala 87:17]
+  wire  d_io_lw; // @[Decode.scala 87:17]
+  wire  d_io_lbu; // @[Decode.scala 87:17]
+  wire  d_io_lhu; // @[Decode.scala 87:17]
+  wire  d_io_sb; // @[Decode.scala 87:17]
+  wire  d_io_sh; // @[Decode.scala 87:17]
+  wire  d_io_sw; // @[Decode.scala 87:17]
+  wire  d_io_fence; // @[Decode.scala 87:17]
+  wire  d_io_addi; // @[Decode.scala 87:17]
+  wire  d_io_slti; // @[Decode.scala 87:17]
+  wire  d_io_sltiu; // @[Decode.scala 87:17]
+  wire  d_io_xori; // @[Decode.scala 87:17]
+  wire  d_io_ori; // @[Decode.scala 87:17]
+  wire  d_io_andi; // @[Decode.scala 87:17]
+  wire  d_io_slli; // @[Decode.scala 87:17]
+  wire  d_io_srli; // @[Decode.scala 87:17]
+  wire  d_io_srai; // @[Decode.scala 87:17]
+  wire  d_io_add; // @[Decode.scala 87:17]
+  wire  d_io_sub; // @[Decode.scala 87:17]
+  wire  d_io_slt; // @[Decode.scala 87:17]
+  wire  d_io_sltu; // @[Decode.scala 87:17]
+  wire  d_io_xor; // @[Decode.scala 87:17]
+  wire  d_io_or; // @[Decode.scala 87:17]
+  wire  d_io_and; // @[Decode.scala 87:17]
+  wire  d_io_sll; // @[Decode.scala 87:17]
+  wire  d_io_srl; // @[Decode.scala 87:17]
+  wire  d_io_sra; // @[Decode.scala 87:17]
+  wire  d_io_mul; // @[Decode.scala 87:17]
+  wire  d_io_mulh; // @[Decode.scala 87:17]
+  wire  d_io_mulhsu; // @[Decode.scala 87:17]
+  wire  d_io_mulhu; // @[Decode.scala 87:17]
+  wire  d_io_mulhr; // @[Decode.scala 87:17]
+  wire  d_io_mulhsur; // @[Decode.scala 87:17]
+  wire  d_io_mulhur; // @[Decode.scala 87:17]
+  wire  d_io_dmulh; // @[Decode.scala 87:17]
+  wire  d_io_dmulhr; // @[Decode.scala 87:17]
+  wire  d_io_div; // @[Decode.scala 87:17]
+  wire  d_io_divu; // @[Decode.scala 87:17]
+  wire  d_io_rem; // @[Decode.scala 87:17]
+  wire  d_io_remu; // @[Decode.scala 87:17]
+  wire  d_io_clz; // @[Decode.scala 87:17]
+  wire  d_io_ctz; // @[Decode.scala 87:17]
+  wire  d_io_pcnt; // @[Decode.scala 87:17]
+  wire  d_io_min; // @[Decode.scala 87:17]
+  wire  d_io_minu; // @[Decode.scala 87:17]
+  wire  d_io_max; // @[Decode.scala 87:17]
+  wire  d_io_maxu; // @[Decode.scala 87:17]
+  wire  d_io_getvl; // @[Decode.scala 87:17]
+  wire  d_io_getmaxvl; // @[Decode.scala 87:17]
+  wire  d_io_vld; // @[Decode.scala 87:17]
+  wire  d_io_vst; // @[Decode.scala 87:17]
+  wire  d_io_viop; // @[Decode.scala 87:17]
+  wire  d_io_ebreak; // @[Decode.scala 87:17]
+  wire  d_io_ecall; // @[Decode.scala 87:17]
+  wire  d_io_eexit; // @[Decode.scala 87:17]
+  wire  d_io_eyield; // @[Decode.scala 87:17]
+  wire  d_io_ectxsw; // @[Decode.scala 87:17]
+  wire  d_io_mpause; // @[Decode.scala 87:17]
+  wire  d_io_mret; // @[Decode.scala 87:17]
+  wire  d_io_undef; // @[Decode.scala 87:17]
+  wire  d_io_fencei; // @[Decode.scala 87:17]
+  wire  d_io_flushat; // @[Decode.scala 87:17]
+  wire  d_io_flushall; // @[Decode.scala 87:17]
+  wire  d_io_slog; // @[Decode.scala 87:17]
+  wire  decodeEn = io_inst_valid & io_inst_ready & ~io_branchTaken; // @[Decode.scala 84:49]
+  wire  vldst = d_io_vld | d_io_vst; // @[Decode.scala 91:24]
+  wire  vldst_wb = vldst & io_inst_inst[28]; // @[Decode.scala 92:24]
+  wire [4:0] rdAddr = vldst ? io_inst_inst[19:15] : io_inst_inst[11:7]; // @[Decode.scala 94:20]
+  wire [4:0] rs2Addr = io_inst_inst[24:20]; // @[Decode.scala 96:29]
+  wire [4:0] rs3Addr = io_inst_inst[31:27]; // @[Decode.scala 97:29]
+  wire  _isAluImm_T_3 = d_io_addi | d_io_slti | d_io_sltiu | d_io_xori | d_io_ori; // @[Decode.scala 99:68]
+  wire  isAluImm = _isAluImm_T_3 | d_io_andi | d_io_slli | d_io_srli | d_io_srai; // @[Decode.scala 100:66]
+  wire  _isAluReg_T_4 = d_io_add | d_io_sub | d_io_slt | d_io_sltu | d_io_xor | d_io_or; // @[Decode.scala 102:76]
+  wire  isAluReg = _isAluReg_T_4 | d_io_and | d_io_sll | d_io_srl | d_io_sra; // @[Decode.scala 103:62]
+  wire  isAlu1Bit = d_io_clz | d_io_ctz | d_io_pcnt; // @[Decode.scala 105:40]
+  wire  isAlu2Bit = d_io_min | d_io_minu | d_io_max | d_io_maxu; // @[Decode.scala 106:53]
+  wire  _isCondBr_T_3 = d_io_beq | d_io_bne | d_io_blt | d_io_bge | d_io_bltu; // @[Decode.scala 108:63]
+  wire  isCondBr = _isCondBr_T_3 | d_io_bgeu; // @[Decode.scala 109:28]
+  wire  isCsr = d_io_csrrw | d_io_csrrs | d_io_csrrc; // @[Decode.scala 111:40]
+  wire  isCsrImm = isCsr & io_inst_inst[14]; // @[Decode.scala 112:24]
+  wire  isCsrReg = isCsr & ~io_inst_inst[14]; // @[Decode.scala 113:24]
+  wire  isLoad = d_io_lb | d_io_lh | d_io_lw | d_io_lbu | d_io_lhu; // @[Decode.scala 115:58]
+  wire  isStore = d_io_sb | d_io_sh | d_io_sw; // @[Decode.scala 116:36]
+  wire  isLsu = isLoad | isStore | d_io_vld | d_io_vst | d_io_flushat | d_io_flushall; // @[Decode.scala 117:73]
   wire  isMul = d_io_mul | d_io_mulh | d_io_mulhsu | d_io_mulhu | d_io_mulhr | d_io_mulhsur | d_io_mulhur | d_io_dmulh
-     | d_io_dmulhr; // @[Decode.scala 123:125]
-  wire  isDvu = d_io_div | d_io_divu | d_io_rem | d_io_remu; // @[Decode.scala 125:49]
-  wire  fpuRd = d_io_flw | d_io_fmadd | d_io_fmsub | d_io_fnmsub | d_io_fnmadd | d_io_fadd | d_io_fsub | d_io_fmul |
-    d_io_fdiv | d_io_fsqrt | d_io_fsgnj | d_io_fsgnjn | d_io_fsgnjx | d_io_fmin | d_io_fmax | d_io_fcvtsw | d_io_fcvtswu
-     | d_io_fmvwx; // @[Decode.scala 127:249]
-  wire  _fpuRs1_T_2 = d_io_fmadd | d_io_fmsub | d_io_fnmsub | d_io_fnmadd; // @[Decode.scala 128:56]
-  wire  fpuRs1 = d_io_fmadd | d_io_fmsub | d_io_fnmsub | d_io_fnmadd | d_io_fadd | d_io_fsub | d_io_fmul | d_io_fdiv |
-    d_io_fsqrt | d_io_fsgnj | d_io_fsgnjn | d_io_fsgnjx | d_io_fmin | d_io_fmax | d_io_fcvtws | d_io_feq | d_io_flt |
-    d_io_fle | d_io_fclass | d_io_fcvtws | d_io_fcvtwus | d_io_fmvxw; // @[Decode.scala 128:304]
-  wire  _fpuRs2_T_17 = d_io_vfop & io_inst_inst[1]; // @[Decode.scala 129:255]
-  wire  fpuRs2 = _fpuRs1_T_2 | d_io_fsw | d_io_fadd | d_io_fsub | d_io_fmul | d_io_fdiv | d_io_fsgnj | d_io_fsgnjn |
-    d_io_fsgnjx | d_io_fmin | d_io_fmax | d_io_feq | d_io_flt | d_io_fle | d_io_vfop & io_inst_inst[1]; // @[Decode.scala 129:241]
-  wire  isFloat = fpuRs1 | fpuRs2 | _fpuRs1_T_2 | fpuRd; // @[Decode.scala 131:44]
-  wire  isVFop = io_vinst_op[5]; // @[Decode.scala 133:27]
-  wire  isVIop = io_vinst_op[4]; // @[Decode.scala 134:27]
-  wire  isVIopVs2 = isVIop & io_inst_inst[1:0] == 2'h0; // @[Decode.scala 137:26]
-  wire [31:0] _aluRdEn_T = io_scoreboard_comb >> rdAddr; // @[Decode.scala 141:37]
-  wire  aluRdEn = ~_aluRdEn_T[0] | isVIop | isStore | isCondBr | isFloat & ~(d_io_fcvtws | d_io_fcvtwus | d_io_fmvxw); // @[Decode.scala 141:83]
-  wire [31:0] _aluRs1En_T = io_scoreboard_comb >> io_inst_inst[19:15]; // @[Decode.scala 142:37]
-  wire  aluRs1En = ~_aluRs1En_T[0] | isVIop | isLsu | d_io_auipc | isVFop | isFloat & ~(d_io_fcvtsw | d_io_fcvtswu |
-    d_io_fmvwx); // @[Decode.scala 142:93]
-  wire [31:0] _aluRs2En_T = io_scoreboard_comb >> rs2Addr; // @[Decode.scala 143:37]
-  wire  aluRs2En = ~_aluRs2En_T[0] | isVIopVs2 | isLsu | d_io_auipc | isVFop | isAluImm | isAlu1Bit | isFloat; // @[Decode.scala 143:118]
-  wire  aluEn = aluRdEn & aluRs1En & aluRs2En; // @[Decode.scala 146:35]
-  wire [31:0] _bruEn_T_1 = io_scoreboard_regd >> io_inst_inst[19:15]; // @[Decode.scala 149:48]
-  wire  _bruEn_T_6 = io_inst_inst[31:20] == 12'h0; // @[Decode.scala 150:35]
-  wire  bruEn = ~d_io_jalr | ~_bruEn_T_1[0] | _bruEn_T_6; // @[Decode.scala 149:58]
-  wire  _lsuEn_T_11 = io_busRead_bypass ? _aluRs1En_T[0] : _bruEn_T_1[0]; // @[Decode.scala 156:20]
-  wire  _lsuEn_T_15 = _aluRs2En_T[0] & (isStore | vldst); // @[Decode.scala 158:49]
-  wire  _lsuEn_T_16 = _lsuEn_T_11 | _lsuEn_T_15; // @[Decode.scala 157:50]
-  wire  _lsuEn_T_17 = ~_lsuEn_T_16; // @[Decode.scala 156:15]
-  wire  _lsuEn_T_18 = io_lsu_ready & _lsuEn_T_17; // @[Decode.scala 155:50]
-  wire  lsuEn = ~isLsu | _lsuEn_T_18; // @[Decode.scala 153:22]
-  wire [31:0] _fpuEn_T_1 = io_fscoreboard >> rdAddr; // @[Decode.scala 164:52]
-  wire [31:0] _fpuEn_T_4 = io_fscoreboard >> io_inst_inst[19:15]; // @[Decode.scala 165:53]
-  wire  _fpuEn_T_6 = fpuRs1 & _fpuEn_T_4[0]; // @[Decode.scala 165:36]
-  wire  _fpuEn_T_7 = fpuRd & _fpuEn_T_1[0] | _fpuEn_T_6; // @[Decode.scala 164:61]
-  wire [31:0] _fpuEn_T_8 = io_fscoreboard >> rs2Addr; // @[Decode.scala 166:53]
-  wire  _fpuEn_T_10 = fpuRs2 & _fpuEn_T_8[0]; // @[Decode.scala 166:36]
-  wire  _fpuEn_T_11 = _fpuEn_T_7 | _fpuEn_T_10; // @[Decode.scala 165:63]
-  wire [31:0] _fpuEn_T_12 = io_fscoreboard >> rs3Addr; // @[Decode.scala 167:53]
-  wire  _fpuEn_T_14 = _fpuRs1_T_2 & _fpuEn_T_12[0]; // @[Decode.scala 167:36]
-  wire  _fpuEn_T_15 = _fpuEn_T_11 | _fpuEn_T_14; // @[Decode.scala 166:63]
-  wire  _fpuEn_T_16 = d_io_fdiv & io_fpu_busyFDiv; // @[Decode.scala 168:39]
-  wire  _fpuEn_T_17 = _fpuEn_T_15 | _fpuEn_T_16; // @[Decode.scala 167:63]
-  wire  _fpuEn_T_18 = d_io_fsqrt & io_fpu_busyFSqrt; // @[Decode.scala 169:40]
-  wire  _fpuEn_T_19 = _fpuEn_T_17 | _fpuEn_T_18; // @[Decode.scala 168:58]
-  wire  fpuEn = ~isFloat | ~_fpuEn_T_19; // @[Decode.scala 164:24]
-  wire  vinstEn = ~(io_vinst_op != 6'h0 & ~io_vinst_ready); // @[Decode.scala 174:17]
-  wire  fenceEn = ~(d_io_fence & io_mactive); // @[Decode.scala 178:17]
-  wire  aluValid_value__9 = io_alu_op[18]; // @[Library.scala 182:26]
+     | d_io_dmulhr; // @[Decode.scala 119:125]
+  wire  isDvu = d_io_div | d_io_divu | d_io_rem | d_io_remu; // @[Decode.scala 121:49]
+  wire  isVIop = io_vinst_op[4]; // @[Decode.scala 123:27]
+  wire  isVIopVs2 = isVIop & io_inst_inst[1:0] == 2'h0; // @[Decode.scala 126:26]
+  wire [31:0] _aluRdEn_T = io_scoreboard_comb >> rdAddr; // @[Decode.scala 130:37]
+  wire  aluRdEn = ~_aluRdEn_T[0] | isVIop | isStore | isCondBr; // @[Decode.scala 130:71]
+  wire [31:0] _aluRs1En_T = io_scoreboard_comb >> io_inst_inst[19:15]; // @[Decode.scala 131:37]
+  wire  aluRs1En = ~_aluRs1En_T[0] | isVIop | isLsu | d_io_auipc; // @[Decode.scala 131:69]
+  wire [31:0] _aluRs2En_T = io_scoreboard_comb >> rs2Addr; // @[Decode.scala 132:37]
+  wire  aluRs2En = ~_aluRs2En_T[0] | isVIopVs2 | isLsu | d_io_auipc | isAluImm | isAlu1Bit; // @[Decode.scala 132:95]
+  wire  aluEn = aluRdEn & aluRs1En & aluRs2En; // @[Decode.scala 135:35]
+  wire [31:0] _bruEn_T_1 = io_scoreboard_regd >> io_inst_inst[19:15]; // @[Decode.scala 138:48]
+  wire  _bruEn_T_6 = io_inst_inst[31:20] == 12'h0; // @[Decode.scala 139:35]
+  wire  bruEn = ~d_io_jalr | ~_bruEn_T_1[0] | _bruEn_T_6; // @[Decode.scala 138:58]
+  wire  _lsuEn_T_11 = io_busRead_bypass ? _aluRs1En_T[0] : _bruEn_T_1[0]; // @[Decode.scala 145:20]
+  wire  _lsuEn_T_15 = _aluRs2En_T[0] & (isStore | vldst); // @[Decode.scala 147:49]
+  wire  _lsuEn_T_16 = _lsuEn_T_11 | _lsuEn_T_15; // @[Decode.scala 146:50]
+  wire  _lsuEn_T_17 = ~_lsuEn_T_16; // @[Decode.scala 145:15]
+  wire  _lsuEn_T_18 = io_lsu_ready & _lsuEn_T_17; // @[Decode.scala 144:50]
+  wire  lsuEn = ~isLsu | _lsuEn_T_18; // @[Decode.scala 142:22]
+  wire  vinstEn = ~(io_vinst_op != 5'h0 & ~io_vinst_ready); // @[Decode.scala 155:17]
+  wire  fenceEn = ~(d_io_fence & io_mactive); // @[Decode.scala 159:17]
   wire  aluValid_value__0 = io_alu_op[0] | io_alu_op[1]; // @[Library.scala 194:39]
   wire  aluValid_value__1 = io_alu_op[2] | io_alu_op[3]; // @[Library.scala 194:39]
   wire  aluValid_value__2 = io_alu_op[4] | io_alu_op[5]; // @[Library.scala 194:39]
@@ -8961,32 +8602,30 @@
   wire  aluValid_value_1_1 = aluValid_value__2 | aluValid_value__3; // @[Library.scala 194:39]
   wire  aluValid_value_1_2 = aluValid_value__4 | aluValid_value__5; // @[Library.scala 194:39]
   wire  aluValid_value_1_3 = aluValid_value__6 | aluValid_value__7; // @[Library.scala 194:39]
-  wire  aluValid_value_1_4 = aluValid_value__8 | aluValid_value__9; // @[Library.scala 194:39]
   wire  aluValid_value_2_0 = aluValid_value_1_0 | aluValid_value_1_1; // @[Library.scala 194:39]
   wire  aluValid_value_2_1 = aluValid_value_1_2 | aluValid_value_1_3; // @[Library.scala 194:39]
   wire  aluValid_value_3_0 = aluValid_value_2_0 | aluValid_value_2_1; // @[Library.scala 194:39]
-  wire  aluValid_value_4_0 = aluValid_value_3_0 | aluValid_value_1_4; // @[Library.scala 194:39]
-  wire  aluOp_1 = d_io_sub; // @[Decode.scala 182:19 189:19]
-  wire  aluOp_0 = d_io_auipc | d_io_addi | d_io_add; // @[Decode.scala 188:46]
-  wire  aluOp_3 = d_io_sltiu | d_io_sltu; // @[Decode.scala 191:33]
-  wire  aluOp_2 = d_io_slti | d_io_slt; // @[Decode.scala 190:32]
-  wire  aluOp_5 = d_io_ori | d_io_or; // @[Decode.scala 193:31]
-  wire  aluOp_4 = d_io_xori | d_io_xor; // @[Decode.scala 192:32]
-  wire  aluOp_8 = d_io_srli | d_io_srl; // @[Decode.scala 196:32]
-  wire  aluOp_7 = d_io_slli | d_io_sll; // @[Decode.scala 195:32]
-  wire  aluOp_6 = d_io_andi | d_io_and; // @[Decode.scala 194:32]
-  wire [8:0] io_alu_op_lo = {aluOp_8,aluOp_7,aluOp_6,aluOp_5,aluOp_4,aluOp_3,aluOp_2,aluOp_1,aluOp_0}; // @[Decode.scala 186:22]
-  wire  aluOp_10 = d_io_lui; // @[Decode.scala 182:19 198:19]
-  wire  aluOp_9 = d_io_srai | d_io_sra; // @[Decode.scala 197:32]
-  wire  aluOp_13 = d_io_ctz; // @[Decode.scala 182:19 201:19]
-  wire  aluOp_12 = d_io_clz; // @[Decode.scala 182:19 200:19]
-  wire  aluOp_11 = d_io_clb; // @[Decode.scala 182:19 199:19]
-  wire  aluOp_15 = d_io_min; // @[Decode.scala 182:19 203:19]
-  wire  aluOp_14 = d_io_pcnt; // @[Decode.scala 182:19 202:19]
-  wire  aluOp_18 = d_io_maxu; // @[Decode.scala 182:19 206:19]
-  wire  aluOp_17 = d_io_max; // @[Decode.scala 182:19 205:19]
-  wire  aluOp_16 = d_io_minu; // @[Decode.scala 182:19 204:19]
-  wire [9:0] io_alu_op_hi = {aluOp_18,aluOp_17,aluOp_16,aluOp_15,aluOp_14,aluOp_13,aluOp_12,aluOp_11,aluOp_10,aluOp_9}; // @[Decode.scala 186:22]
+  wire  aluValid_value_4_0 = aluValid_value_3_0 | aluValid_value__8; // @[Library.scala 194:39]
+  wire  aluOp_1 = d_io_sub; // @[Decode.scala 163:19 170:19]
+  wire  aluOp_0 = d_io_auipc | d_io_addi | d_io_add; // @[Decode.scala 169:46]
+  wire  aluOp_3 = d_io_sltiu | d_io_sltu; // @[Decode.scala 172:33]
+  wire  aluOp_2 = d_io_slti | d_io_slt; // @[Decode.scala 171:32]
+  wire  aluOp_5 = d_io_ori | d_io_or; // @[Decode.scala 174:31]
+  wire  aluOp_4 = d_io_xori | d_io_xor; // @[Decode.scala 173:32]
+  wire  aluOp_8 = d_io_srli | d_io_srl; // @[Decode.scala 177:32]
+  wire  aluOp_7 = d_io_slli | d_io_sll; // @[Decode.scala 176:32]
+  wire  aluOp_6 = d_io_andi | d_io_and; // @[Decode.scala 175:32]
+  wire [8:0] io_alu_op_lo = {aluOp_8,aluOp_7,aluOp_6,aluOp_5,aluOp_4,aluOp_3,aluOp_2,aluOp_1,aluOp_0}; // @[Decode.scala 167:22]
+  wire  aluOp_10 = d_io_lui; // @[Decode.scala 163:19 179:19]
+  wire  aluOp_9 = d_io_srai | d_io_sra; // @[Decode.scala 178:32]
+  wire  aluOp_12 = d_io_ctz; // @[Decode.scala 163:19 181:19]
+  wire  aluOp_11 = d_io_clz; // @[Decode.scala 163:19 180:19]
+  wire  aluOp_14 = d_io_min; // @[Decode.scala 163:19 183:19]
+  wire  aluOp_13 = d_io_pcnt; // @[Decode.scala 163:19 182:19]
+  wire  aluOp_17 = d_io_maxu; // @[Decode.scala 163:19 186:19]
+  wire  aluOp_16 = d_io_max; // @[Decode.scala 163:19 185:19]
+  wire  aluOp_15 = d_io_minu; // @[Decode.scala 163:19 184:19]
+  wire [8:0] io_alu_op_hi = {aluOp_17,aluOp_16,aluOp_15,aluOp_14,aluOp_13,aluOp_12,aluOp_11,aluOp_10,aluOp_9}; // @[Decode.scala 167:22]
   wire  bruValid_value__8 = io_bru_op[16]; // @[Library.scala 182:26]
   wire  bruValid_value__0 = io_bru_op[0] | io_bru_op[1]; // @[Library.scala 194:39]
   wire  bruValid_value__1 = io_bru_op[2] | io_bru_op[3]; // @[Library.scala 194:39]
@@ -9004,60 +8643,56 @@
   wire  bruValid_value_2_1 = bruValid_value_1_2 | bruValid_value_1_3; // @[Library.scala 194:39]
   wire  bruValid_value_3_0 = bruValid_value_2_0 | bruValid_value_2_1; // @[Library.scala 194:39]
   wire  bruValid_value_4_0 = bruValid_value_3_0 | bruValid_value__8; // @[Library.scala 194:39]
-  wire  bruOp_1 = d_io_jalr; // @[Decode.scala 210:19 220:19]
-  wire  bruOp_0 = d_io_jal; // @[Decode.scala 210:19 219:19]
-  wire  bruOp_3 = d_io_bne; // @[Decode.scala 210:19 222:19]
-  wire  bruOp_2 = d_io_beq; // @[Decode.scala 210:19 221:19]
-  wire  bruOp_5 = d_io_bge; // @[Decode.scala 210:19 224:19]
-  wire  bruOp_4 = d_io_blt; // @[Decode.scala 210:19 223:19]
-  wire  bruOp_7 = d_io_bgeu; // @[Decode.scala 210:19 226:19]
-  wire  bruOp_6 = d_io_bltu; // @[Decode.scala 210:19 225:19]
-  wire [7:0] io_bru_op_lo = {bruOp_7,bruOp_6,bruOp_5,bruOp_4,bruOp_3,bruOp_2,bruOp_1,bruOp_0}; // @[Decode.scala 214:22]
-  wire  bruOp_9 = d_io_ecall; // @[Decode.scala 210:19 228:21]
-  wire  bruOp_8 = d_io_ebreak; // @[Decode.scala 210:19 227:21]
-  wire  bruOp_11 = d_io_eyield; // @[Decode.scala 210:19 230:21]
-  wire  bruOp_10 = d_io_eexit; // @[Decode.scala 210:19 229:21]
-  wire  bruOp_13 = d_io_mpause; // @[Decode.scala 210:19 232:21]
-  wire  bruOp_12 = d_io_ectxsw; // @[Decode.scala 210:19 231:21]
-  wire  bruOp_16 = d_io_undef; // @[Decode.scala 210:19 235:21]
-  wire  bruOp_15 = d_io_fencei; // @[Decode.scala 210:19 234:21]
-  wire  bruOp_14 = d_io_mret; // @[Decode.scala 210:19 233:21]
-  wire [8:0] io_bru_op_hi = {bruOp_16,bruOp_15,bruOp_14,bruOp_13,bruOp_12,bruOp_11,bruOp_10,bruOp_9,bruOp_8}; // @[Decode.scala 214:22]
-  wire [31:0] _io_bru_target_T_1 = io_inst_inst[2] ? d_io_immjal : d_io_immbr; // @[Decode.scala 216:38]
+  wire  bruOp_1 = d_io_jalr; // @[Decode.scala 190:19 200:19]
+  wire  bruOp_0 = d_io_jal; // @[Decode.scala 190:19 199:19]
+  wire  bruOp_3 = d_io_bne; // @[Decode.scala 190:19 202:19]
+  wire  bruOp_2 = d_io_beq; // @[Decode.scala 190:19 201:19]
+  wire  bruOp_5 = d_io_bge; // @[Decode.scala 190:19 204:19]
+  wire  bruOp_4 = d_io_blt; // @[Decode.scala 190:19 203:19]
+  wire  bruOp_7 = d_io_bgeu; // @[Decode.scala 190:19 206:19]
+  wire  bruOp_6 = d_io_bltu; // @[Decode.scala 190:19 205:19]
+  wire [7:0] io_bru_op_lo = {bruOp_7,bruOp_6,bruOp_5,bruOp_4,bruOp_3,bruOp_2,bruOp_1,bruOp_0}; // @[Decode.scala 194:22]
+  wire  bruOp_9 = d_io_ecall; // @[Decode.scala 190:19 208:21]
+  wire  bruOp_8 = d_io_ebreak; // @[Decode.scala 190:19 207:21]
+  wire  bruOp_11 = d_io_eyield; // @[Decode.scala 190:19 210:21]
+  wire  bruOp_10 = d_io_eexit; // @[Decode.scala 190:19 209:21]
+  wire  bruOp_13 = d_io_mpause; // @[Decode.scala 190:19 212:21]
+  wire  bruOp_12 = d_io_ectxsw; // @[Decode.scala 190:19 211:21]
+  wire  bruOp_16 = d_io_undef; // @[Decode.scala 190:19 215:21]
+  wire  bruOp_15 = d_io_fencei; // @[Decode.scala 190:19 214:21]
+  wire  bruOp_14 = d_io_mret; // @[Decode.scala 190:19 213:21]
+  wire [8:0] io_bru_op_hi = {bruOp_16,bruOp_15,bruOp_14,bruOp_13,bruOp_12,bruOp_11,bruOp_10,bruOp_9,bruOp_8}; // @[Decode.scala 194:22]
+  wire [31:0] _io_bru_target_T_1 = io_inst_inst[2] ? d_io_immjal : d_io_immbr; // @[Decode.scala 196:38]
   wire  csrValid_value__1 = io_csr_op[2]; // @[Library.scala 182:26]
   wire  csrValid_value__0 = io_csr_op[0] | io_csr_op[1]; // @[Library.scala 194:39]
   wire  csrValid_value_1_0 = csrValid_value__0 | csrValid_value__1; // @[Library.scala 194:39]
-  wire  csrOp_2 = d_io_csrrc; // @[Decode.scala 239:19 248:20]
-  wire  csrOp_1 = d_io_csrrs; // @[Decode.scala 239:19 247:20]
-  wire [1:0] io_csr_op_hi = {csrOp_2,csrOp_1}; // @[Decode.scala 244:22]
-  wire  csrOp_0 = d_io_csrrw; // @[Decode.scala 239:19 246:20]
+  wire  csrOp_2 = d_io_csrrc; // @[Decode.scala 219:19 228:20]
+  wire  csrOp_1 = d_io_csrrs; // @[Decode.scala 219:19 227:20]
+  wire [1:0] io_csr_op_hi = {csrOp_2,csrOp_1}; // @[Decode.scala 224:22]
+  wire  csrOp_0 = d_io_csrrw; // @[Decode.scala 219:19 226:20]
   wire  lsuValid_value__0 = io_lsu_op[0] | io_lsu_op[1]; // @[Library.scala 194:39]
   wire  lsuValid_value__1 = io_lsu_op[2] | io_lsu_op[3]; // @[Library.scala 194:39]
   wire  lsuValid_value__2 = io_lsu_op[4] | io_lsu_op[5]; // @[Library.scala 194:39]
   wire  lsuValid_value__3 = io_lsu_op[6] | io_lsu_op[7]; // @[Library.scala 194:39]
   wire  lsuValid_value__4 = io_lsu_op[8] | io_lsu_op[9]; // @[Library.scala 194:39]
   wire  lsuValid_value__5 = io_lsu_op[10] | io_lsu_op[11]; // @[Library.scala 194:39]
-  wire  lsuValid_value__6 = io_lsu_op[12] | io_lsu_op[13]; // @[Library.scala 194:39]
   wire  lsuValid_value_1_0 = lsuValid_value__0 | lsuValid_value__1; // @[Library.scala 194:39]
   wire  lsuValid_value_1_1 = lsuValid_value__2 | lsuValid_value__3; // @[Library.scala 194:39]
   wire  lsuValid_value_1_2 = lsuValid_value__4 | lsuValid_value__5; // @[Library.scala 194:39]
   wire  lsuValid_value_2_0 = lsuValid_value_1_0 | lsuValid_value_1_1; // @[Library.scala 194:39]
-  wire  lsuValid_value_2_1 = lsuValid_value_1_2 | lsuValid_value__6; // @[Library.scala 194:39]
-  wire  lsuValid_value_3_0 = lsuValid_value_2_0 | lsuValid_value_2_1; // @[Library.scala 194:39]
-  wire  lsuOp_2 = d_io_lw; // @[Decode.scala 252:19 261:18]
-  wire  lsuOp_1 = d_io_lh; // @[Decode.scala 252:19 260:18]
-  wire  lsuOp_0 = d_io_lb; // @[Decode.scala 252:19 259:18]
-  wire  lsuOp_4 = d_io_lhu; // @[Decode.scala 252:19 263:18]
-  wire  lsuOp_3 = d_io_lbu; // @[Decode.scala 252:19 262:18]
-  wire  lsuOp_6 = d_io_sh; // @[Decode.scala 252:19 265:18]
-  wire  lsuOp_5 = d_io_sb; // @[Decode.scala 252:19 264:18]
-  wire [6:0] io_lsu_op_lo = {lsuOp_6,lsuOp_5,lsuOp_4,lsuOp_3,lsuOp_2,lsuOp_1,lsuOp_0}; // @[Decode.scala 257:22]
-  wire  lsuOp_9 = d_io_fsw; // @[Decode.scala 252:19 271:18]
-  wire  lsuOp_8 = d_io_flw; // @[Decode.scala 252:19 270:18]
-  wire  lsuOp_7 = d_io_sw; // @[Decode.scala 252:19 266:18]
-  wire  lsuOp_11 = d_io_flushat; // @[Decode.scala 252:19 268:23]
-  wire  lsuOp_12 = d_io_flushall; // @[Decode.scala 252:19 269:23]
-  wire [6:0] io_lsu_op_hi = {vldst,lsuOp_12,lsuOp_11,bruOp_15,lsuOp_9,lsuOp_8,lsuOp_7}; // @[Decode.scala 257:22]
+  wire  lsuValid_value_3_0 = lsuValid_value_2_0 | lsuValid_value_1_2; // @[Library.scala 194:39]
+  wire  lsuOp_2 = d_io_lw; // @[Decode.scala 232:19 241:18]
+  wire  lsuOp_1 = d_io_lh; // @[Decode.scala 232:19 240:18]
+  wire  lsuOp_0 = d_io_lb; // @[Decode.scala 232:19 239:18]
+  wire  lsuOp_5 = d_io_sb; // @[Decode.scala 232:19 244:18]
+  wire  lsuOp_4 = d_io_lhu; // @[Decode.scala 232:19 243:18]
+  wire  lsuOp_3 = d_io_lbu; // @[Decode.scala 232:19 242:18]
+  wire [5:0] io_lsu_op_lo = {lsuOp_5,lsuOp_4,lsuOp_3,lsuOp_2,lsuOp_1,lsuOp_0}; // @[Decode.scala 237:22]
+  wire  lsuOp_7 = d_io_sw; // @[Decode.scala 232:19 246:18]
+  wire  lsuOp_6 = d_io_sh; // @[Decode.scala 232:19 245:18]
+  wire  lsuOp_10 = d_io_flushall; // @[Decode.scala 232:19 249:23]
+  wire  lsuOp_9 = d_io_flushat; // @[Decode.scala 232:19 248:23]
+  wire [5:0] io_lsu_op_hi = {vldst,lsuOp_10,lsuOp_9,bruOp_15,lsuOp_7,lsuOp_6}; // @[Decode.scala 237:22]
   wire  mluValid_value__4 = io_mlu_op[8]; // @[Library.scala 182:26]
   wire  mluValid_value__0 = io_mlu_op[0] | io_mlu_op[1]; // @[Library.scala 194:39]
   wire  mluValid_value__1 = io_mlu_op[2] | io_mlu_op[3]; // @[Library.scala 194:39]
@@ -9067,120 +8702,62 @@
   wire  mluValid_value_1_1 = mluValid_value__2 | mluValid_value__3; // @[Library.scala 194:39]
   wire  mluValid_value_2_0 = mluValid_value_1_0 | mluValid_value_1_1; // @[Library.scala 194:39]
   wire  mluValid_value_3_0 = mluValid_value_2_0 | mluValid_value__4; // @[Library.scala 194:39]
-  wire  mluOp_1 = d_io_mulh; // @[Decode.scala 276:19 283:22]
-  wire  mluOp_0 = d_io_mul; // @[Decode.scala 276:19 282:22]
-  wire  mluOp_3 = d_io_mulhu; // @[Decode.scala 276:19 285:22]
-  wire  mluOp_2 = d_io_mulhsu; // @[Decode.scala 276:19 284:22]
-  wire [3:0] io_mlu_op_lo = {mluOp_3,mluOp_2,mluOp_1,mluOp_0}; // @[Decode.scala 280:22]
-  wire  mluOp_5 = d_io_mulhsur; // @[Decode.scala 276:19 287:22]
-  wire  mluOp_4 = d_io_mulhr; // @[Decode.scala 276:19 286:22]
-  wire  mluOp_8 = d_io_dmulhr; // @[Decode.scala 276:19 290:22]
-  wire  mluOp_7 = d_io_dmulh; // @[Decode.scala 276:19 289:22]
-  wire  mluOp_6 = d_io_mulhur; // @[Decode.scala 276:19 288:22]
-  wire [4:0] io_mlu_op_hi = {mluOp_8,mluOp_7,mluOp_6,mluOp_5,mluOp_4}; // @[Decode.scala 280:22]
+  wire  mluOp_1 = d_io_mulh; // @[Decode.scala 255:19 262:22]
+  wire  mluOp_0 = d_io_mul; // @[Decode.scala 255:19 261:22]
+  wire  mluOp_3 = d_io_mulhu; // @[Decode.scala 255:19 264:22]
+  wire  mluOp_2 = d_io_mulhsu; // @[Decode.scala 255:19 263:22]
+  wire [3:0] io_mlu_op_lo = {mluOp_3,mluOp_2,mluOp_1,mluOp_0}; // @[Decode.scala 259:22]
+  wire  mluOp_5 = d_io_mulhsur; // @[Decode.scala 255:19 266:22]
+  wire  mluOp_4 = d_io_mulhr; // @[Decode.scala 255:19 265:22]
+  wire  mluOp_8 = d_io_dmulhr; // @[Decode.scala 255:19 269:22]
+  wire  mluOp_7 = d_io_dmulh; // @[Decode.scala 255:19 268:22]
+  wire  mluOp_6 = d_io_mulhur; // @[Decode.scala 255:19 267:22]
+  wire [4:0] io_mlu_op_hi = {mluOp_8,mluOp_7,mluOp_6,mluOp_5,mluOp_4}; // @[Decode.scala 259:22]
   wire  dvuValid_value__0 = io_dvu_op[0] | io_dvu_op[1]; // @[Library.scala 194:39]
   wire  dvuValid_value__1 = io_dvu_op[2] | io_dvu_op[3]; // @[Library.scala 194:39]
   wire  dvuValid_value_1_0 = dvuValid_value__0 | dvuValid_value__1; // @[Library.scala 194:39]
-  wire  dvuOp_1 = d_io_divu; // @[Decode.scala 294:19 301:19]
-  wire  dvuOp_0 = d_io_div; // @[Decode.scala 294:19 300:19]
-  wire [1:0] io_dvu_op_lo = {dvuOp_1,dvuOp_0}; // @[Decode.scala 298:22]
-  wire  dvuOp_3 = d_io_remu; // @[Decode.scala 294:19 303:19]
-  wire  dvuOp_2 = d_io_rem; // @[Decode.scala 294:19 302:19]
-  wire [1:0] io_dvu_op_hi = {dvuOp_3,dvuOp_2}; // @[Decode.scala 298:22]
-  wire  dvuEn = ~dvuValid_value_1_0 | io_dvu_ready; // @[Decode.scala 305:42]
-  wire  fpuValid_value__0 = lsuOp_8 | lsuOp_9; // @[Library.scala 194:39]
-  wire  fpuOp_2 = d_io_fmadd; // @[Decode.scala 309:19 321:22]
-  wire  fpuOp_3 = d_io_fmsub; // @[Decode.scala 309:19 322:22]
-  wire  fpuValid_value__1 = fpuOp_2 | fpuOp_3; // @[Library.scala 194:39]
-  wire  fpuOp_4 = d_io_fnmsub; // @[Decode.scala 309:19 323:22]
-  wire  fpuOp_5 = d_io_fnmadd; // @[Decode.scala 309:19 324:22]
-  wire  fpuValid_value__2 = fpuOp_4 | fpuOp_5; // @[Library.scala 194:39]
-  wire  fpuOp_6 = d_io_fadd; // @[Decode.scala 309:19 325:22]
-  wire  fpuOp_7 = d_io_fsub; // @[Decode.scala 309:19 326:22]
-  wire  fpuValid_value__3 = fpuOp_6 | fpuOp_7; // @[Library.scala 194:39]
-  wire  fpuOp_8 = d_io_fmul; // @[Decode.scala 309:19 327:22]
-  wire  fpuOp_9 = d_io_fdiv; // @[Decode.scala 309:19 328:22]
-  wire  fpuValid_value__4 = fpuOp_8 | fpuOp_9; // @[Library.scala 194:39]
-  wire  fpuOp_10 = d_io_fsqrt; // @[Decode.scala 309:19 329:22]
-  wire  fpuOp_11 = d_io_fsgnj; // @[Decode.scala 309:19 330:22]
-  wire  fpuValid_value__5 = fpuOp_10 | fpuOp_11; // @[Library.scala 194:39]
-  wire  fpuOp_12 = d_io_fsgnjn; // @[Decode.scala 309:19 331:22]
-  wire  fpuOp_13 = d_io_fsgnjx; // @[Decode.scala 309:19 332:22]
-  wire  fpuValid_value__6 = fpuOp_12 | fpuOp_13; // @[Library.scala 194:39]
-  wire  fpuOp_14 = d_io_fmin; // @[Decode.scala 309:19 333:22]
-  wire  fpuOp_15 = d_io_fmax; // @[Decode.scala 309:19 334:22]
-  wire  fpuValid_value__7 = fpuOp_14 | fpuOp_15; // @[Library.scala 194:39]
-  wire  fpuOp_16 = d_io_fcvtws; // @[Decode.scala 309:19 335:22]
-  wire  fpuOp_17 = d_io_fcvtwus; // @[Decode.scala 309:19 336:22]
-  wire  fpuValid_value__8 = fpuOp_16 | fpuOp_17; // @[Library.scala 194:39]
-  wire  fpuOp_18 = d_io_fmvxw; // @[Decode.scala 309:19 337:22]
-  wire  fpuOp_19 = d_io_feq; // @[Decode.scala 309:19 338:22]
-  wire  fpuValid_value__9 = fpuOp_18 | fpuOp_19; // @[Library.scala 194:39]
-  wire  fpuOp_20 = d_io_flt; // @[Decode.scala 309:19 339:22]
-  wire  fpuOp_21 = d_io_fle; // @[Decode.scala 309:19 340:22]
-  wire  fpuValid_value__10 = fpuOp_20 | fpuOp_21; // @[Library.scala 194:39]
-  wire  fpuOp_22 = d_io_fclass; // @[Decode.scala 309:19 341:22]
-  wire  fpuOp_23 = d_io_fcvtsw; // @[Decode.scala 309:19 342:22]
-  wire  fpuValid_value__11 = fpuOp_22 | fpuOp_23; // @[Library.scala 194:39]
-  wire  fpuOp_24 = d_io_fcvtswu; // @[Decode.scala 309:19 343:22]
-  wire  fpuOp_25 = d_io_fmvwx; // @[Decode.scala 309:19 344:22]
-  wire  fpuValid_value__12 = fpuOp_24 | fpuOp_25; // @[Library.scala 194:39]
-  wire  fpuValid_value_1_0 = fpuValid_value__0 | fpuValid_value__1; // @[Library.scala 194:39]
-  wire  fpuValid_value_1_1 = fpuValid_value__2 | fpuValid_value__3; // @[Library.scala 194:39]
-  wire  fpuValid_value_1_2 = fpuValid_value__4 | fpuValid_value__5; // @[Library.scala 194:39]
-  wire  fpuValid_value_1_3 = fpuValid_value__6 | fpuValid_value__7; // @[Library.scala 194:39]
-  wire  fpuValid_value_1_4 = fpuValid_value__8 | fpuValid_value__9; // @[Library.scala 194:39]
-  wire  fpuValid_value_1_5 = fpuValid_value__10 | fpuValid_value__11; // @[Library.scala 194:39]
-  wire  fpuValid_value_1_6 = fpuValid_value__12 | _fpuRs2_T_17; // @[Library.scala 194:39]
-  wire  fpuValid_value_2_0 = fpuValid_value_1_0 | fpuValid_value_1_1; // @[Library.scala 194:39]
-  wire  fpuValid_value_2_1 = fpuValid_value_1_2 | fpuValid_value_1_3; // @[Library.scala 194:39]
-  wire  fpuValid_value_2_2 = fpuValid_value_1_4 | fpuValid_value_1_5; // @[Library.scala 194:39]
-  wire  fpuValid_value_3_0 = fpuValid_value_2_0 | fpuValid_value_2_1; // @[Library.scala 194:39]
-  wire  fpuValid_value_3_1 = fpuValid_value_2_2 | fpuValid_value_1_6; // @[Library.scala 194:39]
-  wire  fpuValid_value_4_0 = fpuValid_value_3_0 | fpuValid_value_3_1; // @[Library.scala 194:39]
-  wire [5:0] io_fpu_op_lo_lo = {fpuOp_5,fpuOp_4,fpuOp_3,fpuOp_2,lsuOp_9,lsuOp_8}; // @[Decode.scala 313:22]
-  wire [12:0] io_fpu_op_lo = {fpuOp_12,fpuOp_11,fpuOp_10,fpuOp_9,fpuOp_8,fpuOp_7,fpuOp_6,io_fpu_op_lo_lo}; // @[Decode.scala 313:22]
-  wire [6:0] io_fpu_op_hi_lo = {fpuOp_19,fpuOp_18,fpuOp_17,fpuOp_16,fpuOp_15,fpuOp_14,fpuOp_13}; // @[Decode.scala 313:22]
-  wire [13:0] io_fpu_op_hi = {_fpuRs2_T_17,fpuOp_25,fpuOp_24,fpuOp_23,fpuOp_22,fpuOp_21,fpuOp_20,io_fpu_op_hi_lo}; // @[Decode.scala 313:22]
-  wire  vinstOp_0 = d_io_getvl; // @[Decode.scala 349:21 361:24]
-  wire  vinstOp_1 = d_io_getmaxvl; // @[Decode.scala 349:21 362:27]
+  wire  dvuOp_1 = d_io_divu; // @[Decode.scala 273:19 280:19]
+  wire  dvuOp_0 = d_io_div; // @[Decode.scala 273:19 279:19]
+  wire [1:0] io_dvu_op_lo = {dvuOp_1,dvuOp_0}; // @[Decode.scala 277:22]
+  wire  dvuOp_3 = d_io_remu; // @[Decode.scala 273:19 282:19]
+  wire  dvuOp_2 = d_io_rem; // @[Decode.scala 273:19 281:19]
+  wire [1:0] io_dvu_op_hi = {dvuOp_3,dvuOp_2}; // @[Decode.scala 277:22]
+  wire  dvuEn = ~dvuValid_value_1_0 | io_dvu_ready; // @[Decode.scala 284:42]
+  wire  vinstOp_0 = d_io_getvl; // @[Decode.scala 288:21 299:24]
+  wire  vinstOp_1 = d_io_getmaxvl; // @[Decode.scala 288:21 300:27]
   wire  vinstValid_value__0 = vinstOp_0 | vinstOp_1; // @[Library.scala 194:39]
-  wire  vinstOp_2 = d_io_vld; // @[Decode.scala 349:21 357:22]
-  wire  vinstOp_3 = d_io_vst; // @[Decode.scala 349:21 358:22]
+  wire  vinstOp_2 = d_io_vld; // @[Decode.scala 288:21 296:22]
+  wire  vinstOp_3 = d_io_vst; // @[Decode.scala 288:21 297:22]
   wire  vinstValid_value__1 = vinstOp_2 | vinstOp_3; // @[Library.scala 194:39]
-  wire  vinstOp_4 = d_io_viop; // @[Decode.scala 349:21 359:23]
-  wire  vinstOp_5 = d_io_vfop; // @[Decode.scala 349:21 360:23]
-  wire  vinstValid_value__2 = vinstOp_4 | vinstOp_5; // @[Library.scala 194:39]
   wire  vinstValid_value_1_0 = vinstValid_value__0 | vinstValid_value__1; // @[Library.scala 194:39]
-  wire  vinstValid_value_2_0 = vinstValid_value_1_0 | vinstValid_value__2; // @[Library.scala 194:39]
-  wire [2:0] io_vinst_op_lo = {vinstOp_2,vinstOp_1,vinstOp_0}; // @[Decode.scala 355:26]
-  wire [2:0] io_vinst_op_hi = {vinstOp_5,vinstOp_4,vinstOp_3}; // @[Decode.scala 355:26]
-  wire  _io_rs1Read_valid_T = isCondBr | isAluReg; // @[Decode.scala 368:45]
-  wire  _io_rs1Read_valid_T_4 = isCondBr | isAluReg | isAluImm | isAlu1Bit | isAlu2Bit | isCsrImm; // @[Decode.scala 368:95]
-  wire  _io_rs1Read_valid_T_9 = _io_rs1Read_valid_T_4 | isCsrReg | isMul | isDvu | d_io_slog | d_io_fcvtsw; // @[Decode.scala 369:75]
-  wire  _io_rs1Read_valid_T_13 = _io_rs1Read_valid_T_9 | d_io_fcvtswu | d_io_fmvwx | d_io_getvl | d_io_vld; // @[Decode.scala 370:79]
-  wire  _io_rs1Read_valid_T_14 = _io_rs1Read_valid_T_13 | d_io_vst; // @[Decode.scala 371:32]
-  wire  _io_rs2Read_valid_T_3 = _io_rs1Read_valid_T | isAlu2Bit | isStore | isCsrReg; // @[Decode.scala 372:81]
-  wire  _io_rs2Read_valid_T_8 = _io_rs2Read_valid_T_3 | isMul | isDvu | d_io_slog | d_io_getvl | d_io_vld; // @[Decode.scala 373:77]
-  wire  _io_rs2Read_valid_T_10 = _io_rs2Read_valid_T_8 | d_io_vst | d_io_viop; // @[Decode.scala 374:44]
-  wire  _io_rs2Set_value_T = d_io_auipc | d_io_lui; // @[Decode.scala 389:45]
-  wire  _rdMark_valid_T_4 = lsuValid_value_3_0 & isLoad; // @[Decode.scala 395:16]
+  wire  vinstOp_4 = d_io_viop; // @[Decode.scala 288:21 298:23]
+  wire  vinstValid_value_2_0 = vinstValid_value_1_0 | vinstOp_4; // @[Library.scala 194:39]
+  wire [1:0] io_vinst_op_lo = {vinstOp_1,vinstOp_0}; // @[Decode.scala 294:26]
+  wire [2:0] io_vinst_op_hi = {vinstOp_4,vinstOp_3,vinstOp_2}; // @[Decode.scala 294:26]
+  wire  _io_rs1Read_valid_T = isCondBr | isAluReg; // @[Decode.scala 306:45]
+  wire  _io_rs1Read_valid_T_4 = isCondBr | isAluReg | isAluImm | isAlu1Bit | isAlu2Bit | isCsrImm; // @[Decode.scala 306:95]
+  wire  _io_rs1Read_valid_T_9 = _io_rs1Read_valid_T_4 | isCsrReg | isMul | isDvu | d_io_slog | d_io_getvl; // @[Decode.scala 307:75]
+  wire  _io_rs1Read_valid_T_11 = _io_rs1Read_valid_T_9 | d_io_vld | d_io_vst; // @[Decode.scala 308:46]
+  wire  _io_rs2Read_valid_T_3 = _io_rs1Read_valid_T | isAlu2Bit | isStore | isCsrReg; // @[Decode.scala 309:81]
+  wire  _io_rs2Read_valid_T_8 = _io_rs2Read_valid_T_3 | isMul | isDvu | d_io_slog | d_io_getvl | d_io_vld; // @[Decode.scala 310:77]
+  wire  _io_rs2Read_valid_T_10 = _io_rs2Read_valid_T_8 | d_io_vst | d_io_viop; // @[Decode.scala 311:44]
+  wire  _io_rs2Set_value_T = d_io_auipc | d_io_lui; // @[Decode.scala 326:45]
+  wire  _rdMark_valid_T_4 = lsuValid_value_3_0 & isLoad; // @[Decode.scala 332:16]
   wire  _rdMark_valid_T_5 = aluValid_value_4_0 | csrValid_value_1_0 | mluValid_value_3_0 | dvuValid_value_1_0 &
-    io_dvu_ready | _rdMark_valid_T_4; // @[Decode.scala 394:68]
-  wire  _rdMark_valid_T_9 = _rdMark_valid_T_5 | d_io_fcvtws | d_io_fcvtwus | d_io_fmvxw | d_io_feq; // @[Decode.scala 395:71]
-  wire  _rdMark_valid_T_13 = _rdMark_valid_T_9 | d_io_flt | d_io_fle | d_io_fclass | d_io_getvl; // @[Decode.scala 396:55]
-  wire  _rdMark_valid_T_19 = bruValid_value_4_0 & (bruOp_0 | bruOp_1) & rdAddr != 5'h0; // @[Decode.scala 398:55]
-  wire  rdMark_valid = _rdMark_valid_T_13 | d_io_getmaxvl | vldst_wb | _rdMark_valid_T_19; // @[Decode.scala 397:47]
+    io_dvu_ready | _rdMark_valid_T_4; // @[Decode.scala 331:68]
+  wire  _rdMark_valid_T_6 = _rdMark_valid_T_5 | d_io_getvl; // @[Decode.scala 332:26]
+  wire  _rdMark_valid_T_12 = bruValid_value_4_0 & (bruOp_0 | bruOp_1) & rdAddr != 5'h0; // @[Decode.scala 334:55]
+  wire  rdMark_valid = _rdMark_valid_T_6 | d_io_getmaxvl | vldst_wb | _rdMark_valid_T_12; // @[Decode.scala 333:47]
   wire [31:0] _scoreboard_spec_T = 32'h1 << rdAddr; // @[OneHot.scala 64:12]
-  wire [31:0] scoreboard_spec = rdMark_valid ? _scoreboard_spec_T : 32'h0; // @[Decode.scala 401:28]
-  wire  _io_busRead_bypass_T_9 = io_inst_inst[11:7] == 5'h0; // @[Decode.scala 413:65]
-  wire  _io_busRead_bypass_T_10 = ~io_inst_inst[5] | io_inst_inst[6] ? rs2Addr == 5'h0 : _io_busRead_bypass_T_9; // @[Decode.scala 412:8]
-  wire  storeSelect = io_inst_inst[6:3] == 4'h4 & io_inst_inst[1:0] == 2'h3; // @[Decode.scala 417:47]
-  wire [4:0] _io_busRead_immed_T_3 = storeSelect ? d_io_immst[4:0] : d_io_imm12[4:0]; // @[Decode.scala 420:30]
-  wire  _io_inst_ready_T_6 = aluEn & bruEn & lsuEn & dvuEn & fpuEn & vinstEn & fenceEn; // @[Decode.scala 425:82]
-  wire  _io_serializeOut_jump_T_2 = bruOp_0 | d_io_jalr | d_io_ebreak; // @[Decode.scala 434:72]
-  wire  _io_serializeOut_jump_T_5 = _io_serializeOut_jump_T_2 | d_io_ecall | d_io_eexit | d_io_eyield; // @[Decode.scala 435:67]
-  DecodedInstruction d ( // @[Decode.scala 91:17]
+  wire [31:0] scoreboard_spec = rdMark_valid ? _scoreboard_spec_T : 32'h0; // @[Decode.scala 337:28]
+  wire  _io_busRead_bypass_T_9 = io_inst_inst[11:7] == 5'h0; // @[Decode.scala 349:65]
+  wire  _io_busRead_bypass_T_10 = ~io_inst_inst[5] | io_inst_inst[6] ? rs2Addr == 5'h0 : _io_busRead_bypass_T_9; // @[Decode.scala 348:8]
+  wire  storeSelect = io_inst_inst[6:3] == 4'h4 & io_inst_inst[1:0] == 2'h3; // @[Decode.scala 353:47]
+  wire [4:0] _io_busRead_immed_T_3 = storeSelect ? d_io_immst[4:0] : d_io_imm12[4:0]; // @[Decode.scala 356:30]
+  wire  _io_inst_ready_T_5 = aluEn & bruEn & lsuEn & dvuEn & vinstEn & fenceEn; // @[Decode.scala 361:73]
+  wire  _io_serializeOut_jump_T_2 = bruOp_0 | d_io_jalr | d_io_ebreak; // @[Decode.scala 370:72]
+  wire  _io_serializeOut_jump_T_5 = _io_serializeOut_jump_T_2 | d_io_ecall | d_io_eexit | d_io_eyield; // @[Decode.scala 371:67]
+  DecodedInstruction d ( // @[Decode.scala 87:17]
     .clock(d_clock),
     .reset(d_reset),
     .io_addr(d_io_addr),
@@ -9245,33 +8822,6 @@
     .io_divu(d_io_divu),
     .io_rem(d_io_rem),
     .io_remu(d_io_remu),
-    .io_flw(d_io_flw),
-    .io_fsw(d_io_fsw),
-    .io_fmadd(d_io_fmadd),
-    .io_fmsub(d_io_fmsub),
-    .io_fnmsub(d_io_fnmsub),
-    .io_fnmadd(d_io_fnmadd),
-    .io_fadd(d_io_fadd),
-    .io_fsub(d_io_fsub),
-    .io_fmul(d_io_fmul),
-    .io_fdiv(d_io_fdiv),
-    .io_fsqrt(d_io_fsqrt),
-    .io_fsgnj(d_io_fsgnj),
-    .io_fsgnjn(d_io_fsgnjn),
-    .io_fsgnjx(d_io_fsgnjx),
-    .io_fmin(d_io_fmin),
-    .io_fmax(d_io_fmax),
-    .io_fcvtws(d_io_fcvtws),
-    .io_fcvtwus(d_io_fcvtwus),
-    .io_fmvxw(d_io_fmvxw),
-    .io_feq(d_io_feq),
-    .io_flt(d_io_flt),
-    .io_fle(d_io_fle),
-    .io_fclass(d_io_fclass),
-    .io_fcvtsw(d_io_fcvtsw),
-    .io_fcvtswu(d_io_fcvtswu),
-    .io_fmvwx(d_io_fmvwx),
-    .io_clb(d_io_clb),
     .io_clz(d_io_clz),
     .io_ctz(d_io_ctz),
     .io_pcnt(d_io_pcnt),
@@ -9284,7 +8834,6 @@
     .io_vld(d_io_vld),
     .io_vst(d_io_vst),
     .io_viop(d_io_viop),
-    .io_vfop(d_io_vfop),
     .io_ebreak(d_io_ebreak),
     .io_ecall(d_io_ecall),
     .io_eexit(d_io_eexit),
@@ -9298,61 +8847,55 @@
     .io_flushall(d_io_flushall),
     .io_slog(d_io_slog)
   );
-  assign io_inst_ready = _io_inst_ready_T_6 & ~io_halted & ~io_interlock; // @[Decode.scala 426:55]
+  assign io_inst_ready = _io_inst_ready_T_5 & ~io_halted & ~io_interlock; // @[Decode.scala 362:55]
   assign io_scoreboard_spec = {scoreboard_spec[31:1],1'h0}; // @[Cat.scala 31:58]
-  assign io_rs1Read_valid = decodeEn & _io_rs1Read_valid_T_14; // @[Decode.scala 368:32]
-  assign io_rs1Read_addr = io_inst_inst[0] ? io_inst_inst[19:15] : rs3Addr; // @[Decode.scala 377:25]
-  assign io_rs1Set_valid = decodeEn & (d_io_auipc | isCsrImm); // @[Decode.scala 383:31]
-  assign io_rs1Set_value = isCsr ? d_io_immcsr : io_inst_addr; // @[Decode.scala 386:25]
-  assign io_rs2Read_valid = decodeEn & _io_rs2Read_valid_T_10; // @[Decode.scala 372:32]
-  assign io_rs2Read_addr = io_inst_inst[24:20]; // @[Decode.scala 100:29]
-  assign io_rs2Set_valid = io_rs1Set_valid | decodeEn & (isAluImm | isAlu1Bit | d_io_lui); // @[Decode.scala 384:38]
+  assign io_rs1Read_valid = decodeEn & _io_rs1Read_valid_T_11; // @[Decode.scala 306:32]
+  assign io_rs1Read_addr = io_inst_inst[0] ? io_inst_inst[19:15] : rs3Addr; // @[Decode.scala 314:25]
+  assign io_rs1Set_valid = decodeEn & (d_io_auipc | isCsrImm); // @[Decode.scala 320:31]
+  assign io_rs1Set_value = isCsr ? d_io_immcsr : io_inst_addr; // @[Decode.scala 323:25]
+  assign io_rs2Read_valid = decodeEn & _io_rs2Read_valid_T_10; // @[Decode.scala 309:32]
+  assign io_rs2Read_addr = io_inst_inst[24:20]; // @[Decode.scala 96:29]
+  assign io_rs2Set_valid = io_rs1Set_valid | decodeEn & (isAluImm | isAlu1Bit | d_io_lui); // @[Decode.scala 321:38]
   assign io_rs2Set_value = _io_rs2Set_value_T ? d_io_imm20 : d_io_imm12; // @[Mux.scala 101:16]
-  assign io_rdMark_valid = decodeEn & rdMark_valid; // @[Decode.scala 404:31]
-  assign io_rdMark_addr = vldst ? io_inst_inst[19:15] : io_inst_inst[11:7]; // @[Decode.scala 98:20]
-  assign io_busRead_bypass = io_inst_inst[31:25] == 7'h0 & _io_busRead_bypass_T_10; // @[Decode.scala 411:52]
-  assign io_busRead_immen = ~d_io_flushat; // @[Decode.scala 418:23]
+  assign io_rdMark_valid = decodeEn & rdMark_valid; // @[Decode.scala 340:31]
+  assign io_rdMark_addr = vldst ? io_inst_inst[19:15] : io_inst_inst[11:7]; // @[Decode.scala 94:20]
+  assign io_busRead_bypass = io_inst_inst[31:25] == 7'h0 & _io_busRead_bypass_T_10; // @[Decode.scala 347:52]
+  assign io_busRead_immen = ~d_io_flushat; // @[Decode.scala 354:23]
   assign io_busRead_immed = {d_io_imm12[31:5],_io_busRead_immed_T_3}; // @[Cat.scala 31:58]
-  assign io_alu_valid = decodeEn & aluValid_value_4_0; // @[Decode.scala 184:28]
-  assign io_alu_addr = vldst ? io_inst_inst[19:15] : io_inst_inst[11:7]; // @[Decode.scala 98:20]
-  assign io_alu_op = {io_alu_op_hi,io_alu_op_lo}; // @[Decode.scala 186:22]
-  assign io_bru_valid = decodeEn & bruValid_value_4_0; // @[Decode.scala 212:28]
-  assign io_bru_fwd = io_inst_brchFwd; // @[Decode.scala 213:14]
-  assign io_bru_op = {io_bru_op_hi,io_bru_op_lo}; // @[Decode.scala 214:22]
-  assign io_bru_pc = io_inst_addr; // @[Decode.scala 215:13]
-  assign io_bru_target = io_inst_addr + _io_bru_target_T_1; // @[Decode.scala 216:33]
-  assign io_bru_link = vldst ? io_inst_inst[19:15] : io_inst_inst[11:7]; // @[Decode.scala 98:20]
-  assign io_csr_valid = decodeEn & csrValid_value_1_0; // @[Decode.scala 241:28]
-  assign io_csr_addr = vldst ? io_inst_inst[19:15] : io_inst_inst[11:7]; // @[Decode.scala 98:20]
-  assign io_csr_index = io_inst_inst[31:20]; // @[Decode.scala 243:31]
-  assign io_csr_op = {io_csr_op_hi,csrOp_0}; // @[Decode.scala 244:22]
-  assign io_lsu_valid = decodeEn & lsuValid_value_3_0; // @[Decode.scala 254:28]
-  assign io_lsu_addr = vldst ? io_inst_inst[19:15] : io_inst_inst[11:7]; // @[Decode.scala 98:20]
-  assign io_lsu_op = {io_lsu_op_hi,io_lsu_op_lo}; // @[Decode.scala 257:22]
-  assign io_mlu_valid = decodeEn & mluValid_value_3_0; // @[Decode.scala 278:28]
-  assign io_mlu_addr = vldst ? io_inst_inst[19:15] : io_inst_inst[11:7]; // @[Decode.scala 98:20]
-  assign io_mlu_op = {io_mlu_op_hi,io_mlu_op_lo}; // @[Decode.scala 280:22]
-  assign io_dvu_valid = decodeEn & dvuValid_value_1_0; // @[Decode.scala 296:28]
-  assign io_dvu_addr = vldst ? io_inst_inst[19:15] : io_inst_inst[11:7]; // @[Decode.scala 98:20]
-  assign io_dvu_op = {io_dvu_op_hi,io_dvu_op_lo}; // @[Decode.scala 298:22]
-  assign io_fpu_valid = decodeEn & fpuValid_value_4_0; // @[Decode.scala 312:28]
-  assign io_fpu_raddr_0 = io_inst_inst[19:15]; // @[Decode.scala 99:29]
-  assign io_fpu_raddr_1 = io_inst_inst[24:20]; // @[Decode.scala 100:29]
-  assign io_fpu_raddr_2 = io_inst_inst[31:27]; // @[Decode.scala 101:29]
-  assign io_fpu_waddr = vldst ? io_inst_inst[19:15] : io_inst_inst[11:7]; // @[Decode.scala 98:20]
-  assign io_fpu_op = {io_fpu_op_hi,io_fpu_op_lo}; // @[Decode.scala 313:22]
-  assign io_vinst_valid = decodeEn & vinstValid_value_2_0; // @[Decode.scala 352:30]
-  assign io_vinst_addr = vldst ? io_inst_inst[19:15] : io_inst_inst[11:7]; // @[Decode.scala 98:20]
-  assign io_vinst_inst = io_inst_inst; // @[Decode.scala 354:17]
-  assign io_vinst_op = {io_vinst_op_hi,io_vinst_op_lo}; // @[Decode.scala 355:26]
+  assign io_alu_valid = decodeEn & aluValid_value_4_0; // @[Decode.scala 165:28]
+  assign io_alu_addr = vldst ? io_inst_inst[19:15] : io_inst_inst[11:7]; // @[Decode.scala 94:20]
+  assign io_alu_op = {io_alu_op_hi,io_alu_op_lo}; // @[Decode.scala 167:22]
+  assign io_bru_valid = decodeEn & bruValid_value_4_0; // @[Decode.scala 192:28]
+  assign io_bru_fwd = io_inst_brchFwd; // @[Decode.scala 193:14]
+  assign io_bru_op = {io_bru_op_hi,io_bru_op_lo}; // @[Decode.scala 194:22]
+  assign io_bru_pc = io_inst_addr; // @[Decode.scala 195:13]
+  assign io_bru_target = io_inst_addr + _io_bru_target_T_1; // @[Decode.scala 196:33]
+  assign io_bru_link = vldst ? io_inst_inst[19:15] : io_inst_inst[11:7]; // @[Decode.scala 94:20]
+  assign io_csr_valid = decodeEn & csrValid_value_1_0; // @[Decode.scala 221:28]
+  assign io_csr_addr = vldst ? io_inst_inst[19:15] : io_inst_inst[11:7]; // @[Decode.scala 94:20]
+  assign io_csr_index = io_inst_inst[31:20]; // @[Decode.scala 223:31]
+  assign io_csr_op = {io_csr_op_hi,csrOp_0}; // @[Decode.scala 224:22]
+  assign io_lsu_valid = decodeEn & lsuValid_value_3_0; // @[Decode.scala 234:28]
+  assign io_lsu_addr = vldst ? io_inst_inst[19:15] : io_inst_inst[11:7]; // @[Decode.scala 94:20]
+  assign io_lsu_op = {io_lsu_op_hi,io_lsu_op_lo}; // @[Decode.scala 237:22]
+  assign io_mlu_valid = decodeEn & mluValid_value_3_0; // @[Decode.scala 257:28]
+  assign io_mlu_addr = vldst ? io_inst_inst[19:15] : io_inst_inst[11:7]; // @[Decode.scala 94:20]
+  assign io_mlu_op = {io_mlu_op_hi,io_mlu_op_lo}; // @[Decode.scala 259:22]
+  assign io_dvu_valid = decodeEn & dvuValid_value_1_0; // @[Decode.scala 275:28]
+  assign io_dvu_addr = vldst ? io_inst_inst[19:15] : io_inst_inst[11:7]; // @[Decode.scala 94:20]
+  assign io_dvu_op = {io_dvu_op_hi,io_dvu_op_lo}; // @[Decode.scala 277:22]
+  assign io_vinst_valid = decodeEn & vinstValid_value_2_0; // @[Decode.scala 291:30]
+  assign io_vinst_addr = vldst ? io_inst_inst[19:15] : io_inst_inst[11:7]; // @[Decode.scala 94:20]
+  assign io_vinst_inst = io_inst_inst; // @[Decode.scala 293:17]
+  assign io_vinst_op = {io_vinst_op_hi,io_vinst_op_lo}; // @[Decode.scala 294:26]
   assign io_serializeOut_mul = mluValid_value_2_0 | mluValid_value__4; // @[Library.scala 194:39]
-  assign io_serializeOut_jump = _io_serializeOut_jump_T_5 | d_io_ectxsw | d_io_mpause | d_io_mret; // @[Decode.scala 436:69]
-  assign io_serializeOut_brcond = bruOp_2 | d_io_bne | d_io_blt | d_io_bge | d_io_bltu | d_io_bgeu; // @[Decode.scala 438:65]
-  assign io_slog = decodeEn & d_io_slog; // @[Decode.scala 365:23]
+  assign io_serializeOut_jump = _io_serializeOut_jump_T_5 | d_io_ectxsw | d_io_mpause | d_io_mret; // @[Decode.scala 372:69]
+  assign io_serializeOut_brcond = bruOp_2 | d_io_bne | d_io_blt | d_io_bge | d_io_bltu | d_io_bgeu; // @[Decode.scala 374:65]
+  assign io_slog = decodeEn & d_io_slog; // @[Decode.scala 303:23]
   assign d_clock = clock;
   assign d_reset = reset;
-  assign d_io_addr = io_inst_addr; // @[Decode.scala 92:13]
-  assign d_io_inst = io_inst_inst; // @[Decode.scala 93:13]
+  assign d_io_addr = io_inst_addr; // @[Decode.scala 88:13]
+  assign d_io_inst = io_inst_inst; // @[Decode.scala 89:13]
 endmodule
 module DecodedInstruction_1(
   input         clock,
@@ -9418,33 +8961,6 @@
   output        io_divu,
   output        io_rem,
   output        io_remu,
-  output        io_flw,
-  output        io_fsw,
-  output        io_fmadd,
-  output        io_fmsub,
-  output        io_fnmsub,
-  output        io_fnmadd,
-  output        io_fadd,
-  output        io_fsub,
-  output        io_fmul,
-  output        io_fdiv,
-  output        io_fsqrt,
-  output        io_fsgnj,
-  output        io_fsgnjn,
-  output        io_fsgnjx,
-  output        io_fmin,
-  output        io_fmax,
-  output        io_fcvtws,
-  output        io_fcvtwus,
-  output        io_fmvxw,
-  output        io_feq,
-  output        io_flt,
-  output        io_fle,
-  output        io_fclass,
-  output        io_fcvtsw,
-  output        io_fcvtswu,
-  output        io_fmvwx,
-  output        io_clb,
   output        io_clz,
   output        io_ctz,
   output        io_pcnt,
@@ -9457,7 +8973,6 @@
   output        io_vld,
   output        io_vst,
   output        io_viop,
-  output        io_vfop,
   output        io_ebreak,
   output        io_ecall,
   output        io_eexit,
@@ -9481,343 +8996,318 @@
   wire [4:0] io_immbr_lo = {io_inst[11:8],1'h0}; // @[Cat.scala 31:58]
   wire [26:0] io_immbr_hi = {_io_imm12_T_2,io_inst[7],io_inst[30:25]}; // @[Cat.scala 31:58]
   wire [26:0] io_immst_hi = {_io_imm12_T_2,io_inst[31:25]}; // @[Cat.scala 31:58]
-  wire  io_lui_bit_1 = io_inst[30]; // @[Library.scala 316:23]
-  wire  io_lui_bit_2 = io_inst[29]; // @[Library.scala 316:23]
-  wire  io_lui_bit_3 = io_inst[28]; // @[Library.scala 316:23]
-  wire  io_lui_bit_4 = io_inst[27]; // @[Library.scala 316:23]
-  wire  io_lui_bit_5 = io_inst[26]; // @[Library.scala 316:23]
-  wire  io_lui_bit_6 = io_inst[25]; // @[Library.scala 316:23]
-  wire  io_lui_bit_7 = io_inst[24]; // @[Library.scala 316:23]
-  wire  io_lui_bit_8 = io_inst[23]; // @[Library.scala 316:23]
-  wire  io_lui_bit_9 = io_inst[22]; // @[Library.scala 316:23]
-  wire  io_lui_bit_10 = io_inst[21]; // @[Library.scala 316:23]
-  wire  io_lui_bit_12 = io_inst[19]; // @[Library.scala 316:23]
-  wire  io_lui_bit_13 = io_inst[18]; // @[Library.scala 316:23]
-  wire  io_lui_bit_14 = io_inst[17]; // @[Library.scala 316:23]
-  wire  io_lui_bit_15 = io_inst[16]; // @[Library.scala 316:23]
-  wire  io_lui_bit_16 = io_inst[15]; // @[Library.scala 316:23]
-  wire  io_lui_bit_17 = io_inst[14]; // @[Library.scala 316:23]
-  wire  io_lui_bit_18 = io_inst[13]; // @[Library.scala 316:23]
-  wire  io_lui_bit_19 = io_inst[12]; // @[Library.scala 316:23]
-  wire  io_lui_bit_25 = ~io_inst[6]; // @[Library.scala 310:19]
-  wire  io_lui_bit_26 = io_inst[5]; // @[Library.scala 313:23]
-  wire  io_lui_bit_27 = io_inst[4]; // @[Library.scala 313:23]
-  wire  _io_lui_T_2 = io_lui_bit_25 & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 314:48]
-  wire  io_lui_bit_28 = ~io_inst[3]; // @[Library.scala 310:19]
-  wire  _io_lui_T_3 = _io_lui_T_2 & io_lui_bit_28; // @[Library.scala 311:48]
-  wire  io_lui_bit_29 = io_inst[2]; // @[Library.scala 313:23]
-  wire  io_lui_bit_30 = io_inst[1]; // @[Library.scala 313:23]
-  wire  io_lui_bit_31 = io_inst[0]; // @[Library.scala 313:23]
-  wire  io_auipc_bit_26 = ~io_lui_bit_26; // @[Library.scala 310:19]
-  wire  _io_auipc_T_1 = io_lui_bit_25 & io_auipc_bit_26; // @[Library.scala 311:48]
-  wire  _io_auipc_T_2 = _io_auipc_T_1 & io_lui_bit_27; // @[Library.scala 314:48]
-  wire  _io_auipc_T_3 = _io_auipc_T_2 & io_lui_bit_28; // @[Library.scala 311:48]
-  wire  _io_jal_T_1 = io_inst[6] & io_lui_bit_26; // @[Library.scala 314:48]
-  wire  io_jal_bit_27 = ~io_lui_bit_27; // @[Library.scala 310:19]
-  wire  _io_jal_T_2 = _io_jal_T_1 & io_jal_bit_27; // @[Library.scala 311:48]
-  wire  io_jalr_bit_17 = ~io_lui_bit_17; // @[Library.scala 310:19]
-  wire  io_jalr_bit_18 = ~io_lui_bit_18; // @[Library.scala 310:19]
-  wire  _io_jalr_T_1 = io_jalr_bit_17 & io_jalr_bit_18; // @[Library.scala 311:48]
-  wire  io_jalr_bit_19 = ~io_lui_bit_19; // @[Library.scala 310:19]
-  wire  _io_jalr_T_2 = io_jalr_bit_17 & io_jalr_bit_18 & io_jalr_bit_19; // @[Library.scala 311:48]
-  wire  _io_jalr_T_4 = _io_jalr_T_2 & io_inst[6] & io_lui_bit_26; // @[Library.scala 314:48]
-  wire  _io_jalr_T_6 = _io_jalr_T_4 & io_jal_bit_27 & io_lui_bit_28; // @[Library.scala 311:48]
-  wire  io_beq_bit_29 = ~io_lui_bit_29; // @[Library.scala 310:19]
-  wire  _io_beq_T_7 = _io_jalr_T_4 & io_jal_bit_27 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 311:48]
-  wire  _io_bne_T_2 = _io_jalr_T_1 & io_lui_bit_19; // @[Library.scala 314:48]
-  wire  _io_bne_T_4 = _io_jalr_T_1 & io_lui_bit_19 & io_inst[6] & io_lui_bit_26; // @[Library.scala 314:48]
-  wire  _io_bne_T_7 = _io_bne_T_4 & io_jal_bit_27 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 311:48]
-  wire  _io_blt_T_1 = io_lui_bit_17 & io_jalr_bit_18; // @[Library.scala 311:48]
-  wire  _io_blt_T_2 = io_lui_bit_17 & io_jalr_bit_18 & io_jalr_bit_19; // @[Library.scala 311:48]
-  wire  _io_blt_T_4 = _io_blt_T_2 & io_inst[6] & io_lui_bit_26; // @[Library.scala 314:48]
-  wire  _io_blt_T_7 = _io_blt_T_4 & io_jal_bit_27 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 311:48]
-  wire  _io_bge_T_2 = _io_blt_T_1 & io_lui_bit_19; // @[Library.scala 314:48]
-  wire  _io_bge_T_4 = _io_blt_T_1 & io_lui_bit_19 & io_inst[6] & io_lui_bit_26; // @[Library.scala 314:48]
-  wire  _io_bge_T_7 = _io_bge_T_4 & io_jal_bit_27 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 311:48]
-  wire  _io_bltu_T_1 = io_lui_bit_17 & io_lui_bit_18; // @[Library.scala 314:48]
-  wire  _io_bltu_T_2 = _io_bltu_T_1 & io_jalr_bit_19; // @[Library.scala 311:48]
-  wire  _io_bltu_T_4 = _io_bltu_T_2 & io_inst[6] & io_lui_bit_26; // @[Library.scala 314:48]
-  wire  _io_bltu_T_7 = _io_bltu_T_4 & io_jal_bit_27 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 311:48]
-  wire  _io_bgeu_T_2 = io_lui_bit_17 & io_lui_bit_18 & io_lui_bit_19; // @[Library.scala 314:48]
-  wire  _io_bgeu_T_4 = io_lui_bit_17 & io_lui_bit_18 & io_lui_bit_19 & io_inst[6] & io_lui_bit_26; // @[Library.scala 314:48]
-  wire  _io_bgeu_T_7 = _io_bgeu_T_4 & io_jal_bit_27 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 311:48]
-  wire  _io_lb_T_3 = io_jalr_bit_17 & io_jalr_bit_18 & io_jalr_bit_19 & io_lui_bit_25; // @[Library.scala 311:48]
-  wire  _io_lb_T_4 = io_jalr_bit_17 & io_jalr_bit_18 & io_jalr_bit_19 & io_lui_bit_25 & io_auipc_bit_26; // @[Library.scala 311:48]
+  wire  io_lui_bit_1 = io_inst[30]; // @[Library.scala 318:23]
+  wire  io_lui_bit_2 = io_inst[29]; // @[Library.scala 318:23]
+  wire  io_lui_bit_3 = io_inst[28]; // @[Library.scala 318:23]
+  wire  io_lui_bit_4 = io_inst[27]; // @[Library.scala 318:23]
+  wire  io_lui_bit_5 = io_inst[26]; // @[Library.scala 318:23]
+  wire  io_lui_bit_6 = io_inst[25]; // @[Library.scala 318:23]
+  wire  io_lui_bit_7 = io_inst[24]; // @[Library.scala 318:23]
+  wire  io_lui_bit_8 = io_inst[23]; // @[Library.scala 318:23]
+  wire  io_lui_bit_9 = io_inst[22]; // @[Library.scala 318:23]
+  wire  io_lui_bit_10 = io_inst[21]; // @[Library.scala 318:23]
+  wire  io_lui_bit_12 = io_inst[19]; // @[Library.scala 318:23]
+  wire  io_lui_bit_13 = io_inst[18]; // @[Library.scala 318:23]
+  wire  io_lui_bit_14 = io_inst[17]; // @[Library.scala 318:23]
+  wire  io_lui_bit_15 = io_inst[16]; // @[Library.scala 318:23]
+  wire  io_lui_bit_16 = io_inst[15]; // @[Library.scala 318:23]
+  wire  io_lui_bit_17 = io_inst[14]; // @[Library.scala 318:23]
+  wire  io_lui_bit_18 = io_inst[13]; // @[Library.scala 318:23]
+  wire  io_lui_bit_19 = io_inst[12]; // @[Library.scala 318:23]
+  wire  io_lui_bit_25 = ~io_inst[6]; // @[Library.scala 312:19]
+  wire  io_lui_bit_26 = io_inst[5]; // @[Library.scala 315:23]
+  wire  io_lui_bit_27 = io_inst[4]; // @[Library.scala 315:23]
+  wire  _io_lui_T_2 = io_lui_bit_25 & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 316:48]
+  wire  io_lui_bit_28 = ~io_inst[3]; // @[Library.scala 312:19]
+  wire  _io_lui_T_3 = _io_lui_T_2 & io_lui_bit_28; // @[Library.scala 313:48]
+  wire  io_lui_bit_29 = io_inst[2]; // @[Library.scala 315:23]
+  wire  io_lui_bit_30 = io_inst[1]; // @[Library.scala 315:23]
+  wire  io_lui_bit_31 = io_inst[0]; // @[Library.scala 315:23]
+  wire  io_auipc_bit_26 = ~io_lui_bit_26; // @[Library.scala 312:19]
+  wire  _io_auipc_T_1 = io_lui_bit_25 & io_auipc_bit_26; // @[Library.scala 313:48]
+  wire  _io_auipc_T_2 = _io_auipc_T_1 & io_lui_bit_27; // @[Library.scala 316:48]
+  wire  _io_auipc_T_3 = _io_auipc_T_2 & io_lui_bit_28; // @[Library.scala 313:48]
+  wire  _io_jal_T_1 = io_inst[6] & io_lui_bit_26; // @[Library.scala 316:48]
+  wire  io_jal_bit_27 = ~io_lui_bit_27; // @[Library.scala 312:19]
+  wire  _io_jal_T_2 = _io_jal_T_1 & io_jal_bit_27; // @[Library.scala 313:48]
+  wire  io_jalr_bit_17 = ~io_lui_bit_17; // @[Library.scala 312:19]
+  wire  io_jalr_bit_18 = ~io_lui_bit_18; // @[Library.scala 312:19]
+  wire  _io_jalr_T_1 = io_jalr_bit_17 & io_jalr_bit_18; // @[Library.scala 313:48]
+  wire  io_jalr_bit_19 = ~io_lui_bit_19; // @[Library.scala 312:19]
+  wire  _io_jalr_T_2 = io_jalr_bit_17 & io_jalr_bit_18 & io_jalr_bit_19; // @[Library.scala 313:48]
+  wire  _io_jalr_T_4 = _io_jalr_T_2 & io_inst[6] & io_lui_bit_26; // @[Library.scala 316:48]
+  wire  _io_jalr_T_6 = _io_jalr_T_4 & io_jal_bit_27 & io_lui_bit_28; // @[Library.scala 313:48]
+  wire  io_beq_bit_29 = ~io_lui_bit_29; // @[Library.scala 312:19]
+  wire  _io_beq_T_7 = _io_jalr_T_4 & io_jal_bit_27 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 313:48]
+  wire  _io_bne_T_2 = _io_jalr_T_1 & io_lui_bit_19; // @[Library.scala 316:48]
+  wire  _io_bne_T_4 = _io_jalr_T_1 & io_lui_bit_19 & io_inst[6] & io_lui_bit_26; // @[Library.scala 316:48]
+  wire  _io_bne_T_7 = _io_bne_T_4 & io_jal_bit_27 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 313:48]
+  wire  _io_blt_T_1 = io_lui_bit_17 & io_jalr_bit_18; // @[Library.scala 313:48]
+  wire  _io_blt_T_2 = io_lui_bit_17 & io_jalr_bit_18 & io_jalr_bit_19; // @[Library.scala 313:48]
+  wire  _io_blt_T_4 = _io_blt_T_2 & io_inst[6] & io_lui_bit_26; // @[Library.scala 316:48]
+  wire  _io_blt_T_7 = _io_blt_T_4 & io_jal_bit_27 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 313:48]
+  wire  _io_bge_T_2 = _io_blt_T_1 & io_lui_bit_19; // @[Library.scala 316:48]
+  wire  _io_bge_T_4 = _io_blt_T_1 & io_lui_bit_19 & io_inst[6] & io_lui_bit_26; // @[Library.scala 316:48]
+  wire  _io_bge_T_7 = _io_bge_T_4 & io_jal_bit_27 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 313:48]
+  wire  _io_bltu_T_1 = io_lui_bit_17 & io_lui_bit_18; // @[Library.scala 316:48]
+  wire  _io_bltu_T_2 = _io_bltu_T_1 & io_jalr_bit_19; // @[Library.scala 313:48]
+  wire  _io_bltu_T_4 = _io_bltu_T_2 & io_inst[6] & io_lui_bit_26; // @[Library.scala 316:48]
+  wire  _io_bltu_T_7 = _io_bltu_T_4 & io_jal_bit_27 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 313:48]
+  wire  _io_bgeu_T_2 = io_lui_bit_17 & io_lui_bit_18 & io_lui_bit_19; // @[Library.scala 316:48]
+  wire  _io_bgeu_T_4 = io_lui_bit_17 & io_lui_bit_18 & io_lui_bit_19 & io_inst[6] & io_lui_bit_26; // @[Library.scala 316:48]
+  wire  _io_bgeu_T_7 = _io_bgeu_T_4 & io_jal_bit_27 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 313:48]
+  wire  _io_lb_T_3 = io_jalr_bit_17 & io_jalr_bit_18 & io_jalr_bit_19 & io_lui_bit_25; // @[Library.scala 313:48]
+  wire  _io_lb_T_4 = io_jalr_bit_17 & io_jalr_bit_18 & io_jalr_bit_19 & io_lui_bit_25 & io_auipc_bit_26; // @[Library.scala 313:48]
   wire  _io_lb_T_7 = io_jalr_bit_17 & io_jalr_bit_18 & io_jalr_bit_19 & io_lui_bit_25 & io_auipc_bit_26 & io_jal_bit_27
-     & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 311:48]
-  wire  _io_lh_T_3 = _io_bne_T_2 & io_lui_bit_25; // @[Library.scala 311:48]
-  wire  _io_lh_T_7 = _io_bne_T_2 & io_lui_bit_25 & io_auipc_bit_26 & io_jal_bit_27 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 311:48]
-  wire  _io_lw_T_1 = io_jalr_bit_17 & io_lui_bit_18; // @[Library.scala 314:48]
-  wire  _io_lw_T_3 = _io_lw_T_1 & io_jalr_bit_19 & io_lui_bit_25; // @[Library.scala 311:48]
-  wire  _io_lw_T_4 = _io_lw_T_1 & io_jalr_bit_19 & io_lui_bit_25 & io_auipc_bit_26; // @[Library.scala 311:48]
+     & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 313:48]
+  wire  _io_lh_T_3 = _io_bne_T_2 & io_lui_bit_25; // @[Library.scala 313:48]
+  wire  _io_lh_T_7 = _io_bne_T_2 & io_lui_bit_25 & io_auipc_bit_26 & io_jal_bit_27 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 313:48]
+  wire  _io_lw_T_1 = io_jalr_bit_17 & io_lui_bit_18; // @[Library.scala 316:48]
+  wire  _io_lw_T_3 = _io_lw_T_1 & io_jalr_bit_19 & io_lui_bit_25; // @[Library.scala 313:48]
+  wire  _io_lw_T_4 = _io_lw_T_1 & io_jalr_bit_19 & io_lui_bit_25 & io_auipc_bit_26; // @[Library.scala 313:48]
   wire  _io_lw_T_7 = _io_lw_T_1 & io_jalr_bit_19 & io_lui_bit_25 & io_auipc_bit_26 & io_jal_bit_27 & io_lui_bit_28 &
-    io_beq_bit_29; // @[Library.scala 311:48]
-  wire  _io_lbu_T_4 = io_lui_bit_17 & io_jalr_bit_18 & io_jalr_bit_19 & io_lui_bit_25 & io_auipc_bit_26; // @[Library.scala 311:48]
+    io_beq_bit_29; // @[Library.scala 313:48]
+  wire  _io_lbu_T_4 = io_lui_bit_17 & io_jalr_bit_18 & io_jalr_bit_19 & io_lui_bit_25 & io_auipc_bit_26; // @[Library.scala 313:48]
   wire  _io_lbu_T_7 = io_lui_bit_17 & io_jalr_bit_18 & io_jalr_bit_19 & io_lui_bit_25 & io_auipc_bit_26 & io_jal_bit_27
-     & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 311:48]
-  wire  _io_lhu_T_7 = _io_bge_T_2 & io_lui_bit_25 & io_auipc_bit_26 & io_jal_bit_27 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 311:48]
-  wire  _io_sb_T_4 = _io_lb_T_3 & io_lui_bit_26; // @[Library.scala 314:48]
-  wire  _io_sb_T_7 = _io_sb_T_4 & io_jal_bit_27 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 311:48]
-  wire  _io_sh_T_4 = _io_lh_T_3 & io_lui_bit_26; // @[Library.scala 314:48]
-  wire  _io_sh_T_7 = _io_sh_T_4 & io_jal_bit_27 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 311:48]
-  wire  _io_sw_T_4 = _io_lw_T_3 & io_lui_bit_26; // @[Library.scala 314:48]
-  wire  _io_sw_T_7 = _io_sw_T_4 & io_jal_bit_27 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 311:48]
-  wire  io_fence_bit = ~io_inst[31]; // @[Library.scala 310:19]
-  wire  io_fence_bit_1 = ~io_lui_bit_1; // @[Library.scala 310:19]
-  wire  _io_fence_T_1 = io_fence_bit & io_fence_bit_1; // @[Library.scala 311:48]
-  wire  io_fence_bit_2 = ~io_lui_bit_2; // @[Library.scala 310:19]
-  wire  _io_fence_T_2 = io_fence_bit & io_fence_bit_1 & io_fence_bit_2; // @[Library.scala 311:48]
-  wire  io_fence_bit_3 = ~io_lui_bit_3; // @[Library.scala 310:19]
-  wire  _io_fence_T_3 = io_fence_bit & io_fence_bit_1 & io_fence_bit_2 & io_fence_bit_3; // @[Library.scala 311:48]
-  wire  io_fence_bit_12 = ~io_lui_bit_12; // @[Library.scala 310:19]
-  wire  io_fence_bit_13 = ~io_lui_bit_13; // @[Library.scala 310:19]
-  wire  io_fence_bit_14 = ~io_lui_bit_14; // @[Library.scala 310:19]
-  wire  io_fence_bit_15 = ~io_lui_bit_15; // @[Library.scala 310:19]
-  wire  io_fence_bit_16 = ~io_lui_bit_16; // @[Library.scala 310:19]
-  wire  _io_addi_T_5 = _io_lb_T_4 & io_lui_bit_27; // @[Library.scala 314:48]
-  wire  _io_addi_T_7 = _io_addi_T_5 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 311:48]
-  wire  _io_slti_T_5 = _io_lw_T_4 & io_lui_bit_27; // @[Library.scala 314:48]
-  wire  _io_slti_T_7 = _io_slti_T_5 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 311:48]
-  wire  _io_sltiu_T_2 = io_jalr_bit_17 & io_lui_bit_18 & io_lui_bit_19; // @[Library.scala 314:48]
-  wire  _io_sltiu_T_4 = _io_sltiu_T_2 & io_lui_bit_25 & io_auipc_bit_26; // @[Library.scala 311:48]
-  wire  _io_sltiu_T_5 = _io_sltiu_T_4 & io_lui_bit_27; // @[Library.scala 314:48]
-  wire  _io_sltiu_T_7 = _io_sltiu_T_5 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 311:48]
-  wire  _io_xori_T_5 = _io_lbu_T_4 & io_lui_bit_27; // @[Library.scala 314:48]
-  wire  _io_xori_T_7 = _io_xori_T_5 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 311:48]
-  wire  _io_ori_T_4 = _io_bltu_T_1 & io_jalr_bit_19 & io_lui_bit_25 & io_auipc_bit_26; // @[Library.scala 311:48]
-  wire  _io_ori_T_5 = _io_ori_T_4 & io_lui_bit_27; // @[Library.scala 314:48]
-  wire  _io_ori_T_7 = _io_ori_T_5 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 311:48]
-  wire  _io_andi_T_4 = _io_bgeu_T_2 & io_lui_bit_25 & io_auipc_bit_26; // @[Library.scala 311:48]
-  wire  _io_andi_T_5 = _io_andi_T_4 & io_lui_bit_27; // @[Library.scala 314:48]
-  wire  _io_andi_T_7 = _io_andi_T_5 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 311:48]
-  wire  io_slli_bit_4 = ~io_lui_bit_4; // @[Library.scala 310:19]
-  wire  _io_slli_T_4 = io_fence_bit & io_fence_bit_1 & io_fence_bit_2 & io_fence_bit_3 & io_slli_bit_4; // @[Library.scala 311:48]
-  wire  io_slli_bit_5 = ~io_lui_bit_5; // @[Library.scala 310:19]
-  wire  _io_slli_T_5 = io_fence_bit & io_fence_bit_1 & io_fence_bit_2 & io_fence_bit_3 & io_slli_bit_4 & io_slli_bit_5; // @[Library.scala 311:48]
-  wire  io_slli_bit_6 = ~io_lui_bit_6; // @[Library.scala 310:19]
+     & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 313:48]
+  wire  _io_lhu_T_7 = _io_bge_T_2 & io_lui_bit_25 & io_auipc_bit_26 & io_jal_bit_27 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 313:48]
+  wire  _io_sb_T_4 = _io_lb_T_3 & io_lui_bit_26; // @[Library.scala 316:48]
+  wire  _io_sb_T_7 = _io_sb_T_4 & io_jal_bit_27 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 313:48]
+  wire  _io_sh_T_4 = _io_lh_T_3 & io_lui_bit_26; // @[Library.scala 316:48]
+  wire  _io_sh_T_7 = _io_sh_T_4 & io_jal_bit_27 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 313:48]
+  wire  _io_sw_T_4 = _io_lw_T_3 & io_lui_bit_26; // @[Library.scala 316:48]
+  wire  _io_sw_T_7 = _io_sw_T_4 & io_jal_bit_27 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 313:48]
+  wire  io_fence_bit = ~io_inst[31]; // @[Library.scala 312:19]
+  wire  io_fence_bit_1 = ~io_lui_bit_1; // @[Library.scala 312:19]
+  wire  _io_fence_T_1 = io_fence_bit & io_fence_bit_1; // @[Library.scala 313:48]
+  wire  io_fence_bit_2 = ~io_lui_bit_2; // @[Library.scala 312:19]
+  wire  _io_fence_T_2 = io_fence_bit & io_fence_bit_1 & io_fence_bit_2; // @[Library.scala 313:48]
+  wire  io_fence_bit_3 = ~io_lui_bit_3; // @[Library.scala 312:19]
+  wire  _io_fence_T_3 = io_fence_bit & io_fence_bit_1 & io_fence_bit_2 & io_fence_bit_3; // @[Library.scala 313:48]
+  wire  io_fence_bit_12 = ~io_lui_bit_12; // @[Library.scala 312:19]
+  wire  io_fence_bit_13 = ~io_lui_bit_13; // @[Library.scala 312:19]
+  wire  io_fence_bit_14 = ~io_lui_bit_14; // @[Library.scala 312:19]
+  wire  io_fence_bit_15 = ~io_lui_bit_15; // @[Library.scala 312:19]
+  wire  io_fence_bit_16 = ~io_lui_bit_16; // @[Library.scala 312:19]
+  wire  _io_addi_T_5 = _io_lb_T_4 & io_lui_bit_27; // @[Library.scala 316:48]
+  wire  _io_addi_T_7 = _io_addi_T_5 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 313:48]
+  wire  _io_slti_T_5 = _io_lw_T_4 & io_lui_bit_27; // @[Library.scala 316:48]
+  wire  _io_slti_T_7 = _io_slti_T_5 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 313:48]
+  wire  _io_sltiu_T_2 = io_jalr_bit_17 & io_lui_bit_18 & io_lui_bit_19; // @[Library.scala 316:48]
+  wire  _io_sltiu_T_4 = _io_sltiu_T_2 & io_lui_bit_25 & io_auipc_bit_26; // @[Library.scala 313:48]
+  wire  _io_sltiu_T_5 = _io_sltiu_T_4 & io_lui_bit_27; // @[Library.scala 316:48]
+  wire  _io_sltiu_T_7 = _io_sltiu_T_5 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 313:48]
+  wire  _io_xori_T_5 = _io_lbu_T_4 & io_lui_bit_27; // @[Library.scala 316:48]
+  wire  _io_xori_T_7 = _io_xori_T_5 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 313:48]
+  wire  _io_ori_T_4 = _io_bltu_T_1 & io_jalr_bit_19 & io_lui_bit_25 & io_auipc_bit_26; // @[Library.scala 313:48]
+  wire  _io_ori_T_5 = _io_ori_T_4 & io_lui_bit_27; // @[Library.scala 316:48]
+  wire  _io_ori_T_7 = _io_ori_T_5 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 313:48]
+  wire  _io_andi_T_4 = _io_bgeu_T_2 & io_lui_bit_25 & io_auipc_bit_26; // @[Library.scala 313:48]
+  wire  _io_andi_T_5 = _io_andi_T_4 & io_lui_bit_27; // @[Library.scala 316:48]
+  wire  _io_andi_T_7 = _io_andi_T_5 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 313:48]
+  wire  io_slli_bit_4 = ~io_lui_bit_4; // @[Library.scala 312:19]
+  wire  _io_slli_T_4 = io_fence_bit & io_fence_bit_1 & io_fence_bit_2 & io_fence_bit_3 & io_slli_bit_4; // @[Library.scala 313:48]
+  wire  io_slli_bit_5 = ~io_lui_bit_5; // @[Library.scala 312:19]
+  wire  _io_slli_T_5 = io_fence_bit & io_fence_bit_1 & io_fence_bit_2 & io_fence_bit_3 & io_slli_bit_4 & io_slli_bit_5; // @[Library.scala 313:48]
+  wire  io_slli_bit_6 = ~io_lui_bit_6; // @[Library.scala 312:19]
   wire  _io_slli_T_6 = io_fence_bit & io_fence_bit_1 & io_fence_bit_2 & io_fence_bit_3 & io_slli_bit_4 & io_slli_bit_5
-     & io_slli_bit_6; // @[Library.scala 311:48]
+     & io_slli_bit_6; // @[Library.scala 313:48]
   wire  _io_slli_T_7 = io_fence_bit & io_fence_bit_1 & io_fence_bit_2 & io_fence_bit_3 & io_slli_bit_4 & io_slli_bit_5
-     & io_slli_bit_6 & io_jalr_bit_17; // @[Library.scala 311:48]
+     & io_slli_bit_6 & io_jalr_bit_17; // @[Library.scala 313:48]
   wire  _io_slli_T_8 = io_fence_bit & io_fence_bit_1 & io_fence_bit_2 & io_fence_bit_3 & io_slli_bit_4 & io_slli_bit_5
-     & io_slli_bit_6 & io_jalr_bit_17 & io_jalr_bit_18; // @[Library.scala 311:48]
-  wire  _io_slli_T_9 = _io_slli_T_8 & io_lui_bit_19; // @[Library.scala 314:48]
-  wire  _io_slli_T_10 = _io_slli_T_9 & io_lui_bit_25; // @[Library.scala 311:48]
-  wire  _io_slli_T_11 = _io_slli_T_9 & io_lui_bit_25 & io_auipc_bit_26; // @[Library.scala 311:48]
-  wire  _io_slli_T_12 = _io_slli_T_11 & io_lui_bit_27; // @[Library.scala 314:48]
-  wire  _io_slli_T_14 = _io_slli_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 311:48]
-  wire  _io_srli_T_7 = _io_slli_T_6 & io_lui_bit_17; // @[Library.scala 314:48]
-  wire  _io_srli_T_8 = _io_srli_T_7 & io_jalr_bit_18; // @[Library.scala 311:48]
-  wire  _io_srli_T_9 = _io_srli_T_8 & io_lui_bit_19; // @[Library.scala 314:48]
-  wire  _io_srli_T_10 = _io_srli_T_9 & io_lui_bit_25; // @[Library.scala 311:48]
-  wire  _io_srli_T_11 = _io_srli_T_9 & io_lui_bit_25 & io_auipc_bit_26; // @[Library.scala 311:48]
-  wire  _io_srli_T_12 = _io_srli_T_11 & io_lui_bit_27; // @[Library.scala 314:48]
-  wire  _io_srli_T_14 = _io_srli_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 311:48]
-  wire  _io_srai_T_1 = io_fence_bit & io_lui_bit_1; // @[Library.scala 314:48]
-  wire  _io_srai_T_2 = _io_srai_T_1 & io_fence_bit_2; // @[Library.scala 311:48]
-  wire  _io_srai_T_6 = _io_srai_T_1 & io_fence_bit_2 & io_fence_bit_3 & io_slli_bit_4 & io_slli_bit_5 & io_slli_bit_6; // @[Library.scala 311:48]
-  wire  _io_srai_T_7 = _io_srai_T_6 & io_lui_bit_17; // @[Library.scala 314:48]
-  wire  _io_srai_T_8 = _io_srai_T_7 & io_jalr_bit_18; // @[Library.scala 311:48]
-  wire  _io_srai_T_9 = _io_srai_T_8 & io_lui_bit_19; // @[Library.scala 314:48]
-  wire  _io_srai_T_10 = _io_srai_T_9 & io_lui_bit_25; // @[Library.scala 311:48]
-  wire  _io_srai_T_11 = _io_srai_T_9 & io_lui_bit_25 & io_auipc_bit_26; // @[Library.scala 311:48]
-  wire  _io_srai_T_12 = _io_srai_T_11 & io_lui_bit_27; // @[Library.scala 314:48]
-  wire  _io_srai_T_14 = _io_srai_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 311:48]
+     & io_slli_bit_6 & io_jalr_bit_17 & io_jalr_bit_18; // @[Library.scala 313:48]
+  wire  _io_slli_T_9 = _io_slli_T_8 & io_lui_bit_19; // @[Library.scala 316:48]
+  wire  _io_slli_T_10 = _io_slli_T_9 & io_lui_bit_25; // @[Library.scala 313:48]
+  wire  _io_slli_T_11 = _io_slli_T_9 & io_lui_bit_25 & io_auipc_bit_26; // @[Library.scala 313:48]
+  wire  _io_slli_T_12 = _io_slli_T_11 & io_lui_bit_27; // @[Library.scala 316:48]
+  wire  _io_slli_T_14 = _io_slli_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 313:48]
+  wire  _io_srli_T_7 = _io_slli_T_6 & io_lui_bit_17; // @[Library.scala 316:48]
+  wire  _io_srli_T_8 = _io_srli_T_7 & io_jalr_bit_18; // @[Library.scala 313:48]
+  wire  _io_srli_T_9 = _io_srli_T_8 & io_lui_bit_19; // @[Library.scala 316:48]
+  wire  _io_srli_T_10 = _io_srli_T_9 & io_lui_bit_25; // @[Library.scala 313:48]
+  wire  _io_srli_T_11 = _io_srli_T_9 & io_lui_bit_25 & io_auipc_bit_26; // @[Library.scala 313:48]
+  wire  _io_srli_T_12 = _io_srli_T_11 & io_lui_bit_27; // @[Library.scala 316:48]
+  wire  _io_srli_T_14 = _io_srli_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 313:48]
+  wire  _io_srai_T_1 = io_fence_bit & io_lui_bit_1; // @[Library.scala 316:48]
+  wire  _io_srai_T_2 = _io_srai_T_1 & io_fence_bit_2; // @[Library.scala 313:48]
+  wire  _io_srai_T_6 = _io_srai_T_1 & io_fence_bit_2 & io_fence_bit_3 & io_slli_bit_4 & io_slli_bit_5 & io_slli_bit_6; // @[Library.scala 313:48]
+  wire  _io_srai_T_7 = _io_srai_T_6 & io_lui_bit_17; // @[Library.scala 316:48]
+  wire  _io_srai_T_8 = _io_srai_T_7 & io_jalr_bit_18; // @[Library.scala 313:48]
+  wire  _io_srai_T_9 = _io_srai_T_8 & io_lui_bit_19; // @[Library.scala 316:48]
+  wire  _io_srai_T_10 = _io_srai_T_9 & io_lui_bit_25; // @[Library.scala 313:48]
+  wire  _io_srai_T_11 = _io_srai_T_9 & io_lui_bit_25 & io_auipc_bit_26; // @[Library.scala 313:48]
+  wire  _io_srai_T_12 = _io_srai_T_11 & io_lui_bit_27; // @[Library.scala 316:48]
+  wire  _io_srai_T_14 = _io_srai_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 313:48]
   wire  _io_add_T_10 = io_fence_bit & io_fence_bit_1 & io_fence_bit_2 & io_fence_bit_3 & io_slli_bit_4 & io_slli_bit_5
-     & io_slli_bit_6 & io_jalr_bit_17 & io_jalr_bit_18 & io_jalr_bit_19 & io_lui_bit_25; // @[Library.scala 311:48]
-  wire  _io_add_T_12 = _io_add_T_10 & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 314:48]
-  wire  _io_add_T_14 = _io_add_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 311:48]
+     & io_slli_bit_6 & io_jalr_bit_17 & io_jalr_bit_18 & io_jalr_bit_19 & io_lui_bit_25; // @[Library.scala 313:48]
+  wire  _io_add_T_12 = _io_add_T_10 & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 316:48]
+  wire  _io_add_T_14 = _io_add_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 313:48]
   wire  _io_sub_T_10 = _io_srai_T_1 & io_fence_bit_2 & io_fence_bit_3 & io_slli_bit_4 & io_slli_bit_5 & io_slli_bit_6 &
-    io_jalr_bit_17 & io_jalr_bit_18 & io_jalr_bit_19 & io_lui_bit_25; // @[Library.scala 311:48]
-  wire  _io_sub_T_12 = _io_sub_T_10 & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 314:48]
-  wire  _io_sub_T_14 = _io_sub_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 311:48]
-  wire  _io_slt_T_8 = _io_slli_T_7 & io_lui_bit_18; // @[Library.scala 314:48]
-  wire  _io_slt_T_10 = _io_slt_T_8 & io_jalr_bit_19 & io_lui_bit_25; // @[Library.scala 311:48]
-  wire  _io_slt_T_12 = _io_slt_T_10 & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 314:48]
-  wire  _io_slt_T_14 = _io_slt_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 311:48]
-  wire  _io_sltu_T_9 = _io_slli_T_7 & io_lui_bit_18 & io_lui_bit_19; // @[Library.scala 314:48]
-  wire  _io_sltu_T_10 = _io_sltu_T_9 & io_lui_bit_25; // @[Library.scala 311:48]
-  wire  _io_sltu_T_12 = _io_sltu_T_10 & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 314:48]
-  wire  _io_sltu_T_14 = _io_sltu_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 311:48]
-  wire  _io_xor_T_10 = _io_srli_T_7 & io_jalr_bit_18 & io_jalr_bit_19 & io_lui_bit_25; // @[Library.scala 311:48]
-  wire  _io_xor_T_12 = _io_xor_T_10 & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 314:48]
-  wire  _io_xor_T_14 = _io_xor_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 311:48]
-  wire  _io_or_T_8 = _io_slli_T_6 & io_lui_bit_17 & io_lui_bit_18; // @[Library.scala 314:48]
-  wire  _io_or_T_10 = _io_or_T_8 & io_jalr_bit_19 & io_lui_bit_25; // @[Library.scala 311:48]
-  wire  _io_or_T_12 = _io_or_T_10 & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 314:48]
-  wire  _io_or_T_14 = _io_or_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 311:48]
-  wire  _io_and_T_9 = _io_slli_T_6 & io_lui_bit_17 & io_lui_bit_18 & io_lui_bit_19; // @[Library.scala 314:48]
-  wire  _io_and_T_10 = _io_and_T_9 & io_lui_bit_25; // @[Library.scala 311:48]
-  wire  _io_and_T_12 = _io_and_T_10 & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 314:48]
-  wire  _io_and_T_14 = _io_and_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 311:48]
-  wire  _io_sll_T_12 = _io_slli_T_10 & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 314:48]
-  wire  _io_sll_T_14 = _io_sll_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 311:48]
-  wire  _io_srl_T_12 = _io_srli_T_10 & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 314:48]
-  wire  _io_srl_T_14 = _io_srl_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 311:48]
-  wire  _io_sra_T_12 = _io_srai_T_10 & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 314:48]
-  wire  _io_sra_T_14 = _io_sra_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 311:48]
-  wire  _io_mul_T_6 = _io_slli_T_5 & io_lui_bit_6; // @[Library.scala 314:48]
-  wire  _io_mul_T_7 = _io_mul_T_6 & io_jalr_bit_17; // @[Library.scala 311:48]
-  wire  _io_mul_T_8 = _io_mul_T_6 & io_jalr_bit_17 & io_jalr_bit_18; // @[Library.scala 311:48]
-  wire  _io_mul_T_10 = _io_mul_T_6 & io_jalr_bit_17 & io_jalr_bit_18 & io_jalr_bit_19 & io_lui_bit_25; // @[Library.scala 311:48]
-  wire  _io_mul_T_12 = _io_mul_T_10 & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 314:48]
-  wire  _io_mul_T_14 = _io_mul_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 311:48]
-  wire  _io_mulh_T_9 = _io_mul_T_8 & io_lui_bit_19; // @[Library.scala 314:48]
-  wire  _io_mulh_T_10 = _io_mulh_T_9 & io_lui_bit_25; // @[Library.scala 311:48]
-  wire  _io_mulh_T_12 = _io_mulh_T_10 & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 314:48]
-  wire  _io_mulh_T_14 = _io_mulh_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 311:48]
-  wire  _io_mulhsu_T_8 = _io_mul_T_7 & io_lui_bit_18; // @[Library.scala 314:48]
-  wire  _io_mulhsu_T_10 = _io_mulhsu_T_8 & io_jalr_bit_19 & io_lui_bit_25; // @[Library.scala 311:48]
-  wire  _io_mulhsu_T_12 = _io_mulhsu_T_10 & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 314:48]
-  wire  _io_mulhsu_T_14 = _io_mulhsu_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 311:48]
-  wire  _io_mulhu_T_9 = _io_mul_T_7 & io_lui_bit_18 & io_lui_bit_19; // @[Library.scala 314:48]
-  wire  _io_mulhu_T_10 = _io_mulhu_T_9 & io_lui_bit_25; // @[Library.scala 311:48]
-  wire  _io_mulhu_T_12 = _io_mulhu_T_10 & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 314:48]
-  wire  _io_mulhu_T_14 = _io_mulhu_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 311:48]
-  wire  _io_mulhr_T_2 = _io_fence_T_1 & io_lui_bit_2; // @[Library.scala 314:48]
-  wire  _io_mulhr_T_4 = _io_mulhr_T_2 & io_fence_bit_3 & io_slli_bit_4; // @[Library.scala 311:48]
-  wire  _io_mulhr_T_5 = _io_mulhr_T_2 & io_fence_bit_3 & io_slli_bit_4 & io_slli_bit_5; // @[Library.scala 311:48]
-  wire  _io_mulhr_T_6 = _io_mulhr_T_5 & io_lui_bit_6; // @[Library.scala 314:48]
-  wire  _io_mulhr_T_7 = _io_mulhr_T_6 & io_jalr_bit_17; // @[Library.scala 311:48]
-  wire  _io_mulhr_T_8 = _io_mulhr_T_6 & io_jalr_bit_17 & io_jalr_bit_18; // @[Library.scala 311:48]
-  wire  _io_mulhr_T_9 = _io_mulhr_T_8 & io_lui_bit_19; // @[Library.scala 314:48]
-  wire  _io_mulhr_T_10 = _io_mulhr_T_9 & io_lui_bit_25; // @[Library.scala 311:48]
-  wire  _io_mulhr_T_12 = _io_mulhr_T_10 & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 314:48]
-  wire  _io_mulhr_T_14 = _io_mulhr_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 311:48]
-  wire  _io_mulhsur_T_8 = _io_mulhr_T_7 & io_lui_bit_18; // @[Library.scala 314:48]
-  wire  _io_mulhsur_T_10 = _io_mulhsur_T_8 & io_jalr_bit_19 & io_lui_bit_25; // @[Library.scala 311:48]
-  wire  _io_mulhsur_T_12 = _io_mulhsur_T_10 & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 314:48]
-  wire  _io_mulhsur_T_14 = _io_mulhsur_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 311:48]
-  wire  _io_mulhur_T_9 = _io_mulhr_T_7 & io_lui_bit_18 & io_lui_bit_19; // @[Library.scala 314:48]
-  wire  _io_mulhur_T_10 = _io_mulhur_T_9 & io_lui_bit_25; // @[Library.scala 311:48]
-  wire  _io_mulhur_T_12 = _io_mulhur_T_10 & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 314:48]
-  wire  _io_mulhur_T_14 = _io_mulhur_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 311:48]
-  wire  _io_dmulh_T_5 = _io_slli_T_4 & io_lui_bit_5; // @[Library.scala 314:48]
-  wire  _io_dmulh_T_8 = _io_dmulh_T_5 & io_slli_bit_6 & io_jalr_bit_17 & io_jalr_bit_18; // @[Library.scala 311:48]
-  wire  _io_dmulh_T_9 = _io_dmulh_T_8 & io_lui_bit_19; // @[Library.scala 314:48]
-  wire  _io_dmulh_T_10 = _io_dmulh_T_9 & io_lui_bit_25; // @[Library.scala 311:48]
-  wire  _io_dmulh_T_12 = _io_dmulh_T_10 & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 314:48]
-  wire  _io_dmulh_T_14 = _io_dmulh_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 311:48]
-  wire  _io_dmulhr_T_5 = _io_mulhr_T_4 & io_lui_bit_5; // @[Library.scala 314:48]
-  wire  _io_dmulhr_T_8 = _io_dmulhr_T_5 & io_slli_bit_6 & io_jalr_bit_17 & io_jalr_bit_18; // @[Library.scala 311:48]
-  wire  _io_dmulhr_T_9 = _io_dmulhr_T_8 & io_lui_bit_19; // @[Library.scala 314:48]
-  wire  _io_dmulhr_T_10 = _io_dmulhr_T_9 & io_lui_bit_25; // @[Library.scala 311:48]
-  wire  _io_dmulhr_T_12 = _io_dmulhr_T_10 & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 314:48]
-  wire  _io_dmulhr_T_14 = _io_dmulhr_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 311:48]
-  wire  _io_fsub_T_4 = _io_fence_T_3 & io_lui_bit_4; // @[Library.scala 314:48]
-  wire  _io_fsub_T_5 = _io_fsub_T_4 & io_slli_bit_5; // @[Library.scala 311:48]
-  wire  _io_fmul_T_3 = _io_fence_T_2 & io_lui_bit_3; // @[Library.scala 314:48]
-  wire  _io_fsqrt_T_3 = _io_srai_T_2 & io_lui_bit_3; // @[Library.scala 314:48]
-  wire  io_fcvtws_bit_7 = ~io_lui_bit_7; // @[Library.scala 310:19]
-  wire  io_fcvtws_bit_8 = ~io_lui_bit_8; // @[Library.scala 310:19]
-  wire  io_fcvtws_bit_9 = ~io_lui_bit_9; // @[Library.scala 310:19]
-  wire  io_fcvtws_bit_10 = ~io_lui_bit_10; // @[Library.scala 310:19]
-  wire  io_fcvtws_bit_11 = ~io_inst[20]; // @[Library.scala 310:19]
-  wire  _io_clb_T_2 = io_fence_bit & io_lui_bit_1 & io_lui_bit_2; // @[Library.scala 314:48]
-  wire  _io_clb_T_7 = _io_clb_T_2 & io_fence_bit_3 & io_slli_bit_4 & io_slli_bit_5 & io_slli_bit_6 & io_fcvtws_bit_7; // @[Library.scala 311:48]
-  wire  _io_clb_T_8 = _io_clb_T_7 & io_lui_bit_8; // @[Library.scala 314:48]
-  wire  _io_clb_T_13 = _io_clb_T_8 & io_fcvtws_bit_9 & io_fcvtws_bit_10 & io_fcvtws_bit_11 & io_jalr_bit_17 &
-    io_jalr_bit_18; // @[Library.scala 311:48]
-  wire  _io_clb_T_14 = _io_clb_T_13 & io_lui_bit_19; // @[Library.scala 314:48]
-  wire  _io_clb_T_16 = _io_clb_T_14 & io_lui_bit_25 & io_auipc_bit_26; // @[Library.scala 311:48]
-  wire  _io_clb_T_17 = _io_clb_T_16 & io_lui_bit_27; // @[Library.scala 314:48]
-  wire  _io_clb_T_19 = _io_clb_T_17 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 311:48]
-  wire  _io_clz_T_9 = _io_clb_T_2 & io_fence_bit_3 & io_slli_bit_4 & io_slli_bit_5 & io_slli_bit_6 & io_fcvtws_bit_7 &
-    io_fcvtws_bit_8 & io_fcvtws_bit_9; // @[Library.scala 311:48]
-  wire  _io_clz_T_10 = _io_clb_T_2 & io_fence_bit_3 & io_slli_bit_4 & io_slli_bit_5 & io_slli_bit_6 & io_fcvtws_bit_7 &
-    io_fcvtws_bit_8 & io_fcvtws_bit_9 & io_fcvtws_bit_10; // @[Library.scala 311:48]
-  wire  _io_clz_T_13 = _io_clb_T_2 & io_fence_bit_3 & io_slli_bit_4 & io_slli_bit_5 & io_slli_bit_6 & io_fcvtws_bit_7 &
-    io_fcvtws_bit_8 & io_fcvtws_bit_9 & io_fcvtws_bit_10 & io_fcvtws_bit_11 & io_jalr_bit_17 & io_jalr_bit_18; // @[Library.scala 311:48]
-  wire  _io_clz_T_14 = _io_clz_T_13 & io_lui_bit_19; // @[Library.scala 314:48]
-  wire  _io_clz_T_16 = _io_clz_T_14 & io_lui_bit_25 & io_auipc_bit_26; // @[Library.scala 311:48]
-  wire  _io_clz_T_17 = _io_clz_T_16 & io_lui_bit_27; // @[Library.scala 314:48]
-  wire  _io_clz_T_19 = _io_clz_T_17 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 311:48]
-  wire  _io_ctz_T_11 = _io_clz_T_10 & io_inst[20]; // @[Library.scala 314:48]
-  wire  _io_ctz_T_13 = _io_ctz_T_11 & io_jalr_bit_17 & io_jalr_bit_18; // @[Library.scala 311:48]
-  wire  _io_ctz_T_14 = _io_ctz_T_13 & io_lui_bit_19; // @[Library.scala 314:48]
-  wire  _io_ctz_T_16 = _io_ctz_T_14 & io_lui_bit_25 & io_auipc_bit_26; // @[Library.scala 311:48]
-  wire  _io_ctz_T_17 = _io_ctz_T_16 & io_lui_bit_27; // @[Library.scala 314:48]
-  wire  _io_ctz_T_19 = _io_ctz_T_17 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 311:48]
-  wire  _io_pcnt_T_10 = _io_clz_T_9 & io_lui_bit_10; // @[Library.scala 314:48]
-  wire  _io_pcnt_T_13 = _io_pcnt_T_10 & io_fcvtws_bit_11 & io_jalr_bit_17 & io_jalr_bit_18; // @[Library.scala 311:48]
-  wire  _io_pcnt_T_14 = _io_pcnt_T_13 & io_lui_bit_19; // @[Library.scala 314:48]
-  wire  _io_pcnt_T_16 = _io_pcnt_T_14 & io_lui_bit_25 & io_auipc_bit_26; // @[Library.scala 311:48]
-  wire  _io_pcnt_T_17 = _io_pcnt_T_16 & io_lui_bit_27; // @[Library.scala 314:48]
-  wire  _io_pcnt_T_19 = _io_pcnt_T_17 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 311:48]
-  wire  _io_min_T_7 = _io_fsub_T_5 & io_lui_bit_6 & io_lui_bit_17; // @[Library.scala 314:48]
-  wire  _io_min_T_8 = _io_min_T_7 & io_jalr_bit_18; // @[Library.scala 311:48]
-  wire  _io_min_T_10 = _io_min_T_7 & io_jalr_bit_18 & io_jalr_bit_19 & io_lui_bit_25; // @[Library.scala 311:48]
-  wire  _io_min_T_12 = _io_min_T_10 & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 314:48]
-  wire  _io_min_T_14 = _io_min_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 311:48]
-  wire  _io_minu_T_8 = _io_fsub_T_5 & io_lui_bit_6 & io_lui_bit_17 & io_lui_bit_18; // @[Library.scala 314:48]
-  wire  _io_minu_T_10 = _io_minu_T_8 & io_jalr_bit_19 & io_lui_bit_25; // @[Library.scala 311:48]
-  wire  _io_minu_T_12 = _io_minu_T_10 & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 314:48]
-  wire  _io_minu_T_14 = _io_minu_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 311:48]
-  wire  _io_max_T_9 = _io_min_T_8 & io_lui_bit_19; // @[Library.scala 314:48]
-  wire  _io_max_T_10 = _io_max_T_9 & io_lui_bit_25; // @[Library.scala 311:48]
-  wire  _io_max_T_12 = _io_max_T_10 & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 314:48]
-  wire  _io_max_T_14 = _io_max_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 311:48]
-  wire  _io_maxu_T_9 = _io_fsub_T_5 & io_lui_bit_6 & io_lui_bit_17 & io_lui_bit_18 & io_lui_bit_19; // @[Library.scala 314:48]
-  wire  _io_maxu_T_10 = _io_maxu_T_9 & io_lui_bit_25; // @[Library.scala 311:48]
-  wire  _io_maxu_T_12 = _io_maxu_T_10 & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 314:48]
-  wire  _io_maxu_T_14 = _io_maxu_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 311:48]
-  wire  _io_getvl_T_6 = _io_fmul_T_3 & io_jalr_bit_17 & io_jalr_bit_18 & io_jalr_bit_19; // @[Library.scala 311:48]
-  wire  _io_getvl_T_9 = _io_getvl_T_6 & io_inst[6] & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 314:48]
-  wire  _io_getvl_T_10 = _io_getvl_T_9 & io_lui_bit_28; // @[Library.scala 311:48]
-  wire  _io_getvl_T_13 = _io_getvl_T_10 & io_lui_bit_29 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 314:48]
-  wire  _io_getvl_T_15 = io_inst[26:25] != 2'h3; // @[Decode.scala 688:89]
-  wire  _io_getmaxvl_T_16 = _io_fmul_T_3 & io_fcvtws_bit_7 & io_fcvtws_bit_8 & io_fcvtws_bit_9 & io_fcvtws_bit_10 &
-    io_fcvtws_bit_11 & io_fence_bit_12 & io_fence_bit_13 & io_fence_bit_14 & io_fence_bit_15 & io_fence_bit_16 &
-    io_jalr_bit_17 & io_jalr_bit_18 & io_jalr_bit_19; // @[Library.scala 311:48]
-  wire  _io_getmaxvl_T_19 = _io_getmaxvl_T_16 & io_inst[6] & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 314:48]
-  wire  _io_getmaxvl_T_20 = _io_getmaxvl_T_19 & io_lui_bit_28; // @[Library.scala 311:48]
-  wire  _io_getmaxvl_T_23 = _io_getmaxvl_T_20 & io_lui_bit_29 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 314:48]
-  wire  _io_vld_T_4 = io_fence_bit & io_fence_bit_1 & io_fence_bit_2 & io_slli_bit_6 & io_jalr_bit_17; // @[Library.scala 311:48]
-  wire  _io_vst_T_4 = _io_mulhr_T_2 & io_slli_bit_6 & io_jalr_bit_17; // @[Library.scala 311:48]
-  wire  _io_vst_T_9 = _io_vst_T_4 & io_lui_bit_27 & io_inst[3] & io_lui_bit_29 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 314:48]
-  wire  _io_vst_T_14 = _io_clb_T_2 & io_slli_bit_6 & io_jalr_bit_17; // @[Library.scala 311:48]
-  wire  _io_vst_T_19 = _io_vst_T_14 & io_lui_bit_27 & io_inst[3] & io_lui_bit_29 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 314:48]
-  wire  _vconv_T_17 = _io_fsqrt_T_3 & io_slli_bit_4 & io_slli_bit_5 & io_slli_bit_6 & io_fcvtws_bit_7 & io_fcvtws_bit_8
-     & io_fcvtws_bit_9 & io_fcvtws_bit_10 & io_fcvtws_bit_11 & io_fence_bit_12 & io_fence_bit_13 & io_fence_bit_14 &
-    io_fence_bit_15 & io_fence_bit_16 & io_jalr_bit_17; // @[Library.scala 311:48]
-  wire  vconv = _vconv_T_17 & io_lui_bit_27 & io_inst[3] & io_lui_bit_29 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 314:48]
+    io_jalr_bit_17 & io_jalr_bit_18 & io_jalr_bit_19 & io_lui_bit_25; // @[Library.scala 313:48]
+  wire  _io_sub_T_12 = _io_sub_T_10 & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 316:48]
+  wire  _io_sub_T_14 = _io_sub_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 313:48]
+  wire  _io_slt_T_8 = _io_slli_T_7 & io_lui_bit_18; // @[Library.scala 316:48]
+  wire  _io_slt_T_10 = _io_slt_T_8 & io_jalr_bit_19 & io_lui_bit_25; // @[Library.scala 313:48]
+  wire  _io_slt_T_12 = _io_slt_T_10 & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 316:48]
+  wire  _io_slt_T_14 = _io_slt_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 313:48]
+  wire  _io_sltu_T_9 = _io_slli_T_7 & io_lui_bit_18 & io_lui_bit_19; // @[Library.scala 316:48]
+  wire  _io_sltu_T_10 = _io_sltu_T_9 & io_lui_bit_25; // @[Library.scala 313:48]
+  wire  _io_sltu_T_12 = _io_sltu_T_10 & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 316:48]
+  wire  _io_sltu_T_14 = _io_sltu_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 313:48]
+  wire  _io_xor_T_10 = _io_srli_T_7 & io_jalr_bit_18 & io_jalr_bit_19 & io_lui_bit_25; // @[Library.scala 313:48]
+  wire  _io_xor_T_12 = _io_xor_T_10 & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 316:48]
+  wire  _io_xor_T_14 = _io_xor_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 313:48]
+  wire  _io_or_T_8 = _io_slli_T_6 & io_lui_bit_17 & io_lui_bit_18; // @[Library.scala 316:48]
+  wire  _io_or_T_10 = _io_or_T_8 & io_jalr_bit_19 & io_lui_bit_25; // @[Library.scala 313:48]
+  wire  _io_or_T_12 = _io_or_T_10 & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 316:48]
+  wire  _io_or_T_14 = _io_or_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 313:48]
+  wire  _io_and_T_9 = _io_slli_T_6 & io_lui_bit_17 & io_lui_bit_18 & io_lui_bit_19; // @[Library.scala 316:48]
+  wire  _io_and_T_10 = _io_and_T_9 & io_lui_bit_25; // @[Library.scala 313:48]
+  wire  _io_and_T_12 = _io_and_T_10 & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 316:48]
+  wire  _io_and_T_14 = _io_and_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 313:48]
+  wire  _io_sll_T_12 = _io_slli_T_10 & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 316:48]
+  wire  _io_sll_T_14 = _io_sll_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 313:48]
+  wire  _io_srl_T_12 = _io_srli_T_10 & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 316:48]
+  wire  _io_srl_T_14 = _io_srl_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 313:48]
+  wire  _io_sra_T_12 = _io_srai_T_10 & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 316:48]
+  wire  _io_sra_T_14 = _io_sra_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 313:48]
+  wire  _io_mul_T_6 = _io_slli_T_5 & io_lui_bit_6; // @[Library.scala 316:48]
+  wire  _io_mul_T_7 = _io_mul_T_6 & io_jalr_bit_17; // @[Library.scala 313:48]
+  wire  _io_mul_T_8 = _io_mul_T_6 & io_jalr_bit_17 & io_jalr_bit_18; // @[Library.scala 313:48]
+  wire  _io_mul_T_10 = _io_mul_T_6 & io_jalr_bit_17 & io_jalr_bit_18 & io_jalr_bit_19 & io_lui_bit_25; // @[Library.scala 313:48]
+  wire  _io_mul_T_12 = _io_mul_T_10 & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 316:48]
+  wire  _io_mul_T_14 = _io_mul_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 313:48]
+  wire  _io_mulh_T_9 = _io_mul_T_8 & io_lui_bit_19; // @[Library.scala 316:48]
+  wire  _io_mulh_T_10 = _io_mulh_T_9 & io_lui_bit_25; // @[Library.scala 313:48]
+  wire  _io_mulh_T_12 = _io_mulh_T_10 & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 316:48]
+  wire  _io_mulh_T_14 = _io_mulh_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 313:48]
+  wire  _io_mulhsu_T_8 = _io_mul_T_7 & io_lui_bit_18; // @[Library.scala 316:48]
+  wire  _io_mulhsu_T_10 = _io_mulhsu_T_8 & io_jalr_bit_19 & io_lui_bit_25; // @[Library.scala 313:48]
+  wire  _io_mulhsu_T_12 = _io_mulhsu_T_10 & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 316:48]
+  wire  _io_mulhsu_T_14 = _io_mulhsu_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 313:48]
+  wire  _io_mulhu_T_9 = _io_mul_T_7 & io_lui_bit_18 & io_lui_bit_19; // @[Library.scala 316:48]
+  wire  _io_mulhu_T_10 = _io_mulhu_T_9 & io_lui_bit_25; // @[Library.scala 313:48]
+  wire  _io_mulhu_T_12 = _io_mulhu_T_10 & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 316:48]
+  wire  _io_mulhu_T_14 = _io_mulhu_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 313:48]
+  wire  _io_mulhr_T_2 = _io_fence_T_1 & io_lui_bit_2; // @[Library.scala 316:48]
+  wire  _io_mulhr_T_4 = _io_mulhr_T_2 & io_fence_bit_3 & io_slli_bit_4; // @[Library.scala 313:48]
+  wire  _io_mulhr_T_5 = _io_mulhr_T_2 & io_fence_bit_3 & io_slli_bit_4 & io_slli_bit_5; // @[Library.scala 313:48]
+  wire  _io_mulhr_T_6 = _io_mulhr_T_5 & io_lui_bit_6; // @[Library.scala 316:48]
+  wire  _io_mulhr_T_7 = _io_mulhr_T_6 & io_jalr_bit_17; // @[Library.scala 313:48]
+  wire  _io_mulhr_T_8 = _io_mulhr_T_6 & io_jalr_bit_17 & io_jalr_bit_18; // @[Library.scala 313:48]
+  wire  _io_mulhr_T_9 = _io_mulhr_T_8 & io_lui_bit_19; // @[Library.scala 316:48]
+  wire  _io_mulhr_T_10 = _io_mulhr_T_9 & io_lui_bit_25; // @[Library.scala 313:48]
+  wire  _io_mulhr_T_12 = _io_mulhr_T_10 & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 316:48]
+  wire  _io_mulhr_T_14 = _io_mulhr_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 313:48]
+  wire  _io_mulhsur_T_8 = _io_mulhr_T_7 & io_lui_bit_18; // @[Library.scala 316:48]
+  wire  _io_mulhsur_T_10 = _io_mulhsur_T_8 & io_jalr_bit_19 & io_lui_bit_25; // @[Library.scala 313:48]
+  wire  _io_mulhsur_T_12 = _io_mulhsur_T_10 & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 316:48]
+  wire  _io_mulhsur_T_14 = _io_mulhsur_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 313:48]
+  wire  _io_mulhur_T_9 = _io_mulhr_T_7 & io_lui_bit_18 & io_lui_bit_19; // @[Library.scala 316:48]
+  wire  _io_mulhur_T_10 = _io_mulhur_T_9 & io_lui_bit_25; // @[Library.scala 313:48]
+  wire  _io_mulhur_T_12 = _io_mulhur_T_10 & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 316:48]
+  wire  _io_mulhur_T_14 = _io_mulhur_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 313:48]
+  wire  _io_dmulh_T_5 = _io_slli_T_4 & io_lui_bit_5; // @[Library.scala 316:48]
+  wire  _io_dmulh_T_8 = _io_dmulh_T_5 & io_slli_bit_6 & io_jalr_bit_17 & io_jalr_bit_18; // @[Library.scala 313:48]
+  wire  _io_dmulh_T_9 = _io_dmulh_T_8 & io_lui_bit_19; // @[Library.scala 316:48]
+  wire  _io_dmulh_T_10 = _io_dmulh_T_9 & io_lui_bit_25; // @[Library.scala 313:48]
+  wire  _io_dmulh_T_12 = _io_dmulh_T_10 & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 316:48]
+  wire  _io_dmulh_T_14 = _io_dmulh_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 313:48]
+  wire  _io_dmulhr_T_5 = _io_mulhr_T_4 & io_lui_bit_5; // @[Library.scala 316:48]
+  wire  _io_dmulhr_T_8 = _io_dmulhr_T_5 & io_slli_bit_6 & io_jalr_bit_17 & io_jalr_bit_18; // @[Library.scala 313:48]
+  wire  _io_dmulhr_T_9 = _io_dmulhr_T_8 & io_lui_bit_19; // @[Library.scala 316:48]
+  wire  _io_dmulhr_T_10 = _io_dmulhr_T_9 & io_lui_bit_25; // @[Library.scala 313:48]
+  wire  _io_dmulhr_T_12 = _io_dmulhr_T_10 & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 316:48]
+  wire  _io_dmulhr_T_14 = _io_dmulhr_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 313:48]
+  wire  _io_clz_T_2 = io_fence_bit & io_lui_bit_1 & io_lui_bit_2; // @[Library.scala 316:48]
+  wire  io_clz_bit_7 = ~io_lui_bit_7; // @[Library.scala 312:19]
+  wire  io_clz_bit_8 = ~io_lui_bit_8; // @[Library.scala 312:19]
+  wire  io_clz_bit_9 = ~io_lui_bit_9; // @[Library.scala 312:19]
+  wire  _io_clz_T_9 = _io_clz_T_2 & io_fence_bit_3 & io_slli_bit_4 & io_slli_bit_5 & io_slli_bit_6 & io_clz_bit_7 &
+    io_clz_bit_8 & io_clz_bit_9; // @[Library.scala 313:48]
+  wire  io_clz_bit_10 = ~io_lui_bit_10; // @[Library.scala 312:19]
+  wire  _io_clz_T_10 = _io_clz_T_2 & io_fence_bit_3 & io_slli_bit_4 & io_slli_bit_5 & io_slli_bit_6 & io_clz_bit_7 &
+    io_clz_bit_8 & io_clz_bit_9 & io_clz_bit_10; // @[Library.scala 313:48]
+  wire  io_clz_bit_11 = ~io_inst[20]; // @[Library.scala 312:19]
+  wire  _io_clz_T_13 = _io_clz_T_2 & io_fence_bit_3 & io_slli_bit_4 & io_slli_bit_5 & io_slli_bit_6 & io_clz_bit_7 &
+    io_clz_bit_8 & io_clz_bit_9 & io_clz_bit_10 & io_clz_bit_11 & io_jalr_bit_17 & io_jalr_bit_18; // @[Library.scala 313:48]
+  wire  _io_clz_T_14 = _io_clz_T_13 & io_lui_bit_19; // @[Library.scala 316:48]
+  wire  _io_clz_T_16 = _io_clz_T_14 & io_lui_bit_25 & io_auipc_bit_26; // @[Library.scala 313:48]
+  wire  _io_clz_T_17 = _io_clz_T_16 & io_lui_bit_27; // @[Library.scala 316:48]
+  wire  _io_clz_T_19 = _io_clz_T_17 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 313:48]
+  wire  _io_ctz_T_11 = _io_clz_T_10 & io_inst[20]; // @[Library.scala 316:48]
+  wire  _io_ctz_T_13 = _io_ctz_T_11 & io_jalr_bit_17 & io_jalr_bit_18; // @[Library.scala 313:48]
+  wire  _io_ctz_T_14 = _io_ctz_T_13 & io_lui_bit_19; // @[Library.scala 316:48]
+  wire  _io_ctz_T_16 = _io_ctz_T_14 & io_lui_bit_25 & io_auipc_bit_26; // @[Library.scala 313:48]
+  wire  _io_ctz_T_17 = _io_ctz_T_16 & io_lui_bit_27; // @[Library.scala 316:48]
+  wire  _io_ctz_T_19 = _io_ctz_T_17 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 313:48]
+  wire  _io_pcnt_T_10 = _io_clz_T_9 & io_lui_bit_10; // @[Library.scala 316:48]
+  wire  _io_pcnt_T_13 = _io_pcnt_T_10 & io_clz_bit_11 & io_jalr_bit_17 & io_jalr_bit_18; // @[Library.scala 313:48]
+  wire  _io_pcnt_T_14 = _io_pcnt_T_13 & io_lui_bit_19; // @[Library.scala 316:48]
+  wire  _io_pcnt_T_16 = _io_pcnt_T_14 & io_lui_bit_25 & io_auipc_bit_26; // @[Library.scala 313:48]
+  wire  _io_pcnt_T_17 = _io_pcnt_T_16 & io_lui_bit_27; // @[Library.scala 316:48]
+  wire  _io_pcnt_T_19 = _io_pcnt_T_17 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 313:48]
+  wire  _io_min_T_4 = _io_fence_T_3 & io_lui_bit_4; // @[Library.scala 316:48]
+  wire  _io_min_T_5 = _io_min_T_4 & io_slli_bit_5; // @[Library.scala 313:48]
+  wire  _io_min_T_7 = _io_min_T_5 & io_lui_bit_6 & io_lui_bit_17; // @[Library.scala 316:48]
+  wire  _io_min_T_8 = _io_min_T_7 & io_jalr_bit_18; // @[Library.scala 313:48]
+  wire  _io_min_T_10 = _io_min_T_7 & io_jalr_bit_18 & io_jalr_bit_19 & io_lui_bit_25; // @[Library.scala 313:48]
+  wire  _io_min_T_12 = _io_min_T_10 & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 316:48]
+  wire  _io_min_T_14 = _io_min_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 313:48]
+  wire  _io_minu_T_9 = _io_min_T_8 & io_lui_bit_19; // @[Library.scala 316:48]
+  wire  _io_minu_T_10 = _io_minu_T_9 & io_lui_bit_25; // @[Library.scala 313:48]
+  wire  _io_minu_T_12 = _io_minu_T_10 & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 316:48]
+  wire  _io_minu_T_14 = _io_minu_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 313:48]
+  wire  _io_max_T_8 = _io_min_T_5 & io_lui_bit_6 & io_lui_bit_17 & io_lui_bit_18; // @[Library.scala 316:48]
+  wire  _io_max_T_10 = _io_max_T_8 & io_jalr_bit_19 & io_lui_bit_25; // @[Library.scala 313:48]
+  wire  _io_max_T_12 = _io_max_T_10 & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 316:48]
+  wire  _io_max_T_14 = _io_max_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 313:48]
+  wire  _io_maxu_T_9 = _io_min_T_5 & io_lui_bit_6 & io_lui_bit_17 & io_lui_bit_18 & io_lui_bit_19; // @[Library.scala 316:48]
+  wire  _io_maxu_T_10 = _io_maxu_T_9 & io_lui_bit_25; // @[Library.scala 313:48]
+  wire  _io_maxu_T_12 = _io_maxu_T_10 & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 316:48]
+  wire  _io_maxu_T_14 = _io_maxu_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 313:48]
+  wire  _io_getvl_T_3 = _io_fence_T_2 & io_lui_bit_3; // @[Library.scala 316:48]
+  wire  _io_getvl_T_6 = _io_getvl_T_3 & io_jalr_bit_17 & io_jalr_bit_18 & io_jalr_bit_19; // @[Library.scala 313:48]
+  wire  _io_getvl_T_9 = _io_getvl_T_6 & io_inst[6] & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 316:48]
+  wire  _io_getvl_T_10 = _io_getvl_T_9 & io_lui_bit_28; // @[Library.scala 313:48]
+  wire  _io_getvl_T_13 = _io_getvl_T_10 & io_lui_bit_29 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 316:48]
+  wire  _io_getvl_T_15 = io_inst[26:25] != 2'h3; // @[Decode.scala 565:89]
+  wire  _io_getmaxvl_T_16 = _io_getvl_T_3 & io_clz_bit_7 & io_clz_bit_8 & io_clz_bit_9 & io_clz_bit_10 & io_clz_bit_11
+     & io_fence_bit_12 & io_fence_bit_13 & io_fence_bit_14 & io_fence_bit_15 & io_fence_bit_16 & io_jalr_bit_17 &
+    io_jalr_bit_18 & io_jalr_bit_19; // @[Library.scala 313:48]
+  wire  _io_getmaxvl_T_19 = _io_getmaxvl_T_16 & io_inst[6] & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 316:48]
+  wire  _io_getmaxvl_T_20 = _io_getmaxvl_T_19 & io_lui_bit_28; // @[Library.scala 313:48]
+  wire  _io_getmaxvl_T_23 = _io_getmaxvl_T_20 & io_lui_bit_29 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 316:48]
+  wire  _io_vld_T_4 = io_fence_bit & io_fence_bit_1 & io_fence_bit_2 & io_slli_bit_6 & io_jalr_bit_17; // @[Library.scala 313:48]
+  wire  _io_vst_T_4 = _io_mulhr_T_2 & io_slli_bit_6 & io_jalr_bit_17; // @[Library.scala 313:48]
+  wire  _io_vst_T_9 = _io_vst_T_4 & io_lui_bit_27 & io_inst[3] & io_lui_bit_29 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 316:48]
+  wire  _io_vst_T_14 = _io_clz_T_2 & io_slli_bit_6 & io_jalr_bit_17; // @[Library.scala 313:48]
+  wire  _io_vst_T_19 = _io_vst_T_14 & io_lui_bit_27 & io_inst[3] & io_lui_bit_29 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 316:48]
+  wire  _vconv_T_3 = _io_srai_T_2 & io_lui_bit_3; // @[Library.scala 316:48]
+  wire  _vconv_T_17 = _vconv_T_3 & io_slli_bit_4 & io_slli_bit_5 & io_slli_bit_6 & io_clz_bit_7 & io_clz_bit_8 &
+    io_clz_bit_9 & io_clz_bit_10 & io_clz_bit_11 & io_fence_bit_12 & io_fence_bit_13 & io_fence_bit_14 & io_fence_bit_15
+     & io_fence_bit_16 & io_jalr_bit_17; // @[Library.scala 313:48]
+  wire  vconv = _vconv_T_17 & io_lui_bit_27 & io_inst[3] & io_lui_bit_29 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 316:48]
   wire  _vdup_T_11 = _io_srai_T_1 & io_fence_bit_2 & io_fence_bit_3 & io_slli_bit_4 & io_slli_bit_6 & io_fence_bit_12 &
-    io_fence_bit_13 & io_fence_bit_14 & io_fence_bit_15 & io_fence_bit_16 & io_jalr_bit_17; // @[Library.scala 311:48]
-  wire  _vdup_T_16 = _vdup_T_11 & io_lui_bit_27 & io_inst[3] & io_lui_bit_29 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 314:48]
-  wire  vdup = _vdup_T_16 & io_inst[13:12] <= 2'h2; // @[Decode.scala 701:72]
-  wire  vdupi = vdup & io_slli_bit_5; // @[Decode.scala 702:20]
-  wire  vdupf = vdup & io_lui_bit_5; // @[Decode.scala 703:20]
-  wire  _vfma_T_1 = ~io_lui_bit_31; // @[Decode.scala 706:21]
-  wire  vfma = ~io_lui_bit_31 & io_inst[4:2] == 3'h5; // @[Decode.scala 706:29]
-  wire  _vfma4_T_1 = io_inst[1:0] == 2'h1; // @[Decode.scala 707:23]
-  wire [3:0] _vfma4_T_4 = {io_inst[13:12],io_inst[4:3]}; // @[Cat.scala 31:58]
-  wire  vfma4 = io_inst[1:0] == 2'h1 & _vfma4_T_4 == 4'h0; // @[Decode.scala 707:31]
-  wire  _io_viop_T_7 = _vfma4_T_1 & ~vfma4; // @[Decode.scala 712:30]
-  wire  _io_viop_T_8 = _vfma_T_1 & ~vfma | _io_viop_T_7; // @[Decode.scala 711:37]
-  wire  _io_viop_T_9 = _io_viop_T_8 | vconv; // @[Decode.scala 712:40]
-  wire [5:0] decoded_lo_lo_lo_lo = {io_mpause,io_mret,io_fencei,io_flushat,io_flushall,io_slog}; // @[Cat.scala 31:58]
-  wire [12:0] decoded_lo_lo_lo = {io_getvl,io_getmaxvl,io_ebreak,io_ecall,io_eexit,io_eyield,io_ectxsw,
-    decoded_lo_lo_lo_lo}; // @[Cat.scala 31:58]
-  wire [5:0] decoded_lo_lo_hi_lo = {io_max,io_maxu,io_viop,io_vfop,io_vld,io_vst}; // @[Cat.scala 31:58]
-  wire [25:0] decoded_lo_lo = {io_fmvwx,io_clb,io_clz,io_ctz,io_pcnt,io_min,io_minu,decoded_lo_lo_hi_lo,decoded_lo_lo_lo
-    }; // @[Cat.scala 31:58]
-  wire [5:0] decoded_lo_hi_lo_lo = {io_feq,io_flt,io_fle,io_fclass,io_fcvtsw,io_fcvtswu}; // @[Cat.scala 31:58]
-  wire [12:0] decoded_lo_hi_lo = {io_fsgnjn,io_fsgnjx,io_fmin,io_fmax,io_fcvtws,io_fcvtwus,io_fmvxw,decoded_lo_hi_lo_lo}
+    io_fence_bit_13 & io_fence_bit_14 & io_fence_bit_15 & io_fence_bit_16 & io_jalr_bit_17; // @[Library.scala 313:48]
+  wire  _vdup_T_16 = _vdup_T_11 & io_lui_bit_27 & io_inst[3] & io_lui_bit_29 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 316:48]
+  wire  vdup = _vdup_T_16 & io_inst[13:12] <= 2'h2; // @[Decode.scala 578:72]
+  wire  vdupi = vdup & io_slli_bit_5; // @[Decode.scala 579:20]
+  wire  _io_viop_T_3 = io_inst[1:0] == 2'h1; // @[Decode.scala 583:22]
+  wire  _io_viop_T_4 = ~io_lui_bit_31 | _io_viop_T_3; // @[Decode.scala 582:28]
+  wire  _io_viop_T_5 = _io_viop_T_4 | vconv; // @[Decode.scala 583:30]
+  wire [9:0] decoded_lo_lo_hi = {io_minu,io_max,io_maxu,io_viop,io_vld,io_vst,io_getvl,io_getmaxvl,io_ebreak,io_ecall}; // @[Cat.scala 31:58]
+  wire [18:0] decoded_lo_lo = {decoded_lo_lo_hi,io_eexit,io_eyield,io_ectxsw,io_mpause,io_mret,io_fencei,io_flushat,
+    io_flushall,io_slog}; // @[Cat.scala 31:58]
+  wire [9:0] decoded_lo_hi_hi = {io_srl,io_sra,io_mul,io_mulh,io_mulhsu,io_mulhu,io_mulhr,io_mulhsur,io_mulhur,io_dmulh}
     ; // @[Cat.scala 31:58]
-  wire [5:0] decoded_lo_hi_hi_lo = {io_fadd,io_fsub,io_fmul,io_fdiv,io_fsqrt,io_fsgnj}; // @[Cat.scala 31:58]
-  wire [51:0] decoded_lo = {io_remu,io_flw,io_fsw,io_fmadd,io_fmsub,io_fnmsub,io_fnmadd,decoded_lo_hi_hi_lo,
-    decoded_lo_hi_lo,decoded_lo_lo}; // @[Cat.scala 31:58]
-  wire [5:0] decoded_hi_lo_lo_lo = {io_mulhur,io_dmulh,io_dmulhr,io_div,io_divu,io_rem}; // @[Cat.scala 31:58]
-  wire [12:0] decoded_hi_lo_lo = {io_sra,io_mul,io_mulh,io_mulhsu,io_mulhu,io_mulhr,io_mulhsur,decoded_hi_lo_lo_lo}; // @[Cat.scala 31:58]
-  wire [5:0] decoded_hi_lo_hi_lo = {io_and,io_slli,io_srli,io_srai,io_sll,io_srl}; // @[Cat.scala 31:58]
-  wire [25:0] decoded_hi_lo = {io_andi,io_add,io_sub,io_slt,io_sltu,io_xor,io_or,decoded_hi_lo_hi_lo,decoded_hi_lo_lo}; // @[Cat.scala 31:58]
-  wire [5:0] decoded_hi_hi_lo_lo = {io_fence,io_addi,io_slti,io_sltiu,io_xori,io_ori}; // @[Cat.scala 31:58]
-  wire [12:0] decoded_hi_hi_lo = {io_lh,io_lw,io_lbu,io_lhu,io_sb,io_sh,io_sw,decoded_hi_hi_lo_lo}; // @[Cat.scala 31:58]
-  wire [6:0] decoded_hi_hi_hi_lo = {io_bge,io_bltu,io_bgeu,io_csrrw,io_csrrs,io_csrrc,io_lb}; // @[Cat.scala 31:58]
-  wire [52:0] decoded_hi = {io_lui,io_auipc,io_jal,io_jalr,io_beq,io_bne,io_blt,decoded_hi_hi_hi_lo,decoded_hi_hi_lo,
-    decoded_hi_lo}; // @[Cat.scala 31:58]
-  wire [104:0] decoded = {decoded_hi,decoded_lo}; // @[Cat.scala 31:58]
-  wire  io_undef_value__52 = decoded[104]; // @[Library.scala 182:26]
+  wire [18:0] decoded_lo_hi = {decoded_lo_hi_hi,io_dmulhr,io_div,io_divu,io_rem,io_remu,io_clz,io_ctz,io_pcnt,io_min}; // @[Cat.scala 31:58]
+  wire [9:0] decoded_hi_lo_hi = {io_sw,io_fence,io_addi,io_slti,io_sltiu,io_xori,io_ori,io_andi,io_add,io_sub}; // @[Cat.scala 31:58]
+  wire [18:0] decoded_hi_lo = {decoded_hi_lo_hi,io_slt,io_sltu,io_xor,io_or,io_and,io_slli,io_srli,io_srai,io_sll}; // @[Cat.scala 31:58]
+  wire [9:0] decoded_hi_hi_lo = {io_csrrw,io_csrrs,io_csrrc,io_lb,io_lh,io_lw,io_lbu,io_lhu,io_sb,io_sh}; // @[Cat.scala 31:58]
+  wire [9:0] decoded_hi_hi_hi = {io_lui,io_auipc,io_jal,io_jalr,io_beq,io_bne,io_blt,io_bge,io_bltu,io_bgeu}; // @[Cat.scala 31:58]
+  wire [76:0] decoded = {decoded_hi_hi_hi,decoded_hi_hi_lo,decoded_hi_lo,decoded_lo_hi,decoded_lo_lo}; // @[Cat.scala 31:58]
+  wire  io_undef_value__38 = decoded[76]; // @[Library.scala 182:26]
   wire  io_undef_value__0 = decoded[0] | decoded[1]; // @[Library.scala 194:39]
   wire  io_undef_value__1 = decoded[2] | decoded[3]; // @[Library.scala 194:39]
   wire  io_undef_value__2 = decoded[4] | decoded[5]; // @[Library.scala 194:39]
@@ -9856,20 +9346,6 @@
   wire  io_undef_value__35 = decoded[70] | decoded[71]; // @[Library.scala 194:39]
   wire  io_undef_value__36 = decoded[72] | decoded[73]; // @[Library.scala 194:39]
   wire  io_undef_value__37 = decoded[74] | decoded[75]; // @[Library.scala 194:39]
-  wire  io_undef_value__38 = decoded[76] | decoded[77]; // @[Library.scala 194:39]
-  wire  io_undef_value__39 = decoded[78] | decoded[79]; // @[Library.scala 194:39]
-  wire  io_undef_value__40 = decoded[80] | decoded[81]; // @[Library.scala 194:39]
-  wire  io_undef_value__41 = decoded[82] | decoded[83]; // @[Library.scala 194:39]
-  wire  io_undef_value__42 = decoded[84] | decoded[85]; // @[Library.scala 194:39]
-  wire  io_undef_value__43 = decoded[86] | decoded[87]; // @[Library.scala 194:39]
-  wire  io_undef_value__44 = decoded[88] | decoded[89]; // @[Library.scala 194:39]
-  wire  io_undef_value__45 = decoded[90] | decoded[91]; // @[Library.scala 194:39]
-  wire  io_undef_value__46 = decoded[92] | decoded[93]; // @[Library.scala 194:39]
-  wire  io_undef_value__47 = decoded[94] | decoded[95]; // @[Library.scala 194:39]
-  wire  io_undef_value__48 = decoded[96] | decoded[97]; // @[Library.scala 194:39]
-  wire  io_undef_value__49 = decoded[98] | decoded[99]; // @[Library.scala 194:39]
-  wire  io_undef_value__50 = decoded[100] | decoded[101]; // @[Library.scala 194:39]
-  wire  io_undef_value__51 = decoded[102] | decoded[103]; // @[Library.scala 194:39]
   wire  io_undef_value_1_0 = io_undef_value__0 | io_undef_value__1; // @[Library.scala 194:39]
   wire  io_undef_value_1_1 = io_undef_value__2 | io_undef_value__3; // @[Library.scala 194:39]
   wire  io_undef_value_1_2 = io_undef_value__4 | io_undef_value__5; // @[Library.scala 194:39]
@@ -9889,13 +9365,6 @@
   wire  io_undef_value_1_16 = io_undef_value__32 | io_undef_value__33; // @[Library.scala 194:39]
   wire  io_undef_value_1_17 = io_undef_value__34 | io_undef_value__35; // @[Library.scala 194:39]
   wire  io_undef_value_1_18 = io_undef_value__36 | io_undef_value__37; // @[Library.scala 194:39]
-  wire  io_undef_value_1_19 = io_undef_value__38 | io_undef_value__39; // @[Library.scala 194:39]
-  wire  io_undef_value_1_20 = io_undef_value__40 | io_undef_value__41; // @[Library.scala 194:39]
-  wire  io_undef_value_1_21 = io_undef_value__42 | io_undef_value__43; // @[Library.scala 194:39]
-  wire  io_undef_value_1_22 = io_undef_value__44 | io_undef_value__45; // @[Library.scala 194:39]
-  wire  io_undef_value_1_23 = io_undef_value__46 | io_undef_value__47; // @[Library.scala 194:39]
-  wire  io_undef_value_1_24 = io_undef_value__48 | io_undef_value__49; // @[Library.scala 194:39]
-  wire  io_undef_value_1_25 = io_undef_value__50 | io_undef_value__51; // @[Library.scala 194:39]
   wire  io_undef_value_2_0 = io_undef_value_1_0 | io_undef_value_1_1; // @[Library.scala 194:39]
   wire  io_undef_value_2_1 = io_undef_value_1_2 | io_undef_value_1_3; // @[Library.scala 194:39]
   wire  io_undef_value_2_2 = io_undef_value_1_4 | io_undef_value_1_5; // @[Library.scala 194:39]
@@ -9905,282 +9374,200 @@
   wire  io_undef_value_2_6 = io_undef_value_1_12 | io_undef_value_1_13; // @[Library.scala 194:39]
   wire  io_undef_value_2_7 = io_undef_value_1_14 | io_undef_value_1_15; // @[Library.scala 194:39]
   wire  io_undef_value_2_8 = io_undef_value_1_16 | io_undef_value_1_17; // @[Library.scala 194:39]
-  wire  io_undef_value_2_9 = io_undef_value_1_18 | io_undef_value_1_19; // @[Library.scala 194:39]
-  wire  io_undef_value_2_10 = io_undef_value_1_20 | io_undef_value_1_21; // @[Library.scala 194:39]
-  wire  io_undef_value_2_11 = io_undef_value_1_22 | io_undef_value_1_23; // @[Library.scala 194:39]
-  wire  io_undef_value_2_12 = io_undef_value_1_24 | io_undef_value_1_25; // @[Library.scala 194:39]
+  wire  io_undef_value_2_9 = io_undef_value_1_18 | io_undef_value__38; // @[Library.scala 194:39]
   wire  io_undef_value_3_0 = io_undef_value_2_0 | io_undef_value_2_1; // @[Library.scala 194:39]
   wire  io_undef_value_3_1 = io_undef_value_2_2 | io_undef_value_2_3; // @[Library.scala 194:39]
   wire  io_undef_value_3_2 = io_undef_value_2_4 | io_undef_value_2_5; // @[Library.scala 194:39]
   wire  io_undef_value_3_3 = io_undef_value_2_6 | io_undef_value_2_7; // @[Library.scala 194:39]
   wire  io_undef_value_3_4 = io_undef_value_2_8 | io_undef_value_2_9; // @[Library.scala 194:39]
-  wire  io_undef_value_3_5 = io_undef_value_2_10 | io_undef_value_2_11; // @[Library.scala 194:39]
-  wire  io_undef_value_3_6 = io_undef_value_2_12 | io_undef_value__52; // @[Library.scala 194:39]
   wire  io_undef_value_4_0 = io_undef_value_3_0 | io_undef_value_3_1; // @[Library.scala 194:39]
   wire  io_undef_value_4_1 = io_undef_value_3_2 | io_undef_value_3_3; // @[Library.scala 194:39]
-  wire  io_undef_value_4_2 = io_undef_value_3_4 | io_undef_value_3_5; // @[Library.scala 194:39]
   wire  io_undef_value_5_0 = io_undef_value_4_0 | io_undef_value_4_1; // @[Library.scala 194:39]
-  wire  io_undef_value_5_1 = io_undef_value_4_2 | io_undef_value_3_6; // @[Library.scala 194:39]
-  wire  io_undef_value_6_0 = io_undef_value_5_0 | io_undef_value_5_1; // @[Library.scala 194:39]
-  reg  onehot_failed; // @[Decode.scala 813:30]
-  wire  _T_2 = ~reset; // @[Decode.scala 814:9]
-  wire [1:0] _onehot_decode_T_105 = decoded[1] + decoded[2]; // @[Bitwise.scala 48:55]
-  wire [1:0] _GEN_1 = {{1'd0}, decoded[0]}; // @[Bitwise.scala 48:55]
-  wire [2:0] _onehot_decode_T_107 = _GEN_1 + _onehot_decode_T_105; // @[Bitwise.scala 48:55]
-  wire [1:0] _onehot_decode_T_109 = decoded[4] + decoded[5]; // @[Bitwise.scala 48:55]
-  wire [1:0] _GEN_2 = {{1'd0}, decoded[3]}; // @[Bitwise.scala 48:55]
-  wire [2:0] _onehot_decode_T_111 = _GEN_2 + _onehot_decode_T_109; // @[Bitwise.scala 48:55]
-  wire [2:0] _onehot_decode_T_113 = _onehot_decode_T_107[1:0] + _onehot_decode_T_111[1:0]; // @[Bitwise.scala 48:55]
-  wire [1:0] _onehot_decode_T_115 = decoded[7] + decoded[8]; // @[Bitwise.scala 48:55]
-  wire [1:0] _GEN_3 = {{1'd0}, decoded[6]}; // @[Bitwise.scala 48:55]
-  wire [2:0] _onehot_decode_T_117 = _GEN_3 + _onehot_decode_T_115; // @[Bitwise.scala 48:55]
-  wire [1:0] _onehot_decode_T_119 = decoded[9] + decoded[10]; // @[Bitwise.scala 48:55]
-  wire [1:0] _onehot_decode_T_121 = decoded[11] + decoded[12]; // @[Bitwise.scala 48:55]
-  wire [2:0] _onehot_decode_T_123 = _onehot_decode_T_119 + _onehot_decode_T_121; // @[Bitwise.scala 48:55]
-  wire [2:0] _GEN_4 = {{1'd0}, _onehot_decode_T_117[1:0]}; // @[Bitwise.scala 48:55]
-  wire [3:0] _onehot_decode_T_125 = _GEN_4 + _onehot_decode_T_123; // @[Bitwise.scala 48:55]
-  wire [3:0] _onehot_decode_T_127 = _onehot_decode_T_113 + _onehot_decode_T_125[2:0]; // @[Bitwise.scala 48:55]
-  wire [1:0] _onehot_decode_T_129 = decoded[14] + decoded[15]; // @[Bitwise.scala 48:55]
-  wire [1:0] _GEN_5 = {{1'd0}, decoded[13]}; // @[Bitwise.scala 48:55]
-  wire [2:0] _onehot_decode_T_131 = _GEN_5 + _onehot_decode_T_129; // @[Bitwise.scala 48:55]
-  wire [1:0] _onehot_decode_T_133 = decoded[17] + decoded[18]; // @[Bitwise.scala 48:55]
-  wire [1:0] _GEN_6 = {{1'd0}, decoded[16]}; // @[Bitwise.scala 48:55]
-  wire [2:0] _onehot_decode_T_135 = _GEN_6 + _onehot_decode_T_133; // @[Bitwise.scala 48:55]
-  wire [2:0] _onehot_decode_T_137 = _onehot_decode_T_131[1:0] + _onehot_decode_T_135[1:0]; // @[Bitwise.scala 48:55]
-  wire [1:0] _onehot_decode_T_139 = decoded[20] + decoded[21]; // @[Bitwise.scala 48:55]
-  wire [1:0] _GEN_7 = {{1'd0}, decoded[19]}; // @[Bitwise.scala 48:55]
-  wire [2:0] _onehot_decode_T_141 = _GEN_7 + _onehot_decode_T_139; // @[Bitwise.scala 48:55]
-  wire [1:0] _onehot_decode_T_143 = decoded[22] + decoded[23]; // @[Bitwise.scala 48:55]
-  wire [1:0] _onehot_decode_T_145 = decoded[24] + decoded[25]; // @[Bitwise.scala 48:55]
-  wire [2:0] _onehot_decode_T_147 = _onehot_decode_T_143 + _onehot_decode_T_145; // @[Bitwise.scala 48:55]
-  wire [2:0] _GEN_8 = {{1'd0}, _onehot_decode_T_141[1:0]}; // @[Bitwise.scala 48:55]
-  wire [3:0] _onehot_decode_T_149 = _GEN_8 + _onehot_decode_T_147; // @[Bitwise.scala 48:55]
-  wire [3:0] _onehot_decode_T_151 = _onehot_decode_T_137 + _onehot_decode_T_149[2:0]; // @[Bitwise.scala 48:55]
-  wire [4:0] _onehot_decode_T_153 = _onehot_decode_T_127 + _onehot_decode_T_151; // @[Bitwise.scala 48:55]
-  wire [1:0] _onehot_decode_T_155 = decoded[27] + decoded[28]; // @[Bitwise.scala 48:55]
-  wire [1:0] _GEN_9 = {{1'd0}, decoded[26]}; // @[Bitwise.scala 48:55]
-  wire [2:0] _onehot_decode_T_157 = _GEN_9 + _onehot_decode_T_155; // @[Bitwise.scala 48:55]
-  wire [1:0] _onehot_decode_T_159 = decoded[30] + decoded[31]; // @[Bitwise.scala 48:55]
-  wire [1:0] _GEN_10 = {{1'd0}, decoded[29]}; // @[Bitwise.scala 48:55]
-  wire [2:0] _onehot_decode_T_161 = _GEN_10 + _onehot_decode_T_159; // @[Bitwise.scala 48:55]
-  wire [2:0] _onehot_decode_T_163 = _onehot_decode_T_157[1:0] + _onehot_decode_T_161[1:0]; // @[Bitwise.scala 48:55]
-  wire [1:0] _onehot_decode_T_165 = decoded[33] + decoded[34]; // @[Bitwise.scala 48:55]
-  wire [1:0] _GEN_11 = {{1'd0}, decoded[32]}; // @[Bitwise.scala 48:55]
-  wire [2:0] _onehot_decode_T_167 = _GEN_11 + _onehot_decode_T_165; // @[Bitwise.scala 48:55]
-  wire [1:0] _onehot_decode_T_169 = decoded[35] + decoded[36]; // @[Bitwise.scala 48:55]
-  wire [1:0] _onehot_decode_T_171 = decoded[37] + decoded[38]; // @[Bitwise.scala 48:55]
-  wire [2:0] _onehot_decode_T_173 = _onehot_decode_T_169 + _onehot_decode_T_171; // @[Bitwise.scala 48:55]
-  wire [2:0] _GEN_12 = {{1'd0}, _onehot_decode_T_167[1:0]}; // @[Bitwise.scala 48:55]
-  wire [3:0] _onehot_decode_T_175 = _GEN_12 + _onehot_decode_T_173; // @[Bitwise.scala 48:55]
-  wire [3:0] _onehot_decode_T_177 = _onehot_decode_T_163 + _onehot_decode_T_175[2:0]; // @[Bitwise.scala 48:55]
-  wire [1:0] _onehot_decode_T_179 = decoded[40] + decoded[41]; // @[Bitwise.scala 48:55]
-  wire [1:0] _GEN_13 = {{1'd0}, decoded[39]}; // @[Bitwise.scala 48:55]
-  wire [2:0] _onehot_decode_T_181 = _GEN_13 + _onehot_decode_T_179; // @[Bitwise.scala 48:55]
-  wire [1:0] _onehot_decode_T_183 = decoded[43] + decoded[44]; // @[Bitwise.scala 48:55]
-  wire [1:0] _GEN_14 = {{1'd0}, decoded[42]}; // @[Bitwise.scala 48:55]
-  wire [2:0] _onehot_decode_T_185 = _GEN_14 + _onehot_decode_T_183; // @[Bitwise.scala 48:55]
-  wire [2:0] _onehot_decode_T_187 = _onehot_decode_T_181[1:0] + _onehot_decode_T_185[1:0]; // @[Bitwise.scala 48:55]
-  wire [1:0] _onehot_decode_T_189 = decoded[46] + decoded[47]; // @[Bitwise.scala 48:55]
-  wire [1:0] _GEN_15 = {{1'd0}, decoded[45]}; // @[Bitwise.scala 48:55]
-  wire [2:0] _onehot_decode_T_191 = _GEN_15 + _onehot_decode_T_189; // @[Bitwise.scala 48:55]
-  wire [1:0] _onehot_decode_T_193 = decoded[48] + decoded[49]; // @[Bitwise.scala 48:55]
-  wire [1:0] _onehot_decode_T_195 = decoded[50] + decoded[51]; // @[Bitwise.scala 48:55]
-  wire [2:0] _onehot_decode_T_197 = _onehot_decode_T_193 + _onehot_decode_T_195; // @[Bitwise.scala 48:55]
-  wire [2:0] _GEN_16 = {{1'd0}, _onehot_decode_T_191[1:0]}; // @[Bitwise.scala 48:55]
-  wire [3:0] _onehot_decode_T_199 = _GEN_16 + _onehot_decode_T_197; // @[Bitwise.scala 48:55]
-  wire [3:0] _onehot_decode_T_201 = _onehot_decode_T_187 + _onehot_decode_T_199[2:0]; // @[Bitwise.scala 48:55]
-  wire [4:0] _onehot_decode_T_203 = _onehot_decode_T_177 + _onehot_decode_T_201; // @[Bitwise.scala 48:55]
-  wire [5:0] _onehot_decode_T_205 = _onehot_decode_T_153 + _onehot_decode_T_203; // @[Bitwise.scala 48:55]
-  wire [1:0] _onehot_decode_T_207 = decoded[53] + decoded[54]; // @[Bitwise.scala 48:55]
-  wire [1:0] _GEN_17 = {{1'd0}, decoded[52]}; // @[Bitwise.scala 48:55]
-  wire [2:0] _onehot_decode_T_209 = _GEN_17 + _onehot_decode_T_207; // @[Bitwise.scala 48:55]
-  wire [1:0] _onehot_decode_T_211 = decoded[56] + decoded[57]; // @[Bitwise.scala 48:55]
-  wire [1:0] _GEN_18 = {{1'd0}, decoded[55]}; // @[Bitwise.scala 48:55]
-  wire [2:0] _onehot_decode_T_213 = _GEN_18 + _onehot_decode_T_211; // @[Bitwise.scala 48:55]
-  wire [2:0] _onehot_decode_T_215 = _onehot_decode_T_209[1:0] + _onehot_decode_T_213[1:0]; // @[Bitwise.scala 48:55]
-  wire [1:0] _onehot_decode_T_217 = decoded[59] + decoded[60]; // @[Bitwise.scala 48:55]
-  wire [1:0] _GEN_19 = {{1'd0}, decoded[58]}; // @[Bitwise.scala 48:55]
-  wire [2:0] _onehot_decode_T_219 = _GEN_19 + _onehot_decode_T_217; // @[Bitwise.scala 48:55]
-  wire [1:0] _onehot_decode_T_221 = decoded[61] + decoded[62]; // @[Bitwise.scala 48:55]
-  wire [1:0] _onehot_decode_T_223 = decoded[63] + decoded[64]; // @[Bitwise.scala 48:55]
-  wire [2:0] _onehot_decode_T_225 = _onehot_decode_T_221 + _onehot_decode_T_223; // @[Bitwise.scala 48:55]
-  wire [2:0] _GEN_20 = {{1'd0}, _onehot_decode_T_219[1:0]}; // @[Bitwise.scala 48:55]
-  wire [3:0] _onehot_decode_T_227 = _GEN_20 + _onehot_decode_T_225; // @[Bitwise.scala 48:55]
-  wire [3:0] _onehot_decode_T_229 = _onehot_decode_T_215 + _onehot_decode_T_227[2:0]; // @[Bitwise.scala 48:55]
-  wire [1:0] _onehot_decode_T_231 = decoded[66] + decoded[67]; // @[Bitwise.scala 48:55]
-  wire [1:0] _GEN_21 = {{1'd0}, decoded[65]}; // @[Bitwise.scala 48:55]
-  wire [2:0] _onehot_decode_T_233 = _GEN_21 + _onehot_decode_T_231; // @[Bitwise.scala 48:55]
-  wire [1:0] _onehot_decode_T_235 = decoded[69] + decoded[70]; // @[Bitwise.scala 48:55]
-  wire [1:0] _GEN_22 = {{1'd0}, decoded[68]}; // @[Bitwise.scala 48:55]
-  wire [2:0] _onehot_decode_T_237 = _GEN_22 + _onehot_decode_T_235; // @[Bitwise.scala 48:55]
-  wire [2:0] _onehot_decode_T_239 = _onehot_decode_T_233[1:0] + _onehot_decode_T_237[1:0]; // @[Bitwise.scala 48:55]
-  wire [1:0] _onehot_decode_T_241 = decoded[72] + decoded[73]; // @[Bitwise.scala 48:55]
-  wire [1:0] _GEN_23 = {{1'd0}, decoded[71]}; // @[Bitwise.scala 48:55]
-  wire [2:0] _onehot_decode_T_243 = _GEN_23 + _onehot_decode_T_241; // @[Bitwise.scala 48:55]
-  wire [1:0] _onehot_decode_T_245 = decoded[74] + decoded[75]; // @[Bitwise.scala 48:55]
-  wire [1:0] _onehot_decode_T_247 = decoded[76] + decoded[77]; // @[Bitwise.scala 48:55]
-  wire [2:0] _onehot_decode_T_249 = _onehot_decode_T_245 + _onehot_decode_T_247; // @[Bitwise.scala 48:55]
-  wire [2:0] _GEN_24 = {{1'd0}, _onehot_decode_T_243[1:0]}; // @[Bitwise.scala 48:55]
-  wire [3:0] _onehot_decode_T_251 = _GEN_24 + _onehot_decode_T_249; // @[Bitwise.scala 48:55]
-  wire [3:0] _onehot_decode_T_253 = _onehot_decode_T_239 + _onehot_decode_T_251[2:0]; // @[Bitwise.scala 48:55]
-  wire [4:0] _onehot_decode_T_255 = _onehot_decode_T_229 + _onehot_decode_T_253; // @[Bitwise.scala 48:55]
-  wire [1:0] _onehot_decode_T_257 = decoded[79] + decoded[80]; // @[Bitwise.scala 48:55]
-  wire [1:0] _GEN_25 = {{1'd0}, decoded[78]}; // @[Bitwise.scala 48:55]
-  wire [2:0] _onehot_decode_T_259 = _GEN_25 + _onehot_decode_T_257; // @[Bitwise.scala 48:55]
-  wire [1:0] _onehot_decode_T_261 = decoded[82] + decoded[83]; // @[Bitwise.scala 48:55]
-  wire [1:0] _GEN_26 = {{1'd0}, decoded[81]}; // @[Bitwise.scala 48:55]
-  wire [2:0] _onehot_decode_T_263 = _GEN_26 + _onehot_decode_T_261; // @[Bitwise.scala 48:55]
-  wire [2:0] _onehot_decode_T_265 = _onehot_decode_T_259[1:0] + _onehot_decode_T_263[1:0]; // @[Bitwise.scala 48:55]
-  wire [1:0] _onehot_decode_T_267 = decoded[85] + decoded[86]; // @[Bitwise.scala 48:55]
-  wire [1:0] _GEN_27 = {{1'd0}, decoded[84]}; // @[Bitwise.scala 48:55]
-  wire [2:0] _onehot_decode_T_269 = _GEN_27 + _onehot_decode_T_267; // @[Bitwise.scala 48:55]
-  wire [1:0] _onehot_decode_T_271 = decoded[87] + decoded[88]; // @[Bitwise.scala 48:55]
-  wire [1:0] _onehot_decode_T_273 = decoded[89] + decoded[90]; // @[Bitwise.scala 48:55]
-  wire [2:0] _onehot_decode_T_275 = _onehot_decode_T_271 + _onehot_decode_T_273; // @[Bitwise.scala 48:55]
-  wire [2:0] _GEN_28 = {{1'd0}, _onehot_decode_T_269[1:0]}; // @[Bitwise.scala 48:55]
-  wire [3:0] _onehot_decode_T_277 = _GEN_28 + _onehot_decode_T_275; // @[Bitwise.scala 48:55]
-  wire [3:0] _onehot_decode_T_279 = _onehot_decode_T_265 + _onehot_decode_T_277[2:0]; // @[Bitwise.scala 48:55]
-  wire [1:0] _onehot_decode_T_281 = decoded[92] + decoded[93]; // @[Bitwise.scala 48:55]
-  wire [1:0] _GEN_29 = {{1'd0}, decoded[91]}; // @[Bitwise.scala 48:55]
-  wire [2:0] _onehot_decode_T_283 = _GEN_29 + _onehot_decode_T_281; // @[Bitwise.scala 48:55]
-  wire [1:0] _onehot_decode_T_285 = decoded[94] + decoded[95]; // @[Bitwise.scala 48:55]
-  wire [1:0] _onehot_decode_T_287 = decoded[96] + decoded[97]; // @[Bitwise.scala 48:55]
-  wire [2:0] _onehot_decode_T_289 = _onehot_decode_T_285 + _onehot_decode_T_287; // @[Bitwise.scala 48:55]
-  wire [2:0] _GEN_30 = {{1'd0}, _onehot_decode_T_283[1:0]}; // @[Bitwise.scala 48:55]
-  wire [3:0] _onehot_decode_T_291 = _GEN_30 + _onehot_decode_T_289; // @[Bitwise.scala 48:55]
-  wire [1:0] _onehot_decode_T_293 = decoded[99] + decoded[100]; // @[Bitwise.scala 48:55]
-  wire [1:0] _GEN_31 = {{1'd0}, decoded[98]}; // @[Bitwise.scala 48:55]
-  wire [2:0] _onehot_decode_T_295 = _GEN_31 + _onehot_decode_T_293; // @[Bitwise.scala 48:55]
-  wire [1:0] _onehot_decode_T_297 = decoded[101] + decoded[102]; // @[Bitwise.scala 48:55]
-  wire [1:0] _onehot_decode_T_299 = decoded[103] + io_undef_value__52; // @[Bitwise.scala 48:55]
-  wire [2:0] _onehot_decode_T_301 = _onehot_decode_T_297 + _onehot_decode_T_299; // @[Bitwise.scala 48:55]
-  wire [2:0] _GEN_32 = {{1'd0}, _onehot_decode_T_295[1:0]}; // @[Bitwise.scala 48:55]
-  wire [3:0] _onehot_decode_T_303 = _GEN_32 + _onehot_decode_T_301; // @[Bitwise.scala 48:55]
-  wire [3:0] _onehot_decode_T_305 = _onehot_decode_T_291[2:0] + _onehot_decode_T_303[2:0]; // @[Bitwise.scala 48:55]
-  wire [4:0] _onehot_decode_T_307 = _onehot_decode_T_279 + _onehot_decode_T_305; // @[Bitwise.scala 48:55]
-  wire [5:0] _onehot_decode_T_309 = _onehot_decode_T_255 + _onehot_decode_T_307; // @[Bitwise.scala 48:55]
-  wire [6:0] onehot_decode = _onehot_decode_T_205 + _onehot_decode_T_309; // @[Bitwise.scala 48:55]
-  wire [6:0] _GEN_33 = {{6'd0}, io_undef}; // @[Decode.scala 817:24]
-  wire [6:0] _T_5 = onehot_decode + _GEN_33; // @[Decode.scala 817:24]
-  wire  _T_6 = _T_5 != 7'h1; // @[Decode.scala 817:36]
+  wire  io_undef_value_6_0 = io_undef_value_5_0 | io_undef_value_3_4; // @[Library.scala 194:39]
+  reg  onehot_failed; // @[Decode.scala 651:30]
+  wire  _T_2 = ~reset; // @[Decode.scala 652:9]
+  wire [1:0] _onehot_decode_T_77 = decoded[0] + decoded[1]; // @[Bitwise.scala 48:55]
+  wire [1:0] _onehot_decode_T_79 = decoded[2] + decoded[3]; // @[Bitwise.scala 48:55]
+  wire [2:0] _onehot_decode_T_81 = _onehot_decode_T_77 + _onehot_decode_T_79; // @[Bitwise.scala 48:55]
+  wire [1:0] _onehot_decode_T_83 = decoded[4] + decoded[5]; // @[Bitwise.scala 48:55]
+  wire [1:0] _onehot_decode_T_85 = decoded[7] + decoded[8]; // @[Bitwise.scala 48:55]
+  wire [1:0] _GEN_1 = {{1'd0}, decoded[6]}; // @[Bitwise.scala 48:55]
+  wire [2:0] _onehot_decode_T_87 = _GEN_1 + _onehot_decode_T_85; // @[Bitwise.scala 48:55]
+  wire [2:0] _onehot_decode_T_89 = _onehot_decode_T_83 + _onehot_decode_T_87[1:0]; // @[Bitwise.scala 48:55]
+  wire [3:0] _onehot_decode_T_91 = _onehot_decode_T_81 + _onehot_decode_T_89; // @[Bitwise.scala 48:55]
+  wire [1:0] _onehot_decode_T_93 = decoded[9] + decoded[10]; // @[Bitwise.scala 48:55]
+  wire [1:0] _onehot_decode_T_95 = decoded[12] + decoded[13]; // @[Bitwise.scala 48:55]
+  wire [1:0] _GEN_2 = {{1'd0}, decoded[11]}; // @[Bitwise.scala 48:55]
+  wire [2:0] _onehot_decode_T_97 = _GEN_2 + _onehot_decode_T_95; // @[Bitwise.scala 48:55]
+  wire [2:0] _onehot_decode_T_99 = _onehot_decode_T_93 + _onehot_decode_T_97[1:0]; // @[Bitwise.scala 48:55]
+  wire [1:0] _onehot_decode_T_101 = decoded[14] + decoded[15]; // @[Bitwise.scala 48:55]
+  wire [1:0] _onehot_decode_T_103 = decoded[17] + decoded[18]; // @[Bitwise.scala 48:55]
+  wire [1:0] _GEN_3 = {{1'd0}, decoded[16]}; // @[Bitwise.scala 48:55]
+  wire [2:0] _onehot_decode_T_105 = _GEN_3 + _onehot_decode_T_103; // @[Bitwise.scala 48:55]
+  wire [2:0] _onehot_decode_T_107 = _onehot_decode_T_101 + _onehot_decode_T_105[1:0]; // @[Bitwise.scala 48:55]
+  wire [3:0] _onehot_decode_T_109 = _onehot_decode_T_99 + _onehot_decode_T_107; // @[Bitwise.scala 48:55]
+  wire [4:0] _onehot_decode_T_111 = _onehot_decode_T_91 + _onehot_decode_T_109; // @[Bitwise.scala 48:55]
+  wire [1:0] _onehot_decode_T_113 = decoded[19] + decoded[20]; // @[Bitwise.scala 48:55]
+  wire [1:0] _onehot_decode_T_115 = decoded[21] + decoded[22]; // @[Bitwise.scala 48:55]
+  wire [2:0] _onehot_decode_T_117 = _onehot_decode_T_113 + _onehot_decode_T_115; // @[Bitwise.scala 48:55]
+  wire [1:0] _onehot_decode_T_119 = decoded[23] + decoded[24]; // @[Bitwise.scala 48:55]
+  wire [1:0] _onehot_decode_T_121 = decoded[26] + decoded[27]; // @[Bitwise.scala 48:55]
+  wire [1:0] _GEN_4 = {{1'd0}, decoded[25]}; // @[Bitwise.scala 48:55]
+  wire [2:0] _onehot_decode_T_123 = _GEN_4 + _onehot_decode_T_121; // @[Bitwise.scala 48:55]
+  wire [2:0] _onehot_decode_T_125 = _onehot_decode_T_119 + _onehot_decode_T_123[1:0]; // @[Bitwise.scala 48:55]
+  wire [3:0] _onehot_decode_T_127 = _onehot_decode_T_117 + _onehot_decode_T_125; // @[Bitwise.scala 48:55]
+  wire [1:0] _onehot_decode_T_129 = decoded[28] + decoded[29]; // @[Bitwise.scala 48:55]
+  wire [1:0] _onehot_decode_T_131 = decoded[31] + decoded[32]; // @[Bitwise.scala 48:55]
+  wire [1:0] _GEN_5 = {{1'd0}, decoded[30]}; // @[Bitwise.scala 48:55]
+  wire [2:0] _onehot_decode_T_133 = _GEN_5 + _onehot_decode_T_131; // @[Bitwise.scala 48:55]
+  wire [2:0] _onehot_decode_T_135 = _onehot_decode_T_129 + _onehot_decode_T_133[1:0]; // @[Bitwise.scala 48:55]
+  wire [1:0] _onehot_decode_T_137 = decoded[33] + decoded[34]; // @[Bitwise.scala 48:55]
+  wire [1:0] _onehot_decode_T_139 = decoded[36] + decoded[37]; // @[Bitwise.scala 48:55]
+  wire [1:0] _GEN_6 = {{1'd0}, decoded[35]}; // @[Bitwise.scala 48:55]
+  wire [2:0] _onehot_decode_T_141 = _GEN_6 + _onehot_decode_T_139; // @[Bitwise.scala 48:55]
+  wire [2:0] _onehot_decode_T_143 = _onehot_decode_T_137 + _onehot_decode_T_141[1:0]; // @[Bitwise.scala 48:55]
+  wire [3:0] _onehot_decode_T_145 = _onehot_decode_T_135 + _onehot_decode_T_143; // @[Bitwise.scala 48:55]
+  wire [4:0] _onehot_decode_T_147 = _onehot_decode_T_127 + _onehot_decode_T_145; // @[Bitwise.scala 48:55]
+  wire [5:0] _onehot_decode_T_149 = _onehot_decode_T_111 + _onehot_decode_T_147; // @[Bitwise.scala 48:55]
+  wire [1:0] _onehot_decode_T_151 = decoded[38] + decoded[39]; // @[Bitwise.scala 48:55]
+  wire [1:0] _onehot_decode_T_153 = decoded[40] + decoded[41]; // @[Bitwise.scala 48:55]
+  wire [2:0] _onehot_decode_T_155 = _onehot_decode_T_151 + _onehot_decode_T_153; // @[Bitwise.scala 48:55]
+  wire [1:0] _onehot_decode_T_157 = decoded[42] + decoded[43]; // @[Bitwise.scala 48:55]
+  wire [1:0] _onehot_decode_T_159 = decoded[45] + decoded[46]; // @[Bitwise.scala 48:55]
+  wire [1:0] _GEN_7 = {{1'd0}, decoded[44]}; // @[Bitwise.scala 48:55]
+  wire [2:0] _onehot_decode_T_161 = _GEN_7 + _onehot_decode_T_159; // @[Bitwise.scala 48:55]
+  wire [2:0] _onehot_decode_T_163 = _onehot_decode_T_157 + _onehot_decode_T_161[1:0]; // @[Bitwise.scala 48:55]
+  wire [3:0] _onehot_decode_T_165 = _onehot_decode_T_155 + _onehot_decode_T_163; // @[Bitwise.scala 48:55]
+  wire [1:0] _onehot_decode_T_167 = decoded[47] + decoded[48]; // @[Bitwise.scala 48:55]
+  wire [1:0] _onehot_decode_T_169 = decoded[50] + decoded[51]; // @[Bitwise.scala 48:55]
+  wire [1:0] _GEN_8 = {{1'd0}, decoded[49]}; // @[Bitwise.scala 48:55]
+  wire [2:0] _onehot_decode_T_171 = _GEN_8 + _onehot_decode_T_169; // @[Bitwise.scala 48:55]
+  wire [2:0] _onehot_decode_T_173 = _onehot_decode_T_167 + _onehot_decode_T_171[1:0]; // @[Bitwise.scala 48:55]
+  wire [1:0] _onehot_decode_T_175 = decoded[52] + decoded[53]; // @[Bitwise.scala 48:55]
+  wire [1:0] _onehot_decode_T_177 = decoded[55] + decoded[56]; // @[Bitwise.scala 48:55]
+  wire [1:0] _GEN_9 = {{1'd0}, decoded[54]}; // @[Bitwise.scala 48:55]
+  wire [2:0] _onehot_decode_T_179 = _GEN_9 + _onehot_decode_T_177; // @[Bitwise.scala 48:55]
+  wire [2:0] _onehot_decode_T_181 = _onehot_decode_T_175 + _onehot_decode_T_179[1:0]; // @[Bitwise.scala 48:55]
+  wire [3:0] _onehot_decode_T_183 = _onehot_decode_T_173 + _onehot_decode_T_181; // @[Bitwise.scala 48:55]
+  wire [4:0] _onehot_decode_T_185 = _onehot_decode_T_165 + _onehot_decode_T_183; // @[Bitwise.scala 48:55]
+  wire [1:0] _onehot_decode_T_187 = decoded[57] + decoded[58]; // @[Bitwise.scala 48:55]
+  wire [1:0] _onehot_decode_T_189 = decoded[60] + decoded[61]; // @[Bitwise.scala 48:55]
+  wire [1:0] _GEN_10 = {{1'd0}, decoded[59]}; // @[Bitwise.scala 48:55]
+  wire [2:0] _onehot_decode_T_191 = _GEN_10 + _onehot_decode_T_189; // @[Bitwise.scala 48:55]
+  wire [2:0] _onehot_decode_T_193 = _onehot_decode_T_187 + _onehot_decode_T_191[1:0]; // @[Bitwise.scala 48:55]
+  wire [1:0] _onehot_decode_T_195 = decoded[62] + decoded[63]; // @[Bitwise.scala 48:55]
+  wire [1:0] _onehot_decode_T_197 = decoded[65] + decoded[66]; // @[Bitwise.scala 48:55]
+  wire [1:0] _GEN_11 = {{1'd0}, decoded[64]}; // @[Bitwise.scala 48:55]
+  wire [2:0] _onehot_decode_T_199 = _GEN_11 + _onehot_decode_T_197; // @[Bitwise.scala 48:55]
+  wire [2:0] _onehot_decode_T_201 = _onehot_decode_T_195 + _onehot_decode_T_199[1:0]; // @[Bitwise.scala 48:55]
+  wire [3:0] _onehot_decode_T_203 = _onehot_decode_T_193 + _onehot_decode_T_201; // @[Bitwise.scala 48:55]
+  wire [1:0] _onehot_decode_T_205 = decoded[67] + decoded[68]; // @[Bitwise.scala 48:55]
+  wire [1:0] _onehot_decode_T_207 = decoded[70] + decoded[71]; // @[Bitwise.scala 48:55]
+  wire [1:0] _GEN_12 = {{1'd0}, decoded[69]}; // @[Bitwise.scala 48:55]
+  wire [2:0] _onehot_decode_T_209 = _GEN_12 + _onehot_decode_T_207; // @[Bitwise.scala 48:55]
+  wire [2:0] _onehot_decode_T_211 = _onehot_decode_T_205 + _onehot_decode_T_209[1:0]; // @[Bitwise.scala 48:55]
+  wire [1:0] _onehot_decode_T_213 = decoded[72] + decoded[73]; // @[Bitwise.scala 48:55]
+  wire [1:0] _onehot_decode_T_215 = decoded[75] + io_undef_value__38; // @[Bitwise.scala 48:55]
+  wire [1:0] _GEN_13 = {{1'd0}, decoded[74]}; // @[Bitwise.scala 48:55]
+  wire [2:0] _onehot_decode_T_217 = _GEN_13 + _onehot_decode_T_215; // @[Bitwise.scala 48:55]
+  wire [2:0] _onehot_decode_T_219 = _onehot_decode_T_213 + _onehot_decode_T_217[1:0]; // @[Bitwise.scala 48:55]
+  wire [3:0] _onehot_decode_T_221 = _onehot_decode_T_211 + _onehot_decode_T_219; // @[Bitwise.scala 48:55]
+  wire [4:0] _onehot_decode_T_223 = _onehot_decode_T_203 + _onehot_decode_T_221; // @[Bitwise.scala 48:55]
+  wire [5:0] _onehot_decode_T_225 = _onehot_decode_T_185 + _onehot_decode_T_223; // @[Bitwise.scala 48:55]
+  wire [6:0] onehot_decode = _onehot_decode_T_149 + _onehot_decode_T_225; // @[Bitwise.scala 48:55]
+  wire [6:0] _GEN_14 = {{6'd0}, io_undef}; // @[Decode.scala 655:24]
+  wire [6:0] _T_5 = onehot_decode + _GEN_14; // @[Decode.scala 655:24]
+  wire  _T_6 = _T_5 != 7'h1; // @[Decode.scala 655:36]
   assign io_imm12 = {_io_imm12_T_2,io_inst[31:20]}; // @[Cat.scala 31:58]
   assign io_imm20 = {io_inst[31:12],12'h0}; // @[Cat.scala 31:58]
   assign io_immjal = {io_immjal_hi,io_immjal_lo}; // @[Cat.scala 31:58]
   assign io_immbr = {io_immbr_hi,io_immbr_lo}; // @[Cat.scala 31:58]
   assign io_immst = {io_immst_hi,io_inst[11:7]}; // @[Cat.scala 31:58]
-  assign io_lui = _io_lui_T_3 & io_lui_bit_29 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 314:48]
-  assign io_auipc = _io_auipc_T_3 & io_lui_bit_29 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 314:48]
-  assign io_jal = _io_jal_T_2 & io_inst[3] & io_lui_bit_29 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 314:48]
-  assign io_jalr = _io_jalr_T_6 & io_lui_bit_29 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 314:48]
-  assign io_beq = _io_beq_T_7 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 314:48]
-  assign io_bne = _io_bne_T_7 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 314:48]
-  assign io_blt = _io_blt_T_7 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 314:48]
-  assign io_bge = _io_bge_T_7 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 314:48]
-  assign io_bltu = _io_bltu_T_7 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 314:48]
-  assign io_bgeu = _io_bgeu_T_7 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 314:48]
-  assign io_csrrw = 1'h0; // @[Decode.scala 734:14]
-  assign io_csrrs = 1'h0; // @[Decode.scala 735:14]
-  assign io_csrrc = 1'h0; // @[Decode.scala 736:14]
-  assign io_lb = _io_lb_T_7 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 314:48]
-  assign io_lh = _io_lh_T_7 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 314:48]
-  assign io_lw = _io_lw_T_7 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 314:48]
-  assign io_lbu = _io_lbu_T_7 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 314:48]
-  assign io_lhu = _io_lhu_T_7 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 314:48]
-  assign io_sb = _io_sb_T_7 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 314:48]
-  assign io_sh = _io_sh_T_7 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 314:48]
-  assign io_sw = _io_sw_T_7 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 314:48]
-  assign io_fence = 1'h0; // @[Decode.scala 778:17]
-  assign io_addi = _io_addi_T_7 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 314:48]
-  assign io_slti = _io_slti_T_7 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 314:48]
-  assign io_sltiu = _io_sltiu_T_7 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 314:48]
-  assign io_xori = _io_xori_T_7 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 314:48]
-  assign io_ori = _io_ori_T_7 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 314:48]
-  assign io_andi = _io_andi_T_7 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 314:48]
-  assign io_slli = _io_slli_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 314:48]
-  assign io_srli = _io_srli_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 314:48]
-  assign io_srai = _io_srai_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 314:48]
-  assign io_add = _io_add_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 314:48]
-  assign io_sub = _io_sub_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 314:48]
-  assign io_slt = _io_slt_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 314:48]
-  assign io_sltu = _io_sltu_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 314:48]
-  assign io_xor = _io_xor_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 314:48]
-  assign io_or = _io_or_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 314:48]
-  assign io_and = _io_and_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 314:48]
-  assign io_sll = _io_sll_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 314:48]
-  assign io_srl = _io_srl_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 314:48]
-  assign io_sra = _io_sra_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 314:48]
-  assign io_mul = _io_mul_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 314:48]
-  assign io_mulh = _io_mulh_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 314:48]
-  assign io_mulhsu = _io_mulhsu_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 314:48]
-  assign io_mulhu = _io_mulhu_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 314:48]
-  assign io_mulhr = _io_mulhr_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 314:48]
-  assign io_mulhsur = _io_mulhsur_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 314:48]
-  assign io_mulhur = _io_mulhur_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 314:48]
-  assign io_dmulh = _io_dmulh_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 314:48]
-  assign io_dmulhr = _io_dmulhr_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 314:48]
-  assign io_div = 1'h0; // @[Decode.scala 738:12]
-  assign io_divu = 1'h0; // @[Decode.scala 739:13]
-  assign io_rem = 1'h0; // @[Decode.scala 740:12]
-  assign io_remu = 1'h0; // @[Decode.scala 741:13]
-  assign io_flw = 1'h0; // @[Decode.scala 743:12]
-  assign io_fsw = 1'h0; // @[Decode.scala 744:12]
-  assign io_fmadd = 1'h0; // @[Decode.scala 745:14]
-  assign io_fmsub = 1'h0; // @[Decode.scala 746:14]
-  assign io_fnmsub = 1'h0; // @[Decode.scala 747:15]
-  assign io_fnmadd = 1'h0; // @[Decode.scala 748:15]
-  assign io_fadd = 1'h0; // @[Decode.scala 749:13]
-  assign io_fsub = 1'h0; // @[Decode.scala 750:13]
-  assign io_fmul = 1'h0; // @[Decode.scala 751:13]
-  assign io_fdiv = 1'h0; // @[Decode.scala 752:13]
-  assign io_fsqrt = 1'h0; // @[Decode.scala 753:14]
-  assign io_fsgnj = 1'h0; // @[Decode.scala 754:14]
-  assign io_fsgnjn = 1'h0; // @[Decode.scala 755:15]
-  assign io_fsgnjx = 1'h0; // @[Decode.scala 756:15]
-  assign io_fmin = 1'h0; // @[Decode.scala 757:13]
-  assign io_fmax = 1'h0; // @[Decode.scala 758:13]
-  assign io_fcvtws = 1'h0; // @[Decode.scala 759:15]
-  assign io_fcvtwus = 1'h0; // @[Decode.scala 760:16]
-  assign io_fmvxw = 1'h0; // @[Decode.scala 761:14]
-  assign io_feq = 1'h0; // @[Decode.scala 762:12]
-  assign io_flt = 1'h0; // @[Decode.scala 763:12]
-  assign io_fle = 1'h0; // @[Decode.scala 764:12]
-  assign io_fclass = 1'h0; // @[Decode.scala 765:15]
-  assign io_fcvtsw = 1'h0; // @[Decode.scala 766:15]
-  assign io_fcvtswu = 1'h0; // @[Decode.scala 767:16]
-  assign io_fmvwx = 1'h0; // @[Decode.scala 768:14]
-  assign io_clb = _io_clb_T_19 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 314:48]
-  assign io_clz = _io_clz_T_19 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 314:48]
-  assign io_ctz = _io_ctz_T_19 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 314:48]
-  assign io_pcnt = _io_pcnt_T_19 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 314:48]
-  assign io_min = _io_min_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 314:48]
-  assign io_minu = _io_minu_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 314:48]
-  assign io_max = _io_max_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 314:48]
-  assign io_maxu = _io_maxu_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 314:48]
-  assign io_getvl = _io_getvl_T_13 & io_inst[26:25] != 2'h3 & (io_inst[24:20] != 5'h0 | io_inst[19:15] != 5'h0); // @[Decode.scala 688:97]
-  assign io_getmaxvl = _io_getmaxvl_T_23 & _io_getvl_T_15; // @[Decode.scala 689:76]
-  assign io_vld = _io_vld_T_4 & io_lui_bit_27 & io_inst[3] & io_lui_bit_29 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 314:48]
-  assign io_vst = _io_vst_T_9 | _io_vst_T_19; // @[Decode.scala 694:71]
-  assign io_viop = _io_viop_T_9 | vdupi; // @[Decode.scala 713:20]
-  assign io_vfop = vfma | vfma4 | vdupf; // @[Decode.scala 708:28]
-  assign io_ebreak = 1'h0; // @[Decode.scala 770:15]
-  assign io_ecall = 1'h0; // @[Decode.scala 771:15]
-  assign io_eexit = 1'h0; // @[Decode.scala 772:15]
-  assign io_eyield = 1'h0; // @[Decode.scala 773:15]
-  assign io_ectxsw = 1'h0; // @[Decode.scala 774:15]
-  assign io_mpause = 1'h0; // @[Decode.scala 775:15]
-  assign io_mret = 1'h0; // @[Decode.scala 776:15]
-  assign io_undef = ~io_undef_value_6_0; // @[Decode.scala 810:15]
-  assign io_fencei = 1'h0; // @[Decode.scala 779:17]
-  assign io_flushat = 1'h0; // @[Decode.scala 780:17]
-  assign io_flushall = 1'h0; // @[Decode.scala 781:17]
-  assign io_slog = 1'h0; // @[Decode.scala 783:13]
+  assign io_lui = _io_lui_T_3 & io_lui_bit_29 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 316:48]
+  assign io_auipc = _io_auipc_T_3 & io_lui_bit_29 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 316:48]
+  assign io_jal = _io_jal_T_2 & io_inst[3] & io_lui_bit_29 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 316:48]
+  assign io_jalr = _io_jalr_T_6 & io_lui_bit_29 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 316:48]
+  assign io_beq = _io_beq_T_7 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 316:48]
+  assign io_bne = _io_bne_T_7 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 316:48]
+  assign io_blt = _io_blt_T_7 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 316:48]
+  assign io_bge = _io_bge_T_7 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 316:48]
+  assign io_bltu = _io_bltu_T_7 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 316:48]
+  assign io_bgeu = _io_bgeu_T_7 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 316:48]
+  assign io_csrrw = 1'h0; // @[Decode.scala 605:14]
+  assign io_csrrs = 1'h0; // @[Decode.scala 606:14]
+  assign io_csrrc = 1'h0; // @[Decode.scala 607:14]
+  assign io_lb = _io_lb_T_7 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 316:48]
+  assign io_lh = _io_lh_T_7 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 316:48]
+  assign io_lw = _io_lw_T_7 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 316:48]
+  assign io_lbu = _io_lbu_T_7 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 316:48]
+  assign io_lhu = _io_lhu_T_7 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 316:48]
+  assign io_sb = _io_sb_T_7 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 316:48]
+  assign io_sh = _io_sh_T_7 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 316:48]
+  assign io_sw = _io_sw_T_7 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 316:48]
+  assign io_fence = 1'h0; // @[Decode.scala 622:17]
+  assign io_addi = _io_addi_T_7 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 316:48]
+  assign io_slti = _io_slti_T_7 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 316:48]
+  assign io_sltiu = _io_sltiu_T_7 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 316:48]
+  assign io_xori = _io_xori_T_7 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 316:48]
+  assign io_ori = _io_ori_T_7 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 316:48]
+  assign io_andi = _io_andi_T_7 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 316:48]
+  assign io_slli = _io_slli_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 316:48]
+  assign io_srli = _io_srli_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 316:48]
+  assign io_srai = _io_srai_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 316:48]
+  assign io_add = _io_add_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 316:48]
+  assign io_sub = _io_sub_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 316:48]
+  assign io_slt = _io_slt_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 316:48]
+  assign io_sltu = _io_sltu_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 316:48]
+  assign io_xor = _io_xor_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 316:48]
+  assign io_or = _io_or_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 316:48]
+  assign io_and = _io_and_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 316:48]
+  assign io_sll = _io_sll_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 316:48]
+  assign io_srl = _io_srl_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 316:48]
+  assign io_sra = _io_sra_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 316:48]
+  assign io_mul = _io_mul_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 316:48]
+  assign io_mulh = _io_mulh_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 316:48]
+  assign io_mulhsu = _io_mulhsu_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 316:48]
+  assign io_mulhu = _io_mulhu_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 316:48]
+  assign io_mulhr = _io_mulhr_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 316:48]
+  assign io_mulhsur = _io_mulhsur_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 316:48]
+  assign io_mulhur = _io_mulhur_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 316:48]
+  assign io_dmulh = _io_dmulh_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 316:48]
+  assign io_dmulhr = _io_dmulhr_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 316:48]
+  assign io_div = 1'h0; // @[Decode.scala 609:12]
+  assign io_divu = 1'h0; // @[Decode.scala 610:13]
+  assign io_rem = 1'h0; // @[Decode.scala 611:12]
+  assign io_remu = 1'h0; // @[Decode.scala 612:13]
+  assign io_clz = _io_clz_T_19 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 316:48]
+  assign io_ctz = _io_ctz_T_19 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 316:48]
+  assign io_pcnt = _io_pcnt_T_19 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 316:48]
+  assign io_min = _io_min_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 316:48]
+  assign io_minu = _io_minu_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 316:48]
+  assign io_max = _io_max_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 316:48]
+  assign io_maxu = _io_maxu_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 316:48]
+  assign io_getvl = _io_getvl_T_13 & io_inst[26:25] != 2'h3 & (io_inst[24:20] != 5'h0 | io_inst[19:15] != 5'h0); // @[Decode.scala 565:97]
+  assign io_getmaxvl = _io_getmaxvl_T_23 & _io_getvl_T_15; // @[Decode.scala 566:76]
+  assign io_vld = _io_vld_T_4 & io_lui_bit_27 & io_inst[3] & io_lui_bit_29 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 316:48]
+  assign io_vst = _io_vst_T_9 | _io_vst_T_19; // @[Decode.scala 571:71]
+  assign io_viop = _io_viop_T_5 | vdupi; // @[Decode.scala 584:20]
+  assign io_ebreak = 1'h0; // @[Decode.scala 614:15]
+  assign io_ecall = 1'h0; // @[Decode.scala 615:15]
+  assign io_eexit = 1'h0; // @[Decode.scala 616:15]
+  assign io_eyield = 1'h0; // @[Decode.scala 617:15]
+  assign io_ectxsw = 1'h0; // @[Decode.scala 618:15]
+  assign io_mpause = 1'h0; // @[Decode.scala 619:15]
+  assign io_mret = 1'h0; // @[Decode.scala 620:15]
+  assign io_undef = ~io_undef_value_6_0; // @[Decode.scala 648:15]
+  assign io_fencei = 1'h0; // @[Decode.scala 623:17]
+  assign io_flushat = 1'h0; // @[Decode.scala 624:17]
+  assign io_flushall = 1'h0; // @[Decode.scala 625:17]
+  assign io_slog = 1'h0; // @[Decode.scala 627:13]
   always @(posedge clock) begin
     `ifndef SYNTHESIS
     `ifdef STOP_COND
       if (`STOP_COND) begin
     `endif
         if (~reset & ~(~onehot_failed)) begin
-          $fatal; // @[Decode.scala 814:9]
+          $fatal; // @[Decode.scala 652:9]
         end
     `ifdef STOP_COND
       end
@@ -10191,7 +9578,7 @@
       if (`PRINTF_COND) begin
     `endif
         if (~reset & ~(~onehot_failed)) begin
-          $fwrite(32'h80000002,"Assertion failed\n    at Decode.scala:814 assert(!onehot_failed)\n"); // @[Decode.scala 814:9]
+          $fwrite(32'h80000002,"Assertion failed\n    at Decode.scala:652 assert(!onehot_failed)\n"); // @[Decode.scala 652:9]
         end
     `ifdef PRINTF_COND
       end
@@ -10203,7 +9590,7 @@
     `endif
         if (_T_6 & _T_2) begin
           $fwrite(32'h80000002,"[FAIL] decode  inst=%x  addr=%x  decoded=0b%b  pipeline=%d\n",io_inst,io_addr,decoded,1'h1
-            ); // @[Decode.scala 819:11]
+            ); // @[Decode.scala 657:11]
         end
     `ifdef PRINTF_COND
       end
@@ -10211,10 +9598,10 @@
     `endif // SYNTHESIS
   end
   always @(posedge clock or posedge reset) begin
-    if (reset) begin // @[Decode.scala 817:45]
-      onehot_failed <= 1'h0; // @[Decode.scala 818:19]
+    if (reset) begin // @[Decode.scala 655:45]
+      onehot_failed <= 1'h0; // @[Decode.scala 656:19]
     end else begin
-      onehot_failed <= _T_5 != 7'h1 | onehot_failed; // @[Decode.scala 813:30]
+      onehot_failed <= _T_5 != 7'h1 | onehot_failed; // @[Decode.scala 651:30]
     end
   end
 // Register and memory initialization
@@ -10278,7 +9665,6 @@
   input  [31:0] io_scoreboard_regd,
   input  [31:0] io_scoreboard_comb,
   output [31:0] io_scoreboard_spec,
-  input  [31:0] io_fscoreboard,
   output        io_rs1Read_valid,
   output [4:0]  io_rs1Read_addr,
   output        io_rs1Set_valid,
@@ -10293,7 +9679,7 @@
   output [31:0] io_busRead_immed,
   output        io_alu_valid,
   output [4:0]  io_alu_addr,
-  output [18:0] io_alu_op,
+  output [17:0] io_alu_op,
   output        io_bru_valid,
   output        io_bru_fwd,
   output [16:0] io_bru_op,
@@ -10304,18 +9690,16 @@
   output        io_lsu_valid,
   input         io_lsu_ready,
   output [4:0]  io_lsu_addr,
-  output [13:0] io_lsu_op,
+  output [11:0] io_lsu_op,
   output        io_mlu_valid,
   output [4:0]  io_mlu_addr,
   output [8:0]  io_mlu_op,
   output [3:0]  io_dvu_op,
-  output [4:0]  io_fpu_raddr_1,
-  output [26:0] io_fpu_op,
   output        io_vinst_valid,
   input         io_vinst_ready,
   output [4:0]  io_vinst_addr,
   output [31:0] io_vinst_inst,
-  output [5:0]  io_vinst_op,
+  output [4:0]  io_vinst_op,
   input         io_branchTaken,
   input         io_interlock,
   input         io_serializeIn_mul,
@@ -10325,172 +9709,136 @@
   output        io_serializeOut_jump,
   output        io_serializeOut_brcond
 );
-  wire  d_clock; // @[Decode.scala 91:17]
-  wire  d_reset; // @[Decode.scala 91:17]
-  wire [31:0] d_io_addr; // @[Decode.scala 91:17]
-  wire [31:0] d_io_inst; // @[Decode.scala 91:17]
-  wire [31:0] d_io_imm12; // @[Decode.scala 91:17]
-  wire [31:0] d_io_imm20; // @[Decode.scala 91:17]
-  wire [31:0] d_io_immjal; // @[Decode.scala 91:17]
-  wire [31:0] d_io_immbr; // @[Decode.scala 91:17]
-  wire [31:0] d_io_immst; // @[Decode.scala 91:17]
-  wire  d_io_lui; // @[Decode.scala 91:17]
-  wire  d_io_auipc; // @[Decode.scala 91:17]
-  wire  d_io_jal; // @[Decode.scala 91:17]
-  wire  d_io_jalr; // @[Decode.scala 91:17]
-  wire  d_io_beq; // @[Decode.scala 91:17]
-  wire  d_io_bne; // @[Decode.scala 91:17]
-  wire  d_io_blt; // @[Decode.scala 91:17]
-  wire  d_io_bge; // @[Decode.scala 91:17]
-  wire  d_io_bltu; // @[Decode.scala 91:17]
-  wire  d_io_bgeu; // @[Decode.scala 91:17]
-  wire  d_io_csrrw; // @[Decode.scala 91:17]
-  wire  d_io_csrrs; // @[Decode.scala 91:17]
-  wire  d_io_csrrc; // @[Decode.scala 91:17]
-  wire  d_io_lb; // @[Decode.scala 91:17]
-  wire  d_io_lh; // @[Decode.scala 91:17]
-  wire  d_io_lw; // @[Decode.scala 91:17]
-  wire  d_io_lbu; // @[Decode.scala 91:17]
-  wire  d_io_lhu; // @[Decode.scala 91:17]
-  wire  d_io_sb; // @[Decode.scala 91:17]
-  wire  d_io_sh; // @[Decode.scala 91:17]
-  wire  d_io_sw; // @[Decode.scala 91:17]
-  wire  d_io_fence; // @[Decode.scala 91:17]
-  wire  d_io_addi; // @[Decode.scala 91:17]
-  wire  d_io_slti; // @[Decode.scala 91:17]
-  wire  d_io_sltiu; // @[Decode.scala 91:17]
-  wire  d_io_xori; // @[Decode.scala 91:17]
-  wire  d_io_ori; // @[Decode.scala 91:17]
-  wire  d_io_andi; // @[Decode.scala 91:17]
-  wire  d_io_slli; // @[Decode.scala 91:17]
-  wire  d_io_srli; // @[Decode.scala 91:17]
-  wire  d_io_srai; // @[Decode.scala 91:17]
-  wire  d_io_add; // @[Decode.scala 91:17]
-  wire  d_io_sub; // @[Decode.scala 91:17]
-  wire  d_io_slt; // @[Decode.scala 91:17]
-  wire  d_io_sltu; // @[Decode.scala 91:17]
-  wire  d_io_xor; // @[Decode.scala 91:17]
-  wire  d_io_or; // @[Decode.scala 91:17]
-  wire  d_io_and; // @[Decode.scala 91:17]
-  wire  d_io_sll; // @[Decode.scala 91:17]
-  wire  d_io_srl; // @[Decode.scala 91:17]
-  wire  d_io_sra; // @[Decode.scala 91:17]
-  wire  d_io_mul; // @[Decode.scala 91:17]
-  wire  d_io_mulh; // @[Decode.scala 91:17]
-  wire  d_io_mulhsu; // @[Decode.scala 91:17]
-  wire  d_io_mulhu; // @[Decode.scala 91:17]
-  wire  d_io_mulhr; // @[Decode.scala 91:17]
-  wire  d_io_mulhsur; // @[Decode.scala 91:17]
-  wire  d_io_mulhur; // @[Decode.scala 91:17]
-  wire  d_io_dmulh; // @[Decode.scala 91:17]
-  wire  d_io_dmulhr; // @[Decode.scala 91:17]
-  wire  d_io_div; // @[Decode.scala 91:17]
-  wire  d_io_divu; // @[Decode.scala 91:17]
-  wire  d_io_rem; // @[Decode.scala 91:17]
-  wire  d_io_remu; // @[Decode.scala 91:17]
-  wire  d_io_flw; // @[Decode.scala 91:17]
-  wire  d_io_fsw; // @[Decode.scala 91:17]
-  wire  d_io_fmadd; // @[Decode.scala 91:17]
-  wire  d_io_fmsub; // @[Decode.scala 91:17]
-  wire  d_io_fnmsub; // @[Decode.scala 91:17]
-  wire  d_io_fnmadd; // @[Decode.scala 91:17]
-  wire  d_io_fadd; // @[Decode.scala 91:17]
-  wire  d_io_fsub; // @[Decode.scala 91:17]
-  wire  d_io_fmul; // @[Decode.scala 91:17]
-  wire  d_io_fdiv; // @[Decode.scala 91:17]
-  wire  d_io_fsqrt; // @[Decode.scala 91:17]
-  wire  d_io_fsgnj; // @[Decode.scala 91:17]
-  wire  d_io_fsgnjn; // @[Decode.scala 91:17]
-  wire  d_io_fsgnjx; // @[Decode.scala 91:17]
-  wire  d_io_fmin; // @[Decode.scala 91:17]
-  wire  d_io_fmax; // @[Decode.scala 91:17]
-  wire  d_io_fcvtws; // @[Decode.scala 91:17]
-  wire  d_io_fcvtwus; // @[Decode.scala 91:17]
-  wire  d_io_fmvxw; // @[Decode.scala 91:17]
-  wire  d_io_feq; // @[Decode.scala 91:17]
-  wire  d_io_flt; // @[Decode.scala 91:17]
-  wire  d_io_fle; // @[Decode.scala 91:17]
-  wire  d_io_fclass; // @[Decode.scala 91:17]
-  wire  d_io_fcvtsw; // @[Decode.scala 91:17]
-  wire  d_io_fcvtswu; // @[Decode.scala 91:17]
-  wire  d_io_fmvwx; // @[Decode.scala 91:17]
-  wire  d_io_clb; // @[Decode.scala 91:17]
-  wire  d_io_clz; // @[Decode.scala 91:17]
-  wire  d_io_ctz; // @[Decode.scala 91:17]
-  wire  d_io_pcnt; // @[Decode.scala 91:17]
-  wire  d_io_min; // @[Decode.scala 91:17]
-  wire  d_io_minu; // @[Decode.scala 91:17]
-  wire  d_io_max; // @[Decode.scala 91:17]
-  wire  d_io_maxu; // @[Decode.scala 91:17]
-  wire  d_io_getvl; // @[Decode.scala 91:17]
-  wire  d_io_getmaxvl; // @[Decode.scala 91:17]
-  wire  d_io_vld; // @[Decode.scala 91:17]
-  wire  d_io_vst; // @[Decode.scala 91:17]
-  wire  d_io_viop; // @[Decode.scala 91:17]
-  wire  d_io_vfop; // @[Decode.scala 91:17]
-  wire  d_io_ebreak; // @[Decode.scala 91:17]
-  wire  d_io_ecall; // @[Decode.scala 91:17]
-  wire  d_io_eexit; // @[Decode.scala 91:17]
-  wire  d_io_eyield; // @[Decode.scala 91:17]
-  wire  d_io_ectxsw; // @[Decode.scala 91:17]
-  wire  d_io_mpause; // @[Decode.scala 91:17]
-  wire  d_io_mret; // @[Decode.scala 91:17]
-  wire  d_io_undef; // @[Decode.scala 91:17]
-  wire  d_io_fencei; // @[Decode.scala 91:17]
-  wire  d_io_flushat; // @[Decode.scala 91:17]
-  wire  d_io_flushall; // @[Decode.scala 91:17]
-  wire  d_io_slog; // @[Decode.scala 91:17]
-  wire  decodeEn = io_inst_valid & io_inst_ready & ~io_branchTaken; // @[Decode.scala 88:49]
-  wire  vldst = d_io_vld | d_io_vst; // @[Decode.scala 95:24]
-  wire  vldst_wb = vldst & io_inst_inst[28]; // @[Decode.scala 96:24]
-  wire [4:0] rdAddr = vldst ? io_inst_inst[19:15] : io_inst_inst[11:7]; // @[Decode.scala 98:20]
-  wire [4:0] rs2Addr = io_inst_inst[24:20]; // @[Decode.scala 100:29]
-  wire [4:0] rs3Addr = io_inst_inst[31:27]; // @[Decode.scala 101:29]
-  wire  _isAluImm_T_3 = d_io_addi | d_io_slti | d_io_sltiu | d_io_xori | d_io_ori; // @[Decode.scala 103:68]
-  wire  isAluImm = _isAluImm_T_3 | d_io_andi | d_io_slli | d_io_srli | d_io_srai; // @[Decode.scala 104:66]
-  wire  _isAluReg_T_4 = d_io_add | d_io_sub | d_io_slt | d_io_sltu | d_io_xor | d_io_or; // @[Decode.scala 106:76]
-  wire  isAluReg = _isAluReg_T_4 | d_io_and | d_io_sll | d_io_srl | d_io_sra; // @[Decode.scala 107:62]
-  wire  isAlu1Bit = d_io_clb | d_io_clz | d_io_ctz | d_io_pcnt; // @[Decode.scala 109:52]
-  wire  isAlu2Bit = d_io_min | d_io_minu | d_io_max | d_io_maxu; // @[Decode.scala 110:53]
-  wire  _isCondBr_T_3 = d_io_beq | d_io_bne | d_io_blt | d_io_bge | d_io_bltu; // @[Decode.scala 112:63]
-  wire  isCondBr = _isCondBr_T_3 | d_io_bgeu; // @[Decode.scala 113:28]
-  wire  isLoad = d_io_lb | d_io_lh | d_io_lw | d_io_lbu | d_io_lhu; // @[Decode.scala 119:58]
-  wire  isStore = d_io_sb | d_io_sh | d_io_sw; // @[Decode.scala 120:36]
-  wire  isLsu = isLoad | isStore | d_io_vld | d_io_vst; // @[Decode.scala 121:69]
+  wire  d_clock; // @[Decode.scala 87:17]
+  wire  d_reset; // @[Decode.scala 87:17]
+  wire [31:0] d_io_addr; // @[Decode.scala 87:17]
+  wire [31:0] d_io_inst; // @[Decode.scala 87:17]
+  wire [31:0] d_io_imm12; // @[Decode.scala 87:17]
+  wire [31:0] d_io_imm20; // @[Decode.scala 87:17]
+  wire [31:0] d_io_immjal; // @[Decode.scala 87:17]
+  wire [31:0] d_io_immbr; // @[Decode.scala 87:17]
+  wire [31:0] d_io_immst; // @[Decode.scala 87:17]
+  wire  d_io_lui; // @[Decode.scala 87:17]
+  wire  d_io_auipc; // @[Decode.scala 87:17]
+  wire  d_io_jal; // @[Decode.scala 87:17]
+  wire  d_io_jalr; // @[Decode.scala 87:17]
+  wire  d_io_beq; // @[Decode.scala 87:17]
+  wire  d_io_bne; // @[Decode.scala 87:17]
+  wire  d_io_blt; // @[Decode.scala 87:17]
+  wire  d_io_bge; // @[Decode.scala 87:17]
+  wire  d_io_bltu; // @[Decode.scala 87:17]
+  wire  d_io_bgeu; // @[Decode.scala 87:17]
+  wire  d_io_csrrw; // @[Decode.scala 87:17]
+  wire  d_io_csrrs; // @[Decode.scala 87:17]
+  wire  d_io_csrrc; // @[Decode.scala 87:17]
+  wire  d_io_lb; // @[Decode.scala 87:17]
+  wire  d_io_lh; // @[Decode.scala 87:17]
+  wire  d_io_lw; // @[Decode.scala 87:17]
+  wire  d_io_lbu; // @[Decode.scala 87:17]
+  wire  d_io_lhu; // @[Decode.scala 87:17]
+  wire  d_io_sb; // @[Decode.scala 87:17]
+  wire  d_io_sh; // @[Decode.scala 87:17]
+  wire  d_io_sw; // @[Decode.scala 87:17]
+  wire  d_io_fence; // @[Decode.scala 87:17]
+  wire  d_io_addi; // @[Decode.scala 87:17]
+  wire  d_io_slti; // @[Decode.scala 87:17]
+  wire  d_io_sltiu; // @[Decode.scala 87:17]
+  wire  d_io_xori; // @[Decode.scala 87:17]
+  wire  d_io_ori; // @[Decode.scala 87:17]
+  wire  d_io_andi; // @[Decode.scala 87:17]
+  wire  d_io_slli; // @[Decode.scala 87:17]
+  wire  d_io_srli; // @[Decode.scala 87:17]
+  wire  d_io_srai; // @[Decode.scala 87:17]
+  wire  d_io_add; // @[Decode.scala 87:17]
+  wire  d_io_sub; // @[Decode.scala 87:17]
+  wire  d_io_slt; // @[Decode.scala 87:17]
+  wire  d_io_sltu; // @[Decode.scala 87:17]
+  wire  d_io_xor; // @[Decode.scala 87:17]
+  wire  d_io_or; // @[Decode.scala 87:17]
+  wire  d_io_and; // @[Decode.scala 87:17]
+  wire  d_io_sll; // @[Decode.scala 87:17]
+  wire  d_io_srl; // @[Decode.scala 87:17]
+  wire  d_io_sra; // @[Decode.scala 87:17]
+  wire  d_io_mul; // @[Decode.scala 87:17]
+  wire  d_io_mulh; // @[Decode.scala 87:17]
+  wire  d_io_mulhsu; // @[Decode.scala 87:17]
+  wire  d_io_mulhu; // @[Decode.scala 87:17]
+  wire  d_io_mulhr; // @[Decode.scala 87:17]
+  wire  d_io_mulhsur; // @[Decode.scala 87:17]
+  wire  d_io_mulhur; // @[Decode.scala 87:17]
+  wire  d_io_dmulh; // @[Decode.scala 87:17]
+  wire  d_io_dmulhr; // @[Decode.scala 87:17]
+  wire  d_io_div; // @[Decode.scala 87:17]
+  wire  d_io_divu; // @[Decode.scala 87:17]
+  wire  d_io_rem; // @[Decode.scala 87:17]
+  wire  d_io_remu; // @[Decode.scala 87:17]
+  wire  d_io_clz; // @[Decode.scala 87:17]
+  wire  d_io_ctz; // @[Decode.scala 87:17]
+  wire  d_io_pcnt; // @[Decode.scala 87:17]
+  wire  d_io_min; // @[Decode.scala 87:17]
+  wire  d_io_minu; // @[Decode.scala 87:17]
+  wire  d_io_max; // @[Decode.scala 87:17]
+  wire  d_io_maxu; // @[Decode.scala 87:17]
+  wire  d_io_getvl; // @[Decode.scala 87:17]
+  wire  d_io_getmaxvl; // @[Decode.scala 87:17]
+  wire  d_io_vld; // @[Decode.scala 87:17]
+  wire  d_io_vst; // @[Decode.scala 87:17]
+  wire  d_io_viop; // @[Decode.scala 87:17]
+  wire  d_io_ebreak; // @[Decode.scala 87:17]
+  wire  d_io_ecall; // @[Decode.scala 87:17]
+  wire  d_io_eexit; // @[Decode.scala 87:17]
+  wire  d_io_eyield; // @[Decode.scala 87:17]
+  wire  d_io_ectxsw; // @[Decode.scala 87:17]
+  wire  d_io_mpause; // @[Decode.scala 87:17]
+  wire  d_io_mret; // @[Decode.scala 87:17]
+  wire  d_io_undef; // @[Decode.scala 87:17]
+  wire  d_io_fencei; // @[Decode.scala 87:17]
+  wire  d_io_flushat; // @[Decode.scala 87:17]
+  wire  d_io_flushall; // @[Decode.scala 87:17]
+  wire  d_io_slog; // @[Decode.scala 87:17]
+  wire  decodeEn = io_inst_valid & io_inst_ready & ~io_branchTaken; // @[Decode.scala 84:49]
+  wire  vldst = d_io_vld | d_io_vst; // @[Decode.scala 91:24]
+  wire  vldst_wb = vldst & io_inst_inst[28]; // @[Decode.scala 92:24]
+  wire [4:0] rdAddr = vldst ? io_inst_inst[19:15] : io_inst_inst[11:7]; // @[Decode.scala 94:20]
+  wire [4:0] rs2Addr = io_inst_inst[24:20]; // @[Decode.scala 96:29]
+  wire [4:0] rs3Addr = io_inst_inst[31:27]; // @[Decode.scala 97:29]
+  wire  _isAluImm_T_3 = d_io_addi | d_io_slti | d_io_sltiu | d_io_xori | d_io_ori; // @[Decode.scala 99:68]
+  wire  isAluImm = _isAluImm_T_3 | d_io_andi | d_io_slli | d_io_srli | d_io_srai; // @[Decode.scala 100:66]
+  wire  _isAluReg_T_4 = d_io_add | d_io_sub | d_io_slt | d_io_sltu | d_io_xor | d_io_or; // @[Decode.scala 102:76]
+  wire  isAluReg = _isAluReg_T_4 | d_io_and | d_io_sll | d_io_srl | d_io_sra; // @[Decode.scala 103:62]
+  wire  isAlu1Bit = d_io_clz | d_io_ctz | d_io_pcnt; // @[Decode.scala 105:40]
+  wire  isAlu2Bit = d_io_min | d_io_minu | d_io_max | d_io_maxu; // @[Decode.scala 106:53]
+  wire  _isCondBr_T_3 = d_io_beq | d_io_bne | d_io_blt | d_io_bge | d_io_bltu; // @[Decode.scala 108:63]
+  wire  isCondBr = _isCondBr_T_3 | d_io_bgeu; // @[Decode.scala 109:28]
+  wire  isLoad = d_io_lb | d_io_lh | d_io_lw | d_io_lbu | d_io_lhu; // @[Decode.scala 115:58]
+  wire  isStore = d_io_sb | d_io_sh | d_io_sw; // @[Decode.scala 116:36]
+  wire  isLsu = isLoad | isStore | d_io_vld | d_io_vst; // @[Decode.scala 117:45]
   wire  isMul = d_io_mul | d_io_mulh | d_io_mulhsu | d_io_mulhu | d_io_mulhr | d_io_mulhsur | d_io_mulhur | d_io_dmulh
-     | d_io_dmulhr; // @[Decode.scala 123:125]
-  wire  fpuRs2 = d_io_vfop & io_inst_inst[1]; // @[Decode.scala 129:255]
-  wire  isVFop = io_vinst_op[5]; // @[Decode.scala 133:27]
-  wire  isVIop = io_vinst_op[4]; // @[Decode.scala 134:27]
-  wire  isVIopVs2 = isVIop & io_inst_inst[1:0] == 2'h0; // @[Decode.scala 137:26]
-  wire [31:0] _aluRdEn_T = io_scoreboard_comb >> rdAddr; // @[Decode.scala 141:37]
-  wire  aluRdEn = ~_aluRdEn_T[0] | isVIop | isStore | isCondBr | fpuRs2; // @[Decode.scala 141:83]
-  wire [31:0] _aluRs1En_T = io_scoreboard_comb >> io_inst_inst[19:15]; // @[Decode.scala 142:37]
-  wire  aluRs1En = ~_aluRs1En_T[0] | isVIop | isLsu | d_io_auipc | isVFop | fpuRs2; // @[Decode.scala 142:93]
-  wire [31:0] _aluRs2En_T = io_scoreboard_comb >> rs2Addr; // @[Decode.scala 143:37]
-  wire  aluRs2En = ~_aluRs2En_T[0] | isVIopVs2 | isLsu | d_io_auipc | isVFop | isAluImm | isAlu1Bit | fpuRs2; // @[Decode.scala 143:118]
-  wire  aluEn = aluRdEn & aluRs1En & aluRs2En; // @[Decode.scala 146:35]
-  wire [31:0] _bruEn_T_1 = io_scoreboard_regd >> io_inst_inst[19:15]; // @[Decode.scala 149:48]
-  wire  _bruEn_T_6 = io_inst_inst[31:20] == 12'h0; // @[Decode.scala 150:35]
-  wire  bruEn = ~d_io_jalr | ~_bruEn_T_1[0] | _bruEn_T_6; // @[Decode.scala 149:58]
-  wire  _lsuEn_T = ~isLsu; // @[Decode.scala 153:15]
-  wire  _lsuEn_T_5 = _lsuEn_T | ~io_serializeIn_brcond; // @[Decode.scala 155:23]
-  wire  _lsuEn_T_6 = io_lsu_ready & _lsuEn_T_5; // @[Decode.scala 154:51]
-  wire  _lsuEn_T_11 = io_busRead_bypass ? _aluRs1En_T[0] : _bruEn_T_1[0]; // @[Decode.scala 156:20]
-  wire  _lsuEn_T_15 = _aluRs2En_T[0] & (isStore | vldst); // @[Decode.scala 158:49]
-  wire  _lsuEn_T_16 = _lsuEn_T_11 | _lsuEn_T_15; // @[Decode.scala 157:50]
-  wire  _lsuEn_T_17 = ~_lsuEn_T_16; // @[Decode.scala 156:15]
-  wire  _lsuEn_T_18 = _lsuEn_T_6 & _lsuEn_T_17; // @[Decode.scala 155:50]
-  wire  lsuEn = ~isLsu | _lsuEn_T_18; // @[Decode.scala 153:22]
-  wire  mulEn = ~isMul | ~io_serializeIn_mul; // @[Decode.scala 161:22]
-  wire [31:0] _fpuEn_T_8 = io_fscoreboard >> rs2Addr; // @[Decode.scala 166:53]
-  wire  _fpuEn_T_10 = fpuRs2 & _fpuEn_T_8[0]; // @[Decode.scala 166:36]
-  wire  fpuEn = ~fpuRs2 | ~_fpuEn_T_10; // @[Decode.scala 164:24]
-  wire  _vinstEn_T_5 = ~(isVFop & io_serializeIn_brcond); // @[Decode.scala 173:17]
-  wire  _vinstEn_T_6 = ~(isVIop & io_serializeIn_brcond) & _vinstEn_T_5; // @[Decode.scala 172:76]
-  wire  _vinstEn_T_10 = ~(io_vinst_op != 6'h0 & ~io_vinst_ready); // @[Decode.scala 174:17]
-  wire  vinstEn = _vinstEn_T_6 & _vinstEn_T_10; // @[Decode.scala 173:76]
-  wire  aluValid_value__9 = io_alu_op[18]; // @[Library.scala 182:26]
+     | d_io_dmulhr; // @[Decode.scala 119:125]
+  wire  isVIop = io_vinst_op[4]; // @[Decode.scala 123:27]
+  wire  isVIopVs2 = isVIop & io_inst_inst[1:0] == 2'h0; // @[Decode.scala 126:26]
+  wire [31:0] _aluRdEn_T = io_scoreboard_comb >> rdAddr; // @[Decode.scala 130:37]
+  wire  aluRdEn = ~_aluRdEn_T[0] | isVIop | isStore | isCondBr; // @[Decode.scala 130:71]
+  wire [31:0] _aluRs1En_T = io_scoreboard_comb >> io_inst_inst[19:15]; // @[Decode.scala 131:37]
+  wire  aluRs1En = ~_aluRs1En_T[0] | isVIop | isLsu | d_io_auipc; // @[Decode.scala 131:69]
+  wire [31:0] _aluRs2En_T = io_scoreboard_comb >> rs2Addr; // @[Decode.scala 132:37]
+  wire  aluRs2En = ~_aluRs2En_T[0] | isVIopVs2 | isLsu | d_io_auipc | isAluImm | isAlu1Bit; // @[Decode.scala 132:95]
+  wire  aluEn = aluRdEn & aluRs1En & aluRs2En; // @[Decode.scala 135:35]
+  wire [31:0] _bruEn_T_1 = io_scoreboard_regd >> io_inst_inst[19:15]; // @[Decode.scala 138:48]
+  wire  _bruEn_T_6 = io_inst_inst[31:20] == 12'h0; // @[Decode.scala 139:35]
+  wire  bruEn = ~d_io_jalr | ~_bruEn_T_1[0] | _bruEn_T_6; // @[Decode.scala 138:58]
+  wire  _lsuEn_T = ~isLsu; // @[Decode.scala 142:15]
+  wire  _lsuEn_T_5 = _lsuEn_T | ~io_serializeIn_brcond; // @[Decode.scala 144:23]
+  wire  _lsuEn_T_6 = io_lsu_ready & _lsuEn_T_5; // @[Decode.scala 143:51]
+  wire  _lsuEn_T_11 = io_busRead_bypass ? _aluRs1En_T[0] : _bruEn_T_1[0]; // @[Decode.scala 145:20]
+  wire  _lsuEn_T_15 = _aluRs2En_T[0] & (isStore | vldst); // @[Decode.scala 147:49]
+  wire  _lsuEn_T_16 = _lsuEn_T_11 | _lsuEn_T_15; // @[Decode.scala 146:50]
+  wire  _lsuEn_T_17 = ~_lsuEn_T_16; // @[Decode.scala 145:15]
+  wire  _lsuEn_T_18 = _lsuEn_T_6 & _lsuEn_T_17; // @[Decode.scala 144:50]
+  wire  lsuEn = ~isLsu | _lsuEn_T_18; // @[Decode.scala 142:22]
+  wire  mulEn = ~isMul | ~io_serializeIn_mul; // @[Decode.scala 150:22]
+  wire  _vinstEn_T_6 = ~(io_vinst_op != 5'h0 & ~io_vinst_ready); // @[Decode.scala 155:17]
+  wire  vinstEn = ~(isVIop & io_serializeIn_brcond) & _vinstEn_T_6; // @[Decode.scala 154:76]
   wire  aluValid_value__0 = io_alu_op[0] | io_alu_op[1]; // @[Library.scala 194:39]
   wire  aluValid_value__1 = io_alu_op[2] | io_alu_op[3]; // @[Library.scala 194:39]
   wire  aluValid_value__2 = io_alu_op[4] | io_alu_op[5]; // @[Library.scala 194:39]
@@ -10504,32 +9852,30 @@
   wire  aluValid_value_1_1 = aluValid_value__2 | aluValid_value__3; // @[Library.scala 194:39]
   wire  aluValid_value_1_2 = aluValid_value__4 | aluValid_value__5; // @[Library.scala 194:39]
   wire  aluValid_value_1_3 = aluValid_value__6 | aluValid_value__7; // @[Library.scala 194:39]
-  wire  aluValid_value_1_4 = aluValid_value__8 | aluValid_value__9; // @[Library.scala 194:39]
   wire  aluValid_value_2_0 = aluValid_value_1_0 | aluValid_value_1_1; // @[Library.scala 194:39]
   wire  aluValid_value_2_1 = aluValid_value_1_2 | aluValid_value_1_3; // @[Library.scala 194:39]
   wire  aluValid_value_3_0 = aluValid_value_2_0 | aluValid_value_2_1; // @[Library.scala 194:39]
-  wire  aluValid_value_4_0 = aluValid_value_3_0 | aluValid_value_1_4; // @[Library.scala 194:39]
-  wire  aluOp_1 = d_io_sub; // @[Decode.scala 182:19 189:19]
-  wire  aluOp_0 = d_io_auipc | d_io_addi | d_io_add; // @[Decode.scala 188:46]
-  wire  aluOp_3 = d_io_sltiu | d_io_sltu; // @[Decode.scala 191:33]
-  wire  aluOp_2 = d_io_slti | d_io_slt; // @[Decode.scala 190:32]
-  wire  aluOp_5 = d_io_ori | d_io_or; // @[Decode.scala 193:31]
-  wire  aluOp_4 = d_io_xori | d_io_xor; // @[Decode.scala 192:32]
-  wire  aluOp_8 = d_io_srli | d_io_srl; // @[Decode.scala 196:32]
-  wire  aluOp_7 = d_io_slli | d_io_sll; // @[Decode.scala 195:32]
-  wire  aluOp_6 = d_io_andi | d_io_and; // @[Decode.scala 194:32]
-  wire [8:0] io_alu_op_lo = {aluOp_8,aluOp_7,aluOp_6,aluOp_5,aluOp_4,aluOp_3,aluOp_2,aluOp_1,aluOp_0}; // @[Decode.scala 186:22]
-  wire  aluOp_10 = d_io_lui; // @[Decode.scala 182:19 198:19]
-  wire  aluOp_9 = d_io_srai | d_io_sra; // @[Decode.scala 197:32]
-  wire  aluOp_13 = d_io_ctz; // @[Decode.scala 182:19 201:19]
-  wire  aluOp_12 = d_io_clz; // @[Decode.scala 182:19 200:19]
-  wire  aluOp_11 = d_io_clb; // @[Decode.scala 182:19 199:19]
-  wire  aluOp_15 = d_io_min; // @[Decode.scala 182:19 203:19]
-  wire  aluOp_14 = d_io_pcnt; // @[Decode.scala 182:19 202:19]
-  wire  aluOp_18 = d_io_maxu; // @[Decode.scala 182:19 206:19]
-  wire  aluOp_17 = d_io_max; // @[Decode.scala 182:19 205:19]
-  wire  aluOp_16 = d_io_minu; // @[Decode.scala 182:19 204:19]
-  wire [9:0] io_alu_op_hi = {aluOp_18,aluOp_17,aluOp_16,aluOp_15,aluOp_14,aluOp_13,aluOp_12,aluOp_11,aluOp_10,aluOp_9}; // @[Decode.scala 186:22]
+  wire  aluValid_value_4_0 = aluValid_value_3_0 | aluValid_value__8; // @[Library.scala 194:39]
+  wire  aluOp_1 = d_io_sub; // @[Decode.scala 163:19 170:19]
+  wire  aluOp_0 = d_io_auipc | d_io_addi | d_io_add; // @[Decode.scala 169:46]
+  wire  aluOp_3 = d_io_sltiu | d_io_sltu; // @[Decode.scala 172:33]
+  wire  aluOp_2 = d_io_slti | d_io_slt; // @[Decode.scala 171:32]
+  wire  aluOp_5 = d_io_ori | d_io_or; // @[Decode.scala 174:31]
+  wire  aluOp_4 = d_io_xori | d_io_xor; // @[Decode.scala 173:32]
+  wire  aluOp_8 = d_io_srli | d_io_srl; // @[Decode.scala 177:32]
+  wire  aluOp_7 = d_io_slli | d_io_sll; // @[Decode.scala 176:32]
+  wire  aluOp_6 = d_io_andi | d_io_and; // @[Decode.scala 175:32]
+  wire [8:0] io_alu_op_lo = {aluOp_8,aluOp_7,aluOp_6,aluOp_5,aluOp_4,aluOp_3,aluOp_2,aluOp_1,aluOp_0}; // @[Decode.scala 167:22]
+  wire  aluOp_10 = d_io_lui; // @[Decode.scala 163:19 179:19]
+  wire  aluOp_9 = d_io_srai | d_io_sra; // @[Decode.scala 178:32]
+  wire  aluOp_12 = d_io_ctz; // @[Decode.scala 163:19 181:19]
+  wire  aluOp_11 = d_io_clz; // @[Decode.scala 163:19 180:19]
+  wire  aluOp_14 = d_io_min; // @[Decode.scala 163:19 183:19]
+  wire  aluOp_13 = d_io_pcnt; // @[Decode.scala 163:19 182:19]
+  wire  aluOp_17 = d_io_maxu; // @[Decode.scala 163:19 186:19]
+  wire  aluOp_16 = d_io_max; // @[Decode.scala 163:19 185:19]
+  wire  aluOp_15 = d_io_minu; // @[Decode.scala 163:19 184:19]
+  wire [8:0] io_alu_op_hi = {aluOp_17,aluOp_16,aluOp_15,aluOp_14,aluOp_13,aluOp_12,aluOp_11,aluOp_10,aluOp_9}; // @[Decode.scala 167:22]
   wire  bruValid_value__8 = io_bru_op[16]; // @[Library.scala 182:26]
   wire  bruValid_value__0 = io_bru_op[0] | io_bru_op[1]; // @[Library.scala 194:39]
   wire  bruValid_value__1 = io_bru_op[2] | io_bru_op[3]; // @[Library.scala 194:39]
@@ -10547,18 +9893,18 @@
   wire  bruValid_value_2_1 = bruValid_value_1_2 | bruValid_value_1_3; // @[Library.scala 194:39]
   wire  bruValid_value_3_0 = bruValid_value_2_0 | bruValid_value_2_1; // @[Library.scala 194:39]
   wire  bruValid_value_4_0 = bruValid_value_3_0 | bruValid_value__8; // @[Library.scala 194:39]
-  wire  bruOp_1 = d_io_jalr; // @[Decode.scala 210:19 220:19]
-  wire  bruOp_0 = d_io_jal; // @[Decode.scala 210:19 219:19]
-  wire  bruOp_3 = d_io_bne; // @[Decode.scala 210:19 222:19]
-  wire  bruOp_2 = d_io_beq; // @[Decode.scala 210:19 221:19]
-  wire  bruOp_5 = d_io_bge; // @[Decode.scala 210:19 224:19]
-  wire  bruOp_4 = d_io_blt; // @[Decode.scala 210:19 223:19]
-  wire  bruOp_7 = d_io_bgeu; // @[Decode.scala 210:19 226:19]
-  wire  bruOp_6 = d_io_bltu; // @[Decode.scala 210:19 225:19]
-  wire [7:0] io_bru_op_lo = {bruOp_7,bruOp_6,bruOp_5,bruOp_4,bruOp_3,bruOp_2,bruOp_1,bruOp_0}; // @[Decode.scala 214:22]
-  wire  bruOp_16 = d_io_undef; // @[Decode.scala 210:19 235:21]
-  wire [8:0] io_bru_op_hi = {bruOp_16,1'h0,1'h0,2'h0,4'h0}; // @[Decode.scala 214:22]
-  wire [31:0] _io_bru_target_T_1 = io_inst_inst[2] ? d_io_immjal : d_io_immbr; // @[Decode.scala 216:38]
+  wire  bruOp_1 = d_io_jalr; // @[Decode.scala 190:19 200:19]
+  wire  bruOp_0 = d_io_jal; // @[Decode.scala 190:19 199:19]
+  wire  bruOp_3 = d_io_bne; // @[Decode.scala 190:19 202:19]
+  wire  bruOp_2 = d_io_beq; // @[Decode.scala 190:19 201:19]
+  wire  bruOp_5 = d_io_bge; // @[Decode.scala 190:19 204:19]
+  wire  bruOp_4 = d_io_blt; // @[Decode.scala 190:19 203:19]
+  wire  bruOp_7 = d_io_bgeu; // @[Decode.scala 190:19 206:19]
+  wire  bruOp_6 = d_io_bltu; // @[Decode.scala 190:19 205:19]
+  wire [7:0] io_bru_op_lo = {bruOp_7,bruOp_6,bruOp_5,bruOp_4,bruOp_3,bruOp_2,bruOp_1,bruOp_0}; // @[Decode.scala 194:22]
+  wire  bruOp_16 = d_io_undef; // @[Decode.scala 190:19 215:21]
+  wire [8:0] io_bru_op_hi = {bruOp_16,1'h0,1'h0,2'h0,4'h0}; // @[Decode.scala 194:22]
+  wire [31:0] _io_bru_target_T_1 = io_inst_inst[2] ? d_io_immjal : d_io_immbr; // @[Decode.scala 196:38]
   wire  csrValid_value__1 = io_csr_op[2]; // @[Library.scala 182:26]
   wire  csrValid_value__0 = io_csr_op[0] | io_csr_op[1]; // @[Library.scala 194:39]
   wire  csrValid_value_1_0 = csrValid_value__0 | csrValid_value__1; // @[Library.scala 194:39]
@@ -10568,23 +9914,21 @@
   wire  lsuValid_value__3 = io_lsu_op[6] | io_lsu_op[7]; // @[Library.scala 194:39]
   wire  lsuValid_value__4 = io_lsu_op[8] | io_lsu_op[9]; // @[Library.scala 194:39]
   wire  lsuValid_value__5 = io_lsu_op[10] | io_lsu_op[11]; // @[Library.scala 194:39]
-  wire  lsuValid_value__6 = io_lsu_op[12] | io_lsu_op[13]; // @[Library.scala 194:39]
   wire  lsuValid_value_1_0 = lsuValid_value__0 | lsuValid_value__1; // @[Library.scala 194:39]
   wire  lsuValid_value_1_1 = lsuValid_value__2 | lsuValid_value__3; // @[Library.scala 194:39]
   wire  lsuValid_value_1_2 = lsuValid_value__4 | lsuValid_value__5; // @[Library.scala 194:39]
   wire  lsuValid_value_2_0 = lsuValid_value_1_0 | lsuValid_value_1_1; // @[Library.scala 194:39]
-  wire  lsuValid_value_2_1 = lsuValid_value_1_2 | lsuValid_value__6; // @[Library.scala 194:39]
-  wire  lsuValid_value_3_0 = lsuValid_value_2_0 | lsuValid_value_2_1; // @[Library.scala 194:39]
-  wire  lsuOp_2 = d_io_lw; // @[Decode.scala 252:19 261:18]
-  wire  lsuOp_1 = d_io_lh; // @[Decode.scala 252:19 260:18]
-  wire  lsuOp_0 = d_io_lb; // @[Decode.scala 252:19 259:18]
-  wire  lsuOp_4 = d_io_lhu; // @[Decode.scala 252:19 263:18]
-  wire  lsuOp_3 = d_io_lbu; // @[Decode.scala 252:19 262:18]
-  wire  lsuOp_6 = d_io_sh; // @[Decode.scala 252:19 265:18]
-  wire  lsuOp_5 = d_io_sb; // @[Decode.scala 252:19 264:18]
-  wire [6:0] io_lsu_op_lo = {lsuOp_6,lsuOp_5,lsuOp_4,lsuOp_3,lsuOp_2,lsuOp_1,lsuOp_0}; // @[Decode.scala 257:22]
-  wire  lsuOp_7 = d_io_sw; // @[Decode.scala 252:19 266:18]
-  wire [6:0] io_lsu_op_hi = {vldst,1'h0,2'h0,2'h0,lsuOp_7}; // @[Decode.scala 257:22]
+  wire  lsuValid_value_3_0 = lsuValid_value_2_0 | lsuValid_value_1_2; // @[Library.scala 194:39]
+  wire  lsuOp_2 = d_io_lw; // @[Decode.scala 232:19 241:18]
+  wire  lsuOp_1 = d_io_lh; // @[Decode.scala 232:19 240:18]
+  wire  lsuOp_0 = d_io_lb; // @[Decode.scala 232:19 239:18]
+  wire  lsuOp_5 = d_io_sb; // @[Decode.scala 232:19 244:18]
+  wire  lsuOp_4 = d_io_lhu; // @[Decode.scala 232:19 243:18]
+  wire  lsuOp_3 = d_io_lbu; // @[Decode.scala 232:19 242:18]
+  wire [5:0] io_lsu_op_lo = {lsuOp_5,lsuOp_4,lsuOp_3,lsuOp_2,lsuOp_1,lsuOp_0}; // @[Decode.scala 237:22]
+  wire  lsuOp_7 = d_io_sw; // @[Decode.scala 232:19 246:18]
+  wire  lsuOp_6 = d_io_sh; // @[Decode.scala 232:19 245:18]
+  wire [5:0] io_lsu_op_hi = {vldst,1'h0,1'h0,1'h0,lsuOp_7,lsuOp_6}; // @[Decode.scala 237:22]
   wire  mluValid_value__4 = io_mlu_op[8]; // @[Library.scala 182:26]
   wire  mluValid_value__0 = io_mlu_op[0] | io_mlu_op[1]; // @[Library.scala 194:39]
   wire  mluValid_value__1 = io_mlu_op[2] | io_mlu_op[3]; // @[Library.scala 194:39]
@@ -10594,60 +9938,56 @@
   wire  mluValid_value_1_1 = mluValid_value__2 | mluValid_value__3; // @[Library.scala 194:39]
   wire  mluValid_value_2_0 = mluValid_value_1_0 | mluValid_value_1_1; // @[Library.scala 194:39]
   wire  mluValid_value_3_0 = mluValid_value_2_0 | mluValid_value__4; // @[Library.scala 194:39]
-  wire  mluOp_1 = d_io_mulh; // @[Decode.scala 276:19 283:22]
-  wire  mluOp_0 = d_io_mul; // @[Decode.scala 276:19 282:22]
-  wire  mluOp_3 = d_io_mulhu; // @[Decode.scala 276:19 285:22]
-  wire  mluOp_2 = d_io_mulhsu; // @[Decode.scala 276:19 284:22]
-  wire [3:0] io_mlu_op_lo = {mluOp_3,mluOp_2,mluOp_1,mluOp_0}; // @[Decode.scala 280:22]
-  wire  mluOp_5 = d_io_mulhsur; // @[Decode.scala 276:19 287:22]
-  wire  mluOp_4 = d_io_mulhr; // @[Decode.scala 276:19 286:22]
-  wire  mluOp_8 = d_io_dmulhr; // @[Decode.scala 276:19 290:22]
-  wire  mluOp_7 = d_io_dmulh; // @[Decode.scala 276:19 289:22]
-  wire  mluOp_6 = d_io_mulhur; // @[Decode.scala 276:19 288:22]
-  wire [4:0] io_mlu_op_hi = {mluOp_8,mluOp_7,mluOp_6,mluOp_5,mluOp_4}; // @[Decode.scala 280:22]
+  wire  mluOp_1 = d_io_mulh; // @[Decode.scala 255:19 262:22]
+  wire  mluOp_0 = d_io_mul; // @[Decode.scala 255:19 261:22]
+  wire  mluOp_3 = d_io_mulhu; // @[Decode.scala 255:19 264:22]
+  wire  mluOp_2 = d_io_mulhsu; // @[Decode.scala 255:19 263:22]
+  wire [3:0] io_mlu_op_lo = {mluOp_3,mluOp_2,mluOp_1,mluOp_0}; // @[Decode.scala 259:22]
+  wire  mluOp_5 = d_io_mulhsur; // @[Decode.scala 255:19 266:22]
+  wire  mluOp_4 = d_io_mulhr; // @[Decode.scala 255:19 265:22]
+  wire  mluOp_8 = d_io_dmulhr; // @[Decode.scala 255:19 269:22]
+  wire  mluOp_7 = d_io_dmulh; // @[Decode.scala 255:19 268:22]
+  wire  mluOp_6 = d_io_mulhur; // @[Decode.scala 255:19 267:22]
+  wire [4:0] io_mlu_op_hi = {mluOp_8,mluOp_7,mluOp_6,mluOp_5,mluOp_4}; // @[Decode.scala 259:22]
   wire  dvuValid_value__0 = io_dvu_op[0] | io_dvu_op[1]; // @[Library.scala 194:39]
   wire  dvuValid_value__1 = io_dvu_op[2] | io_dvu_op[3]; // @[Library.scala 194:39]
   wire  dvuValid_value_1_0 = dvuValid_value__0 | dvuValid_value__1; // @[Library.scala 194:39]
-  wire  dvuEn = ~dvuValid_value_1_0; // @[Decode.scala 305:34]
-  wire [13:0] io_fpu_op_hi = {fpuRs2,1'h0,2'h0,3'h0,7'h0}; // @[Decode.scala 313:22]
-  wire  vinstOp_0 = d_io_getvl; // @[Decode.scala 349:21 361:24]
-  wire  vinstOp_1 = d_io_getmaxvl; // @[Decode.scala 349:21 362:27]
+  wire  dvuEn = ~dvuValid_value_1_0; // @[Decode.scala 284:34]
+  wire  vinstOp_0 = d_io_getvl; // @[Decode.scala 288:21 299:24]
+  wire  vinstOp_1 = d_io_getmaxvl; // @[Decode.scala 288:21 300:27]
   wire  vinstValid_value__0 = vinstOp_0 | vinstOp_1; // @[Library.scala 194:39]
-  wire  vinstOp_2 = d_io_vld; // @[Decode.scala 349:21 357:22]
-  wire  vinstOp_3 = d_io_vst; // @[Decode.scala 349:21 358:22]
+  wire  vinstOp_2 = d_io_vld; // @[Decode.scala 288:21 296:22]
+  wire  vinstOp_3 = d_io_vst; // @[Decode.scala 288:21 297:22]
   wire  vinstValid_value__1 = vinstOp_2 | vinstOp_3; // @[Library.scala 194:39]
-  wire  vinstOp_4 = d_io_viop; // @[Decode.scala 349:21 359:23]
-  wire  vinstOp_5 = d_io_vfop; // @[Decode.scala 349:21 360:23]
-  wire  vinstValid_value__2 = vinstOp_4 | vinstOp_5; // @[Library.scala 194:39]
   wire  vinstValid_value_1_0 = vinstValid_value__0 | vinstValid_value__1; // @[Library.scala 194:39]
-  wire  vinstValid_value_2_0 = vinstValid_value_1_0 | vinstValid_value__2; // @[Library.scala 194:39]
-  wire [2:0] io_vinst_op_lo = {vinstOp_2,vinstOp_1,vinstOp_0}; // @[Decode.scala 355:26]
-  wire [2:0] io_vinst_op_hi = {vinstOp_5,vinstOp_4,vinstOp_3}; // @[Decode.scala 355:26]
-  wire  _io_rs1Read_valid_T = isCondBr | isAluReg; // @[Decode.scala 368:45]
-  wire  _io_rs1Read_valid_T_3 = isCondBr | isAluReg | isAluImm | isAlu1Bit | isAlu2Bit; // @[Decode.scala 368:82]
-  wire  _io_rs1Read_valid_T_6 = _io_rs1Read_valid_T_3 | isMul; // @[Decode.scala 369:44]
-  wire  _io_rs1Read_valid_T_13 = _io_rs1Read_valid_T_6 | d_io_getvl | d_io_vld; // @[Decode.scala 370:79]
-  wire  _io_rs1Read_valid_T_14 = _io_rs1Read_valid_T_13 | d_io_vst; // @[Decode.scala 371:32]
-  wire  _io_rs2Read_valid_T_2 = _io_rs1Read_valid_T | isAlu2Bit | isStore; // @[Decode.scala 372:70]
-  wire  _io_rs2Read_valid_T_8 = _io_rs2Read_valid_T_2 | isMul | d_io_getvl | d_io_vld; // @[Decode.scala 373:77]
-  wire  _io_rs2Read_valid_T_10 = _io_rs2Read_valid_T_8 | d_io_vst | d_io_viop; // @[Decode.scala 374:44]
-  wire  _io_rs2Set_value_T = d_io_auipc | d_io_lui; // @[Decode.scala 389:45]
-  wire  _rdMark_valid_T_4 = lsuValid_value_3_0 & isLoad; // @[Decode.scala 395:16]
-  wire  _rdMark_valid_T_5 = aluValid_value_4_0 | csrValid_value_1_0 | mluValid_value_3_0 | _rdMark_valid_T_4; // @[Decode.scala 394:68]
-  wire  _rdMark_valid_T_13 = _rdMark_valid_T_5 | d_io_getvl; // @[Decode.scala 396:55]
-  wire  _rdMark_valid_T_19 = bruValid_value_4_0 & (bruOp_0 | bruOp_1) & rdAddr != 5'h0; // @[Decode.scala 398:55]
-  wire  rdMark_valid = _rdMark_valid_T_13 | d_io_getmaxvl | vldst_wb | _rdMark_valid_T_19; // @[Decode.scala 397:47]
+  wire  vinstOp_4 = d_io_viop; // @[Decode.scala 288:21 298:23]
+  wire  vinstValid_value_2_0 = vinstValid_value_1_0 | vinstOp_4; // @[Library.scala 194:39]
+  wire [1:0] io_vinst_op_lo = {vinstOp_1,vinstOp_0}; // @[Decode.scala 294:26]
+  wire [2:0] io_vinst_op_hi = {vinstOp_4,vinstOp_3,vinstOp_2}; // @[Decode.scala 294:26]
+  wire  _io_rs1Read_valid_T = isCondBr | isAluReg; // @[Decode.scala 306:45]
+  wire  _io_rs1Read_valid_T_3 = isCondBr | isAluReg | isAluImm | isAlu1Bit | isAlu2Bit; // @[Decode.scala 306:82]
+  wire  _io_rs1Read_valid_T_9 = _io_rs1Read_valid_T_3 | isMul | d_io_getvl; // @[Decode.scala 307:75]
+  wire  _io_rs1Read_valid_T_11 = _io_rs1Read_valid_T_9 | d_io_vld | d_io_vst; // @[Decode.scala 308:46]
+  wire  _io_rs2Read_valid_T_2 = _io_rs1Read_valid_T | isAlu2Bit | isStore; // @[Decode.scala 309:70]
+  wire  _io_rs2Read_valid_T_8 = _io_rs2Read_valid_T_2 | isMul | d_io_getvl | d_io_vld; // @[Decode.scala 310:77]
+  wire  _io_rs2Read_valid_T_10 = _io_rs2Read_valid_T_8 | d_io_vst | d_io_viop; // @[Decode.scala 311:44]
+  wire  _io_rs2Set_value_T = d_io_auipc | d_io_lui; // @[Decode.scala 326:45]
+  wire  _rdMark_valid_T_4 = lsuValid_value_3_0 & isLoad; // @[Decode.scala 332:16]
+  wire  _rdMark_valid_T_5 = aluValid_value_4_0 | csrValid_value_1_0 | mluValid_value_3_0 | _rdMark_valid_T_4; // @[Decode.scala 331:68]
+  wire  _rdMark_valid_T_6 = _rdMark_valid_T_5 | d_io_getvl; // @[Decode.scala 332:26]
+  wire  _rdMark_valid_T_12 = bruValid_value_4_0 & (bruOp_0 | bruOp_1) & rdAddr != 5'h0; // @[Decode.scala 334:55]
+  wire  rdMark_valid = _rdMark_valid_T_6 | d_io_getmaxvl | vldst_wb | _rdMark_valid_T_12; // @[Decode.scala 333:47]
   wire [31:0] _scoreboard_spec_T = 32'h1 << rdAddr; // @[OneHot.scala 64:12]
-  wire [31:0] scoreboard_spec = rdMark_valid ? _scoreboard_spec_T : 32'h0; // @[Decode.scala 401:28]
-  wire  _io_busRead_bypass_T_9 = io_inst_inst[11:7] == 5'h0; // @[Decode.scala 413:65]
-  wire  _io_busRead_bypass_T_10 = ~io_inst_inst[5] | io_inst_inst[6] ? rs2Addr == 5'h0 : _io_busRead_bypass_T_9; // @[Decode.scala 412:8]
-  wire  storeSelect = io_inst_inst[6:3] == 4'h4 & io_inst_inst[1:0] == 2'h3; // @[Decode.scala 417:47]
-  wire [4:0] _io_busRead_immed_T_3 = storeSelect ? d_io_immst[4:0] : d_io_imm12[4:0]; // @[Decode.scala 420:30]
-  wire  _io_inst_ready_T_7 = ~io_serializeIn_jump; // @[Decode.scala 426:20]
-  wire  _io_inst_ready_T_8 = aluEn & bruEn & lsuEn & mulEn & dvuEn & fpuEn & vinstEn & _io_inst_ready_T_7; // @[Decode.scala 425:93]
-  wire  _io_inst_ready_T_14 = ~d_io_undef; // @[Decode.scala 427:43]
-  wire  _io_serializeOut_brcond_T = io_serializeIn_brcond | d_io_beq; // @[Decode.scala 437:51]
-  DecodedInstruction_1 d ( // @[Decode.scala 91:17]
+  wire [31:0] scoreboard_spec = rdMark_valid ? _scoreboard_spec_T : 32'h0; // @[Decode.scala 337:28]
+  wire  _io_busRead_bypass_T_9 = io_inst_inst[11:7] == 5'h0; // @[Decode.scala 349:65]
+  wire  _io_busRead_bypass_T_10 = ~io_inst_inst[5] | io_inst_inst[6] ? rs2Addr == 5'h0 : _io_busRead_bypass_T_9; // @[Decode.scala 348:8]
+  wire  storeSelect = io_inst_inst[6:3] == 4'h4 & io_inst_inst[1:0] == 2'h3; // @[Decode.scala 353:47]
+  wire [4:0] _io_busRead_immed_T_3 = storeSelect ? d_io_immst[4:0] : d_io_imm12[4:0]; // @[Decode.scala 356:30]
+  wire  _io_inst_ready_T_6 = ~io_serializeIn_jump; // @[Decode.scala 362:20]
+  wire  _io_inst_ready_T_7 = aluEn & bruEn & lsuEn & mulEn & dvuEn & vinstEn & _io_inst_ready_T_6; // @[Decode.scala 361:84]
+  wire  _io_inst_ready_T_13 = ~d_io_undef; // @[Decode.scala 363:43]
+  wire  _io_serializeOut_brcond_T = io_serializeIn_brcond | d_io_beq; // @[Decode.scala 373:51]
+  DecodedInstruction_1 d ( // @[Decode.scala 87:17]
     .clock(d_clock),
     .reset(d_reset),
     .io_addr(d_io_addr),
@@ -10711,33 +10051,6 @@
     .io_divu(d_io_divu),
     .io_rem(d_io_rem),
     .io_remu(d_io_remu),
-    .io_flw(d_io_flw),
-    .io_fsw(d_io_fsw),
-    .io_fmadd(d_io_fmadd),
-    .io_fmsub(d_io_fmsub),
-    .io_fnmsub(d_io_fnmsub),
-    .io_fnmadd(d_io_fnmadd),
-    .io_fadd(d_io_fadd),
-    .io_fsub(d_io_fsub),
-    .io_fmul(d_io_fmul),
-    .io_fdiv(d_io_fdiv),
-    .io_fsqrt(d_io_fsqrt),
-    .io_fsgnj(d_io_fsgnj),
-    .io_fsgnjn(d_io_fsgnjn),
-    .io_fsgnjx(d_io_fsgnjx),
-    .io_fmin(d_io_fmin),
-    .io_fmax(d_io_fmax),
-    .io_fcvtws(d_io_fcvtws),
-    .io_fcvtwus(d_io_fcvtwus),
-    .io_fmvxw(d_io_fmvxw),
-    .io_feq(d_io_feq),
-    .io_flt(d_io_flt),
-    .io_fle(d_io_fle),
-    .io_fclass(d_io_fclass),
-    .io_fcvtsw(d_io_fcvtsw),
-    .io_fcvtswu(d_io_fcvtswu),
-    .io_fmvwx(d_io_fmvwx),
-    .io_clb(d_io_clb),
     .io_clz(d_io_clz),
     .io_ctz(d_io_ctz),
     .io_pcnt(d_io_pcnt),
@@ -10750,7 +10063,6 @@
     .io_vld(d_io_vld),
     .io_vst(d_io_vst),
     .io_viop(d_io_viop),
-    .io_vfop(d_io_vfop),
     .io_ebreak(d_io_ebreak),
     .io_ecall(d_io_ecall),
     .io_eexit(d_io_eexit),
@@ -10764,50 +10076,48 @@
     .io_flushall(d_io_flushall),
     .io_slog(d_io_slog)
   );
-  assign io_inst_ready = _io_inst_ready_T_8 & ~io_halted & ~io_interlock & _io_inst_ready_T_14; // @[Decode.scala 426:72]
+  assign io_inst_ready = _io_inst_ready_T_7 & ~io_halted & ~io_interlock & _io_inst_ready_T_13; // @[Decode.scala 362:72]
   assign io_scoreboard_spec = {scoreboard_spec[31:1],1'h0}; // @[Cat.scala 31:58]
-  assign io_rs1Read_valid = decodeEn & _io_rs1Read_valid_T_14; // @[Decode.scala 368:32]
-  assign io_rs1Read_addr = io_inst_inst[0] ? io_inst_inst[19:15] : rs3Addr; // @[Decode.scala 377:25]
-  assign io_rs1Set_valid = decodeEn & d_io_auipc; // @[Decode.scala 383:31]
-  assign io_rs1Set_value = io_inst_addr; // @[Decode.scala 386:25]
-  assign io_rs2Read_valid = decodeEn & _io_rs2Read_valid_T_10; // @[Decode.scala 372:32]
-  assign io_rs2Read_addr = io_inst_inst[24:20]; // @[Decode.scala 100:29]
-  assign io_rs2Set_valid = io_rs1Set_valid | decodeEn & (isAluImm | isAlu1Bit | d_io_lui); // @[Decode.scala 384:38]
+  assign io_rs1Read_valid = decodeEn & _io_rs1Read_valid_T_11; // @[Decode.scala 306:32]
+  assign io_rs1Read_addr = io_inst_inst[0] ? io_inst_inst[19:15] : rs3Addr; // @[Decode.scala 314:25]
+  assign io_rs1Set_valid = decodeEn & d_io_auipc; // @[Decode.scala 320:31]
+  assign io_rs1Set_value = io_inst_addr; // @[Decode.scala 323:25]
+  assign io_rs2Read_valid = decodeEn & _io_rs2Read_valid_T_10; // @[Decode.scala 309:32]
+  assign io_rs2Read_addr = io_inst_inst[24:20]; // @[Decode.scala 96:29]
+  assign io_rs2Set_valid = io_rs1Set_valid | decodeEn & (isAluImm | isAlu1Bit | d_io_lui); // @[Decode.scala 321:38]
   assign io_rs2Set_value = _io_rs2Set_value_T ? d_io_imm20 : d_io_imm12; // @[Mux.scala 101:16]
-  assign io_rdMark_valid = decodeEn & rdMark_valid; // @[Decode.scala 404:31]
-  assign io_rdMark_addr = vldst ? io_inst_inst[19:15] : io_inst_inst[11:7]; // @[Decode.scala 98:20]
-  assign io_busRead_bypass = io_inst_inst[31:25] == 7'h0 & _io_busRead_bypass_T_10; // @[Decode.scala 411:52]
+  assign io_rdMark_valid = decodeEn & rdMark_valid; // @[Decode.scala 340:31]
+  assign io_rdMark_addr = vldst ? io_inst_inst[19:15] : io_inst_inst[11:7]; // @[Decode.scala 94:20]
+  assign io_busRead_bypass = io_inst_inst[31:25] == 7'h0 & _io_busRead_bypass_T_10; // @[Decode.scala 347:52]
   assign io_busRead_immed = {d_io_imm12[31:5],_io_busRead_immed_T_3}; // @[Cat.scala 31:58]
-  assign io_alu_valid = decodeEn & aluValid_value_4_0; // @[Decode.scala 184:28]
-  assign io_alu_addr = vldst ? io_inst_inst[19:15] : io_inst_inst[11:7]; // @[Decode.scala 98:20]
-  assign io_alu_op = {io_alu_op_hi,io_alu_op_lo}; // @[Decode.scala 186:22]
-  assign io_bru_valid = decodeEn & bruValid_value_4_0; // @[Decode.scala 212:28]
-  assign io_bru_fwd = io_inst_brchFwd; // @[Decode.scala 213:14]
-  assign io_bru_op = {io_bru_op_hi,io_bru_op_lo}; // @[Decode.scala 214:22]
-  assign io_bru_pc = io_inst_addr; // @[Decode.scala 215:13]
-  assign io_bru_target = io_inst_addr + _io_bru_target_T_1; // @[Decode.scala 216:33]
-  assign io_bru_link = vldst ? io_inst_inst[19:15] : io_inst_inst[11:7]; // @[Decode.scala 98:20]
-  assign io_csr_op = 3'h0; // @[Decode.scala 244:22]
-  assign io_lsu_valid = decodeEn & lsuValid_value_3_0; // @[Decode.scala 254:28]
-  assign io_lsu_addr = vldst ? io_inst_inst[19:15] : io_inst_inst[11:7]; // @[Decode.scala 98:20]
-  assign io_lsu_op = {io_lsu_op_hi,io_lsu_op_lo}; // @[Decode.scala 257:22]
-  assign io_mlu_valid = decodeEn & mluValid_value_3_0; // @[Decode.scala 278:28]
-  assign io_mlu_addr = vldst ? io_inst_inst[19:15] : io_inst_inst[11:7]; // @[Decode.scala 98:20]
-  assign io_mlu_op = {io_mlu_op_hi,io_mlu_op_lo}; // @[Decode.scala 280:22]
-  assign io_dvu_op = 4'h0; // @[Decode.scala 298:22]
-  assign io_fpu_raddr_1 = io_inst_inst[24:20]; // @[Decode.scala 100:29]
-  assign io_fpu_op = {io_fpu_op_hi,13'h0}; // @[Decode.scala 313:22]
-  assign io_vinst_valid = decodeEn & vinstValid_value_2_0; // @[Decode.scala 352:30]
-  assign io_vinst_addr = vldst ? io_inst_inst[19:15] : io_inst_inst[11:7]; // @[Decode.scala 98:20]
-  assign io_vinst_inst = io_inst_inst; // @[Decode.scala 354:17]
-  assign io_vinst_op = {io_vinst_op_hi,io_vinst_op_lo}; // @[Decode.scala 355:26]
-  assign io_serializeOut_mul = io_serializeIn_mul | mluValid_value_3_0; // @[Decode.scala 433:46]
-  assign io_serializeOut_jump = io_serializeIn_jump | d_io_jal | d_io_jalr; // @[Decode.scala 434:59]
-  assign io_serializeOut_brcond = _io_serializeOut_brcond_T | d_io_bne | d_io_blt | d_io_bge | d_io_bltu | d_io_bgeu; // @[Decode.scala 438:65]
+  assign io_alu_valid = decodeEn & aluValid_value_4_0; // @[Decode.scala 165:28]
+  assign io_alu_addr = vldst ? io_inst_inst[19:15] : io_inst_inst[11:7]; // @[Decode.scala 94:20]
+  assign io_alu_op = {io_alu_op_hi,io_alu_op_lo}; // @[Decode.scala 167:22]
+  assign io_bru_valid = decodeEn & bruValid_value_4_0; // @[Decode.scala 192:28]
+  assign io_bru_fwd = io_inst_brchFwd; // @[Decode.scala 193:14]
+  assign io_bru_op = {io_bru_op_hi,io_bru_op_lo}; // @[Decode.scala 194:22]
+  assign io_bru_pc = io_inst_addr; // @[Decode.scala 195:13]
+  assign io_bru_target = io_inst_addr + _io_bru_target_T_1; // @[Decode.scala 196:33]
+  assign io_bru_link = vldst ? io_inst_inst[19:15] : io_inst_inst[11:7]; // @[Decode.scala 94:20]
+  assign io_csr_op = 3'h0; // @[Decode.scala 224:22]
+  assign io_lsu_valid = decodeEn & lsuValid_value_3_0; // @[Decode.scala 234:28]
+  assign io_lsu_addr = vldst ? io_inst_inst[19:15] : io_inst_inst[11:7]; // @[Decode.scala 94:20]
+  assign io_lsu_op = {io_lsu_op_hi,io_lsu_op_lo}; // @[Decode.scala 237:22]
+  assign io_mlu_valid = decodeEn & mluValid_value_3_0; // @[Decode.scala 257:28]
+  assign io_mlu_addr = vldst ? io_inst_inst[19:15] : io_inst_inst[11:7]; // @[Decode.scala 94:20]
+  assign io_mlu_op = {io_mlu_op_hi,io_mlu_op_lo}; // @[Decode.scala 259:22]
+  assign io_dvu_op = 4'h0; // @[Decode.scala 277:22]
+  assign io_vinst_valid = decodeEn & vinstValid_value_2_0; // @[Decode.scala 291:30]
+  assign io_vinst_addr = vldst ? io_inst_inst[19:15] : io_inst_inst[11:7]; // @[Decode.scala 94:20]
+  assign io_vinst_inst = io_inst_inst; // @[Decode.scala 293:17]
+  assign io_vinst_op = {io_vinst_op_hi,io_vinst_op_lo}; // @[Decode.scala 294:26]
+  assign io_serializeOut_mul = io_serializeIn_mul | mluValid_value_3_0; // @[Decode.scala 369:46]
+  assign io_serializeOut_jump = io_serializeIn_jump | d_io_jal | d_io_jalr; // @[Decode.scala 370:59]
+  assign io_serializeOut_brcond = _io_serializeOut_brcond_T | d_io_bne | d_io_blt | d_io_bge | d_io_bltu | d_io_bgeu; // @[Decode.scala 374:65]
   assign d_clock = clock;
   assign d_reset = reset;
-  assign d_io_addr = io_inst_addr; // @[Decode.scala 92:13]
-  assign d_io_inst = io_inst_inst; // @[Decode.scala 93:13]
+  assign d_io_addr = io_inst_addr; // @[Decode.scala 88:13]
+  assign d_io_inst = io_inst_inst; // @[Decode.scala 89:13]
 endmodule
 module DecodedInstruction_2(
   input         clock,
@@ -10873,33 +10183,6 @@
   output        io_divu,
   output        io_rem,
   output        io_remu,
-  output        io_flw,
-  output        io_fsw,
-  output        io_fmadd,
-  output        io_fmsub,
-  output        io_fnmsub,
-  output        io_fnmadd,
-  output        io_fadd,
-  output        io_fsub,
-  output        io_fmul,
-  output        io_fdiv,
-  output        io_fsqrt,
-  output        io_fsgnj,
-  output        io_fsgnjn,
-  output        io_fsgnjx,
-  output        io_fmin,
-  output        io_fmax,
-  output        io_fcvtws,
-  output        io_fcvtwus,
-  output        io_fmvxw,
-  output        io_feq,
-  output        io_flt,
-  output        io_fle,
-  output        io_fclass,
-  output        io_fcvtsw,
-  output        io_fcvtswu,
-  output        io_fmvwx,
-  output        io_clb,
   output        io_clz,
   output        io_ctz,
   output        io_pcnt,
@@ -10912,7 +10195,6 @@
   output        io_vld,
   output        io_vst,
   output        io_viop,
-  output        io_vfop,
   output        io_ebreak,
   output        io_ecall,
   output        io_eexit,
@@ -10936,343 +10218,318 @@
   wire [4:0] io_immbr_lo = {io_inst[11:8],1'h0}; // @[Cat.scala 31:58]
   wire [26:0] io_immbr_hi = {_io_imm12_T_2,io_inst[7],io_inst[30:25]}; // @[Cat.scala 31:58]
   wire [26:0] io_immst_hi = {_io_imm12_T_2,io_inst[31:25]}; // @[Cat.scala 31:58]
-  wire  io_lui_bit_1 = io_inst[30]; // @[Library.scala 316:23]
-  wire  io_lui_bit_2 = io_inst[29]; // @[Library.scala 316:23]
-  wire  io_lui_bit_3 = io_inst[28]; // @[Library.scala 316:23]
-  wire  io_lui_bit_4 = io_inst[27]; // @[Library.scala 316:23]
-  wire  io_lui_bit_5 = io_inst[26]; // @[Library.scala 316:23]
-  wire  io_lui_bit_6 = io_inst[25]; // @[Library.scala 316:23]
-  wire  io_lui_bit_7 = io_inst[24]; // @[Library.scala 316:23]
-  wire  io_lui_bit_8 = io_inst[23]; // @[Library.scala 316:23]
-  wire  io_lui_bit_9 = io_inst[22]; // @[Library.scala 316:23]
-  wire  io_lui_bit_10 = io_inst[21]; // @[Library.scala 316:23]
-  wire  io_lui_bit_12 = io_inst[19]; // @[Library.scala 316:23]
-  wire  io_lui_bit_13 = io_inst[18]; // @[Library.scala 316:23]
-  wire  io_lui_bit_14 = io_inst[17]; // @[Library.scala 316:23]
-  wire  io_lui_bit_15 = io_inst[16]; // @[Library.scala 316:23]
-  wire  io_lui_bit_16 = io_inst[15]; // @[Library.scala 316:23]
-  wire  io_lui_bit_17 = io_inst[14]; // @[Library.scala 316:23]
-  wire  io_lui_bit_18 = io_inst[13]; // @[Library.scala 316:23]
-  wire  io_lui_bit_19 = io_inst[12]; // @[Library.scala 316:23]
-  wire  io_lui_bit_25 = ~io_inst[6]; // @[Library.scala 310:19]
-  wire  io_lui_bit_26 = io_inst[5]; // @[Library.scala 313:23]
-  wire  io_lui_bit_27 = io_inst[4]; // @[Library.scala 313:23]
-  wire  _io_lui_T_2 = io_lui_bit_25 & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 314:48]
-  wire  io_lui_bit_28 = ~io_inst[3]; // @[Library.scala 310:19]
-  wire  _io_lui_T_3 = _io_lui_T_2 & io_lui_bit_28; // @[Library.scala 311:48]
-  wire  io_lui_bit_29 = io_inst[2]; // @[Library.scala 313:23]
-  wire  io_lui_bit_30 = io_inst[1]; // @[Library.scala 313:23]
-  wire  io_lui_bit_31 = io_inst[0]; // @[Library.scala 313:23]
-  wire  io_auipc_bit_26 = ~io_lui_bit_26; // @[Library.scala 310:19]
-  wire  _io_auipc_T_1 = io_lui_bit_25 & io_auipc_bit_26; // @[Library.scala 311:48]
-  wire  _io_auipc_T_2 = _io_auipc_T_1 & io_lui_bit_27; // @[Library.scala 314:48]
-  wire  _io_auipc_T_3 = _io_auipc_T_2 & io_lui_bit_28; // @[Library.scala 311:48]
-  wire  _io_jal_T_1 = io_inst[6] & io_lui_bit_26; // @[Library.scala 314:48]
-  wire  io_jal_bit_27 = ~io_lui_bit_27; // @[Library.scala 310:19]
-  wire  _io_jal_T_2 = _io_jal_T_1 & io_jal_bit_27; // @[Library.scala 311:48]
-  wire  io_jalr_bit_17 = ~io_lui_bit_17; // @[Library.scala 310:19]
-  wire  io_jalr_bit_18 = ~io_lui_bit_18; // @[Library.scala 310:19]
-  wire  _io_jalr_T_1 = io_jalr_bit_17 & io_jalr_bit_18; // @[Library.scala 311:48]
-  wire  io_jalr_bit_19 = ~io_lui_bit_19; // @[Library.scala 310:19]
-  wire  _io_jalr_T_2 = io_jalr_bit_17 & io_jalr_bit_18 & io_jalr_bit_19; // @[Library.scala 311:48]
-  wire  _io_jalr_T_4 = _io_jalr_T_2 & io_inst[6] & io_lui_bit_26; // @[Library.scala 314:48]
-  wire  _io_jalr_T_6 = _io_jalr_T_4 & io_jal_bit_27 & io_lui_bit_28; // @[Library.scala 311:48]
-  wire  io_beq_bit_29 = ~io_lui_bit_29; // @[Library.scala 310:19]
-  wire  _io_beq_T_7 = _io_jalr_T_4 & io_jal_bit_27 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 311:48]
-  wire  _io_bne_T_2 = _io_jalr_T_1 & io_lui_bit_19; // @[Library.scala 314:48]
-  wire  _io_bne_T_4 = _io_jalr_T_1 & io_lui_bit_19 & io_inst[6] & io_lui_bit_26; // @[Library.scala 314:48]
-  wire  _io_bne_T_7 = _io_bne_T_4 & io_jal_bit_27 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 311:48]
-  wire  _io_blt_T_1 = io_lui_bit_17 & io_jalr_bit_18; // @[Library.scala 311:48]
-  wire  _io_blt_T_2 = io_lui_bit_17 & io_jalr_bit_18 & io_jalr_bit_19; // @[Library.scala 311:48]
-  wire  _io_blt_T_4 = _io_blt_T_2 & io_inst[6] & io_lui_bit_26; // @[Library.scala 314:48]
-  wire  _io_blt_T_7 = _io_blt_T_4 & io_jal_bit_27 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 311:48]
-  wire  _io_bge_T_2 = _io_blt_T_1 & io_lui_bit_19; // @[Library.scala 314:48]
-  wire  _io_bge_T_4 = _io_blt_T_1 & io_lui_bit_19 & io_inst[6] & io_lui_bit_26; // @[Library.scala 314:48]
-  wire  _io_bge_T_7 = _io_bge_T_4 & io_jal_bit_27 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 311:48]
-  wire  _io_bltu_T_1 = io_lui_bit_17 & io_lui_bit_18; // @[Library.scala 314:48]
-  wire  _io_bltu_T_2 = _io_bltu_T_1 & io_jalr_bit_19; // @[Library.scala 311:48]
-  wire  _io_bltu_T_4 = _io_bltu_T_2 & io_inst[6] & io_lui_bit_26; // @[Library.scala 314:48]
-  wire  _io_bltu_T_7 = _io_bltu_T_4 & io_jal_bit_27 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 311:48]
-  wire  _io_bgeu_T_2 = io_lui_bit_17 & io_lui_bit_18 & io_lui_bit_19; // @[Library.scala 314:48]
-  wire  _io_bgeu_T_4 = io_lui_bit_17 & io_lui_bit_18 & io_lui_bit_19 & io_inst[6] & io_lui_bit_26; // @[Library.scala 314:48]
-  wire  _io_bgeu_T_7 = _io_bgeu_T_4 & io_jal_bit_27 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 311:48]
-  wire  _io_lb_T_3 = io_jalr_bit_17 & io_jalr_bit_18 & io_jalr_bit_19 & io_lui_bit_25; // @[Library.scala 311:48]
-  wire  _io_lb_T_4 = io_jalr_bit_17 & io_jalr_bit_18 & io_jalr_bit_19 & io_lui_bit_25 & io_auipc_bit_26; // @[Library.scala 311:48]
+  wire  io_lui_bit_1 = io_inst[30]; // @[Library.scala 318:23]
+  wire  io_lui_bit_2 = io_inst[29]; // @[Library.scala 318:23]
+  wire  io_lui_bit_3 = io_inst[28]; // @[Library.scala 318:23]
+  wire  io_lui_bit_4 = io_inst[27]; // @[Library.scala 318:23]
+  wire  io_lui_bit_5 = io_inst[26]; // @[Library.scala 318:23]
+  wire  io_lui_bit_6 = io_inst[25]; // @[Library.scala 318:23]
+  wire  io_lui_bit_7 = io_inst[24]; // @[Library.scala 318:23]
+  wire  io_lui_bit_8 = io_inst[23]; // @[Library.scala 318:23]
+  wire  io_lui_bit_9 = io_inst[22]; // @[Library.scala 318:23]
+  wire  io_lui_bit_10 = io_inst[21]; // @[Library.scala 318:23]
+  wire  io_lui_bit_12 = io_inst[19]; // @[Library.scala 318:23]
+  wire  io_lui_bit_13 = io_inst[18]; // @[Library.scala 318:23]
+  wire  io_lui_bit_14 = io_inst[17]; // @[Library.scala 318:23]
+  wire  io_lui_bit_15 = io_inst[16]; // @[Library.scala 318:23]
+  wire  io_lui_bit_16 = io_inst[15]; // @[Library.scala 318:23]
+  wire  io_lui_bit_17 = io_inst[14]; // @[Library.scala 318:23]
+  wire  io_lui_bit_18 = io_inst[13]; // @[Library.scala 318:23]
+  wire  io_lui_bit_19 = io_inst[12]; // @[Library.scala 318:23]
+  wire  io_lui_bit_25 = ~io_inst[6]; // @[Library.scala 312:19]
+  wire  io_lui_bit_26 = io_inst[5]; // @[Library.scala 315:23]
+  wire  io_lui_bit_27 = io_inst[4]; // @[Library.scala 315:23]
+  wire  _io_lui_T_2 = io_lui_bit_25 & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 316:48]
+  wire  io_lui_bit_28 = ~io_inst[3]; // @[Library.scala 312:19]
+  wire  _io_lui_T_3 = _io_lui_T_2 & io_lui_bit_28; // @[Library.scala 313:48]
+  wire  io_lui_bit_29 = io_inst[2]; // @[Library.scala 315:23]
+  wire  io_lui_bit_30 = io_inst[1]; // @[Library.scala 315:23]
+  wire  io_lui_bit_31 = io_inst[0]; // @[Library.scala 315:23]
+  wire  io_auipc_bit_26 = ~io_lui_bit_26; // @[Library.scala 312:19]
+  wire  _io_auipc_T_1 = io_lui_bit_25 & io_auipc_bit_26; // @[Library.scala 313:48]
+  wire  _io_auipc_T_2 = _io_auipc_T_1 & io_lui_bit_27; // @[Library.scala 316:48]
+  wire  _io_auipc_T_3 = _io_auipc_T_2 & io_lui_bit_28; // @[Library.scala 313:48]
+  wire  _io_jal_T_1 = io_inst[6] & io_lui_bit_26; // @[Library.scala 316:48]
+  wire  io_jal_bit_27 = ~io_lui_bit_27; // @[Library.scala 312:19]
+  wire  _io_jal_T_2 = _io_jal_T_1 & io_jal_bit_27; // @[Library.scala 313:48]
+  wire  io_jalr_bit_17 = ~io_lui_bit_17; // @[Library.scala 312:19]
+  wire  io_jalr_bit_18 = ~io_lui_bit_18; // @[Library.scala 312:19]
+  wire  _io_jalr_T_1 = io_jalr_bit_17 & io_jalr_bit_18; // @[Library.scala 313:48]
+  wire  io_jalr_bit_19 = ~io_lui_bit_19; // @[Library.scala 312:19]
+  wire  _io_jalr_T_2 = io_jalr_bit_17 & io_jalr_bit_18 & io_jalr_bit_19; // @[Library.scala 313:48]
+  wire  _io_jalr_T_4 = _io_jalr_T_2 & io_inst[6] & io_lui_bit_26; // @[Library.scala 316:48]
+  wire  _io_jalr_T_6 = _io_jalr_T_4 & io_jal_bit_27 & io_lui_bit_28; // @[Library.scala 313:48]
+  wire  io_beq_bit_29 = ~io_lui_bit_29; // @[Library.scala 312:19]
+  wire  _io_beq_T_7 = _io_jalr_T_4 & io_jal_bit_27 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 313:48]
+  wire  _io_bne_T_2 = _io_jalr_T_1 & io_lui_bit_19; // @[Library.scala 316:48]
+  wire  _io_bne_T_4 = _io_jalr_T_1 & io_lui_bit_19 & io_inst[6] & io_lui_bit_26; // @[Library.scala 316:48]
+  wire  _io_bne_T_7 = _io_bne_T_4 & io_jal_bit_27 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 313:48]
+  wire  _io_blt_T_1 = io_lui_bit_17 & io_jalr_bit_18; // @[Library.scala 313:48]
+  wire  _io_blt_T_2 = io_lui_bit_17 & io_jalr_bit_18 & io_jalr_bit_19; // @[Library.scala 313:48]
+  wire  _io_blt_T_4 = _io_blt_T_2 & io_inst[6] & io_lui_bit_26; // @[Library.scala 316:48]
+  wire  _io_blt_T_7 = _io_blt_T_4 & io_jal_bit_27 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 313:48]
+  wire  _io_bge_T_2 = _io_blt_T_1 & io_lui_bit_19; // @[Library.scala 316:48]
+  wire  _io_bge_T_4 = _io_blt_T_1 & io_lui_bit_19 & io_inst[6] & io_lui_bit_26; // @[Library.scala 316:48]
+  wire  _io_bge_T_7 = _io_bge_T_4 & io_jal_bit_27 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 313:48]
+  wire  _io_bltu_T_1 = io_lui_bit_17 & io_lui_bit_18; // @[Library.scala 316:48]
+  wire  _io_bltu_T_2 = _io_bltu_T_1 & io_jalr_bit_19; // @[Library.scala 313:48]
+  wire  _io_bltu_T_4 = _io_bltu_T_2 & io_inst[6] & io_lui_bit_26; // @[Library.scala 316:48]
+  wire  _io_bltu_T_7 = _io_bltu_T_4 & io_jal_bit_27 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 313:48]
+  wire  _io_bgeu_T_2 = io_lui_bit_17 & io_lui_bit_18 & io_lui_bit_19; // @[Library.scala 316:48]
+  wire  _io_bgeu_T_4 = io_lui_bit_17 & io_lui_bit_18 & io_lui_bit_19 & io_inst[6] & io_lui_bit_26; // @[Library.scala 316:48]
+  wire  _io_bgeu_T_7 = _io_bgeu_T_4 & io_jal_bit_27 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 313:48]
+  wire  _io_lb_T_3 = io_jalr_bit_17 & io_jalr_bit_18 & io_jalr_bit_19 & io_lui_bit_25; // @[Library.scala 313:48]
+  wire  _io_lb_T_4 = io_jalr_bit_17 & io_jalr_bit_18 & io_jalr_bit_19 & io_lui_bit_25 & io_auipc_bit_26; // @[Library.scala 313:48]
   wire  _io_lb_T_7 = io_jalr_bit_17 & io_jalr_bit_18 & io_jalr_bit_19 & io_lui_bit_25 & io_auipc_bit_26 & io_jal_bit_27
-     & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 311:48]
-  wire  _io_lh_T_3 = _io_bne_T_2 & io_lui_bit_25; // @[Library.scala 311:48]
-  wire  _io_lh_T_7 = _io_bne_T_2 & io_lui_bit_25 & io_auipc_bit_26 & io_jal_bit_27 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 311:48]
-  wire  _io_lw_T_1 = io_jalr_bit_17 & io_lui_bit_18; // @[Library.scala 314:48]
-  wire  _io_lw_T_3 = _io_lw_T_1 & io_jalr_bit_19 & io_lui_bit_25; // @[Library.scala 311:48]
-  wire  _io_lw_T_4 = _io_lw_T_1 & io_jalr_bit_19 & io_lui_bit_25 & io_auipc_bit_26; // @[Library.scala 311:48]
+     & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 313:48]
+  wire  _io_lh_T_3 = _io_bne_T_2 & io_lui_bit_25; // @[Library.scala 313:48]
+  wire  _io_lh_T_7 = _io_bne_T_2 & io_lui_bit_25 & io_auipc_bit_26 & io_jal_bit_27 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 313:48]
+  wire  _io_lw_T_1 = io_jalr_bit_17 & io_lui_bit_18; // @[Library.scala 316:48]
+  wire  _io_lw_T_3 = _io_lw_T_1 & io_jalr_bit_19 & io_lui_bit_25; // @[Library.scala 313:48]
+  wire  _io_lw_T_4 = _io_lw_T_1 & io_jalr_bit_19 & io_lui_bit_25 & io_auipc_bit_26; // @[Library.scala 313:48]
   wire  _io_lw_T_7 = _io_lw_T_1 & io_jalr_bit_19 & io_lui_bit_25 & io_auipc_bit_26 & io_jal_bit_27 & io_lui_bit_28 &
-    io_beq_bit_29; // @[Library.scala 311:48]
-  wire  _io_lbu_T_4 = io_lui_bit_17 & io_jalr_bit_18 & io_jalr_bit_19 & io_lui_bit_25 & io_auipc_bit_26; // @[Library.scala 311:48]
+    io_beq_bit_29; // @[Library.scala 313:48]
+  wire  _io_lbu_T_4 = io_lui_bit_17 & io_jalr_bit_18 & io_jalr_bit_19 & io_lui_bit_25 & io_auipc_bit_26; // @[Library.scala 313:48]
   wire  _io_lbu_T_7 = io_lui_bit_17 & io_jalr_bit_18 & io_jalr_bit_19 & io_lui_bit_25 & io_auipc_bit_26 & io_jal_bit_27
-     & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 311:48]
-  wire  _io_lhu_T_7 = _io_bge_T_2 & io_lui_bit_25 & io_auipc_bit_26 & io_jal_bit_27 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 311:48]
-  wire  _io_sb_T_4 = _io_lb_T_3 & io_lui_bit_26; // @[Library.scala 314:48]
-  wire  _io_sb_T_7 = _io_sb_T_4 & io_jal_bit_27 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 311:48]
-  wire  _io_sh_T_4 = _io_lh_T_3 & io_lui_bit_26; // @[Library.scala 314:48]
-  wire  _io_sh_T_7 = _io_sh_T_4 & io_jal_bit_27 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 311:48]
-  wire  _io_sw_T_4 = _io_lw_T_3 & io_lui_bit_26; // @[Library.scala 314:48]
-  wire  _io_sw_T_7 = _io_sw_T_4 & io_jal_bit_27 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 311:48]
-  wire  io_fence_bit = ~io_inst[31]; // @[Library.scala 310:19]
-  wire  io_fence_bit_1 = ~io_lui_bit_1; // @[Library.scala 310:19]
-  wire  _io_fence_T_1 = io_fence_bit & io_fence_bit_1; // @[Library.scala 311:48]
-  wire  io_fence_bit_2 = ~io_lui_bit_2; // @[Library.scala 310:19]
-  wire  _io_fence_T_2 = io_fence_bit & io_fence_bit_1 & io_fence_bit_2; // @[Library.scala 311:48]
-  wire  io_fence_bit_3 = ~io_lui_bit_3; // @[Library.scala 310:19]
-  wire  _io_fence_T_3 = io_fence_bit & io_fence_bit_1 & io_fence_bit_2 & io_fence_bit_3; // @[Library.scala 311:48]
-  wire  io_fence_bit_12 = ~io_lui_bit_12; // @[Library.scala 310:19]
-  wire  io_fence_bit_13 = ~io_lui_bit_13; // @[Library.scala 310:19]
-  wire  io_fence_bit_14 = ~io_lui_bit_14; // @[Library.scala 310:19]
-  wire  io_fence_bit_15 = ~io_lui_bit_15; // @[Library.scala 310:19]
-  wire  io_fence_bit_16 = ~io_lui_bit_16; // @[Library.scala 310:19]
-  wire  _io_addi_T_5 = _io_lb_T_4 & io_lui_bit_27; // @[Library.scala 314:48]
-  wire  _io_addi_T_7 = _io_addi_T_5 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 311:48]
-  wire  _io_slti_T_5 = _io_lw_T_4 & io_lui_bit_27; // @[Library.scala 314:48]
-  wire  _io_slti_T_7 = _io_slti_T_5 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 311:48]
-  wire  _io_sltiu_T_2 = io_jalr_bit_17 & io_lui_bit_18 & io_lui_bit_19; // @[Library.scala 314:48]
-  wire  _io_sltiu_T_4 = _io_sltiu_T_2 & io_lui_bit_25 & io_auipc_bit_26; // @[Library.scala 311:48]
-  wire  _io_sltiu_T_5 = _io_sltiu_T_4 & io_lui_bit_27; // @[Library.scala 314:48]
-  wire  _io_sltiu_T_7 = _io_sltiu_T_5 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 311:48]
-  wire  _io_xori_T_5 = _io_lbu_T_4 & io_lui_bit_27; // @[Library.scala 314:48]
-  wire  _io_xori_T_7 = _io_xori_T_5 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 311:48]
-  wire  _io_ori_T_4 = _io_bltu_T_1 & io_jalr_bit_19 & io_lui_bit_25 & io_auipc_bit_26; // @[Library.scala 311:48]
-  wire  _io_ori_T_5 = _io_ori_T_4 & io_lui_bit_27; // @[Library.scala 314:48]
-  wire  _io_ori_T_7 = _io_ori_T_5 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 311:48]
-  wire  _io_andi_T_4 = _io_bgeu_T_2 & io_lui_bit_25 & io_auipc_bit_26; // @[Library.scala 311:48]
-  wire  _io_andi_T_5 = _io_andi_T_4 & io_lui_bit_27; // @[Library.scala 314:48]
-  wire  _io_andi_T_7 = _io_andi_T_5 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 311:48]
-  wire  io_slli_bit_4 = ~io_lui_bit_4; // @[Library.scala 310:19]
-  wire  _io_slli_T_4 = io_fence_bit & io_fence_bit_1 & io_fence_bit_2 & io_fence_bit_3 & io_slli_bit_4; // @[Library.scala 311:48]
-  wire  io_slli_bit_5 = ~io_lui_bit_5; // @[Library.scala 310:19]
-  wire  _io_slli_T_5 = io_fence_bit & io_fence_bit_1 & io_fence_bit_2 & io_fence_bit_3 & io_slli_bit_4 & io_slli_bit_5; // @[Library.scala 311:48]
-  wire  io_slli_bit_6 = ~io_lui_bit_6; // @[Library.scala 310:19]
+     & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 313:48]
+  wire  _io_lhu_T_7 = _io_bge_T_2 & io_lui_bit_25 & io_auipc_bit_26 & io_jal_bit_27 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 313:48]
+  wire  _io_sb_T_4 = _io_lb_T_3 & io_lui_bit_26; // @[Library.scala 316:48]
+  wire  _io_sb_T_7 = _io_sb_T_4 & io_jal_bit_27 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 313:48]
+  wire  _io_sh_T_4 = _io_lh_T_3 & io_lui_bit_26; // @[Library.scala 316:48]
+  wire  _io_sh_T_7 = _io_sh_T_4 & io_jal_bit_27 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 313:48]
+  wire  _io_sw_T_4 = _io_lw_T_3 & io_lui_bit_26; // @[Library.scala 316:48]
+  wire  _io_sw_T_7 = _io_sw_T_4 & io_jal_bit_27 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 313:48]
+  wire  io_fence_bit = ~io_inst[31]; // @[Library.scala 312:19]
+  wire  io_fence_bit_1 = ~io_lui_bit_1; // @[Library.scala 312:19]
+  wire  _io_fence_T_1 = io_fence_bit & io_fence_bit_1; // @[Library.scala 313:48]
+  wire  io_fence_bit_2 = ~io_lui_bit_2; // @[Library.scala 312:19]
+  wire  _io_fence_T_2 = io_fence_bit & io_fence_bit_1 & io_fence_bit_2; // @[Library.scala 313:48]
+  wire  io_fence_bit_3 = ~io_lui_bit_3; // @[Library.scala 312:19]
+  wire  _io_fence_T_3 = io_fence_bit & io_fence_bit_1 & io_fence_bit_2 & io_fence_bit_3; // @[Library.scala 313:48]
+  wire  io_fence_bit_12 = ~io_lui_bit_12; // @[Library.scala 312:19]
+  wire  io_fence_bit_13 = ~io_lui_bit_13; // @[Library.scala 312:19]
+  wire  io_fence_bit_14 = ~io_lui_bit_14; // @[Library.scala 312:19]
+  wire  io_fence_bit_15 = ~io_lui_bit_15; // @[Library.scala 312:19]
+  wire  io_fence_bit_16 = ~io_lui_bit_16; // @[Library.scala 312:19]
+  wire  _io_addi_T_5 = _io_lb_T_4 & io_lui_bit_27; // @[Library.scala 316:48]
+  wire  _io_addi_T_7 = _io_addi_T_5 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 313:48]
+  wire  _io_slti_T_5 = _io_lw_T_4 & io_lui_bit_27; // @[Library.scala 316:48]
+  wire  _io_slti_T_7 = _io_slti_T_5 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 313:48]
+  wire  _io_sltiu_T_2 = io_jalr_bit_17 & io_lui_bit_18 & io_lui_bit_19; // @[Library.scala 316:48]
+  wire  _io_sltiu_T_4 = _io_sltiu_T_2 & io_lui_bit_25 & io_auipc_bit_26; // @[Library.scala 313:48]
+  wire  _io_sltiu_T_5 = _io_sltiu_T_4 & io_lui_bit_27; // @[Library.scala 316:48]
+  wire  _io_sltiu_T_7 = _io_sltiu_T_5 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 313:48]
+  wire  _io_xori_T_5 = _io_lbu_T_4 & io_lui_bit_27; // @[Library.scala 316:48]
+  wire  _io_xori_T_7 = _io_xori_T_5 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 313:48]
+  wire  _io_ori_T_4 = _io_bltu_T_1 & io_jalr_bit_19 & io_lui_bit_25 & io_auipc_bit_26; // @[Library.scala 313:48]
+  wire  _io_ori_T_5 = _io_ori_T_4 & io_lui_bit_27; // @[Library.scala 316:48]
+  wire  _io_ori_T_7 = _io_ori_T_5 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 313:48]
+  wire  _io_andi_T_4 = _io_bgeu_T_2 & io_lui_bit_25 & io_auipc_bit_26; // @[Library.scala 313:48]
+  wire  _io_andi_T_5 = _io_andi_T_4 & io_lui_bit_27; // @[Library.scala 316:48]
+  wire  _io_andi_T_7 = _io_andi_T_5 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 313:48]
+  wire  io_slli_bit_4 = ~io_lui_bit_4; // @[Library.scala 312:19]
+  wire  _io_slli_T_4 = io_fence_bit & io_fence_bit_1 & io_fence_bit_2 & io_fence_bit_3 & io_slli_bit_4; // @[Library.scala 313:48]
+  wire  io_slli_bit_5 = ~io_lui_bit_5; // @[Library.scala 312:19]
+  wire  _io_slli_T_5 = io_fence_bit & io_fence_bit_1 & io_fence_bit_2 & io_fence_bit_3 & io_slli_bit_4 & io_slli_bit_5; // @[Library.scala 313:48]
+  wire  io_slli_bit_6 = ~io_lui_bit_6; // @[Library.scala 312:19]
   wire  _io_slli_T_6 = io_fence_bit & io_fence_bit_1 & io_fence_bit_2 & io_fence_bit_3 & io_slli_bit_4 & io_slli_bit_5
-     & io_slli_bit_6; // @[Library.scala 311:48]
+     & io_slli_bit_6; // @[Library.scala 313:48]
   wire  _io_slli_T_7 = io_fence_bit & io_fence_bit_1 & io_fence_bit_2 & io_fence_bit_3 & io_slli_bit_4 & io_slli_bit_5
-     & io_slli_bit_6 & io_jalr_bit_17; // @[Library.scala 311:48]
+     & io_slli_bit_6 & io_jalr_bit_17; // @[Library.scala 313:48]
   wire  _io_slli_T_8 = io_fence_bit & io_fence_bit_1 & io_fence_bit_2 & io_fence_bit_3 & io_slli_bit_4 & io_slli_bit_5
-     & io_slli_bit_6 & io_jalr_bit_17 & io_jalr_bit_18; // @[Library.scala 311:48]
-  wire  _io_slli_T_9 = _io_slli_T_8 & io_lui_bit_19; // @[Library.scala 314:48]
-  wire  _io_slli_T_10 = _io_slli_T_9 & io_lui_bit_25; // @[Library.scala 311:48]
-  wire  _io_slli_T_11 = _io_slli_T_9 & io_lui_bit_25 & io_auipc_bit_26; // @[Library.scala 311:48]
-  wire  _io_slli_T_12 = _io_slli_T_11 & io_lui_bit_27; // @[Library.scala 314:48]
-  wire  _io_slli_T_14 = _io_slli_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 311:48]
-  wire  _io_srli_T_7 = _io_slli_T_6 & io_lui_bit_17; // @[Library.scala 314:48]
-  wire  _io_srli_T_8 = _io_srli_T_7 & io_jalr_bit_18; // @[Library.scala 311:48]
-  wire  _io_srli_T_9 = _io_srli_T_8 & io_lui_bit_19; // @[Library.scala 314:48]
-  wire  _io_srli_T_10 = _io_srli_T_9 & io_lui_bit_25; // @[Library.scala 311:48]
-  wire  _io_srli_T_11 = _io_srli_T_9 & io_lui_bit_25 & io_auipc_bit_26; // @[Library.scala 311:48]
-  wire  _io_srli_T_12 = _io_srli_T_11 & io_lui_bit_27; // @[Library.scala 314:48]
-  wire  _io_srli_T_14 = _io_srli_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 311:48]
-  wire  _io_srai_T_1 = io_fence_bit & io_lui_bit_1; // @[Library.scala 314:48]
-  wire  _io_srai_T_2 = _io_srai_T_1 & io_fence_bit_2; // @[Library.scala 311:48]
-  wire  _io_srai_T_6 = _io_srai_T_1 & io_fence_bit_2 & io_fence_bit_3 & io_slli_bit_4 & io_slli_bit_5 & io_slli_bit_6; // @[Library.scala 311:48]
-  wire  _io_srai_T_7 = _io_srai_T_6 & io_lui_bit_17; // @[Library.scala 314:48]
-  wire  _io_srai_T_8 = _io_srai_T_7 & io_jalr_bit_18; // @[Library.scala 311:48]
-  wire  _io_srai_T_9 = _io_srai_T_8 & io_lui_bit_19; // @[Library.scala 314:48]
-  wire  _io_srai_T_10 = _io_srai_T_9 & io_lui_bit_25; // @[Library.scala 311:48]
-  wire  _io_srai_T_11 = _io_srai_T_9 & io_lui_bit_25 & io_auipc_bit_26; // @[Library.scala 311:48]
-  wire  _io_srai_T_12 = _io_srai_T_11 & io_lui_bit_27; // @[Library.scala 314:48]
-  wire  _io_srai_T_14 = _io_srai_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 311:48]
+     & io_slli_bit_6 & io_jalr_bit_17 & io_jalr_bit_18; // @[Library.scala 313:48]
+  wire  _io_slli_T_9 = _io_slli_T_8 & io_lui_bit_19; // @[Library.scala 316:48]
+  wire  _io_slli_T_10 = _io_slli_T_9 & io_lui_bit_25; // @[Library.scala 313:48]
+  wire  _io_slli_T_11 = _io_slli_T_9 & io_lui_bit_25 & io_auipc_bit_26; // @[Library.scala 313:48]
+  wire  _io_slli_T_12 = _io_slli_T_11 & io_lui_bit_27; // @[Library.scala 316:48]
+  wire  _io_slli_T_14 = _io_slli_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 313:48]
+  wire  _io_srli_T_7 = _io_slli_T_6 & io_lui_bit_17; // @[Library.scala 316:48]
+  wire  _io_srli_T_8 = _io_srli_T_7 & io_jalr_bit_18; // @[Library.scala 313:48]
+  wire  _io_srli_T_9 = _io_srli_T_8 & io_lui_bit_19; // @[Library.scala 316:48]
+  wire  _io_srli_T_10 = _io_srli_T_9 & io_lui_bit_25; // @[Library.scala 313:48]
+  wire  _io_srli_T_11 = _io_srli_T_9 & io_lui_bit_25 & io_auipc_bit_26; // @[Library.scala 313:48]
+  wire  _io_srli_T_12 = _io_srli_T_11 & io_lui_bit_27; // @[Library.scala 316:48]
+  wire  _io_srli_T_14 = _io_srli_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 313:48]
+  wire  _io_srai_T_1 = io_fence_bit & io_lui_bit_1; // @[Library.scala 316:48]
+  wire  _io_srai_T_2 = _io_srai_T_1 & io_fence_bit_2; // @[Library.scala 313:48]
+  wire  _io_srai_T_6 = _io_srai_T_1 & io_fence_bit_2 & io_fence_bit_3 & io_slli_bit_4 & io_slli_bit_5 & io_slli_bit_6; // @[Library.scala 313:48]
+  wire  _io_srai_T_7 = _io_srai_T_6 & io_lui_bit_17; // @[Library.scala 316:48]
+  wire  _io_srai_T_8 = _io_srai_T_7 & io_jalr_bit_18; // @[Library.scala 313:48]
+  wire  _io_srai_T_9 = _io_srai_T_8 & io_lui_bit_19; // @[Library.scala 316:48]
+  wire  _io_srai_T_10 = _io_srai_T_9 & io_lui_bit_25; // @[Library.scala 313:48]
+  wire  _io_srai_T_11 = _io_srai_T_9 & io_lui_bit_25 & io_auipc_bit_26; // @[Library.scala 313:48]
+  wire  _io_srai_T_12 = _io_srai_T_11 & io_lui_bit_27; // @[Library.scala 316:48]
+  wire  _io_srai_T_14 = _io_srai_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 313:48]
   wire  _io_add_T_10 = io_fence_bit & io_fence_bit_1 & io_fence_bit_2 & io_fence_bit_3 & io_slli_bit_4 & io_slli_bit_5
-     & io_slli_bit_6 & io_jalr_bit_17 & io_jalr_bit_18 & io_jalr_bit_19 & io_lui_bit_25; // @[Library.scala 311:48]
-  wire  _io_add_T_12 = _io_add_T_10 & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 314:48]
-  wire  _io_add_T_14 = _io_add_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 311:48]
+     & io_slli_bit_6 & io_jalr_bit_17 & io_jalr_bit_18 & io_jalr_bit_19 & io_lui_bit_25; // @[Library.scala 313:48]
+  wire  _io_add_T_12 = _io_add_T_10 & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 316:48]
+  wire  _io_add_T_14 = _io_add_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 313:48]
   wire  _io_sub_T_10 = _io_srai_T_1 & io_fence_bit_2 & io_fence_bit_3 & io_slli_bit_4 & io_slli_bit_5 & io_slli_bit_6 &
-    io_jalr_bit_17 & io_jalr_bit_18 & io_jalr_bit_19 & io_lui_bit_25; // @[Library.scala 311:48]
-  wire  _io_sub_T_12 = _io_sub_T_10 & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 314:48]
-  wire  _io_sub_T_14 = _io_sub_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 311:48]
-  wire  _io_slt_T_8 = _io_slli_T_7 & io_lui_bit_18; // @[Library.scala 314:48]
-  wire  _io_slt_T_10 = _io_slt_T_8 & io_jalr_bit_19 & io_lui_bit_25; // @[Library.scala 311:48]
-  wire  _io_slt_T_12 = _io_slt_T_10 & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 314:48]
-  wire  _io_slt_T_14 = _io_slt_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 311:48]
-  wire  _io_sltu_T_9 = _io_slli_T_7 & io_lui_bit_18 & io_lui_bit_19; // @[Library.scala 314:48]
-  wire  _io_sltu_T_10 = _io_sltu_T_9 & io_lui_bit_25; // @[Library.scala 311:48]
-  wire  _io_sltu_T_12 = _io_sltu_T_10 & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 314:48]
-  wire  _io_sltu_T_14 = _io_sltu_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 311:48]
-  wire  _io_xor_T_10 = _io_srli_T_7 & io_jalr_bit_18 & io_jalr_bit_19 & io_lui_bit_25; // @[Library.scala 311:48]
-  wire  _io_xor_T_12 = _io_xor_T_10 & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 314:48]
-  wire  _io_xor_T_14 = _io_xor_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 311:48]
-  wire  _io_or_T_8 = _io_slli_T_6 & io_lui_bit_17 & io_lui_bit_18; // @[Library.scala 314:48]
-  wire  _io_or_T_10 = _io_or_T_8 & io_jalr_bit_19 & io_lui_bit_25; // @[Library.scala 311:48]
-  wire  _io_or_T_12 = _io_or_T_10 & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 314:48]
-  wire  _io_or_T_14 = _io_or_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 311:48]
-  wire  _io_and_T_9 = _io_slli_T_6 & io_lui_bit_17 & io_lui_bit_18 & io_lui_bit_19; // @[Library.scala 314:48]
-  wire  _io_and_T_10 = _io_and_T_9 & io_lui_bit_25; // @[Library.scala 311:48]
-  wire  _io_and_T_12 = _io_and_T_10 & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 314:48]
-  wire  _io_and_T_14 = _io_and_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 311:48]
-  wire  _io_sll_T_12 = _io_slli_T_10 & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 314:48]
-  wire  _io_sll_T_14 = _io_sll_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 311:48]
-  wire  _io_srl_T_12 = _io_srli_T_10 & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 314:48]
-  wire  _io_srl_T_14 = _io_srl_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 311:48]
-  wire  _io_sra_T_12 = _io_srai_T_10 & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 314:48]
-  wire  _io_sra_T_14 = _io_sra_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 311:48]
-  wire  _io_mul_T_6 = _io_slli_T_5 & io_lui_bit_6; // @[Library.scala 314:48]
-  wire  _io_mul_T_7 = _io_mul_T_6 & io_jalr_bit_17; // @[Library.scala 311:48]
-  wire  _io_mul_T_8 = _io_mul_T_6 & io_jalr_bit_17 & io_jalr_bit_18; // @[Library.scala 311:48]
-  wire  _io_mul_T_10 = _io_mul_T_6 & io_jalr_bit_17 & io_jalr_bit_18 & io_jalr_bit_19 & io_lui_bit_25; // @[Library.scala 311:48]
-  wire  _io_mul_T_12 = _io_mul_T_10 & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 314:48]
-  wire  _io_mul_T_14 = _io_mul_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 311:48]
-  wire  _io_mulh_T_9 = _io_mul_T_8 & io_lui_bit_19; // @[Library.scala 314:48]
-  wire  _io_mulh_T_10 = _io_mulh_T_9 & io_lui_bit_25; // @[Library.scala 311:48]
-  wire  _io_mulh_T_12 = _io_mulh_T_10 & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 314:48]
-  wire  _io_mulh_T_14 = _io_mulh_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 311:48]
-  wire  _io_mulhsu_T_8 = _io_mul_T_7 & io_lui_bit_18; // @[Library.scala 314:48]
-  wire  _io_mulhsu_T_10 = _io_mulhsu_T_8 & io_jalr_bit_19 & io_lui_bit_25; // @[Library.scala 311:48]
-  wire  _io_mulhsu_T_12 = _io_mulhsu_T_10 & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 314:48]
-  wire  _io_mulhsu_T_14 = _io_mulhsu_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 311:48]
-  wire  _io_mulhu_T_9 = _io_mul_T_7 & io_lui_bit_18 & io_lui_bit_19; // @[Library.scala 314:48]
-  wire  _io_mulhu_T_10 = _io_mulhu_T_9 & io_lui_bit_25; // @[Library.scala 311:48]
-  wire  _io_mulhu_T_12 = _io_mulhu_T_10 & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 314:48]
-  wire  _io_mulhu_T_14 = _io_mulhu_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 311:48]
-  wire  _io_mulhr_T_2 = _io_fence_T_1 & io_lui_bit_2; // @[Library.scala 314:48]
-  wire  _io_mulhr_T_4 = _io_mulhr_T_2 & io_fence_bit_3 & io_slli_bit_4; // @[Library.scala 311:48]
-  wire  _io_mulhr_T_5 = _io_mulhr_T_2 & io_fence_bit_3 & io_slli_bit_4 & io_slli_bit_5; // @[Library.scala 311:48]
-  wire  _io_mulhr_T_6 = _io_mulhr_T_5 & io_lui_bit_6; // @[Library.scala 314:48]
-  wire  _io_mulhr_T_7 = _io_mulhr_T_6 & io_jalr_bit_17; // @[Library.scala 311:48]
-  wire  _io_mulhr_T_8 = _io_mulhr_T_6 & io_jalr_bit_17 & io_jalr_bit_18; // @[Library.scala 311:48]
-  wire  _io_mulhr_T_9 = _io_mulhr_T_8 & io_lui_bit_19; // @[Library.scala 314:48]
-  wire  _io_mulhr_T_10 = _io_mulhr_T_9 & io_lui_bit_25; // @[Library.scala 311:48]
-  wire  _io_mulhr_T_12 = _io_mulhr_T_10 & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 314:48]
-  wire  _io_mulhr_T_14 = _io_mulhr_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 311:48]
-  wire  _io_mulhsur_T_8 = _io_mulhr_T_7 & io_lui_bit_18; // @[Library.scala 314:48]
-  wire  _io_mulhsur_T_10 = _io_mulhsur_T_8 & io_jalr_bit_19 & io_lui_bit_25; // @[Library.scala 311:48]
-  wire  _io_mulhsur_T_12 = _io_mulhsur_T_10 & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 314:48]
-  wire  _io_mulhsur_T_14 = _io_mulhsur_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 311:48]
-  wire  _io_mulhur_T_9 = _io_mulhr_T_7 & io_lui_bit_18 & io_lui_bit_19; // @[Library.scala 314:48]
-  wire  _io_mulhur_T_10 = _io_mulhur_T_9 & io_lui_bit_25; // @[Library.scala 311:48]
-  wire  _io_mulhur_T_12 = _io_mulhur_T_10 & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 314:48]
-  wire  _io_mulhur_T_14 = _io_mulhur_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 311:48]
-  wire  _io_dmulh_T_5 = _io_slli_T_4 & io_lui_bit_5; // @[Library.scala 314:48]
-  wire  _io_dmulh_T_8 = _io_dmulh_T_5 & io_slli_bit_6 & io_jalr_bit_17 & io_jalr_bit_18; // @[Library.scala 311:48]
-  wire  _io_dmulh_T_9 = _io_dmulh_T_8 & io_lui_bit_19; // @[Library.scala 314:48]
-  wire  _io_dmulh_T_10 = _io_dmulh_T_9 & io_lui_bit_25; // @[Library.scala 311:48]
-  wire  _io_dmulh_T_12 = _io_dmulh_T_10 & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 314:48]
-  wire  _io_dmulh_T_14 = _io_dmulh_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 311:48]
-  wire  _io_dmulhr_T_5 = _io_mulhr_T_4 & io_lui_bit_5; // @[Library.scala 314:48]
-  wire  _io_dmulhr_T_8 = _io_dmulhr_T_5 & io_slli_bit_6 & io_jalr_bit_17 & io_jalr_bit_18; // @[Library.scala 311:48]
-  wire  _io_dmulhr_T_9 = _io_dmulhr_T_8 & io_lui_bit_19; // @[Library.scala 314:48]
-  wire  _io_dmulhr_T_10 = _io_dmulhr_T_9 & io_lui_bit_25; // @[Library.scala 311:48]
-  wire  _io_dmulhr_T_12 = _io_dmulhr_T_10 & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 314:48]
-  wire  _io_dmulhr_T_14 = _io_dmulhr_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 311:48]
-  wire  _io_fsub_T_4 = _io_fence_T_3 & io_lui_bit_4; // @[Library.scala 314:48]
-  wire  _io_fsub_T_5 = _io_fsub_T_4 & io_slli_bit_5; // @[Library.scala 311:48]
-  wire  _io_fmul_T_3 = _io_fence_T_2 & io_lui_bit_3; // @[Library.scala 314:48]
-  wire  _io_fsqrt_T_3 = _io_srai_T_2 & io_lui_bit_3; // @[Library.scala 314:48]
-  wire  io_fcvtws_bit_7 = ~io_lui_bit_7; // @[Library.scala 310:19]
-  wire  io_fcvtws_bit_8 = ~io_lui_bit_8; // @[Library.scala 310:19]
-  wire  io_fcvtws_bit_9 = ~io_lui_bit_9; // @[Library.scala 310:19]
-  wire  io_fcvtws_bit_10 = ~io_lui_bit_10; // @[Library.scala 310:19]
-  wire  io_fcvtws_bit_11 = ~io_inst[20]; // @[Library.scala 310:19]
-  wire  _io_clb_T_2 = io_fence_bit & io_lui_bit_1 & io_lui_bit_2; // @[Library.scala 314:48]
-  wire  _io_clb_T_7 = _io_clb_T_2 & io_fence_bit_3 & io_slli_bit_4 & io_slli_bit_5 & io_slli_bit_6 & io_fcvtws_bit_7; // @[Library.scala 311:48]
-  wire  _io_clb_T_8 = _io_clb_T_7 & io_lui_bit_8; // @[Library.scala 314:48]
-  wire  _io_clb_T_13 = _io_clb_T_8 & io_fcvtws_bit_9 & io_fcvtws_bit_10 & io_fcvtws_bit_11 & io_jalr_bit_17 &
-    io_jalr_bit_18; // @[Library.scala 311:48]
-  wire  _io_clb_T_14 = _io_clb_T_13 & io_lui_bit_19; // @[Library.scala 314:48]
-  wire  _io_clb_T_16 = _io_clb_T_14 & io_lui_bit_25 & io_auipc_bit_26; // @[Library.scala 311:48]
-  wire  _io_clb_T_17 = _io_clb_T_16 & io_lui_bit_27; // @[Library.scala 314:48]
-  wire  _io_clb_T_19 = _io_clb_T_17 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 311:48]
-  wire  _io_clz_T_9 = _io_clb_T_2 & io_fence_bit_3 & io_slli_bit_4 & io_slli_bit_5 & io_slli_bit_6 & io_fcvtws_bit_7 &
-    io_fcvtws_bit_8 & io_fcvtws_bit_9; // @[Library.scala 311:48]
-  wire  _io_clz_T_10 = _io_clb_T_2 & io_fence_bit_3 & io_slli_bit_4 & io_slli_bit_5 & io_slli_bit_6 & io_fcvtws_bit_7 &
-    io_fcvtws_bit_8 & io_fcvtws_bit_9 & io_fcvtws_bit_10; // @[Library.scala 311:48]
-  wire  _io_clz_T_13 = _io_clb_T_2 & io_fence_bit_3 & io_slli_bit_4 & io_slli_bit_5 & io_slli_bit_6 & io_fcvtws_bit_7 &
-    io_fcvtws_bit_8 & io_fcvtws_bit_9 & io_fcvtws_bit_10 & io_fcvtws_bit_11 & io_jalr_bit_17 & io_jalr_bit_18; // @[Library.scala 311:48]
-  wire  _io_clz_T_14 = _io_clz_T_13 & io_lui_bit_19; // @[Library.scala 314:48]
-  wire  _io_clz_T_16 = _io_clz_T_14 & io_lui_bit_25 & io_auipc_bit_26; // @[Library.scala 311:48]
-  wire  _io_clz_T_17 = _io_clz_T_16 & io_lui_bit_27; // @[Library.scala 314:48]
-  wire  _io_clz_T_19 = _io_clz_T_17 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 311:48]
-  wire  _io_ctz_T_11 = _io_clz_T_10 & io_inst[20]; // @[Library.scala 314:48]
-  wire  _io_ctz_T_13 = _io_ctz_T_11 & io_jalr_bit_17 & io_jalr_bit_18; // @[Library.scala 311:48]
-  wire  _io_ctz_T_14 = _io_ctz_T_13 & io_lui_bit_19; // @[Library.scala 314:48]
-  wire  _io_ctz_T_16 = _io_ctz_T_14 & io_lui_bit_25 & io_auipc_bit_26; // @[Library.scala 311:48]
-  wire  _io_ctz_T_17 = _io_ctz_T_16 & io_lui_bit_27; // @[Library.scala 314:48]
-  wire  _io_ctz_T_19 = _io_ctz_T_17 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 311:48]
-  wire  _io_pcnt_T_10 = _io_clz_T_9 & io_lui_bit_10; // @[Library.scala 314:48]
-  wire  _io_pcnt_T_13 = _io_pcnt_T_10 & io_fcvtws_bit_11 & io_jalr_bit_17 & io_jalr_bit_18; // @[Library.scala 311:48]
-  wire  _io_pcnt_T_14 = _io_pcnt_T_13 & io_lui_bit_19; // @[Library.scala 314:48]
-  wire  _io_pcnt_T_16 = _io_pcnt_T_14 & io_lui_bit_25 & io_auipc_bit_26; // @[Library.scala 311:48]
-  wire  _io_pcnt_T_17 = _io_pcnt_T_16 & io_lui_bit_27; // @[Library.scala 314:48]
-  wire  _io_pcnt_T_19 = _io_pcnt_T_17 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 311:48]
-  wire  _io_min_T_7 = _io_fsub_T_5 & io_lui_bit_6 & io_lui_bit_17; // @[Library.scala 314:48]
-  wire  _io_min_T_8 = _io_min_T_7 & io_jalr_bit_18; // @[Library.scala 311:48]
-  wire  _io_min_T_10 = _io_min_T_7 & io_jalr_bit_18 & io_jalr_bit_19 & io_lui_bit_25; // @[Library.scala 311:48]
-  wire  _io_min_T_12 = _io_min_T_10 & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 314:48]
-  wire  _io_min_T_14 = _io_min_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 311:48]
-  wire  _io_minu_T_8 = _io_fsub_T_5 & io_lui_bit_6 & io_lui_bit_17 & io_lui_bit_18; // @[Library.scala 314:48]
-  wire  _io_minu_T_10 = _io_minu_T_8 & io_jalr_bit_19 & io_lui_bit_25; // @[Library.scala 311:48]
-  wire  _io_minu_T_12 = _io_minu_T_10 & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 314:48]
-  wire  _io_minu_T_14 = _io_minu_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 311:48]
-  wire  _io_max_T_9 = _io_min_T_8 & io_lui_bit_19; // @[Library.scala 314:48]
-  wire  _io_max_T_10 = _io_max_T_9 & io_lui_bit_25; // @[Library.scala 311:48]
-  wire  _io_max_T_12 = _io_max_T_10 & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 314:48]
-  wire  _io_max_T_14 = _io_max_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 311:48]
-  wire  _io_maxu_T_9 = _io_fsub_T_5 & io_lui_bit_6 & io_lui_bit_17 & io_lui_bit_18 & io_lui_bit_19; // @[Library.scala 314:48]
-  wire  _io_maxu_T_10 = _io_maxu_T_9 & io_lui_bit_25; // @[Library.scala 311:48]
-  wire  _io_maxu_T_12 = _io_maxu_T_10 & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 314:48]
-  wire  _io_maxu_T_14 = _io_maxu_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 311:48]
-  wire  _io_getvl_T_6 = _io_fmul_T_3 & io_jalr_bit_17 & io_jalr_bit_18 & io_jalr_bit_19; // @[Library.scala 311:48]
-  wire  _io_getvl_T_9 = _io_getvl_T_6 & io_inst[6] & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 314:48]
-  wire  _io_getvl_T_10 = _io_getvl_T_9 & io_lui_bit_28; // @[Library.scala 311:48]
-  wire  _io_getvl_T_13 = _io_getvl_T_10 & io_lui_bit_29 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 314:48]
-  wire  _io_getvl_T_15 = io_inst[26:25] != 2'h3; // @[Decode.scala 688:89]
-  wire  _io_getmaxvl_T_16 = _io_fmul_T_3 & io_fcvtws_bit_7 & io_fcvtws_bit_8 & io_fcvtws_bit_9 & io_fcvtws_bit_10 &
-    io_fcvtws_bit_11 & io_fence_bit_12 & io_fence_bit_13 & io_fence_bit_14 & io_fence_bit_15 & io_fence_bit_16 &
-    io_jalr_bit_17 & io_jalr_bit_18 & io_jalr_bit_19; // @[Library.scala 311:48]
-  wire  _io_getmaxvl_T_19 = _io_getmaxvl_T_16 & io_inst[6] & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 314:48]
-  wire  _io_getmaxvl_T_20 = _io_getmaxvl_T_19 & io_lui_bit_28; // @[Library.scala 311:48]
-  wire  _io_getmaxvl_T_23 = _io_getmaxvl_T_20 & io_lui_bit_29 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 314:48]
-  wire  _io_vld_T_4 = io_fence_bit & io_fence_bit_1 & io_fence_bit_2 & io_slli_bit_6 & io_jalr_bit_17; // @[Library.scala 311:48]
-  wire  _io_vst_T_4 = _io_mulhr_T_2 & io_slli_bit_6 & io_jalr_bit_17; // @[Library.scala 311:48]
-  wire  _io_vst_T_9 = _io_vst_T_4 & io_lui_bit_27 & io_inst[3] & io_lui_bit_29 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 314:48]
-  wire  _io_vst_T_14 = _io_clb_T_2 & io_slli_bit_6 & io_jalr_bit_17; // @[Library.scala 311:48]
-  wire  _io_vst_T_19 = _io_vst_T_14 & io_lui_bit_27 & io_inst[3] & io_lui_bit_29 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 314:48]
-  wire  _vconv_T_17 = _io_fsqrt_T_3 & io_slli_bit_4 & io_slli_bit_5 & io_slli_bit_6 & io_fcvtws_bit_7 & io_fcvtws_bit_8
-     & io_fcvtws_bit_9 & io_fcvtws_bit_10 & io_fcvtws_bit_11 & io_fence_bit_12 & io_fence_bit_13 & io_fence_bit_14 &
-    io_fence_bit_15 & io_fence_bit_16 & io_jalr_bit_17; // @[Library.scala 311:48]
-  wire  vconv = _vconv_T_17 & io_lui_bit_27 & io_inst[3] & io_lui_bit_29 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 314:48]
+    io_jalr_bit_17 & io_jalr_bit_18 & io_jalr_bit_19 & io_lui_bit_25; // @[Library.scala 313:48]
+  wire  _io_sub_T_12 = _io_sub_T_10 & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 316:48]
+  wire  _io_sub_T_14 = _io_sub_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 313:48]
+  wire  _io_slt_T_8 = _io_slli_T_7 & io_lui_bit_18; // @[Library.scala 316:48]
+  wire  _io_slt_T_10 = _io_slt_T_8 & io_jalr_bit_19 & io_lui_bit_25; // @[Library.scala 313:48]
+  wire  _io_slt_T_12 = _io_slt_T_10 & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 316:48]
+  wire  _io_slt_T_14 = _io_slt_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 313:48]
+  wire  _io_sltu_T_9 = _io_slli_T_7 & io_lui_bit_18 & io_lui_bit_19; // @[Library.scala 316:48]
+  wire  _io_sltu_T_10 = _io_sltu_T_9 & io_lui_bit_25; // @[Library.scala 313:48]
+  wire  _io_sltu_T_12 = _io_sltu_T_10 & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 316:48]
+  wire  _io_sltu_T_14 = _io_sltu_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 313:48]
+  wire  _io_xor_T_10 = _io_srli_T_7 & io_jalr_bit_18 & io_jalr_bit_19 & io_lui_bit_25; // @[Library.scala 313:48]
+  wire  _io_xor_T_12 = _io_xor_T_10 & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 316:48]
+  wire  _io_xor_T_14 = _io_xor_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 313:48]
+  wire  _io_or_T_8 = _io_slli_T_6 & io_lui_bit_17 & io_lui_bit_18; // @[Library.scala 316:48]
+  wire  _io_or_T_10 = _io_or_T_8 & io_jalr_bit_19 & io_lui_bit_25; // @[Library.scala 313:48]
+  wire  _io_or_T_12 = _io_or_T_10 & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 316:48]
+  wire  _io_or_T_14 = _io_or_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 313:48]
+  wire  _io_and_T_9 = _io_slli_T_6 & io_lui_bit_17 & io_lui_bit_18 & io_lui_bit_19; // @[Library.scala 316:48]
+  wire  _io_and_T_10 = _io_and_T_9 & io_lui_bit_25; // @[Library.scala 313:48]
+  wire  _io_and_T_12 = _io_and_T_10 & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 316:48]
+  wire  _io_and_T_14 = _io_and_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 313:48]
+  wire  _io_sll_T_12 = _io_slli_T_10 & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 316:48]
+  wire  _io_sll_T_14 = _io_sll_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 313:48]
+  wire  _io_srl_T_12 = _io_srli_T_10 & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 316:48]
+  wire  _io_srl_T_14 = _io_srl_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 313:48]
+  wire  _io_sra_T_12 = _io_srai_T_10 & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 316:48]
+  wire  _io_sra_T_14 = _io_sra_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 313:48]
+  wire  _io_mul_T_6 = _io_slli_T_5 & io_lui_bit_6; // @[Library.scala 316:48]
+  wire  _io_mul_T_7 = _io_mul_T_6 & io_jalr_bit_17; // @[Library.scala 313:48]
+  wire  _io_mul_T_8 = _io_mul_T_6 & io_jalr_bit_17 & io_jalr_bit_18; // @[Library.scala 313:48]
+  wire  _io_mul_T_10 = _io_mul_T_6 & io_jalr_bit_17 & io_jalr_bit_18 & io_jalr_bit_19 & io_lui_bit_25; // @[Library.scala 313:48]
+  wire  _io_mul_T_12 = _io_mul_T_10 & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 316:48]
+  wire  _io_mul_T_14 = _io_mul_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 313:48]
+  wire  _io_mulh_T_9 = _io_mul_T_8 & io_lui_bit_19; // @[Library.scala 316:48]
+  wire  _io_mulh_T_10 = _io_mulh_T_9 & io_lui_bit_25; // @[Library.scala 313:48]
+  wire  _io_mulh_T_12 = _io_mulh_T_10 & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 316:48]
+  wire  _io_mulh_T_14 = _io_mulh_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 313:48]
+  wire  _io_mulhsu_T_8 = _io_mul_T_7 & io_lui_bit_18; // @[Library.scala 316:48]
+  wire  _io_mulhsu_T_10 = _io_mulhsu_T_8 & io_jalr_bit_19 & io_lui_bit_25; // @[Library.scala 313:48]
+  wire  _io_mulhsu_T_12 = _io_mulhsu_T_10 & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 316:48]
+  wire  _io_mulhsu_T_14 = _io_mulhsu_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 313:48]
+  wire  _io_mulhu_T_9 = _io_mul_T_7 & io_lui_bit_18 & io_lui_bit_19; // @[Library.scala 316:48]
+  wire  _io_mulhu_T_10 = _io_mulhu_T_9 & io_lui_bit_25; // @[Library.scala 313:48]
+  wire  _io_mulhu_T_12 = _io_mulhu_T_10 & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 316:48]
+  wire  _io_mulhu_T_14 = _io_mulhu_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 313:48]
+  wire  _io_mulhr_T_2 = _io_fence_T_1 & io_lui_bit_2; // @[Library.scala 316:48]
+  wire  _io_mulhr_T_4 = _io_mulhr_T_2 & io_fence_bit_3 & io_slli_bit_4; // @[Library.scala 313:48]
+  wire  _io_mulhr_T_5 = _io_mulhr_T_2 & io_fence_bit_3 & io_slli_bit_4 & io_slli_bit_5; // @[Library.scala 313:48]
+  wire  _io_mulhr_T_6 = _io_mulhr_T_5 & io_lui_bit_6; // @[Library.scala 316:48]
+  wire  _io_mulhr_T_7 = _io_mulhr_T_6 & io_jalr_bit_17; // @[Library.scala 313:48]
+  wire  _io_mulhr_T_8 = _io_mulhr_T_6 & io_jalr_bit_17 & io_jalr_bit_18; // @[Library.scala 313:48]
+  wire  _io_mulhr_T_9 = _io_mulhr_T_8 & io_lui_bit_19; // @[Library.scala 316:48]
+  wire  _io_mulhr_T_10 = _io_mulhr_T_9 & io_lui_bit_25; // @[Library.scala 313:48]
+  wire  _io_mulhr_T_12 = _io_mulhr_T_10 & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 316:48]
+  wire  _io_mulhr_T_14 = _io_mulhr_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 313:48]
+  wire  _io_mulhsur_T_8 = _io_mulhr_T_7 & io_lui_bit_18; // @[Library.scala 316:48]
+  wire  _io_mulhsur_T_10 = _io_mulhsur_T_8 & io_jalr_bit_19 & io_lui_bit_25; // @[Library.scala 313:48]
+  wire  _io_mulhsur_T_12 = _io_mulhsur_T_10 & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 316:48]
+  wire  _io_mulhsur_T_14 = _io_mulhsur_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 313:48]
+  wire  _io_mulhur_T_9 = _io_mulhr_T_7 & io_lui_bit_18 & io_lui_bit_19; // @[Library.scala 316:48]
+  wire  _io_mulhur_T_10 = _io_mulhur_T_9 & io_lui_bit_25; // @[Library.scala 313:48]
+  wire  _io_mulhur_T_12 = _io_mulhur_T_10 & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 316:48]
+  wire  _io_mulhur_T_14 = _io_mulhur_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 313:48]
+  wire  _io_dmulh_T_5 = _io_slli_T_4 & io_lui_bit_5; // @[Library.scala 316:48]
+  wire  _io_dmulh_T_8 = _io_dmulh_T_5 & io_slli_bit_6 & io_jalr_bit_17 & io_jalr_bit_18; // @[Library.scala 313:48]
+  wire  _io_dmulh_T_9 = _io_dmulh_T_8 & io_lui_bit_19; // @[Library.scala 316:48]
+  wire  _io_dmulh_T_10 = _io_dmulh_T_9 & io_lui_bit_25; // @[Library.scala 313:48]
+  wire  _io_dmulh_T_12 = _io_dmulh_T_10 & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 316:48]
+  wire  _io_dmulh_T_14 = _io_dmulh_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 313:48]
+  wire  _io_dmulhr_T_5 = _io_mulhr_T_4 & io_lui_bit_5; // @[Library.scala 316:48]
+  wire  _io_dmulhr_T_8 = _io_dmulhr_T_5 & io_slli_bit_6 & io_jalr_bit_17 & io_jalr_bit_18; // @[Library.scala 313:48]
+  wire  _io_dmulhr_T_9 = _io_dmulhr_T_8 & io_lui_bit_19; // @[Library.scala 316:48]
+  wire  _io_dmulhr_T_10 = _io_dmulhr_T_9 & io_lui_bit_25; // @[Library.scala 313:48]
+  wire  _io_dmulhr_T_12 = _io_dmulhr_T_10 & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 316:48]
+  wire  _io_dmulhr_T_14 = _io_dmulhr_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 313:48]
+  wire  _io_clz_T_2 = io_fence_bit & io_lui_bit_1 & io_lui_bit_2; // @[Library.scala 316:48]
+  wire  io_clz_bit_7 = ~io_lui_bit_7; // @[Library.scala 312:19]
+  wire  io_clz_bit_8 = ~io_lui_bit_8; // @[Library.scala 312:19]
+  wire  io_clz_bit_9 = ~io_lui_bit_9; // @[Library.scala 312:19]
+  wire  _io_clz_T_9 = _io_clz_T_2 & io_fence_bit_3 & io_slli_bit_4 & io_slli_bit_5 & io_slli_bit_6 & io_clz_bit_7 &
+    io_clz_bit_8 & io_clz_bit_9; // @[Library.scala 313:48]
+  wire  io_clz_bit_10 = ~io_lui_bit_10; // @[Library.scala 312:19]
+  wire  _io_clz_T_10 = _io_clz_T_2 & io_fence_bit_3 & io_slli_bit_4 & io_slli_bit_5 & io_slli_bit_6 & io_clz_bit_7 &
+    io_clz_bit_8 & io_clz_bit_9 & io_clz_bit_10; // @[Library.scala 313:48]
+  wire  io_clz_bit_11 = ~io_inst[20]; // @[Library.scala 312:19]
+  wire  _io_clz_T_13 = _io_clz_T_2 & io_fence_bit_3 & io_slli_bit_4 & io_slli_bit_5 & io_slli_bit_6 & io_clz_bit_7 &
+    io_clz_bit_8 & io_clz_bit_9 & io_clz_bit_10 & io_clz_bit_11 & io_jalr_bit_17 & io_jalr_bit_18; // @[Library.scala 313:48]
+  wire  _io_clz_T_14 = _io_clz_T_13 & io_lui_bit_19; // @[Library.scala 316:48]
+  wire  _io_clz_T_16 = _io_clz_T_14 & io_lui_bit_25 & io_auipc_bit_26; // @[Library.scala 313:48]
+  wire  _io_clz_T_17 = _io_clz_T_16 & io_lui_bit_27; // @[Library.scala 316:48]
+  wire  _io_clz_T_19 = _io_clz_T_17 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 313:48]
+  wire  _io_ctz_T_11 = _io_clz_T_10 & io_inst[20]; // @[Library.scala 316:48]
+  wire  _io_ctz_T_13 = _io_ctz_T_11 & io_jalr_bit_17 & io_jalr_bit_18; // @[Library.scala 313:48]
+  wire  _io_ctz_T_14 = _io_ctz_T_13 & io_lui_bit_19; // @[Library.scala 316:48]
+  wire  _io_ctz_T_16 = _io_ctz_T_14 & io_lui_bit_25 & io_auipc_bit_26; // @[Library.scala 313:48]
+  wire  _io_ctz_T_17 = _io_ctz_T_16 & io_lui_bit_27; // @[Library.scala 316:48]
+  wire  _io_ctz_T_19 = _io_ctz_T_17 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 313:48]
+  wire  _io_pcnt_T_10 = _io_clz_T_9 & io_lui_bit_10; // @[Library.scala 316:48]
+  wire  _io_pcnt_T_13 = _io_pcnt_T_10 & io_clz_bit_11 & io_jalr_bit_17 & io_jalr_bit_18; // @[Library.scala 313:48]
+  wire  _io_pcnt_T_14 = _io_pcnt_T_13 & io_lui_bit_19; // @[Library.scala 316:48]
+  wire  _io_pcnt_T_16 = _io_pcnt_T_14 & io_lui_bit_25 & io_auipc_bit_26; // @[Library.scala 313:48]
+  wire  _io_pcnt_T_17 = _io_pcnt_T_16 & io_lui_bit_27; // @[Library.scala 316:48]
+  wire  _io_pcnt_T_19 = _io_pcnt_T_17 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 313:48]
+  wire  _io_min_T_4 = _io_fence_T_3 & io_lui_bit_4; // @[Library.scala 316:48]
+  wire  _io_min_T_5 = _io_min_T_4 & io_slli_bit_5; // @[Library.scala 313:48]
+  wire  _io_min_T_7 = _io_min_T_5 & io_lui_bit_6 & io_lui_bit_17; // @[Library.scala 316:48]
+  wire  _io_min_T_8 = _io_min_T_7 & io_jalr_bit_18; // @[Library.scala 313:48]
+  wire  _io_min_T_10 = _io_min_T_7 & io_jalr_bit_18 & io_jalr_bit_19 & io_lui_bit_25; // @[Library.scala 313:48]
+  wire  _io_min_T_12 = _io_min_T_10 & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 316:48]
+  wire  _io_min_T_14 = _io_min_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 313:48]
+  wire  _io_minu_T_9 = _io_min_T_8 & io_lui_bit_19; // @[Library.scala 316:48]
+  wire  _io_minu_T_10 = _io_minu_T_9 & io_lui_bit_25; // @[Library.scala 313:48]
+  wire  _io_minu_T_12 = _io_minu_T_10 & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 316:48]
+  wire  _io_minu_T_14 = _io_minu_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 313:48]
+  wire  _io_max_T_8 = _io_min_T_5 & io_lui_bit_6 & io_lui_bit_17 & io_lui_bit_18; // @[Library.scala 316:48]
+  wire  _io_max_T_10 = _io_max_T_8 & io_jalr_bit_19 & io_lui_bit_25; // @[Library.scala 313:48]
+  wire  _io_max_T_12 = _io_max_T_10 & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 316:48]
+  wire  _io_max_T_14 = _io_max_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 313:48]
+  wire  _io_maxu_T_9 = _io_min_T_5 & io_lui_bit_6 & io_lui_bit_17 & io_lui_bit_18 & io_lui_bit_19; // @[Library.scala 316:48]
+  wire  _io_maxu_T_10 = _io_maxu_T_9 & io_lui_bit_25; // @[Library.scala 313:48]
+  wire  _io_maxu_T_12 = _io_maxu_T_10 & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 316:48]
+  wire  _io_maxu_T_14 = _io_maxu_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 313:48]
+  wire  _io_getvl_T_3 = _io_fence_T_2 & io_lui_bit_3; // @[Library.scala 316:48]
+  wire  _io_getvl_T_6 = _io_getvl_T_3 & io_jalr_bit_17 & io_jalr_bit_18 & io_jalr_bit_19; // @[Library.scala 313:48]
+  wire  _io_getvl_T_9 = _io_getvl_T_6 & io_inst[6] & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 316:48]
+  wire  _io_getvl_T_10 = _io_getvl_T_9 & io_lui_bit_28; // @[Library.scala 313:48]
+  wire  _io_getvl_T_13 = _io_getvl_T_10 & io_lui_bit_29 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 316:48]
+  wire  _io_getvl_T_15 = io_inst[26:25] != 2'h3; // @[Decode.scala 565:89]
+  wire  _io_getmaxvl_T_16 = _io_getvl_T_3 & io_clz_bit_7 & io_clz_bit_8 & io_clz_bit_9 & io_clz_bit_10 & io_clz_bit_11
+     & io_fence_bit_12 & io_fence_bit_13 & io_fence_bit_14 & io_fence_bit_15 & io_fence_bit_16 & io_jalr_bit_17 &
+    io_jalr_bit_18 & io_jalr_bit_19; // @[Library.scala 313:48]
+  wire  _io_getmaxvl_T_19 = _io_getmaxvl_T_16 & io_inst[6] & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 316:48]
+  wire  _io_getmaxvl_T_20 = _io_getmaxvl_T_19 & io_lui_bit_28; // @[Library.scala 313:48]
+  wire  _io_getmaxvl_T_23 = _io_getmaxvl_T_20 & io_lui_bit_29 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 316:48]
+  wire  _io_vld_T_4 = io_fence_bit & io_fence_bit_1 & io_fence_bit_2 & io_slli_bit_6 & io_jalr_bit_17; // @[Library.scala 313:48]
+  wire  _io_vst_T_4 = _io_mulhr_T_2 & io_slli_bit_6 & io_jalr_bit_17; // @[Library.scala 313:48]
+  wire  _io_vst_T_9 = _io_vst_T_4 & io_lui_bit_27 & io_inst[3] & io_lui_bit_29 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 316:48]
+  wire  _io_vst_T_14 = _io_clz_T_2 & io_slli_bit_6 & io_jalr_bit_17; // @[Library.scala 313:48]
+  wire  _io_vst_T_19 = _io_vst_T_14 & io_lui_bit_27 & io_inst[3] & io_lui_bit_29 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 316:48]
+  wire  _vconv_T_3 = _io_srai_T_2 & io_lui_bit_3; // @[Library.scala 316:48]
+  wire  _vconv_T_17 = _vconv_T_3 & io_slli_bit_4 & io_slli_bit_5 & io_slli_bit_6 & io_clz_bit_7 & io_clz_bit_8 &
+    io_clz_bit_9 & io_clz_bit_10 & io_clz_bit_11 & io_fence_bit_12 & io_fence_bit_13 & io_fence_bit_14 & io_fence_bit_15
+     & io_fence_bit_16 & io_jalr_bit_17; // @[Library.scala 313:48]
+  wire  vconv = _vconv_T_17 & io_lui_bit_27 & io_inst[3] & io_lui_bit_29 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 316:48]
   wire  _vdup_T_11 = _io_srai_T_1 & io_fence_bit_2 & io_fence_bit_3 & io_slli_bit_4 & io_slli_bit_6 & io_fence_bit_12 &
-    io_fence_bit_13 & io_fence_bit_14 & io_fence_bit_15 & io_fence_bit_16 & io_jalr_bit_17; // @[Library.scala 311:48]
-  wire  _vdup_T_16 = _vdup_T_11 & io_lui_bit_27 & io_inst[3] & io_lui_bit_29 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 314:48]
-  wire  vdup = _vdup_T_16 & io_inst[13:12] <= 2'h2; // @[Decode.scala 701:72]
-  wire  vdupi = vdup & io_slli_bit_5; // @[Decode.scala 702:20]
-  wire  vdupf = vdup & io_lui_bit_5; // @[Decode.scala 703:20]
-  wire  _vfma_T_1 = ~io_lui_bit_31; // @[Decode.scala 706:21]
-  wire  vfma = ~io_lui_bit_31 & io_inst[4:2] == 3'h5; // @[Decode.scala 706:29]
-  wire  _vfma4_T_1 = io_inst[1:0] == 2'h1; // @[Decode.scala 707:23]
-  wire [3:0] _vfma4_T_4 = {io_inst[13:12],io_inst[4:3]}; // @[Cat.scala 31:58]
-  wire  vfma4 = io_inst[1:0] == 2'h1 & _vfma4_T_4 == 4'h0; // @[Decode.scala 707:31]
-  wire  _io_viop_T_7 = _vfma4_T_1 & ~vfma4; // @[Decode.scala 712:30]
-  wire  _io_viop_T_8 = _vfma_T_1 & ~vfma | _io_viop_T_7; // @[Decode.scala 711:37]
-  wire  _io_viop_T_9 = _io_viop_T_8 | vconv; // @[Decode.scala 712:40]
-  wire [5:0] decoded_lo_lo_lo_lo = {io_mpause,io_mret,io_fencei,io_flushat,io_flushall,io_slog}; // @[Cat.scala 31:58]
-  wire [12:0] decoded_lo_lo_lo = {io_getvl,io_getmaxvl,io_ebreak,io_ecall,io_eexit,io_eyield,io_ectxsw,
-    decoded_lo_lo_lo_lo}; // @[Cat.scala 31:58]
-  wire [5:0] decoded_lo_lo_hi_lo = {io_max,io_maxu,io_viop,io_vfop,io_vld,io_vst}; // @[Cat.scala 31:58]
-  wire [25:0] decoded_lo_lo = {io_fmvwx,io_clb,io_clz,io_ctz,io_pcnt,io_min,io_minu,decoded_lo_lo_hi_lo,decoded_lo_lo_lo
-    }; // @[Cat.scala 31:58]
-  wire [5:0] decoded_lo_hi_lo_lo = {io_feq,io_flt,io_fle,io_fclass,io_fcvtsw,io_fcvtswu}; // @[Cat.scala 31:58]
-  wire [12:0] decoded_lo_hi_lo = {io_fsgnjn,io_fsgnjx,io_fmin,io_fmax,io_fcvtws,io_fcvtwus,io_fmvxw,decoded_lo_hi_lo_lo}
+    io_fence_bit_13 & io_fence_bit_14 & io_fence_bit_15 & io_fence_bit_16 & io_jalr_bit_17; // @[Library.scala 313:48]
+  wire  _vdup_T_16 = _vdup_T_11 & io_lui_bit_27 & io_inst[3] & io_lui_bit_29 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 316:48]
+  wire  vdup = _vdup_T_16 & io_inst[13:12] <= 2'h2; // @[Decode.scala 578:72]
+  wire  vdupi = vdup & io_slli_bit_5; // @[Decode.scala 579:20]
+  wire  _io_viop_T_3 = io_inst[1:0] == 2'h1; // @[Decode.scala 583:22]
+  wire  _io_viop_T_4 = ~io_lui_bit_31 | _io_viop_T_3; // @[Decode.scala 582:28]
+  wire  _io_viop_T_5 = _io_viop_T_4 | vconv; // @[Decode.scala 583:30]
+  wire [9:0] decoded_lo_lo_hi = {io_minu,io_max,io_maxu,io_viop,io_vld,io_vst,io_getvl,io_getmaxvl,io_ebreak,io_ecall}; // @[Cat.scala 31:58]
+  wire [18:0] decoded_lo_lo = {decoded_lo_lo_hi,io_eexit,io_eyield,io_ectxsw,io_mpause,io_mret,io_fencei,io_flushat,
+    io_flushall,io_slog}; // @[Cat.scala 31:58]
+  wire [9:0] decoded_lo_hi_hi = {io_srl,io_sra,io_mul,io_mulh,io_mulhsu,io_mulhu,io_mulhr,io_mulhsur,io_mulhur,io_dmulh}
     ; // @[Cat.scala 31:58]
-  wire [5:0] decoded_lo_hi_hi_lo = {io_fadd,io_fsub,io_fmul,io_fdiv,io_fsqrt,io_fsgnj}; // @[Cat.scala 31:58]
-  wire [51:0] decoded_lo = {io_remu,io_flw,io_fsw,io_fmadd,io_fmsub,io_fnmsub,io_fnmadd,decoded_lo_hi_hi_lo,
-    decoded_lo_hi_lo,decoded_lo_lo}; // @[Cat.scala 31:58]
-  wire [5:0] decoded_hi_lo_lo_lo = {io_mulhur,io_dmulh,io_dmulhr,io_div,io_divu,io_rem}; // @[Cat.scala 31:58]
-  wire [12:0] decoded_hi_lo_lo = {io_sra,io_mul,io_mulh,io_mulhsu,io_mulhu,io_mulhr,io_mulhsur,decoded_hi_lo_lo_lo}; // @[Cat.scala 31:58]
-  wire [5:0] decoded_hi_lo_hi_lo = {io_and,io_slli,io_srli,io_srai,io_sll,io_srl}; // @[Cat.scala 31:58]
-  wire [25:0] decoded_hi_lo = {io_andi,io_add,io_sub,io_slt,io_sltu,io_xor,io_or,decoded_hi_lo_hi_lo,decoded_hi_lo_lo}; // @[Cat.scala 31:58]
-  wire [5:0] decoded_hi_hi_lo_lo = {io_fence,io_addi,io_slti,io_sltiu,io_xori,io_ori}; // @[Cat.scala 31:58]
-  wire [12:0] decoded_hi_hi_lo = {io_lh,io_lw,io_lbu,io_lhu,io_sb,io_sh,io_sw,decoded_hi_hi_lo_lo}; // @[Cat.scala 31:58]
-  wire [6:0] decoded_hi_hi_hi_lo = {io_bge,io_bltu,io_bgeu,io_csrrw,io_csrrs,io_csrrc,io_lb}; // @[Cat.scala 31:58]
-  wire [52:0] decoded_hi = {io_lui,io_auipc,io_jal,io_jalr,io_beq,io_bne,io_blt,decoded_hi_hi_hi_lo,decoded_hi_hi_lo,
-    decoded_hi_lo}; // @[Cat.scala 31:58]
-  wire [104:0] decoded = {decoded_hi,decoded_lo}; // @[Cat.scala 31:58]
-  wire  io_undef_value__52 = decoded[104]; // @[Library.scala 182:26]
+  wire [18:0] decoded_lo_hi = {decoded_lo_hi_hi,io_dmulhr,io_div,io_divu,io_rem,io_remu,io_clz,io_ctz,io_pcnt,io_min}; // @[Cat.scala 31:58]
+  wire [9:0] decoded_hi_lo_hi = {io_sw,io_fence,io_addi,io_slti,io_sltiu,io_xori,io_ori,io_andi,io_add,io_sub}; // @[Cat.scala 31:58]
+  wire [18:0] decoded_hi_lo = {decoded_hi_lo_hi,io_slt,io_sltu,io_xor,io_or,io_and,io_slli,io_srli,io_srai,io_sll}; // @[Cat.scala 31:58]
+  wire [9:0] decoded_hi_hi_lo = {io_csrrw,io_csrrs,io_csrrc,io_lb,io_lh,io_lw,io_lbu,io_lhu,io_sb,io_sh}; // @[Cat.scala 31:58]
+  wire [9:0] decoded_hi_hi_hi = {io_lui,io_auipc,io_jal,io_jalr,io_beq,io_bne,io_blt,io_bge,io_bltu,io_bgeu}; // @[Cat.scala 31:58]
+  wire [76:0] decoded = {decoded_hi_hi_hi,decoded_hi_hi_lo,decoded_hi_lo,decoded_lo_hi,decoded_lo_lo}; // @[Cat.scala 31:58]
+  wire  io_undef_value__38 = decoded[76]; // @[Library.scala 182:26]
   wire  io_undef_value__0 = decoded[0] | decoded[1]; // @[Library.scala 194:39]
   wire  io_undef_value__1 = decoded[2] | decoded[3]; // @[Library.scala 194:39]
   wire  io_undef_value__2 = decoded[4] | decoded[5]; // @[Library.scala 194:39]
@@ -11311,20 +10568,6 @@
   wire  io_undef_value__35 = decoded[70] | decoded[71]; // @[Library.scala 194:39]
   wire  io_undef_value__36 = decoded[72] | decoded[73]; // @[Library.scala 194:39]
   wire  io_undef_value__37 = decoded[74] | decoded[75]; // @[Library.scala 194:39]
-  wire  io_undef_value__38 = decoded[76] | decoded[77]; // @[Library.scala 194:39]
-  wire  io_undef_value__39 = decoded[78] | decoded[79]; // @[Library.scala 194:39]
-  wire  io_undef_value__40 = decoded[80] | decoded[81]; // @[Library.scala 194:39]
-  wire  io_undef_value__41 = decoded[82] | decoded[83]; // @[Library.scala 194:39]
-  wire  io_undef_value__42 = decoded[84] | decoded[85]; // @[Library.scala 194:39]
-  wire  io_undef_value__43 = decoded[86] | decoded[87]; // @[Library.scala 194:39]
-  wire  io_undef_value__44 = decoded[88] | decoded[89]; // @[Library.scala 194:39]
-  wire  io_undef_value__45 = decoded[90] | decoded[91]; // @[Library.scala 194:39]
-  wire  io_undef_value__46 = decoded[92] | decoded[93]; // @[Library.scala 194:39]
-  wire  io_undef_value__47 = decoded[94] | decoded[95]; // @[Library.scala 194:39]
-  wire  io_undef_value__48 = decoded[96] | decoded[97]; // @[Library.scala 194:39]
-  wire  io_undef_value__49 = decoded[98] | decoded[99]; // @[Library.scala 194:39]
-  wire  io_undef_value__50 = decoded[100] | decoded[101]; // @[Library.scala 194:39]
-  wire  io_undef_value__51 = decoded[102] | decoded[103]; // @[Library.scala 194:39]
   wire  io_undef_value_1_0 = io_undef_value__0 | io_undef_value__1; // @[Library.scala 194:39]
   wire  io_undef_value_1_1 = io_undef_value__2 | io_undef_value__3; // @[Library.scala 194:39]
   wire  io_undef_value_1_2 = io_undef_value__4 | io_undef_value__5; // @[Library.scala 194:39]
@@ -11344,13 +10587,6 @@
   wire  io_undef_value_1_16 = io_undef_value__32 | io_undef_value__33; // @[Library.scala 194:39]
   wire  io_undef_value_1_17 = io_undef_value__34 | io_undef_value__35; // @[Library.scala 194:39]
   wire  io_undef_value_1_18 = io_undef_value__36 | io_undef_value__37; // @[Library.scala 194:39]
-  wire  io_undef_value_1_19 = io_undef_value__38 | io_undef_value__39; // @[Library.scala 194:39]
-  wire  io_undef_value_1_20 = io_undef_value__40 | io_undef_value__41; // @[Library.scala 194:39]
-  wire  io_undef_value_1_21 = io_undef_value__42 | io_undef_value__43; // @[Library.scala 194:39]
-  wire  io_undef_value_1_22 = io_undef_value__44 | io_undef_value__45; // @[Library.scala 194:39]
-  wire  io_undef_value_1_23 = io_undef_value__46 | io_undef_value__47; // @[Library.scala 194:39]
-  wire  io_undef_value_1_24 = io_undef_value__48 | io_undef_value__49; // @[Library.scala 194:39]
-  wire  io_undef_value_1_25 = io_undef_value__50 | io_undef_value__51; // @[Library.scala 194:39]
   wire  io_undef_value_2_0 = io_undef_value_1_0 | io_undef_value_1_1; // @[Library.scala 194:39]
   wire  io_undef_value_2_1 = io_undef_value_1_2 | io_undef_value_1_3; // @[Library.scala 194:39]
   wire  io_undef_value_2_2 = io_undef_value_1_4 | io_undef_value_1_5; // @[Library.scala 194:39]
@@ -11360,282 +10596,200 @@
   wire  io_undef_value_2_6 = io_undef_value_1_12 | io_undef_value_1_13; // @[Library.scala 194:39]
   wire  io_undef_value_2_7 = io_undef_value_1_14 | io_undef_value_1_15; // @[Library.scala 194:39]
   wire  io_undef_value_2_8 = io_undef_value_1_16 | io_undef_value_1_17; // @[Library.scala 194:39]
-  wire  io_undef_value_2_9 = io_undef_value_1_18 | io_undef_value_1_19; // @[Library.scala 194:39]
-  wire  io_undef_value_2_10 = io_undef_value_1_20 | io_undef_value_1_21; // @[Library.scala 194:39]
-  wire  io_undef_value_2_11 = io_undef_value_1_22 | io_undef_value_1_23; // @[Library.scala 194:39]
-  wire  io_undef_value_2_12 = io_undef_value_1_24 | io_undef_value_1_25; // @[Library.scala 194:39]
+  wire  io_undef_value_2_9 = io_undef_value_1_18 | io_undef_value__38; // @[Library.scala 194:39]
   wire  io_undef_value_3_0 = io_undef_value_2_0 | io_undef_value_2_1; // @[Library.scala 194:39]
   wire  io_undef_value_3_1 = io_undef_value_2_2 | io_undef_value_2_3; // @[Library.scala 194:39]
   wire  io_undef_value_3_2 = io_undef_value_2_4 | io_undef_value_2_5; // @[Library.scala 194:39]
   wire  io_undef_value_3_3 = io_undef_value_2_6 | io_undef_value_2_7; // @[Library.scala 194:39]
   wire  io_undef_value_3_4 = io_undef_value_2_8 | io_undef_value_2_9; // @[Library.scala 194:39]
-  wire  io_undef_value_3_5 = io_undef_value_2_10 | io_undef_value_2_11; // @[Library.scala 194:39]
-  wire  io_undef_value_3_6 = io_undef_value_2_12 | io_undef_value__52; // @[Library.scala 194:39]
   wire  io_undef_value_4_0 = io_undef_value_3_0 | io_undef_value_3_1; // @[Library.scala 194:39]
   wire  io_undef_value_4_1 = io_undef_value_3_2 | io_undef_value_3_3; // @[Library.scala 194:39]
-  wire  io_undef_value_4_2 = io_undef_value_3_4 | io_undef_value_3_5; // @[Library.scala 194:39]
   wire  io_undef_value_5_0 = io_undef_value_4_0 | io_undef_value_4_1; // @[Library.scala 194:39]
-  wire  io_undef_value_5_1 = io_undef_value_4_2 | io_undef_value_3_6; // @[Library.scala 194:39]
-  wire  io_undef_value_6_0 = io_undef_value_5_0 | io_undef_value_5_1; // @[Library.scala 194:39]
-  reg  onehot_failed; // @[Decode.scala 813:30]
-  wire  _T_2 = ~reset; // @[Decode.scala 814:9]
-  wire [1:0] _onehot_decode_T_105 = decoded[1] + decoded[2]; // @[Bitwise.scala 48:55]
-  wire [1:0] _GEN_1 = {{1'd0}, decoded[0]}; // @[Bitwise.scala 48:55]
-  wire [2:0] _onehot_decode_T_107 = _GEN_1 + _onehot_decode_T_105; // @[Bitwise.scala 48:55]
-  wire [1:0] _onehot_decode_T_109 = decoded[4] + decoded[5]; // @[Bitwise.scala 48:55]
-  wire [1:0] _GEN_2 = {{1'd0}, decoded[3]}; // @[Bitwise.scala 48:55]
-  wire [2:0] _onehot_decode_T_111 = _GEN_2 + _onehot_decode_T_109; // @[Bitwise.scala 48:55]
-  wire [2:0] _onehot_decode_T_113 = _onehot_decode_T_107[1:0] + _onehot_decode_T_111[1:0]; // @[Bitwise.scala 48:55]
-  wire [1:0] _onehot_decode_T_115 = decoded[7] + decoded[8]; // @[Bitwise.scala 48:55]
-  wire [1:0] _GEN_3 = {{1'd0}, decoded[6]}; // @[Bitwise.scala 48:55]
-  wire [2:0] _onehot_decode_T_117 = _GEN_3 + _onehot_decode_T_115; // @[Bitwise.scala 48:55]
-  wire [1:0] _onehot_decode_T_119 = decoded[9] + decoded[10]; // @[Bitwise.scala 48:55]
-  wire [1:0] _onehot_decode_T_121 = decoded[11] + decoded[12]; // @[Bitwise.scala 48:55]
-  wire [2:0] _onehot_decode_T_123 = _onehot_decode_T_119 + _onehot_decode_T_121; // @[Bitwise.scala 48:55]
-  wire [2:0] _GEN_4 = {{1'd0}, _onehot_decode_T_117[1:0]}; // @[Bitwise.scala 48:55]
-  wire [3:0] _onehot_decode_T_125 = _GEN_4 + _onehot_decode_T_123; // @[Bitwise.scala 48:55]
-  wire [3:0] _onehot_decode_T_127 = _onehot_decode_T_113 + _onehot_decode_T_125[2:0]; // @[Bitwise.scala 48:55]
-  wire [1:0] _onehot_decode_T_129 = decoded[14] + decoded[15]; // @[Bitwise.scala 48:55]
-  wire [1:0] _GEN_5 = {{1'd0}, decoded[13]}; // @[Bitwise.scala 48:55]
-  wire [2:0] _onehot_decode_T_131 = _GEN_5 + _onehot_decode_T_129; // @[Bitwise.scala 48:55]
-  wire [1:0] _onehot_decode_T_133 = decoded[17] + decoded[18]; // @[Bitwise.scala 48:55]
-  wire [1:0] _GEN_6 = {{1'd0}, decoded[16]}; // @[Bitwise.scala 48:55]
-  wire [2:0] _onehot_decode_T_135 = _GEN_6 + _onehot_decode_T_133; // @[Bitwise.scala 48:55]
-  wire [2:0] _onehot_decode_T_137 = _onehot_decode_T_131[1:0] + _onehot_decode_T_135[1:0]; // @[Bitwise.scala 48:55]
-  wire [1:0] _onehot_decode_T_139 = decoded[20] + decoded[21]; // @[Bitwise.scala 48:55]
-  wire [1:0] _GEN_7 = {{1'd0}, decoded[19]}; // @[Bitwise.scala 48:55]
-  wire [2:0] _onehot_decode_T_141 = _GEN_7 + _onehot_decode_T_139; // @[Bitwise.scala 48:55]
-  wire [1:0] _onehot_decode_T_143 = decoded[22] + decoded[23]; // @[Bitwise.scala 48:55]
-  wire [1:0] _onehot_decode_T_145 = decoded[24] + decoded[25]; // @[Bitwise.scala 48:55]
-  wire [2:0] _onehot_decode_T_147 = _onehot_decode_T_143 + _onehot_decode_T_145; // @[Bitwise.scala 48:55]
-  wire [2:0] _GEN_8 = {{1'd0}, _onehot_decode_T_141[1:0]}; // @[Bitwise.scala 48:55]
-  wire [3:0] _onehot_decode_T_149 = _GEN_8 + _onehot_decode_T_147; // @[Bitwise.scala 48:55]
-  wire [3:0] _onehot_decode_T_151 = _onehot_decode_T_137 + _onehot_decode_T_149[2:0]; // @[Bitwise.scala 48:55]
-  wire [4:0] _onehot_decode_T_153 = _onehot_decode_T_127 + _onehot_decode_T_151; // @[Bitwise.scala 48:55]
-  wire [1:0] _onehot_decode_T_155 = decoded[27] + decoded[28]; // @[Bitwise.scala 48:55]
-  wire [1:0] _GEN_9 = {{1'd0}, decoded[26]}; // @[Bitwise.scala 48:55]
-  wire [2:0] _onehot_decode_T_157 = _GEN_9 + _onehot_decode_T_155; // @[Bitwise.scala 48:55]
-  wire [1:0] _onehot_decode_T_159 = decoded[30] + decoded[31]; // @[Bitwise.scala 48:55]
-  wire [1:0] _GEN_10 = {{1'd0}, decoded[29]}; // @[Bitwise.scala 48:55]
-  wire [2:0] _onehot_decode_T_161 = _GEN_10 + _onehot_decode_T_159; // @[Bitwise.scala 48:55]
-  wire [2:0] _onehot_decode_T_163 = _onehot_decode_T_157[1:0] + _onehot_decode_T_161[1:0]; // @[Bitwise.scala 48:55]
-  wire [1:0] _onehot_decode_T_165 = decoded[33] + decoded[34]; // @[Bitwise.scala 48:55]
-  wire [1:0] _GEN_11 = {{1'd0}, decoded[32]}; // @[Bitwise.scala 48:55]
-  wire [2:0] _onehot_decode_T_167 = _GEN_11 + _onehot_decode_T_165; // @[Bitwise.scala 48:55]
-  wire [1:0] _onehot_decode_T_169 = decoded[35] + decoded[36]; // @[Bitwise.scala 48:55]
-  wire [1:0] _onehot_decode_T_171 = decoded[37] + decoded[38]; // @[Bitwise.scala 48:55]
-  wire [2:0] _onehot_decode_T_173 = _onehot_decode_T_169 + _onehot_decode_T_171; // @[Bitwise.scala 48:55]
-  wire [2:0] _GEN_12 = {{1'd0}, _onehot_decode_T_167[1:0]}; // @[Bitwise.scala 48:55]
-  wire [3:0] _onehot_decode_T_175 = _GEN_12 + _onehot_decode_T_173; // @[Bitwise.scala 48:55]
-  wire [3:0] _onehot_decode_T_177 = _onehot_decode_T_163 + _onehot_decode_T_175[2:0]; // @[Bitwise.scala 48:55]
-  wire [1:0] _onehot_decode_T_179 = decoded[40] + decoded[41]; // @[Bitwise.scala 48:55]
-  wire [1:0] _GEN_13 = {{1'd0}, decoded[39]}; // @[Bitwise.scala 48:55]
-  wire [2:0] _onehot_decode_T_181 = _GEN_13 + _onehot_decode_T_179; // @[Bitwise.scala 48:55]
-  wire [1:0] _onehot_decode_T_183 = decoded[43] + decoded[44]; // @[Bitwise.scala 48:55]
-  wire [1:0] _GEN_14 = {{1'd0}, decoded[42]}; // @[Bitwise.scala 48:55]
-  wire [2:0] _onehot_decode_T_185 = _GEN_14 + _onehot_decode_T_183; // @[Bitwise.scala 48:55]
-  wire [2:0] _onehot_decode_T_187 = _onehot_decode_T_181[1:0] + _onehot_decode_T_185[1:0]; // @[Bitwise.scala 48:55]
-  wire [1:0] _onehot_decode_T_189 = decoded[46] + decoded[47]; // @[Bitwise.scala 48:55]
-  wire [1:0] _GEN_15 = {{1'd0}, decoded[45]}; // @[Bitwise.scala 48:55]
-  wire [2:0] _onehot_decode_T_191 = _GEN_15 + _onehot_decode_T_189; // @[Bitwise.scala 48:55]
-  wire [1:0] _onehot_decode_T_193 = decoded[48] + decoded[49]; // @[Bitwise.scala 48:55]
-  wire [1:0] _onehot_decode_T_195 = decoded[50] + decoded[51]; // @[Bitwise.scala 48:55]
-  wire [2:0] _onehot_decode_T_197 = _onehot_decode_T_193 + _onehot_decode_T_195; // @[Bitwise.scala 48:55]
-  wire [2:0] _GEN_16 = {{1'd0}, _onehot_decode_T_191[1:0]}; // @[Bitwise.scala 48:55]
-  wire [3:0] _onehot_decode_T_199 = _GEN_16 + _onehot_decode_T_197; // @[Bitwise.scala 48:55]
-  wire [3:0] _onehot_decode_T_201 = _onehot_decode_T_187 + _onehot_decode_T_199[2:0]; // @[Bitwise.scala 48:55]
-  wire [4:0] _onehot_decode_T_203 = _onehot_decode_T_177 + _onehot_decode_T_201; // @[Bitwise.scala 48:55]
-  wire [5:0] _onehot_decode_T_205 = _onehot_decode_T_153 + _onehot_decode_T_203; // @[Bitwise.scala 48:55]
-  wire [1:0] _onehot_decode_T_207 = decoded[53] + decoded[54]; // @[Bitwise.scala 48:55]
-  wire [1:0] _GEN_17 = {{1'd0}, decoded[52]}; // @[Bitwise.scala 48:55]
-  wire [2:0] _onehot_decode_T_209 = _GEN_17 + _onehot_decode_T_207; // @[Bitwise.scala 48:55]
-  wire [1:0] _onehot_decode_T_211 = decoded[56] + decoded[57]; // @[Bitwise.scala 48:55]
-  wire [1:0] _GEN_18 = {{1'd0}, decoded[55]}; // @[Bitwise.scala 48:55]
-  wire [2:0] _onehot_decode_T_213 = _GEN_18 + _onehot_decode_T_211; // @[Bitwise.scala 48:55]
-  wire [2:0] _onehot_decode_T_215 = _onehot_decode_T_209[1:0] + _onehot_decode_T_213[1:0]; // @[Bitwise.scala 48:55]
-  wire [1:0] _onehot_decode_T_217 = decoded[59] + decoded[60]; // @[Bitwise.scala 48:55]
-  wire [1:0] _GEN_19 = {{1'd0}, decoded[58]}; // @[Bitwise.scala 48:55]
-  wire [2:0] _onehot_decode_T_219 = _GEN_19 + _onehot_decode_T_217; // @[Bitwise.scala 48:55]
-  wire [1:0] _onehot_decode_T_221 = decoded[61] + decoded[62]; // @[Bitwise.scala 48:55]
-  wire [1:0] _onehot_decode_T_223 = decoded[63] + decoded[64]; // @[Bitwise.scala 48:55]
-  wire [2:0] _onehot_decode_T_225 = _onehot_decode_T_221 + _onehot_decode_T_223; // @[Bitwise.scala 48:55]
-  wire [2:0] _GEN_20 = {{1'd0}, _onehot_decode_T_219[1:0]}; // @[Bitwise.scala 48:55]
-  wire [3:0] _onehot_decode_T_227 = _GEN_20 + _onehot_decode_T_225; // @[Bitwise.scala 48:55]
-  wire [3:0] _onehot_decode_T_229 = _onehot_decode_T_215 + _onehot_decode_T_227[2:0]; // @[Bitwise.scala 48:55]
-  wire [1:0] _onehot_decode_T_231 = decoded[66] + decoded[67]; // @[Bitwise.scala 48:55]
-  wire [1:0] _GEN_21 = {{1'd0}, decoded[65]}; // @[Bitwise.scala 48:55]
-  wire [2:0] _onehot_decode_T_233 = _GEN_21 + _onehot_decode_T_231; // @[Bitwise.scala 48:55]
-  wire [1:0] _onehot_decode_T_235 = decoded[69] + decoded[70]; // @[Bitwise.scala 48:55]
-  wire [1:0] _GEN_22 = {{1'd0}, decoded[68]}; // @[Bitwise.scala 48:55]
-  wire [2:0] _onehot_decode_T_237 = _GEN_22 + _onehot_decode_T_235; // @[Bitwise.scala 48:55]
-  wire [2:0] _onehot_decode_T_239 = _onehot_decode_T_233[1:0] + _onehot_decode_T_237[1:0]; // @[Bitwise.scala 48:55]
-  wire [1:0] _onehot_decode_T_241 = decoded[72] + decoded[73]; // @[Bitwise.scala 48:55]
-  wire [1:0] _GEN_23 = {{1'd0}, decoded[71]}; // @[Bitwise.scala 48:55]
-  wire [2:0] _onehot_decode_T_243 = _GEN_23 + _onehot_decode_T_241; // @[Bitwise.scala 48:55]
-  wire [1:0] _onehot_decode_T_245 = decoded[74] + decoded[75]; // @[Bitwise.scala 48:55]
-  wire [1:0] _onehot_decode_T_247 = decoded[76] + decoded[77]; // @[Bitwise.scala 48:55]
-  wire [2:0] _onehot_decode_T_249 = _onehot_decode_T_245 + _onehot_decode_T_247; // @[Bitwise.scala 48:55]
-  wire [2:0] _GEN_24 = {{1'd0}, _onehot_decode_T_243[1:0]}; // @[Bitwise.scala 48:55]
-  wire [3:0] _onehot_decode_T_251 = _GEN_24 + _onehot_decode_T_249; // @[Bitwise.scala 48:55]
-  wire [3:0] _onehot_decode_T_253 = _onehot_decode_T_239 + _onehot_decode_T_251[2:0]; // @[Bitwise.scala 48:55]
-  wire [4:0] _onehot_decode_T_255 = _onehot_decode_T_229 + _onehot_decode_T_253; // @[Bitwise.scala 48:55]
-  wire [1:0] _onehot_decode_T_257 = decoded[79] + decoded[80]; // @[Bitwise.scala 48:55]
-  wire [1:0] _GEN_25 = {{1'd0}, decoded[78]}; // @[Bitwise.scala 48:55]
-  wire [2:0] _onehot_decode_T_259 = _GEN_25 + _onehot_decode_T_257; // @[Bitwise.scala 48:55]
-  wire [1:0] _onehot_decode_T_261 = decoded[82] + decoded[83]; // @[Bitwise.scala 48:55]
-  wire [1:0] _GEN_26 = {{1'd0}, decoded[81]}; // @[Bitwise.scala 48:55]
-  wire [2:0] _onehot_decode_T_263 = _GEN_26 + _onehot_decode_T_261; // @[Bitwise.scala 48:55]
-  wire [2:0] _onehot_decode_T_265 = _onehot_decode_T_259[1:0] + _onehot_decode_T_263[1:0]; // @[Bitwise.scala 48:55]
-  wire [1:0] _onehot_decode_T_267 = decoded[85] + decoded[86]; // @[Bitwise.scala 48:55]
-  wire [1:0] _GEN_27 = {{1'd0}, decoded[84]}; // @[Bitwise.scala 48:55]
-  wire [2:0] _onehot_decode_T_269 = _GEN_27 + _onehot_decode_T_267; // @[Bitwise.scala 48:55]
-  wire [1:0] _onehot_decode_T_271 = decoded[87] + decoded[88]; // @[Bitwise.scala 48:55]
-  wire [1:0] _onehot_decode_T_273 = decoded[89] + decoded[90]; // @[Bitwise.scala 48:55]
-  wire [2:0] _onehot_decode_T_275 = _onehot_decode_T_271 + _onehot_decode_T_273; // @[Bitwise.scala 48:55]
-  wire [2:0] _GEN_28 = {{1'd0}, _onehot_decode_T_269[1:0]}; // @[Bitwise.scala 48:55]
-  wire [3:0] _onehot_decode_T_277 = _GEN_28 + _onehot_decode_T_275; // @[Bitwise.scala 48:55]
-  wire [3:0] _onehot_decode_T_279 = _onehot_decode_T_265 + _onehot_decode_T_277[2:0]; // @[Bitwise.scala 48:55]
-  wire [1:0] _onehot_decode_T_281 = decoded[92] + decoded[93]; // @[Bitwise.scala 48:55]
-  wire [1:0] _GEN_29 = {{1'd0}, decoded[91]}; // @[Bitwise.scala 48:55]
-  wire [2:0] _onehot_decode_T_283 = _GEN_29 + _onehot_decode_T_281; // @[Bitwise.scala 48:55]
-  wire [1:0] _onehot_decode_T_285 = decoded[94] + decoded[95]; // @[Bitwise.scala 48:55]
-  wire [1:0] _onehot_decode_T_287 = decoded[96] + decoded[97]; // @[Bitwise.scala 48:55]
-  wire [2:0] _onehot_decode_T_289 = _onehot_decode_T_285 + _onehot_decode_T_287; // @[Bitwise.scala 48:55]
-  wire [2:0] _GEN_30 = {{1'd0}, _onehot_decode_T_283[1:0]}; // @[Bitwise.scala 48:55]
-  wire [3:0] _onehot_decode_T_291 = _GEN_30 + _onehot_decode_T_289; // @[Bitwise.scala 48:55]
-  wire [1:0] _onehot_decode_T_293 = decoded[99] + decoded[100]; // @[Bitwise.scala 48:55]
-  wire [1:0] _GEN_31 = {{1'd0}, decoded[98]}; // @[Bitwise.scala 48:55]
-  wire [2:0] _onehot_decode_T_295 = _GEN_31 + _onehot_decode_T_293; // @[Bitwise.scala 48:55]
-  wire [1:0] _onehot_decode_T_297 = decoded[101] + decoded[102]; // @[Bitwise.scala 48:55]
-  wire [1:0] _onehot_decode_T_299 = decoded[103] + io_undef_value__52; // @[Bitwise.scala 48:55]
-  wire [2:0] _onehot_decode_T_301 = _onehot_decode_T_297 + _onehot_decode_T_299; // @[Bitwise.scala 48:55]
-  wire [2:0] _GEN_32 = {{1'd0}, _onehot_decode_T_295[1:0]}; // @[Bitwise.scala 48:55]
-  wire [3:0] _onehot_decode_T_303 = _GEN_32 + _onehot_decode_T_301; // @[Bitwise.scala 48:55]
-  wire [3:0] _onehot_decode_T_305 = _onehot_decode_T_291[2:0] + _onehot_decode_T_303[2:0]; // @[Bitwise.scala 48:55]
-  wire [4:0] _onehot_decode_T_307 = _onehot_decode_T_279 + _onehot_decode_T_305; // @[Bitwise.scala 48:55]
-  wire [5:0] _onehot_decode_T_309 = _onehot_decode_T_255 + _onehot_decode_T_307; // @[Bitwise.scala 48:55]
-  wire [6:0] onehot_decode = _onehot_decode_T_205 + _onehot_decode_T_309; // @[Bitwise.scala 48:55]
-  wire [6:0] _GEN_33 = {{6'd0}, io_undef}; // @[Decode.scala 817:24]
-  wire [6:0] _T_5 = onehot_decode + _GEN_33; // @[Decode.scala 817:24]
-  wire  _T_6 = _T_5 != 7'h1; // @[Decode.scala 817:36]
+  wire  io_undef_value_6_0 = io_undef_value_5_0 | io_undef_value_3_4; // @[Library.scala 194:39]
+  reg  onehot_failed; // @[Decode.scala 651:30]
+  wire  _T_2 = ~reset; // @[Decode.scala 652:9]
+  wire [1:0] _onehot_decode_T_77 = decoded[0] + decoded[1]; // @[Bitwise.scala 48:55]
+  wire [1:0] _onehot_decode_T_79 = decoded[2] + decoded[3]; // @[Bitwise.scala 48:55]
+  wire [2:0] _onehot_decode_T_81 = _onehot_decode_T_77 + _onehot_decode_T_79; // @[Bitwise.scala 48:55]
+  wire [1:0] _onehot_decode_T_83 = decoded[4] + decoded[5]; // @[Bitwise.scala 48:55]
+  wire [1:0] _onehot_decode_T_85 = decoded[7] + decoded[8]; // @[Bitwise.scala 48:55]
+  wire [1:0] _GEN_1 = {{1'd0}, decoded[6]}; // @[Bitwise.scala 48:55]
+  wire [2:0] _onehot_decode_T_87 = _GEN_1 + _onehot_decode_T_85; // @[Bitwise.scala 48:55]
+  wire [2:0] _onehot_decode_T_89 = _onehot_decode_T_83 + _onehot_decode_T_87[1:0]; // @[Bitwise.scala 48:55]
+  wire [3:0] _onehot_decode_T_91 = _onehot_decode_T_81 + _onehot_decode_T_89; // @[Bitwise.scala 48:55]
+  wire [1:0] _onehot_decode_T_93 = decoded[9] + decoded[10]; // @[Bitwise.scala 48:55]
+  wire [1:0] _onehot_decode_T_95 = decoded[12] + decoded[13]; // @[Bitwise.scala 48:55]
+  wire [1:0] _GEN_2 = {{1'd0}, decoded[11]}; // @[Bitwise.scala 48:55]
+  wire [2:0] _onehot_decode_T_97 = _GEN_2 + _onehot_decode_T_95; // @[Bitwise.scala 48:55]
+  wire [2:0] _onehot_decode_T_99 = _onehot_decode_T_93 + _onehot_decode_T_97[1:0]; // @[Bitwise.scala 48:55]
+  wire [1:0] _onehot_decode_T_101 = decoded[14] + decoded[15]; // @[Bitwise.scala 48:55]
+  wire [1:0] _onehot_decode_T_103 = decoded[17] + decoded[18]; // @[Bitwise.scala 48:55]
+  wire [1:0] _GEN_3 = {{1'd0}, decoded[16]}; // @[Bitwise.scala 48:55]
+  wire [2:0] _onehot_decode_T_105 = _GEN_3 + _onehot_decode_T_103; // @[Bitwise.scala 48:55]
+  wire [2:0] _onehot_decode_T_107 = _onehot_decode_T_101 + _onehot_decode_T_105[1:0]; // @[Bitwise.scala 48:55]
+  wire [3:0] _onehot_decode_T_109 = _onehot_decode_T_99 + _onehot_decode_T_107; // @[Bitwise.scala 48:55]
+  wire [4:0] _onehot_decode_T_111 = _onehot_decode_T_91 + _onehot_decode_T_109; // @[Bitwise.scala 48:55]
+  wire [1:0] _onehot_decode_T_113 = decoded[19] + decoded[20]; // @[Bitwise.scala 48:55]
+  wire [1:0] _onehot_decode_T_115 = decoded[21] + decoded[22]; // @[Bitwise.scala 48:55]
+  wire [2:0] _onehot_decode_T_117 = _onehot_decode_T_113 + _onehot_decode_T_115; // @[Bitwise.scala 48:55]
+  wire [1:0] _onehot_decode_T_119 = decoded[23] + decoded[24]; // @[Bitwise.scala 48:55]
+  wire [1:0] _onehot_decode_T_121 = decoded[26] + decoded[27]; // @[Bitwise.scala 48:55]
+  wire [1:0] _GEN_4 = {{1'd0}, decoded[25]}; // @[Bitwise.scala 48:55]
+  wire [2:0] _onehot_decode_T_123 = _GEN_4 + _onehot_decode_T_121; // @[Bitwise.scala 48:55]
+  wire [2:0] _onehot_decode_T_125 = _onehot_decode_T_119 + _onehot_decode_T_123[1:0]; // @[Bitwise.scala 48:55]
+  wire [3:0] _onehot_decode_T_127 = _onehot_decode_T_117 + _onehot_decode_T_125; // @[Bitwise.scala 48:55]
+  wire [1:0] _onehot_decode_T_129 = decoded[28] + decoded[29]; // @[Bitwise.scala 48:55]
+  wire [1:0] _onehot_decode_T_131 = decoded[31] + decoded[32]; // @[Bitwise.scala 48:55]
+  wire [1:0] _GEN_5 = {{1'd0}, decoded[30]}; // @[Bitwise.scala 48:55]
+  wire [2:0] _onehot_decode_T_133 = _GEN_5 + _onehot_decode_T_131; // @[Bitwise.scala 48:55]
+  wire [2:0] _onehot_decode_T_135 = _onehot_decode_T_129 + _onehot_decode_T_133[1:0]; // @[Bitwise.scala 48:55]
+  wire [1:0] _onehot_decode_T_137 = decoded[33] + decoded[34]; // @[Bitwise.scala 48:55]
+  wire [1:0] _onehot_decode_T_139 = decoded[36] + decoded[37]; // @[Bitwise.scala 48:55]
+  wire [1:0] _GEN_6 = {{1'd0}, decoded[35]}; // @[Bitwise.scala 48:55]
+  wire [2:0] _onehot_decode_T_141 = _GEN_6 + _onehot_decode_T_139; // @[Bitwise.scala 48:55]
+  wire [2:0] _onehot_decode_T_143 = _onehot_decode_T_137 + _onehot_decode_T_141[1:0]; // @[Bitwise.scala 48:55]
+  wire [3:0] _onehot_decode_T_145 = _onehot_decode_T_135 + _onehot_decode_T_143; // @[Bitwise.scala 48:55]
+  wire [4:0] _onehot_decode_T_147 = _onehot_decode_T_127 + _onehot_decode_T_145; // @[Bitwise.scala 48:55]
+  wire [5:0] _onehot_decode_T_149 = _onehot_decode_T_111 + _onehot_decode_T_147; // @[Bitwise.scala 48:55]
+  wire [1:0] _onehot_decode_T_151 = decoded[38] + decoded[39]; // @[Bitwise.scala 48:55]
+  wire [1:0] _onehot_decode_T_153 = decoded[40] + decoded[41]; // @[Bitwise.scala 48:55]
+  wire [2:0] _onehot_decode_T_155 = _onehot_decode_T_151 + _onehot_decode_T_153; // @[Bitwise.scala 48:55]
+  wire [1:0] _onehot_decode_T_157 = decoded[42] + decoded[43]; // @[Bitwise.scala 48:55]
+  wire [1:0] _onehot_decode_T_159 = decoded[45] + decoded[46]; // @[Bitwise.scala 48:55]
+  wire [1:0] _GEN_7 = {{1'd0}, decoded[44]}; // @[Bitwise.scala 48:55]
+  wire [2:0] _onehot_decode_T_161 = _GEN_7 + _onehot_decode_T_159; // @[Bitwise.scala 48:55]
+  wire [2:0] _onehot_decode_T_163 = _onehot_decode_T_157 + _onehot_decode_T_161[1:0]; // @[Bitwise.scala 48:55]
+  wire [3:0] _onehot_decode_T_165 = _onehot_decode_T_155 + _onehot_decode_T_163; // @[Bitwise.scala 48:55]
+  wire [1:0] _onehot_decode_T_167 = decoded[47] + decoded[48]; // @[Bitwise.scala 48:55]
+  wire [1:0] _onehot_decode_T_169 = decoded[50] + decoded[51]; // @[Bitwise.scala 48:55]
+  wire [1:0] _GEN_8 = {{1'd0}, decoded[49]}; // @[Bitwise.scala 48:55]
+  wire [2:0] _onehot_decode_T_171 = _GEN_8 + _onehot_decode_T_169; // @[Bitwise.scala 48:55]
+  wire [2:0] _onehot_decode_T_173 = _onehot_decode_T_167 + _onehot_decode_T_171[1:0]; // @[Bitwise.scala 48:55]
+  wire [1:0] _onehot_decode_T_175 = decoded[52] + decoded[53]; // @[Bitwise.scala 48:55]
+  wire [1:0] _onehot_decode_T_177 = decoded[55] + decoded[56]; // @[Bitwise.scala 48:55]
+  wire [1:0] _GEN_9 = {{1'd0}, decoded[54]}; // @[Bitwise.scala 48:55]
+  wire [2:0] _onehot_decode_T_179 = _GEN_9 + _onehot_decode_T_177; // @[Bitwise.scala 48:55]
+  wire [2:0] _onehot_decode_T_181 = _onehot_decode_T_175 + _onehot_decode_T_179[1:0]; // @[Bitwise.scala 48:55]
+  wire [3:0] _onehot_decode_T_183 = _onehot_decode_T_173 + _onehot_decode_T_181; // @[Bitwise.scala 48:55]
+  wire [4:0] _onehot_decode_T_185 = _onehot_decode_T_165 + _onehot_decode_T_183; // @[Bitwise.scala 48:55]
+  wire [1:0] _onehot_decode_T_187 = decoded[57] + decoded[58]; // @[Bitwise.scala 48:55]
+  wire [1:0] _onehot_decode_T_189 = decoded[60] + decoded[61]; // @[Bitwise.scala 48:55]
+  wire [1:0] _GEN_10 = {{1'd0}, decoded[59]}; // @[Bitwise.scala 48:55]
+  wire [2:0] _onehot_decode_T_191 = _GEN_10 + _onehot_decode_T_189; // @[Bitwise.scala 48:55]
+  wire [2:0] _onehot_decode_T_193 = _onehot_decode_T_187 + _onehot_decode_T_191[1:0]; // @[Bitwise.scala 48:55]
+  wire [1:0] _onehot_decode_T_195 = decoded[62] + decoded[63]; // @[Bitwise.scala 48:55]
+  wire [1:0] _onehot_decode_T_197 = decoded[65] + decoded[66]; // @[Bitwise.scala 48:55]
+  wire [1:0] _GEN_11 = {{1'd0}, decoded[64]}; // @[Bitwise.scala 48:55]
+  wire [2:0] _onehot_decode_T_199 = _GEN_11 + _onehot_decode_T_197; // @[Bitwise.scala 48:55]
+  wire [2:0] _onehot_decode_T_201 = _onehot_decode_T_195 + _onehot_decode_T_199[1:0]; // @[Bitwise.scala 48:55]
+  wire [3:0] _onehot_decode_T_203 = _onehot_decode_T_193 + _onehot_decode_T_201; // @[Bitwise.scala 48:55]
+  wire [1:0] _onehot_decode_T_205 = decoded[67] + decoded[68]; // @[Bitwise.scala 48:55]
+  wire [1:0] _onehot_decode_T_207 = decoded[70] + decoded[71]; // @[Bitwise.scala 48:55]
+  wire [1:0] _GEN_12 = {{1'd0}, decoded[69]}; // @[Bitwise.scala 48:55]
+  wire [2:0] _onehot_decode_T_209 = _GEN_12 + _onehot_decode_T_207; // @[Bitwise.scala 48:55]
+  wire [2:0] _onehot_decode_T_211 = _onehot_decode_T_205 + _onehot_decode_T_209[1:0]; // @[Bitwise.scala 48:55]
+  wire [1:0] _onehot_decode_T_213 = decoded[72] + decoded[73]; // @[Bitwise.scala 48:55]
+  wire [1:0] _onehot_decode_T_215 = decoded[75] + io_undef_value__38; // @[Bitwise.scala 48:55]
+  wire [1:0] _GEN_13 = {{1'd0}, decoded[74]}; // @[Bitwise.scala 48:55]
+  wire [2:0] _onehot_decode_T_217 = _GEN_13 + _onehot_decode_T_215; // @[Bitwise.scala 48:55]
+  wire [2:0] _onehot_decode_T_219 = _onehot_decode_T_213 + _onehot_decode_T_217[1:0]; // @[Bitwise.scala 48:55]
+  wire [3:0] _onehot_decode_T_221 = _onehot_decode_T_211 + _onehot_decode_T_219; // @[Bitwise.scala 48:55]
+  wire [4:0] _onehot_decode_T_223 = _onehot_decode_T_203 + _onehot_decode_T_221; // @[Bitwise.scala 48:55]
+  wire [5:0] _onehot_decode_T_225 = _onehot_decode_T_185 + _onehot_decode_T_223; // @[Bitwise.scala 48:55]
+  wire [6:0] onehot_decode = _onehot_decode_T_149 + _onehot_decode_T_225; // @[Bitwise.scala 48:55]
+  wire [6:0] _GEN_14 = {{6'd0}, io_undef}; // @[Decode.scala 655:24]
+  wire [6:0] _T_5 = onehot_decode + _GEN_14; // @[Decode.scala 655:24]
+  wire  _T_6 = _T_5 != 7'h1; // @[Decode.scala 655:36]
   assign io_imm12 = {_io_imm12_T_2,io_inst[31:20]}; // @[Cat.scala 31:58]
   assign io_imm20 = {io_inst[31:12],12'h0}; // @[Cat.scala 31:58]
   assign io_immjal = {io_immjal_hi,io_immjal_lo}; // @[Cat.scala 31:58]
   assign io_immbr = {io_immbr_hi,io_immbr_lo}; // @[Cat.scala 31:58]
   assign io_immst = {io_immst_hi,io_inst[11:7]}; // @[Cat.scala 31:58]
-  assign io_lui = _io_lui_T_3 & io_lui_bit_29 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 314:48]
-  assign io_auipc = _io_auipc_T_3 & io_lui_bit_29 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 314:48]
-  assign io_jal = _io_jal_T_2 & io_inst[3] & io_lui_bit_29 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 314:48]
-  assign io_jalr = _io_jalr_T_6 & io_lui_bit_29 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 314:48]
-  assign io_beq = _io_beq_T_7 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 314:48]
-  assign io_bne = _io_bne_T_7 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 314:48]
-  assign io_blt = _io_blt_T_7 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 314:48]
-  assign io_bge = _io_bge_T_7 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 314:48]
-  assign io_bltu = _io_bltu_T_7 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 314:48]
-  assign io_bgeu = _io_bgeu_T_7 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 314:48]
-  assign io_csrrw = 1'h0; // @[Decode.scala 734:14]
-  assign io_csrrs = 1'h0; // @[Decode.scala 735:14]
-  assign io_csrrc = 1'h0; // @[Decode.scala 736:14]
-  assign io_lb = _io_lb_T_7 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 314:48]
-  assign io_lh = _io_lh_T_7 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 314:48]
-  assign io_lw = _io_lw_T_7 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 314:48]
-  assign io_lbu = _io_lbu_T_7 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 314:48]
-  assign io_lhu = _io_lhu_T_7 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 314:48]
-  assign io_sb = _io_sb_T_7 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 314:48]
-  assign io_sh = _io_sh_T_7 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 314:48]
-  assign io_sw = _io_sw_T_7 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 314:48]
-  assign io_fence = 1'h0; // @[Decode.scala 778:17]
-  assign io_addi = _io_addi_T_7 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 314:48]
-  assign io_slti = _io_slti_T_7 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 314:48]
-  assign io_sltiu = _io_sltiu_T_7 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 314:48]
-  assign io_xori = _io_xori_T_7 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 314:48]
-  assign io_ori = _io_ori_T_7 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 314:48]
-  assign io_andi = _io_andi_T_7 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 314:48]
-  assign io_slli = _io_slli_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 314:48]
-  assign io_srli = _io_srli_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 314:48]
-  assign io_srai = _io_srai_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 314:48]
-  assign io_add = _io_add_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 314:48]
-  assign io_sub = _io_sub_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 314:48]
-  assign io_slt = _io_slt_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 314:48]
-  assign io_sltu = _io_sltu_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 314:48]
-  assign io_xor = _io_xor_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 314:48]
-  assign io_or = _io_or_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 314:48]
-  assign io_and = _io_and_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 314:48]
-  assign io_sll = _io_sll_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 314:48]
-  assign io_srl = _io_srl_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 314:48]
-  assign io_sra = _io_sra_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 314:48]
-  assign io_mul = _io_mul_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 314:48]
-  assign io_mulh = _io_mulh_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 314:48]
-  assign io_mulhsu = _io_mulhsu_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 314:48]
-  assign io_mulhu = _io_mulhu_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 314:48]
-  assign io_mulhr = _io_mulhr_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 314:48]
-  assign io_mulhsur = _io_mulhsur_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 314:48]
-  assign io_mulhur = _io_mulhur_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 314:48]
-  assign io_dmulh = _io_dmulh_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 314:48]
-  assign io_dmulhr = _io_dmulhr_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 314:48]
-  assign io_div = 1'h0; // @[Decode.scala 738:12]
-  assign io_divu = 1'h0; // @[Decode.scala 739:13]
-  assign io_rem = 1'h0; // @[Decode.scala 740:12]
-  assign io_remu = 1'h0; // @[Decode.scala 741:13]
-  assign io_flw = 1'h0; // @[Decode.scala 743:12]
-  assign io_fsw = 1'h0; // @[Decode.scala 744:12]
-  assign io_fmadd = 1'h0; // @[Decode.scala 745:14]
-  assign io_fmsub = 1'h0; // @[Decode.scala 746:14]
-  assign io_fnmsub = 1'h0; // @[Decode.scala 747:15]
-  assign io_fnmadd = 1'h0; // @[Decode.scala 748:15]
-  assign io_fadd = 1'h0; // @[Decode.scala 749:13]
-  assign io_fsub = 1'h0; // @[Decode.scala 750:13]
-  assign io_fmul = 1'h0; // @[Decode.scala 751:13]
-  assign io_fdiv = 1'h0; // @[Decode.scala 752:13]
-  assign io_fsqrt = 1'h0; // @[Decode.scala 753:14]
-  assign io_fsgnj = 1'h0; // @[Decode.scala 754:14]
-  assign io_fsgnjn = 1'h0; // @[Decode.scala 755:15]
-  assign io_fsgnjx = 1'h0; // @[Decode.scala 756:15]
-  assign io_fmin = 1'h0; // @[Decode.scala 757:13]
-  assign io_fmax = 1'h0; // @[Decode.scala 758:13]
-  assign io_fcvtws = 1'h0; // @[Decode.scala 759:15]
-  assign io_fcvtwus = 1'h0; // @[Decode.scala 760:16]
-  assign io_fmvxw = 1'h0; // @[Decode.scala 761:14]
-  assign io_feq = 1'h0; // @[Decode.scala 762:12]
-  assign io_flt = 1'h0; // @[Decode.scala 763:12]
-  assign io_fle = 1'h0; // @[Decode.scala 764:12]
-  assign io_fclass = 1'h0; // @[Decode.scala 765:15]
-  assign io_fcvtsw = 1'h0; // @[Decode.scala 766:15]
-  assign io_fcvtswu = 1'h0; // @[Decode.scala 767:16]
-  assign io_fmvwx = 1'h0; // @[Decode.scala 768:14]
-  assign io_clb = _io_clb_T_19 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 314:48]
-  assign io_clz = _io_clz_T_19 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 314:48]
-  assign io_ctz = _io_ctz_T_19 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 314:48]
-  assign io_pcnt = _io_pcnt_T_19 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 314:48]
-  assign io_min = _io_min_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 314:48]
-  assign io_minu = _io_minu_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 314:48]
-  assign io_max = _io_max_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 314:48]
-  assign io_maxu = _io_maxu_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 314:48]
-  assign io_getvl = _io_getvl_T_13 & io_inst[26:25] != 2'h3 & (io_inst[24:20] != 5'h0 | io_inst[19:15] != 5'h0); // @[Decode.scala 688:97]
-  assign io_getmaxvl = _io_getmaxvl_T_23 & _io_getvl_T_15; // @[Decode.scala 689:76]
-  assign io_vld = _io_vld_T_4 & io_lui_bit_27 & io_inst[3] & io_lui_bit_29 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 314:48]
-  assign io_vst = _io_vst_T_9 | _io_vst_T_19; // @[Decode.scala 694:71]
-  assign io_viop = _io_viop_T_9 | vdupi; // @[Decode.scala 713:20]
-  assign io_vfop = vfma | vfma4 | vdupf; // @[Decode.scala 708:28]
-  assign io_ebreak = 1'h0; // @[Decode.scala 770:15]
-  assign io_ecall = 1'h0; // @[Decode.scala 771:15]
-  assign io_eexit = 1'h0; // @[Decode.scala 772:15]
-  assign io_eyield = 1'h0; // @[Decode.scala 773:15]
-  assign io_ectxsw = 1'h0; // @[Decode.scala 774:15]
-  assign io_mpause = 1'h0; // @[Decode.scala 775:15]
-  assign io_mret = 1'h0; // @[Decode.scala 776:15]
-  assign io_undef = ~io_undef_value_6_0; // @[Decode.scala 810:15]
-  assign io_fencei = 1'h0; // @[Decode.scala 779:17]
-  assign io_flushat = 1'h0; // @[Decode.scala 780:17]
-  assign io_flushall = 1'h0; // @[Decode.scala 781:17]
-  assign io_slog = 1'h0; // @[Decode.scala 783:13]
+  assign io_lui = _io_lui_T_3 & io_lui_bit_29 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 316:48]
+  assign io_auipc = _io_auipc_T_3 & io_lui_bit_29 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 316:48]
+  assign io_jal = _io_jal_T_2 & io_inst[3] & io_lui_bit_29 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 316:48]
+  assign io_jalr = _io_jalr_T_6 & io_lui_bit_29 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 316:48]
+  assign io_beq = _io_beq_T_7 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 316:48]
+  assign io_bne = _io_bne_T_7 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 316:48]
+  assign io_blt = _io_blt_T_7 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 316:48]
+  assign io_bge = _io_bge_T_7 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 316:48]
+  assign io_bltu = _io_bltu_T_7 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 316:48]
+  assign io_bgeu = _io_bgeu_T_7 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 316:48]
+  assign io_csrrw = 1'h0; // @[Decode.scala 605:14]
+  assign io_csrrs = 1'h0; // @[Decode.scala 606:14]
+  assign io_csrrc = 1'h0; // @[Decode.scala 607:14]
+  assign io_lb = _io_lb_T_7 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 316:48]
+  assign io_lh = _io_lh_T_7 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 316:48]
+  assign io_lw = _io_lw_T_7 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 316:48]
+  assign io_lbu = _io_lbu_T_7 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 316:48]
+  assign io_lhu = _io_lhu_T_7 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 316:48]
+  assign io_sb = _io_sb_T_7 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 316:48]
+  assign io_sh = _io_sh_T_7 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 316:48]
+  assign io_sw = _io_sw_T_7 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 316:48]
+  assign io_fence = 1'h0; // @[Decode.scala 622:17]
+  assign io_addi = _io_addi_T_7 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 316:48]
+  assign io_slti = _io_slti_T_7 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 316:48]
+  assign io_sltiu = _io_sltiu_T_7 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 316:48]
+  assign io_xori = _io_xori_T_7 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 316:48]
+  assign io_ori = _io_ori_T_7 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 316:48]
+  assign io_andi = _io_andi_T_7 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 316:48]
+  assign io_slli = _io_slli_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 316:48]
+  assign io_srli = _io_srli_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 316:48]
+  assign io_srai = _io_srai_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 316:48]
+  assign io_add = _io_add_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 316:48]
+  assign io_sub = _io_sub_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 316:48]
+  assign io_slt = _io_slt_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 316:48]
+  assign io_sltu = _io_sltu_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 316:48]
+  assign io_xor = _io_xor_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 316:48]
+  assign io_or = _io_or_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 316:48]
+  assign io_and = _io_and_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 316:48]
+  assign io_sll = _io_sll_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 316:48]
+  assign io_srl = _io_srl_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 316:48]
+  assign io_sra = _io_sra_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 316:48]
+  assign io_mul = _io_mul_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 316:48]
+  assign io_mulh = _io_mulh_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 316:48]
+  assign io_mulhsu = _io_mulhsu_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 316:48]
+  assign io_mulhu = _io_mulhu_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 316:48]
+  assign io_mulhr = _io_mulhr_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 316:48]
+  assign io_mulhsur = _io_mulhsur_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 316:48]
+  assign io_mulhur = _io_mulhur_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 316:48]
+  assign io_dmulh = _io_dmulh_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 316:48]
+  assign io_dmulhr = _io_dmulhr_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 316:48]
+  assign io_div = 1'h0; // @[Decode.scala 609:12]
+  assign io_divu = 1'h0; // @[Decode.scala 610:13]
+  assign io_rem = 1'h0; // @[Decode.scala 611:12]
+  assign io_remu = 1'h0; // @[Decode.scala 612:13]
+  assign io_clz = _io_clz_T_19 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 316:48]
+  assign io_ctz = _io_ctz_T_19 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 316:48]
+  assign io_pcnt = _io_pcnt_T_19 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 316:48]
+  assign io_min = _io_min_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 316:48]
+  assign io_minu = _io_minu_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 316:48]
+  assign io_max = _io_max_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 316:48]
+  assign io_maxu = _io_maxu_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 316:48]
+  assign io_getvl = _io_getvl_T_13 & io_inst[26:25] != 2'h3 & (io_inst[24:20] != 5'h0 | io_inst[19:15] != 5'h0); // @[Decode.scala 565:97]
+  assign io_getmaxvl = _io_getmaxvl_T_23 & _io_getvl_T_15; // @[Decode.scala 566:76]
+  assign io_vld = _io_vld_T_4 & io_lui_bit_27 & io_inst[3] & io_lui_bit_29 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 316:48]
+  assign io_vst = _io_vst_T_9 | _io_vst_T_19; // @[Decode.scala 571:71]
+  assign io_viop = _io_viop_T_5 | vdupi; // @[Decode.scala 584:20]
+  assign io_ebreak = 1'h0; // @[Decode.scala 614:15]
+  assign io_ecall = 1'h0; // @[Decode.scala 615:15]
+  assign io_eexit = 1'h0; // @[Decode.scala 616:15]
+  assign io_eyield = 1'h0; // @[Decode.scala 617:15]
+  assign io_ectxsw = 1'h0; // @[Decode.scala 618:15]
+  assign io_mpause = 1'h0; // @[Decode.scala 619:15]
+  assign io_mret = 1'h0; // @[Decode.scala 620:15]
+  assign io_undef = ~io_undef_value_6_0; // @[Decode.scala 648:15]
+  assign io_fencei = 1'h0; // @[Decode.scala 623:17]
+  assign io_flushat = 1'h0; // @[Decode.scala 624:17]
+  assign io_flushall = 1'h0; // @[Decode.scala 625:17]
+  assign io_slog = 1'h0; // @[Decode.scala 627:13]
   always @(posedge clock) begin
     `ifndef SYNTHESIS
     `ifdef STOP_COND
       if (`STOP_COND) begin
     `endif
         if (~reset & ~(~onehot_failed)) begin
-          $fatal; // @[Decode.scala 814:9]
+          $fatal; // @[Decode.scala 652:9]
         end
     `ifdef STOP_COND
       end
@@ -11646,7 +10800,7 @@
       if (`PRINTF_COND) begin
     `endif
         if (~reset & ~(~onehot_failed)) begin
-          $fwrite(32'h80000002,"Assertion failed\n    at Decode.scala:814 assert(!onehot_failed)\n"); // @[Decode.scala 814:9]
+          $fwrite(32'h80000002,"Assertion failed\n    at Decode.scala:652 assert(!onehot_failed)\n"); // @[Decode.scala 652:9]
         end
     `ifdef PRINTF_COND
       end
@@ -11658,7 +10812,7 @@
     `endif
         if (_T_6 & _T_2) begin
           $fwrite(32'h80000002,"[FAIL] decode  inst=%x  addr=%x  decoded=0b%b  pipeline=%d\n",io_inst,io_addr,decoded,2'h2
-            ); // @[Decode.scala 819:11]
+            ); // @[Decode.scala 657:11]
         end
     `ifdef PRINTF_COND
       end
@@ -11666,10 +10820,10 @@
     `endif // SYNTHESIS
   end
   always @(posedge clock or posedge reset) begin
-    if (reset) begin // @[Decode.scala 817:45]
-      onehot_failed <= 1'h0; // @[Decode.scala 818:19]
+    if (reset) begin // @[Decode.scala 655:45]
+      onehot_failed <= 1'h0; // @[Decode.scala 656:19]
     end else begin
-      onehot_failed <= _T_5 != 7'h1 | onehot_failed; // @[Decode.scala 813:30]
+      onehot_failed <= _T_5 != 7'h1 | onehot_failed; // @[Decode.scala 651:30]
     end
   end
 // Register and memory initialization
@@ -11733,7 +10887,6 @@
   input  [31:0] io_scoreboard_regd,
   input  [31:0] io_scoreboard_comb,
   output [31:0] io_scoreboard_spec,
-  input  [31:0] io_fscoreboard,
   output        io_rs1Read_valid,
   output [4:0]  io_rs1Read_addr,
   output        io_rs1Set_valid,
@@ -11748,7 +10901,7 @@
   output [31:0] io_busRead_immed,
   output        io_alu_valid,
   output [4:0]  io_alu_addr,
-  output [18:0] io_alu_op,
+  output [17:0] io_alu_op,
   output        io_bru_valid,
   output        io_bru_fwd,
   output [16:0] io_bru_op,
@@ -11759,18 +10912,16 @@
   output        io_lsu_valid,
   input         io_lsu_ready,
   output [4:0]  io_lsu_addr,
-  output [13:0] io_lsu_op,
+  output [11:0] io_lsu_op,
   output        io_mlu_valid,
   output [4:0]  io_mlu_addr,
   output [8:0]  io_mlu_op,
   output [3:0]  io_dvu_op,
-  output [4:0]  io_fpu_raddr_1,
-  output [26:0] io_fpu_op,
   output        io_vinst_valid,
   input         io_vinst_ready,
   output [4:0]  io_vinst_addr,
   output [31:0] io_vinst_inst,
-  output [5:0]  io_vinst_op,
+  output [4:0]  io_vinst_op,
   input         io_branchTaken,
   input         io_interlock,
   input         io_serializeIn_mul,
@@ -11780,172 +10931,136 @@
   output        io_serializeOut_jump,
   output        io_serializeOut_brcond
 );
-  wire  d_clock; // @[Decode.scala 91:17]
-  wire  d_reset; // @[Decode.scala 91:17]
-  wire [31:0] d_io_addr; // @[Decode.scala 91:17]
-  wire [31:0] d_io_inst; // @[Decode.scala 91:17]
-  wire [31:0] d_io_imm12; // @[Decode.scala 91:17]
-  wire [31:0] d_io_imm20; // @[Decode.scala 91:17]
-  wire [31:0] d_io_immjal; // @[Decode.scala 91:17]
-  wire [31:0] d_io_immbr; // @[Decode.scala 91:17]
-  wire [31:0] d_io_immst; // @[Decode.scala 91:17]
-  wire  d_io_lui; // @[Decode.scala 91:17]
-  wire  d_io_auipc; // @[Decode.scala 91:17]
-  wire  d_io_jal; // @[Decode.scala 91:17]
-  wire  d_io_jalr; // @[Decode.scala 91:17]
-  wire  d_io_beq; // @[Decode.scala 91:17]
-  wire  d_io_bne; // @[Decode.scala 91:17]
-  wire  d_io_blt; // @[Decode.scala 91:17]
-  wire  d_io_bge; // @[Decode.scala 91:17]
-  wire  d_io_bltu; // @[Decode.scala 91:17]
-  wire  d_io_bgeu; // @[Decode.scala 91:17]
-  wire  d_io_csrrw; // @[Decode.scala 91:17]
-  wire  d_io_csrrs; // @[Decode.scala 91:17]
-  wire  d_io_csrrc; // @[Decode.scala 91:17]
-  wire  d_io_lb; // @[Decode.scala 91:17]
-  wire  d_io_lh; // @[Decode.scala 91:17]
-  wire  d_io_lw; // @[Decode.scala 91:17]
-  wire  d_io_lbu; // @[Decode.scala 91:17]
-  wire  d_io_lhu; // @[Decode.scala 91:17]
-  wire  d_io_sb; // @[Decode.scala 91:17]
-  wire  d_io_sh; // @[Decode.scala 91:17]
-  wire  d_io_sw; // @[Decode.scala 91:17]
-  wire  d_io_fence; // @[Decode.scala 91:17]
-  wire  d_io_addi; // @[Decode.scala 91:17]
-  wire  d_io_slti; // @[Decode.scala 91:17]
-  wire  d_io_sltiu; // @[Decode.scala 91:17]
-  wire  d_io_xori; // @[Decode.scala 91:17]
-  wire  d_io_ori; // @[Decode.scala 91:17]
-  wire  d_io_andi; // @[Decode.scala 91:17]
-  wire  d_io_slli; // @[Decode.scala 91:17]
-  wire  d_io_srli; // @[Decode.scala 91:17]
-  wire  d_io_srai; // @[Decode.scala 91:17]
-  wire  d_io_add; // @[Decode.scala 91:17]
-  wire  d_io_sub; // @[Decode.scala 91:17]
-  wire  d_io_slt; // @[Decode.scala 91:17]
-  wire  d_io_sltu; // @[Decode.scala 91:17]
-  wire  d_io_xor; // @[Decode.scala 91:17]
-  wire  d_io_or; // @[Decode.scala 91:17]
-  wire  d_io_and; // @[Decode.scala 91:17]
-  wire  d_io_sll; // @[Decode.scala 91:17]
-  wire  d_io_srl; // @[Decode.scala 91:17]
-  wire  d_io_sra; // @[Decode.scala 91:17]
-  wire  d_io_mul; // @[Decode.scala 91:17]
-  wire  d_io_mulh; // @[Decode.scala 91:17]
-  wire  d_io_mulhsu; // @[Decode.scala 91:17]
-  wire  d_io_mulhu; // @[Decode.scala 91:17]
-  wire  d_io_mulhr; // @[Decode.scala 91:17]
-  wire  d_io_mulhsur; // @[Decode.scala 91:17]
-  wire  d_io_mulhur; // @[Decode.scala 91:17]
-  wire  d_io_dmulh; // @[Decode.scala 91:17]
-  wire  d_io_dmulhr; // @[Decode.scala 91:17]
-  wire  d_io_div; // @[Decode.scala 91:17]
-  wire  d_io_divu; // @[Decode.scala 91:17]
-  wire  d_io_rem; // @[Decode.scala 91:17]
-  wire  d_io_remu; // @[Decode.scala 91:17]
-  wire  d_io_flw; // @[Decode.scala 91:17]
-  wire  d_io_fsw; // @[Decode.scala 91:17]
-  wire  d_io_fmadd; // @[Decode.scala 91:17]
-  wire  d_io_fmsub; // @[Decode.scala 91:17]
-  wire  d_io_fnmsub; // @[Decode.scala 91:17]
-  wire  d_io_fnmadd; // @[Decode.scala 91:17]
-  wire  d_io_fadd; // @[Decode.scala 91:17]
-  wire  d_io_fsub; // @[Decode.scala 91:17]
-  wire  d_io_fmul; // @[Decode.scala 91:17]
-  wire  d_io_fdiv; // @[Decode.scala 91:17]
-  wire  d_io_fsqrt; // @[Decode.scala 91:17]
-  wire  d_io_fsgnj; // @[Decode.scala 91:17]
-  wire  d_io_fsgnjn; // @[Decode.scala 91:17]
-  wire  d_io_fsgnjx; // @[Decode.scala 91:17]
-  wire  d_io_fmin; // @[Decode.scala 91:17]
-  wire  d_io_fmax; // @[Decode.scala 91:17]
-  wire  d_io_fcvtws; // @[Decode.scala 91:17]
-  wire  d_io_fcvtwus; // @[Decode.scala 91:17]
-  wire  d_io_fmvxw; // @[Decode.scala 91:17]
-  wire  d_io_feq; // @[Decode.scala 91:17]
-  wire  d_io_flt; // @[Decode.scala 91:17]
-  wire  d_io_fle; // @[Decode.scala 91:17]
-  wire  d_io_fclass; // @[Decode.scala 91:17]
-  wire  d_io_fcvtsw; // @[Decode.scala 91:17]
-  wire  d_io_fcvtswu; // @[Decode.scala 91:17]
-  wire  d_io_fmvwx; // @[Decode.scala 91:17]
-  wire  d_io_clb; // @[Decode.scala 91:17]
-  wire  d_io_clz; // @[Decode.scala 91:17]
-  wire  d_io_ctz; // @[Decode.scala 91:17]
-  wire  d_io_pcnt; // @[Decode.scala 91:17]
-  wire  d_io_min; // @[Decode.scala 91:17]
-  wire  d_io_minu; // @[Decode.scala 91:17]
-  wire  d_io_max; // @[Decode.scala 91:17]
-  wire  d_io_maxu; // @[Decode.scala 91:17]
-  wire  d_io_getvl; // @[Decode.scala 91:17]
-  wire  d_io_getmaxvl; // @[Decode.scala 91:17]
-  wire  d_io_vld; // @[Decode.scala 91:17]
-  wire  d_io_vst; // @[Decode.scala 91:17]
-  wire  d_io_viop; // @[Decode.scala 91:17]
-  wire  d_io_vfop; // @[Decode.scala 91:17]
-  wire  d_io_ebreak; // @[Decode.scala 91:17]
-  wire  d_io_ecall; // @[Decode.scala 91:17]
-  wire  d_io_eexit; // @[Decode.scala 91:17]
-  wire  d_io_eyield; // @[Decode.scala 91:17]
-  wire  d_io_ectxsw; // @[Decode.scala 91:17]
-  wire  d_io_mpause; // @[Decode.scala 91:17]
-  wire  d_io_mret; // @[Decode.scala 91:17]
-  wire  d_io_undef; // @[Decode.scala 91:17]
-  wire  d_io_fencei; // @[Decode.scala 91:17]
-  wire  d_io_flushat; // @[Decode.scala 91:17]
-  wire  d_io_flushall; // @[Decode.scala 91:17]
-  wire  d_io_slog; // @[Decode.scala 91:17]
-  wire  decodeEn = io_inst_valid & io_inst_ready & ~io_branchTaken; // @[Decode.scala 88:49]
-  wire  vldst = d_io_vld | d_io_vst; // @[Decode.scala 95:24]
-  wire  vldst_wb = vldst & io_inst_inst[28]; // @[Decode.scala 96:24]
-  wire [4:0] rdAddr = vldst ? io_inst_inst[19:15] : io_inst_inst[11:7]; // @[Decode.scala 98:20]
-  wire [4:0] rs2Addr = io_inst_inst[24:20]; // @[Decode.scala 100:29]
-  wire [4:0] rs3Addr = io_inst_inst[31:27]; // @[Decode.scala 101:29]
-  wire  _isAluImm_T_3 = d_io_addi | d_io_slti | d_io_sltiu | d_io_xori | d_io_ori; // @[Decode.scala 103:68]
-  wire  isAluImm = _isAluImm_T_3 | d_io_andi | d_io_slli | d_io_srli | d_io_srai; // @[Decode.scala 104:66]
-  wire  _isAluReg_T_4 = d_io_add | d_io_sub | d_io_slt | d_io_sltu | d_io_xor | d_io_or; // @[Decode.scala 106:76]
-  wire  isAluReg = _isAluReg_T_4 | d_io_and | d_io_sll | d_io_srl | d_io_sra; // @[Decode.scala 107:62]
-  wire  isAlu1Bit = d_io_clb | d_io_clz | d_io_ctz | d_io_pcnt; // @[Decode.scala 109:52]
-  wire  isAlu2Bit = d_io_min | d_io_minu | d_io_max | d_io_maxu; // @[Decode.scala 110:53]
-  wire  _isCondBr_T_3 = d_io_beq | d_io_bne | d_io_blt | d_io_bge | d_io_bltu; // @[Decode.scala 112:63]
-  wire  isCondBr = _isCondBr_T_3 | d_io_bgeu; // @[Decode.scala 113:28]
-  wire  isLoad = d_io_lb | d_io_lh | d_io_lw | d_io_lbu | d_io_lhu; // @[Decode.scala 119:58]
-  wire  isStore = d_io_sb | d_io_sh | d_io_sw; // @[Decode.scala 120:36]
-  wire  isLsu = isLoad | isStore | d_io_vld | d_io_vst; // @[Decode.scala 121:69]
+  wire  d_clock; // @[Decode.scala 87:17]
+  wire  d_reset; // @[Decode.scala 87:17]
+  wire [31:0] d_io_addr; // @[Decode.scala 87:17]
+  wire [31:0] d_io_inst; // @[Decode.scala 87:17]
+  wire [31:0] d_io_imm12; // @[Decode.scala 87:17]
+  wire [31:0] d_io_imm20; // @[Decode.scala 87:17]
+  wire [31:0] d_io_immjal; // @[Decode.scala 87:17]
+  wire [31:0] d_io_immbr; // @[Decode.scala 87:17]
+  wire [31:0] d_io_immst; // @[Decode.scala 87:17]
+  wire  d_io_lui; // @[Decode.scala 87:17]
+  wire  d_io_auipc; // @[Decode.scala 87:17]
+  wire  d_io_jal; // @[Decode.scala 87:17]
+  wire  d_io_jalr; // @[Decode.scala 87:17]
+  wire  d_io_beq; // @[Decode.scala 87:17]
+  wire  d_io_bne; // @[Decode.scala 87:17]
+  wire  d_io_blt; // @[Decode.scala 87:17]
+  wire  d_io_bge; // @[Decode.scala 87:17]
+  wire  d_io_bltu; // @[Decode.scala 87:17]
+  wire  d_io_bgeu; // @[Decode.scala 87:17]
+  wire  d_io_csrrw; // @[Decode.scala 87:17]
+  wire  d_io_csrrs; // @[Decode.scala 87:17]
+  wire  d_io_csrrc; // @[Decode.scala 87:17]
+  wire  d_io_lb; // @[Decode.scala 87:17]
+  wire  d_io_lh; // @[Decode.scala 87:17]
+  wire  d_io_lw; // @[Decode.scala 87:17]
+  wire  d_io_lbu; // @[Decode.scala 87:17]
+  wire  d_io_lhu; // @[Decode.scala 87:17]
+  wire  d_io_sb; // @[Decode.scala 87:17]
+  wire  d_io_sh; // @[Decode.scala 87:17]
+  wire  d_io_sw; // @[Decode.scala 87:17]
+  wire  d_io_fence; // @[Decode.scala 87:17]
+  wire  d_io_addi; // @[Decode.scala 87:17]
+  wire  d_io_slti; // @[Decode.scala 87:17]
+  wire  d_io_sltiu; // @[Decode.scala 87:17]
+  wire  d_io_xori; // @[Decode.scala 87:17]
+  wire  d_io_ori; // @[Decode.scala 87:17]
+  wire  d_io_andi; // @[Decode.scala 87:17]
+  wire  d_io_slli; // @[Decode.scala 87:17]
+  wire  d_io_srli; // @[Decode.scala 87:17]
+  wire  d_io_srai; // @[Decode.scala 87:17]
+  wire  d_io_add; // @[Decode.scala 87:17]
+  wire  d_io_sub; // @[Decode.scala 87:17]
+  wire  d_io_slt; // @[Decode.scala 87:17]
+  wire  d_io_sltu; // @[Decode.scala 87:17]
+  wire  d_io_xor; // @[Decode.scala 87:17]
+  wire  d_io_or; // @[Decode.scala 87:17]
+  wire  d_io_and; // @[Decode.scala 87:17]
+  wire  d_io_sll; // @[Decode.scala 87:17]
+  wire  d_io_srl; // @[Decode.scala 87:17]
+  wire  d_io_sra; // @[Decode.scala 87:17]
+  wire  d_io_mul; // @[Decode.scala 87:17]
+  wire  d_io_mulh; // @[Decode.scala 87:17]
+  wire  d_io_mulhsu; // @[Decode.scala 87:17]
+  wire  d_io_mulhu; // @[Decode.scala 87:17]
+  wire  d_io_mulhr; // @[Decode.scala 87:17]
+  wire  d_io_mulhsur; // @[Decode.scala 87:17]
+  wire  d_io_mulhur; // @[Decode.scala 87:17]
+  wire  d_io_dmulh; // @[Decode.scala 87:17]
+  wire  d_io_dmulhr; // @[Decode.scala 87:17]
+  wire  d_io_div; // @[Decode.scala 87:17]
+  wire  d_io_divu; // @[Decode.scala 87:17]
+  wire  d_io_rem; // @[Decode.scala 87:17]
+  wire  d_io_remu; // @[Decode.scala 87:17]
+  wire  d_io_clz; // @[Decode.scala 87:17]
+  wire  d_io_ctz; // @[Decode.scala 87:17]
+  wire  d_io_pcnt; // @[Decode.scala 87:17]
+  wire  d_io_min; // @[Decode.scala 87:17]
+  wire  d_io_minu; // @[Decode.scala 87:17]
+  wire  d_io_max; // @[Decode.scala 87:17]
+  wire  d_io_maxu; // @[Decode.scala 87:17]
+  wire  d_io_getvl; // @[Decode.scala 87:17]
+  wire  d_io_getmaxvl; // @[Decode.scala 87:17]
+  wire  d_io_vld; // @[Decode.scala 87:17]
+  wire  d_io_vst; // @[Decode.scala 87:17]
+  wire  d_io_viop; // @[Decode.scala 87:17]
+  wire  d_io_ebreak; // @[Decode.scala 87:17]
+  wire  d_io_ecall; // @[Decode.scala 87:17]
+  wire  d_io_eexit; // @[Decode.scala 87:17]
+  wire  d_io_eyield; // @[Decode.scala 87:17]
+  wire  d_io_ectxsw; // @[Decode.scala 87:17]
+  wire  d_io_mpause; // @[Decode.scala 87:17]
+  wire  d_io_mret; // @[Decode.scala 87:17]
+  wire  d_io_undef; // @[Decode.scala 87:17]
+  wire  d_io_fencei; // @[Decode.scala 87:17]
+  wire  d_io_flushat; // @[Decode.scala 87:17]
+  wire  d_io_flushall; // @[Decode.scala 87:17]
+  wire  d_io_slog; // @[Decode.scala 87:17]
+  wire  decodeEn = io_inst_valid & io_inst_ready & ~io_branchTaken; // @[Decode.scala 84:49]
+  wire  vldst = d_io_vld | d_io_vst; // @[Decode.scala 91:24]
+  wire  vldst_wb = vldst & io_inst_inst[28]; // @[Decode.scala 92:24]
+  wire [4:0] rdAddr = vldst ? io_inst_inst[19:15] : io_inst_inst[11:7]; // @[Decode.scala 94:20]
+  wire [4:0] rs2Addr = io_inst_inst[24:20]; // @[Decode.scala 96:29]
+  wire [4:0] rs3Addr = io_inst_inst[31:27]; // @[Decode.scala 97:29]
+  wire  _isAluImm_T_3 = d_io_addi | d_io_slti | d_io_sltiu | d_io_xori | d_io_ori; // @[Decode.scala 99:68]
+  wire  isAluImm = _isAluImm_T_3 | d_io_andi | d_io_slli | d_io_srli | d_io_srai; // @[Decode.scala 100:66]
+  wire  _isAluReg_T_4 = d_io_add | d_io_sub | d_io_slt | d_io_sltu | d_io_xor | d_io_or; // @[Decode.scala 102:76]
+  wire  isAluReg = _isAluReg_T_4 | d_io_and | d_io_sll | d_io_srl | d_io_sra; // @[Decode.scala 103:62]
+  wire  isAlu1Bit = d_io_clz | d_io_ctz | d_io_pcnt; // @[Decode.scala 105:40]
+  wire  isAlu2Bit = d_io_min | d_io_minu | d_io_max | d_io_maxu; // @[Decode.scala 106:53]
+  wire  _isCondBr_T_3 = d_io_beq | d_io_bne | d_io_blt | d_io_bge | d_io_bltu; // @[Decode.scala 108:63]
+  wire  isCondBr = _isCondBr_T_3 | d_io_bgeu; // @[Decode.scala 109:28]
+  wire  isLoad = d_io_lb | d_io_lh | d_io_lw | d_io_lbu | d_io_lhu; // @[Decode.scala 115:58]
+  wire  isStore = d_io_sb | d_io_sh | d_io_sw; // @[Decode.scala 116:36]
+  wire  isLsu = isLoad | isStore | d_io_vld | d_io_vst; // @[Decode.scala 117:45]
   wire  isMul = d_io_mul | d_io_mulh | d_io_mulhsu | d_io_mulhu | d_io_mulhr | d_io_mulhsur | d_io_mulhur | d_io_dmulh
-     | d_io_dmulhr; // @[Decode.scala 123:125]
-  wire  fpuRs2 = d_io_vfop & io_inst_inst[1]; // @[Decode.scala 129:255]
-  wire  isVFop = io_vinst_op[5]; // @[Decode.scala 133:27]
-  wire  isVIop = io_vinst_op[4]; // @[Decode.scala 134:27]
-  wire  isVIopVs2 = isVIop & io_inst_inst[1:0] == 2'h0; // @[Decode.scala 137:26]
-  wire [31:0] _aluRdEn_T = io_scoreboard_comb >> rdAddr; // @[Decode.scala 141:37]
-  wire  aluRdEn = ~_aluRdEn_T[0] | isVIop | isStore | isCondBr | fpuRs2; // @[Decode.scala 141:83]
-  wire [31:0] _aluRs1En_T = io_scoreboard_comb >> io_inst_inst[19:15]; // @[Decode.scala 142:37]
-  wire  aluRs1En = ~_aluRs1En_T[0] | isVIop | isLsu | d_io_auipc | isVFop | fpuRs2; // @[Decode.scala 142:93]
-  wire [31:0] _aluRs2En_T = io_scoreboard_comb >> rs2Addr; // @[Decode.scala 143:37]
-  wire  aluRs2En = ~_aluRs2En_T[0] | isVIopVs2 | isLsu | d_io_auipc | isVFop | isAluImm | isAlu1Bit | fpuRs2; // @[Decode.scala 143:118]
-  wire  aluEn = aluRdEn & aluRs1En & aluRs2En; // @[Decode.scala 146:35]
-  wire [31:0] _bruEn_T_1 = io_scoreboard_regd >> io_inst_inst[19:15]; // @[Decode.scala 149:48]
-  wire  _bruEn_T_6 = io_inst_inst[31:20] == 12'h0; // @[Decode.scala 150:35]
-  wire  bruEn = ~d_io_jalr | ~_bruEn_T_1[0] | _bruEn_T_6; // @[Decode.scala 149:58]
-  wire  _lsuEn_T = ~isLsu; // @[Decode.scala 153:15]
-  wire  _lsuEn_T_5 = _lsuEn_T | ~io_serializeIn_brcond; // @[Decode.scala 155:23]
-  wire  _lsuEn_T_6 = io_lsu_ready & _lsuEn_T_5; // @[Decode.scala 154:51]
-  wire  _lsuEn_T_11 = io_busRead_bypass ? _aluRs1En_T[0] : _bruEn_T_1[0]; // @[Decode.scala 156:20]
-  wire  _lsuEn_T_15 = _aluRs2En_T[0] & (isStore | vldst); // @[Decode.scala 158:49]
-  wire  _lsuEn_T_16 = _lsuEn_T_11 | _lsuEn_T_15; // @[Decode.scala 157:50]
-  wire  _lsuEn_T_17 = ~_lsuEn_T_16; // @[Decode.scala 156:15]
-  wire  _lsuEn_T_18 = _lsuEn_T_6 & _lsuEn_T_17; // @[Decode.scala 155:50]
-  wire  lsuEn = ~isLsu | _lsuEn_T_18; // @[Decode.scala 153:22]
-  wire  mulEn = ~isMul | ~io_serializeIn_mul; // @[Decode.scala 161:22]
-  wire [31:0] _fpuEn_T_8 = io_fscoreboard >> rs2Addr; // @[Decode.scala 166:53]
-  wire  _fpuEn_T_10 = fpuRs2 & _fpuEn_T_8[0]; // @[Decode.scala 166:36]
-  wire  fpuEn = ~fpuRs2 | ~_fpuEn_T_10; // @[Decode.scala 164:24]
-  wire  _vinstEn_T_5 = ~(isVFop & io_serializeIn_brcond); // @[Decode.scala 173:17]
-  wire  _vinstEn_T_6 = ~(isVIop & io_serializeIn_brcond) & _vinstEn_T_5; // @[Decode.scala 172:76]
-  wire  _vinstEn_T_10 = ~(io_vinst_op != 6'h0 & ~io_vinst_ready); // @[Decode.scala 174:17]
-  wire  vinstEn = _vinstEn_T_6 & _vinstEn_T_10; // @[Decode.scala 173:76]
-  wire  aluValid_value__9 = io_alu_op[18]; // @[Library.scala 182:26]
+     | d_io_dmulhr; // @[Decode.scala 119:125]
+  wire  isVIop = io_vinst_op[4]; // @[Decode.scala 123:27]
+  wire  isVIopVs2 = isVIop & io_inst_inst[1:0] == 2'h0; // @[Decode.scala 126:26]
+  wire [31:0] _aluRdEn_T = io_scoreboard_comb >> rdAddr; // @[Decode.scala 130:37]
+  wire  aluRdEn = ~_aluRdEn_T[0] | isVIop | isStore | isCondBr; // @[Decode.scala 130:71]
+  wire [31:0] _aluRs1En_T = io_scoreboard_comb >> io_inst_inst[19:15]; // @[Decode.scala 131:37]
+  wire  aluRs1En = ~_aluRs1En_T[0] | isVIop | isLsu | d_io_auipc; // @[Decode.scala 131:69]
+  wire [31:0] _aluRs2En_T = io_scoreboard_comb >> rs2Addr; // @[Decode.scala 132:37]
+  wire  aluRs2En = ~_aluRs2En_T[0] | isVIopVs2 | isLsu | d_io_auipc | isAluImm | isAlu1Bit; // @[Decode.scala 132:95]
+  wire  aluEn = aluRdEn & aluRs1En & aluRs2En; // @[Decode.scala 135:35]
+  wire [31:0] _bruEn_T_1 = io_scoreboard_regd >> io_inst_inst[19:15]; // @[Decode.scala 138:48]
+  wire  _bruEn_T_6 = io_inst_inst[31:20] == 12'h0; // @[Decode.scala 139:35]
+  wire  bruEn = ~d_io_jalr | ~_bruEn_T_1[0] | _bruEn_T_6; // @[Decode.scala 138:58]
+  wire  _lsuEn_T = ~isLsu; // @[Decode.scala 142:15]
+  wire  _lsuEn_T_5 = _lsuEn_T | ~io_serializeIn_brcond; // @[Decode.scala 144:23]
+  wire  _lsuEn_T_6 = io_lsu_ready & _lsuEn_T_5; // @[Decode.scala 143:51]
+  wire  _lsuEn_T_11 = io_busRead_bypass ? _aluRs1En_T[0] : _bruEn_T_1[0]; // @[Decode.scala 145:20]
+  wire  _lsuEn_T_15 = _aluRs2En_T[0] & (isStore | vldst); // @[Decode.scala 147:49]
+  wire  _lsuEn_T_16 = _lsuEn_T_11 | _lsuEn_T_15; // @[Decode.scala 146:50]
+  wire  _lsuEn_T_17 = ~_lsuEn_T_16; // @[Decode.scala 145:15]
+  wire  _lsuEn_T_18 = _lsuEn_T_6 & _lsuEn_T_17; // @[Decode.scala 144:50]
+  wire  lsuEn = ~isLsu | _lsuEn_T_18; // @[Decode.scala 142:22]
+  wire  mulEn = ~isMul | ~io_serializeIn_mul; // @[Decode.scala 150:22]
+  wire  _vinstEn_T_6 = ~(io_vinst_op != 5'h0 & ~io_vinst_ready); // @[Decode.scala 155:17]
+  wire  vinstEn = ~(isVIop & io_serializeIn_brcond) & _vinstEn_T_6; // @[Decode.scala 154:76]
   wire  aluValid_value__0 = io_alu_op[0] | io_alu_op[1]; // @[Library.scala 194:39]
   wire  aluValid_value__1 = io_alu_op[2] | io_alu_op[3]; // @[Library.scala 194:39]
   wire  aluValid_value__2 = io_alu_op[4] | io_alu_op[5]; // @[Library.scala 194:39]
@@ -11959,32 +11074,30 @@
   wire  aluValid_value_1_1 = aluValid_value__2 | aluValid_value__3; // @[Library.scala 194:39]
   wire  aluValid_value_1_2 = aluValid_value__4 | aluValid_value__5; // @[Library.scala 194:39]
   wire  aluValid_value_1_3 = aluValid_value__6 | aluValid_value__7; // @[Library.scala 194:39]
-  wire  aluValid_value_1_4 = aluValid_value__8 | aluValid_value__9; // @[Library.scala 194:39]
   wire  aluValid_value_2_0 = aluValid_value_1_0 | aluValid_value_1_1; // @[Library.scala 194:39]
   wire  aluValid_value_2_1 = aluValid_value_1_2 | aluValid_value_1_3; // @[Library.scala 194:39]
   wire  aluValid_value_3_0 = aluValid_value_2_0 | aluValid_value_2_1; // @[Library.scala 194:39]
-  wire  aluValid_value_4_0 = aluValid_value_3_0 | aluValid_value_1_4; // @[Library.scala 194:39]
-  wire  aluOp_1 = d_io_sub; // @[Decode.scala 182:19 189:19]
-  wire  aluOp_0 = d_io_auipc | d_io_addi | d_io_add; // @[Decode.scala 188:46]
-  wire  aluOp_3 = d_io_sltiu | d_io_sltu; // @[Decode.scala 191:33]
-  wire  aluOp_2 = d_io_slti | d_io_slt; // @[Decode.scala 190:32]
-  wire  aluOp_5 = d_io_ori | d_io_or; // @[Decode.scala 193:31]
-  wire  aluOp_4 = d_io_xori | d_io_xor; // @[Decode.scala 192:32]
-  wire  aluOp_8 = d_io_srli | d_io_srl; // @[Decode.scala 196:32]
-  wire  aluOp_7 = d_io_slli | d_io_sll; // @[Decode.scala 195:32]
-  wire  aluOp_6 = d_io_andi | d_io_and; // @[Decode.scala 194:32]
-  wire [8:0] io_alu_op_lo = {aluOp_8,aluOp_7,aluOp_6,aluOp_5,aluOp_4,aluOp_3,aluOp_2,aluOp_1,aluOp_0}; // @[Decode.scala 186:22]
-  wire  aluOp_10 = d_io_lui; // @[Decode.scala 182:19 198:19]
-  wire  aluOp_9 = d_io_srai | d_io_sra; // @[Decode.scala 197:32]
-  wire  aluOp_13 = d_io_ctz; // @[Decode.scala 182:19 201:19]
-  wire  aluOp_12 = d_io_clz; // @[Decode.scala 182:19 200:19]
-  wire  aluOp_11 = d_io_clb; // @[Decode.scala 182:19 199:19]
-  wire  aluOp_15 = d_io_min; // @[Decode.scala 182:19 203:19]
-  wire  aluOp_14 = d_io_pcnt; // @[Decode.scala 182:19 202:19]
-  wire  aluOp_18 = d_io_maxu; // @[Decode.scala 182:19 206:19]
-  wire  aluOp_17 = d_io_max; // @[Decode.scala 182:19 205:19]
-  wire  aluOp_16 = d_io_minu; // @[Decode.scala 182:19 204:19]
-  wire [9:0] io_alu_op_hi = {aluOp_18,aluOp_17,aluOp_16,aluOp_15,aluOp_14,aluOp_13,aluOp_12,aluOp_11,aluOp_10,aluOp_9}; // @[Decode.scala 186:22]
+  wire  aluValid_value_4_0 = aluValid_value_3_0 | aluValid_value__8; // @[Library.scala 194:39]
+  wire  aluOp_1 = d_io_sub; // @[Decode.scala 163:19 170:19]
+  wire  aluOp_0 = d_io_auipc | d_io_addi | d_io_add; // @[Decode.scala 169:46]
+  wire  aluOp_3 = d_io_sltiu | d_io_sltu; // @[Decode.scala 172:33]
+  wire  aluOp_2 = d_io_slti | d_io_slt; // @[Decode.scala 171:32]
+  wire  aluOp_5 = d_io_ori | d_io_or; // @[Decode.scala 174:31]
+  wire  aluOp_4 = d_io_xori | d_io_xor; // @[Decode.scala 173:32]
+  wire  aluOp_8 = d_io_srli | d_io_srl; // @[Decode.scala 177:32]
+  wire  aluOp_7 = d_io_slli | d_io_sll; // @[Decode.scala 176:32]
+  wire  aluOp_6 = d_io_andi | d_io_and; // @[Decode.scala 175:32]
+  wire [8:0] io_alu_op_lo = {aluOp_8,aluOp_7,aluOp_6,aluOp_5,aluOp_4,aluOp_3,aluOp_2,aluOp_1,aluOp_0}; // @[Decode.scala 167:22]
+  wire  aluOp_10 = d_io_lui; // @[Decode.scala 163:19 179:19]
+  wire  aluOp_9 = d_io_srai | d_io_sra; // @[Decode.scala 178:32]
+  wire  aluOp_12 = d_io_ctz; // @[Decode.scala 163:19 181:19]
+  wire  aluOp_11 = d_io_clz; // @[Decode.scala 163:19 180:19]
+  wire  aluOp_14 = d_io_min; // @[Decode.scala 163:19 183:19]
+  wire  aluOp_13 = d_io_pcnt; // @[Decode.scala 163:19 182:19]
+  wire  aluOp_17 = d_io_maxu; // @[Decode.scala 163:19 186:19]
+  wire  aluOp_16 = d_io_max; // @[Decode.scala 163:19 185:19]
+  wire  aluOp_15 = d_io_minu; // @[Decode.scala 163:19 184:19]
+  wire [8:0] io_alu_op_hi = {aluOp_17,aluOp_16,aluOp_15,aluOp_14,aluOp_13,aluOp_12,aluOp_11,aluOp_10,aluOp_9}; // @[Decode.scala 167:22]
   wire  bruValid_value__8 = io_bru_op[16]; // @[Library.scala 182:26]
   wire  bruValid_value__0 = io_bru_op[0] | io_bru_op[1]; // @[Library.scala 194:39]
   wire  bruValid_value__1 = io_bru_op[2] | io_bru_op[3]; // @[Library.scala 194:39]
@@ -12002,18 +11115,18 @@
   wire  bruValid_value_2_1 = bruValid_value_1_2 | bruValid_value_1_3; // @[Library.scala 194:39]
   wire  bruValid_value_3_0 = bruValid_value_2_0 | bruValid_value_2_1; // @[Library.scala 194:39]
   wire  bruValid_value_4_0 = bruValid_value_3_0 | bruValid_value__8; // @[Library.scala 194:39]
-  wire  bruOp_1 = d_io_jalr; // @[Decode.scala 210:19 220:19]
-  wire  bruOp_0 = d_io_jal; // @[Decode.scala 210:19 219:19]
-  wire  bruOp_3 = d_io_bne; // @[Decode.scala 210:19 222:19]
-  wire  bruOp_2 = d_io_beq; // @[Decode.scala 210:19 221:19]
-  wire  bruOp_5 = d_io_bge; // @[Decode.scala 210:19 224:19]
-  wire  bruOp_4 = d_io_blt; // @[Decode.scala 210:19 223:19]
-  wire  bruOp_7 = d_io_bgeu; // @[Decode.scala 210:19 226:19]
-  wire  bruOp_6 = d_io_bltu; // @[Decode.scala 210:19 225:19]
-  wire [7:0] io_bru_op_lo = {bruOp_7,bruOp_6,bruOp_5,bruOp_4,bruOp_3,bruOp_2,bruOp_1,bruOp_0}; // @[Decode.scala 214:22]
-  wire  bruOp_16 = d_io_undef; // @[Decode.scala 210:19 235:21]
-  wire [8:0] io_bru_op_hi = {bruOp_16,1'h0,1'h0,2'h0,4'h0}; // @[Decode.scala 214:22]
-  wire [31:0] _io_bru_target_T_1 = io_inst_inst[2] ? d_io_immjal : d_io_immbr; // @[Decode.scala 216:38]
+  wire  bruOp_1 = d_io_jalr; // @[Decode.scala 190:19 200:19]
+  wire  bruOp_0 = d_io_jal; // @[Decode.scala 190:19 199:19]
+  wire  bruOp_3 = d_io_bne; // @[Decode.scala 190:19 202:19]
+  wire  bruOp_2 = d_io_beq; // @[Decode.scala 190:19 201:19]
+  wire  bruOp_5 = d_io_bge; // @[Decode.scala 190:19 204:19]
+  wire  bruOp_4 = d_io_blt; // @[Decode.scala 190:19 203:19]
+  wire  bruOp_7 = d_io_bgeu; // @[Decode.scala 190:19 206:19]
+  wire  bruOp_6 = d_io_bltu; // @[Decode.scala 190:19 205:19]
+  wire [7:0] io_bru_op_lo = {bruOp_7,bruOp_6,bruOp_5,bruOp_4,bruOp_3,bruOp_2,bruOp_1,bruOp_0}; // @[Decode.scala 194:22]
+  wire  bruOp_16 = d_io_undef; // @[Decode.scala 190:19 215:21]
+  wire [8:0] io_bru_op_hi = {bruOp_16,1'h0,1'h0,2'h0,4'h0}; // @[Decode.scala 194:22]
+  wire [31:0] _io_bru_target_T_1 = io_inst_inst[2] ? d_io_immjal : d_io_immbr; // @[Decode.scala 196:38]
   wire  csrValid_value__1 = io_csr_op[2]; // @[Library.scala 182:26]
   wire  csrValid_value__0 = io_csr_op[0] | io_csr_op[1]; // @[Library.scala 194:39]
   wire  csrValid_value_1_0 = csrValid_value__0 | csrValid_value__1; // @[Library.scala 194:39]
@@ -12023,23 +11136,21 @@
   wire  lsuValid_value__3 = io_lsu_op[6] | io_lsu_op[7]; // @[Library.scala 194:39]
   wire  lsuValid_value__4 = io_lsu_op[8] | io_lsu_op[9]; // @[Library.scala 194:39]
   wire  lsuValid_value__5 = io_lsu_op[10] | io_lsu_op[11]; // @[Library.scala 194:39]
-  wire  lsuValid_value__6 = io_lsu_op[12] | io_lsu_op[13]; // @[Library.scala 194:39]
   wire  lsuValid_value_1_0 = lsuValid_value__0 | lsuValid_value__1; // @[Library.scala 194:39]
   wire  lsuValid_value_1_1 = lsuValid_value__2 | lsuValid_value__3; // @[Library.scala 194:39]
   wire  lsuValid_value_1_2 = lsuValid_value__4 | lsuValid_value__5; // @[Library.scala 194:39]
   wire  lsuValid_value_2_0 = lsuValid_value_1_0 | lsuValid_value_1_1; // @[Library.scala 194:39]
-  wire  lsuValid_value_2_1 = lsuValid_value_1_2 | lsuValid_value__6; // @[Library.scala 194:39]
-  wire  lsuValid_value_3_0 = lsuValid_value_2_0 | lsuValid_value_2_1; // @[Library.scala 194:39]
-  wire  lsuOp_2 = d_io_lw; // @[Decode.scala 252:19 261:18]
-  wire  lsuOp_1 = d_io_lh; // @[Decode.scala 252:19 260:18]
-  wire  lsuOp_0 = d_io_lb; // @[Decode.scala 252:19 259:18]
-  wire  lsuOp_4 = d_io_lhu; // @[Decode.scala 252:19 263:18]
-  wire  lsuOp_3 = d_io_lbu; // @[Decode.scala 252:19 262:18]
-  wire  lsuOp_6 = d_io_sh; // @[Decode.scala 252:19 265:18]
-  wire  lsuOp_5 = d_io_sb; // @[Decode.scala 252:19 264:18]
-  wire [6:0] io_lsu_op_lo = {lsuOp_6,lsuOp_5,lsuOp_4,lsuOp_3,lsuOp_2,lsuOp_1,lsuOp_0}; // @[Decode.scala 257:22]
-  wire  lsuOp_7 = d_io_sw; // @[Decode.scala 252:19 266:18]
-  wire [6:0] io_lsu_op_hi = {vldst,1'h0,2'h0,2'h0,lsuOp_7}; // @[Decode.scala 257:22]
+  wire  lsuValid_value_3_0 = lsuValid_value_2_0 | lsuValid_value_1_2; // @[Library.scala 194:39]
+  wire  lsuOp_2 = d_io_lw; // @[Decode.scala 232:19 241:18]
+  wire  lsuOp_1 = d_io_lh; // @[Decode.scala 232:19 240:18]
+  wire  lsuOp_0 = d_io_lb; // @[Decode.scala 232:19 239:18]
+  wire  lsuOp_5 = d_io_sb; // @[Decode.scala 232:19 244:18]
+  wire  lsuOp_4 = d_io_lhu; // @[Decode.scala 232:19 243:18]
+  wire  lsuOp_3 = d_io_lbu; // @[Decode.scala 232:19 242:18]
+  wire [5:0] io_lsu_op_lo = {lsuOp_5,lsuOp_4,lsuOp_3,lsuOp_2,lsuOp_1,lsuOp_0}; // @[Decode.scala 237:22]
+  wire  lsuOp_7 = d_io_sw; // @[Decode.scala 232:19 246:18]
+  wire  lsuOp_6 = d_io_sh; // @[Decode.scala 232:19 245:18]
+  wire [5:0] io_lsu_op_hi = {vldst,1'h0,1'h0,1'h0,lsuOp_7,lsuOp_6}; // @[Decode.scala 237:22]
   wire  mluValid_value__4 = io_mlu_op[8]; // @[Library.scala 182:26]
   wire  mluValid_value__0 = io_mlu_op[0] | io_mlu_op[1]; // @[Library.scala 194:39]
   wire  mluValid_value__1 = io_mlu_op[2] | io_mlu_op[3]; // @[Library.scala 194:39]
@@ -12049,60 +11160,56 @@
   wire  mluValid_value_1_1 = mluValid_value__2 | mluValid_value__3; // @[Library.scala 194:39]
   wire  mluValid_value_2_0 = mluValid_value_1_0 | mluValid_value_1_1; // @[Library.scala 194:39]
   wire  mluValid_value_3_0 = mluValid_value_2_0 | mluValid_value__4; // @[Library.scala 194:39]
-  wire  mluOp_1 = d_io_mulh; // @[Decode.scala 276:19 283:22]
-  wire  mluOp_0 = d_io_mul; // @[Decode.scala 276:19 282:22]
-  wire  mluOp_3 = d_io_mulhu; // @[Decode.scala 276:19 285:22]
-  wire  mluOp_2 = d_io_mulhsu; // @[Decode.scala 276:19 284:22]
-  wire [3:0] io_mlu_op_lo = {mluOp_3,mluOp_2,mluOp_1,mluOp_0}; // @[Decode.scala 280:22]
-  wire  mluOp_5 = d_io_mulhsur; // @[Decode.scala 276:19 287:22]
-  wire  mluOp_4 = d_io_mulhr; // @[Decode.scala 276:19 286:22]
-  wire  mluOp_8 = d_io_dmulhr; // @[Decode.scala 276:19 290:22]
-  wire  mluOp_7 = d_io_dmulh; // @[Decode.scala 276:19 289:22]
-  wire  mluOp_6 = d_io_mulhur; // @[Decode.scala 276:19 288:22]
-  wire [4:0] io_mlu_op_hi = {mluOp_8,mluOp_7,mluOp_6,mluOp_5,mluOp_4}; // @[Decode.scala 280:22]
+  wire  mluOp_1 = d_io_mulh; // @[Decode.scala 255:19 262:22]
+  wire  mluOp_0 = d_io_mul; // @[Decode.scala 255:19 261:22]
+  wire  mluOp_3 = d_io_mulhu; // @[Decode.scala 255:19 264:22]
+  wire  mluOp_2 = d_io_mulhsu; // @[Decode.scala 255:19 263:22]
+  wire [3:0] io_mlu_op_lo = {mluOp_3,mluOp_2,mluOp_1,mluOp_0}; // @[Decode.scala 259:22]
+  wire  mluOp_5 = d_io_mulhsur; // @[Decode.scala 255:19 266:22]
+  wire  mluOp_4 = d_io_mulhr; // @[Decode.scala 255:19 265:22]
+  wire  mluOp_8 = d_io_dmulhr; // @[Decode.scala 255:19 269:22]
+  wire  mluOp_7 = d_io_dmulh; // @[Decode.scala 255:19 268:22]
+  wire  mluOp_6 = d_io_mulhur; // @[Decode.scala 255:19 267:22]
+  wire [4:0] io_mlu_op_hi = {mluOp_8,mluOp_7,mluOp_6,mluOp_5,mluOp_4}; // @[Decode.scala 259:22]
   wire  dvuValid_value__0 = io_dvu_op[0] | io_dvu_op[1]; // @[Library.scala 194:39]
   wire  dvuValid_value__1 = io_dvu_op[2] | io_dvu_op[3]; // @[Library.scala 194:39]
   wire  dvuValid_value_1_0 = dvuValid_value__0 | dvuValid_value__1; // @[Library.scala 194:39]
-  wire  dvuEn = ~dvuValid_value_1_0; // @[Decode.scala 305:34]
-  wire [13:0] io_fpu_op_hi = {fpuRs2,1'h0,2'h0,3'h0,7'h0}; // @[Decode.scala 313:22]
-  wire  vinstOp_0 = d_io_getvl; // @[Decode.scala 349:21 361:24]
-  wire  vinstOp_1 = d_io_getmaxvl; // @[Decode.scala 349:21 362:27]
+  wire  dvuEn = ~dvuValid_value_1_0; // @[Decode.scala 284:34]
+  wire  vinstOp_0 = d_io_getvl; // @[Decode.scala 288:21 299:24]
+  wire  vinstOp_1 = d_io_getmaxvl; // @[Decode.scala 288:21 300:27]
   wire  vinstValid_value__0 = vinstOp_0 | vinstOp_1; // @[Library.scala 194:39]
-  wire  vinstOp_2 = d_io_vld; // @[Decode.scala 349:21 357:22]
-  wire  vinstOp_3 = d_io_vst; // @[Decode.scala 349:21 358:22]
+  wire  vinstOp_2 = d_io_vld; // @[Decode.scala 288:21 296:22]
+  wire  vinstOp_3 = d_io_vst; // @[Decode.scala 288:21 297:22]
   wire  vinstValid_value__1 = vinstOp_2 | vinstOp_3; // @[Library.scala 194:39]
-  wire  vinstOp_4 = d_io_viop; // @[Decode.scala 349:21 359:23]
-  wire  vinstOp_5 = d_io_vfop; // @[Decode.scala 349:21 360:23]
-  wire  vinstValid_value__2 = vinstOp_4 | vinstOp_5; // @[Library.scala 194:39]
   wire  vinstValid_value_1_0 = vinstValid_value__0 | vinstValid_value__1; // @[Library.scala 194:39]
-  wire  vinstValid_value_2_0 = vinstValid_value_1_0 | vinstValid_value__2; // @[Library.scala 194:39]
-  wire [2:0] io_vinst_op_lo = {vinstOp_2,vinstOp_1,vinstOp_0}; // @[Decode.scala 355:26]
-  wire [2:0] io_vinst_op_hi = {vinstOp_5,vinstOp_4,vinstOp_3}; // @[Decode.scala 355:26]
-  wire  _io_rs1Read_valid_T = isCondBr | isAluReg; // @[Decode.scala 368:45]
-  wire  _io_rs1Read_valid_T_3 = isCondBr | isAluReg | isAluImm | isAlu1Bit | isAlu2Bit; // @[Decode.scala 368:82]
-  wire  _io_rs1Read_valid_T_6 = _io_rs1Read_valid_T_3 | isMul; // @[Decode.scala 369:44]
-  wire  _io_rs1Read_valid_T_13 = _io_rs1Read_valid_T_6 | d_io_getvl | d_io_vld; // @[Decode.scala 370:79]
-  wire  _io_rs1Read_valid_T_14 = _io_rs1Read_valid_T_13 | d_io_vst; // @[Decode.scala 371:32]
-  wire  _io_rs2Read_valid_T_2 = _io_rs1Read_valid_T | isAlu2Bit | isStore; // @[Decode.scala 372:70]
-  wire  _io_rs2Read_valid_T_8 = _io_rs2Read_valid_T_2 | isMul | d_io_getvl | d_io_vld; // @[Decode.scala 373:77]
-  wire  _io_rs2Read_valid_T_10 = _io_rs2Read_valid_T_8 | d_io_vst | d_io_viop; // @[Decode.scala 374:44]
-  wire  _io_rs2Set_value_T = d_io_auipc | d_io_lui; // @[Decode.scala 389:45]
-  wire  _rdMark_valid_T_4 = lsuValid_value_3_0 & isLoad; // @[Decode.scala 395:16]
-  wire  _rdMark_valid_T_5 = aluValid_value_4_0 | csrValid_value_1_0 | mluValid_value_3_0 | _rdMark_valid_T_4; // @[Decode.scala 394:68]
-  wire  _rdMark_valid_T_13 = _rdMark_valid_T_5 | d_io_getvl; // @[Decode.scala 396:55]
-  wire  _rdMark_valid_T_19 = bruValid_value_4_0 & (bruOp_0 | bruOp_1) & rdAddr != 5'h0; // @[Decode.scala 398:55]
-  wire  rdMark_valid = _rdMark_valid_T_13 | d_io_getmaxvl | vldst_wb | _rdMark_valid_T_19; // @[Decode.scala 397:47]
+  wire  vinstOp_4 = d_io_viop; // @[Decode.scala 288:21 298:23]
+  wire  vinstValid_value_2_0 = vinstValid_value_1_0 | vinstOp_4; // @[Library.scala 194:39]
+  wire [1:0] io_vinst_op_lo = {vinstOp_1,vinstOp_0}; // @[Decode.scala 294:26]
+  wire [2:0] io_vinst_op_hi = {vinstOp_4,vinstOp_3,vinstOp_2}; // @[Decode.scala 294:26]
+  wire  _io_rs1Read_valid_T = isCondBr | isAluReg; // @[Decode.scala 306:45]
+  wire  _io_rs1Read_valid_T_3 = isCondBr | isAluReg | isAluImm | isAlu1Bit | isAlu2Bit; // @[Decode.scala 306:82]
+  wire  _io_rs1Read_valid_T_9 = _io_rs1Read_valid_T_3 | isMul | d_io_getvl; // @[Decode.scala 307:75]
+  wire  _io_rs1Read_valid_T_11 = _io_rs1Read_valid_T_9 | d_io_vld | d_io_vst; // @[Decode.scala 308:46]
+  wire  _io_rs2Read_valid_T_2 = _io_rs1Read_valid_T | isAlu2Bit | isStore; // @[Decode.scala 309:70]
+  wire  _io_rs2Read_valid_T_8 = _io_rs2Read_valid_T_2 | isMul | d_io_getvl | d_io_vld; // @[Decode.scala 310:77]
+  wire  _io_rs2Read_valid_T_10 = _io_rs2Read_valid_T_8 | d_io_vst | d_io_viop; // @[Decode.scala 311:44]
+  wire  _io_rs2Set_value_T = d_io_auipc | d_io_lui; // @[Decode.scala 326:45]
+  wire  _rdMark_valid_T_4 = lsuValid_value_3_0 & isLoad; // @[Decode.scala 332:16]
+  wire  _rdMark_valid_T_5 = aluValid_value_4_0 | csrValid_value_1_0 | mluValid_value_3_0 | _rdMark_valid_T_4; // @[Decode.scala 331:68]
+  wire  _rdMark_valid_T_6 = _rdMark_valid_T_5 | d_io_getvl; // @[Decode.scala 332:26]
+  wire  _rdMark_valid_T_12 = bruValid_value_4_0 & (bruOp_0 | bruOp_1) & rdAddr != 5'h0; // @[Decode.scala 334:55]
+  wire  rdMark_valid = _rdMark_valid_T_6 | d_io_getmaxvl | vldst_wb | _rdMark_valid_T_12; // @[Decode.scala 333:47]
   wire [31:0] _scoreboard_spec_T = 32'h1 << rdAddr; // @[OneHot.scala 64:12]
-  wire [31:0] scoreboard_spec = rdMark_valid ? _scoreboard_spec_T : 32'h0; // @[Decode.scala 401:28]
-  wire  _io_busRead_bypass_T_9 = io_inst_inst[11:7] == 5'h0; // @[Decode.scala 413:65]
-  wire  _io_busRead_bypass_T_10 = ~io_inst_inst[5] | io_inst_inst[6] ? rs2Addr == 5'h0 : _io_busRead_bypass_T_9; // @[Decode.scala 412:8]
-  wire  storeSelect = io_inst_inst[6:3] == 4'h4 & io_inst_inst[1:0] == 2'h3; // @[Decode.scala 417:47]
-  wire [4:0] _io_busRead_immed_T_3 = storeSelect ? d_io_immst[4:0] : d_io_imm12[4:0]; // @[Decode.scala 420:30]
-  wire  _io_inst_ready_T_7 = ~io_serializeIn_jump; // @[Decode.scala 426:20]
-  wire  _io_inst_ready_T_8 = aluEn & bruEn & lsuEn & mulEn & dvuEn & fpuEn & vinstEn & _io_inst_ready_T_7; // @[Decode.scala 425:93]
-  wire  _io_inst_ready_T_14 = ~d_io_undef; // @[Decode.scala 427:43]
-  wire  _io_serializeOut_brcond_T = io_serializeIn_brcond | d_io_beq; // @[Decode.scala 437:51]
-  DecodedInstruction_2 d ( // @[Decode.scala 91:17]
+  wire [31:0] scoreboard_spec = rdMark_valid ? _scoreboard_spec_T : 32'h0; // @[Decode.scala 337:28]
+  wire  _io_busRead_bypass_T_9 = io_inst_inst[11:7] == 5'h0; // @[Decode.scala 349:65]
+  wire  _io_busRead_bypass_T_10 = ~io_inst_inst[5] | io_inst_inst[6] ? rs2Addr == 5'h0 : _io_busRead_bypass_T_9; // @[Decode.scala 348:8]
+  wire  storeSelect = io_inst_inst[6:3] == 4'h4 & io_inst_inst[1:0] == 2'h3; // @[Decode.scala 353:47]
+  wire [4:0] _io_busRead_immed_T_3 = storeSelect ? d_io_immst[4:0] : d_io_imm12[4:0]; // @[Decode.scala 356:30]
+  wire  _io_inst_ready_T_6 = ~io_serializeIn_jump; // @[Decode.scala 362:20]
+  wire  _io_inst_ready_T_7 = aluEn & bruEn & lsuEn & mulEn & dvuEn & vinstEn & _io_inst_ready_T_6; // @[Decode.scala 361:84]
+  wire  _io_inst_ready_T_13 = ~d_io_undef; // @[Decode.scala 363:43]
+  wire  _io_serializeOut_brcond_T = io_serializeIn_brcond | d_io_beq; // @[Decode.scala 373:51]
+  DecodedInstruction_2 d ( // @[Decode.scala 87:17]
     .clock(d_clock),
     .reset(d_reset),
     .io_addr(d_io_addr),
@@ -12166,33 +11273,6 @@
     .io_divu(d_io_divu),
     .io_rem(d_io_rem),
     .io_remu(d_io_remu),
-    .io_flw(d_io_flw),
-    .io_fsw(d_io_fsw),
-    .io_fmadd(d_io_fmadd),
-    .io_fmsub(d_io_fmsub),
-    .io_fnmsub(d_io_fnmsub),
-    .io_fnmadd(d_io_fnmadd),
-    .io_fadd(d_io_fadd),
-    .io_fsub(d_io_fsub),
-    .io_fmul(d_io_fmul),
-    .io_fdiv(d_io_fdiv),
-    .io_fsqrt(d_io_fsqrt),
-    .io_fsgnj(d_io_fsgnj),
-    .io_fsgnjn(d_io_fsgnjn),
-    .io_fsgnjx(d_io_fsgnjx),
-    .io_fmin(d_io_fmin),
-    .io_fmax(d_io_fmax),
-    .io_fcvtws(d_io_fcvtws),
-    .io_fcvtwus(d_io_fcvtwus),
-    .io_fmvxw(d_io_fmvxw),
-    .io_feq(d_io_feq),
-    .io_flt(d_io_flt),
-    .io_fle(d_io_fle),
-    .io_fclass(d_io_fclass),
-    .io_fcvtsw(d_io_fcvtsw),
-    .io_fcvtswu(d_io_fcvtswu),
-    .io_fmvwx(d_io_fmvwx),
-    .io_clb(d_io_clb),
     .io_clz(d_io_clz),
     .io_ctz(d_io_ctz),
     .io_pcnt(d_io_pcnt),
@@ -12205,7 +11285,6 @@
     .io_vld(d_io_vld),
     .io_vst(d_io_vst),
     .io_viop(d_io_viop),
-    .io_vfop(d_io_vfop),
     .io_ebreak(d_io_ebreak),
     .io_ecall(d_io_ecall),
     .io_eexit(d_io_eexit),
@@ -12219,50 +11298,48 @@
     .io_flushall(d_io_flushall),
     .io_slog(d_io_slog)
   );
-  assign io_inst_ready = _io_inst_ready_T_8 & ~io_halted & ~io_interlock & _io_inst_ready_T_14; // @[Decode.scala 426:72]
+  assign io_inst_ready = _io_inst_ready_T_7 & ~io_halted & ~io_interlock & _io_inst_ready_T_13; // @[Decode.scala 362:72]
   assign io_scoreboard_spec = {scoreboard_spec[31:1],1'h0}; // @[Cat.scala 31:58]
-  assign io_rs1Read_valid = decodeEn & _io_rs1Read_valid_T_14; // @[Decode.scala 368:32]
-  assign io_rs1Read_addr = io_inst_inst[0] ? io_inst_inst[19:15] : rs3Addr; // @[Decode.scala 377:25]
-  assign io_rs1Set_valid = decodeEn & d_io_auipc; // @[Decode.scala 383:31]
-  assign io_rs1Set_value = io_inst_addr; // @[Decode.scala 386:25]
-  assign io_rs2Read_valid = decodeEn & _io_rs2Read_valid_T_10; // @[Decode.scala 372:32]
-  assign io_rs2Read_addr = io_inst_inst[24:20]; // @[Decode.scala 100:29]
-  assign io_rs2Set_valid = io_rs1Set_valid | decodeEn & (isAluImm | isAlu1Bit | d_io_lui); // @[Decode.scala 384:38]
+  assign io_rs1Read_valid = decodeEn & _io_rs1Read_valid_T_11; // @[Decode.scala 306:32]
+  assign io_rs1Read_addr = io_inst_inst[0] ? io_inst_inst[19:15] : rs3Addr; // @[Decode.scala 314:25]
+  assign io_rs1Set_valid = decodeEn & d_io_auipc; // @[Decode.scala 320:31]
+  assign io_rs1Set_value = io_inst_addr; // @[Decode.scala 323:25]
+  assign io_rs2Read_valid = decodeEn & _io_rs2Read_valid_T_10; // @[Decode.scala 309:32]
+  assign io_rs2Read_addr = io_inst_inst[24:20]; // @[Decode.scala 96:29]
+  assign io_rs2Set_valid = io_rs1Set_valid | decodeEn & (isAluImm | isAlu1Bit | d_io_lui); // @[Decode.scala 321:38]
   assign io_rs2Set_value = _io_rs2Set_value_T ? d_io_imm20 : d_io_imm12; // @[Mux.scala 101:16]
-  assign io_rdMark_valid = decodeEn & rdMark_valid; // @[Decode.scala 404:31]
-  assign io_rdMark_addr = vldst ? io_inst_inst[19:15] : io_inst_inst[11:7]; // @[Decode.scala 98:20]
-  assign io_busRead_bypass = io_inst_inst[31:25] == 7'h0 & _io_busRead_bypass_T_10; // @[Decode.scala 411:52]
+  assign io_rdMark_valid = decodeEn & rdMark_valid; // @[Decode.scala 340:31]
+  assign io_rdMark_addr = vldst ? io_inst_inst[19:15] : io_inst_inst[11:7]; // @[Decode.scala 94:20]
+  assign io_busRead_bypass = io_inst_inst[31:25] == 7'h0 & _io_busRead_bypass_T_10; // @[Decode.scala 347:52]
   assign io_busRead_immed = {d_io_imm12[31:5],_io_busRead_immed_T_3}; // @[Cat.scala 31:58]
-  assign io_alu_valid = decodeEn & aluValid_value_4_0; // @[Decode.scala 184:28]
-  assign io_alu_addr = vldst ? io_inst_inst[19:15] : io_inst_inst[11:7]; // @[Decode.scala 98:20]
-  assign io_alu_op = {io_alu_op_hi,io_alu_op_lo}; // @[Decode.scala 186:22]
-  assign io_bru_valid = decodeEn & bruValid_value_4_0; // @[Decode.scala 212:28]
-  assign io_bru_fwd = io_inst_brchFwd; // @[Decode.scala 213:14]
-  assign io_bru_op = {io_bru_op_hi,io_bru_op_lo}; // @[Decode.scala 214:22]
-  assign io_bru_pc = io_inst_addr; // @[Decode.scala 215:13]
-  assign io_bru_target = io_inst_addr + _io_bru_target_T_1; // @[Decode.scala 216:33]
-  assign io_bru_link = vldst ? io_inst_inst[19:15] : io_inst_inst[11:7]; // @[Decode.scala 98:20]
-  assign io_csr_op = 3'h0; // @[Decode.scala 244:22]
-  assign io_lsu_valid = decodeEn & lsuValid_value_3_0; // @[Decode.scala 254:28]
-  assign io_lsu_addr = vldst ? io_inst_inst[19:15] : io_inst_inst[11:7]; // @[Decode.scala 98:20]
-  assign io_lsu_op = {io_lsu_op_hi,io_lsu_op_lo}; // @[Decode.scala 257:22]
-  assign io_mlu_valid = decodeEn & mluValid_value_3_0; // @[Decode.scala 278:28]
-  assign io_mlu_addr = vldst ? io_inst_inst[19:15] : io_inst_inst[11:7]; // @[Decode.scala 98:20]
-  assign io_mlu_op = {io_mlu_op_hi,io_mlu_op_lo}; // @[Decode.scala 280:22]
-  assign io_dvu_op = 4'h0; // @[Decode.scala 298:22]
-  assign io_fpu_raddr_1 = io_inst_inst[24:20]; // @[Decode.scala 100:29]
-  assign io_fpu_op = {io_fpu_op_hi,13'h0}; // @[Decode.scala 313:22]
-  assign io_vinst_valid = decodeEn & vinstValid_value_2_0; // @[Decode.scala 352:30]
-  assign io_vinst_addr = vldst ? io_inst_inst[19:15] : io_inst_inst[11:7]; // @[Decode.scala 98:20]
-  assign io_vinst_inst = io_inst_inst; // @[Decode.scala 354:17]
-  assign io_vinst_op = {io_vinst_op_hi,io_vinst_op_lo}; // @[Decode.scala 355:26]
-  assign io_serializeOut_mul = io_serializeIn_mul | mluValid_value_3_0; // @[Decode.scala 433:46]
-  assign io_serializeOut_jump = io_serializeIn_jump | d_io_jal | d_io_jalr; // @[Decode.scala 434:59]
-  assign io_serializeOut_brcond = _io_serializeOut_brcond_T | d_io_bne | d_io_blt | d_io_bge | d_io_bltu | d_io_bgeu; // @[Decode.scala 438:65]
+  assign io_alu_valid = decodeEn & aluValid_value_4_0; // @[Decode.scala 165:28]
+  assign io_alu_addr = vldst ? io_inst_inst[19:15] : io_inst_inst[11:7]; // @[Decode.scala 94:20]
+  assign io_alu_op = {io_alu_op_hi,io_alu_op_lo}; // @[Decode.scala 167:22]
+  assign io_bru_valid = decodeEn & bruValid_value_4_0; // @[Decode.scala 192:28]
+  assign io_bru_fwd = io_inst_brchFwd; // @[Decode.scala 193:14]
+  assign io_bru_op = {io_bru_op_hi,io_bru_op_lo}; // @[Decode.scala 194:22]
+  assign io_bru_pc = io_inst_addr; // @[Decode.scala 195:13]
+  assign io_bru_target = io_inst_addr + _io_bru_target_T_1; // @[Decode.scala 196:33]
+  assign io_bru_link = vldst ? io_inst_inst[19:15] : io_inst_inst[11:7]; // @[Decode.scala 94:20]
+  assign io_csr_op = 3'h0; // @[Decode.scala 224:22]
+  assign io_lsu_valid = decodeEn & lsuValid_value_3_0; // @[Decode.scala 234:28]
+  assign io_lsu_addr = vldst ? io_inst_inst[19:15] : io_inst_inst[11:7]; // @[Decode.scala 94:20]
+  assign io_lsu_op = {io_lsu_op_hi,io_lsu_op_lo}; // @[Decode.scala 237:22]
+  assign io_mlu_valid = decodeEn & mluValid_value_3_0; // @[Decode.scala 257:28]
+  assign io_mlu_addr = vldst ? io_inst_inst[19:15] : io_inst_inst[11:7]; // @[Decode.scala 94:20]
+  assign io_mlu_op = {io_mlu_op_hi,io_mlu_op_lo}; // @[Decode.scala 259:22]
+  assign io_dvu_op = 4'h0; // @[Decode.scala 277:22]
+  assign io_vinst_valid = decodeEn & vinstValid_value_2_0; // @[Decode.scala 291:30]
+  assign io_vinst_addr = vldst ? io_inst_inst[19:15] : io_inst_inst[11:7]; // @[Decode.scala 94:20]
+  assign io_vinst_inst = io_inst_inst; // @[Decode.scala 293:17]
+  assign io_vinst_op = {io_vinst_op_hi,io_vinst_op_lo}; // @[Decode.scala 294:26]
+  assign io_serializeOut_mul = io_serializeIn_mul | mluValid_value_3_0; // @[Decode.scala 369:46]
+  assign io_serializeOut_jump = io_serializeIn_jump | d_io_jal | d_io_jalr; // @[Decode.scala 370:59]
+  assign io_serializeOut_brcond = _io_serializeOut_brcond_T | d_io_bne | d_io_blt | d_io_bge | d_io_bltu | d_io_bgeu; // @[Decode.scala 374:65]
   assign d_clock = clock;
   assign d_reset = reset;
-  assign d_io_addr = io_inst_addr; // @[Decode.scala 92:13]
-  assign d_io_inst = io_inst_inst; // @[Decode.scala 93:13]
+  assign d_io_addr = io_inst_addr; // @[Decode.scala 88:13]
+  assign d_io_inst = io_inst_inst; // @[Decode.scala 89:13]
 endmodule
 module DecodedInstruction_3(
   input         clock,
@@ -12328,33 +11405,6 @@
   output        io_divu,
   output        io_rem,
   output        io_remu,
-  output        io_flw,
-  output        io_fsw,
-  output        io_fmadd,
-  output        io_fmsub,
-  output        io_fnmsub,
-  output        io_fnmadd,
-  output        io_fadd,
-  output        io_fsub,
-  output        io_fmul,
-  output        io_fdiv,
-  output        io_fsqrt,
-  output        io_fsgnj,
-  output        io_fsgnjn,
-  output        io_fsgnjx,
-  output        io_fmin,
-  output        io_fmax,
-  output        io_fcvtws,
-  output        io_fcvtwus,
-  output        io_fmvxw,
-  output        io_feq,
-  output        io_flt,
-  output        io_fle,
-  output        io_fclass,
-  output        io_fcvtsw,
-  output        io_fcvtswu,
-  output        io_fmvwx,
-  output        io_clb,
   output        io_clz,
   output        io_ctz,
   output        io_pcnt,
@@ -12367,7 +11417,6 @@
   output        io_vld,
   output        io_vst,
   output        io_viop,
-  output        io_vfop,
   output        io_ebreak,
   output        io_ecall,
   output        io_eexit,
@@ -12391,343 +11440,318 @@
   wire [4:0] io_immbr_lo = {io_inst[11:8],1'h0}; // @[Cat.scala 31:58]
   wire [26:0] io_immbr_hi = {_io_imm12_T_2,io_inst[7],io_inst[30:25]}; // @[Cat.scala 31:58]
   wire [26:0] io_immst_hi = {_io_imm12_T_2,io_inst[31:25]}; // @[Cat.scala 31:58]
-  wire  io_lui_bit_1 = io_inst[30]; // @[Library.scala 316:23]
-  wire  io_lui_bit_2 = io_inst[29]; // @[Library.scala 316:23]
-  wire  io_lui_bit_3 = io_inst[28]; // @[Library.scala 316:23]
-  wire  io_lui_bit_4 = io_inst[27]; // @[Library.scala 316:23]
-  wire  io_lui_bit_5 = io_inst[26]; // @[Library.scala 316:23]
-  wire  io_lui_bit_6 = io_inst[25]; // @[Library.scala 316:23]
-  wire  io_lui_bit_7 = io_inst[24]; // @[Library.scala 316:23]
-  wire  io_lui_bit_8 = io_inst[23]; // @[Library.scala 316:23]
-  wire  io_lui_bit_9 = io_inst[22]; // @[Library.scala 316:23]
-  wire  io_lui_bit_10 = io_inst[21]; // @[Library.scala 316:23]
-  wire  io_lui_bit_12 = io_inst[19]; // @[Library.scala 316:23]
-  wire  io_lui_bit_13 = io_inst[18]; // @[Library.scala 316:23]
-  wire  io_lui_bit_14 = io_inst[17]; // @[Library.scala 316:23]
-  wire  io_lui_bit_15 = io_inst[16]; // @[Library.scala 316:23]
-  wire  io_lui_bit_16 = io_inst[15]; // @[Library.scala 316:23]
-  wire  io_lui_bit_17 = io_inst[14]; // @[Library.scala 316:23]
-  wire  io_lui_bit_18 = io_inst[13]; // @[Library.scala 316:23]
-  wire  io_lui_bit_19 = io_inst[12]; // @[Library.scala 316:23]
-  wire  io_lui_bit_25 = ~io_inst[6]; // @[Library.scala 310:19]
-  wire  io_lui_bit_26 = io_inst[5]; // @[Library.scala 313:23]
-  wire  io_lui_bit_27 = io_inst[4]; // @[Library.scala 313:23]
-  wire  _io_lui_T_2 = io_lui_bit_25 & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 314:48]
-  wire  io_lui_bit_28 = ~io_inst[3]; // @[Library.scala 310:19]
-  wire  _io_lui_T_3 = _io_lui_T_2 & io_lui_bit_28; // @[Library.scala 311:48]
-  wire  io_lui_bit_29 = io_inst[2]; // @[Library.scala 313:23]
-  wire  io_lui_bit_30 = io_inst[1]; // @[Library.scala 313:23]
-  wire  io_lui_bit_31 = io_inst[0]; // @[Library.scala 313:23]
-  wire  io_auipc_bit_26 = ~io_lui_bit_26; // @[Library.scala 310:19]
-  wire  _io_auipc_T_1 = io_lui_bit_25 & io_auipc_bit_26; // @[Library.scala 311:48]
-  wire  _io_auipc_T_2 = _io_auipc_T_1 & io_lui_bit_27; // @[Library.scala 314:48]
-  wire  _io_auipc_T_3 = _io_auipc_T_2 & io_lui_bit_28; // @[Library.scala 311:48]
-  wire  _io_jal_T_1 = io_inst[6] & io_lui_bit_26; // @[Library.scala 314:48]
-  wire  io_jal_bit_27 = ~io_lui_bit_27; // @[Library.scala 310:19]
-  wire  _io_jal_T_2 = _io_jal_T_1 & io_jal_bit_27; // @[Library.scala 311:48]
-  wire  io_jalr_bit_17 = ~io_lui_bit_17; // @[Library.scala 310:19]
-  wire  io_jalr_bit_18 = ~io_lui_bit_18; // @[Library.scala 310:19]
-  wire  _io_jalr_T_1 = io_jalr_bit_17 & io_jalr_bit_18; // @[Library.scala 311:48]
-  wire  io_jalr_bit_19 = ~io_lui_bit_19; // @[Library.scala 310:19]
-  wire  _io_jalr_T_2 = io_jalr_bit_17 & io_jalr_bit_18 & io_jalr_bit_19; // @[Library.scala 311:48]
-  wire  _io_jalr_T_4 = _io_jalr_T_2 & io_inst[6] & io_lui_bit_26; // @[Library.scala 314:48]
-  wire  _io_jalr_T_6 = _io_jalr_T_4 & io_jal_bit_27 & io_lui_bit_28; // @[Library.scala 311:48]
-  wire  io_beq_bit_29 = ~io_lui_bit_29; // @[Library.scala 310:19]
-  wire  _io_beq_T_7 = _io_jalr_T_4 & io_jal_bit_27 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 311:48]
-  wire  _io_bne_T_2 = _io_jalr_T_1 & io_lui_bit_19; // @[Library.scala 314:48]
-  wire  _io_bne_T_4 = _io_jalr_T_1 & io_lui_bit_19 & io_inst[6] & io_lui_bit_26; // @[Library.scala 314:48]
-  wire  _io_bne_T_7 = _io_bne_T_4 & io_jal_bit_27 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 311:48]
-  wire  _io_blt_T_1 = io_lui_bit_17 & io_jalr_bit_18; // @[Library.scala 311:48]
-  wire  _io_blt_T_2 = io_lui_bit_17 & io_jalr_bit_18 & io_jalr_bit_19; // @[Library.scala 311:48]
-  wire  _io_blt_T_4 = _io_blt_T_2 & io_inst[6] & io_lui_bit_26; // @[Library.scala 314:48]
-  wire  _io_blt_T_7 = _io_blt_T_4 & io_jal_bit_27 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 311:48]
-  wire  _io_bge_T_2 = _io_blt_T_1 & io_lui_bit_19; // @[Library.scala 314:48]
-  wire  _io_bge_T_4 = _io_blt_T_1 & io_lui_bit_19 & io_inst[6] & io_lui_bit_26; // @[Library.scala 314:48]
-  wire  _io_bge_T_7 = _io_bge_T_4 & io_jal_bit_27 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 311:48]
-  wire  _io_bltu_T_1 = io_lui_bit_17 & io_lui_bit_18; // @[Library.scala 314:48]
-  wire  _io_bltu_T_2 = _io_bltu_T_1 & io_jalr_bit_19; // @[Library.scala 311:48]
-  wire  _io_bltu_T_4 = _io_bltu_T_2 & io_inst[6] & io_lui_bit_26; // @[Library.scala 314:48]
-  wire  _io_bltu_T_7 = _io_bltu_T_4 & io_jal_bit_27 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 311:48]
-  wire  _io_bgeu_T_2 = io_lui_bit_17 & io_lui_bit_18 & io_lui_bit_19; // @[Library.scala 314:48]
-  wire  _io_bgeu_T_4 = io_lui_bit_17 & io_lui_bit_18 & io_lui_bit_19 & io_inst[6] & io_lui_bit_26; // @[Library.scala 314:48]
-  wire  _io_bgeu_T_7 = _io_bgeu_T_4 & io_jal_bit_27 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 311:48]
-  wire  _io_lb_T_3 = io_jalr_bit_17 & io_jalr_bit_18 & io_jalr_bit_19 & io_lui_bit_25; // @[Library.scala 311:48]
-  wire  _io_lb_T_4 = io_jalr_bit_17 & io_jalr_bit_18 & io_jalr_bit_19 & io_lui_bit_25 & io_auipc_bit_26; // @[Library.scala 311:48]
+  wire  io_lui_bit_1 = io_inst[30]; // @[Library.scala 318:23]
+  wire  io_lui_bit_2 = io_inst[29]; // @[Library.scala 318:23]
+  wire  io_lui_bit_3 = io_inst[28]; // @[Library.scala 318:23]
+  wire  io_lui_bit_4 = io_inst[27]; // @[Library.scala 318:23]
+  wire  io_lui_bit_5 = io_inst[26]; // @[Library.scala 318:23]
+  wire  io_lui_bit_6 = io_inst[25]; // @[Library.scala 318:23]
+  wire  io_lui_bit_7 = io_inst[24]; // @[Library.scala 318:23]
+  wire  io_lui_bit_8 = io_inst[23]; // @[Library.scala 318:23]
+  wire  io_lui_bit_9 = io_inst[22]; // @[Library.scala 318:23]
+  wire  io_lui_bit_10 = io_inst[21]; // @[Library.scala 318:23]
+  wire  io_lui_bit_12 = io_inst[19]; // @[Library.scala 318:23]
+  wire  io_lui_bit_13 = io_inst[18]; // @[Library.scala 318:23]
+  wire  io_lui_bit_14 = io_inst[17]; // @[Library.scala 318:23]
+  wire  io_lui_bit_15 = io_inst[16]; // @[Library.scala 318:23]
+  wire  io_lui_bit_16 = io_inst[15]; // @[Library.scala 318:23]
+  wire  io_lui_bit_17 = io_inst[14]; // @[Library.scala 318:23]
+  wire  io_lui_bit_18 = io_inst[13]; // @[Library.scala 318:23]
+  wire  io_lui_bit_19 = io_inst[12]; // @[Library.scala 318:23]
+  wire  io_lui_bit_25 = ~io_inst[6]; // @[Library.scala 312:19]
+  wire  io_lui_bit_26 = io_inst[5]; // @[Library.scala 315:23]
+  wire  io_lui_bit_27 = io_inst[4]; // @[Library.scala 315:23]
+  wire  _io_lui_T_2 = io_lui_bit_25 & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 316:48]
+  wire  io_lui_bit_28 = ~io_inst[3]; // @[Library.scala 312:19]
+  wire  _io_lui_T_3 = _io_lui_T_2 & io_lui_bit_28; // @[Library.scala 313:48]
+  wire  io_lui_bit_29 = io_inst[2]; // @[Library.scala 315:23]
+  wire  io_lui_bit_30 = io_inst[1]; // @[Library.scala 315:23]
+  wire  io_lui_bit_31 = io_inst[0]; // @[Library.scala 315:23]
+  wire  io_auipc_bit_26 = ~io_lui_bit_26; // @[Library.scala 312:19]
+  wire  _io_auipc_T_1 = io_lui_bit_25 & io_auipc_bit_26; // @[Library.scala 313:48]
+  wire  _io_auipc_T_2 = _io_auipc_T_1 & io_lui_bit_27; // @[Library.scala 316:48]
+  wire  _io_auipc_T_3 = _io_auipc_T_2 & io_lui_bit_28; // @[Library.scala 313:48]
+  wire  _io_jal_T_1 = io_inst[6] & io_lui_bit_26; // @[Library.scala 316:48]
+  wire  io_jal_bit_27 = ~io_lui_bit_27; // @[Library.scala 312:19]
+  wire  _io_jal_T_2 = _io_jal_T_1 & io_jal_bit_27; // @[Library.scala 313:48]
+  wire  io_jalr_bit_17 = ~io_lui_bit_17; // @[Library.scala 312:19]
+  wire  io_jalr_bit_18 = ~io_lui_bit_18; // @[Library.scala 312:19]
+  wire  _io_jalr_T_1 = io_jalr_bit_17 & io_jalr_bit_18; // @[Library.scala 313:48]
+  wire  io_jalr_bit_19 = ~io_lui_bit_19; // @[Library.scala 312:19]
+  wire  _io_jalr_T_2 = io_jalr_bit_17 & io_jalr_bit_18 & io_jalr_bit_19; // @[Library.scala 313:48]
+  wire  _io_jalr_T_4 = _io_jalr_T_2 & io_inst[6] & io_lui_bit_26; // @[Library.scala 316:48]
+  wire  _io_jalr_T_6 = _io_jalr_T_4 & io_jal_bit_27 & io_lui_bit_28; // @[Library.scala 313:48]
+  wire  io_beq_bit_29 = ~io_lui_bit_29; // @[Library.scala 312:19]
+  wire  _io_beq_T_7 = _io_jalr_T_4 & io_jal_bit_27 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 313:48]
+  wire  _io_bne_T_2 = _io_jalr_T_1 & io_lui_bit_19; // @[Library.scala 316:48]
+  wire  _io_bne_T_4 = _io_jalr_T_1 & io_lui_bit_19 & io_inst[6] & io_lui_bit_26; // @[Library.scala 316:48]
+  wire  _io_bne_T_7 = _io_bne_T_4 & io_jal_bit_27 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 313:48]
+  wire  _io_blt_T_1 = io_lui_bit_17 & io_jalr_bit_18; // @[Library.scala 313:48]
+  wire  _io_blt_T_2 = io_lui_bit_17 & io_jalr_bit_18 & io_jalr_bit_19; // @[Library.scala 313:48]
+  wire  _io_blt_T_4 = _io_blt_T_2 & io_inst[6] & io_lui_bit_26; // @[Library.scala 316:48]
+  wire  _io_blt_T_7 = _io_blt_T_4 & io_jal_bit_27 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 313:48]
+  wire  _io_bge_T_2 = _io_blt_T_1 & io_lui_bit_19; // @[Library.scala 316:48]
+  wire  _io_bge_T_4 = _io_blt_T_1 & io_lui_bit_19 & io_inst[6] & io_lui_bit_26; // @[Library.scala 316:48]
+  wire  _io_bge_T_7 = _io_bge_T_4 & io_jal_bit_27 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 313:48]
+  wire  _io_bltu_T_1 = io_lui_bit_17 & io_lui_bit_18; // @[Library.scala 316:48]
+  wire  _io_bltu_T_2 = _io_bltu_T_1 & io_jalr_bit_19; // @[Library.scala 313:48]
+  wire  _io_bltu_T_4 = _io_bltu_T_2 & io_inst[6] & io_lui_bit_26; // @[Library.scala 316:48]
+  wire  _io_bltu_T_7 = _io_bltu_T_4 & io_jal_bit_27 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 313:48]
+  wire  _io_bgeu_T_2 = io_lui_bit_17 & io_lui_bit_18 & io_lui_bit_19; // @[Library.scala 316:48]
+  wire  _io_bgeu_T_4 = io_lui_bit_17 & io_lui_bit_18 & io_lui_bit_19 & io_inst[6] & io_lui_bit_26; // @[Library.scala 316:48]
+  wire  _io_bgeu_T_7 = _io_bgeu_T_4 & io_jal_bit_27 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 313:48]
+  wire  _io_lb_T_3 = io_jalr_bit_17 & io_jalr_bit_18 & io_jalr_bit_19 & io_lui_bit_25; // @[Library.scala 313:48]
+  wire  _io_lb_T_4 = io_jalr_bit_17 & io_jalr_bit_18 & io_jalr_bit_19 & io_lui_bit_25 & io_auipc_bit_26; // @[Library.scala 313:48]
   wire  _io_lb_T_7 = io_jalr_bit_17 & io_jalr_bit_18 & io_jalr_bit_19 & io_lui_bit_25 & io_auipc_bit_26 & io_jal_bit_27
-     & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 311:48]
-  wire  _io_lh_T_3 = _io_bne_T_2 & io_lui_bit_25; // @[Library.scala 311:48]
-  wire  _io_lh_T_7 = _io_bne_T_2 & io_lui_bit_25 & io_auipc_bit_26 & io_jal_bit_27 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 311:48]
-  wire  _io_lw_T_1 = io_jalr_bit_17 & io_lui_bit_18; // @[Library.scala 314:48]
-  wire  _io_lw_T_3 = _io_lw_T_1 & io_jalr_bit_19 & io_lui_bit_25; // @[Library.scala 311:48]
-  wire  _io_lw_T_4 = _io_lw_T_1 & io_jalr_bit_19 & io_lui_bit_25 & io_auipc_bit_26; // @[Library.scala 311:48]
+     & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 313:48]
+  wire  _io_lh_T_3 = _io_bne_T_2 & io_lui_bit_25; // @[Library.scala 313:48]
+  wire  _io_lh_T_7 = _io_bne_T_2 & io_lui_bit_25 & io_auipc_bit_26 & io_jal_bit_27 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 313:48]
+  wire  _io_lw_T_1 = io_jalr_bit_17 & io_lui_bit_18; // @[Library.scala 316:48]
+  wire  _io_lw_T_3 = _io_lw_T_1 & io_jalr_bit_19 & io_lui_bit_25; // @[Library.scala 313:48]
+  wire  _io_lw_T_4 = _io_lw_T_1 & io_jalr_bit_19 & io_lui_bit_25 & io_auipc_bit_26; // @[Library.scala 313:48]
   wire  _io_lw_T_7 = _io_lw_T_1 & io_jalr_bit_19 & io_lui_bit_25 & io_auipc_bit_26 & io_jal_bit_27 & io_lui_bit_28 &
-    io_beq_bit_29; // @[Library.scala 311:48]
-  wire  _io_lbu_T_4 = io_lui_bit_17 & io_jalr_bit_18 & io_jalr_bit_19 & io_lui_bit_25 & io_auipc_bit_26; // @[Library.scala 311:48]
+    io_beq_bit_29; // @[Library.scala 313:48]
+  wire  _io_lbu_T_4 = io_lui_bit_17 & io_jalr_bit_18 & io_jalr_bit_19 & io_lui_bit_25 & io_auipc_bit_26; // @[Library.scala 313:48]
   wire  _io_lbu_T_7 = io_lui_bit_17 & io_jalr_bit_18 & io_jalr_bit_19 & io_lui_bit_25 & io_auipc_bit_26 & io_jal_bit_27
-     & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 311:48]
-  wire  _io_lhu_T_7 = _io_bge_T_2 & io_lui_bit_25 & io_auipc_bit_26 & io_jal_bit_27 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 311:48]
-  wire  _io_sb_T_4 = _io_lb_T_3 & io_lui_bit_26; // @[Library.scala 314:48]
-  wire  _io_sb_T_7 = _io_sb_T_4 & io_jal_bit_27 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 311:48]
-  wire  _io_sh_T_4 = _io_lh_T_3 & io_lui_bit_26; // @[Library.scala 314:48]
-  wire  _io_sh_T_7 = _io_sh_T_4 & io_jal_bit_27 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 311:48]
-  wire  _io_sw_T_4 = _io_lw_T_3 & io_lui_bit_26; // @[Library.scala 314:48]
-  wire  _io_sw_T_7 = _io_sw_T_4 & io_jal_bit_27 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 311:48]
-  wire  io_fence_bit = ~io_inst[31]; // @[Library.scala 310:19]
-  wire  io_fence_bit_1 = ~io_lui_bit_1; // @[Library.scala 310:19]
-  wire  _io_fence_T_1 = io_fence_bit & io_fence_bit_1; // @[Library.scala 311:48]
-  wire  io_fence_bit_2 = ~io_lui_bit_2; // @[Library.scala 310:19]
-  wire  _io_fence_T_2 = io_fence_bit & io_fence_bit_1 & io_fence_bit_2; // @[Library.scala 311:48]
-  wire  io_fence_bit_3 = ~io_lui_bit_3; // @[Library.scala 310:19]
-  wire  _io_fence_T_3 = io_fence_bit & io_fence_bit_1 & io_fence_bit_2 & io_fence_bit_3; // @[Library.scala 311:48]
-  wire  io_fence_bit_12 = ~io_lui_bit_12; // @[Library.scala 310:19]
-  wire  io_fence_bit_13 = ~io_lui_bit_13; // @[Library.scala 310:19]
-  wire  io_fence_bit_14 = ~io_lui_bit_14; // @[Library.scala 310:19]
-  wire  io_fence_bit_15 = ~io_lui_bit_15; // @[Library.scala 310:19]
-  wire  io_fence_bit_16 = ~io_lui_bit_16; // @[Library.scala 310:19]
-  wire  _io_addi_T_5 = _io_lb_T_4 & io_lui_bit_27; // @[Library.scala 314:48]
-  wire  _io_addi_T_7 = _io_addi_T_5 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 311:48]
-  wire  _io_slti_T_5 = _io_lw_T_4 & io_lui_bit_27; // @[Library.scala 314:48]
-  wire  _io_slti_T_7 = _io_slti_T_5 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 311:48]
-  wire  _io_sltiu_T_2 = io_jalr_bit_17 & io_lui_bit_18 & io_lui_bit_19; // @[Library.scala 314:48]
-  wire  _io_sltiu_T_4 = _io_sltiu_T_2 & io_lui_bit_25 & io_auipc_bit_26; // @[Library.scala 311:48]
-  wire  _io_sltiu_T_5 = _io_sltiu_T_4 & io_lui_bit_27; // @[Library.scala 314:48]
-  wire  _io_sltiu_T_7 = _io_sltiu_T_5 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 311:48]
-  wire  _io_xori_T_5 = _io_lbu_T_4 & io_lui_bit_27; // @[Library.scala 314:48]
-  wire  _io_xori_T_7 = _io_xori_T_5 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 311:48]
-  wire  _io_ori_T_4 = _io_bltu_T_1 & io_jalr_bit_19 & io_lui_bit_25 & io_auipc_bit_26; // @[Library.scala 311:48]
-  wire  _io_ori_T_5 = _io_ori_T_4 & io_lui_bit_27; // @[Library.scala 314:48]
-  wire  _io_ori_T_7 = _io_ori_T_5 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 311:48]
-  wire  _io_andi_T_4 = _io_bgeu_T_2 & io_lui_bit_25 & io_auipc_bit_26; // @[Library.scala 311:48]
-  wire  _io_andi_T_5 = _io_andi_T_4 & io_lui_bit_27; // @[Library.scala 314:48]
-  wire  _io_andi_T_7 = _io_andi_T_5 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 311:48]
-  wire  io_slli_bit_4 = ~io_lui_bit_4; // @[Library.scala 310:19]
-  wire  _io_slli_T_4 = io_fence_bit & io_fence_bit_1 & io_fence_bit_2 & io_fence_bit_3 & io_slli_bit_4; // @[Library.scala 311:48]
-  wire  io_slli_bit_5 = ~io_lui_bit_5; // @[Library.scala 310:19]
-  wire  _io_slli_T_5 = io_fence_bit & io_fence_bit_1 & io_fence_bit_2 & io_fence_bit_3 & io_slli_bit_4 & io_slli_bit_5; // @[Library.scala 311:48]
-  wire  io_slli_bit_6 = ~io_lui_bit_6; // @[Library.scala 310:19]
+     & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 313:48]
+  wire  _io_lhu_T_7 = _io_bge_T_2 & io_lui_bit_25 & io_auipc_bit_26 & io_jal_bit_27 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 313:48]
+  wire  _io_sb_T_4 = _io_lb_T_3 & io_lui_bit_26; // @[Library.scala 316:48]
+  wire  _io_sb_T_7 = _io_sb_T_4 & io_jal_bit_27 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 313:48]
+  wire  _io_sh_T_4 = _io_lh_T_3 & io_lui_bit_26; // @[Library.scala 316:48]
+  wire  _io_sh_T_7 = _io_sh_T_4 & io_jal_bit_27 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 313:48]
+  wire  _io_sw_T_4 = _io_lw_T_3 & io_lui_bit_26; // @[Library.scala 316:48]
+  wire  _io_sw_T_7 = _io_sw_T_4 & io_jal_bit_27 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 313:48]
+  wire  io_fence_bit = ~io_inst[31]; // @[Library.scala 312:19]
+  wire  io_fence_bit_1 = ~io_lui_bit_1; // @[Library.scala 312:19]
+  wire  _io_fence_T_1 = io_fence_bit & io_fence_bit_1; // @[Library.scala 313:48]
+  wire  io_fence_bit_2 = ~io_lui_bit_2; // @[Library.scala 312:19]
+  wire  _io_fence_T_2 = io_fence_bit & io_fence_bit_1 & io_fence_bit_2; // @[Library.scala 313:48]
+  wire  io_fence_bit_3 = ~io_lui_bit_3; // @[Library.scala 312:19]
+  wire  _io_fence_T_3 = io_fence_bit & io_fence_bit_1 & io_fence_bit_2 & io_fence_bit_3; // @[Library.scala 313:48]
+  wire  io_fence_bit_12 = ~io_lui_bit_12; // @[Library.scala 312:19]
+  wire  io_fence_bit_13 = ~io_lui_bit_13; // @[Library.scala 312:19]
+  wire  io_fence_bit_14 = ~io_lui_bit_14; // @[Library.scala 312:19]
+  wire  io_fence_bit_15 = ~io_lui_bit_15; // @[Library.scala 312:19]
+  wire  io_fence_bit_16 = ~io_lui_bit_16; // @[Library.scala 312:19]
+  wire  _io_addi_T_5 = _io_lb_T_4 & io_lui_bit_27; // @[Library.scala 316:48]
+  wire  _io_addi_T_7 = _io_addi_T_5 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 313:48]
+  wire  _io_slti_T_5 = _io_lw_T_4 & io_lui_bit_27; // @[Library.scala 316:48]
+  wire  _io_slti_T_7 = _io_slti_T_5 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 313:48]
+  wire  _io_sltiu_T_2 = io_jalr_bit_17 & io_lui_bit_18 & io_lui_bit_19; // @[Library.scala 316:48]
+  wire  _io_sltiu_T_4 = _io_sltiu_T_2 & io_lui_bit_25 & io_auipc_bit_26; // @[Library.scala 313:48]
+  wire  _io_sltiu_T_5 = _io_sltiu_T_4 & io_lui_bit_27; // @[Library.scala 316:48]
+  wire  _io_sltiu_T_7 = _io_sltiu_T_5 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 313:48]
+  wire  _io_xori_T_5 = _io_lbu_T_4 & io_lui_bit_27; // @[Library.scala 316:48]
+  wire  _io_xori_T_7 = _io_xori_T_5 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 313:48]
+  wire  _io_ori_T_4 = _io_bltu_T_1 & io_jalr_bit_19 & io_lui_bit_25 & io_auipc_bit_26; // @[Library.scala 313:48]
+  wire  _io_ori_T_5 = _io_ori_T_4 & io_lui_bit_27; // @[Library.scala 316:48]
+  wire  _io_ori_T_7 = _io_ori_T_5 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 313:48]
+  wire  _io_andi_T_4 = _io_bgeu_T_2 & io_lui_bit_25 & io_auipc_bit_26; // @[Library.scala 313:48]
+  wire  _io_andi_T_5 = _io_andi_T_4 & io_lui_bit_27; // @[Library.scala 316:48]
+  wire  _io_andi_T_7 = _io_andi_T_5 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 313:48]
+  wire  io_slli_bit_4 = ~io_lui_bit_4; // @[Library.scala 312:19]
+  wire  _io_slli_T_4 = io_fence_bit & io_fence_bit_1 & io_fence_bit_2 & io_fence_bit_3 & io_slli_bit_4; // @[Library.scala 313:48]
+  wire  io_slli_bit_5 = ~io_lui_bit_5; // @[Library.scala 312:19]
+  wire  _io_slli_T_5 = io_fence_bit & io_fence_bit_1 & io_fence_bit_2 & io_fence_bit_3 & io_slli_bit_4 & io_slli_bit_5; // @[Library.scala 313:48]
+  wire  io_slli_bit_6 = ~io_lui_bit_6; // @[Library.scala 312:19]
   wire  _io_slli_T_6 = io_fence_bit & io_fence_bit_1 & io_fence_bit_2 & io_fence_bit_3 & io_slli_bit_4 & io_slli_bit_5
-     & io_slli_bit_6; // @[Library.scala 311:48]
+     & io_slli_bit_6; // @[Library.scala 313:48]
   wire  _io_slli_T_7 = io_fence_bit & io_fence_bit_1 & io_fence_bit_2 & io_fence_bit_3 & io_slli_bit_4 & io_slli_bit_5
-     & io_slli_bit_6 & io_jalr_bit_17; // @[Library.scala 311:48]
+     & io_slli_bit_6 & io_jalr_bit_17; // @[Library.scala 313:48]
   wire  _io_slli_T_8 = io_fence_bit & io_fence_bit_1 & io_fence_bit_2 & io_fence_bit_3 & io_slli_bit_4 & io_slli_bit_5
-     & io_slli_bit_6 & io_jalr_bit_17 & io_jalr_bit_18; // @[Library.scala 311:48]
-  wire  _io_slli_T_9 = _io_slli_T_8 & io_lui_bit_19; // @[Library.scala 314:48]
-  wire  _io_slli_T_10 = _io_slli_T_9 & io_lui_bit_25; // @[Library.scala 311:48]
-  wire  _io_slli_T_11 = _io_slli_T_9 & io_lui_bit_25 & io_auipc_bit_26; // @[Library.scala 311:48]
-  wire  _io_slli_T_12 = _io_slli_T_11 & io_lui_bit_27; // @[Library.scala 314:48]
-  wire  _io_slli_T_14 = _io_slli_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 311:48]
-  wire  _io_srli_T_7 = _io_slli_T_6 & io_lui_bit_17; // @[Library.scala 314:48]
-  wire  _io_srli_T_8 = _io_srli_T_7 & io_jalr_bit_18; // @[Library.scala 311:48]
-  wire  _io_srli_T_9 = _io_srli_T_8 & io_lui_bit_19; // @[Library.scala 314:48]
-  wire  _io_srli_T_10 = _io_srli_T_9 & io_lui_bit_25; // @[Library.scala 311:48]
-  wire  _io_srli_T_11 = _io_srli_T_9 & io_lui_bit_25 & io_auipc_bit_26; // @[Library.scala 311:48]
-  wire  _io_srli_T_12 = _io_srli_T_11 & io_lui_bit_27; // @[Library.scala 314:48]
-  wire  _io_srli_T_14 = _io_srli_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 311:48]
-  wire  _io_srai_T_1 = io_fence_bit & io_lui_bit_1; // @[Library.scala 314:48]
-  wire  _io_srai_T_2 = _io_srai_T_1 & io_fence_bit_2; // @[Library.scala 311:48]
-  wire  _io_srai_T_6 = _io_srai_T_1 & io_fence_bit_2 & io_fence_bit_3 & io_slli_bit_4 & io_slli_bit_5 & io_slli_bit_6; // @[Library.scala 311:48]
-  wire  _io_srai_T_7 = _io_srai_T_6 & io_lui_bit_17; // @[Library.scala 314:48]
-  wire  _io_srai_T_8 = _io_srai_T_7 & io_jalr_bit_18; // @[Library.scala 311:48]
-  wire  _io_srai_T_9 = _io_srai_T_8 & io_lui_bit_19; // @[Library.scala 314:48]
-  wire  _io_srai_T_10 = _io_srai_T_9 & io_lui_bit_25; // @[Library.scala 311:48]
-  wire  _io_srai_T_11 = _io_srai_T_9 & io_lui_bit_25 & io_auipc_bit_26; // @[Library.scala 311:48]
-  wire  _io_srai_T_12 = _io_srai_T_11 & io_lui_bit_27; // @[Library.scala 314:48]
-  wire  _io_srai_T_14 = _io_srai_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 311:48]
+     & io_slli_bit_6 & io_jalr_bit_17 & io_jalr_bit_18; // @[Library.scala 313:48]
+  wire  _io_slli_T_9 = _io_slli_T_8 & io_lui_bit_19; // @[Library.scala 316:48]
+  wire  _io_slli_T_10 = _io_slli_T_9 & io_lui_bit_25; // @[Library.scala 313:48]
+  wire  _io_slli_T_11 = _io_slli_T_9 & io_lui_bit_25 & io_auipc_bit_26; // @[Library.scala 313:48]
+  wire  _io_slli_T_12 = _io_slli_T_11 & io_lui_bit_27; // @[Library.scala 316:48]
+  wire  _io_slli_T_14 = _io_slli_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 313:48]
+  wire  _io_srli_T_7 = _io_slli_T_6 & io_lui_bit_17; // @[Library.scala 316:48]
+  wire  _io_srli_T_8 = _io_srli_T_7 & io_jalr_bit_18; // @[Library.scala 313:48]
+  wire  _io_srli_T_9 = _io_srli_T_8 & io_lui_bit_19; // @[Library.scala 316:48]
+  wire  _io_srli_T_10 = _io_srli_T_9 & io_lui_bit_25; // @[Library.scala 313:48]
+  wire  _io_srli_T_11 = _io_srli_T_9 & io_lui_bit_25 & io_auipc_bit_26; // @[Library.scala 313:48]
+  wire  _io_srli_T_12 = _io_srli_T_11 & io_lui_bit_27; // @[Library.scala 316:48]
+  wire  _io_srli_T_14 = _io_srli_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 313:48]
+  wire  _io_srai_T_1 = io_fence_bit & io_lui_bit_1; // @[Library.scala 316:48]
+  wire  _io_srai_T_2 = _io_srai_T_1 & io_fence_bit_2; // @[Library.scala 313:48]
+  wire  _io_srai_T_6 = _io_srai_T_1 & io_fence_bit_2 & io_fence_bit_3 & io_slli_bit_4 & io_slli_bit_5 & io_slli_bit_6; // @[Library.scala 313:48]
+  wire  _io_srai_T_7 = _io_srai_T_6 & io_lui_bit_17; // @[Library.scala 316:48]
+  wire  _io_srai_T_8 = _io_srai_T_7 & io_jalr_bit_18; // @[Library.scala 313:48]
+  wire  _io_srai_T_9 = _io_srai_T_8 & io_lui_bit_19; // @[Library.scala 316:48]
+  wire  _io_srai_T_10 = _io_srai_T_9 & io_lui_bit_25; // @[Library.scala 313:48]
+  wire  _io_srai_T_11 = _io_srai_T_9 & io_lui_bit_25 & io_auipc_bit_26; // @[Library.scala 313:48]
+  wire  _io_srai_T_12 = _io_srai_T_11 & io_lui_bit_27; // @[Library.scala 316:48]
+  wire  _io_srai_T_14 = _io_srai_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 313:48]
   wire  _io_add_T_10 = io_fence_bit & io_fence_bit_1 & io_fence_bit_2 & io_fence_bit_3 & io_slli_bit_4 & io_slli_bit_5
-     & io_slli_bit_6 & io_jalr_bit_17 & io_jalr_bit_18 & io_jalr_bit_19 & io_lui_bit_25; // @[Library.scala 311:48]
-  wire  _io_add_T_12 = _io_add_T_10 & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 314:48]
-  wire  _io_add_T_14 = _io_add_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 311:48]
+     & io_slli_bit_6 & io_jalr_bit_17 & io_jalr_bit_18 & io_jalr_bit_19 & io_lui_bit_25; // @[Library.scala 313:48]
+  wire  _io_add_T_12 = _io_add_T_10 & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 316:48]
+  wire  _io_add_T_14 = _io_add_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 313:48]
   wire  _io_sub_T_10 = _io_srai_T_1 & io_fence_bit_2 & io_fence_bit_3 & io_slli_bit_4 & io_slli_bit_5 & io_slli_bit_6 &
-    io_jalr_bit_17 & io_jalr_bit_18 & io_jalr_bit_19 & io_lui_bit_25; // @[Library.scala 311:48]
-  wire  _io_sub_T_12 = _io_sub_T_10 & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 314:48]
-  wire  _io_sub_T_14 = _io_sub_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 311:48]
-  wire  _io_slt_T_8 = _io_slli_T_7 & io_lui_bit_18; // @[Library.scala 314:48]
-  wire  _io_slt_T_10 = _io_slt_T_8 & io_jalr_bit_19 & io_lui_bit_25; // @[Library.scala 311:48]
-  wire  _io_slt_T_12 = _io_slt_T_10 & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 314:48]
-  wire  _io_slt_T_14 = _io_slt_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 311:48]
-  wire  _io_sltu_T_9 = _io_slli_T_7 & io_lui_bit_18 & io_lui_bit_19; // @[Library.scala 314:48]
-  wire  _io_sltu_T_10 = _io_sltu_T_9 & io_lui_bit_25; // @[Library.scala 311:48]
-  wire  _io_sltu_T_12 = _io_sltu_T_10 & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 314:48]
-  wire  _io_sltu_T_14 = _io_sltu_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 311:48]
-  wire  _io_xor_T_10 = _io_srli_T_7 & io_jalr_bit_18 & io_jalr_bit_19 & io_lui_bit_25; // @[Library.scala 311:48]
-  wire  _io_xor_T_12 = _io_xor_T_10 & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 314:48]
-  wire  _io_xor_T_14 = _io_xor_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 311:48]
-  wire  _io_or_T_8 = _io_slli_T_6 & io_lui_bit_17 & io_lui_bit_18; // @[Library.scala 314:48]
-  wire  _io_or_T_10 = _io_or_T_8 & io_jalr_bit_19 & io_lui_bit_25; // @[Library.scala 311:48]
-  wire  _io_or_T_12 = _io_or_T_10 & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 314:48]
-  wire  _io_or_T_14 = _io_or_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 311:48]
-  wire  _io_and_T_9 = _io_slli_T_6 & io_lui_bit_17 & io_lui_bit_18 & io_lui_bit_19; // @[Library.scala 314:48]
-  wire  _io_and_T_10 = _io_and_T_9 & io_lui_bit_25; // @[Library.scala 311:48]
-  wire  _io_and_T_12 = _io_and_T_10 & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 314:48]
-  wire  _io_and_T_14 = _io_and_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 311:48]
-  wire  _io_sll_T_12 = _io_slli_T_10 & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 314:48]
-  wire  _io_sll_T_14 = _io_sll_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 311:48]
-  wire  _io_srl_T_12 = _io_srli_T_10 & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 314:48]
-  wire  _io_srl_T_14 = _io_srl_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 311:48]
-  wire  _io_sra_T_12 = _io_srai_T_10 & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 314:48]
-  wire  _io_sra_T_14 = _io_sra_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 311:48]
-  wire  _io_mul_T_6 = _io_slli_T_5 & io_lui_bit_6; // @[Library.scala 314:48]
-  wire  _io_mul_T_7 = _io_mul_T_6 & io_jalr_bit_17; // @[Library.scala 311:48]
-  wire  _io_mul_T_8 = _io_mul_T_6 & io_jalr_bit_17 & io_jalr_bit_18; // @[Library.scala 311:48]
-  wire  _io_mul_T_10 = _io_mul_T_6 & io_jalr_bit_17 & io_jalr_bit_18 & io_jalr_bit_19 & io_lui_bit_25; // @[Library.scala 311:48]
-  wire  _io_mul_T_12 = _io_mul_T_10 & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 314:48]
-  wire  _io_mul_T_14 = _io_mul_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 311:48]
-  wire  _io_mulh_T_9 = _io_mul_T_8 & io_lui_bit_19; // @[Library.scala 314:48]
-  wire  _io_mulh_T_10 = _io_mulh_T_9 & io_lui_bit_25; // @[Library.scala 311:48]
-  wire  _io_mulh_T_12 = _io_mulh_T_10 & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 314:48]
-  wire  _io_mulh_T_14 = _io_mulh_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 311:48]
-  wire  _io_mulhsu_T_8 = _io_mul_T_7 & io_lui_bit_18; // @[Library.scala 314:48]
-  wire  _io_mulhsu_T_10 = _io_mulhsu_T_8 & io_jalr_bit_19 & io_lui_bit_25; // @[Library.scala 311:48]
-  wire  _io_mulhsu_T_12 = _io_mulhsu_T_10 & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 314:48]
-  wire  _io_mulhsu_T_14 = _io_mulhsu_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 311:48]
-  wire  _io_mulhu_T_9 = _io_mul_T_7 & io_lui_bit_18 & io_lui_bit_19; // @[Library.scala 314:48]
-  wire  _io_mulhu_T_10 = _io_mulhu_T_9 & io_lui_bit_25; // @[Library.scala 311:48]
-  wire  _io_mulhu_T_12 = _io_mulhu_T_10 & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 314:48]
-  wire  _io_mulhu_T_14 = _io_mulhu_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 311:48]
-  wire  _io_mulhr_T_2 = _io_fence_T_1 & io_lui_bit_2; // @[Library.scala 314:48]
-  wire  _io_mulhr_T_4 = _io_mulhr_T_2 & io_fence_bit_3 & io_slli_bit_4; // @[Library.scala 311:48]
-  wire  _io_mulhr_T_5 = _io_mulhr_T_2 & io_fence_bit_3 & io_slli_bit_4 & io_slli_bit_5; // @[Library.scala 311:48]
-  wire  _io_mulhr_T_6 = _io_mulhr_T_5 & io_lui_bit_6; // @[Library.scala 314:48]
-  wire  _io_mulhr_T_7 = _io_mulhr_T_6 & io_jalr_bit_17; // @[Library.scala 311:48]
-  wire  _io_mulhr_T_8 = _io_mulhr_T_6 & io_jalr_bit_17 & io_jalr_bit_18; // @[Library.scala 311:48]
-  wire  _io_mulhr_T_9 = _io_mulhr_T_8 & io_lui_bit_19; // @[Library.scala 314:48]
-  wire  _io_mulhr_T_10 = _io_mulhr_T_9 & io_lui_bit_25; // @[Library.scala 311:48]
-  wire  _io_mulhr_T_12 = _io_mulhr_T_10 & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 314:48]
-  wire  _io_mulhr_T_14 = _io_mulhr_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 311:48]
-  wire  _io_mulhsur_T_8 = _io_mulhr_T_7 & io_lui_bit_18; // @[Library.scala 314:48]
-  wire  _io_mulhsur_T_10 = _io_mulhsur_T_8 & io_jalr_bit_19 & io_lui_bit_25; // @[Library.scala 311:48]
-  wire  _io_mulhsur_T_12 = _io_mulhsur_T_10 & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 314:48]
-  wire  _io_mulhsur_T_14 = _io_mulhsur_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 311:48]
-  wire  _io_mulhur_T_9 = _io_mulhr_T_7 & io_lui_bit_18 & io_lui_bit_19; // @[Library.scala 314:48]
-  wire  _io_mulhur_T_10 = _io_mulhur_T_9 & io_lui_bit_25; // @[Library.scala 311:48]
-  wire  _io_mulhur_T_12 = _io_mulhur_T_10 & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 314:48]
-  wire  _io_mulhur_T_14 = _io_mulhur_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 311:48]
-  wire  _io_dmulh_T_5 = _io_slli_T_4 & io_lui_bit_5; // @[Library.scala 314:48]
-  wire  _io_dmulh_T_8 = _io_dmulh_T_5 & io_slli_bit_6 & io_jalr_bit_17 & io_jalr_bit_18; // @[Library.scala 311:48]
-  wire  _io_dmulh_T_9 = _io_dmulh_T_8 & io_lui_bit_19; // @[Library.scala 314:48]
-  wire  _io_dmulh_T_10 = _io_dmulh_T_9 & io_lui_bit_25; // @[Library.scala 311:48]
-  wire  _io_dmulh_T_12 = _io_dmulh_T_10 & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 314:48]
-  wire  _io_dmulh_T_14 = _io_dmulh_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 311:48]
-  wire  _io_dmulhr_T_5 = _io_mulhr_T_4 & io_lui_bit_5; // @[Library.scala 314:48]
-  wire  _io_dmulhr_T_8 = _io_dmulhr_T_5 & io_slli_bit_6 & io_jalr_bit_17 & io_jalr_bit_18; // @[Library.scala 311:48]
-  wire  _io_dmulhr_T_9 = _io_dmulhr_T_8 & io_lui_bit_19; // @[Library.scala 314:48]
-  wire  _io_dmulhr_T_10 = _io_dmulhr_T_9 & io_lui_bit_25; // @[Library.scala 311:48]
-  wire  _io_dmulhr_T_12 = _io_dmulhr_T_10 & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 314:48]
-  wire  _io_dmulhr_T_14 = _io_dmulhr_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 311:48]
-  wire  _io_fsub_T_4 = _io_fence_T_3 & io_lui_bit_4; // @[Library.scala 314:48]
-  wire  _io_fsub_T_5 = _io_fsub_T_4 & io_slli_bit_5; // @[Library.scala 311:48]
-  wire  _io_fmul_T_3 = _io_fence_T_2 & io_lui_bit_3; // @[Library.scala 314:48]
-  wire  _io_fsqrt_T_3 = _io_srai_T_2 & io_lui_bit_3; // @[Library.scala 314:48]
-  wire  io_fcvtws_bit_7 = ~io_lui_bit_7; // @[Library.scala 310:19]
-  wire  io_fcvtws_bit_8 = ~io_lui_bit_8; // @[Library.scala 310:19]
-  wire  io_fcvtws_bit_9 = ~io_lui_bit_9; // @[Library.scala 310:19]
-  wire  io_fcvtws_bit_10 = ~io_lui_bit_10; // @[Library.scala 310:19]
-  wire  io_fcvtws_bit_11 = ~io_inst[20]; // @[Library.scala 310:19]
-  wire  _io_clb_T_2 = io_fence_bit & io_lui_bit_1 & io_lui_bit_2; // @[Library.scala 314:48]
-  wire  _io_clb_T_7 = _io_clb_T_2 & io_fence_bit_3 & io_slli_bit_4 & io_slli_bit_5 & io_slli_bit_6 & io_fcvtws_bit_7; // @[Library.scala 311:48]
-  wire  _io_clb_T_8 = _io_clb_T_7 & io_lui_bit_8; // @[Library.scala 314:48]
-  wire  _io_clb_T_13 = _io_clb_T_8 & io_fcvtws_bit_9 & io_fcvtws_bit_10 & io_fcvtws_bit_11 & io_jalr_bit_17 &
-    io_jalr_bit_18; // @[Library.scala 311:48]
-  wire  _io_clb_T_14 = _io_clb_T_13 & io_lui_bit_19; // @[Library.scala 314:48]
-  wire  _io_clb_T_16 = _io_clb_T_14 & io_lui_bit_25 & io_auipc_bit_26; // @[Library.scala 311:48]
-  wire  _io_clb_T_17 = _io_clb_T_16 & io_lui_bit_27; // @[Library.scala 314:48]
-  wire  _io_clb_T_19 = _io_clb_T_17 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 311:48]
-  wire  _io_clz_T_9 = _io_clb_T_2 & io_fence_bit_3 & io_slli_bit_4 & io_slli_bit_5 & io_slli_bit_6 & io_fcvtws_bit_7 &
-    io_fcvtws_bit_8 & io_fcvtws_bit_9; // @[Library.scala 311:48]
-  wire  _io_clz_T_10 = _io_clb_T_2 & io_fence_bit_3 & io_slli_bit_4 & io_slli_bit_5 & io_slli_bit_6 & io_fcvtws_bit_7 &
-    io_fcvtws_bit_8 & io_fcvtws_bit_9 & io_fcvtws_bit_10; // @[Library.scala 311:48]
-  wire  _io_clz_T_13 = _io_clb_T_2 & io_fence_bit_3 & io_slli_bit_4 & io_slli_bit_5 & io_slli_bit_6 & io_fcvtws_bit_7 &
-    io_fcvtws_bit_8 & io_fcvtws_bit_9 & io_fcvtws_bit_10 & io_fcvtws_bit_11 & io_jalr_bit_17 & io_jalr_bit_18; // @[Library.scala 311:48]
-  wire  _io_clz_T_14 = _io_clz_T_13 & io_lui_bit_19; // @[Library.scala 314:48]
-  wire  _io_clz_T_16 = _io_clz_T_14 & io_lui_bit_25 & io_auipc_bit_26; // @[Library.scala 311:48]
-  wire  _io_clz_T_17 = _io_clz_T_16 & io_lui_bit_27; // @[Library.scala 314:48]
-  wire  _io_clz_T_19 = _io_clz_T_17 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 311:48]
-  wire  _io_ctz_T_11 = _io_clz_T_10 & io_inst[20]; // @[Library.scala 314:48]
-  wire  _io_ctz_T_13 = _io_ctz_T_11 & io_jalr_bit_17 & io_jalr_bit_18; // @[Library.scala 311:48]
-  wire  _io_ctz_T_14 = _io_ctz_T_13 & io_lui_bit_19; // @[Library.scala 314:48]
-  wire  _io_ctz_T_16 = _io_ctz_T_14 & io_lui_bit_25 & io_auipc_bit_26; // @[Library.scala 311:48]
-  wire  _io_ctz_T_17 = _io_ctz_T_16 & io_lui_bit_27; // @[Library.scala 314:48]
-  wire  _io_ctz_T_19 = _io_ctz_T_17 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 311:48]
-  wire  _io_pcnt_T_10 = _io_clz_T_9 & io_lui_bit_10; // @[Library.scala 314:48]
-  wire  _io_pcnt_T_13 = _io_pcnt_T_10 & io_fcvtws_bit_11 & io_jalr_bit_17 & io_jalr_bit_18; // @[Library.scala 311:48]
-  wire  _io_pcnt_T_14 = _io_pcnt_T_13 & io_lui_bit_19; // @[Library.scala 314:48]
-  wire  _io_pcnt_T_16 = _io_pcnt_T_14 & io_lui_bit_25 & io_auipc_bit_26; // @[Library.scala 311:48]
-  wire  _io_pcnt_T_17 = _io_pcnt_T_16 & io_lui_bit_27; // @[Library.scala 314:48]
-  wire  _io_pcnt_T_19 = _io_pcnt_T_17 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 311:48]
-  wire  _io_min_T_7 = _io_fsub_T_5 & io_lui_bit_6 & io_lui_bit_17; // @[Library.scala 314:48]
-  wire  _io_min_T_8 = _io_min_T_7 & io_jalr_bit_18; // @[Library.scala 311:48]
-  wire  _io_min_T_10 = _io_min_T_7 & io_jalr_bit_18 & io_jalr_bit_19 & io_lui_bit_25; // @[Library.scala 311:48]
-  wire  _io_min_T_12 = _io_min_T_10 & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 314:48]
-  wire  _io_min_T_14 = _io_min_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 311:48]
-  wire  _io_minu_T_8 = _io_fsub_T_5 & io_lui_bit_6 & io_lui_bit_17 & io_lui_bit_18; // @[Library.scala 314:48]
-  wire  _io_minu_T_10 = _io_minu_T_8 & io_jalr_bit_19 & io_lui_bit_25; // @[Library.scala 311:48]
-  wire  _io_minu_T_12 = _io_minu_T_10 & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 314:48]
-  wire  _io_minu_T_14 = _io_minu_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 311:48]
-  wire  _io_max_T_9 = _io_min_T_8 & io_lui_bit_19; // @[Library.scala 314:48]
-  wire  _io_max_T_10 = _io_max_T_9 & io_lui_bit_25; // @[Library.scala 311:48]
-  wire  _io_max_T_12 = _io_max_T_10 & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 314:48]
-  wire  _io_max_T_14 = _io_max_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 311:48]
-  wire  _io_maxu_T_9 = _io_fsub_T_5 & io_lui_bit_6 & io_lui_bit_17 & io_lui_bit_18 & io_lui_bit_19; // @[Library.scala 314:48]
-  wire  _io_maxu_T_10 = _io_maxu_T_9 & io_lui_bit_25; // @[Library.scala 311:48]
-  wire  _io_maxu_T_12 = _io_maxu_T_10 & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 314:48]
-  wire  _io_maxu_T_14 = _io_maxu_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 311:48]
-  wire  _io_getvl_T_6 = _io_fmul_T_3 & io_jalr_bit_17 & io_jalr_bit_18 & io_jalr_bit_19; // @[Library.scala 311:48]
-  wire  _io_getvl_T_9 = _io_getvl_T_6 & io_inst[6] & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 314:48]
-  wire  _io_getvl_T_10 = _io_getvl_T_9 & io_lui_bit_28; // @[Library.scala 311:48]
-  wire  _io_getvl_T_13 = _io_getvl_T_10 & io_lui_bit_29 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 314:48]
-  wire  _io_getvl_T_15 = io_inst[26:25] != 2'h3; // @[Decode.scala 688:89]
-  wire  _io_getmaxvl_T_16 = _io_fmul_T_3 & io_fcvtws_bit_7 & io_fcvtws_bit_8 & io_fcvtws_bit_9 & io_fcvtws_bit_10 &
-    io_fcvtws_bit_11 & io_fence_bit_12 & io_fence_bit_13 & io_fence_bit_14 & io_fence_bit_15 & io_fence_bit_16 &
-    io_jalr_bit_17 & io_jalr_bit_18 & io_jalr_bit_19; // @[Library.scala 311:48]
-  wire  _io_getmaxvl_T_19 = _io_getmaxvl_T_16 & io_inst[6] & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 314:48]
-  wire  _io_getmaxvl_T_20 = _io_getmaxvl_T_19 & io_lui_bit_28; // @[Library.scala 311:48]
-  wire  _io_getmaxvl_T_23 = _io_getmaxvl_T_20 & io_lui_bit_29 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 314:48]
-  wire  _io_vld_T_4 = io_fence_bit & io_fence_bit_1 & io_fence_bit_2 & io_slli_bit_6 & io_jalr_bit_17; // @[Library.scala 311:48]
-  wire  _io_vst_T_4 = _io_mulhr_T_2 & io_slli_bit_6 & io_jalr_bit_17; // @[Library.scala 311:48]
-  wire  _io_vst_T_9 = _io_vst_T_4 & io_lui_bit_27 & io_inst[3] & io_lui_bit_29 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 314:48]
-  wire  _io_vst_T_14 = _io_clb_T_2 & io_slli_bit_6 & io_jalr_bit_17; // @[Library.scala 311:48]
-  wire  _io_vst_T_19 = _io_vst_T_14 & io_lui_bit_27 & io_inst[3] & io_lui_bit_29 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 314:48]
-  wire  _vconv_T_17 = _io_fsqrt_T_3 & io_slli_bit_4 & io_slli_bit_5 & io_slli_bit_6 & io_fcvtws_bit_7 & io_fcvtws_bit_8
-     & io_fcvtws_bit_9 & io_fcvtws_bit_10 & io_fcvtws_bit_11 & io_fence_bit_12 & io_fence_bit_13 & io_fence_bit_14 &
-    io_fence_bit_15 & io_fence_bit_16 & io_jalr_bit_17; // @[Library.scala 311:48]
-  wire  vconv = _vconv_T_17 & io_lui_bit_27 & io_inst[3] & io_lui_bit_29 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 314:48]
+    io_jalr_bit_17 & io_jalr_bit_18 & io_jalr_bit_19 & io_lui_bit_25; // @[Library.scala 313:48]
+  wire  _io_sub_T_12 = _io_sub_T_10 & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 316:48]
+  wire  _io_sub_T_14 = _io_sub_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 313:48]
+  wire  _io_slt_T_8 = _io_slli_T_7 & io_lui_bit_18; // @[Library.scala 316:48]
+  wire  _io_slt_T_10 = _io_slt_T_8 & io_jalr_bit_19 & io_lui_bit_25; // @[Library.scala 313:48]
+  wire  _io_slt_T_12 = _io_slt_T_10 & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 316:48]
+  wire  _io_slt_T_14 = _io_slt_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 313:48]
+  wire  _io_sltu_T_9 = _io_slli_T_7 & io_lui_bit_18 & io_lui_bit_19; // @[Library.scala 316:48]
+  wire  _io_sltu_T_10 = _io_sltu_T_9 & io_lui_bit_25; // @[Library.scala 313:48]
+  wire  _io_sltu_T_12 = _io_sltu_T_10 & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 316:48]
+  wire  _io_sltu_T_14 = _io_sltu_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 313:48]
+  wire  _io_xor_T_10 = _io_srli_T_7 & io_jalr_bit_18 & io_jalr_bit_19 & io_lui_bit_25; // @[Library.scala 313:48]
+  wire  _io_xor_T_12 = _io_xor_T_10 & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 316:48]
+  wire  _io_xor_T_14 = _io_xor_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 313:48]
+  wire  _io_or_T_8 = _io_slli_T_6 & io_lui_bit_17 & io_lui_bit_18; // @[Library.scala 316:48]
+  wire  _io_or_T_10 = _io_or_T_8 & io_jalr_bit_19 & io_lui_bit_25; // @[Library.scala 313:48]
+  wire  _io_or_T_12 = _io_or_T_10 & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 316:48]
+  wire  _io_or_T_14 = _io_or_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 313:48]
+  wire  _io_and_T_9 = _io_slli_T_6 & io_lui_bit_17 & io_lui_bit_18 & io_lui_bit_19; // @[Library.scala 316:48]
+  wire  _io_and_T_10 = _io_and_T_9 & io_lui_bit_25; // @[Library.scala 313:48]
+  wire  _io_and_T_12 = _io_and_T_10 & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 316:48]
+  wire  _io_and_T_14 = _io_and_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 313:48]
+  wire  _io_sll_T_12 = _io_slli_T_10 & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 316:48]
+  wire  _io_sll_T_14 = _io_sll_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 313:48]
+  wire  _io_srl_T_12 = _io_srli_T_10 & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 316:48]
+  wire  _io_srl_T_14 = _io_srl_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 313:48]
+  wire  _io_sra_T_12 = _io_srai_T_10 & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 316:48]
+  wire  _io_sra_T_14 = _io_sra_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 313:48]
+  wire  _io_mul_T_6 = _io_slli_T_5 & io_lui_bit_6; // @[Library.scala 316:48]
+  wire  _io_mul_T_7 = _io_mul_T_6 & io_jalr_bit_17; // @[Library.scala 313:48]
+  wire  _io_mul_T_8 = _io_mul_T_6 & io_jalr_bit_17 & io_jalr_bit_18; // @[Library.scala 313:48]
+  wire  _io_mul_T_10 = _io_mul_T_6 & io_jalr_bit_17 & io_jalr_bit_18 & io_jalr_bit_19 & io_lui_bit_25; // @[Library.scala 313:48]
+  wire  _io_mul_T_12 = _io_mul_T_10 & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 316:48]
+  wire  _io_mul_T_14 = _io_mul_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 313:48]
+  wire  _io_mulh_T_9 = _io_mul_T_8 & io_lui_bit_19; // @[Library.scala 316:48]
+  wire  _io_mulh_T_10 = _io_mulh_T_9 & io_lui_bit_25; // @[Library.scala 313:48]
+  wire  _io_mulh_T_12 = _io_mulh_T_10 & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 316:48]
+  wire  _io_mulh_T_14 = _io_mulh_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 313:48]
+  wire  _io_mulhsu_T_8 = _io_mul_T_7 & io_lui_bit_18; // @[Library.scala 316:48]
+  wire  _io_mulhsu_T_10 = _io_mulhsu_T_8 & io_jalr_bit_19 & io_lui_bit_25; // @[Library.scala 313:48]
+  wire  _io_mulhsu_T_12 = _io_mulhsu_T_10 & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 316:48]
+  wire  _io_mulhsu_T_14 = _io_mulhsu_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 313:48]
+  wire  _io_mulhu_T_9 = _io_mul_T_7 & io_lui_bit_18 & io_lui_bit_19; // @[Library.scala 316:48]
+  wire  _io_mulhu_T_10 = _io_mulhu_T_9 & io_lui_bit_25; // @[Library.scala 313:48]
+  wire  _io_mulhu_T_12 = _io_mulhu_T_10 & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 316:48]
+  wire  _io_mulhu_T_14 = _io_mulhu_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 313:48]
+  wire  _io_mulhr_T_2 = _io_fence_T_1 & io_lui_bit_2; // @[Library.scala 316:48]
+  wire  _io_mulhr_T_4 = _io_mulhr_T_2 & io_fence_bit_3 & io_slli_bit_4; // @[Library.scala 313:48]
+  wire  _io_mulhr_T_5 = _io_mulhr_T_2 & io_fence_bit_3 & io_slli_bit_4 & io_slli_bit_5; // @[Library.scala 313:48]
+  wire  _io_mulhr_T_6 = _io_mulhr_T_5 & io_lui_bit_6; // @[Library.scala 316:48]
+  wire  _io_mulhr_T_7 = _io_mulhr_T_6 & io_jalr_bit_17; // @[Library.scala 313:48]
+  wire  _io_mulhr_T_8 = _io_mulhr_T_6 & io_jalr_bit_17 & io_jalr_bit_18; // @[Library.scala 313:48]
+  wire  _io_mulhr_T_9 = _io_mulhr_T_8 & io_lui_bit_19; // @[Library.scala 316:48]
+  wire  _io_mulhr_T_10 = _io_mulhr_T_9 & io_lui_bit_25; // @[Library.scala 313:48]
+  wire  _io_mulhr_T_12 = _io_mulhr_T_10 & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 316:48]
+  wire  _io_mulhr_T_14 = _io_mulhr_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 313:48]
+  wire  _io_mulhsur_T_8 = _io_mulhr_T_7 & io_lui_bit_18; // @[Library.scala 316:48]
+  wire  _io_mulhsur_T_10 = _io_mulhsur_T_8 & io_jalr_bit_19 & io_lui_bit_25; // @[Library.scala 313:48]
+  wire  _io_mulhsur_T_12 = _io_mulhsur_T_10 & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 316:48]
+  wire  _io_mulhsur_T_14 = _io_mulhsur_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 313:48]
+  wire  _io_mulhur_T_9 = _io_mulhr_T_7 & io_lui_bit_18 & io_lui_bit_19; // @[Library.scala 316:48]
+  wire  _io_mulhur_T_10 = _io_mulhur_T_9 & io_lui_bit_25; // @[Library.scala 313:48]
+  wire  _io_mulhur_T_12 = _io_mulhur_T_10 & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 316:48]
+  wire  _io_mulhur_T_14 = _io_mulhur_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 313:48]
+  wire  _io_dmulh_T_5 = _io_slli_T_4 & io_lui_bit_5; // @[Library.scala 316:48]
+  wire  _io_dmulh_T_8 = _io_dmulh_T_5 & io_slli_bit_6 & io_jalr_bit_17 & io_jalr_bit_18; // @[Library.scala 313:48]
+  wire  _io_dmulh_T_9 = _io_dmulh_T_8 & io_lui_bit_19; // @[Library.scala 316:48]
+  wire  _io_dmulh_T_10 = _io_dmulh_T_9 & io_lui_bit_25; // @[Library.scala 313:48]
+  wire  _io_dmulh_T_12 = _io_dmulh_T_10 & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 316:48]
+  wire  _io_dmulh_T_14 = _io_dmulh_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 313:48]
+  wire  _io_dmulhr_T_5 = _io_mulhr_T_4 & io_lui_bit_5; // @[Library.scala 316:48]
+  wire  _io_dmulhr_T_8 = _io_dmulhr_T_5 & io_slli_bit_6 & io_jalr_bit_17 & io_jalr_bit_18; // @[Library.scala 313:48]
+  wire  _io_dmulhr_T_9 = _io_dmulhr_T_8 & io_lui_bit_19; // @[Library.scala 316:48]
+  wire  _io_dmulhr_T_10 = _io_dmulhr_T_9 & io_lui_bit_25; // @[Library.scala 313:48]
+  wire  _io_dmulhr_T_12 = _io_dmulhr_T_10 & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 316:48]
+  wire  _io_dmulhr_T_14 = _io_dmulhr_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 313:48]
+  wire  _io_clz_T_2 = io_fence_bit & io_lui_bit_1 & io_lui_bit_2; // @[Library.scala 316:48]
+  wire  io_clz_bit_7 = ~io_lui_bit_7; // @[Library.scala 312:19]
+  wire  io_clz_bit_8 = ~io_lui_bit_8; // @[Library.scala 312:19]
+  wire  io_clz_bit_9 = ~io_lui_bit_9; // @[Library.scala 312:19]
+  wire  _io_clz_T_9 = _io_clz_T_2 & io_fence_bit_3 & io_slli_bit_4 & io_slli_bit_5 & io_slli_bit_6 & io_clz_bit_7 &
+    io_clz_bit_8 & io_clz_bit_9; // @[Library.scala 313:48]
+  wire  io_clz_bit_10 = ~io_lui_bit_10; // @[Library.scala 312:19]
+  wire  _io_clz_T_10 = _io_clz_T_2 & io_fence_bit_3 & io_slli_bit_4 & io_slli_bit_5 & io_slli_bit_6 & io_clz_bit_7 &
+    io_clz_bit_8 & io_clz_bit_9 & io_clz_bit_10; // @[Library.scala 313:48]
+  wire  io_clz_bit_11 = ~io_inst[20]; // @[Library.scala 312:19]
+  wire  _io_clz_T_13 = _io_clz_T_2 & io_fence_bit_3 & io_slli_bit_4 & io_slli_bit_5 & io_slli_bit_6 & io_clz_bit_7 &
+    io_clz_bit_8 & io_clz_bit_9 & io_clz_bit_10 & io_clz_bit_11 & io_jalr_bit_17 & io_jalr_bit_18; // @[Library.scala 313:48]
+  wire  _io_clz_T_14 = _io_clz_T_13 & io_lui_bit_19; // @[Library.scala 316:48]
+  wire  _io_clz_T_16 = _io_clz_T_14 & io_lui_bit_25 & io_auipc_bit_26; // @[Library.scala 313:48]
+  wire  _io_clz_T_17 = _io_clz_T_16 & io_lui_bit_27; // @[Library.scala 316:48]
+  wire  _io_clz_T_19 = _io_clz_T_17 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 313:48]
+  wire  _io_ctz_T_11 = _io_clz_T_10 & io_inst[20]; // @[Library.scala 316:48]
+  wire  _io_ctz_T_13 = _io_ctz_T_11 & io_jalr_bit_17 & io_jalr_bit_18; // @[Library.scala 313:48]
+  wire  _io_ctz_T_14 = _io_ctz_T_13 & io_lui_bit_19; // @[Library.scala 316:48]
+  wire  _io_ctz_T_16 = _io_ctz_T_14 & io_lui_bit_25 & io_auipc_bit_26; // @[Library.scala 313:48]
+  wire  _io_ctz_T_17 = _io_ctz_T_16 & io_lui_bit_27; // @[Library.scala 316:48]
+  wire  _io_ctz_T_19 = _io_ctz_T_17 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 313:48]
+  wire  _io_pcnt_T_10 = _io_clz_T_9 & io_lui_bit_10; // @[Library.scala 316:48]
+  wire  _io_pcnt_T_13 = _io_pcnt_T_10 & io_clz_bit_11 & io_jalr_bit_17 & io_jalr_bit_18; // @[Library.scala 313:48]
+  wire  _io_pcnt_T_14 = _io_pcnt_T_13 & io_lui_bit_19; // @[Library.scala 316:48]
+  wire  _io_pcnt_T_16 = _io_pcnt_T_14 & io_lui_bit_25 & io_auipc_bit_26; // @[Library.scala 313:48]
+  wire  _io_pcnt_T_17 = _io_pcnt_T_16 & io_lui_bit_27; // @[Library.scala 316:48]
+  wire  _io_pcnt_T_19 = _io_pcnt_T_17 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 313:48]
+  wire  _io_min_T_4 = _io_fence_T_3 & io_lui_bit_4; // @[Library.scala 316:48]
+  wire  _io_min_T_5 = _io_min_T_4 & io_slli_bit_5; // @[Library.scala 313:48]
+  wire  _io_min_T_7 = _io_min_T_5 & io_lui_bit_6 & io_lui_bit_17; // @[Library.scala 316:48]
+  wire  _io_min_T_8 = _io_min_T_7 & io_jalr_bit_18; // @[Library.scala 313:48]
+  wire  _io_min_T_10 = _io_min_T_7 & io_jalr_bit_18 & io_jalr_bit_19 & io_lui_bit_25; // @[Library.scala 313:48]
+  wire  _io_min_T_12 = _io_min_T_10 & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 316:48]
+  wire  _io_min_T_14 = _io_min_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 313:48]
+  wire  _io_minu_T_9 = _io_min_T_8 & io_lui_bit_19; // @[Library.scala 316:48]
+  wire  _io_minu_T_10 = _io_minu_T_9 & io_lui_bit_25; // @[Library.scala 313:48]
+  wire  _io_minu_T_12 = _io_minu_T_10 & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 316:48]
+  wire  _io_minu_T_14 = _io_minu_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 313:48]
+  wire  _io_max_T_8 = _io_min_T_5 & io_lui_bit_6 & io_lui_bit_17 & io_lui_bit_18; // @[Library.scala 316:48]
+  wire  _io_max_T_10 = _io_max_T_8 & io_jalr_bit_19 & io_lui_bit_25; // @[Library.scala 313:48]
+  wire  _io_max_T_12 = _io_max_T_10 & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 316:48]
+  wire  _io_max_T_14 = _io_max_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 313:48]
+  wire  _io_maxu_T_9 = _io_min_T_5 & io_lui_bit_6 & io_lui_bit_17 & io_lui_bit_18 & io_lui_bit_19; // @[Library.scala 316:48]
+  wire  _io_maxu_T_10 = _io_maxu_T_9 & io_lui_bit_25; // @[Library.scala 313:48]
+  wire  _io_maxu_T_12 = _io_maxu_T_10 & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 316:48]
+  wire  _io_maxu_T_14 = _io_maxu_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 313:48]
+  wire  _io_getvl_T_3 = _io_fence_T_2 & io_lui_bit_3; // @[Library.scala 316:48]
+  wire  _io_getvl_T_6 = _io_getvl_T_3 & io_jalr_bit_17 & io_jalr_bit_18 & io_jalr_bit_19; // @[Library.scala 313:48]
+  wire  _io_getvl_T_9 = _io_getvl_T_6 & io_inst[6] & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 316:48]
+  wire  _io_getvl_T_10 = _io_getvl_T_9 & io_lui_bit_28; // @[Library.scala 313:48]
+  wire  _io_getvl_T_13 = _io_getvl_T_10 & io_lui_bit_29 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 316:48]
+  wire  _io_getvl_T_15 = io_inst[26:25] != 2'h3; // @[Decode.scala 565:89]
+  wire  _io_getmaxvl_T_16 = _io_getvl_T_3 & io_clz_bit_7 & io_clz_bit_8 & io_clz_bit_9 & io_clz_bit_10 & io_clz_bit_11
+     & io_fence_bit_12 & io_fence_bit_13 & io_fence_bit_14 & io_fence_bit_15 & io_fence_bit_16 & io_jalr_bit_17 &
+    io_jalr_bit_18 & io_jalr_bit_19; // @[Library.scala 313:48]
+  wire  _io_getmaxvl_T_19 = _io_getmaxvl_T_16 & io_inst[6] & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 316:48]
+  wire  _io_getmaxvl_T_20 = _io_getmaxvl_T_19 & io_lui_bit_28; // @[Library.scala 313:48]
+  wire  _io_getmaxvl_T_23 = _io_getmaxvl_T_20 & io_lui_bit_29 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 316:48]
+  wire  _io_vld_T_4 = io_fence_bit & io_fence_bit_1 & io_fence_bit_2 & io_slli_bit_6 & io_jalr_bit_17; // @[Library.scala 313:48]
+  wire  _io_vst_T_4 = _io_mulhr_T_2 & io_slli_bit_6 & io_jalr_bit_17; // @[Library.scala 313:48]
+  wire  _io_vst_T_9 = _io_vst_T_4 & io_lui_bit_27 & io_inst[3] & io_lui_bit_29 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 316:48]
+  wire  _io_vst_T_14 = _io_clz_T_2 & io_slli_bit_6 & io_jalr_bit_17; // @[Library.scala 313:48]
+  wire  _io_vst_T_19 = _io_vst_T_14 & io_lui_bit_27 & io_inst[3] & io_lui_bit_29 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 316:48]
+  wire  _vconv_T_3 = _io_srai_T_2 & io_lui_bit_3; // @[Library.scala 316:48]
+  wire  _vconv_T_17 = _vconv_T_3 & io_slli_bit_4 & io_slli_bit_5 & io_slli_bit_6 & io_clz_bit_7 & io_clz_bit_8 &
+    io_clz_bit_9 & io_clz_bit_10 & io_clz_bit_11 & io_fence_bit_12 & io_fence_bit_13 & io_fence_bit_14 & io_fence_bit_15
+     & io_fence_bit_16 & io_jalr_bit_17; // @[Library.scala 313:48]
+  wire  vconv = _vconv_T_17 & io_lui_bit_27 & io_inst[3] & io_lui_bit_29 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 316:48]
   wire  _vdup_T_11 = _io_srai_T_1 & io_fence_bit_2 & io_fence_bit_3 & io_slli_bit_4 & io_slli_bit_6 & io_fence_bit_12 &
-    io_fence_bit_13 & io_fence_bit_14 & io_fence_bit_15 & io_fence_bit_16 & io_jalr_bit_17; // @[Library.scala 311:48]
-  wire  _vdup_T_16 = _vdup_T_11 & io_lui_bit_27 & io_inst[3] & io_lui_bit_29 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 314:48]
-  wire  vdup = _vdup_T_16 & io_inst[13:12] <= 2'h2; // @[Decode.scala 701:72]
-  wire  vdupi = vdup & io_slli_bit_5; // @[Decode.scala 702:20]
-  wire  vdupf = vdup & io_lui_bit_5; // @[Decode.scala 703:20]
-  wire  _vfma_T_1 = ~io_lui_bit_31; // @[Decode.scala 706:21]
-  wire  vfma = ~io_lui_bit_31 & io_inst[4:2] == 3'h5; // @[Decode.scala 706:29]
-  wire  _vfma4_T_1 = io_inst[1:0] == 2'h1; // @[Decode.scala 707:23]
-  wire [3:0] _vfma4_T_4 = {io_inst[13:12],io_inst[4:3]}; // @[Cat.scala 31:58]
-  wire  vfma4 = io_inst[1:0] == 2'h1 & _vfma4_T_4 == 4'h0; // @[Decode.scala 707:31]
-  wire  _io_viop_T_7 = _vfma4_T_1 & ~vfma4; // @[Decode.scala 712:30]
-  wire  _io_viop_T_8 = _vfma_T_1 & ~vfma | _io_viop_T_7; // @[Decode.scala 711:37]
-  wire  _io_viop_T_9 = _io_viop_T_8 | vconv; // @[Decode.scala 712:40]
-  wire [5:0] decoded_lo_lo_lo_lo = {io_mpause,io_mret,io_fencei,io_flushat,io_flushall,io_slog}; // @[Cat.scala 31:58]
-  wire [12:0] decoded_lo_lo_lo = {io_getvl,io_getmaxvl,io_ebreak,io_ecall,io_eexit,io_eyield,io_ectxsw,
-    decoded_lo_lo_lo_lo}; // @[Cat.scala 31:58]
-  wire [5:0] decoded_lo_lo_hi_lo = {io_max,io_maxu,io_viop,io_vfop,io_vld,io_vst}; // @[Cat.scala 31:58]
-  wire [25:0] decoded_lo_lo = {io_fmvwx,io_clb,io_clz,io_ctz,io_pcnt,io_min,io_minu,decoded_lo_lo_hi_lo,decoded_lo_lo_lo
-    }; // @[Cat.scala 31:58]
-  wire [5:0] decoded_lo_hi_lo_lo = {io_feq,io_flt,io_fle,io_fclass,io_fcvtsw,io_fcvtswu}; // @[Cat.scala 31:58]
-  wire [12:0] decoded_lo_hi_lo = {io_fsgnjn,io_fsgnjx,io_fmin,io_fmax,io_fcvtws,io_fcvtwus,io_fmvxw,decoded_lo_hi_lo_lo}
+    io_fence_bit_13 & io_fence_bit_14 & io_fence_bit_15 & io_fence_bit_16 & io_jalr_bit_17; // @[Library.scala 313:48]
+  wire  _vdup_T_16 = _vdup_T_11 & io_lui_bit_27 & io_inst[3] & io_lui_bit_29 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 316:48]
+  wire  vdup = _vdup_T_16 & io_inst[13:12] <= 2'h2; // @[Decode.scala 578:72]
+  wire  vdupi = vdup & io_slli_bit_5; // @[Decode.scala 579:20]
+  wire  _io_viop_T_3 = io_inst[1:0] == 2'h1; // @[Decode.scala 583:22]
+  wire  _io_viop_T_4 = ~io_lui_bit_31 | _io_viop_T_3; // @[Decode.scala 582:28]
+  wire  _io_viop_T_5 = _io_viop_T_4 | vconv; // @[Decode.scala 583:30]
+  wire [9:0] decoded_lo_lo_hi = {io_minu,io_max,io_maxu,io_viop,io_vld,io_vst,io_getvl,io_getmaxvl,io_ebreak,io_ecall}; // @[Cat.scala 31:58]
+  wire [18:0] decoded_lo_lo = {decoded_lo_lo_hi,io_eexit,io_eyield,io_ectxsw,io_mpause,io_mret,io_fencei,io_flushat,
+    io_flushall,io_slog}; // @[Cat.scala 31:58]
+  wire [9:0] decoded_lo_hi_hi = {io_srl,io_sra,io_mul,io_mulh,io_mulhsu,io_mulhu,io_mulhr,io_mulhsur,io_mulhur,io_dmulh}
     ; // @[Cat.scala 31:58]
-  wire [5:0] decoded_lo_hi_hi_lo = {io_fadd,io_fsub,io_fmul,io_fdiv,io_fsqrt,io_fsgnj}; // @[Cat.scala 31:58]
-  wire [51:0] decoded_lo = {io_remu,io_flw,io_fsw,io_fmadd,io_fmsub,io_fnmsub,io_fnmadd,decoded_lo_hi_hi_lo,
-    decoded_lo_hi_lo,decoded_lo_lo}; // @[Cat.scala 31:58]
-  wire [5:0] decoded_hi_lo_lo_lo = {io_mulhur,io_dmulh,io_dmulhr,io_div,io_divu,io_rem}; // @[Cat.scala 31:58]
-  wire [12:0] decoded_hi_lo_lo = {io_sra,io_mul,io_mulh,io_mulhsu,io_mulhu,io_mulhr,io_mulhsur,decoded_hi_lo_lo_lo}; // @[Cat.scala 31:58]
-  wire [5:0] decoded_hi_lo_hi_lo = {io_and,io_slli,io_srli,io_srai,io_sll,io_srl}; // @[Cat.scala 31:58]
-  wire [25:0] decoded_hi_lo = {io_andi,io_add,io_sub,io_slt,io_sltu,io_xor,io_or,decoded_hi_lo_hi_lo,decoded_hi_lo_lo}; // @[Cat.scala 31:58]
-  wire [5:0] decoded_hi_hi_lo_lo = {io_fence,io_addi,io_slti,io_sltiu,io_xori,io_ori}; // @[Cat.scala 31:58]
-  wire [12:0] decoded_hi_hi_lo = {io_lh,io_lw,io_lbu,io_lhu,io_sb,io_sh,io_sw,decoded_hi_hi_lo_lo}; // @[Cat.scala 31:58]
-  wire [6:0] decoded_hi_hi_hi_lo = {io_bge,io_bltu,io_bgeu,io_csrrw,io_csrrs,io_csrrc,io_lb}; // @[Cat.scala 31:58]
-  wire [52:0] decoded_hi = {io_lui,io_auipc,io_jal,io_jalr,io_beq,io_bne,io_blt,decoded_hi_hi_hi_lo,decoded_hi_hi_lo,
-    decoded_hi_lo}; // @[Cat.scala 31:58]
-  wire [104:0] decoded = {decoded_hi,decoded_lo}; // @[Cat.scala 31:58]
-  wire  io_undef_value__52 = decoded[104]; // @[Library.scala 182:26]
+  wire [18:0] decoded_lo_hi = {decoded_lo_hi_hi,io_dmulhr,io_div,io_divu,io_rem,io_remu,io_clz,io_ctz,io_pcnt,io_min}; // @[Cat.scala 31:58]
+  wire [9:0] decoded_hi_lo_hi = {io_sw,io_fence,io_addi,io_slti,io_sltiu,io_xori,io_ori,io_andi,io_add,io_sub}; // @[Cat.scala 31:58]
+  wire [18:0] decoded_hi_lo = {decoded_hi_lo_hi,io_slt,io_sltu,io_xor,io_or,io_and,io_slli,io_srli,io_srai,io_sll}; // @[Cat.scala 31:58]
+  wire [9:0] decoded_hi_hi_lo = {io_csrrw,io_csrrs,io_csrrc,io_lb,io_lh,io_lw,io_lbu,io_lhu,io_sb,io_sh}; // @[Cat.scala 31:58]
+  wire [9:0] decoded_hi_hi_hi = {io_lui,io_auipc,io_jal,io_jalr,io_beq,io_bne,io_blt,io_bge,io_bltu,io_bgeu}; // @[Cat.scala 31:58]
+  wire [76:0] decoded = {decoded_hi_hi_hi,decoded_hi_hi_lo,decoded_hi_lo,decoded_lo_hi,decoded_lo_lo}; // @[Cat.scala 31:58]
+  wire  io_undef_value__38 = decoded[76]; // @[Library.scala 182:26]
   wire  io_undef_value__0 = decoded[0] | decoded[1]; // @[Library.scala 194:39]
   wire  io_undef_value__1 = decoded[2] | decoded[3]; // @[Library.scala 194:39]
   wire  io_undef_value__2 = decoded[4] | decoded[5]; // @[Library.scala 194:39]
@@ -12766,20 +11790,6 @@
   wire  io_undef_value__35 = decoded[70] | decoded[71]; // @[Library.scala 194:39]
   wire  io_undef_value__36 = decoded[72] | decoded[73]; // @[Library.scala 194:39]
   wire  io_undef_value__37 = decoded[74] | decoded[75]; // @[Library.scala 194:39]
-  wire  io_undef_value__38 = decoded[76] | decoded[77]; // @[Library.scala 194:39]
-  wire  io_undef_value__39 = decoded[78] | decoded[79]; // @[Library.scala 194:39]
-  wire  io_undef_value__40 = decoded[80] | decoded[81]; // @[Library.scala 194:39]
-  wire  io_undef_value__41 = decoded[82] | decoded[83]; // @[Library.scala 194:39]
-  wire  io_undef_value__42 = decoded[84] | decoded[85]; // @[Library.scala 194:39]
-  wire  io_undef_value__43 = decoded[86] | decoded[87]; // @[Library.scala 194:39]
-  wire  io_undef_value__44 = decoded[88] | decoded[89]; // @[Library.scala 194:39]
-  wire  io_undef_value__45 = decoded[90] | decoded[91]; // @[Library.scala 194:39]
-  wire  io_undef_value__46 = decoded[92] | decoded[93]; // @[Library.scala 194:39]
-  wire  io_undef_value__47 = decoded[94] | decoded[95]; // @[Library.scala 194:39]
-  wire  io_undef_value__48 = decoded[96] | decoded[97]; // @[Library.scala 194:39]
-  wire  io_undef_value__49 = decoded[98] | decoded[99]; // @[Library.scala 194:39]
-  wire  io_undef_value__50 = decoded[100] | decoded[101]; // @[Library.scala 194:39]
-  wire  io_undef_value__51 = decoded[102] | decoded[103]; // @[Library.scala 194:39]
   wire  io_undef_value_1_0 = io_undef_value__0 | io_undef_value__1; // @[Library.scala 194:39]
   wire  io_undef_value_1_1 = io_undef_value__2 | io_undef_value__3; // @[Library.scala 194:39]
   wire  io_undef_value_1_2 = io_undef_value__4 | io_undef_value__5; // @[Library.scala 194:39]
@@ -12799,13 +11809,6 @@
   wire  io_undef_value_1_16 = io_undef_value__32 | io_undef_value__33; // @[Library.scala 194:39]
   wire  io_undef_value_1_17 = io_undef_value__34 | io_undef_value__35; // @[Library.scala 194:39]
   wire  io_undef_value_1_18 = io_undef_value__36 | io_undef_value__37; // @[Library.scala 194:39]
-  wire  io_undef_value_1_19 = io_undef_value__38 | io_undef_value__39; // @[Library.scala 194:39]
-  wire  io_undef_value_1_20 = io_undef_value__40 | io_undef_value__41; // @[Library.scala 194:39]
-  wire  io_undef_value_1_21 = io_undef_value__42 | io_undef_value__43; // @[Library.scala 194:39]
-  wire  io_undef_value_1_22 = io_undef_value__44 | io_undef_value__45; // @[Library.scala 194:39]
-  wire  io_undef_value_1_23 = io_undef_value__46 | io_undef_value__47; // @[Library.scala 194:39]
-  wire  io_undef_value_1_24 = io_undef_value__48 | io_undef_value__49; // @[Library.scala 194:39]
-  wire  io_undef_value_1_25 = io_undef_value__50 | io_undef_value__51; // @[Library.scala 194:39]
   wire  io_undef_value_2_0 = io_undef_value_1_0 | io_undef_value_1_1; // @[Library.scala 194:39]
   wire  io_undef_value_2_1 = io_undef_value_1_2 | io_undef_value_1_3; // @[Library.scala 194:39]
   wire  io_undef_value_2_2 = io_undef_value_1_4 | io_undef_value_1_5; // @[Library.scala 194:39]
@@ -12815,282 +11818,200 @@
   wire  io_undef_value_2_6 = io_undef_value_1_12 | io_undef_value_1_13; // @[Library.scala 194:39]
   wire  io_undef_value_2_7 = io_undef_value_1_14 | io_undef_value_1_15; // @[Library.scala 194:39]
   wire  io_undef_value_2_8 = io_undef_value_1_16 | io_undef_value_1_17; // @[Library.scala 194:39]
-  wire  io_undef_value_2_9 = io_undef_value_1_18 | io_undef_value_1_19; // @[Library.scala 194:39]
-  wire  io_undef_value_2_10 = io_undef_value_1_20 | io_undef_value_1_21; // @[Library.scala 194:39]
-  wire  io_undef_value_2_11 = io_undef_value_1_22 | io_undef_value_1_23; // @[Library.scala 194:39]
-  wire  io_undef_value_2_12 = io_undef_value_1_24 | io_undef_value_1_25; // @[Library.scala 194:39]
+  wire  io_undef_value_2_9 = io_undef_value_1_18 | io_undef_value__38; // @[Library.scala 194:39]
   wire  io_undef_value_3_0 = io_undef_value_2_0 | io_undef_value_2_1; // @[Library.scala 194:39]
   wire  io_undef_value_3_1 = io_undef_value_2_2 | io_undef_value_2_3; // @[Library.scala 194:39]
   wire  io_undef_value_3_2 = io_undef_value_2_4 | io_undef_value_2_5; // @[Library.scala 194:39]
   wire  io_undef_value_3_3 = io_undef_value_2_6 | io_undef_value_2_7; // @[Library.scala 194:39]
   wire  io_undef_value_3_4 = io_undef_value_2_8 | io_undef_value_2_9; // @[Library.scala 194:39]
-  wire  io_undef_value_3_5 = io_undef_value_2_10 | io_undef_value_2_11; // @[Library.scala 194:39]
-  wire  io_undef_value_3_6 = io_undef_value_2_12 | io_undef_value__52; // @[Library.scala 194:39]
   wire  io_undef_value_4_0 = io_undef_value_3_0 | io_undef_value_3_1; // @[Library.scala 194:39]
   wire  io_undef_value_4_1 = io_undef_value_3_2 | io_undef_value_3_3; // @[Library.scala 194:39]
-  wire  io_undef_value_4_2 = io_undef_value_3_4 | io_undef_value_3_5; // @[Library.scala 194:39]
   wire  io_undef_value_5_0 = io_undef_value_4_0 | io_undef_value_4_1; // @[Library.scala 194:39]
-  wire  io_undef_value_5_1 = io_undef_value_4_2 | io_undef_value_3_6; // @[Library.scala 194:39]
-  wire  io_undef_value_6_0 = io_undef_value_5_0 | io_undef_value_5_1; // @[Library.scala 194:39]
-  reg  onehot_failed; // @[Decode.scala 813:30]
-  wire  _T_2 = ~reset; // @[Decode.scala 814:9]
-  wire [1:0] _onehot_decode_T_105 = decoded[1] + decoded[2]; // @[Bitwise.scala 48:55]
-  wire [1:0] _GEN_1 = {{1'd0}, decoded[0]}; // @[Bitwise.scala 48:55]
-  wire [2:0] _onehot_decode_T_107 = _GEN_1 + _onehot_decode_T_105; // @[Bitwise.scala 48:55]
-  wire [1:0] _onehot_decode_T_109 = decoded[4] + decoded[5]; // @[Bitwise.scala 48:55]
-  wire [1:0] _GEN_2 = {{1'd0}, decoded[3]}; // @[Bitwise.scala 48:55]
-  wire [2:0] _onehot_decode_T_111 = _GEN_2 + _onehot_decode_T_109; // @[Bitwise.scala 48:55]
-  wire [2:0] _onehot_decode_T_113 = _onehot_decode_T_107[1:0] + _onehot_decode_T_111[1:0]; // @[Bitwise.scala 48:55]
-  wire [1:0] _onehot_decode_T_115 = decoded[7] + decoded[8]; // @[Bitwise.scala 48:55]
-  wire [1:0] _GEN_3 = {{1'd0}, decoded[6]}; // @[Bitwise.scala 48:55]
-  wire [2:0] _onehot_decode_T_117 = _GEN_3 + _onehot_decode_T_115; // @[Bitwise.scala 48:55]
-  wire [1:0] _onehot_decode_T_119 = decoded[9] + decoded[10]; // @[Bitwise.scala 48:55]
-  wire [1:0] _onehot_decode_T_121 = decoded[11] + decoded[12]; // @[Bitwise.scala 48:55]
-  wire [2:0] _onehot_decode_T_123 = _onehot_decode_T_119 + _onehot_decode_T_121; // @[Bitwise.scala 48:55]
-  wire [2:0] _GEN_4 = {{1'd0}, _onehot_decode_T_117[1:0]}; // @[Bitwise.scala 48:55]
-  wire [3:0] _onehot_decode_T_125 = _GEN_4 + _onehot_decode_T_123; // @[Bitwise.scala 48:55]
-  wire [3:0] _onehot_decode_T_127 = _onehot_decode_T_113 + _onehot_decode_T_125[2:0]; // @[Bitwise.scala 48:55]
-  wire [1:0] _onehot_decode_T_129 = decoded[14] + decoded[15]; // @[Bitwise.scala 48:55]
-  wire [1:0] _GEN_5 = {{1'd0}, decoded[13]}; // @[Bitwise.scala 48:55]
-  wire [2:0] _onehot_decode_T_131 = _GEN_5 + _onehot_decode_T_129; // @[Bitwise.scala 48:55]
-  wire [1:0] _onehot_decode_T_133 = decoded[17] + decoded[18]; // @[Bitwise.scala 48:55]
-  wire [1:0] _GEN_6 = {{1'd0}, decoded[16]}; // @[Bitwise.scala 48:55]
-  wire [2:0] _onehot_decode_T_135 = _GEN_6 + _onehot_decode_T_133; // @[Bitwise.scala 48:55]
-  wire [2:0] _onehot_decode_T_137 = _onehot_decode_T_131[1:0] + _onehot_decode_T_135[1:0]; // @[Bitwise.scala 48:55]
-  wire [1:0] _onehot_decode_T_139 = decoded[20] + decoded[21]; // @[Bitwise.scala 48:55]
-  wire [1:0] _GEN_7 = {{1'd0}, decoded[19]}; // @[Bitwise.scala 48:55]
-  wire [2:0] _onehot_decode_T_141 = _GEN_7 + _onehot_decode_T_139; // @[Bitwise.scala 48:55]
-  wire [1:0] _onehot_decode_T_143 = decoded[22] + decoded[23]; // @[Bitwise.scala 48:55]
-  wire [1:0] _onehot_decode_T_145 = decoded[24] + decoded[25]; // @[Bitwise.scala 48:55]
-  wire [2:0] _onehot_decode_T_147 = _onehot_decode_T_143 + _onehot_decode_T_145; // @[Bitwise.scala 48:55]
-  wire [2:0] _GEN_8 = {{1'd0}, _onehot_decode_T_141[1:0]}; // @[Bitwise.scala 48:55]
-  wire [3:0] _onehot_decode_T_149 = _GEN_8 + _onehot_decode_T_147; // @[Bitwise.scala 48:55]
-  wire [3:0] _onehot_decode_T_151 = _onehot_decode_T_137 + _onehot_decode_T_149[2:0]; // @[Bitwise.scala 48:55]
-  wire [4:0] _onehot_decode_T_153 = _onehot_decode_T_127 + _onehot_decode_T_151; // @[Bitwise.scala 48:55]
-  wire [1:0] _onehot_decode_T_155 = decoded[27] + decoded[28]; // @[Bitwise.scala 48:55]
-  wire [1:0] _GEN_9 = {{1'd0}, decoded[26]}; // @[Bitwise.scala 48:55]
-  wire [2:0] _onehot_decode_T_157 = _GEN_9 + _onehot_decode_T_155; // @[Bitwise.scala 48:55]
-  wire [1:0] _onehot_decode_T_159 = decoded[30] + decoded[31]; // @[Bitwise.scala 48:55]
-  wire [1:0] _GEN_10 = {{1'd0}, decoded[29]}; // @[Bitwise.scala 48:55]
-  wire [2:0] _onehot_decode_T_161 = _GEN_10 + _onehot_decode_T_159; // @[Bitwise.scala 48:55]
-  wire [2:0] _onehot_decode_T_163 = _onehot_decode_T_157[1:0] + _onehot_decode_T_161[1:0]; // @[Bitwise.scala 48:55]
-  wire [1:0] _onehot_decode_T_165 = decoded[33] + decoded[34]; // @[Bitwise.scala 48:55]
-  wire [1:0] _GEN_11 = {{1'd0}, decoded[32]}; // @[Bitwise.scala 48:55]
-  wire [2:0] _onehot_decode_T_167 = _GEN_11 + _onehot_decode_T_165; // @[Bitwise.scala 48:55]
-  wire [1:0] _onehot_decode_T_169 = decoded[35] + decoded[36]; // @[Bitwise.scala 48:55]
-  wire [1:0] _onehot_decode_T_171 = decoded[37] + decoded[38]; // @[Bitwise.scala 48:55]
-  wire [2:0] _onehot_decode_T_173 = _onehot_decode_T_169 + _onehot_decode_T_171; // @[Bitwise.scala 48:55]
-  wire [2:0] _GEN_12 = {{1'd0}, _onehot_decode_T_167[1:0]}; // @[Bitwise.scala 48:55]
-  wire [3:0] _onehot_decode_T_175 = _GEN_12 + _onehot_decode_T_173; // @[Bitwise.scala 48:55]
-  wire [3:0] _onehot_decode_T_177 = _onehot_decode_T_163 + _onehot_decode_T_175[2:0]; // @[Bitwise.scala 48:55]
-  wire [1:0] _onehot_decode_T_179 = decoded[40] + decoded[41]; // @[Bitwise.scala 48:55]
-  wire [1:0] _GEN_13 = {{1'd0}, decoded[39]}; // @[Bitwise.scala 48:55]
-  wire [2:0] _onehot_decode_T_181 = _GEN_13 + _onehot_decode_T_179; // @[Bitwise.scala 48:55]
-  wire [1:0] _onehot_decode_T_183 = decoded[43] + decoded[44]; // @[Bitwise.scala 48:55]
-  wire [1:0] _GEN_14 = {{1'd0}, decoded[42]}; // @[Bitwise.scala 48:55]
-  wire [2:0] _onehot_decode_T_185 = _GEN_14 + _onehot_decode_T_183; // @[Bitwise.scala 48:55]
-  wire [2:0] _onehot_decode_T_187 = _onehot_decode_T_181[1:0] + _onehot_decode_T_185[1:0]; // @[Bitwise.scala 48:55]
-  wire [1:0] _onehot_decode_T_189 = decoded[46] + decoded[47]; // @[Bitwise.scala 48:55]
-  wire [1:0] _GEN_15 = {{1'd0}, decoded[45]}; // @[Bitwise.scala 48:55]
-  wire [2:0] _onehot_decode_T_191 = _GEN_15 + _onehot_decode_T_189; // @[Bitwise.scala 48:55]
-  wire [1:0] _onehot_decode_T_193 = decoded[48] + decoded[49]; // @[Bitwise.scala 48:55]
-  wire [1:0] _onehot_decode_T_195 = decoded[50] + decoded[51]; // @[Bitwise.scala 48:55]
-  wire [2:0] _onehot_decode_T_197 = _onehot_decode_T_193 + _onehot_decode_T_195; // @[Bitwise.scala 48:55]
-  wire [2:0] _GEN_16 = {{1'd0}, _onehot_decode_T_191[1:0]}; // @[Bitwise.scala 48:55]
-  wire [3:0] _onehot_decode_T_199 = _GEN_16 + _onehot_decode_T_197; // @[Bitwise.scala 48:55]
-  wire [3:0] _onehot_decode_T_201 = _onehot_decode_T_187 + _onehot_decode_T_199[2:0]; // @[Bitwise.scala 48:55]
-  wire [4:0] _onehot_decode_T_203 = _onehot_decode_T_177 + _onehot_decode_T_201; // @[Bitwise.scala 48:55]
-  wire [5:0] _onehot_decode_T_205 = _onehot_decode_T_153 + _onehot_decode_T_203; // @[Bitwise.scala 48:55]
-  wire [1:0] _onehot_decode_T_207 = decoded[53] + decoded[54]; // @[Bitwise.scala 48:55]
-  wire [1:0] _GEN_17 = {{1'd0}, decoded[52]}; // @[Bitwise.scala 48:55]
-  wire [2:0] _onehot_decode_T_209 = _GEN_17 + _onehot_decode_T_207; // @[Bitwise.scala 48:55]
-  wire [1:0] _onehot_decode_T_211 = decoded[56] + decoded[57]; // @[Bitwise.scala 48:55]
-  wire [1:0] _GEN_18 = {{1'd0}, decoded[55]}; // @[Bitwise.scala 48:55]
-  wire [2:0] _onehot_decode_T_213 = _GEN_18 + _onehot_decode_T_211; // @[Bitwise.scala 48:55]
-  wire [2:0] _onehot_decode_T_215 = _onehot_decode_T_209[1:0] + _onehot_decode_T_213[1:0]; // @[Bitwise.scala 48:55]
-  wire [1:0] _onehot_decode_T_217 = decoded[59] + decoded[60]; // @[Bitwise.scala 48:55]
-  wire [1:0] _GEN_19 = {{1'd0}, decoded[58]}; // @[Bitwise.scala 48:55]
-  wire [2:0] _onehot_decode_T_219 = _GEN_19 + _onehot_decode_T_217; // @[Bitwise.scala 48:55]
-  wire [1:0] _onehot_decode_T_221 = decoded[61] + decoded[62]; // @[Bitwise.scala 48:55]
-  wire [1:0] _onehot_decode_T_223 = decoded[63] + decoded[64]; // @[Bitwise.scala 48:55]
-  wire [2:0] _onehot_decode_T_225 = _onehot_decode_T_221 + _onehot_decode_T_223; // @[Bitwise.scala 48:55]
-  wire [2:0] _GEN_20 = {{1'd0}, _onehot_decode_T_219[1:0]}; // @[Bitwise.scala 48:55]
-  wire [3:0] _onehot_decode_T_227 = _GEN_20 + _onehot_decode_T_225; // @[Bitwise.scala 48:55]
-  wire [3:0] _onehot_decode_T_229 = _onehot_decode_T_215 + _onehot_decode_T_227[2:0]; // @[Bitwise.scala 48:55]
-  wire [1:0] _onehot_decode_T_231 = decoded[66] + decoded[67]; // @[Bitwise.scala 48:55]
-  wire [1:0] _GEN_21 = {{1'd0}, decoded[65]}; // @[Bitwise.scala 48:55]
-  wire [2:0] _onehot_decode_T_233 = _GEN_21 + _onehot_decode_T_231; // @[Bitwise.scala 48:55]
-  wire [1:0] _onehot_decode_T_235 = decoded[69] + decoded[70]; // @[Bitwise.scala 48:55]
-  wire [1:0] _GEN_22 = {{1'd0}, decoded[68]}; // @[Bitwise.scala 48:55]
-  wire [2:0] _onehot_decode_T_237 = _GEN_22 + _onehot_decode_T_235; // @[Bitwise.scala 48:55]
-  wire [2:0] _onehot_decode_T_239 = _onehot_decode_T_233[1:0] + _onehot_decode_T_237[1:0]; // @[Bitwise.scala 48:55]
-  wire [1:0] _onehot_decode_T_241 = decoded[72] + decoded[73]; // @[Bitwise.scala 48:55]
-  wire [1:0] _GEN_23 = {{1'd0}, decoded[71]}; // @[Bitwise.scala 48:55]
-  wire [2:0] _onehot_decode_T_243 = _GEN_23 + _onehot_decode_T_241; // @[Bitwise.scala 48:55]
-  wire [1:0] _onehot_decode_T_245 = decoded[74] + decoded[75]; // @[Bitwise.scala 48:55]
-  wire [1:0] _onehot_decode_T_247 = decoded[76] + decoded[77]; // @[Bitwise.scala 48:55]
-  wire [2:0] _onehot_decode_T_249 = _onehot_decode_T_245 + _onehot_decode_T_247; // @[Bitwise.scala 48:55]
-  wire [2:0] _GEN_24 = {{1'd0}, _onehot_decode_T_243[1:0]}; // @[Bitwise.scala 48:55]
-  wire [3:0] _onehot_decode_T_251 = _GEN_24 + _onehot_decode_T_249; // @[Bitwise.scala 48:55]
-  wire [3:0] _onehot_decode_T_253 = _onehot_decode_T_239 + _onehot_decode_T_251[2:0]; // @[Bitwise.scala 48:55]
-  wire [4:0] _onehot_decode_T_255 = _onehot_decode_T_229 + _onehot_decode_T_253; // @[Bitwise.scala 48:55]
-  wire [1:0] _onehot_decode_T_257 = decoded[79] + decoded[80]; // @[Bitwise.scala 48:55]
-  wire [1:0] _GEN_25 = {{1'd0}, decoded[78]}; // @[Bitwise.scala 48:55]
-  wire [2:0] _onehot_decode_T_259 = _GEN_25 + _onehot_decode_T_257; // @[Bitwise.scala 48:55]
-  wire [1:0] _onehot_decode_T_261 = decoded[82] + decoded[83]; // @[Bitwise.scala 48:55]
-  wire [1:0] _GEN_26 = {{1'd0}, decoded[81]}; // @[Bitwise.scala 48:55]
-  wire [2:0] _onehot_decode_T_263 = _GEN_26 + _onehot_decode_T_261; // @[Bitwise.scala 48:55]
-  wire [2:0] _onehot_decode_T_265 = _onehot_decode_T_259[1:0] + _onehot_decode_T_263[1:0]; // @[Bitwise.scala 48:55]
-  wire [1:0] _onehot_decode_T_267 = decoded[85] + decoded[86]; // @[Bitwise.scala 48:55]
-  wire [1:0] _GEN_27 = {{1'd0}, decoded[84]}; // @[Bitwise.scala 48:55]
-  wire [2:0] _onehot_decode_T_269 = _GEN_27 + _onehot_decode_T_267; // @[Bitwise.scala 48:55]
-  wire [1:0] _onehot_decode_T_271 = decoded[87] + decoded[88]; // @[Bitwise.scala 48:55]
-  wire [1:0] _onehot_decode_T_273 = decoded[89] + decoded[90]; // @[Bitwise.scala 48:55]
-  wire [2:0] _onehot_decode_T_275 = _onehot_decode_T_271 + _onehot_decode_T_273; // @[Bitwise.scala 48:55]
-  wire [2:0] _GEN_28 = {{1'd0}, _onehot_decode_T_269[1:0]}; // @[Bitwise.scala 48:55]
-  wire [3:0] _onehot_decode_T_277 = _GEN_28 + _onehot_decode_T_275; // @[Bitwise.scala 48:55]
-  wire [3:0] _onehot_decode_T_279 = _onehot_decode_T_265 + _onehot_decode_T_277[2:0]; // @[Bitwise.scala 48:55]
-  wire [1:0] _onehot_decode_T_281 = decoded[92] + decoded[93]; // @[Bitwise.scala 48:55]
-  wire [1:0] _GEN_29 = {{1'd0}, decoded[91]}; // @[Bitwise.scala 48:55]
-  wire [2:0] _onehot_decode_T_283 = _GEN_29 + _onehot_decode_T_281; // @[Bitwise.scala 48:55]
-  wire [1:0] _onehot_decode_T_285 = decoded[94] + decoded[95]; // @[Bitwise.scala 48:55]
-  wire [1:0] _onehot_decode_T_287 = decoded[96] + decoded[97]; // @[Bitwise.scala 48:55]
-  wire [2:0] _onehot_decode_T_289 = _onehot_decode_T_285 + _onehot_decode_T_287; // @[Bitwise.scala 48:55]
-  wire [2:0] _GEN_30 = {{1'd0}, _onehot_decode_T_283[1:0]}; // @[Bitwise.scala 48:55]
-  wire [3:0] _onehot_decode_T_291 = _GEN_30 + _onehot_decode_T_289; // @[Bitwise.scala 48:55]
-  wire [1:0] _onehot_decode_T_293 = decoded[99] + decoded[100]; // @[Bitwise.scala 48:55]
-  wire [1:0] _GEN_31 = {{1'd0}, decoded[98]}; // @[Bitwise.scala 48:55]
-  wire [2:0] _onehot_decode_T_295 = _GEN_31 + _onehot_decode_T_293; // @[Bitwise.scala 48:55]
-  wire [1:0] _onehot_decode_T_297 = decoded[101] + decoded[102]; // @[Bitwise.scala 48:55]
-  wire [1:0] _onehot_decode_T_299 = decoded[103] + io_undef_value__52; // @[Bitwise.scala 48:55]
-  wire [2:0] _onehot_decode_T_301 = _onehot_decode_T_297 + _onehot_decode_T_299; // @[Bitwise.scala 48:55]
-  wire [2:0] _GEN_32 = {{1'd0}, _onehot_decode_T_295[1:0]}; // @[Bitwise.scala 48:55]
-  wire [3:0] _onehot_decode_T_303 = _GEN_32 + _onehot_decode_T_301; // @[Bitwise.scala 48:55]
-  wire [3:0] _onehot_decode_T_305 = _onehot_decode_T_291[2:0] + _onehot_decode_T_303[2:0]; // @[Bitwise.scala 48:55]
-  wire [4:0] _onehot_decode_T_307 = _onehot_decode_T_279 + _onehot_decode_T_305; // @[Bitwise.scala 48:55]
-  wire [5:0] _onehot_decode_T_309 = _onehot_decode_T_255 + _onehot_decode_T_307; // @[Bitwise.scala 48:55]
-  wire [6:0] onehot_decode = _onehot_decode_T_205 + _onehot_decode_T_309; // @[Bitwise.scala 48:55]
-  wire [6:0] _GEN_33 = {{6'd0}, io_undef}; // @[Decode.scala 817:24]
-  wire [6:0] _T_5 = onehot_decode + _GEN_33; // @[Decode.scala 817:24]
-  wire  _T_6 = _T_5 != 7'h1; // @[Decode.scala 817:36]
+  wire  io_undef_value_6_0 = io_undef_value_5_0 | io_undef_value_3_4; // @[Library.scala 194:39]
+  reg  onehot_failed; // @[Decode.scala 651:30]
+  wire  _T_2 = ~reset; // @[Decode.scala 652:9]
+  wire [1:0] _onehot_decode_T_77 = decoded[0] + decoded[1]; // @[Bitwise.scala 48:55]
+  wire [1:0] _onehot_decode_T_79 = decoded[2] + decoded[3]; // @[Bitwise.scala 48:55]
+  wire [2:0] _onehot_decode_T_81 = _onehot_decode_T_77 + _onehot_decode_T_79; // @[Bitwise.scala 48:55]
+  wire [1:0] _onehot_decode_T_83 = decoded[4] + decoded[5]; // @[Bitwise.scala 48:55]
+  wire [1:0] _onehot_decode_T_85 = decoded[7] + decoded[8]; // @[Bitwise.scala 48:55]
+  wire [1:0] _GEN_1 = {{1'd0}, decoded[6]}; // @[Bitwise.scala 48:55]
+  wire [2:0] _onehot_decode_T_87 = _GEN_1 + _onehot_decode_T_85; // @[Bitwise.scala 48:55]
+  wire [2:0] _onehot_decode_T_89 = _onehot_decode_T_83 + _onehot_decode_T_87[1:0]; // @[Bitwise.scala 48:55]
+  wire [3:0] _onehot_decode_T_91 = _onehot_decode_T_81 + _onehot_decode_T_89; // @[Bitwise.scala 48:55]
+  wire [1:0] _onehot_decode_T_93 = decoded[9] + decoded[10]; // @[Bitwise.scala 48:55]
+  wire [1:0] _onehot_decode_T_95 = decoded[12] + decoded[13]; // @[Bitwise.scala 48:55]
+  wire [1:0] _GEN_2 = {{1'd0}, decoded[11]}; // @[Bitwise.scala 48:55]
+  wire [2:0] _onehot_decode_T_97 = _GEN_2 + _onehot_decode_T_95; // @[Bitwise.scala 48:55]
+  wire [2:0] _onehot_decode_T_99 = _onehot_decode_T_93 + _onehot_decode_T_97[1:0]; // @[Bitwise.scala 48:55]
+  wire [1:0] _onehot_decode_T_101 = decoded[14] + decoded[15]; // @[Bitwise.scala 48:55]
+  wire [1:0] _onehot_decode_T_103 = decoded[17] + decoded[18]; // @[Bitwise.scala 48:55]
+  wire [1:0] _GEN_3 = {{1'd0}, decoded[16]}; // @[Bitwise.scala 48:55]
+  wire [2:0] _onehot_decode_T_105 = _GEN_3 + _onehot_decode_T_103; // @[Bitwise.scala 48:55]
+  wire [2:0] _onehot_decode_T_107 = _onehot_decode_T_101 + _onehot_decode_T_105[1:0]; // @[Bitwise.scala 48:55]
+  wire [3:0] _onehot_decode_T_109 = _onehot_decode_T_99 + _onehot_decode_T_107; // @[Bitwise.scala 48:55]
+  wire [4:0] _onehot_decode_T_111 = _onehot_decode_T_91 + _onehot_decode_T_109; // @[Bitwise.scala 48:55]
+  wire [1:0] _onehot_decode_T_113 = decoded[19] + decoded[20]; // @[Bitwise.scala 48:55]
+  wire [1:0] _onehot_decode_T_115 = decoded[21] + decoded[22]; // @[Bitwise.scala 48:55]
+  wire [2:0] _onehot_decode_T_117 = _onehot_decode_T_113 + _onehot_decode_T_115; // @[Bitwise.scala 48:55]
+  wire [1:0] _onehot_decode_T_119 = decoded[23] + decoded[24]; // @[Bitwise.scala 48:55]
+  wire [1:0] _onehot_decode_T_121 = decoded[26] + decoded[27]; // @[Bitwise.scala 48:55]
+  wire [1:0] _GEN_4 = {{1'd0}, decoded[25]}; // @[Bitwise.scala 48:55]
+  wire [2:0] _onehot_decode_T_123 = _GEN_4 + _onehot_decode_T_121; // @[Bitwise.scala 48:55]
+  wire [2:0] _onehot_decode_T_125 = _onehot_decode_T_119 + _onehot_decode_T_123[1:0]; // @[Bitwise.scala 48:55]
+  wire [3:0] _onehot_decode_T_127 = _onehot_decode_T_117 + _onehot_decode_T_125; // @[Bitwise.scala 48:55]
+  wire [1:0] _onehot_decode_T_129 = decoded[28] + decoded[29]; // @[Bitwise.scala 48:55]
+  wire [1:0] _onehot_decode_T_131 = decoded[31] + decoded[32]; // @[Bitwise.scala 48:55]
+  wire [1:0] _GEN_5 = {{1'd0}, decoded[30]}; // @[Bitwise.scala 48:55]
+  wire [2:0] _onehot_decode_T_133 = _GEN_5 + _onehot_decode_T_131; // @[Bitwise.scala 48:55]
+  wire [2:0] _onehot_decode_T_135 = _onehot_decode_T_129 + _onehot_decode_T_133[1:0]; // @[Bitwise.scala 48:55]
+  wire [1:0] _onehot_decode_T_137 = decoded[33] + decoded[34]; // @[Bitwise.scala 48:55]
+  wire [1:0] _onehot_decode_T_139 = decoded[36] + decoded[37]; // @[Bitwise.scala 48:55]
+  wire [1:0] _GEN_6 = {{1'd0}, decoded[35]}; // @[Bitwise.scala 48:55]
+  wire [2:0] _onehot_decode_T_141 = _GEN_6 + _onehot_decode_T_139; // @[Bitwise.scala 48:55]
+  wire [2:0] _onehot_decode_T_143 = _onehot_decode_T_137 + _onehot_decode_T_141[1:0]; // @[Bitwise.scala 48:55]
+  wire [3:0] _onehot_decode_T_145 = _onehot_decode_T_135 + _onehot_decode_T_143; // @[Bitwise.scala 48:55]
+  wire [4:0] _onehot_decode_T_147 = _onehot_decode_T_127 + _onehot_decode_T_145; // @[Bitwise.scala 48:55]
+  wire [5:0] _onehot_decode_T_149 = _onehot_decode_T_111 + _onehot_decode_T_147; // @[Bitwise.scala 48:55]
+  wire [1:0] _onehot_decode_T_151 = decoded[38] + decoded[39]; // @[Bitwise.scala 48:55]
+  wire [1:0] _onehot_decode_T_153 = decoded[40] + decoded[41]; // @[Bitwise.scala 48:55]
+  wire [2:0] _onehot_decode_T_155 = _onehot_decode_T_151 + _onehot_decode_T_153; // @[Bitwise.scala 48:55]
+  wire [1:0] _onehot_decode_T_157 = decoded[42] + decoded[43]; // @[Bitwise.scala 48:55]
+  wire [1:0] _onehot_decode_T_159 = decoded[45] + decoded[46]; // @[Bitwise.scala 48:55]
+  wire [1:0] _GEN_7 = {{1'd0}, decoded[44]}; // @[Bitwise.scala 48:55]
+  wire [2:0] _onehot_decode_T_161 = _GEN_7 + _onehot_decode_T_159; // @[Bitwise.scala 48:55]
+  wire [2:0] _onehot_decode_T_163 = _onehot_decode_T_157 + _onehot_decode_T_161[1:0]; // @[Bitwise.scala 48:55]
+  wire [3:0] _onehot_decode_T_165 = _onehot_decode_T_155 + _onehot_decode_T_163; // @[Bitwise.scala 48:55]
+  wire [1:0] _onehot_decode_T_167 = decoded[47] + decoded[48]; // @[Bitwise.scala 48:55]
+  wire [1:0] _onehot_decode_T_169 = decoded[50] + decoded[51]; // @[Bitwise.scala 48:55]
+  wire [1:0] _GEN_8 = {{1'd0}, decoded[49]}; // @[Bitwise.scala 48:55]
+  wire [2:0] _onehot_decode_T_171 = _GEN_8 + _onehot_decode_T_169; // @[Bitwise.scala 48:55]
+  wire [2:0] _onehot_decode_T_173 = _onehot_decode_T_167 + _onehot_decode_T_171[1:0]; // @[Bitwise.scala 48:55]
+  wire [1:0] _onehot_decode_T_175 = decoded[52] + decoded[53]; // @[Bitwise.scala 48:55]
+  wire [1:0] _onehot_decode_T_177 = decoded[55] + decoded[56]; // @[Bitwise.scala 48:55]
+  wire [1:0] _GEN_9 = {{1'd0}, decoded[54]}; // @[Bitwise.scala 48:55]
+  wire [2:0] _onehot_decode_T_179 = _GEN_9 + _onehot_decode_T_177; // @[Bitwise.scala 48:55]
+  wire [2:0] _onehot_decode_T_181 = _onehot_decode_T_175 + _onehot_decode_T_179[1:0]; // @[Bitwise.scala 48:55]
+  wire [3:0] _onehot_decode_T_183 = _onehot_decode_T_173 + _onehot_decode_T_181; // @[Bitwise.scala 48:55]
+  wire [4:0] _onehot_decode_T_185 = _onehot_decode_T_165 + _onehot_decode_T_183; // @[Bitwise.scala 48:55]
+  wire [1:0] _onehot_decode_T_187 = decoded[57] + decoded[58]; // @[Bitwise.scala 48:55]
+  wire [1:0] _onehot_decode_T_189 = decoded[60] + decoded[61]; // @[Bitwise.scala 48:55]
+  wire [1:0] _GEN_10 = {{1'd0}, decoded[59]}; // @[Bitwise.scala 48:55]
+  wire [2:0] _onehot_decode_T_191 = _GEN_10 + _onehot_decode_T_189; // @[Bitwise.scala 48:55]
+  wire [2:0] _onehot_decode_T_193 = _onehot_decode_T_187 + _onehot_decode_T_191[1:0]; // @[Bitwise.scala 48:55]
+  wire [1:0] _onehot_decode_T_195 = decoded[62] + decoded[63]; // @[Bitwise.scala 48:55]
+  wire [1:0] _onehot_decode_T_197 = decoded[65] + decoded[66]; // @[Bitwise.scala 48:55]
+  wire [1:0] _GEN_11 = {{1'd0}, decoded[64]}; // @[Bitwise.scala 48:55]
+  wire [2:0] _onehot_decode_T_199 = _GEN_11 + _onehot_decode_T_197; // @[Bitwise.scala 48:55]
+  wire [2:0] _onehot_decode_T_201 = _onehot_decode_T_195 + _onehot_decode_T_199[1:0]; // @[Bitwise.scala 48:55]
+  wire [3:0] _onehot_decode_T_203 = _onehot_decode_T_193 + _onehot_decode_T_201; // @[Bitwise.scala 48:55]
+  wire [1:0] _onehot_decode_T_205 = decoded[67] + decoded[68]; // @[Bitwise.scala 48:55]
+  wire [1:0] _onehot_decode_T_207 = decoded[70] + decoded[71]; // @[Bitwise.scala 48:55]
+  wire [1:0] _GEN_12 = {{1'd0}, decoded[69]}; // @[Bitwise.scala 48:55]
+  wire [2:0] _onehot_decode_T_209 = _GEN_12 + _onehot_decode_T_207; // @[Bitwise.scala 48:55]
+  wire [2:0] _onehot_decode_T_211 = _onehot_decode_T_205 + _onehot_decode_T_209[1:0]; // @[Bitwise.scala 48:55]
+  wire [1:0] _onehot_decode_T_213 = decoded[72] + decoded[73]; // @[Bitwise.scala 48:55]
+  wire [1:0] _onehot_decode_T_215 = decoded[75] + io_undef_value__38; // @[Bitwise.scala 48:55]
+  wire [1:0] _GEN_13 = {{1'd0}, decoded[74]}; // @[Bitwise.scala 48:55]
+  wire [2:0] _onehot_decode_T_217 = _GEN_13 + _onehot_decode_T_215; // @[Bitwise.scala 48:55]
+  wire [2:0] _onehot_decode_T_219 = _onehot_decode_T_213 + _onehot_decode_T_217[1:0]; // @[Bitwise.scala 48:55]
+  wire [3:0] _onehot_decode_T_221 = _onehot_decode_T_211 + _onehot_decode_T_219; // @[Bitwise.scala 48:55]
+  wire [4:0] _onehot_decode_T_223 = _onehot_decode_T_203 + _onehot_decode_T_221; // @[Bitwise.scala 48:55]
+  wire [5:0] _onehot_decode_T_225 = _onehot_decode_T_185 + _onehot_decode_T_223; // @[Bitwise.scala 48:55]
+  wire [6:0] onehot_decode = _onehot_decode_T_149 + _onehot_decode_T_225; // @[Bitwise.scala 48:55]
+  wire [6:0] _GEN_14 = {{6'd0}, io_undef}; // @[Decode.scala 655:24]
+  wire [6:0] _T_5 = onehot_decode + _GEN_14; // @[Decode.scala 655:24]
+  wire  _T_6 = _T_5 != 7'h1; // @[Decode.scala 655:36]
   assign io_imm12 = {_io_imm12_T_2,io_inst[31:20]}; // @[Cat.scala 31:58]
   assign io_imm20 = {io_inst[31:12],12'h0}; // @[Cat.scala 31:58]
   assign io_immjal = {io_immjal_hi,io_immjal_lo}; // @[Cat.scala 31:58]
   assign io_immbr = {io_immbr_hi,io_immbr_lo}; // @[Cat.scala 31:58]
   assign io_immst = {io_immst_hi,io_inst[11:7]}; // @[Cat.scala 31:58]
-  assign io_lui = _io_lui_T_3 & io_lui_bit_29 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 314:48]
-  assign io_auipc = _io_auipc_T_3 & io_lui_bit_29 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 314:48]
-  assign io_jal = _io_jal_T_2 & io_inst[3] & io_lui_bit_29 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 314:48]
-  assign io_jalr = _io_jalr_T_6 & io_lui_bit_29 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 314:48]
-  assign io_beq = _io_beq_T_7 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 314:48]
-  assign io_bne = _io_bne_T_7 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 314:48]
-  assign io_blt = _io_blt_T_7 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 314:48]
-  assign io_bge = _io_bge_T_7 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 314:48]
-  assign io_bltu = _io_bltu_T_7 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 314:48]
-  assign io_bgeu = _io_bgeu_T_7 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 314:48]
-  assign io_csrrw = 1'h0; // @[Decode.scala 734:14]
-  assign io_csrrs = 1'h0; // @[Decode.scala 735:14]
-  assign io_csrrc = 1'h0; // @[Decode.scala 736:14]
-  assign io_lb = _io_lb_T_7 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 314:48]
-  assign io_lh = _io_lh_T_7 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 314:48]
-  assign io_lw = _io_lw_T_7 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 314:48]
-  assign io_lbu = _io_lbu_T_7 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 314:48]
-  assign io_lhu = _io_lhu_T_7 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 314:48]
-  assign io_sb = _io_sb_T_7 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 314:48]
-  assign io_sh = _io_sh_T_7 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 314:48]
-  assign io_sw = _io_sw_T_7 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 314:48]
-  assign io_fence = 1'h0; // @[Decode.scala 778:17]
-  assign io_addi = _io_addi_T_7 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 314:48]
-  assign io_slti = _io_slti_T_7 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 314:48]
-  assign io_sltiu = _io_sltiu_T_7 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 314:48]
-  assign io_xori = _io_xori_T_7 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 314:48]
-  assign io_ori = _io_ori_T_7 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 314:48]
-  assign io_andi = _io_andi_T_7 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 314:48]
-  assign io_slli = _io_slli_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 314:48]
-  assign io_srli = _io_srli_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 314:48]
-  assign io_srai = _io_srai_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 314:48]
-  assign io_add = _io_add_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 314:48]
-  assign io_sub = _io_sub_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 314:48]
-  assign io_slt = _io_slt_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 314:48]
-  assign io_sltu = _io_sltu_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 314:48]
-  assign io_xor = _io_xor_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 314:48]
-  assign io_or = _io_or_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 314:48]
-  assign io_and = _io_and_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 314:48]
-  assign io_sll = _io_sll_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 314:48]
-  assign io_srl = _io_srl_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 314:48]
-  assign io_sra = _io_sra_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 314:48]
-  assign io_mul = _io_mul_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 314:48]
-  assign io_mulh = _io_mulh_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 314:48]
-  assign io_mulhsu = _io_mulhsu_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 314:48]
-  assign io_mulhu = _io_mulhu_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 314:48]
-  assign io_mulhr = _io_mulhr_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 314:48]
-  assign io_mulhsur = _io_mulhsur_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 314:48]
-  assign io_mulhur = _io_mulhur_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 314:48]
-  assign io_dmulh = _io_dmulh_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 314:48]
-  assign io_dmulhr = _io_dmulhr_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 314:48]
-  assign io_div = 1'h0; // @[Decode.scala 738:12]
-  assign io_divu = 1'h0; // @[Decode.scala 739:13]
-  assign io_rem = 1'h0; // @[Decode.scala 740:12]
-  assign io_remu = 1'h0; // @[Decode.scala 741:13]
-  assign io_flw = 1'h0; // @[Decode.scala 743:12]
-  assign io_fsw = 1'h0; // @[Decode.scala 744:12]
-  assign io_fmadd = 1'h0; // @[Decode.scala 745:14]
-  assign io_fmsub = 1'h0; // @[Decode.scala 746:14]
-  assign io_fnmsub = 1'h0; // @[Decode.scala 747:15]
-  assign io_fnmadd = 1'h0; // @[Decode.scala 748:15]
-  assign io_fadd = 1'h0; // @[Decode.scala 749:13]
-  assign io_fsub = 1'h0; // @[Decode.scala 750:13]
-  assign io_fmul = 1'h0; // @[Decode.scala 751:13]
-  assign io_fdiv = 1'h0; // @[Decode.scala 752:13]
-  assign io_fsqrt = 1'h0; // @[Decode.scala 753:14]
-  assign io_fsgnj = 1'h0; // @[Decode.scala 754:14]
-  assign io_fsgnjn = 1'h0; // @[Decode.scala 755:15]
-  assign io_fsgnjx = 1'h0; // @[Decode.scala 756:15]
-  assign io_fmin = 1'h0; // @[Decode.scala 757:13]
-  assign io_fmax = 1'h0; // @[Decode.scala 758:13]
-  assign io_fcvtws = 1'h0; // @[Decode.scala 759:15]
-  assign io_fcvtwus = 1'h0; // @[Decode.scala 760:16]
-  assign io_fmvxw = 1'h0; // @[Decode.scala 761:14]
-  assign io_feq = 1'h0; // @[Decode.scala 762:12]
-  assign io_flt = 1'h0; // @[Decode.scala 763:12]
-  assign io_fle = 1'h0; // @[Decode.scala 764:12]
-  assign io_fclass = 1'h0; // @[Decode.scala 765:15]
-  assign io_fcvtsw = 1'h0; // @[Decode.scala 766:15]
-  assign io_fcvtswu = 1'h0; // @[Decode.scala 767:16]
-  assign io_fmvwx = 1'h0; // @[Decode.scala 768:14]
-  assign io_clb = _io_clb_T_19 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 314:48]
-  assign io_clz = _io_clz_T_19 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 314:48]
-  assign io_ctz = _io_ctz_T_19 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 314:48]
-  assign io_pcnt = _io_pcnt_T_19 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 314:48]
-  assign io_min = _io_min_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 314:48]
-  assign io_minu = _io_minu_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 314:48]
-  assign io_max = _io_max_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 314:48]
-  assign io_maxu = _io_maxu_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 314:48]
-  assign io_getvl = _io_getvl_T_13 & io_inst[26:25] != 2'h3 & (io_inst[24:20] != 5'h0 | io_inst[19:15] != 5'h0); // @[Decode.scala 688:97]
-  assign io_getmaxvl = _io_getmaxvl_T_23 & _io_getvl_T_15; // @[Decode.scala 689:76]
-  assign io_vld = _io_vld_T_4 & io_lui_bit_27 & io_inst[3] & io_lui_bit_29 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 314:48]
-  assign io_vst = _io_vst_T_9 | _io_vst_T_19; // @[Decode.scala 694:71]
-  assign io_viop = _io_viop_T_9 | vdupi; // @[Decode.scala 713:20]
-  assign io_vfop = vfma | vfma4 | vdupf; // @[Decode.scala 708:28]
-  assign io_ebreak = 1'h0; // @[Decode.scala 770:15]
-  assign io_ecall = 1'h0; // @[Decode.scala 771:15]
-  assign io_eexit = 1'h0; // @[Decode.scala 772:15]
-  assign io_eyield = 1'h0; // @[Decode.scala 773:15]
-  assign io_ectxsw = 1'h0; // @[Decode.scala 774:15]
-  assign io_mpause = 1'h0; // @[Decode.scala 775:15]
-  assign io_mret = 1'h0; // @[Decode.scala 776:15]
-  assign io_undef = ~io_undef_value_6_0; // @[Decode.scala 810:15]
-  assign io_fencei = 1'h0; // @[Decode.scala 779:17]
-  assign io_flushat = 1'h0; // @[Decode.scala 780:17]
-  assign io_flushall = 1'h0; // @[Decode.scala 781:17]
-  assign io_slog = 1'h0; // @[Decode.scala 783:13]
+  assign io_lui = _io_lui_T_3 & io_lui_bit_29 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 316:48]
+  assign io_auipc = _io_auipc_T_3 & io_lui_bit_29 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 316:48]
+  assign io_jal = _io_jal_T_2 & io_inst[3] & io_lui_bit_29 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 316:48]
+  assign io_jalr = _io_jalr_T_6 & io_lui_bit_29 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 316:48]
+  assign io_beq = _io_beq_T_7 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 316:48]
+  assign io_bne = _io_bne_T_7 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 316:48]
+  assign io_blt = _io_blt_T_7 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 316:48]
+  assign io_bge = _io_bge_T_7 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 316:48]
+  assign io_bltu = _io_bltu_T_7 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 316:48]
+  assign io_bgeu = _io_bgeu_T_7 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 316:48]
+  assign io_csrrw = 1'h0; // @[Decode.scala 605:14]
+  assign io_csrrs = 1'h0; // @[Decode.scala 606:14]
+  assign io_csrrc = 1'h0; // @[Decode.scala 607:14]
+  assign io_lb = _io_lb_T_7 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 316:48]
+  assign io_lh = _io_lh_T_7 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 316:48]
+  assign io_lw = _io_lw_T_7 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 316:48]
+  assign io_lbu = _io_lbu_T_7 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 316:48]
+  assign io_lhu = _io_lhu_T_7 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 316:48]
+  assign io_sb = _io_sb_T_7 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 316:48]
+  assign io_sh = _io_sh_T_7 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 316:48]
+  assign io_sw = _io_sw_T_7 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 316:48]
+  assign io_fence = 1'h0; // @[Decode.scala 622:17]
+  assign io_addi = _io_addi_T_7 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 316:48]
+  assign io_slti = _io_slti_T_7 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 316:48]
+  assign io_sltiu = _io_sltiu_T_7 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 316:48]
+  assign io_xori = _io_xori_T_7 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 316:48]
+  assign io_ori = _io_ori_T_7 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 316:48]
+  assign io_andi = _io_andi_T_7 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 316:48]
+  assign io_slli = _io_slli_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 316:48]
+  assign io_srli = _io_srli_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 316:48]
+  assign io_srai = _io_srai_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 316:48]
+  assign io_add = _io_add_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 316:48]
+  assign io_sub = _io_sub_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 316:48]
+  assign io_slt = _io_slt_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 316:48]
+  assign io_sltu = _io_sltu_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 316:48]
+  assign io_xor = _io_xor_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 316:48]
+  assign io_or = _io_or_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 316:48]
+  assign io_and = _io_and_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 316:48]
+  assign io_sll = _io_sll_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 316:48]
+  assign io_srl = _io_srl_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 316:48]
+  assign io_sra = _io_sra_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 316:48]
+  assign io_mul = _io_mul_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 316:48]
+  assign io_mulh = _io_mulh_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 316:48]
+  assign io_mulhsu = _io_mulhsu_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 316:48]
+  assign io_mulhu = _io_mulhu_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 316:48]
+  assign io_mulhr = _io_mulhr_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 316:48]
+  assign io_mulhsur = _io_mulhsur_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 316:48]
+  assign io_mulhur = _io_mulhur_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 316:48]
+  assign io_dmulh = _io_dmulh_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 316:48]
+  assign io_dmulhr = _io_dmulhr_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 316:48]
+  assign io_div = 1'h0; // @[Decode.scala 609:12]
+  assign io_divu = 1'h0; // @[Decode.scala 610:13]
+  assign io_rem = 1'h0; // @[Decode.scala 611:12]
+  assign io_remu = 1'h0; // @[Decode.scala 612:13]
+  assign io_clz = _io_clz_T_19 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 316:48]
+  assign io_ctz = _io_ctz_T_19 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 316:48]
+  assign io_pcnt = _io_pcnt_T_19 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 316:48]
+  assign io_min = _io_min_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 316:48]
+  assign io_minu = _io_minu_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 316:48]
+  assign io_max = _io_max_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 316:48]
+  assign io_maxu = _io_maxu_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 316:48]
+  assign io_getvl = _io_getvl_T_13 & io_inst[26:25] != 2'h3 & (io_inst[24:20] != 5'h0 | io_inst[19:15] != 5'h0); // @[Decode.scala 565:97]
+  assign io_getmaxvl = _io_getmaxvl_T_23 & _io_getvl_T_15; // @[Decode.scala 566:76]
+  assign io_vld = _io_vld_T_4 & io_lui_bit_27 & io_inst[3] & io_lui_bit_29 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 316:48]
+  assign io_vst = _io_vst_T_9 | _io_vst_T_19; // @[Decode.scala 571:71]
+  assign io_viop = _io_viop_T_5 | vdupi; // @[Decode.scala 584:20]
+  assign io_ebreak = 1'h0; // @[Decode.scala 614:15]
+  assign io_ecall = 1'h0; // @[Decode.scala 615:15]
+  assign io_eexit = 1'h0; // @[Decode.scala 616:15]
+  assign io_eyield = 1'h0; // @[Decode.scala 617:15]
+  assign io_ectxsw = 1'h0; // @[Decode.scala 618:15]
+  assign io_mpause = 1'h0; // @[Decode.scala 619:15]
+  assign io_mret = 1'h0; // @[Decode.scala 620:15]
+  assign io_undef = ~io_undef_value_6_0; // @[Decode.scala 648:15]
+  assign io_fencei = 1'h0; // @[Decode.scala 623:17]
+  assign io_flushat = 1'h0; // @[Decode.scala 624:17]
+  assign io_flushall = 1'h0; // @[Decode.scala 625:17]
+  assign io_slog = 1'h0; // @[Decode.scala 627:13]
   always @(posedge clock) begin
     `ifndef SYNTHESIS
     `ifdef STOP_COND
       if (`STOP_COND) begin
     `endif
         if (~reset & ~(~onehot_failed)) begin
-          $fatal; // @[Decode.scala 814:9]
+          $fatal; // @[Decode.scala 652:9]
         end
     `ifdef STOP_COND
       end
@@ -13101,7 +12022,7 @@
       if (`PRINTF_COND) begin
     `endif
         if (~reset & ~(~onehot_failed)) begin
-          $fwrite(32'h80000002,"Assertion failed\n    at Decode.scala:814 assert(!onehot_failed)\n"); // @[Decode.scala 814:9]
+          $fwrite(32'h80000002,"Assertion failed\n    at Decode.scala:652 assert(!onehot_failed)\n"); // @[Decode.scala 652:9]
         end
     `ifdef PRINTF_COND
       end
@@ -13113,7 +12034,7 @@
     `endif
         if (_T_6 & _T_2) begin
           $fwrite(32'h80000002,"[FAIL] decode  inst=%x  addr=%x  decoded=0b%b  pipeline=%d\n",io_inst,io_addr,decoded,2'h3
-            ); // @[Decode.scala 819:11]
+            ); // @[Decode.scala 657:11]
         end
     `ifdef PRINTF_COND
       end
@@ -13121,10 +12042,10 @@
     `endif // SYNTHESIS
   end
   always @(posedge clock or posedge reset) begin
-    if (reset) begin // @[Decode.scala 817:45]
-      onehot_failed <= 1'h0; // @[Decode.scala 818:19]
+    if (reset) begin // @[Decode.scala 655:45]
+      onehot_failed <= 1'h0; // @[Decode.scala 656:19]
     end else begin
-      onehot_failed <= _T_5 != 7'h1 | onehot_failed; // @[Decode.scala 813:30]
+      onehot_failed <= _T_5 != 7'h1 | onehot_failed; // @[Decode.scala 651:30]
     end
   end
 // Register and memory initialization
@@ -13187,7 +12108,6 @@
   input         io_inst_brchFwd,
   input  [31:0] io_scoreboard_regd,
   input  [31:0] io_scoreboard_comb,
-  input  [31:0] io_fscoreboard,
   output        io_rs1Read_valid,
   output [4:0]  io_rs1Read_addr,
   output        io_rs1Set_valid,
@@ -13202,7 +12122,7 @@
   output [31:0] io_busRead_immed,
   output        io_alu_valid,
   output [4:0]  io_alu_addr,
-  output [18:0] io_alu_op,
+  output [17:0] io_alu_op,
   output        io_bru_valid,
   output        io_bru_fwd,
   output [16:0] io_bru_op,
@@ -13213,190 +12133,152 @@
   output        io_lsu_valid,
   input         io_lsu_ready,
   output [4:0]  io_lsu_addr,
-  output [13:0] io_lsu_op,
+  output [11:0] io_lsu_op,
   output        io_mlu_valid,
   output [4:0]  io_mlu_addr,
   output [8:0]  io_mlu_op,
   output [3:0]  io_dvu_op,
-  output [4:0]  io_fpu_raddr_1,
-  output [26:0] io_fpu_op,
   output        io_vinst_valid,
   input         io_vinst_ready,
   output [4:0]  io_vinst_addr,
   output [31:0] io_vinst_inst,
-  output [5:0]  io_vinst_op,
+  output [4:0]  io_vinst_op,
   input         io_branchTaken,
   input         io_interlock,
   input         io_serializeIn_mul,
   input         io_serializeIn_jump,
   input         io_serializeIn_brcond
 );
-  wire  d_clock; // @[Decode.scala 91:17]
-  wire  d_reset; // @[Decode.scala 91:17]
-  wire [31:0] d_io_addr; // @[Decode.scala 91:17]
-  wire [31:0] d_io_inst; // @[Decode.scala 91:17]
-  wire [31:0] d_io_imm12; // @[Decode.scala 91:17]
-  wire [31:0] d_io_imm20; // @[Decode.scala 91:17]
-  wire [31:0] d_io_immjal; // @[Decode.scala 91:17]
-  wire [31:0] d_io_immbr; // @[Decode.scala 91:17]
-  wire [31:0] d_io_immst; // @[Decode.scala 91:17]
-  wire  d_io_lui; // @[Decode.scala 91:17]
-  wire  d_io_auipc; // @[Decode.scala 91:17]
-  wire  d_io_jal; // @[Decode.scala 91:17]
-  wire  d_io_jalr; // @[Decode.scala 91:17]
-  wire  d_io_beq; // @[Decode.scala 91:17]
-  wire  d_io_bne; // @[Decode.scala 91:17]
-  wire  d_io_blt; // @[Decode.scala 91:17]
-  wire  d_io_bge; // @[Decode.scala 91:17]
-  wire  d_io_bltu; // @[Decode.scala 91:17]
-  wire  d_io_bgeu; // @[Decode.scala 91:17]
-  wire  d_io_csrrw; // @[Decode.scala 91:17]
-  wire  d_io_csrrs; // @[Decode.scala 91:17]
-  wire  d_io_csrrc; // @[Decode.scala 91:17]
-  wire  d_io_lb; // @[Decode.scala 91:17]
-  wire  d_io_lh; // @[Decode.scala 91:17]
-  wire  d_io_lw; // @[Decode.scala 91:17]
-  wire  d_io_lbu; // @[Decode.scala 91:17]
-  wire  d_io_lhu; // @[Decode.scala 91:17]
-  wire  d_io_sb; // @[Decode.scala 91:17]
-  wire  d_io_sh; // @[Decode.scala 91:17]
-  wire  d_io_sw; // @[Decode.scala 91:17]
-  wire  d_io_fence; // @[Decode.scala 91:17]
-  wire  d_io_addi; // @[Decode.scala 91:17]
-  wire  d_io_slti; // @[Decode.scala 91:17]
-  wire  d_io_sltiu; // @[Decode.scala 91:17]
-  wire  d_io_xori; // @[Decode.scala 91:17]
-  wire  d_io_ori; // @[Decode.scala 91:17]
-  wire  d_io_andi; // @[Decode.scala 91:17]
-  wire  d_io_slli; // @[Decode.scala 91:17]
-  wire  d_io_srli; // @[Decode.scala 91:17]
-  wire  d_io_srai; // @[Decode.scala 91:17]
-  wire  d_io_add; // @[Decode.scala 91:17]
-  wire  d_io_sub; // @[Decode.scala 91:17]
-  wire  d_io_slt; // @[Decode.scala 91:17]
-  wire  d_io_sltu; // @[Decode.scala 91:17]
-  wire  d_io_xor; // @[Decode.scala 91:17]
-  wire  d_io_or; // @[Decode.scala 91:17]
-  wire  d_io_and; // @[Decode.scala 91:17]
-  wire  d_io_sll; // @[Decode.scala 91:17]
-  wire  d_io_srl; // @[Decode.scala 91:17]
-  wire  d_io_sra; // @[Decode.scala 91:17]
-  wire  d_io_mul; // @[Decode.scala 91:17]
-  wire  d_io_mulh; // @[Decode.scala 91:17]
-  wire  d_io_mulhsu; // @[Decode.scala 91:17]
-  wire  d_io_mulhu; // @[Decode.scala 91:17]
-  wire  d_io_mulhr; // @[Decode.scala 91:17]
-  wire  d_io_mulhsur; // @[Decode.scala 91:17]
-  wire  d_io_mulhur; // @[Decode.scala 91:17]
-  wire  d_io_dmulh; // @[Decode.scala 91:17]
-  wire  d_io_dmulhr; // @[Decode.scala 91:17]
-  wire  d_io_div; // @[Decode.scala 91:17]
-  wire  d_io_divu; // @[Decode.scala 91:17]
-  wire  d_io_rem; // @[Decode.scala 91:17]
-  wire  d_io_remu; // @[Decode.scala 91:17]
-  wire  d_io_flw; // @[Decode.scala 91:17]
-  wire  d_io_fsw; // @[Decode.scala 91:17]
-  wire  d_io_fmadd; // @[Decode.scala 91:17]
-  wire  d_io_fmsub; // @[Decode.scala 91:17]
-  wire  d_io_fnmsub; // @[Decode.scala 91:17]
-  wire  d_io_fnmadd; // @[Decode.scala 91:17]
-  wire  d_io_fadd; // @[Decode.scala 91:17]
-  wire  d_io_fsub; // @[Decode.scala 91:17]
-  wire  d_io_fmul; // @[Decode.scala 91:17]
-  wire  d_io_fdiv; // @[Decode.scala 91:17]
-  wire  d_io_fsqrt; // @[Decode.scala 91:17]
-  wire  d_io_fsgnj; // @[Decode.scala 91:17]
-  wire  d_io_fsgnjn; // @[Decode.scala 91:17]
-  wire  d_io_fsgnjx; // @[Decode.scala 91:17]
-  wire  d_io_fmin; // @[Decode.scala 91:17]
-  wire  d_io_fmax; // @[Decode.scala 91:17]
-  wire  d_io_fcvtws; // @[Decode.scala 91:17]
-  wire  d_io_fcvtwus; // @[Decode.scala 91:17]
-  wire  d_io_fmvxw; // @[Decode.scala 91:17]
-  wire  d_io_feq; // @[Decode.scala 91:17]
-  wire  d_io_flt; // @[Decode.scala 91:17]
-  wire  d_io_fle; // @[Decode.scala 91:17]
-  wire  d_io_fclass; // @[Decode.scala 91:17]
-  wire  d_io_fcvtsw; // @[Decode.scala 91:17]
-  wire  d_io_fcvtswu; // @[Decode.scala 91:17]
-  wire  d_io_fmvwx; // @[Decode.scala 91:17]
-  wire  d_io_clb; // @[Decode.scala 91:17]
-  wire  d_io_clz; // @[Decode.scala 91:17]
-  wire  d_io_ctz; // @[Decode.scala 91:17]
-  wire  d_io_pcnt; // @[Decode.scala 91:17]
-  wire  d_io_min; // @[Decode.scala 91:17]
-  wire  d_io_minu; // @[Decode.scala 91:17]
-  wire  d_io_max; // @[Decode.scala 91:17]
-  wire  d_io_maxu; // @[Decode.scala 91:17]
-  wire  d_io_getvl; // @[Decode.scala 91:17]
-  wire  d_io_getmaxvl; // @[Decode.scala 91:17]
-  wire  d_io_vld; // @[Decode.scala 91:17]
-  wire  d_io_vst; // @[Decode.scala 91:17]
-  wire  d_io_viop; // @[Decode.scala 91:17]
-  wire  d_io_vfop; // @[Decode.scala 91:17]
-  wire  d_io_ebreak; // @[Decode.scala 91:17]
-  wire  d_io_ecall; // @[Decode.scala 91:17]
-  wire  d_io_eexit; // @[Decode.scala 91:17]
-  wire  d_io_eyield; // @[Decode.scala 91:17]
-  wire  d_io_ectxsw; // @[Decode.scala 91:17]
-  wire  d_io_mpause; // @[Decode.scala 91:17]
-  wire  d_io_mret; // @[Decode.scala 91:17]
-  wire  d_io_undef; // @[Decode.scala 91:17]
-  wire  d_io_fencei; // @[Decode.scala 91:17]
-  wire  d_io_flushat; // @[Decode.scala 91:17]
-  wire  d_io_flushall; // @[Decode.scala 91:17]
-  wire  d_io_slog; // @[Decode.scala 91:17]
-  wire  decodeEn = io_inst_valid & io_inst_ready & ~io_branchTaken; // @[Decode.scala 88:49]
-  wire  vldst = d_io_vld | d_io_vst; // @[Decode.scala 95:24]
-  wire  vldst_wb = vldst & io_inst_inst[28]; // @[Decode.scala 96:24]
-  wire [4:0] rdAddr = vldst ? io_inst_inst[19:15] : io_inst_inst[11:7]; // @[Decode.scala 98:20]
-  wire [4:0] rs2Addr = io_inst_inst[24:20]; // @[Decode.scala 100:29]
-  wire [4:0] rs3Addr = io_inst_inst[31:27]; // @[Decode.scala 101:29]
-  wire  _isAluImm_T_3 = d_io_addi | d_io_slti | d_io_sltiu | d_io_xori | d_io_ori; // @[Decode.scala 103:68]
-  wire  isAluImm = _isAluImm_T_3 | d_io_andi | d_io_slli | d_io_srli | d_io_srai; // @[Decode.scala 104:66]
-  wire  _isAluReg_T_4 = d_io_add | d_io_sub | d_io_slt | d_io_sltu | d_io_xor | d_io_or; // @[Decode.scala 106:76]
-  wire  isAluReg = _isAluReg_T_4 | d_io_and | d_io_sll | d_io_srl | d_io_sra; // @[Decode.scala 107:62]
-  wire  isAlu1Bit = d_io_clb | d_io_clz | d_io_ctz | d_io_pcnt; // @[Decode.scala 109:52]
-  wire  isAlu2Bit = d_io_min | d_io_minu | d_io_max | d_io_maxu; // @[Decode.scala 110:53]
-  wire  _isCondBr_T_3 = d_io_beq | d_io_bne | d_io_blt | d_io_bge | d_io_bltu; // @[Decode.scala 112:63]
-  wire  isCondBr = _isCondBr_T_3 | d_io_bgeu; // @[Decode.scala 113:28]
-  wire  isLoad = d_io_lb | d_io_lh | d_io_lw | d_io_lbu | d_io_lhu; // @[Decode.scala 119:58]
-  wire  isStore = d_io_sb | d_io_sh | d_io_sw; // @[Decode.scala 120:36]
-  wire  isLsu = isLoad | isStore | d_io_vld | d_io_vst; // @[Decode.scala 121:69]
+  wire  d_clock; // @[Decode.scala 87:17]
+  wire  d_reset; // @[Decode.scala 87:17]
+  wire [31:0] d_io_addr; // @[Decode.scala 87:17]
+  wire [31:0] d_io_inst; // @[Decode.scala 87:17]
+  wire [31:0] d_io_imm12; // @[Decode.scala 87:17]
+  wire [31:0] d_io_imm20; // @[Decode.scala 87:17]
+  wire [31:0] d_io_immjal; // @[Decode.scala 87:17]
+  wire [31:0] d_io_immbr; // @[Decode.scala 87:17]
+  wire [31:0] d_io_immst; // @[Decode.scala 87:17]
+  wire  d_io_lui; // @[Decode.scala 87:17]
+  wire  d_io_auipc; // @[Decode.scala 87:17]
+  wire  d_io_jal; // @[Decode.scala 87:17]
+  wire  d_io_jalr; // @[Decode.scala 87:17]
+  wire  d_io_beq; // @[Decode.scala 87:17]
+  wire  d_io_bne; // @[Decode.scala 87:17]
+  wire  d_io_blt; // @[Decode.scala 87:17]
+  wire  d_io_bge; // @[Decode.scala 87:17]
+  wire  d_io_bltu; // @[Decode.scala 87:17]
+  wire  d_io_bgeu; // @[Decode.scala 87:17]
+  wire  d_io_csrrw; // @[Decode.scala 87:17]
+  wire  d_io_csrrs; // @[Decode.scala 87:17]
+  wire  d_io_csrrc; // @[Decode.scala 87:17]
+  wire  d_io_lb; // @[Decode.scala 87:17]
+  wire  d_io_lh; // @[Decode.scala 87:17]
+  wire  d_io_lw; // @[Decode.scala 87:17]
+  wire  d_io_lbu; // @[Decode.scala 87:17]
+  wire  d_io_lhu; // @[Decode.scala 87:17]
+  wire  d_io_sb; // @[Decode.scala 87:17]
+  wire  d_io_sh; // @[Decode.scala 87:17]
+  wire  d_io_sw; // @[Decode.scala 87:17]
+  wire  d_io_fence; // @[Decode.scala 87:17]
+  wire  d_io_addi; // @[Decode.scala 87:17]
+  wire  d_io_slti; // @[Decode.scala 87:17]
+  wire  d_io_sltiu; // @[Decode.scala 87:17]
+  wire  d_io_xori; // @[Decode.scala 87:17]
+  wire  d_io_ori; // @[Decode.scala 87:17]
+  wire  d_io_andi; // @[Decode.scala 87:17]
+  wire  d_io_slli; // @[Decode.scala 87:17]
+  wire  d_io_srli; // @[Decode.scala 87:17]
+  wire  d_io_srai; // @[Decode.scala 87:17]
+  wire  d_io_add; // @[Decode.scala 87:17]
+  wire  d_io_sub; // @[Decode.scala 87:17]
+  wire  d_io_slt; // @[Decode.scala 87:17]
+  wire  d_io_sltu; // @[Decode.scala 87:17]
+  wire  d_io_xor; // @[Decode.scala 87:17]
+  wire  d_io_or; // @[Decode.scala 87:17]
+  wire  d_io_and; // @[Decode.scala 87:17]
+  wire  d_io_sll; // @[Decode.scala 87:17]
+  wire  d_io_srl; // @[Decode.scala 87:17]
+  wire  d_io_sra; // @[Decode.scala 87:17]
+  wire  d_io_mul; // @[Decode.scala 87:17]
+  wire  d_io_mulh; // @[Decode.scala 87:17]
+  wire  d_io_mulhsu; // @[Decode.scala 87:17]
+  wire  d_io_mulhu; // @[Decode.scala 87:17]
+  wire  d_io_mulhr; // @[Decode.scala 87:17]
+  wire  d_io_mulhsur; // @[Decode.scala 87:17]
+  wire  d_io_mulhur; // @[Decode.scala 87:17]
+  wire  d_io_dmulh; // @[Decode.scala 87:17]
+  wire  d_io_dmulhr; // @[Decode.scala 87:17]
+  wire  d_io_div; // @[Decode.scala 87:17]
+  wire  d_io_divu; // @[Decode.scala 87:17]
+  wire  d_io_rem; // @[Decode.scala 87:17]
+  wire  d_io_remu; // @[Decode.scala 87:17]
+  wire  d_io_clz; // @[Decode.scala 87:17]
+  wire  d_io_ctz; // @[Decode.scala 87:17]
+  wire  d_io_pcnt; // @[Decode.scala 87:17]
+  wire  d_io_min; // @[Decode.scala 87:17]
+  wire  d_io_minu; // @[Decode.scala 87:17]
+  wire  d_io_max; // @[Decode.scala 87:17]
+  wire  d_io_maxu; // @[Decode.scala 87:17]
+  wire  d_io_getvl; // @[Decode.scala 87:17]
+  wire  d_io_getmaxvl; // @[Decode.scala 87:17]
+  wire  d_io_vld; // @[Decode.scala 87:17]
+  wire  d_io_vst; // @[Decode.scala 87:17]
+  wire  d_io_viop; // @[Decode.scala 87:17]
+  wire  d_io_ebreak; // @[Decode.scala 87:17]
+  wire  d_io_ecall; // @[Decode.scala 87:17]
+  wire  d_io_eexit; // @[Decode.scala 87:17]
+  wire  d_io_eyield; // @[Decode.scala 87:17]
+  wire  d_io_ectxsw; // @[Decode.scala 87:17]
+  wire  d_io_mpause; // @[Decode.scala 87:17]
+  wire  d_io_mret; // @[Decode.scala 87:17]
+  wire  d_io_undef; // @[Decode.scala 87:17]
+  wire  d_io_fencei; // @[Decode.scala 87:17]
+  wire  d_io_flushat; // @[Decode.scala 87:17]
+  wire  d_io_flushall; // @[Decode.scala 87:17]
+  wire  d_io_slog; // @[Decode.scala 87:17]
+  wire  decodeEn = io_inst_valid & io_inst_ready & ~io_branchTaken; // @[Decode.scala 84:49]
+  wire  vldst = d_io_vld | d_io_vst; // @[Decode.scala 91:24]
+  wire  vldst_wb = vldst & io_inst_inst[28]; // @[Decode.scala 92:24]
+  wire [4:0] rdAddr = vldst ? io_inst_inst[19:15] : io_inst_inst[11:7]; // @[Decode.scala 94:20]
+  wire [4:0] rs2Addr = io_inst_inst[24:20]; // @[Decode.scala 96:29]
+  wire [4:0] rs3Addr = io_inst_inst[31:27]; // @[Decode.scala 97:29]
+  wire  _isAluImm_T_3 = d_io_addi | d_io_slti | d_io_sltiu | d_io_xori | d_io_ori; // @[Decode.scala 99:68]
+  wire  isAluImm = _isAluImm_T_3 | d_io_andi | d_io_slli | d_io_srli | d_io_srai; // @[Decode.scala 100:66]
+  wire  _isAluReg_T_4 = d_io_add | d_io_sub | d_io_slt | d_io_sltu | d_io_xor | d_io_or; // @[Decode.scala 102:76]
+  wire  isAluReg = _isAluReg_T_4 | d_io_and | d_io_sll | d_io_srl | d_io_sra; // @[Decode.scala 103:62]
+  wire  isAlu1Bit = d_io_clz | d_io_ctz | d_io_pcnt; // @[Decode.scala 105:40]
+  wire  isAlu2Bit = d_io_min | d_io_minu | d_io_max | d_io_maxu; // @[Decode.scala 106:53]
+  wire  _isCondBr_T_3 = d_io_beq | d_io_bne | d_io_blt | d_io_bge | d_io_bltu; // @[Decode.scala 108:63]
+  wire  isCondBr = _isCondBr_T_3 | d_io_bgeu; // @[Decode.scala 109:28]
+  wire  isLoad = d_io_lb | d_io_lh | d_io_lw | d_io_lbu | d_io_lhu; // @[Decode.scala 115:58]
+  wire  isStore = d_io_sb | d_io_sh | d_io_sw; // @[Decode.scala 116:36]
+  wire  isLsu = isLoad | isStore | d_io_vld | d_io_vst; // @[Decode.scala 117:45]
   wire  isMul = d_io_mul | d_io_mulh | d_io_mulhsu | d_io_mulhu | d_io_mulhr | d_io_mulhsur | d_io_mulhur | d_io_dmulh
-     | d_io_dmulhr; // @[Decode.scala 123:125]
-  wire  fpuRs2 = d_io_vfop & io_inst_inst[1]; // @[Decode.scala 129:255]
-  wire  isVFop = io_vinst_op[5]; // @[Decode.scala 133:27]
-  wire  isVIop = io_vinst_op[4]; // @[Decode.scala 134:27]
-  wire  isVIopVs2 = isVIop & io_inst_inst[1:0] == 2'h0; // @[Decode.scala 137:26]
-  wire [31:0] _aluRdEn_T = io_scoreboard_comb >> rdAddr; // @[Decode.scala 141:37]
-  wire  aluRdEn = ~_aluRdEn_T[0] | isVIop | isStore | isCondBr | fpuRs2; // @[Decode.scala 141:83]
-  wire [31:0] _aluRs1En_T = io_scoreboard_comb >> io_inst_inst[19:15]; // @[Decode.scala 142:37]
-  wire  aluRs1En = ~_aluRs1En_T[0] | isVIop | isLsu | d_io_auipc | isVFop | fpuRs2; // @[Decode.scala 142:93]
-  wire [31:0] _aluRs2En_T = io_scoreboard_comb >> rs2Addr; // @[Decode.scala 143:37]
-  wire  aluRs2En = ~_aluRs2En_T[0] | isVIopVs2 | isLsu | d_io_auipc | isVFop | isAluImm | isAlu1Bit | fpuRs2; // @[Decode.scala 143:118]
-  wire  aluEn = aluRdEn & aluRs1En & aluRs2En; // @[Decode.scala 146:35]
-  wire [31:0] _bruEn_T_1 = io_scoreboard_regd >> io_inst_inst[19:15]; // @[Decode.scala 149:48]
-  wire  _bruEn_T_6 = io_inst_inst[31:20] == 12'h0; // @[Decode.scala 150:35]
-  wire  bruEn = ~d_io_jalr | ~_bruEn_T_1[0] | _bruEn_T_6; // @[Decode.scala 149:58]
-  wire  _lsuEn_T = ~isLsu; // @[Decode.scala 153:15]
-  wire  _lsuEn_T_5 = _lsuEn_T | ~io_serializeIn_brcond; // @[Decode.scala 155:23]
-  wire  _lsuEn_T_6 = io_lsu_ready & _lsuEn_T_5; // @[Decode.scala 154:51]
-  wire  _lsuEn_T_11 = io_busRead_bypass ? _aluRs1En_T[0] : _bruEn_T_1[0]; // @[Decode.scala 156:20]
-  wire  _lsuEn_T_15 = _aluRs2En_T[0] & (isStore | vldst); // @[Decode.scala 158:49]
-  wire  _lsuEn_T_16 = _lsuEn_T_11 | _lsuEn_T_15; // @[Decode.scala 157:50]
-  wire  _lsuEn_T_17 = ~_lsuEn_T_16; // @[Decode.scala 156:15]
-  wire  _lsuEn_T_18 = _lsuEn_T_6 & _lsuEn_T_17; // @[Decode.scala 155:50]
-  wire  lsuEn = ~isLsu | _lsuEn_T_18; // @[Decode.scala 153:22]
-  wire  mulEn = ~isMul | ~io_serializeIn_mul; // @[Decode.scala 161:22]
-  wire [31:0] _fpuEn_T_8 = io_fscoreboard >> rs2Addr; // @[Decode.scala 166:53]
-  wire  _fpuEn_T_10 = fpuRs2 & _fpuEn_T_8[0]; // @[Decode.scala 166:36]
-  wire  fpuEn = ~fpuRs2 | ~_fpuEn_T_10; // @[Decode.scala 164:24]
-  wire  _vinstEn_T_5 = ~(isVFop & io_serializeIn_brcond); // @[Decode.scala 173:17]
-  wire  _vinstEn_T_6 = ~(isVIop & io_serializeIn_brcond) & _vinstEn_T_5; // @[Decode.scala 172:76]
-  wire  _vinstEn_T_10 = ~(io_vinst_op != 6'h0 & ~io_vinst_ready); // @[Decode.scala 174:17]
-  wire  vinstEn = _vinstEn_T_6 & _vinstEn_T_10; // @[Decode.scala 173:76]
-  wire  aluValid_value__9 = io_alu_op[18]; // @[Library.scala 182:26]
+     | d_io_dmulhr; // @[Decode.scala 119:125]
+  wire  isVIop = io_vinst_op[4]; // @[Decode.scala 123:27]
+  wire  isVIopVs2 = isVIop & io_inst_inst[1:0] == 2'h0; // @[Decode.scala 126:26]
+  wire [31:0] _aluRdEn_T = io_scoreboard_comb >> rdAddr; // @[Decode.scala 130:37]
+  wire  aluRdEn = ~_aluRdEn_T[0] | isVIop | isStore | isCondBr; // @[Decode.scala 130:71]
+  wire [31:0] _aluRs1En_T = io_scoreboard_comb >> io_inst_inst[19:15]; // @[Decode.scala 131:37]
+  wire  aluRs1En = ~_aluRs1En_T[0] | isVIop | isLsu | d_io_auipc; // @[Decode.scala 131:69]
+  wire [31:0] _aluRs2En_T = io_scoreboard_comb >> rs2Addr; // @[Decode.scala 132:37]
+  wire  aluRs2En = ~_aluRs2En_T[0] | isVIopVs2 | isLsu | d_io_auipc | isAluImm | isAlu1Bit; // @[Decode.scala 132:95]
+  wire  aluEn = aluRdEn & aluRs1En & aluRs2En; // @[Decode.scala 135:35]
+  wire [31:0] _bruEn_T_1 = io_scoreboard_regd >> io_inst_inst[19:15]; // @[Decode.scala 138:48]
+  wire  _bruEn_T_6 = io_inst_inst[31:20] == 12'h0; // @[Decode.scala 139:35]
+  wire  bruEn = ~d_io_jalr | ~_bruEn_T_1[0] | _bruEn_T_6; // @[Decode.scala 138:58]
+  wire  _lsuEn_T = ~isLsu; // @[Decode.scala 142:15]
+  wire  _lsuEn_T_5 = _lsuEn_T | ~io_serializeIn_brcond; // @[Decode.scala 144:23]
+  wire  _lsuEn_T_6 = io_lsu_ready & _lsuEn_T_5; // @[Decode.scala 143:51]
+  wire  _lsuEn_T_11 = io_busRead_bypass ? _aluRs1En_T[0] : _bruEn_T_1[0]; // @[Decode.scala 145:20]
+  wire  _lsuEn_T_15 = _aluRs2En_T[0] & (isStore | vldst); // @[Decode.scala 147:49]
+  wire  _lsuEn_T_16 = _lsuEn_T_11 | _lsuEn_T_15; // @[Decode.scala 146:50]
+  wire  _lsuEn_T_17 = ~_lsuEn_T_16; // @[Decode.scala 145:15]
+  wire  _lsuEn_T_18 = _lsuEn_T_6 & _lsuEn_T_17; // @[Decode.scala 144:50]
+  wire  lsuEn = ~isLsu | _lsuEn_T_18; // @[Decode.scala 142:22]
+  wire  mulEn = ~isMul | ~io_serializeIn_mul; // @[Decode.scala 150:22]
+  wire  _vinstEn_T_6 = ~(io_vinst_op != 5'h0 & ~io_vinst_ready); // @[Decode.scala 155:17]
+  wire  vinstEn = ~(isVIop & io_serializeIn_brcond) & _vinstEn_T_6; // @[Decode.scala 154:76]
   wire  aluValid_value__0 = io_alu_op[0] | io_alu_op[1]; // @[Library.scala 194:39]
   wire  aluValid_value__1 = io_alu_op[2] | io_alu_op[3]; // @[Library.scala 194:39]
   wire  aluValid_value__2 = io_alu_op[4] | io_alu_op[5]; // @[Library.scala 194:39]
@@ -13410,32 +12292,30 @@
   wire  aluValid_value_1_1 = aluValid_value__2 | aluValid_value__3; // @[Library.scala 194:39]
   wire  aluValid_value_1_2 = aluValid_value__4 | aluValid_value__5; // @[Library.scala 194:39]
   wire  aluValid_value_1_3 = aluValid_value__6 | aluValid_value__7; // @[Library.scala 194:39]
-  wire  aluValid_value_1_4 = aluValid_value__8 | aluValid_value__9; // @[Library.scala 194:39]
   wire  aluValid_value_2_0 = aluValid_value_1_0 | aluValid_value_1_1; // @[Library.scala 194:39]
   wire  aluValid_value_2_1 = aluValid_value_1_2 | aluValid_value_1_3; // @[Library.scala 194:39]
   wire  aluValid_value_3_0 = aluValid_value_2_0 | aluValid_value_2_1; // @[Library.scala 194:39]
-  wire  aluValid_value_4_0 = aluValid_value_3_0 | aluValid_value_1_4; // @[Library.scala 194:39]
-  wire  aluOp_1 = d_io_sub; // @[Decode.scala 182:19 189:19]
-  wire  aluOp_0 = d_io_auipc | d_io_addi | d_io_add; // @[Decode.scala 188:46]
-  wire  aluOp_3 = d_io_sltiu | d_io_sltu; // @[Decode.scala 191:33]
-  wire  aluOp_2 = d_io_slti | d_io_slt; // @[Decode.scala 190:32]
-  wire  aluOp_5 = d_io_ori | d_io_or; // @[Decode.scala 193:31]
-  wire  aluOp_4 = d_io_xori | d_io_xor; // @[Decode.scala 192:32]
-  wire  aluOp_8 = d_io_srli | d_io_srl; // @[Decode.scala 196:32]
-  wire  aluOp_7 = d_io_slli | d_io_sll; // @[Decode.scala 195:32]
-  wire  aluOp_6 = d_io_andi | d_io_and; // @[Decode.scala 194:32]
-  wire [8:0] io_alu_op_lo = {aluOp_8,aluOp_7,aluOp_6,aluOp_5,aluOp_4,aluOp_3,aluOp_2,aluOp_1,aluOp_0}; // @[Decode.scala 186:22]
-  wire  aluOp_10 = d_io_lui; // @[Decode.scala 182:19 198:19]
-  wire  aluOp_9 = d_io_srai | d_io_sra; // @[Decode.scala 197:32]
-  wire  aluOp_13 = d_io_ctz; // @[Decode.scala 182:19 201:19]
-  wire  aluOp_12 = d_io_clz; // @[Decode.scala 182:19 200:19]
-  wire  aluOp_11 = d_io_clb; // @[Decode.scala 182:19 199:19]
-  wire  aluOp_15 = d_io_min; // @[Decode.scala 182:19 203:19]
-  wire  aluOp_14 = d_io_pcnt; // @[Decode.scala 182:19 202:19]
-  wire  aluOp_18 = d_io_maxu; // @[Decode.scala 182:19 206:19]
-  wire  aluOp_17 = d_io_max; // @[Decode.scala 182:19 205:19]
-  wire  aluOp_16 = d_io_minu; // @[Decode.scala 182:19 204:19]
-  wire [9:0] io_alu_op_hi = {aluOp_18,aluOp_17,aluOp_16,aluOp_15,aluOp_14,aluOp_13,aluOp_12,aluOp_11,aluOp_10,aluOp_9}; // @[Decode.scala 186:22]
+  wire  aluValid_value_4_0 = aluValid_value_3_0 | aluValid_value__8; // @[Library.scala 194:39]
+  wire  aluOp_1 = d_io_sub; // @[Decode.scala 163:19 170:19]
+  wire  aluOp_0 = d_io_auipc | d_io_addi | d_io_add; // @[Decode.scala 169:46]
+  wire  aluOp_3 = d_io_sltiu | d_io_sltu; // @[Decode.scala 172:33]
+  wire  aluOp_2 = d_io_slti | d_io_slt; // @[Decode.scala 171:32]
+  wire  aluOp_5 = d_io_ori | d_io_or; // @[Decode.scala 174:31]
+  wire  aluOp_4 = d_io_xori | d_io_xor; // @[Decode.scala 173:32]
+  wire  aluOp_8 = d_io_srli | d_io_srl; // @[Decode.scala 177:32]
+  wire  aluOp_7 = d_io_slli | d_io_sll; // @[Decode.scala 176:32]
+  wire  aluOp_6 = d_io_andi | d_io_and; // @[Decode.scala 175:32]
+  wire [8:0] io_alu_op_lo = {aluOp_8,aluOp_7,aluOp_6,aluOp_5,aluOp_4,aluOp_3,aluOp_2,aluOp_1,aluOp_0}; // @[Decode.scala 167:22]
+  wire  aluOp_10 = d_io_lui; // @[Decode.scala 163:19 179:19]
+  wire  aluOp_9 = d_io_srai | d_io_sra; // @[Decode.scala 178:32]
+  wire  aluOp_12 = d_io_ctz; // @[Decode.scala 163:19 181:19]
+  wire  aluOp_11 = d_io_clz; // @[Decode.scala 163:19 180:19]
+  wire  aluOp_14 = d_io_min; // @[Decode.scala 163:19 183:19]
+  wire  aluOp_13 = d_io_pcnt; // @[Decode.scala 163:19 182:19]
+  wire  aluOp_17 = d_io_maxu; // @[Decode.scala 163:19 186:19]
+  wire  aluOp_16 = d_io_max; // @[Decode.scala 163:19 185:19]
+  wire  aluOp_15 = d_io_minu; // @[Decode.scala 163:19 184:19]
+  wire [8:0] io_alu_op_hi = {aluOp_17,aluOp_16,aluOp_15,aluOp_14,aluOp_13,aluOp_12,aluOp_11,aluOp_10,aluOp_9}; // @[Decode.scala 167:22]
   wire  bruValid_value__8 = io_bru_op[16]; // @[Library.scala 182:26]
   wire  bruValid_value__0 = io_bru_op[0] | io_bru_op[1]; // @[Library.scala 194:39]
   wire  bruValid_value__1 = io_bru_op[2] | io_bru_op[3]; // @[Library.scala 194:39]
@@ -13453,18 +12333,18 @@
   wire  bruValid_value_2_1 = bruValid_value_1_2 | bruValid_value_1_3; // @[Library.scala 194:39]
   wire  bruValid_value_3_0 = bruValid_value_2_0 | bruValid_value_2_1; // @[Library.scala 194:39]
   wire  bruValid_value_4_0 = bruValid_value_3_0 | bruValid_value__8; // @[Library.scala 194:39]
-  wire  bruOp_1 = d_io_jalr; // @[Decode.scala 210:19 220:19]
-  wire  bruOp_0 = d_io_jal; // @[Decode.scala 210:19 219:19]
-  wire  bruOp_3 = d_io_bne; // @[Decode.scala 210:19 222:19]
-  wire  bruOp_2 = d_io_beq; // @[Decode.scala 210:19 221:19]
-  wire  bruOp_5 = d_io_bge; // @[Decode.scala 210:19 224:19]
-  wire  bruOp_4 = d_io_blt; // @[Decode.scala 210:19 223:19]
-  wire  bruOp_7 = d_io_bgeu; // @[Decode.scala 210:19 226:19]
-  wire  bruOp_6 = d_io_bltu; // @[Decode.scala 210:19 225:19]
-  wire [7:0] io_bru_op_lo = {bruOp_7,bruOp_6,bruOp_5,bruOp_4,bruOp_3,bruOp_2,bruOp_1,bruOp_0}; // @[Decode.scala 214:22]
-  wire  bruOp_16 = d_io_undef; // @[Decode.scala 210:19 235:21]
-  wire [8:0] io_bru_op_hi = {bruOp_16,1'h0,1'h0,2'h0,4'h0}; // @[Decode.scala 214:22]
-  wire [31:0] _io_bru_target_T_1 = io_inst_inst[2] ? d_io_immjal : d_io_immbr; // @[Decode.scala 216:38]
+  wire  bruOp_1 = d_io_jalr; // @[Decode.scala 190:19 200:19]
+  wire  bruOp_0 = d_io_jal; // @[Decode.scala 190:19 199:19]
+  wire  bruOp_3 = d_io_bne; // @[Decode.scala 190:19 202:19]
+  wire  bruOp_2 = d_io_beq; // @[Decode.scala 190:19 201:19]
+  wire  bruOp_5 = d_io_bge; // @[Decode.scala 190:19 204:19]
+  wire  bruOp_4 = d_io_blt; // @[Decode.scala 190:19 203:19]
+  wire  bruOp_7 = d_io_bgeu; // @[Decode.scala 190:19 206:19]
+  wire  bruOp_6 = d_io_bltu; // @[Decode.scala 190:19 205:19]
+  wire [7:0] io_bru_op_lo = {bruOp_7,bruOp_6,bruOp_5,bruOp_4,bruOp_3,bruOp_2,bruOp_1,bruOp_0}; // @[Decode.scala 194:22]
+  wire  bruOp_16 = d_io_undef; // @[Decode.scala 190:19 215:21]
+  wire [8:0] io_bru_op_hi = {bruOp_16,1'h0,1'h0,2'h0,4'h0}; // @[Decode.scala 194:22]
+  wire [31:0] _io_bru_target_T_1 = io_inst_inst[2] ? d_io_immjal : d_io_immbr; // @[Decode.scala 196:38]
   wire  csrValid_value__1 = io_csr_op[2]; // @[Library.scala 182:26]
   wire  csrValid_value__0 = io_csr_op[0] | io_csr_op[1]; // @[Library.scala 194:39]
   wire  csrValid_value_1_0 = csrValid_value__0 | csrValid_value__1; // @[Library.scala 194:39]
@@ -13474,23 +12354,21 @@
   wire  lsuValid_value__3 = io_lsu_op[6] | io_lsu_op[7]; // @[Library.scala 194:39]
   wire  lsuValid_value__4 = io_lsu_op[8] | io_lsu_op[9]; // @[Library.scala 194:39]
   wire  lsuValid_value__5 = io_lsu_op[10] | io_lsu_op[11]; // @[Library.scala 194:39]
-  wire  lsuValid_value__6 = io_lsu_op[12] | io_lsu_op[13]; // @[Library.scala 194:39]
   wire  lsuValid_value_1_0 = lsuValid_value__0 | lsuValid_value__1; // @[Library.scala 194:39]
   wire  lsuValid_value_1_1 = lsuValid_value__2 | lsuValid_value__3; // @[Library.scala 194:39]
   wire  lsuValid_value_1_2 = lsuValid_value__4 | lsuValid_value__5; // @[Library.scala 194:39]
   wire  lsuValid_value_2_0 = lsuValid_value_1_0 | lsuValid_value_1_1; // @[Library.scala 194:39]
-  wire  lsuValid_value_2_1 = lsuValid_value_1_2 | lsuValid_value__6; // @[Library.scala 194:39]
-  wire  lsuValid_value_3_0 = lsuValid_value_2_0 | lsuValid_value_2_1; // @[Library.scala 194:39]
-  wire  lsuOp_2 = d_io_lw; // @[Decode.scala 252:19 261:18]
-  wire  lsuOp_1 = d_io_lh; // @[Decode.scala 252:19 260:18]
-  wire  lsuOp_0 = d_io_lb; // @[Decode.scala 252:19 259:18]
-  wire  lsuOp_4 = d_io_lhu; // @[Decode.scala 252:19 263:18]
-  wire  lsuOp_3 = d_io_lbu; // @[Decode.scala 252:19 262:18]
-  wire  lsuOp_6 = d_io_sh; // @[Decode.scala 252:19 265:18]
-  wire  lsuOp_5 = d_io_sb; // @[Decode.scala 252:19 264:18]
-  wire [6:0] io_lsu_op_lo = {lsuOp_6,lsuOp_5,lsuOp_4,lsuOp_3,lsuOp_2,lsuOp_1,lsuOp_0}; // @[Decode.scala 257:22]
-  wire  lsuOp_7 = d_io_sw; // @[Decode.scala 252:19 266:18]
-  wire [6:0] io_lsu_op_hi = {vldst,1'h0,2'h0,2'h0,lsuOp_7}; // @[Decode.scala 257:22]
+  wire  lsuValid_value_3_0 = lsuValid_value_2_0 | lsuValid_value_1_2; // @[Library.scala 194:39]
+  wire  lsuOp_2 = d_io_lw; // @[Decode.scala 232:19 241:18]
+  wire  lsuOp_1 = d_io_lh; // @[Decode.scala 232:19 240:18]
+  wire  lsuOp_0 = d_io_lb; // @[Decode.scala 232:19 239:18]
+  wire  lsuOp_5 = d_io_sb; // @[Decode.scala 232:19 244:18]
+  wire  lsuOp_4 = d_io_lhu; // @[Decode.scala 232:19 243:18]
+  wire  lsuOp_3 = d_io_lbu; // @[Decode.scala 232:19 242:18]
+  wire [5:0] io_lsu_op_lo = {lsuOp_5,lsuOp_4,lsuOp_3,lsuOp_2,lsuOp_1,lsuOp_0}; // @[Decode.scala 237:22]
+  wire  lsuOp_7 = d_io_sw; // @[Decode.scala 232:19 246:18]
+  wire  lsuOp_6 = d_io_sh; // @[Decode.scala 232:19 245:18]
+  wire [5:0] io_lsu_op_hi = {vldst,1'h0,1'h0,1'h0,lsuOp_7,lsuOp_6}; // @[Decode.scala 237:22]
   wire  mluValid_value__4 = io_mlu_op[8]; // @[Library.scala 182:26]
   wire  mluValid_value__0 = io_mlu_op[0] | io_mlu_op[1]; // @[Library.scala 194:39]
   wire  mluValid_value__1 = io_mlu_op[2] | io_mlu_op[3]; // @[Library.scala 194:39]
@@ -13500,57 +12378,53 @@
   wire  mluValid_value_1_1 = mluValid_value__2 | mluValid_value__3; // @[Library.scala 194:39]
   wire  mluValid_value_2_0 = mluValid_value_1_0 | mluValid_value_1_1; // @[Library.scala 194:39]
   wire  mluValid_value_3_0 = mluValid_value_2_0 | mluValid_value__4; // @[Library.scala 194:39]
-  wire  mluOp_1 = d_io_mulh; // @[Decode.scala 276:19 283:22]
-  wire  mluOp_0 = d_io_mul; // @[Decode.scala 276:19 282:22]
-  wire  mluOp_3 = d_io_mulhu; // @[Decode.scala 276:19 285:22]
-  wire  mluOp_2 = d_io_mulhsu; // @[Decode.scala 276:19 284:22]
-  wire [3:0] io_mlu_op_lo = {mluOp_3,mluOp_2,mluOp_1,mluOp_0}; // @[Decode.scala 280:22]
-  wire  mluOp_5 = d_io_mulhsur; // @[Decode.scala 276:19 287:22]
-  wire  mluOp_4 = d_io_mulhr; // @[Decode.scala 276:19 286:22]
-  wire  mluOp_8 = d_io_dmulhr; // @[Decode.scala 276:19 290:22]
-  wire  mluOp_7 = d_io_dmulh; // @[Decode.scala 276:19 289:22]
-  wire  mluOp_6 = d_io_mulhur; // @[Decode.scala 276:19 288:22]
-  wire [4:0] io_mlu_op_hi = {mluOp_8,mluOp_7,mluOp_6,mluOp_5,mluOp_4}; // @[Decode.scala 280:22]
+  wire  mluOp_1 = d_io_mulh; // @[Decode.scala 255:19 262:22]
+  wire  mluOp_0 = d_io_mul; // @[Decode.scala 255:19 261:22]
+  wire  mluOp_3 = d_io_mulhu; // @[Decode.scala 255:19 264:22]
+  wire  mluOp_2 = d_io_mulhsu; // @[Decode.scala 255:19 263:22]
+  wire [3:0] io_mlu_op_lo = {mluOp_3,mluOp_2,mluOp_1,mluOp_0}; // @[Decode.scala 259:22]
+  wire  mluOp_5 = d_io_mulhsur; // @[Decode.scala 255:19 266:22]
+  wire  mluOp_4 = d_io_mulhr; // @[Decode.scala 255:19 265:22]
+  wire  mluOp_8 = d_io_dmulhr; // @[Decode.scala 255:19 269:22]
+  wire  mluOp_7 = d_io_dmulh; // @[Decode.scala 255:19 268:22]
+  wire  mluOp_6 = d_io_mulhur; // @[Decode.scala 255:19 267:22]
+  wire [4:0] io_mlu_op_hi = {mluOp_8,mluOp_7,mluOp_6,mluOp_5,mluOp_4}; // @[Decode.scala 259:22]
   wire  dvuValid_value__0 = io_dvu_op[0] | io_dvu_op[1]; // @[Library.scala 194:39]
   wire  dvuValid_value__1 = io_dvu_op[2] | io_dvu_op[3]; // @[Library.scala 194:39]
   wire  dvuValid_value_1_0 = dvuValid_value__0 | dvuValid_value__1; // @[Library.scala 194:39]
-  wire  dvuEn = ~dvuValid_value_1_0; // @[Decode.scala 305:34]
-  wire [13:0] io_fpu_op_hi = {fpuRs2,1'h0,2'h0,3'h0,7'h0}; // @[Decode.scala 313:22]
-  wire  vinstOp_0 = d_io_getvl; // @[Decode.scala 349:21 361:24]
-  wire  vinstOp_1 = d_io_getmaxvl; // @[Decode.scala 349:21 362:27]
+  wire  dvuEn = ~dvuValid_value_1_0; // @[Decode.scala 284:34]
+  wire  vinstOp_0 = d_io_getvl; // @[Decode.scala 288:21 299:24]
+  wire  vinstOp_1 = d_io_getmaxvl; // @[Decode.scala 288:21 300:27]
   wire  vinstValid_value__0 = vinstOp_0 | vinstOp_1; // @[Library.scala 194:39]
-  wire  vinstOp_2 = d_io_vld; // @[Decode.scala 349:21 357:22]
-  wire  vinstOp_3 = d_io_vst; // @[Decode.scala 349:21 358:22]
+  wire  vinstOp_2 = d_io_vld; // @[Decode.scala 288:21 296:22]
+  wire  vinstOp_3 = d_io_vst; // @[Decode.scala 288:21 297:22]
   wire  vinstValid_value__1 = vinstOp_2 | vinstOp_3; // @[Library.scala 194:39]
-  wire  vinstOp_4 = d_io_viop; // @[Decode.scala 349:21 359:23]
-  wire  vinstOp_5 = d_io_vfop; // @[Decode.scala 349:21 360:23]
-  wire  vinstValid_value__2 = vinstOp_4 | vinstOp_5; // @[Library.scala 194:39]
   wire  vinstValid_value_1_0 = vinstValid_value__0 | vinstValid_value__1; // @[Library.scala 194:39]
-  wire  vinstValid_value_2_0 = vinstValid_value_1_0 | vinstValid_value__2; // @[Library.scala 194:39]
-  wire [2:0] io_vinst_op_lo = {vinstOp_2,vinstOp_1,vinstOp_0}; // @[Decode.scala 355:26]
-  wire [2:0] io_vinst_op_hi = {vinstOp_5,vinstOp_4,vinstOp_3}; // @[Decode.scala 355:26]
-  wire  _io_rs1Read_valid_T = isCondBr | isAluReg; // @[Decode.scala 368:45]
-  wire  _io_rs1Read_valid_T_3 = isCondBr | isAluReg | isAluImm | isAlu1Bit | isAlu2Bit; // @[Decode.scala 368:82]
-  wire  _io_rs1Read_valid_T_6 = _io_rs1Read_valid_T_3 | isMul; // @[Decode.scala 369:44]
-  wire  _io_rs1Read_valid_T_13 = _io_rs1Read_valid_T_6 | d_io_getvl | d_io_vld; // @[Decode.scala 370:79]
-  wire  _io_rs1Read_valid_T_14 = _io_rs1Read_valid_T_13 | d_io_vst; // @[Decode.scala 371:32]
-  wire  _io_rs2Read_valid_T_2 = _io_rs1Read_valid_T | isAlu2Bit | isStore; // @[Decode.scala 372:70]
-  wire  _io_rs2Read_valid_T_8 = _io_rs2Read_valid_T_2 | isMul | d_io_getvl | d_io_vld; // @[Decode.scala 373:77]
-  wire  _io_rs2Read_valid_T_10 = _io_rs2Read_valid_T_8 | d_io_vst | d_io_viop; // @[Decode.scala 374:44]
-  wire  _io_rs2Set_value_T = d_io_auipc | d_io_lui; // @[Decode.scala 389:45]
-  wire  _rdMark_valid_T_4 = lsuValid_value_3_0 & isLoad; // @[Decode.scala 395:16]
-  wire  _rdMark_valid_T_5 = aluValid_value_4_0 | csrValid_value_1_0 | mluValid_value_3_0 | _rdMark_valid_T_4; // @[Decode.scala 394:68]
-  wire  _rdMark_valid_T_13 = _rdMark_valid_T_5 | d_io_getvl; // @[Decode.scala 396:55]
-  wire  _rdMark_valid_T_19 = bruValid_value_4_0 & (bruOp_0 | bruOp_1) & rdAddr != 5'h0; // @[Decode.scala 398:55]
-  wire  rdMark_valid = _rdMark_valid_T_13 | d_io_getmaxvl | vldst_wb | _rdMark_valid_T_19; // @[Decode.scala 397:47]
-  wire  _io_busRead_bypass_T_9 = io_inst_inst[11:7] == 5'h0; // @[Decode.scala 413:65]
-  wire  _io_busRead_bypass_T_10 = ~io_inst_inst[5] | io_inst_inst[6] ? rs2Addr == 5'h0 : _io_busRead_bypass_T_9; // @[Decode.scala 412:8]
-  wire  storeSelect = io_inst_inst[6:3] == 4'h4 & io_inst_inst[1:0] == 2'h3; // @[Decode.scala 417:47]
-  wire [4:0] _io_busRead_immed_T_3 = storeSelect ? d_io_immst[4:0] : d_io_imm12[4:0]; // @[Decode.scala 420:30]
-  wire  _io_inst_ready_T_7 = ~io_serializeIn_jump; // @[Decode.scala 426:20]
-  wire  _io_inst_ready_T_8 = aluEn & bruEn & lsuEn & mulEn & dvuEn & fpuEn & vinstEn & _io_inst_ready_T_7; // @[Decode.scala 425:93]
-  wire  _io_inst_ready_T_14 = ~d_io_undef; // @[Decode.scala 427:43]
-  DecodedInstruction_3 d ( // @[Decode.scala 91:17]
+  wire  vinstOp_4 = d_io_viop; // @[Decode.scala 288:21 298:23]
+  wire  vinstValid_value_2_0 = vinstValid_value_1_0 | vinstOp_4; // @[Library.scala 194:39]
+  wire [1:0] io_vinst_op_lo = {vinstOp_1,vinstOp_0}; // @[Decode.scala 294:26]
+  wire [2:0] io_vinst_op_hi = {vinstOp_4,vinstOp_3,vinstOp_2}; // @[Decode.scala 294:26]
+  wire  _io_rs1Read_valid_T = isCondBr | isAluReg; // @[Decode.scala 306:45]
+  wire  _io_rs1Read_valid_T_3 = isCondBr | isAluReg | isAluImm | isAlu1Bit | isAlu2Bit; // @[Decode.scala 306:82]
+  wire  _io_rs1Read_valid_T_9 = _io_rs1Read_valid_T_3 | isMul | d_io_getvl; // @[Decode.scala 307:75]
+  wire  _io_rs1Read_valid_T_11 = _io_rs1Read_valid_T_9 | d_io_vld | d_io_vst; // @[Decode.scala 308:46]
+  wire  _io_rs2Read_valid_T_2 = _io_rs1Read_valid_T | isAlu2Bit | isStore; // @[Decode.scala 309:70]
+  wire  _io_rs2Read_valid_T_8 = _io_rs2Read_valid_T_2 | isMul | d_io_getvl | d_io_vld; // @[Decode.scala 310:77]
+  wire  _io_rs2Read_valid_T_10 = _io_rs2Read_valid_T_8 | d_io_vst | d_io_viop; // @[Decode.scala 311:44]
+  wire  _io_rs2Set_value_T = d_io_auipc | d_io_lui; // @[Decode.scala 326:45]
+  wire  _rdMark_valid_T_4 = lsuValid_value_3_0 & isLoad; // @[Decode.scala 332:16]
+  wire  _rdMark_valid_T_5 = aluValid_value_4_0 | csrValid_value_1_0 | mluValid_value_3_0 | _rdMark_valid_T_4; // @[Decode.scala 331:68]
+  wire  _rdMark_valid_T_6 = _rdMark_valid_T_5 | d_io_getvl; // @[Decode.scala 332:26]
+  wire  _rdMark_valid_T_12 = bruValid_value_4_0 & (bruOp_0 | bruOp_1) & rdAddr != 5'h0; // @[Decode.scala 334:55]
+  wire  rdMark_valid = _rdMark_valid_T_6 | d_io_getmaxvl | vldst_wb | _rdMark_valid_T_12; // @[Decode.scala 333:47]
+  wire  _io_busRead_bypass_T_9 = io_inst_inst[11:7] == 5'h0; // @[Decode.scala 349:65]
+  wire  _io_busRead_bypass_T_10 = ~io_inst_inst[5] | io_inst_inst[6] ? rs2Addr == 5'h0 : _io_busRead_bypass_T_9; // @[Decode.scala 348:8]
+  wire  storeSelect = io_inst_inst[6:3] == 4'h4 & io_inst_inst[1:0] == 2'h3; // @[Decode.scala 353:47]
+  wire [4:0] _io_busRead_immed_T_3 = storeSelect ? d_io_immst[4:0] : d_io_imm12[4:0]; // @[Decode.scala 356:30]
+  wire  _io_inst_ready_T_6 = ~io_serializeIn_jump; // @[Decode.scala 362:20]
+  wire  _io_inst_ready_T_7 = aluEn & bruEn & lsuEn & mulEn & dvuEn & vinstEn & _io_inst_ready_T_6; // @[Decode.scala 361:84]
+  wire  _io_inst_ready_T_13 = ~d_io_undef; // @[Decode.scala 363:43]
+  DecodedInstruction_3 d ( // @[Decode.scala 87:17]
     .clock(d_clock),
     .reset(d_reset),
     .io_addr(d_io_addr),
@@ -13614,33 +12488,6 @@
     .io_divu(d_io_divu),
     .io_rem(d_io_rem),
     .io_remu(d_io_remu),
-    .io_flw(d_io_flw),
-    .io_fsw(d_io_fsw),
-    .io_fmadd(d_io_fmadd),
-    .io_fmsub(d_io_fmsub),
-    .io_fnmsub(d_io_fnmsub),
-    .io_fnmadd(d_io_fnmadd),
-    .io_fadd(d_io_fadd),
-    .io_fsub(d_io_fsub),
-    .io_fmul(d_io_fmul),
-    .io_fdiv(d_io_fdiv),
-    .io_fsqrt(d_io_fsqrt),
-    .io_fsgnj(d_io_fsgnj),
-    .io_fsgnjn(d_io_fsgnjn),
-    .io_fsgnjx(d_io_fsgnjx),
-    .io_fmin(d_io_fmin),
-    .io_fmax(d_io_fmax),
-    .io_fcvtws(d_io_fcvtws),
-    .io_fcvtwus(d_io_fcvtwus),
-    .io_fmvxw(d_io_fmvxw),
-    .io_feq(d_io_feq),
-    .io_flt(d_io_flt),
-    .io_fle(d_io_fle),
-    .io_fclass(d_io_fclass),
-    .io_fcvtsw(d_io_fcvtsw),
-    .io_fcvtswu(d_io_fcvtswu),
-    .io_fmvwx(d_io_fmvwx),
-    .io_clb(d_io_clb),
     .io_clz(d_io_clz),
     .io_ctz(d_io_ctz),
     .io_pcnt(d_io_pcnt),
@@ -13653,7 +12500,6 @@
     .io_vld(d_io_vld),
     .io_vst(d_io_vst),
     .io_viop(d_io_viop),
-    .io_vfop(d_io_vfop),
     .io_ebreak(d_io_ebreak),
     .io_ecall(d_io_ecall),
     .io_eexit(d_io_eexit),
@@ -13667,53 +12513,51 @@
     .io_flushall(d_io_flushall),
     .io_slog(d_io_slog)
   );
-  assign io_inst_ready = _io_inst_ready_T_8 & ~io_halted & ~io_interlock & _io_inst_ready_T_14; // @[Decode.scala 426:72]
-  assign io_rs1Read_valid = decodeEn & _io_rs1Read_valid_T_14; // @[Decode.scala 368:32]
-  assign io_rs1Read_addr = io_inst_inst[0] ? io_inst_inst[19:15] : rs3Addr; // @[Decode.scala 377:25]
-  assign io_rs1Set_valid = decodeEn & d_io_auipc; // @[Decode.scala 383:31]
-  assign io_rs1Set_value = io_inst_addr; // @[Decode.scala 386:25]
-  assign io_rs2Read_valid = decodeEn & _io_rs2Read_valid_T_10; // @[Decode.scala 372:32]
-  assign io_rs2Read_addr = io_inst_inst[24:20]; // @[Decode.scala 100:29]
-  assign io_rs2Set_valid = io_rs1Set_valid | decodeEn & (isAluImm | isAlu1Bit | d_io_lui); // @[Decode.scala 384:38]
+  assign io_inst_ready = _io_inst_ready_T_7 & ~io_halted & ~io_interlock & _io_inst_ready_T_13; // @[Decode.scala 362:72]
+  assign io_rs1Read_valid = decodeEn & _io_rs1Read_valid_T_11; // @[Decode.scala 306:32]
+  assign io_rs1Read_addr = io_inst_inst[0] ? io_inst_inst[19:15] : rs3Addr; // @[Decode.scala 314:25]
+  assign io_rs1Set_valid = decodeEn & d_io_auipc; // @[Decode.scala 320:31]
+  assign io_rs1Set_value = io_inst_addr; // @[Decode.scala 323:25]
+  assign io_rs2Read_valid = decodeEn & _io_rs2Read_valid_T_10; // @[Decode.scala 309:32]
+  assign io_rs2Read_addr = io_inst_inst[24:20]; // @[Decode.scala 96:29]
+  assign io_rs2Set_valid = io_rs1Set_valid | decodeEn & (isAluImm | isAlu1Bit | d_io_lui); // @[Decode.scala 321:38]
   assign io_rs2Set_value = _io_rs2Set_value_T ? d_io_imm20 : d_io_imm12; // @[Mux.scala 101:16]
-  assign io_rdMark_valid = decodeEn & rdMark_valid; // @[Decode.scala 404:31]
-  assign io_rdMark_addr = vldst ? io_inst_inst[19:15] : io_inst_inst[11:7]; // @[Decode.scala 98:20]
-  assign io_busRead_bypass = io_inst_inst[31:25] == 7'h0 & _io_busRead_bypass_T_10; // @[Decode.scala 411:52]
+  assign io_rdMark_valid = decodeEn & rdMark_valid; // @[Decode.scala 340:31]
+  assign io_rdMark_addr = vldst ? io_inst_inst[19:15] : io_inst_inst[11:7]; // @[Decode.scala 94:20]
+  assign io_busRead_bypass = io_inst_inst[31:25] == 7'h0 & _io_busRead_bypass_T_10; // @[Decode.scala 347:52]
   assign io_busRead_immed = {d_io_imm12[31:5],_io_busRead_immed_T_3}; // @[Cat.scala 31:58]
-  assign io_alu_valid = decodeEn & aluValid_value_4_0; // @[Decode.scala 184:28]
-  assign io_alu_addr = vldst ? io_inst_inst[19:15] : io_inst_inst[11:7]; // @[Decode.scala 98:20]
-  assign io_alu_op = {io_alu_op_hi,io_alu_op_lo}; // @[Decode.scala 186:22]
-  assign io_bru_valid = decodeEn & bruValid_value_4_0; // @[Decode.scala 212:28]
-  assign io_bru_fwd = io_inst_brchFwd; // @[Decode.scala 213:14]
-  assign io_bru_op = {io_bru_op_hi,io_bru_op_lo}; // @[Decode.scala 214:22]
-  assign io_bru_pc = io_inst_addr; // @[Decode.scala 215:13]
-  assign io_bru_target = io_inst_addr + _io_bru_target_T_1; // @[Decode.scala 216:33]
-  assign io_bru_link = vldst ? io_inst_inst[19:15] : io_inst_inst[11:7]; // @[Decode.scala 98:20]
-  assign io_csr_op = 3'h0; // @[Decode.scala 244:22]
-  assign io_lsu_valid = decodeEn & lsuValid_value_3_0; // @[Decode.scala 254:28]
-  assign io_lsu_addr = vldst ? io_inst_inst[19:15] : io_inst_inst[11:7]; // @[Decode.scala 98:20]
-  assign io_lsu_op = {io_lsu_op_hi,io_lsu_op_lo}; // @[Decode.scala 257:22]
-  assign io_mlu_valid = decodeEn & mluValid_value_3_0; // @[Decode.scala 278:28]
-  assign io_mlu_addr = vldst ? io_inst_inst[19:15] : io_inst_inst[11:7]; // @[Decode.scala 98:20]
-  assign io_mlu_op = {io_mlu_op_hi,io_mlu_op_lo}; // @[Decode.scala 280:22]
-  assign io_dvu_op = 4'h0; // @[Decode.scala 298:22]
-  assign io_fpu_raddr_1 = io_inst_inst[24:20]; // @[Decode.scala 100:29]
-  assign io_fpu_op = {io_fpu_op_hi,13'h0}; // @[Decode.scala 313:22]
-  assign io_vinst_valid = decodeEn & vinstValid_value_2_0; // @[Decode.scala 352:30]
-  assign io_vinst_addr = vldst ? io_inst_inst[19:15] : io_inst_inst[11:7]; // @[Decode.scala 98:20]
-  assign io_vinst_inst = io_inst_inst; // @[Decode.scala 354:17]
-  assign io_vinst_op = {io_vinst_op_hi,io_vinst_op_lo}; // @[Decode.scala 355:26]
+  assign io_alu_valid = decodeEn & aluValid_value_4_0; // @[Decode.scala 165:28]
+  assign io_alu_addr = vldst ? io_inst_inst[19:15] : io_inst_inst[11:7]; // @[Decode.scala 94:20]
+  assign io_alu_op = {io_alu_op_hi,io_alu_op_lo}; // @[Decode.scala 167:22]
+  assign io_bru_valid = decodeEn & bruValid_value_4_0; // @[Decode.scala 192:28]
+  assign io_bru_fwd = io_inst_brchFwd; // @[Decode.scala 193:14]
+  assign io_bru_op = {io_bru_op_hi,io_bru_op_lo}; // @[Decode.scala 194:22]
+  assign io_bru_pc = io_inst_addr; // @[Decode.scala 195:13]
+  assign io_bru_target = io_inst_addr + _io_bru_target_T_1; // @[Decode.scala 196:33]
+  assign io_bru_link = vldst ? io_inst_inst[19:15] : io_inst_inst[11:7]; // @[Decode.scala 94:20]
+  assign io_csr_op = 3'h0; // @[Decode.scala 224:22]
+  assign io_lsu_valid = decodeEn & lsuValid_value_3_0; // @[Decode.scala 234:28]
+  assign io_lsu_addr = vldst ? io_inst_inst[19:15] : io_inst_inst[11:7]; // @[Decode.scala 94:20]
+  assign io_lsu_op = {io_lsu_op_hi,io_lsu_op_lo}; // @[Decode.scala 237:22]
+  assign io_mlu_valid = decodeEn & mluValid_value_3_0; // @[Decode.scala 257:28]
+  assign io_mlu_addr = vldst ? io_inst_inst[19:15] : io_inst_inst[11:7]; // @[Decode.scala 94:20]
+  assign io_mlu_op = {io_mlu_op_hi,io_mlu_op_lo}; // @[Decode.scala 259:22]
+  assign io_dvu_op = 4'h0; // @[Decode.scala 277:22]
+  assign io_vinst_valid = decodeEn & vinstValid_value_2_0; // @[Decode.scala 291:30]
+  assign io_vinst_addr = vldst ? io_inst_inst[19:15] : io_inst_inst[11:7]; // @[Decode.scala 94:20]
+  assign io_vinst_inst = io_inst_inst; // @[Decode.scala 293:17]
+  assign io_vinst_op = {io_vinst_op_hi,io_vinst_op_lo}; // @[Decode.scala 294:26]
   assign d_clock = clock;
   assign d_reset = reset;
-  assign d_io_addr = io_inst_addr; // @[Decode.scala 92:13]
-  assign d_io_inst = io_inst_inst; // @[Decode.scala 93:13]
+  assign d_io_addr = io_inst_addr; // @[Decode.scala 88:13]
+  assign d_io_inst = io_inst_inst; // @[Decode.scala 89:13]
 endmodule
 module Alu(
   input         clock,
   input         reset,
   input         io_req_valid,
   input  [4:0]  io_req_addr,
-  input  [18:0] io_req_op,
+  input  [17:0] io_req_op,
   input         io_rs1_valid,
   input  [31:0] io_rs1_data,
   input         io_rs2_valid,
@@ -13727,272 +12571,209 @@
   reg [31:0] _RAND_1;
   reg [31:0] _RAND_2;
 `endif // RANDOMIZE_REG_INIT
-  reg  valid; // @[Alu.scala 55:22]
-  reg [4:0] addr; // @[Alu.scala 56:17]
-  reg [18:0] op; // @[Alu.scala 57:19]
-  wire [4:0] shamt = io_rs2_data[4:0]; // @[Alu.scala 73:18]
-  wire [31:0] _io_rd_data_T_2 = io_rs1_data + io_rs2_data; // @[Alu.scala 96:42]
+  reg  valid; // @[Alu.scala 54:22]
+  reg [4:0] addr; // @[Alu.scala 55:17]
+  reg [17:0] op; // @[Alu.scala 56:19]
+  wire [4:0] shamt = io_rs2_data[4:0]; // @[Alu.scala 72:18]
+  wire [31:0] _io_rd_data_T_2 = io_rs1_data + io_rs2_data; // @[Alu.scala 95:42]
   wire [31:0] _io_rd_data_T_3 = op[0] ? _io_rd_data_T_2 : 32'h0; // @[Library.scala 8:8]
-  wire [31:0] _io_rd_data_T_6 = io_rs1_data - io_rs2_data; // @[Alu.scala 97:42]
+  wire [31:0] _io_rd_data_T_6 = io_rs1_data - io_rs2_data; // @[Alu.scala 96:42]
   wire [31:0] _io_rd_data_T_7 = op[1] ? _io_rd_data_T_6 : 32'h0; // @[Library.scala 8:8]
-  wire [31:0] _io_rd_data_T_8 = _io_rd_data_T_3 | _io_rd_data_T_7; // @[Alu.scala 96:49]
-  wire  _io_rd_data_T_12 = $signed(io_rs1_data) < $signed(io_rs2_data); // @[Alu.scala 98:49]
+  wire [31:0] _io_rd_data_T_8 = _io_rd_data_T_3 | _io_rd_data_T_7; // @[Alu.scala 95:49]
+  wire  _io_rd_data_T_12 = $signed(io_rs1_data) < $signed(io_rs2_data); // @[Alu.scala 97:49]
   wire  _io_rd_data_T_13 = op[2] & _io_rd_data_T_12; // @[Library.scala 12:8]
-  wire [31:0] _GEN_2 = {{31'd0}, _io_rd_data_T_13}; // @[Alu.scala 97:49]
-  wire [31:0] _io_rd_data_T_14 = _io_rd_data_T_8 | _GEN_2; // @[Alu.scala 97:49]
-  wire  _io_rd_data_T_16 = io_rs1_data < io_rs2_data; // @[Alu.scala 99:42]
+  wire [31:0] _GEN_2 = {{31'd0}, _io_rd_data_T_13}; // @[Alu.scala 96:49]
+  wire [31:0] _io_rd_data_T_14 = _io_rd_data_T_8 | _GEN_2; // @[Alu.scala 96:49]
+  wire  _io_rd_data_T_16 = io_rs1_data < io_rs2_data; // @[Alu.scala 98:42]
   wire  _io_rd_data_T_17 = op[3] & _io_rd_data_T_16; // @[Library.scala 12:8]
-  wire [31:0] _GEN_3 = {{31'd0}, _io_rd_data_T_17}; // @[Alu.scala 98:63]
-  wire [31:0] _io_rd_data_T_18 = _io_rd_data_T_14 | _GEN_3; // @[Alu.scala 98:63]
-  wire [31:0] _io_rd_data_T_20 = io_rs1_data ^ io_rs2_data; // @[Alu.scala 100:42]
+  wire [31:0] _GEN_3 = {{31'd0}, _io_rd_data_T_17}; // @[Alu.scala 97:63]
+  wire [31:0] _io_rd_data_T_18 = _io_rd_data_T_14 | _GEN_3; // @[Alu.scala 97:63]
+  wire [31:0] _io_rd_data_T_20 = io_rs1_data ^ io_rs2_data; // @[Alu.scala 99:42]
   wire [31:0] _io_rd_data_T_21 = op[4] ? _io_rd_data_T_20 : 32'h0; // @[Library.scala 8:8]
-  wire [31:0] _io_rd_data_T_22 = _io_rd_data_T_18 | _io_rd_data_T_21; // @[Alu.scala 99:49]
-  wire [31:0] _io_rd_data_T_24 = io_rs1_data | io_rs2_data; // @[Alu.scala 101:42]
+  wire [31:0] _io_rd_data_T_22 = _io_rd_data_T_18 | _io_rd_data_T_21; // @[Alu.scala 98:49]
+  wire [31:0] _io_rd_data_T_24 = io_rs1_data | io_rs2_data; // @[Alu.scala 100:42]
   wire [31:0] _io_rd_data_T_25 = op[5] ? _io_rd_data_T_24 : 32'h0; // @[Library.scala 8:8]
-  wire [31:0] _io_rd_data_T_26 = _io_rd_data_T_22 | _io_rd_data_T_25; // @[Alu.scala 100:49]
-  wire [31:0] _io_rd_data_T_28 = io_rs1_data & io_rs2_data; // @[Alu.scala 102:42]
+  wire [31:0] _io_rd_data_T_26 = _io_rd_data_T_22 | _io_rd_data_T_25; // @[Alu.scala 99:49]
+  wire [31:0] _io_rd_data_T_28 = io_rs1_data & io_rs2_data; // @[Alu.scala 101:42]
   wire [31:0] _io_rd_data_T_29 = op[6] ? _io_rd_data_T_28 : 32'h0; // @[Library.scala 8:8]
-  wire [31:0] _io_rd_data_T_30 = _io_rd_data_T_26 | _io_rd_data_T_29; // @[Alu.scala 101:49]
-  wire [62:0] _GEN_0 = {{31'd0}, io_rs1_data}; // @[Alu.scala 103:42]
-  wire [62:0] _io_rd_data_T_32 = _GEN_0 << shamt; // @[Alu.scala 103:42]
+  wire [31:0] _io_rd_data_T_30 = _io_rd_data_T_26 | _io_rd_data_T_29; // @[Alu.scala 100:49]
+  wire [62:0] _GEN_0 = {{31'd0}, io_rs1_data}; // @[Alu.scala 102:42]
+  wire [62:0] _io_rd_data_T_32 = _GEN_0 << shamt; // @[Alu.scala 102:42]
   wire [62:0] _io_rd_data_T_33 = op[7] ? _io_rd_data_T_32 : 63'h0; // @[Library.scala 8:8]
-  wire [62:0] _GEN_4 = {{31'd0}, _io_rd_data_T_30}; // @[Alu.scala 102:49]
-  wire [62:0] _io_rd_data_T_34 = _GEN_4 | _io_rd_data_T_33; // @[Alu.scala 102:49]
-  wire [31:0] _io_rd_data_T_36 = io_rs1_data >> shamt; // @[Alu.scala 104:42]
+  wire [62:0] _GEN_4 = {{31'd0}, _io_rd_data_T_30}; // @[Alu.scala 101:49]
+  wire [62:0] _io_rd_data_T_34 = _GEN_4 | _io_rd_data_T_33; // @[Alu.scala 101:49]
+  wire [31:0] _io_rd_data_T_36 = io_rs1_data >> shamt; // @[Alu.scala 103:42]
   wire [31:0] _io_rd_data_T_37 = op[8] ? _io_rd_data_T_36 : 32'h0; // @[Library.scala 8:8]
-  wire [62:0] _GEN_5 = {{31'd0}, _io_rd_data_T_37}; // @[Alu.scala 103:52]
-  wire [62:0] _io_rd_data_T_38 = _io_rd_data_T_34 | _GEN_5; // @[Alu.scala 103:52]
-  wire [31:0] _io_rd_data_T_42 = $signed(io_rs1_data) >>> shamt; // @[Alu.scala 105:60]
+  wire [62:0] _GEN_5 = {{31'd0}, _io_rd_data_T_37}; // @[Alu.scala 102:52]
+  wire [62:0] _io_rd_data_T_38 = _io_rd_data_T_34 | _GEN_5; // @[Alu.scala 102:52]
+  wire [31:0] _io_rd_data_T_42 = $signed(io_rs1_data) >>> shamt; // @[Alu.scala 104:60]
   wire [31:0] _io_rd_data_T_43 = op[9] ? _io_rd_data_T_42 : 32'h0; // @[Library.scala 8:8]
-  wire [62:0] _GEN_6 = {{31'd0}, _io_rd_data_T_43}; // @[Alu.scala 104:52]
-  wire [62:0] _io_rd_data_T_44 = _io_rd_data_T_38 | _GEN_6; // @[Alu.scala 104:52]
+  wire [62:0] _GEN_6 = {{31'd0}, _io_rd_data_T_43}; // @[Alu.scala 103:52]
+  wire [62:0] _io_rd_data_T_44 = _io_rd_data_T_38 | _GEN_6; // @[Alu.scala 103:52]
   wire [31:0] _io_rd_data_T_46 = op[10] ? io_rs2_data : 32'h0; // @[Library.scala 8:8]
-  wire [62:0] _GEN_7 = {{31'd0}, _io_rd_data_T_46}; // @[Alu.scala 105:68]
-  wire [62:0] _io_rd_data_T_47 = _io_rd_data_T_44 | _GEN_7; // @[Alu.scala 105:68]
-  wire [31:0] _io_rd_data_clo_T = ~io_rs1_data; // @[Library.scala 280:43]
-  wire [31:0] _GEN_8 = {{16'd0}, _io_rd_data_clo_T[31:16]}; // @[Bitwise.scala 105:31]
-  wire [31:0] _io_rd_data_clo_T_4 = _GEN_8 & 32'hffff; // @[Bitwise.scala 105:31]
-  wire [31:0] _io_rd_data_clo_T_6 = {_io_rd_data_clo_T[15:0], 16'h0}; // @[Bitwise.scala 105:70]
-  wire [31:0] _io_rd_data_clo_T_8 = _io_rd_data_clo_T_6 & 32'hffff0000; // @[Bitwise.scala 105:80]
-  wire [31:0] _io_rd_data_clo_T_9 = _io_rd_data_clo_T_4 | _io_rd_data_clo_T_8; // @[Bitwise.scala 105:39]
-  wire [31:0] _GEN_9 = {{8'd0}, _io_rd_data_clo_T_9[31:8]}; // @[Bitwise.scala 105:31]
-  wire [31:0] _io_rd_data_clo_T_14 = _GEN_9 & 32'hff00ff; // @[Bitwise.scala 105:31]
-  wire [31:0] _io_rd_data_clo_T_16 = {_io_rd_data_clo_T_9[23:0], 8'h0}; // @[Bitwise.scala 105:70]
-  wire [31:0] _io_rd_data_clo_T_18 = _io_rd_data_clo_T_16 & 32'hff00ff00; // @[Bitwise.scala 105:80]
-  wire [31:0] _io_rd_data_clo_T_19 = _io_rd_data_clo_T_14 | _io_rd_data_clo_T_18; // @[Bitwise.scala 105:39]
-  wire [31:0] _GEN_10 = {{4'd0}, _io_rd_data_clo_T_19[31:4]}; // @[Bitwise.scala 105:31]
-  wire [31:0] _io_rd_data_clo_T_24 = _GEN_10 & 32'hf0f0f0f; // @[Bitwise.scala 105:31]
-  wire [31:0] _io_rd_data_clo_T_26 = {_io_rd_data_clo_T_19[27:0], 4'h0}; // @[Bitwise.scala 105:70]
-  wire [31:0] _io_rd_data_clo_T_28 = _io_rd_data_clo_T_26 & 32'hf0f0f0f0; // @[Bitwise.scala 105:80]
-  wire [31:0] _io_rd_data_clo_T_29 = _io_rd_data_clo_T_24 | _io_rd_data_clo_T_28; // @[Bitwise.scala 105:39]
-  wire [31:0] _GEN_11 = {{2'd0}, _io_rd_data_clo_T_29[31:2]}; // @[Bitwise.scala 105:31]
-  wire [31:0] _io_rd_data_clo_T_34 = _GEN_11 & 32'h33333333; // @[Bitwise.scala 105:31]
-  wire [31:0] _io_rd_data_clo_T_36 = {_io_rd_data_clo_T_29[29:0], 2'h0}; // @[Bitwise.scala 105:70]
-  wire [31:0] _io_rd_data_clo_T_38 = _io_rd_data_clo_T_36 & 32'hcccccccc; // @[Bitwise.scala 105:80]
-  wire [31:0] _io_rd_data_clo_T_39 = _io_rd_data_clo_T_34 | _io_rd_data_clo_T_38; // @[Bitwise.scala 105:39]
-  wire [31:0] _GEN_12 = {{1'd0}, _io_rd_data_clo_T_39[31:1]}; // @[Bitwise.scala 105:31]
-  wire [31:0] _io_rd_data_clo_T_44 = _GEN_12 & 32'h55555555; // @[Bitwise.scala 105:31]
-  wire [31:0] _io_rd_data_clo_T_46 = {_io_rd_data_clo_T_39[30:0], 1'h0}; // @[Bitwise.scala 105:70]
-  wire [31:0] _io_rd_data_clo_T_48 = _io_rd_data_clo_T_46 & 32'haaaaaaaa; // @[Bitwise.scala 105:80]
-  wire [31:0] _io_rd_data_clo_T_49 = _io_rd_data_clo_T_44 | _io_rd_data_clo_T_48; // @[Bitwise.scala 105:39]
-  wire [32:0] _io_rd_data_clo_T_50 = {1'h1,_io_rd_data_clo_T_49}; // @[Cat.scala 31:58]
-  wire [5:0] _io_rd_data_clo_T_84 = _io_rd_data_clo_T_50[31] ? 6'h1f : 6'h20; // @[Mux.scala 47:70]
-  wire [5:0] _io_rd_data_clo_T_85 = _io_rd_data_clo_T_50[30] ? 6'h1e : _io_rd_data_clo_T_84; // @[Mux.scala 47:70]
-  wire [5:0] _io_rd_data_clo_T_86 = _io_rd_data_clo_T_50[29] ? 6'h1d : _io_rd_data_clo_T_85; // @[Mux.scala 47:70]
-  wire [5:0] _io_rd_data_clo_T_87 = _io_rd_data_clo_T_50[28] ? 6'h1c : _io_rd_data_clo_T_86; // @[Mux.scala 47:70]
-  wire [5:0] _io_rd_data_clo_T_88 = _io_rd_data_clo_T_50[27] ? 6'h1b : _io_rd_data_clo_T_87; // @[Mux.scala 47:70]
-  wire [5:0] _io_rd_data_clo_T_89 = _io_rd_data_clo_T_50[26] ? 6'h1a : _io_rd_data_clo_T_88; // @[Mux.scala 47:70]
-  wire [5:0] _io_rd_data_clo_T_90 = _io_rd_data_clo_T_50[25] ? 6'h19 : _io_rd_data_clo_T_89; // @[Mux.scala 47:70]
-  wire [5:0] _io_rd_data_clo_T_91 = _io_rd_data_clo_T_50[24] ? 6'h18 : _io_rd_data_clo_T_90; // @[Mux.scala 47:70]
-  wire [5:0] _io_rd_data_clo_T_92 = _io_rd_data_clo_T_50[23] ? 6'h17 : _io_rd_data_clo_T_91; // @[Mux.scala 47:70]
-  wire [5:0] _io_rd_data_clo_T_93 = _io_rd_data_clo_T_50[22] ? 6'h16 : _io_rd_data_clo_T_92; // @[Mux.scala 47:70]
-  wire [5:0] _io_rd_data_clo_T_94 = _io_rd_data_clo_T_50[21] ? 6'h15 : _io_rd_data_clo_T_93; // @[Mux.scala 47:70]
-  wire [5:0] _io_rd_data_clo_T_95 = _io_rd_data_clo_T_50[20] ? 6'h14 : _io_rd_data_clo_T_94; // @[Mux.scala 47:70]
-  wire [5:0] _io_rd_data_clo_T_96 = _io_rd_data_clo_T_50[19] ? 6'h13 : _io_rd_data_clo_T_95; // @[Mux.scala 47:70]
-  wire [5:0] _io_rd_data_clo_T_97 = _io_rd_data_clo_T_50[18] ? 6'h12 : _io_rd_data_clo_T_96; // @[Mux.scala 47:70]
-  wire [5:0] _io_rd_data_clo_T_98 = _io_rd_data_clo_T_50[17] ? 6'h11 : _io_rd_data_clo_T_97; // @[Mux.scala 47:70]
-  wire [5:0] _io_rd_data_clo_T_99 = _io_rd_data_clo_T_50[16] ? 6'h10 : _io_rd_data_clo_T_98; // @[Mux.scala 47:70]
-  wire [5:0] _io_rd_data_clo_T_100 = _io_rd_data_clo_T_50[15] ? 6'hf : _io_rd_data_clo_T_99; // @[Mux.scala 47:70]
-  wire [5:0] _io_rd_data_clo_T_101 = _io_rd_data_clo_T_50[14] ? 6'he : _io_rd_data_clo_T_100; // @[Mux.scala 47:70]
-  wire [5:0] _io_rd_data_clo_T_102 = _io_rd_data_clo_T_50[13] ? 6'hd : _io_rd_data_clo_T_101; // @[Mux.scala 47:70]
-  wire [5:0] _io_rd_data_clo_T_103 = _io_rd_data_clo_T_50[12] ? 6'hc : _io_rd_data_clo_T_102; // @[Mux.scala 47:70]
-  wire [5:0] _io_rd_data_clo_T_104 = _io_rd_data_clo_T_50[11] ? 6'hb : _io_rd_data_clo_T_103; // @[Mux.scala 47:70]
-  wire [5:0] _io_rd_data_clo_T_105 = _io_rd_data_clo_T_50[10] ? 6'ha : _io_rd_data_clo_T_104; // @[Mux.scala 47:70]
-  wire [5:0] _io_rd_data_clo_T_106 = _io_rd_data_clo_T_50[9] ? 6'h9 : _io_rd_data_clo_T_105; // @[Mux.scala 47:70]
-  wire [5:0] _io_rd_data_clo_T_107 = _io_rd_data_clo_T_50[8] ? 6'h8 : _io_rd_data_clo_T_106; // @[Mux.scala 47:70]
-  wire [5:0] _io_rd_data_clo_T_108 = _io_rd_data_clo_T_50[7] ? 6'h7 : _io_rd_data_clo_T_107; // @[Mux.scala 47:70]
-  wire [5:0] _io_rd_data_clo_T_109 = _io_rd_data_clo_T_50[6] ? 6'h6 : _io_rd_data_clo_T_108; // @[Mux.scala 47:70]
-  wire [5:0] _io_rd_data_clo_T_110 = _io_rd_data_clo_T_50[5] ? 6'h5 : _io_rd_data_clo_T_109; // @[Mux.scala 47:70]
-  wire [5:0] _io_rd_data_clo_T_111 = _io_rd_data_clo_T_50[4] ? 6'h4 : _io_rd_data_clo_T_110; // @[Mux.scala 47:70]
-  wire [5:0] _io_rd_data_clo_T_112 = _io_rd_data_clo_T_50[3] ? 6'h3 : _io_rd_data_clo_T_111; // @[Mux.scala 47:70]
-  wire [5:0] _io_rd_data_clo_T_113 = _io_rd_data_clo_T_50[2] ? 6'h2 : _io_rd_data_clo_T_112; // @[Mux.scala 47:70]
-  wire [5:0] _io_rd_data_clo_T_114 = _io_rd_data_clo_T_50[1] ? 6'h1 : _io_rd_data_clo_T_113; // @[Mux.scala 47:70]
-  wire [5:0] io_rd_data_clo = _io_rd_data_clo_T_50[0] ? 6'h0 : _io_rd_data_clo_T_114; // @[Mux.scala 47:70]
-  wire [31:0] _GEN_13 = {{16'd0}, io_rs1_data[31:16]}; // @[Bitwise.scala 105:31]
-  wire [31:0] _io_rd_data_clz_T_3 = _GEN_13 & 32'hffff; // @[Bitwise.scala 105:31]
-  wire [31:0] _io_rd_data_clz_T_5 = {io_rs1_data[15:0], 16'h0}; // @[Bitwise.scala 105:70]
-  wire [31:0] _io_rd_data_clz_T_7 = _io_rd_data_clz_T_5 & 32'hffff0000; // @[Bitwise.scala 105:80]
-  wire [31:0] _io_rd_data_clz_T_8 = _io_rd_data_clz_T_3 | _io_rd_data_clz_T_7; // @[Bitwise.scala 105:39]
-  wire [31:0] _GEN_14 = {{8'd0}, _io_rd_data_clz_T_8[31:8]}; // @[Bitwise.scala 105:31]
-  wire [31:0] _io_rd_data_clz_T_13 = _GEN_14 & 32'hff00ff; // @[Bitwise.scala 105:31]
-  wire [31:0] _io_rd_data_clz_T_15 = {_io_rd_data_clz_T_8[23:0], 8'h0}; // @[Bitwise.scala 105:70]
-  wire [31:0] _io_rd_data_clz_T_17 = _io_rd_data_clz_T_15 & 32'hff00ff00; // @[Bitwise.scala 105:80]
-  wire [31:0] _io_rd_data_clz_T_18 = _io_rd_data_clz_T_13 | _io_rd_data_clz_T_17; // @[Bitwise.scala 105:39]
-  wire [31:0] _GEN_15 = {{4'd0}, _io_rd_data_clz_T_18[31:4]}; // @[Bitwise.scala 105:31]
-  wire [31:0] _io_rd_data_clz_T_23 = _GEN_15 & 32'hf0f0f0f; // @[Bitwise.scala 105:31]
-  wire [31:0] _io_rd_data_clz_T_25 = {_io_rd_data_clz_T_18[27:0], 4'h0}; // @[Bitwise.scala 105:70]
-  wire [31:0] _io_rd_data_clz_T_27 = _io_rd_data_clz_T_25 & 32'hf0f0f0f0; // @[Bitwise.scala 105:80]
-  wire [31:0] _io_rd_data_clz_T_28 = _io_rd_data_clz_T_23 | _io_rd_data_clz_T_27; // @[Bitwise.scala 105:39]
-  wire [31:0] _GEN_16 = {{2'd0}, _io_rd_data_clz_T_28[31:2]}; // @[Bitwise.scala 105:31]
-  wire [31:0] _io_rd_data_clz_T_33 = _GEN_16 & 32'h33333333; // @[Bitwise.scala 105:31]
-  wire [31:0] _io_rd_data_clz_T_35 = {_io_rd_data_clz_T_28[29:0], 2'h0}; // @[Bitwise.scala 105:70]
-  wire [31:0] _io_rd_data_clz_T_37 = _io_rd_data_clz_T_35 & 32'hcccccccc; // @[Bitwise.scala 105:80]
-  wire [31:0] _io_rd_data_clz_T_38 = _io_rd_data_clz_T_33 | _io_rd_data_clz_T_37; // @[Bitwise.scala 105:39]
-  wire [31:0] _GEN_17 = {{1'd0}, _io_rd_data_clz_T_38[31:1]}; // @[Bitwise.scala 105:31]
-  wire [31:0] _io_rd_data_clz_T_43 = _GEN_17 & 32'h55555555; // @[Bitwise.scala 105:31]
-  wire [31:0] _io_rd_data_clz_T_45 = {_io_rd_data_clz_T_38[30:0], 1'h0}; // @[Bitwise.scala 105:70]
-  wire [31:0] _io_rd_data_clz_T_47 = _io_rd_data_clz_T_45 & 32'haaaaaaaa; // @[Bitwise.scala 105:80]
-  wire [31:0] _io_rd_data_clz_T_48 = _io_rd_data_clz_T_43 | _io_rd_data_clz_T_47; // @[Bitwise.scala 105:39]
-  wire [32:0] _io_rd_data_clz_T_49 = {1'h1,_io_rd_data_clz_T_48}; // @[Cat.scala 31:58]
-  wire [5:0] _io_rd_data_clz_T_83 = _io_rd_data_clz_T_49[31] ? 6'h1f : 6'h20; // @[Mux.scala 47:70]
-  wire [5:0] _io_rd_data_clz_T_84 = _io_rd_data_clz_T_49[30] ? 6'h1e : _io_rd_data_clz_T_83; // @[Mux.scala 47:70]
-  wire [5:0] _io_rd_data_clz_T_85 = _io_rd_data_clz_T_49[29] ? 6'h1d : _io_rd_data_clz_T_84; // @[Mux.scala 47:70]
-  wire [5:0] _io_rd_data_clz_T_86 = _io_rd_data_clz_T_49[28] ? 6'h1c : _io_rd_data_clz_T_85; // @[Mux.scala 47:70]
-  wire [5:0] _io_rd_data_clz_T_87 = _io_rd_data_clz_T_49[27] ? 6'h1b : _io_rd_data_clz_T_86; // @[Mux.scala 47:70]
-  wire [5:0] _io_rd_data_clz_T_88 = _io_rd_data_clz_T_49[26] ? 6'h1a : _io_rd_data_clz_T_87; // @[Mux.scala 47:70]
-  wire [5:0] _io_rd_data_clz_T_89 = _io_rd_data_clz_T_49[25] ? 6'h19 : _io_rd_data_clz_T_88; // @[Mux.scala 47:70]
-  wire [5:0] _io_rd_data_clz_T_90 = _io_rd_data_clz_T_49[24] ? 6'h18 : _io_rd_data_clz_T_89; // @[Mux.scala 47:70]
-  wire [5:0] _io_rd_data_clz_T_91 = _io_rd_data_clz_T_49[23] ? 6'h17 : _io_rd_data_clz_T_90; // @[Mux.scala 47:70]
-  wire [5:0] _io_rd_data_clz_T_92 = _io_rd_data_clz_T_49[22] ? 6'h16 : _io_rd_data_clz_T_91; // @[Mux.scala 47:70]
-  wire [5:0] _io_rd_data_clz_T_93 = _io_rd_data_clz_T_49[21] ? 6'h15 : _io_rd_data_clz_T_92; // @[Mux.scala 47:70]
-  wire [5:0] _io_rd_data_clz_T_94 = _io_rd_data_clz_T_49[20] ? 6'h14 : _io_rd_data_clz_T_93; // @[Mux.scala 47:70]
-  wire [5:0] _io_rd_data_clz_T_95 = _io_rd_data_clz_T_49[19] ? 6'h13 : _io_rd_data_clz_T_94; // @[Mux.scala 47:70]
-  wire [5:0] _io_rd_data_clz_T_96 = _io_rd_data_clz_T_49[18] ? 6'h12 : _io_rd_data_clz_T_95; // @[Mux.scala 47:70]
-  wire [5:0] _io_rd_data_clz_T_97 = _io_rd_data_clz_T_49[17] ? 6'h11 : _io_rd_data_clz_T_96; // @[Mux.scala 47:70]
-  wire [5:0] _io_rd_data_clz_T_98 = _io_rd_data_clz_T_49[16] ? 6'h10 : _io_rd_data_clz_T_97; // @[Mux.scala 47:70]
-  wire [5:0] _io_rd_data_clz_T_99 = _io_rd_data_clz_T_49[15] ? 6'hf : _io_rd_data_clz_T_98; // @[Mux.scala 47:70]
-  wire [5:0] _io_rd_data_clz_T_100 = _io_rd_data_clz_T_49[14] ? 6'he : _io_rd_data_clz_T_99; // @[Mux.scala 47:70]
-  wire [5:0] _io_rd_data_clz_T_101 = _io_rd_data_clz_T_49[13] ? 6'hd : _io_rd_data_clz_T_100; // @[Mux.scala 47:70]
-  wire [5:0] _io_rd_data_clz_T_102 = _io_rd_data_clz_T_49[12] ? 6'hc : _io_rd_data_clz_T_101; // @[Mux.scala 47:70]
-  wire [5:0] _io_rd_data_clz_T_103 = _io_rd_data_clz_T_49[11] ? 6'hb : _io_rd_data_clz_T_102; // @[Mux.scala 47:70]
-  wire [5:0] _io_rd_data_clz_T_104 = _io_rd_data_clz_T_49[10] ? 6'ha : _io_rd_data_clz_T_103; // @[Mux.scala 47:70]
-  wire [5:0] _io_rd_data_clz_T_105 = _io_rd_data_clz_T_49[9] ? 6'h9 : _io_rd_data_clz_T_104; // @[Mux.scala 47:70]
-  wire [5:0] _io_rd_data_clz_T_106 = _io_rd_data_clz_T_49[8] ? 6'h8 : _io_rd_data_clz_T_105; // @[Mux.scala 47:70]
-  wire [5:0] _io_rd_data_clz_T_107 = _io_rd_data_clz_T_49[7] ? 6'h7 : _io_rd_data_clz_T_106; // @[Mux.scala 47:70]
-  wire [5:0] _io_rd_data_clz_T_108 = _io_rd_data_clz_T_49[6] ? 6'h6 : _io_rd_data_clz_T_107; // @[Mux.scala 47:70]
-  wire [5:0] _io_rd_data_clz_T_109 = _io_rd_data_clz_T_49[5] ? 6'h5 : _io_rd_data_clz_T_108; // @[Mux.scala 47:70]
-  wire [5:0] _io_rd_data_clz_T_110 = _io_rd_data_clz_T_49[4] ? 6'h4 : _io_rd_data_clz_T_109; // @[Mux.scala 47:70]
-  wire [5:0] _io_rd_data_clz_T_111 = _io_rd_data_clz_T_49[3] ? 6'h3 : _io_rd_data_clz_T_110; // @[Mux.scala 47:70]
-  wire [5:0] _io_rd_data_clz_T_112 = _io_rd_data_clz_T_49[2] ? 6'h2 : _io_rd_data_clz_T_111; // @[Mux.scala 47:70]
-  wire [5:0] _io_rd_data_clz_T_113 = _io_rd_data_clz_T_49[1] ? 6'h1 : _io_rd_data_clz_T_112; // @[Mux.scala 47:70]
-  wire [5:0] io_rd_data_clz = _io_rd_data_clz_T_49[0] ? 6'h0 : _io_rd_data_clz_T_113; // @[Mux.scala 47:70]
-  wire [5:0] _io_rd_data_T_50 = io_rs1_data[31] ? io_rd_data_clo : io_rd_data_clz; // @[Library.scala 274:8]
-  wire [5:0] _io_rd_data_T_51 = op[11] ? _io_rd_data_T_50 : 6'h0; // @[Library.scala 8:8]
-  wire [62:0] _GEN_18 = {{57'd0}, _io_rd_data_T_51}; // @[Alu.scala 106:43]
-  wire [62:0] _io_rd_data_T_52 = _io_rd_data_T_47 | _GEN_18; // @[Alu.scala 106:43]
-  wire [5:0] _io_rd_data_T_169 = op[12] ? io_rd_data_clz : 6'h0; // @[Library.scala 8:8]
-  wire [62:0] _GEN_24 = {{57'd0}, _io_rd_data_T_169}; // @[Alu.scala 107:48]
-  wire [62:0] _io_rd_data_T_170 = _io_rd_data_T_52 | _GEN_24; // @[Alu.scala 107:48]
-  wire [32:0] _io_rd_data_T_172 = {1'h1,io_rs1_data}; // @[Cat.scala 31:58]
-  wire [5:0] _io_rd_data_T_206 = _io_rd_data_T_172[31] ? 6'h1f : 6'h20; // @[Mux.scala 47:70]
-  wire [5:0] _io_rd_data_T_207 = _io_rd_data_T_172[30] ? 6'h1e : _io_rd_data_T_206; // @[Mux.scala 47:70]
-  wire [5:0] _io_rd_data_T_208 = _io_rd_data_T_172[29] ? 6'h1d : _io_rd_data_T_207; // @[Mux.scala 47:70]
-  wire [5:0] _io_rd_data_T_209 = _io_rd_data_T_172[28] ? 6'h1c : _io_rd_data_T_208; // @[Mux.scala 47:70]
-  wire [5:0] _io_rd_data_T_210 = _io_rd_data_T_172[27] ? 6'h1b : _io_rd_data_T_209; // @[Mux.scala 47:70]
-  wire [5:0] _io_rd_data_T_211 = _io_rd_data_T_172[26] ? 6'h1a : _io_rd_data_T_210; // @[Mux.scala 47:70]
-  wire [5:0] _io_rd_data_T_212 = _io_rd_data_T_172[25] ? 6'h19 : _io_rd_data_T_211; // @[Mux.scala 47:70]
-  wire [5:0] _io_rd_data_T_213 = _io_rd_data_T_172[24] ? 6'h18 : _io_rd_data_T_212; // @[Mux.scala 47:70]
-  wire [5:0] _io_rd_data_T_214 = _io_rd_data_T_172[23] ? 6'h17 : _io_rd_data_T_213; // @[Mux.scala 47:70]
-  wire [5:0] _io_rd_data_T_215 = _io_rd_data_T_172[22] ? 6'h16 : _io_rd_data_T_214; // @[Mux.scala 47:70]
-  wire [5:0] _io_rd_data_T_216 = _io_rd_data_T_172[21] ? 6'h15 : _io_rd_data_T_215; // @[Mux.scala 47:70]
-  wire [5:0] _io_rd_data_T_217 = _io_rd_data_T_172[20] ? 6'h14 : _io_rd_data_T_216; // @[Mux.scala 47:70]
-  wire [5:0] _io_rd_data_T_218 = _io_rd_data_T_172[19] ? 6'h13 : _io_rd_data_T_217; // @[Mux.scala 47:70]
-  wire [5:0] _io_rd_data_T_219 = _io_rd_data_T_172[18] ? 6'h12 : _io_rd_data_T_218; // @[Mux.scala 47:70]
-  wire [5:0] _io_rd_data_T_220 = _io_rd_data_T_172[17] ? 6'h11 : _io_rd_data_T_219; // @[Mux.scala 47:70]
-  wire [5:0] _io_rd_data_T_221 = _io_rd_data_T_172[16] ? 6'h10 : _io_rd_data_T_220; // @[Mux.scala 47:70]
-  wire [5:0] _io_rd_data_T_222 = _io_rd_data_T_172[15] ? 6'hf : _io_rd_data_T_221; // @[Mux.scala 47:70]
-  wire [5:0] _io_rd_data_T_223 = _io_rd_data_T_172[14] ? 6'he : _io_rd_data_T_222; // @[Mux.scala 47:70]
-  wire [5:0] _io_rd_data_T_224 = _io_rd_data_T_172[13] ? 6'hd : _io_rd_data_T_223; // @[Mux.scala 47:70]
-  wire [5:0] _io_rd_data_T_225 = _io_rd_data_T_172[12] ? 6'hc : _io_rd_data_T_224; // @[Mux.scala 47:70]
-  wire [5:0] _io_rd_data_T_226 = _io_rd_data_T_172[11] ? 6'hb : _io_rd_data_T_225; // @[Mux.scala 47:70]
-  wire [5:0] _io_rd_data_T_227 = _io_rd_data_T_172[10] ? 6'ha : _io_rd_data_T_226; // @[Mux.scala 47:70]
-  wire [5:0] _io_rd_data_T_228 = _io_rd_data_T_172[9] ? 6'h9 : _io_rd_data_T_227; // @[Mux.scala 47:70]
-  wire [5:0] _io_rd_data_T_229 = _io_rd_data_T_172[8] ? 6'h8 : _io_rd_data_T_228; // @[Mux.scala 47:70]
-  wire [5:0] _io_rd_data_T_230 = _io_rd_data_T_172[7] ? 6'h7 : _io_rd_data_T_229; // @[Mux.scala 47:70]
-  wire [5:0] _io_rd_data_T_231 = _io_rd_data_T_172[6] ? 6'h6 : _io_rd_data_T_230; // @[Mux.scala 47:70]
-  wire [5:0] _io_rd_data_T_232 = _io_rd_data_T_172[5] ? 6'h5 : _io_rd_data_T_231; // @[Mux.scala 47:70]
-  wire [5:0] _io_rd_data_T_233 = _io_rd_data_T_172[4] ? 6'h4 : _io_rd_data_T_232; // @[Mux.scala 47:70]
-  wire [5:0] _io_rd_data_T_234 = _io_rd_data_T_172[3] ? 6'h3 : _io_rd_data_T_233; // @[Mux.scala 47:70]
-  wire [5:0] _io_rd_data_T_235 = _io_rd_data_T_172[2] ? 6'h2 : _io_rd_data_T_234; // @[Mux.scala 47:70]
-  wire [5:0] _io_rd_data_T_236 = _io_rd_data_T_172[1] ? 6'h1 : _io_rd_data_T_235; // @[Mux.scala 47:70]
-  wire [5:0] _io_rd_data_T_237 = _io_rd_data_T_172[0] ? 6'h0 : _io_rd_data_T_236; // @[Mux.scala 47:70]
-  wire [5:0] _io_rd_data_T_238 = op[13] ? _io_rd_data_T_237 : 6'h0; // @[Library.scala 8:8]
-  wire [62:0] _GEN_25 = {{57'd0}, _io_rd_data_T_238}; // @[Alu.scala 108:48]
-  wire [62:0] _io_rd_data_T_239 = _io_rd_data_T_170 | _GEN_25; // @[Alu.scala 108:48]
-  wire [1:0] _io_rd_data_T_273 = io_rs1_data[0] + io_rs1_data[1]; // @[Bitwise.scala 48:55]
-  wire [1:0] _io_rd_data_T_275 = io_rs1_data[2] + io_rs1_data[3]; // @[Bitwise.scala 48:55]
-  wire [2:0] _io_rd_data_T_277 = _io_rd_data_T_273 + _io_rd_data_T_275; // @[Bitwise.scala 48:55]
-  wire [1:0] _io_rd_data_T_279 = io_rs1_data[4] + io_rs1_data[5]; // @[Bitwise.scala 48:55]
-  wire [1:0] _io_rd_data_T_281 = io_rs1_data[6] + io_rs1_data[7]; // @[Bitwise.scala 48:55]
-  wire [2:0] _io_rd_data_T_283 = _io_rd_data_T_279 + _io_rd_data_T_281; // @[Bitwise.scala 48:55]
-  wire [3:0] _io_rd_data_T_285 = _io_rd_data_T_277 + _io_rd_data_T_283; // @[Bitwise.scala 48:55]
-  wire [1:0] _io_rd_data_T_287 = io_rs1_data[8] + io_rs1_data[9]; // @[Bitwise.scala 48:55]
-  wire [1:0] _io_rd_data_T_289 = io_rs1_data[10] + io_rs1_data[11]; // @[Bitwise.scala 48:55]
-  wire [2:0] _io_rd_data_T_291 = _io_rd_data_T_287 + _io_rd_data_T_289; // @[Bitwise.scala 48:55]
-  wire [1:0] _io_rd_data_T_293 = io_rs1_data[12] + io_rs1_data[13]; // @[Bitwise.scala 48:55]
-  wire [1:0] _io_rd_data_T_295 = io_rs1_data[14] + io_rs1_data[15]; // @[Bitwise.scala 48:55]
-  wire [2:0] _io_rd_data_T_297 = _io_rd_data_T_293 + _io_rd_data_T_295; // @[Bitwise.scala 48:55]
-  wire [3:0] _io_rd_data_T_299 = _io_rd_data_T_291 + _io_rd_data_T_297; // @[Bitwise.scala 48:55]
-  wire [4:0] _io_rd_data_T_301 = _io_rd_data_T_285 + _io_rd_data_T_299; // @[Bitwise.scala 48:55]
-  wire [1:0] _io_rd_data_T_303 = io_rs1_data[16] + io_rs1_data[17]; // @[Bitwise.scala 48:55]
-  wire [1:0] _io_rd_data_T_305 = io_rs1_data[18] + io_rs1_data[19]; // @[Bitwise.scala 48:55]
-  wire [2:0] _io_rd_data_T_307 = _io_rd_data_T_303 + _io_rd_data_T_305; // @[Bitwise.scala 48:55]
-  wire [1:0] _io_rd_data_T_309 = io_rs1_data[20] + io_rs1_data[21]; // @[Bitwise.scala 48:55]
-  wire [1:0] _io_rd_data_T_311 = io_rs1_data[22] + io_rs1_data[23]; // @[Bitwise.scala 48:55]
-  wire [2:0] _io_rd_data_T_313 = _io_rd_data_T_309 + _io_rd_data_T_311; // @[Bitwise.scala 48:55]
-  wire [3:0] _io_rd_data_T_315 = _io_rd_data_T_307 + _io_rd_data_T_313; // @[Bitwise.scala 48:55]
-  wire [1:0] _io_rd_data_T_317 = io_rs1_data[24] + io_rs1_data[25]; // @[Bitwise.scala 48:55]
-  wire [1:0] _io_rd_data_T_319 = io_rs1_data[26] + io_rs1_data[27]; // @[Bitwise.scala 48:55]
-  wire [2:0] _io_rd_data_T_321 = _io_rd_data_T_317 + _io_rd_data_T_319; // @[Bitwise.scala 48:55]
-  wire [1:0] _io_rd_data_T_323 = io_rs1_data[28] + io_rs1_data[29]; // @[Bitwise.scala 48:55]
-  wire [1:0] _io_rd_data_T_325 = io_rs1_data[30] + io_rs1_data[31]; // @[Bitwise.scala 48:55]
-  wire [2:0] _io_rd_data_T_327 = _io_rd_data_T_323 + _io_rd_data_T_325; // @[Bitwise.scala 48:55]
-  wire [3:0] _io_rd_data_T_329 = _io_rd_data_T_321 + _io_rd_data_T_327; // @[Bitwise.scala 48:55]
-  wire [4:0] _io_rd_data_T_331 = _io_rd_data_T_315 + _io_rd_data_T_329; // @[Bitwise.scala 48:55]
-  wire [5:0] _io_rd_data_T_333 = _io_rd_data_T_301 + _io_rd_data_T_331; // @[Bitwise.scala 48:55]
-  wire [5:0] _io_rd_data_T_335 = op[14] ? _io_rd_data_T_333 : 6'h0; // @[Library.scala 8:8]
-  wire [62:0] _GEN_26 = {{57'd0}, _io_rd_data_T_335}; // @[Alu.scala 109:48]
-  wire [62:0] _io_rd_data_T_336 = _io_rd_data_T_239 | _GEN_26; // @[Alu.scala 109:48]
-  wire [31:0] _io_rd_data_T_341 = _io_rd_data_T_12 ? io_rs1_data : io_rs2_data; // @[Alu.scala 111:41]
-  wire [31:0] _io_rd_data_T_342 = op[15] ? _io_rd_data_T_341 : 32'h0; // @[Library.scala 8:8]
-  wire [62:0] _GEN_27 = {{31'd0}, _io_rd_data_T_342}; // @[Alu.scala 110:53]
-  wire [62:0] _io_rd_data_T_343 = _io_rd_data_T_336 | _GEN_27; // @[Alu.scala 110:53]
-  wire [31:0] _io_rd_data_T_348 = $signed(io_rs1_data) > $signed(io_rs2_data) ? io_rs1_data : io_rs2_data; // @[Alu.scala 112:41]
-  wire [31:0] _io_rd_data_T_349 = op[17] ? _io_rd_data_T_348 : 32'h0; // @[Library.scala 8:8]
-  wire [62:0] _GEN_28 = {{31'd0}, _io_rd_data_T_349}; // @[Alu.scala 111:78]
-  wire [62:0] _io_rd_data_T_350 = _io_rd_data_T_343 | _GEN_28; // @[Alu.scala 111:78]
-  wire [31:0] _io_rd_data_T_353 = _io_rd_data_T_16 ? io_rs1_data : io_rs2_data; // @[Alu.scala 113:41]
-  wire [31:0] _io_rd_data_T_354 = op[16] ? _io_rd_data_T_353 : 32'h0; // @[Library.scala 8:8]
-  wire [62:0] _GEN_29 = {{31'd0}, _io_rd_data_T_354}; // @[Alu.scala 112:78]
-  wire [62:0] _io_rd_data_T_355 = _io_rd_data_T_350 | _GEN_29; // @[Alu.scala 112:78]
-  wire [31:0] _io_rd_data_T_358 = io_rs1_data > io_rs2_data ? io_rs1_data : io_rs2_data; // @[Alu.scala 114:41]
-  wire [31:0] _io_rd_data_T_359 = op[18] ? _io_rd_data_T_358 : 32'h0; // @[Library.scala 8:8]
-  wire [62:0] _GEN_30 = {{31'd0}, _io_rd_data_T_359}; // @[Alu.scala 113:64]
-  wire [62:0] _io_rd_data_T_360 = _io_rd_data_T_355 | _GEN_30; // @[Alu.scala 113:64]
-  wire  _T_7 = ~reset; // @[Alu.scala 117:9]
-  assign io_rd_valid = valid; // @[Alu.scala 94:15]
-  assign io_rd_addr = addr; // @[Alu.scala 95:15]
-  assign io_rd_data = _io_rd_data_T_360[31:0]; // @[Alu.scala 96:15]
+  wire [62:0] _GEN_7 = {{31'd0}, _io_rd_data_T_46}; // @[Alu.scala 104:68]
+  wire [62:0] _io_rd_data_T_47 = _io_rd_data_T_44 | _GEN_7; // @[Alu.scala 104:68]
+  wire [31:0] _GEN_8 = {{16'd0}, io_rs1_data[31:16]}; // @[Bitwise.scala 105:31]
+  wire [31:0] _io_rd_data_T_52 = _GEN_8 & 32'hffff; // @[Bitwise.scala 105:31]
+  wire [31:0] _io_rd_data_T_54 = {io_rs1_data[15:0], 16'h0}; // @[Bitwise.scala 105:70]
+  wire [31:0] _io_rd_data_T_56 = _io_rd_data_T_54 & 32'hffff0000; // @[Bitwise.scala 105:80]
+  wire [31:0] _io_rd_data_T_57 = _io_rd_data_T_52 | _io_rd_data_T_56; // @[Bitwise.scala 105:39]
+  wire [31:0] _GEN_9 = {{8'd0}, _io_rd_data_T_57[31:8]}; // @[Bitwise.scala 105:31]
+  wire [31:0] _io_rd_data_T_62 = _GEN_9 & 32'hff00ff; // @[Bitwise.scala 105:31]
+  wire [31:0] _io_rd_data_T_64 = {_io_rd_data_T_57[23:0], 8'h0}; // @[Bitwise.scala 105:70]
+  wire [31:0] _io_rd_data_T_66 = _io_rd_data_T_64 & 32'hff00ff00; // @[Bitwise.scala 105:80]
+  wire [31:0] _io_rd_data_T_67 = _io_rd_data_T_62 | _io_rd_data_T_66; // @[Bitwise.scala 105:39]
+  wire [31:0] _GEN_10 = {{4'd0}, _io_rd_data_T_67[31:4]}; // @[Bitwise.scala 105:31]
+  wire [31:0] _io_rd_data_T_72 = _GEN_10 & 32'hf0f0f0f; // @[Bitwise.scala 105:31]
+  wire [31:0] _io_rd_data_T_74 = {_io_rd_data_T_67[27:0], 4'h0}; // @[Bitwise.scala 105:70]
+  wire [31:0] _io_rd_data_T_76 = _io_rd_data_T_74 & 32'hf0f0f0f0; // @[Bitwise.scala 105:80]
+  wire [31:0] _io_rd_data_T_77 = _io_rd_data_T_72 | _io_rd_data_T_76; // @[Bitwise.scala 105:39]
+  wire [31:0] _GEN_11 = {{2'd0}, _io_rd_data_T_77[31:2]}; // @[Bitwise.scala 105:31]
+  wire [31:0] _io_rd_data_T_82 = _GEN_11 & 32'h33333333; // @[Bitwise.scala 105:31]
+  wire [31:0] _io_rd_data_T_84 = {_io_rd_data_T_77[29:0], 2'h0}; // @[Bitwise.scala 105:70]
+  wire [31:0] _io_rd_data_T_86 = _io_rd_data_T_84 & 32'hcccccccc; // @[Bitwise.scala 105:80]
+  wire [31:0] _io_rd_data_T_87 = _io_rd_data_T_82 | _io_rd_data_T_86; // @[Bitwise.scala 105:39]
+  wire [31:0] _GEN_12 = {{1'd0}, _io_rd_data_T_87[31:1]}; // @[Bitwise.scala 105:31]
+  wire [31:0] _io_rd_data_T_92 = _GEN_12 & 32'h55555555; // @[Bitwise.scala 105:31]
+  wire [31:0] _io_rd_data_T_94 = {_io_rd_data_T_87[30:0], 1'h0}; // @[Bitwise.scala 105:70]
+  wire [31:0] _io_rd_data_T_96 = _io_rd_data_T_94 & 32'haaaaaaaa; // @[Bitwise.scala 105:80]
+  wire [31:0] _io_rd_data_T_97 = _io_rd_data_T_92 | _io_rd_data_T_96; // @[Bitwise.scala 105:39]
+  wire [32:0] _io_rd_data_T_98 = {1'h1,_io_rd_data_T_97}; // @[Cat.scala 31:58]
+  wire [5:0] _io_rd_data_T_132 = _io_rd_data_T_98[31] ? 6'h1f : 6'h20; // @[Mux.scala 47:70]
+  wire [5:0] _io_rd_data_T_133 = _io_rd_data_T_98[30] ? 6'h1e : _io_rd_data_T_132; // @[Mux.scala 47:70]
+  wire [5:0] _io_rd_data_T_134 = _io_rd_data_T_98[29] ? 6'h1d : _io_rd_data_T_133; // @[Mux.scala 47:70]
+  wire [5:0] _io_rd_data_T_135 = _io_rd_data_T_98[28] ? 6'h1c : _io_rd_data_T_134; // @[Mux.scala 47:70]
+  wire [5:0] _io_rd_data_T_136 = _io_rd_data_T_98[27] ? 6'h1b : _io_rd_data_T_135; // @[Mux.scala 47:70]
+  wire [5:0] _io_rd_data_T_137 = _io_rd_data_T_98[26] ? 6'h1a : _io_rd_data_T_136; // @[Mux.scala 47:70]
+  wire [5:0] _io_rd_data_T_138 = _io_rd_data_T_98[25] ? 6'h19 : _io_rd_data_T_137; // @[Mux.scala 47:70]
+  wire [5:0] _io_rd_data_T_139 = _io_rd_data_T_98[24] ? 6'h18 : _io_rd_data_T_138; // @[Mux.scala 47:70]
+  wire [5:0] _io_rd_data_T_140 = _io_rd_data_T_98[23] ? 6'h17 : _io_rd_data_T_139; // @[Mux.scala 47:70]
+  wire [5:0] _io_rd_data_T_141 = _io_rd_data_T_98[22] ? 6'h16 : _io_rd_data_T_140; // @[Mux.scala 47:70]
+  wire [5:0] _io_rd_data_T_142 = _io_rd_data_T_98[21] ? 6'h15 : _io_rd_data_T_141; // @[Mux.scala 47:70]
+  wire [5:0] _io_rd_data_T_143 = _io_rd_data_T_98[20] ? 6'h14 : _io_rd_data_T_142; // @[Mux.scala 47:70]
+  wire [5:0] _io_rd_data_T_144 = _io_rd_data_T_98[19] ? 6'h13 : _io_rd_data_T_143; // @[Mux.scala 47:70]
+  wire [5:0] _io_rd_data_T_145 = _io_rd_data_T_98[18] ? 6'h12 : _io_rd_data_T_144; // @[Mux.scala 47:70]
+  wire [5:0] _io_rd_data_T_146 = _io_rd_data_T_98[17] ? 6'h11 : _io_rd_data_T_145; // @[Mux.scala 47:70]
+  wire [5:0] _io_rd_data_T_147 = _io_rd_data_T_98[16] ? 6'h10 : _io_rd_data_T_146; // @[Mux.scala 47:70]
+  wire [5:0] _io_rd_data_T_148 = _io_rd_data_T_98[15] ? 6'hf : _io_rd_data_T_147; // @[Mux.scala 47:70]
+  wire [5:0] _io_rd_data_T_149 = _io_rd_data_T_98[14] ? 6'he : _io_rd_data_T_148; // @[Mux.scala 47:70]
+  wire [5:0] _io_rd_data_T_150 = _io_rd_data_T_98[13] ? 6'hd : _io_rd_data_T_149; // @[Mux.scala 47:70]
+  wire [5:0] _io_rd_data_T_151 = _io_rd_data_T_98[12] ? 6'hc : _io_rd_data_T_150; // @[Mux.scala 47:70]
+  wire [5:0] _io_rd_data_T_152 = _io_rd_data_T_98[11] ? 6'hb : _io_rd_data_T_151; // @[Mux.scala 47:70]
+  wire [5:0] _io_rd_data_T_153 = _io_rd_data_T_98[10] ? 6'ha : _io_rd_data_T_152; // @[Mux.scala 47:70]
+  wire [5:0] _io_rd_data_T_154 = _io_rd_data_T_98[9] ? 6'h9 : _io_rd_data_T_153; // @[Mux.scala 47:70]
+  wire [5:0] _io_rd_data_T_155 = _io_rd_data_T_98[8] ? 6'h8 : _io_rd_data_T_154; // @[Mux.scala 47:70]
+  wire [5:0] _io_rd_data_T_156 = _io_rd_data_T_98[7] ? 6'h7 : _io_rd_data_T_155; // @[Mux.scala 47:70]
+  wire [5:0] _io_rd_data_T_157 = _io_rd_data_T_98[6] ? 6'h6 : _io_rd_data_T_156; // @[Mux.scala 47:70]
+  wire [5:0] _io_rd_data_T_158 = _io_rd_data_T_98[5] ? 6'h5 : _io_rd_data_T_157; // @[Mux.scala 47:70]
+  wire [5:0] _io_rd_data_T_159 = _io_rd_data_T_98[4] ? 6'h4 : _io_rd_data_T_158; // @[Mux.scala 47:70]
+  wire [5:0] _io_rd_data_T_160 = _io_rd_data_T_98[3] ? 6'h3 : _io_rd_data_T_159; // @[Mux.scala 47:70]
+  wire [5:0] _io_rd_data_T_161 = _io_rd_data_T_98[2] ? 6'h2 : _io_rd_data_T_160; // @[Mux.scala 47:70]
+  wire [5:0] _io_rd_data_T_162 = _io_rd_data_T_98[1] ? 6'h1 : _io_rd_data_T_161; // @[Mux.scala 47:70]
+  wire [5:0] _io_rd_data_T_163 = _io_rd_data_T_98[0] ? 6'h0 : _io_rd_data_T_162; // @[Mux.scala 47:70]
+  wire [5:0] _io_rd_data_T_164 = op[11] ? _io_rd_data_T_163 : 6'h0; // @[Library.scala 8:8]
+  wire [62:0] _GEN_13 = {{57'd0}, _io_rd_data_T_164}; // @[Alu.scala 105:43]
+  wire [62:0] _io_rd_data_T_165 = _io_rd_data_T_47 | _GEN_13; // @[Alu.scala 105:43]
+  wire [32:0] _io_rd_data_T_167 = {1'h1,io_rs1_data}; // @[Cat.scala 31:58]
+  wire [5:0] _io_rd_data_T_201 = _io_rd_data_T_167[31] ? 6'h1f : 6'h20; // @[Mux.scala 47:70]
+  wire [5:0] _io_rd_data_T_202 = _io_rd_data_T_167[30] ? 6'h1e : _io_rd_data_T_201; // @[Mux.scala 47:70]
+  wire [5:0] _io_rd_data_T_203 = _io_rd_data_T_167[29] ? 6'h1d : _io_rd_data_T_202; // @[Mux.scala 47:70]
+  wire [5:0] _io_rd_data_T_204 = _io_rd_data_T_167[28] ? 6'h1c : _io_rd_data_T_203; // @[Mux.scala 47:70]
+  wire [5:0] _io_rd_data_T_205 = _io_rd_data_T_167[27] ? 6'h1b : _io_rd_data_T_204; // @[Mux.scala 47:70]
+  wire [5:0] _io_rd_data_T_206 = _io_rd_data_T_167[26] ? 6'h1a : _io_rd_data_T_205; // @[Mux.scala 47:70]
+  wire [5:0] _io_rd_data_T_207 = _io_rd_data_T_167[25] ? 6'h19 : _io_rd_data_T_206; // @[Mux.scala 47:70]
+  wire [5:0] _io_rd_data_T_208 = _io_rd_data_T_167[24] ? 6'h18 : _io_rd_data_T_207; // @[Mux.scala 47:70]
+  wire [5:0] _io_rd_data_T_209 = _io_rd_data_T_167[23] ? 6'h17 : _io_rd_data_T_208; // @[Mux.scala 47:70]
+  wire [5:0] _io_rd_data_T_210 = _io_rd_data_T_167[22] ? 6'h16 : _io_rd_data_T_209; // @[Mux.scala 47:70]
+  wire [5:0] _io_rd_data_T_211 = _io_rd_data_T_167[21] ? 6'h15 : _io_rd_data_T_210; // @[Mux.scala 47:70]
+  wire [5:0] _io_rd_data_T_212 = _io_rd_data_T_167[20] ? 6'h14 : _io_rd_data_T_211; // @[Mux.scala 47:70]
+  wire [5:0] _io_rd_data_T_213 = _io_rd_data_T_167[19] ? 6'h13 : _io_rd_data_T_212; // @[Mux.scala 47:70]
+  wire [5:0] _io_rd_data_T_214 = _io_rd_data_T_167[18] ? 6'h12 : _io_rd_data_T_213; // @[Mux.scala 47:70]
+  wire [5:0] _io_rd_data_T_215 = _io_rd_data_T_167[17] ? 6'h11 : _io_rd_data_T_214; // @[Mux.scala 47:70]
+  wire [5:0] _io_rd_data_T_216 = _io_rd_data_T_167[16] ? 6'h10 : _io_rd_data_T_215; // @[Mux.scala 47:70]
+  wire [5:0] _io_rd_data_T_217 = _io_rd_data_T_167[15] ? 6'hf : _io_rd_data_T_216; // @[Mux.scala 47:70]
+  wire [5:0] _io_rd_data_T_218 = _io_rd_data_T_167[14] ? 6'he : _io_rd_data_T_217; // @[Mux.scala 47:70]
+  wire [5:0] _io_rd_data_T_219 = _io_rd_data_T_167[13] ? 6'hd : _io_rd_data_T_218; // @[Mux.scala 47:70]
+  wire [5:0] _io_rd_data_T_220 = _io_rd_data_T_167[12] ? 6'hc : _io_rd_data_T_219; // @[Mux.scala 47:70]
+  wire [5:0] _io_rd_data_T_221 = _io_rd_data_T_167[11] ? 6'hb : _io_rd_data_T_220; // @[Mux.scala 47:70]
+  wire [5:0] _io_rd_data_T_222 = _io_rd_data_T_167[10] ? 6'ha : _io_rd_data_T_221; // @[Mux.scala 47:70]
+  wire [5:0] _io_rd_data_T_223 = _io_rd_data_T_167[9] ? 6'h9 : _io_rd_data_T_222; // @[Mux.scala 47:70]
+  wire [5:0] _io_rd_data_T_224 = _io_rd_data_T_167[8] ? 6'h8 : _io_rd_data_T_223; // @[Mux.scala 47:70]
+  wire [5:0] _io_rd_data_T_225 = _io_rd_data_T_167[7] ? 6'h7 : _io_rd_data_T_224; // @[Mux.scala 47:70]
+  wire [5:0] _io_rd_data_T_226 = _io_rd_data_T_167[6] ? 6'h6 : _io_rd_data_T_225; // @[Mux.scala 47:70]
+  wire [5:0] _io_rd_data_T_227 = _io_rd_data_T_167[5] ? 6'h5 : _io_rd_data_T_226; // @[Mux.scala 47:70]
+  wire [5:0] _io_rd_data_T_228 = _io_rd_data_T_167[4] ? 6'h4 : _io_rd_data_T_227; // @[Mux.scala 47:70]
+  wire [5:0] _io_rd_data_T_229 = _io_rd_data_T_167[3] ? 6'h3 : _io_rd_data_T_228; // @[Mux.scala 47:70]
+  wire [5:0] _io_rd_data_T_230 = _io_rd_data_T_167[2] ? 6'h2 : _io_rd_data_T_229; // @[Mux.scala 47:70]
+  wire [5:0] _io_rd_data_T_231 = _io_rd_data_T_167[1] ? 6'h1 : _io_rd_data_T_230; // @[Mux.scala 47:70]
+  wire [5:0] _io_rd_data_T_232 = _io_rd_data_T_167[0] ? 6'h0 : _io_rd_data_T_231; // @[Mux.scala 47:70]
+  wire [5:0] _io_rd_data_T_233 = op[12] ? _io_rd_data_T_232 : 6'h0; // @[Library.scala 8:8]
+  wire [62:0] _GEN_14 = {{57'd0}, _io_rd_data_T_233}; // @[Alu.scala 106:48]
+  wire [62:0] _io_rd_data_T_234 = _io_rd_data_T_165 | _GEN_14; // @[Alu.scala 106:48]
+  wire [1:0] _io_rd_data_T_268 = io_rs1_data[0] + io_rs1_data[1]; // @[Bitwise.scala 48:55]
+  wire [1:0] _io_rd_data_T_270 = io_rs1_data[2] + io_rs1_data[3]; // @[Bitwise.scala 48:55]
+  wire [2:0] _io_rd_data_T_272 = _io_rd_data_T_268 + _io_rd_data_T_270; // @[Bitwise.scala 48:55]
+  wire [1:0] _io_rd_data_T_274 = io_rs1_data[4] + io_rs1_data[5]; // @[Bitwise.scala 48:55]
+  wire [1:0] _io_rd_data_T_276 = io_rs1_data[6] + io_rs1_data[7]; // @[Bitwise.scala 48:55]
+  wire [2:0] _io_rd_data_T_278 = _io_rd_data_T_274 + _io_rd_data_T_276; // @[Bitwise.scala 48:55]
+  wire [3:0] _io_rd_data_T_280 = _io_rd_data_T_272 + _io_rd_data_T_278; // @[Bitwise.scala 48:55]
+  wire [1:0] _io_rd_data_T_282 = io_rs1_data[8] + io_rs1_data[9]; // @[Bitwise.scala 48:55]
+  wire [1:0] _io_rd_data_T_284 = io_rs1_data[10] + io_rs1_data[11]; // @[Bitwise.scala 48:55]
+  wire [2:0] _io_rd_data_T_286 = _io_rd_data_T_282 + _io_rd_data_T_284; // @[Bitwise.scala 48:55]
+  wire [1:0] _io_rd_data_T_288 = io_rs1_data[12] + io_rs1_data[13]; // @[Bitwise.scala 48:55]
+  wire [1:0] _io_rd_data_T_290 = io_rs1_data[14] + io_rs1_data[15]; // @[Bitwise.scala 48:55]
+  wire [2:0] _io_rd_data_T_292 = _io_rd_data_T_288 + _io_rd_data_T_290; // @[Bitwise.scala 48:55]
+  wire [3:0] _io_rd_data_T_294 = _io_rd_data_T_286 + _io_rd_data_T_292; // @[Bitwise.scala 48:55]
+  wire [4:0] _io_rd_data_T_296 = _io_rd_data_T_280 + _io_rd_data_T_294; // @[Bitwise.scala 48:55]
+  wire [1:0] _io_rd_data_T_298 = io_rs1_data[16] + io_rs1_data[17]; // @[Bitwise.scala 48:55]
+  wire [1:0] _io_rd_data_T_300 = io_rs1_data[18] + io_rs1_data[19]; // @[Bitwise.scala 48:55]
+  wire [2:0] _io_rd_data_T_302 = _io_rd_data_T_298 + _io_rd_data_T_300; // @[Bitwise.scala 48:55]
+  wire [1:0] _io_rd_data_T_304 = io_rs1_data[20] + io_rs1_data[21]; // @[Bitwise.scala 48:55]
+  wire [1:0] _io_rd_data_T_306 = io_rs1_data[22] + io_rs1_data[23]; // @[Bitwise.scala 48:55]
+  wire [2:0] _io_rd_data_T_308 = _io_rd_data_T_304 + _io_rd_data_T_306; // @[Bitwise.scala 48:55]
+  wire [3:0] _io_rd_data_T_310 = _io_rd_data_T_302 + _io_rd_data_T_308; // @[Bitwise.scala 48:55]
+  wire [1:0] _io_rd_data_T_312 = io_rs1_data[24] + io_rs1_data[25]; // @[Bitwise.scala 48:55]
+  wire [1:0] _io_rd_data_T_314 = io_rs1_data[26] + io_rs1_data[27]; // @[Bitwise.scala 48:55]
+  wire [2:0] _io_rd_data_T_316 = _io_rd_data_T_312 + _io_rd_data_T_314; // @[Bitwise.scala 48:55]
+  wire [1:0] _io_rd_data_T_318 = io_rs1_data[28] + io_rs1_data[29]; // @[Bitwise.scala 48:55]
+  wire [1:0] _io_rd_data_T_320 = io_rs1_data[30] + io_rs1_data[31]; // @[Bitwise.scala 48:55]
+  wire [2:0] _io_rd_data_T_322 = _io_rd_data_T_318 + _io_rd_data_T_320; // @[Bitwise.scala 48:55]
+  wire [3:0] _io_rd_data_T_324 = _io_rd_data_T_316 + _io_rd_data_T_322; // @[Bitwise.scala 48:55]
+  wire [4:0] _io_rd_data_T_326 = _io_rd_data_T_310 + _io_rd_data_T_324; // @[Bitwise.scala 48:55]
+  wire [5:0] _io_rd_data_T_328 = _io_rd_data_T_296 + _io_rd_data_T_326; // @[Bitwise.scala 48:55]
+  wire [5:0] _io_rd_data_T_330 = op[13] ? _io_rd_data_T_328 : 6'h0; // @[Library.scala 8:8]
+  wire [62:0] _GEN_15 = {{57'd0}, _io_rd_data_T_330}; // @[Alu.scala 107:48]
+  wire [62:0] _io_rd_data_T_331 = _io_rd_data_T_234 | _GEN_15; // @[Alu.scala 107:48]
+  wire [31:0] _io_rd_data_T_336 = _io_rd_data_T_12 ? io_rs1_data : io_rs2_data; // @[Alu.scala 109:41]
+  wire [31:0] _io_rd_data_T_337 = op[14] ? _io_rd_data_T_336 : 32'h0; // @[Library.scala 8:8]
+  wire [62:0] _GEN_16 = {{31'd0}, _io_rd_data_T_337}; // @[Alu.scala 108:53]
+  wire [62:0] _io_rd_data_T_338 = _io_rd_data_T_331 | _GEN_16; // @[Alu.scala 108:53]
+  wire [31:0] _io_rd_data_T_343 = $signed(io_rs1_data) > $signed(io_rs2_data) ? io_rs1_data : io_rs2_data; // @[Alu.scala 110:41]
+  wire [31:0] _io_rd_data_T_344 = op[16] ? _io_rd_data_T_343 : 32'h0; // @[Library.scala 8:8]
+  wire [62:0] _GEN_17 = {{31'd0}, _io_rd_data_T_344}; // @[Alu.scala 109:78]
+  wire [62:0] _io_rd_data_T_345 = _io_rd_data_T_338 | _GEN_17; // @[Alu.scala 109:78]
+  wire [31:0] _io_rd_data_T_348 = _io_rd_data_T_16 ? io_rs1_data : io_rs2_data; // @[Alu.scala 111:41]
+  wire [31:0] _io_rd_data_T_349 = op[15] ? _io_rd_data_T_348 : 32'h0; // @[Library.scala 8:8]
+  wire [62:0] _GEN_18 = {{31'd0}, _io_rd_data_T_349}; // @[Alu.scala 110:78]
+  wire [62:0] _io_rd_data_T_350 = _io_rd_data_T_345 | _GEN_18; // @[Alu.scala 110:78]
+  wire [31:0] _io_rd_data_T_353 = io_rs1_data > io_rs2_data ? io_rs1_data : io_rs2_data; // @[Alu.scala 112:41]
+  wire [31:0] _io_rd_data_T_354 = op[17] ? _io_rd_data_T_353 : 32'h0; // @[Library.scala 8:8]
+  wire [62:0] _GEN_19 = {{31'd0}, _io_rd_data_T_354}; // @[Alu.scala 111:64]
+  wire [62:0] _io_rd_data_T_355 = _io_rd_data_T_350 | _GEN_19; // @[Alu.scala 111:64]
+  wire  _T_7 = ~reset; // @[Alu.scala 115:9]
+  assign io_rd_valid = valid; // @[Alu.scala 93:15]
+  assign io_rd_addr = addr; // @[Alu.scala 94:15]
+  assign io_rd_data = _io_rd_data_T_355[31:0]; // @[Alu.scala 95:15]
   always @(posedge clock) begin
-    if (io_req_valid) begin // @[Alu.scala 64:23]
-      addr <= io_req_addr; // @[Alu.scala 65:10]
+    if (io_req_valid) begin // @[Alu.scala 63:23]
+      addr <= io_req_addr; // @[Alu.scala 64:10]
     end
     `ifndef SYNTHESIS
     `ifdef STOP_COND
       if (`STOP_COND) begin
     `endif
         if (~reset & ~(~(valid & ~io_rs1_valid & ~op[10]))) begin
-          $fatal; // @[Alu.scala 117:9]
+          $fatal; // @[Alu.scala 115:9]
         end
     `ifdef STOP_COND
       end
@@ -14004,7 +12785,7 @@
     `endif
         if (~reset & ~(~(valid & ~io_rs1_valid & ~op[10]))) begin
           $fwrite(32'h80000002,
-            "Assertion failed\n    at Alu.scala:117 assert(!(valid && !io.rs1.valid && !op(alu.LUI)))\n"); // @[Alu.scala 117:9]
+            "Assertion failed\n    at Alu.scala:115 assert(!(valid && !io.rs1.valid && !op(alu.LUI)))\n"); // @[Alu.scala 115:9]
         end
     `ifdef PRINTF_COND
       end
@@ -14015,7 +12796,7 @@
       if (`STOP_COND) begin
     `endif
         if (_T_7 & ~(~(valid & ~io_rs2_valid))) begin
-          $fatal; // @[Alu.scala 118:9]
+          $fatal; // @[Alu.scala 116:9]
         end
     `ifdef STOP_COND
       end
@@ -14026,7 +12807,7 @@
       if (`PRINTF_COND) begin
     `endif
         if (_T_7 & ~(~(valid & ~io_rs2_valid))) begin
-          $fwrite(32'h80000002,"Assertion failed\n    at Alu.scala:118 assert(!(valid && !io.rs2.valid))\n"); // @[Alu.scala 118:9]
+          $fwrite(32'h80000002,"Assertion failed\n    at Alu.scala:116 assert(!(valid && !io.rs2.valid))\n"); // @[Alu.scala 116:9]
         end
     `ifdef PRINTF_COND
       end
@@ -14034,16 +12815,16 @@
     `endif // SYNTHESIS
   end
   always @(posedge clock or posedge reset) begin
-    if (reset) begin // @[Alu.scala 55:22]
-      valid <= 1'h0; // @[Alu.scala 55:22]
+    if (reset) begin // @[Alu.scala 54:22]
+      valid <= 1'h0; // @[Alu.scala 54:22]
     end else begin
-      valid <= io_req_valid; // @[Alu.scala 60:9]
+      valid <= io_req_valid; // @[Alu.scala 59:9]
     end
   end
   always @(posedge clock or posedge reset) begin
-    if (reset) begin // @[Alu.scala 64:23]
-      op <= 19'h0; // @[Alu.scala 66:8]
-    end else if (io_req_valid) begin // @[Alu.scala 57:19]
+    if (reset) begin // @[Alu.scala 63:23]
+      op <= 18'h0; // @[Alu.scala 65:8]
+    end else if (io_req_valid) begin // @[Alu.scala 56:19]
       op <= io_req_op;
     end
   end
@@ -14088,13 +12869,13 @@
   _RAND_1 = {1{`RANDOM}};
   addr = _RAND_1[4:0];
   _RAND_2 = {1{`RANDOM}};
-  op = _RAND_2[18:0];
+  op = _RAND_2[17:0];
 `endif // RANDOMIZE_REG_INIT
   if (reset) begin
     valid = 1'h0;
   end
   if (reset) begin
-    op = 19'h0;
+    op = 18'h0;
   end
   `endif // RANDOMIZE
 end // initial
@@ -14980,7 +13761,6 @@
   input  [5:0]  io_in_bits_size,
   input         io_in_bits_write,
   input         io_in_bits_sext,
-  input         io_in_bits_fload,
   input         io_in_bits_iload,
   input         io_in_bits_fencei,
   input         io_in_bits_flushat,
@@ -14997,7 +13777,6 @@
   output [5:0]  io_out_bits_size,
   output        io_out_bits_write,
   output        io_out_bits_sext,
-  output        io_out_bits_fload,
   output        io_out_bits_iload,
   output        io_out_bits_fencei,
   output        io_out_bits_flushat,
@@ -15023,7 +13802,6 @@
   reg [31:0] _RAND_13;
   reg [31:0] _RAND_14;
   reg [31:0] _RAND_15;
-  reg [31:0] _RAND_16;
 `endif // RANDOMIZE_REG_INIT
   reg  ipos; // @[Slice.scala 24:21]
   reg  opos; // @[Slice.scala 25:21]
@@ -15034,7 +13812,6 @@
   reg [5:0] mem_0_size; // @[Slice.scala 27:16]
   reg  mem_0_write; // @[Slice.scala 27:16]
   reg  mem_0_sext; // @[Slice.scala 27:16]
-  reg  mem_0_fload; // @[Slice.scala 27:16]
   reg  mem_0_iload; // @[Slice.scala 27:16]
   reg  mem_0_fencei; // @[Slice.scala 27:16]
   reg  mem_0_flushat; // @[Slice.scala 27:16]
@@ -15054,7 +13831,6 @@
   assign io_out_bits_size = mem_0_size; // @[Slice.scala 89:18]
   assign io_out_bits_write = mem_0_write; // @[Slice.scala 89:18]
   assign io_out_bits_sext = mem_0_sext; // @[Slice.scala 89:18]
-  assign io_out_bits_fload = mem_0_fload; // @[Slice.scala 89:18]
   assign io_out_bits_iload = mem_0_iload; // @[Slice.scala 89:18]
   assign io_out_bits_fencei = mem_0_fencei; // @[Slice.scala 89:18]
   assign io_out_bits_flushat = mem_0_flushat; // @[Slice.scala 89:18]
@@ -15085,9 +13861,6 @@
       mem_0_sext <= io_in_bits_sext; // @[Slice.scala 80:14]
     end
     if (ivalid) begin // @[Slice.scala 79:19]
-      mem_0_fload <= io_in_bits_fload; // @[Slice.scala 80:14]
-    end
-    if (ivalid) begin // @[Slice.scala 79:19]
       mem_0_iload <= io_in_bits_iload; // @[Slice.scala 80:14]
     end
     if (ivalid) begin // @[Slice.scala 79:19]
@@ -15178,21 +13951,19 @@
   _RAND_8 = {1{`RANDOM}};
   mem_0_sext = _RAND_8[0:0];
   _RAND_9 = {1{`RANDOM}};
-  mem_0_fload = _RAND_9[0:0];
+  mem_0_iload = _RAND_9[0:0];
   _RAND_10 = {1{`RANDOM}};
-  mem_0_iload = _RAND_10[0:0];
+  mem_0_fencei = _RAND_10[0:0];
   _RAND_11 = {1{`RANDOM}};
-  mem_0_fencei = _RAND_11[0:0];
+  mem_0_flushat = _RAND_11[0:0];
   _RAND_12 = {1{`RANDOM}};
-  mem_0_flushat = _RAND_12[0:0];
+  mem_0_flushall = _RAND_12[0:0];
   _RAND_13 = {1{`RANDOM}};
-  mem_0_flushall = _RAND_13[0:0];
+  mem_0_sldst = _RAND_13[0:0];
   _RAND_14 = {1{`RANDOM}};
-  mem_0_sldst = _RAND_14[0:0];
+  mem_0_vldst = _RAND_14[0:0];
   _RAND_15 = {1{`RANDOM}};
-  mem_0_vldst = _RAND_15[0:0];
-  _RAND_16 = {1{`RANDOM}};
-  mem_0_suncd = _RAND_16[0:0];
+  mem_0_suncd = _RAND_15[0:0];
 `endif // RANDOMIZE_REG_INIT
   if (reset) begin
     ipos = 1'h0;
@@ -15220,7 +13991,6 @@
   input  [5:0]  io_in_bits_0_bits_size,
   input         io_in_bits_0_bits_write,
   input         io_in_bits_0_bits_sext,
-  input         io_in_bits_0_bits_fload,
   input         io_in_bits_0_bits_iload,
   input         io_in_bits_0_bits_fencei,
   input         io_in_bits_0_bits_flushat,
@@ -15236,7 +14006,6 @@
   input  [5:0]  io_in_bits_1_bits_size,
   input         io_in_bits_1_bits_write,
   input         io_in_bits_1_bits_sext,
-  input         io_in_bits_1_bits_fload,
   input         io_in_bits_1_bits_iload,
   input         io_in_bits_1_bits_fencei,
   input         io_in_bits_1_bits_flushat,
@@ -15252,7 +14021,6 @@
   input  [5:0]  io_in_bits_2_bits_size,
   input         io_in_bits_2_bits_write,
   input         io_in_bits_2_bits_sext,
-  input         io_in_bits_2_bits_fload,
   input         io_in_bits_2_bits_iload,
   input         io_in_bits_2_bits_fencei,
   input         io_in_bits_2_bits_flushat,
@@ -15268,7 +14036,6 @@
   input  [5:0]  io_in_bits_3_bits_size,
   input         io_in_bits_3_bits_write,
   input         io_in_bits_3_bits_sext,
-  input         io_in_bits_3_bits_fload,
   input         io_in_bits_3_bits_iload,
   input         io_in_bits_3_bits_fencei,
   input         io_in_bits_3_bits_flushat,
@@ -15285,7 +14052,6 @@
   output [5:0]  io_out_bits_size,
   output        io_out_bits_write,
   output        io_out_bits_sext,
-  output        io_out_bits_fload,
   output        io_out_bits_iload,
   output        io_out_bits_fencei,
   output        io_out_bits_flushat,
@@ -15310,7 +14076,6 @@
   reg [31:0] _RAND_23;
   reg [31:0] _RAND_25;
   reg [31:0] _RAND_27;
-  reg [31:0] _RAND_29;
 `endif // RANDOMIZE_GARBAGE_ASSIGN
 `ifdef RANDOMIZE_MEM_INIT
   reg [31:0] _RAND_0;
@@ -15327,15 +14092,14 @@
   reg [31:0] _RAND_22;
   reg [31:0] _RAND_24;
   reg [31:0] _RAND_26;
-  reg [31:0] _RAND_28;
 `endif // RANDOMIZE_MEM_INIT
 `ifdef RANDOMIZE_REG_INIT
+  reg [31:0] _RAND_28;
+  reg [31:0] _RAND_29;
   reg [31:0] _RAND_30;
   reg [31:0] _RAND_31;
   reg [31:0] _RAND_32;
   reg [31:0] _RAND_33;
-  reg [31:0] _RAND_34;
-  reg [31:0] _RAND_35;
 `endif // RANDOMIZE_REG_INIT
   reg [31:0] mem_addr [0:6]; // @[Fifo4.scala 59:16]
   wire  mem_addr_mslice_io_in_bits_MPORT_en; // @[Fifo4.scala 59:16]
@@ -16149,122 +14913,6 @@
   wire [2:0] mem_sext_MPORT_27_addr; // @[Fifo4.scala 59:16]
   wire  mem_sext_MPORT_27_mask; // @[Fifo4.scala 59:16]
   wire  mem_sext_MPORT_27_en; // @[Fifo4.scala 59:16]
-  reg  mem_fload [0:6]; // @[Fifo4.scala 59:16]
-  wire  mem_fload_mslice_io_in_bits_MPORT_en; // @[Fifo4.scala 59:16]
-  wire [2:0] mem_fload_mslice_io_in_bits_MPORT_addr; // @[Fifo4.scala 59:16]
-  wire  mem_fload_mslice_io_in_bits_MPORT_data; // @[Fifo4.scala 59:16]
-  wire  mem_fload_MPORT_data; // @[Fifo4.scala 59:16]
-  wire [2:0] mem_fload_MPORT_addr; // @[Fifo4.scala 59:16]
-  wire  mem_fload_MPORT_mask; // @[Fifo4.scala 59:16]
-  wire  mem_fload_MPORT_en; // @[Fifo4.scala 59:16]
-  wire  mem_fload_MPORT_1_data; // @[Fifo4.scala 59:16]
-  wire [2:0] mem_fload_MPORT_1_addr; // @[Fifo4.scala 59:16]
-  wire  mem_fload_MPORT_1_mask; // @[Fifo4.scala 59:16]
-  wire  mem_fload_MPORT_1_en; // @[Fifo4.scala 59:16]
-  wire  mem_fload_MPORT_2_data; // @[Fifo4.scala 59:16]
-  wire [2:0] mem_fload_MPORT_2_addr; // @[Fifo4.scala 59:16]
-  wire  mem_fload_MPORT_2_mask; // @[Fifo4.scala 59:16]
-  wire  mem_fload_MPORT_2_en; // @[Fifo4.scala 59:16]
-  wire  mem_fload_MPORT_3_data; // @[Fifo4.scala 59:16]
-  wire [2:0] mem_fload_MPORT_3_addr; // @[Fifo4.scala 59:16]
-  wire  mem_fload_MPORT_3_mask; // @[Fifo4.scala 59:16]
-  wire  mem_fload_MPORT_3_en; // @[Fifo4.scala 59:16]
-  wire  mem_fload_MPORT_4_data; // @[Fifo4.scala 59:16]
-  wire [2:0] mem_fload_MPORT_4_addr; // @[Fifo4.scala 59:16]
-  wire  mem_fload_MPORT_4_mask; // @[Fifo4.scala 59:16]
-  wire  mem_fload_MPORT_4_en; // @[Fifo4.scala 59:16]
-  wire  mem_fload_MPORT_5_data; // @[Fifo4.scala 59:16]
-  wire [2:0] mem_fload_MPORT_5_addr; // @[Fifo4.scala 59:16]
-  wire  mem_fload_MPORT_5_mask; // @[Fifo4.scala 59:16]
-  wire  mem_fload_MPORT_5_en; // @[Fifo4.scala 59:16]
-  wire  mem_fload_MPORT_6_data; // @[Fifo4.scala 59:16]
-  wire [2:0] mem_fload_MPORT_6_addr; // @[Fifo4.scala 59:16]
-  wire  mem_fload_MPORT_6_mask; // @[Fifo4.scala 59:16]
-  wire  mem_fload_MPORT_6_en; // @[Fifo4.scala 59:16]
-  wire  mem_fload_MPORT_7_data; // @[Fifo4.scala 59:16]
-  wire [2:0] mem_fload_MPORT_7_addr; // @[Fifo4.scala 59:16]
-  wire  mem_fload_MPORT_7_mask; // @[Fifo4.scala 59:16]
-  wire  mem_fload_MPORT_7_en; // @[Fifo4.scala 59:16]
-  wire  mem_fload_MPORT_8_data; // @[Fifo4.scala 59:16]
-  wire [2:0] mem_fload_MPORT_8_addr; // @[Fifo4.scala 59:16]
-  wire  mem_fload_MPORT_8_mask; // @[Fifo4.scala 59:16]
-  wire  mem_fload_MPORT_8_en; // @[Fifo4.scala 59:16]
-  wire  mem_fload_MPORT_9_data; // @[Fifo4.scala 59:16]
-  wire [2:0] mem_fload_MPORT_9_addr; // @[Fifo4.scala 59:16]
-  wire  mem_fload_MPORT_9_mask; // @[Fifo4.scala 59:16]
-  wire  mem_fload_MPORT_9_en; // @[Fifo4.scala 59:16]
-  wire  mem_fload_MPORT_10_data; // @[Fifo4.scala 59:16]
-  wire [2:0] mem_fload_MPORT_10_addr; // @[Fifo4.scala 59:16]
-  wire  mem_fload_MPORT_10_mask; // @[Fifo4.scala 59:16]
-  wire  mem_fload_MPORT_10_en; // @[Fifo4.scala 59:16]
-  wire  mem_fload_MPORT_11_data; // @[Fifo4.scala 59:16]
-  wire [2:0] mem_fload_MPORT_11_addr; // @[Fifo4.scala 59:16]
-  wire  mem_fload_MPORT_11_mask; // @[Fifo4.scala 59:16]
-  wire  mem_fload_MPORT_11_en; // @[Fifo4.scala 59:16]
-  wire  mem_fload_MPORT_12_data; // @[Fifo4.scala 59:16]
-  wire [2:0] mem_fload_MPORT_12_addr; // @[Fifo4.scala 59:16]
-  wire  mem_fload_MPORT_12_mask; // @[Fifo4.scala 59:16]
-  wire  mem_fload_MPORT_12_en; // @[Fifo4.scala 59:16]
-  wire  mem_fload_MPORT_13_data; // @[Fifo4.scala 59:16]
-  wire [2:0] mem_fload_MPORT_13_addr; // @[Fifo4.scala 59:16]
-  wire  mem_fload_MPORT_13_mask; // @[Fifo4.scala 59:16]
-  wire  mem_fload_MPORT_13_en; // @[Fifo4.scala 59:16]
-  wire  mem_fload_MPORT_14_data; // @[Fifo4.scala 59:16]
-  wire [2:0] mem_fload_MPORT_14_addr; // @[Fifo4.scala 59:16]
-  wire  mem_fload_MPORT_14_mask; // @[Fifo4.scala 59:16]
-  wire  mem_fload_MPORT_14_en; // @[Fifo4.scala 59:16]
-  wire  mem_fload_MPORT_15_data; // @[Fifo4.scala 59:16]
-  wire [2:0] mem_fload_MPORT_15_addr; // @[Fifo4.scala 59:16]
-  wire  mem_fload_MPORT_15_mask; // @[Fifo4.scala 59:16]
-  wire  mem_fload_MPORT_15_en; // @[Fifo4.scala 59:16]
-  wire  mem_fload_MPORT_16_data; // @[Fifo4.scala 59:16]
-  wire [2:0] mem_fload_MPORT_16_addr; // @[Fifo4.scala 59:16]
-  wire  mem_fload_MPORT_16_mask; // @[Fifo4.scala 59:16]
-  wire  mem_fload_MPORT_16_en; // @[Fifo4.scala 59:16]
-  wire  mem_fload_MPORT_17_data; // @[Fifo4.scala 59:16]
-  wire [2:0] mem_fload_MPORT_17_addr; // @[Fifo4.scala 59:16]
-  wire  mem_fload_MPORT_17_mask; // @[Fifo4.scala 59:16]
-  wire  mem_fload_MPORT_17_en; // @[Fifo4.scala 59:16]
-  wire  mem_fload_MPORT_18_data; // @[Fifo4.scala 59:16]
-  wire [2:0] mem_fload_MPORT_18_addr; // @[Fifo4.scala 59:16]
-  wire  mem_fload_MPORT_18_mask; // @[Fifo4.scala 59:16]
-  wire  mem_fload_MPORT_18_en; // @[Fifo4.scala 59:16]
-  wire  mem_fload_MPORT_19_data; // @[Fifo4.scala 59:16]
-  wire [2:0] mem_fload_MPORT_19_addr; // @[Fifo4.scala 59:16]
-  wire  mem_fload_MPORT_19_mask; // @[Fifo4.scala 59:16]
-  wire  mem_fload_MPORT_19_en; // @[Fifo4.scala 59:16]
-  wire  mem_fload_MPORT_20_data; // @[Fifo4.scala 59:16]
-  wire [2:0] mem_fload_MPORT_20_addr; // @[Fifo4.scala 59:16]
-  wire  mem_fload_MPORT_20_mask; // @[Fifo4.scala 59:16]
-  wire  mem_fload_MPORT_20_en; // @[Fifo4.scala 59:16]
-  wire  mem_fload_MPORT_21_data; // @[Fifo4.scala 59:16]
-  wire [2:0] mem_fload_MPORT_21_addr; // @[Fifo4.scala 59:16]
-  wire  mem_fload_MPORT_21_mask; // @[Fifo4.scala 59:16]
-  wire  mem_fload_MPORT_21_en; // @[Fifo4.scala 59:16]
-  wire  mem_fload_MPORT_22_data; // @[Fifo4.scala 59:16]
-  wire [2:0] mem_fload_MPORT_22_addr; // @[Fifo4.scala 59:16]
-  wire  mem_fload_MPORT_22_mask; // @[Fifo4.scala 59:16]
-  wire  mem_fload_MPORT_22_en; // @[Fifo4.scala 59:16]
-  wire  mem_fload_MPORT_23_data; // @[Fifo4.scala 59:16]
-  wire [2:0] mem_fload_MPORT_23_addr; // @[Fifo4.scala 59:16]
-  wire  mem_fload_MPORT_23_mask; // @[Fifo4.scala 59:16]
-  wire  mem_fload_MPORT_23_en; // @[Fifo4.scala 59:16]
-  wire  mem_fload_MPORT_24_data; // @[Fifo4.scala 59:16]
-  wire [2:0] mem_fload_MPORT_24_addr; // @[Fifo4.scala 59:16]
-  wire  mem_fload_MPORT_24_mask; // @[Fifo4.scala 59:16]
-  wire  mem_fload_MPORT_24_en; // @[Fifo4.scala 59:16]
-  wire  mem_fload_MPORT_25_data; // @[Fifo4.scala 59:16]
-  wire [2:0] mem_fload_MPORT_25_addr; // @[Fifo4.scala 59:16]
-  wire  mem_fload_MPORT_25_mask; // @[Fifo4.scala 59:16]
-  wire  mem_fload_MPORT_25_en; // @[Fifo4.scala 59:16]
-  wire  mem_fload_MPORT_26_data; // @[Fifo4.scala 59:16]
-  wire [2:0] mem_fload_MPORT_26_addr; // @[Fifo4.scala 59:16]
-  wire  mem_fload_MPORT_26_mask; // @[Fifo4.scala 59:16]
-  wire  mem_fload_MPORT_26_en; // @[Fifo4.scala 59:16]
-  wire  mem_fload_MPORT_27_data; // @[Fifo4.scala 59:16]
-  wire [2:0] mem_fload_MPORT_27_addr; // @[Fifo4.scala 59:16]
-  wire  mem_fload_MPORT_27_mask; // @[Fifo4.scala 59:16]
-  wire  mem_fload_MPORT_27_en; // @[Fifo4.scala 59:16]
   reg  mem_iload [0:6]; // @[Fifo4.scala 59:16]
   wire  mem_iload_mslice_io_in_bits_MPORT_en; // @[Fifo4.scala 59:16]
   wire [2:0] mem_iload_mslice_io_in_bits_MPORT_addr; // @[Fifo4.scala 59:16]
@@ -17088,7 +15736,6 @@
   wire [5:0] mslice_io_in_bits_size; // @[Slice.scala 9:11]
   wire  mslice_io_in_bits_write; // @[Slice.scala 9:11]
   wire  mslice_io_in_bits_sext; // @[Slice.scala 9:11]
-  wire  mslice_io_in_bits_fload; // @[Slice.scala 9:11]
   wire  mslice_io_in_bits_iload; // @[Slice.scala 9:11]
   wire  mslice_io_in_bits_fencei; // @[Slice.scala 9:11]
   wire  mslice_io_in_bits_flushat; // @[Slice.scala 9:11]
@@ -17105,7 +15752,6 @@
   wire [5:0] mslice_io_out_bits_size; // @[Slice.scala 9:11]
   wire  mslice_io_out_bits_write; // @[Slice.scala 9:11]
   wire  mslice_io_out_bits_sext; // @[Slice.scala 9:11]
-  wire  mslice_io_out_bits_fload; // @[Slice.scala 9:11]
   wire  mslice_io_out_bits_iload; // @[Slice.scala 9:11]
   wire  mslice_io_out_bits_fencei; // @[Slice.scala 9:11]
   wire  mslice_io_out_bits_flushat; // @[Slice.scala 9:11]
@@ -17119,15 +15765,15 @@
   reg [2:0] in3pos; // @[Fifo4.scala 65:23]
   reg [2:0] outpos; // @[Fifo4.scala 66:23]
   reg [3:0] mcount; // @[Fifo4.scala 67:23]
-  wire [3:0] _GEN_1950 = {{3'd0}, io_out_valid}; // @[Fifo4.scala 69:22]
+  wire [3:0] _GEN_1846 = {{3'd0}, io_out_valid}; // @[Fifo4.scala 69:22]
   wire  ivalid = io_in_valid & io_in_ready; // @[Fifo4.scala 71:28]
   wire  ovalid = mslice_io_in_valid & mslice_io_in_ready; // @[Fifo4.scala 72:35]
   wire [3:0] iactive = {io_in_bits_3_valid,io_in_bits_2_valid,io_in_bits_1_valid,io_in_bits_0_valid}; // @[Cat.scala 31:58]
   wire [1:0] _icount_T = io_in_bits_0_valid + io_in_bits_1_valid; // @[Fifo4.scala 77:36]
-  wire [1:0] _GEN_1951 = {{1'd0}, io_in_bits_2_valid}; // @[Fifo4.scala 77:59]
-  wire [1:0] _icount_T_2 = _icount_T + _GEN_1951; // @[Fifo4.scala 77:59]
-  wire [1:0] _GEN_1952 = {{1'd0}, io_in_bits_3_valid}; // @[Fifo4.scala 78:36]
-  wire [2:0] icount = _icount_T_2 + _GEN_1952; // @[Fifo4.scala 78:36]
+  wire [1:0] _GEN_1847 = {{1'd0}, io_in_bits_2_valid}; // @[Fifo4.scala 77:59]
+  wire [1:0] _icount_T_2 = _icount_T + _GEN_1847; // @[Fifo4.scala 77:59]
+  wire [1:0] _GEN_1848 = {{1'd0}, io_in_bits_3_valid}; // @[Fifo4.scala 78:36]
+  wire [2:0] icount = _icount_T_2 + _GEN_1848; // @[Fifo4.scala 78:36]
   wire [3:0] in0pos_c = in0pos + icount; // @[Fifo4.scala 54:15]
   wire [3:0] _in0pos_d_T_2 = in0pos_c - 4'h7; // @[Fifo4.scala 55:31]
   wire [3:0] _in0pos_d_T_3 = in0pos_c < 4'h7 ? in0pos_c : _in0pos_d_T_2; // @[Fifo4.scala 55:16]
@@ -17149,10 +15795,10 @@
   wire [3:0] _outpos_d_T_3 = outpos_c < 4'h7 ? outpos_c : _outpos_d_T_2; // @[Fifo4.scala 55:16]
   wire [2:0] outpos_d = _outpos_d_T_3[2:0]; // @[Fifo4.scala 55:37]
   wire [2:0] inc = ivalid ? icount : 3'h0; // @[Library.scala 8:8]
-  wire [3:0] _GEN_1953 = {{1'd0}, inc}; // @[Fifo4.scala 97:22]
-  wire [3:0] _mcount_T_1 = mcount + _GEN_1953; // @[Fifo4.scala 97:22]
-  wire [3:0] _GEN_1954 = {{3'd0}, ovalid}; // @[Fifo4.scala 97:28]
-  wire [3:0] _mcount_T_3 = _mcount_T_1 - _GEN_1954; // @[Fifo4.scala 97:28]
+  wire [3:0] _GEN_1849 = {{1'd0}, inc}; // @[Fifo4.scala 97:22]
+  wire [3:0] _mcount_T_1 = mcount + _GEN_1849; // @[Fifo4.scala 97:22]
+  wire [3:0] _GEN_1850 = {{3'd0}, ovalid}; // @[Fifo4.scala 97:28]
+  wire [3:0] _mcount_T_3 = _mcount_T_1 - _GEN_1850; // @[Fifo4.scala 97:28]
   wire  _in0_T_1 = iactive == 4'h8; // @[Fifo4.scala 17:27]
   wire  _in0_T_3 = iactive[2:0] == 3'h4; // @[Fifo4.scala 18:27]
   wire  _in0_T_5 = iactive[1:0] == 2'h2; // @[Fifo4.scala 19:27]
@@ -17169,9 +15815,9 @@
   wire  _in2_T_4 = iactive == 4'he | _in2_T_3; // @[Fifo4.scala 30:36]
   wire  _in2_T_6 = iactive == 4'hb; // @[Fifo4.scala 32:27]
   wire  _in2_T_7 = _in2_T_4 | _in2_T_6; // @[Fifo4.scala 31:36]
-  wire [3:0] _GEN_1955 = {{1'd0}, iactive[2:0]}; // @[Fifo4.scala 33:27]
+  wire [3:0] _GEN_1851 = {{1'd0}, iactive[2:0]}; // @[Fifo4.scala 33:27]
   wire  _in2_T_11 = iactive[2:0] == 3'h7; // @[Fifo4.scala 34:27]
-  wire  _in2_T_12 = _GEN_1955 == 4'hf | _in2_T_11; // @[Fifo4.scala 33:36]
+  wire  _in2_T_12 = _GEN_1851 == 4'hf | _in2_T_11; // @[Fifo4.scala 33:36]
   wire [3:0] in2valid = {_in2_T_7,_in2_T_12,2'h0}; // @[Cat.scala 31:58]
   wire  _in3_T_1 = iactive == 4'hf; // @[Fifo4.scala 37:27]
   wire [3:0] in3valid = {_in3_T_1,1'h0,2'h0}; // @[Cat.scala 31:58]
@@ -17192,12 +15838,12 @@
   wire  _valid_T_32 = _valid_T & in0valid[1] | _valid_T_31; // @[Fifo4.scala 112:51]
   wire  _valid_T_35 = _valid_T & in0valid[0]; // @[Fifo4.scala 114:36]
   wire [3:0] valid = {_valid_T_14,_valid_T_25,_valid_T_32,_valid_T_35}; // @[Cat.scala 31:58]
-  wire  _GEN_46 = valid[2] ? 1'h0 : valid[3]; // @[Fifo4.scala 131:30 59:16]
-  wire  _GEN_84 = valid[1] ? 1'h0 : valid[2]; // @[Fifo4.scala 129:30 59:16]
-  wire  _GEN_103 = valid[1] ? 1'h0 : _GEN_46; // @[Fifo4.scala 129:30 59:16]
-  wire  _GEN_141 = valid[0] ? 1'h0 : valid[1]; // @[Fifo4.scala 127:23 59:16]
-  wire  _GEN_160 = valid[0] ? 1'h0 : _GEN_84; // @[Fifo4.scala 127:23 59:16]
-  wire  _GEN_179 = valid[0] ? 1'h0 : _GEN_103; // @[Fifo4.scala 127:23 59:16]
+  wire  _GEN_44 = valid[2] ? 1'h0 : valid[3]; // @[Fifo4.scala 131:30 59:16]
+  wire  _GEN_80 = valid[1] ? 1'h0 : valid[2]; // @[Fifo4.scala 129:30 59:16]
+  wire  _GEN_98 = valid[1] ? 1'h0 : _GEN_44; // @[Fifo4.scala 129:30 59:16]
+  wire  _GEN_134 = valid[0] ? 1'h0 : valid[1]; // @[Fifo4.scala 127:23 59:16]
+  wire  _GEN_152 = valid[0] ? 1'h0 : _GEN_80; // @[Fifo4.scala 127:23 59:16]
+  wire  _GEN_170 = valid[0] ? 1'h0 : _GEN_98; // @[Fifo4.scala 127:23 59:16]
   wire  _valid_T_36 = in0pos == 3'h1; // @[Fifo4.scala 105:28]
   wire  _valid_T_39 = in1pos == 3'h1; // @[Fifo4.scala 106:28]
   wire  _valid_T_41 = in1pos == 3'h1 & in1valid[3]; // @[Fifo4.scala 106:36]
@@ -17215,12 +15861,12 @@
   wire  _valid_T_68 = _valid_T_36 & in0valid[1] | _valid_T_67; // @[Fifo4.scala 112:51]
   wire  _valid_T_71 = _valid_T_36 & in0valid[0]; // @[Fifo4.scala 114:36]
   wire [3:0] valid_1 = {_valid_T_50,_valid_T_61,_valid_T_68,_valid_T_71}; // @[Cat.scala 31:58]
-  wire  _GEN_310 = valid_1[2] ? 1'h0 : valid_1[3]; // @[Fifo4.scala 131:30 59:16]
-  wire  _GEN_346 = valid_1[1] ? 1'h0 : valid_1[2]; // @[Fifo4.scala 129:30 59:16]
-  wire  _GEN_364 = valid_1[1] ? 1'h0 : _GEN_310; // @[Fifo4.scala 129:30 59:16]
-  wire  _GEN_400 = valid_1[0] ? 1'h0 : valid_1[1]; // @[Fifo4.scala 127:23 59:16]
-  wire  _GEN_418 = valid_1[0] ? 1'h0 : _GEN_346; // @[Fifo4.scala 127:23 59:16]
-  wire  _GEN_436 = valid_1[0] ? 1'h0 : _GEN_364; // @[Fifo4.scala 127:23 59:16]
+  wire  _GEN_294 = valid_1[2] ? 1'h0 : valid_1[3]; // @[Fifo4.scala 131:30 59:16]
+  wire  _GEN_328 = valid_1[1] ? 1'h0 : valid_1[2]; // @[Fifo4.scala 129:30 59:16]
+  wire  _GEN_345 = valid_1[1] ? 1'h0 : _GEN_294; // @[Fifo4.scala 129:30 59:16]
+  wire  _GEN_379 = valid_1[0] ? 1'h0 : valid_1[1]; // @[Fifo4.scala 127:23 59:16]
+  wire  _GEN_396 = valid_1[0] ? 1'h0 : _GEN_328; // @[Fifo4.scala 127:23 59:16]
+  wire  _GEN_413 = valid_1[0] ? 1'h0 : _GEN_345; // @[Fifo4.scala 127:23 59:16]
   wire  _valid_T_72 = in0pos == 3'h2; // @[Fifo4.scala 105:28]
   wire  _valid_T_75 = in1pos == 3'h2; // @[Fifo4.scala 106:28]
   wire  _valid_T_77 = in1pos == 3'h2 & in1valid[3]; // @[Fifo4.scala 106:36]
@@ -17238,12 +15884,12 @@
   wire  _valid_T_104 = _valid_T_72 & in0valid[1] | _valid_T_103; // @[Fifo4.scala 112:51]
   wire  _valid_T_107 = _valid_T_72 & in0valid[0]; // @[Fifo4.scala 114:36]
   wire [3:0] valid_2 = {_valid_T_86,_valid_T_97,_valid_T_104,_valid_T_107}; // @[Cat.scala 31:58]
-  wire  _GEN_564 = valid_2[2] ? 1'h0 : valid_2[3]; // @[Fifo4.scala 131:30 59:16]
-  wire  _GEN_602 = valid_2[1] ? 1'h0 : valid_2[2]; // @[Fifo4.scala 129:30 59:16]
-  wire  _GEN_621 = valid_2[1] ? 1'h0 : _GEN_564; // @[Fifo4.scala 129:30 59:16]
-  wire  _GEN_659 = valid_2[0] ? 1'h0 : valid_2[1]; // @[Fifo4.scala 127:23 59:16]
-  wire  _GEN_678 = valid_2[0] ? 1'h0 : _GEN_602; // @[Fifo4.scala 127:23 59:16]
-  wire  _GEN_697 = valid_2[0] ? 1'h0 : _GEN_621; // @[Fifo4.scala 127:23 59:16]
+  wire  _GEN_534 = valid_2[2] ? 1'h0 : valid_2[3]; // @[Fifo4.scala 131:30 59:16]
+  wire  _GEN_570 = valid_2[1] ? 1'h0 : valid_2[2]; // @[Fifo4.scala 129:30 59:16]
+  wire  _GEN_588 = valid_2[1] ? 1'h0 : _GEN_534; // @[Fifo4.scala 129:30 59:16]
+  wire  _GEN_624 = valid_2[0] ? 1'h0 : valid_2[1]; // @[Fifo4.scala 127:23 59:16]
+  wire  _GEN_642 = valid_2[0] ? 1'h0 : _GEN_570; // @[Fifo4.scala 127:23 59:16]
+  wire  _GEN_660 = valid_2[0] ? 1'h0 : _GEN_588; // @[Fifo4.scala 127:23 59:16]
   wire  _valid_T_108 = in0pos == 3'h3; // @[Fifo4.scala 105:28]
   wire  _valid_T_111 = in1pos == 3'h3; // @[Fifo4.scala 106:28]
   wire  _valid_T_113 = in1pos == 3'h3 & in1valid[3]; // @[Fifo4.scala 106:36]
@@ -17261,12 +15907,12 @@
   wire  _valid_T_140 = _valid_T_108 & in0valid[1] | _valid_T_139; // @[Fifo4.scala 112:51]
   wire  _valid_T_143 = _valid_T_108 & in0valid[0]; // @[Fifo4.scala 114:36]
   wire [3:0] valid_3 = {_valid_T_122,_valid_T_133,_valid_T_140,_valid_T_143}; // @[Cat.scala 31:58]
-  wire  _GEN_830 = valid_3[2] ? 1'h0 : valid_3[3]; // @[Fifo4.scala 131:30 59:16]
-  wire  _GEN_868 = valid_3[1] ? 1'h0 : valid_3[2]; // @[Fifo4.scala 129:30 59:16]
-  wire  _GEN_887 = valid_3[1] ? 1'h0 : _GEN_830; // @[Fifo4.scala 129:30 59:16]
-  wire  _GEN_925 = valid_3[0] ? 1'h0 : valid_3[1]; // @[Fifo4.scala 127:23 59:16]
-  wire  _GEN_944 = valid_3[0] ? 1'h0 : _GEN_868; // @[Fifo4.scala 127:23 59:16]
-  wire  _GEN_963 = valid_3[0] ? 1'h0 : _GEN_887; // @[Fifo4.scala 127:23 59:16]
+  wire  _GEN_786 = valid_3[2] ? 1'h0 : valid_3[3]; // @[Fifo4.scala 131:30 59:16]
+  wire  _GEN_822 = valid_3[1] ? 1'h0 : valid_3[2]; // @[Fifo4.scala 129:30 59:16]
+  wire  _GEN_840 = valid_3[1] ? 1'h0 : _GEN_786; // @[Fifo4.scala 129:30 59:16]
+  wire  _GEN_876 = valid_3[0] ? 1'h0 : valid_3[1]; // @[Fifo4.scala 127:23 59:16]
+  wire  _GEN_894 = valid_3[0] ? 1'h0 : _GEN_822; // @[Fifo4.scala 127:23 59:16]
+  wire  _GEN_912 = valid_3[0] ? 1'h0 : _GEN_840; // @[Fifo4.scala 127:23 59:16]
   wire  _valid_T_144 = in0pos == 3'h4; // @[Fifo4.scala 105:28]
   wire  _valid_T_147 = in1pos == 3'h4; // @[Fifo4.scala 106:28]
   wire  _valid_T_149 = in1pos == 3'h4 & in1valid[3]; // @[Fifo4.scala 106:36]
@@ -17284,12 +15930,12 @@
   wire  _valid_T_176 = _valid_T_144 & in0valid[1] | _valid_T_175; // @[Fifo4.scala 112:51]
   wire  _valid_T_179 = _valid_T_144 & in0valid[0]; // @[Fifo4.scala 114:36]
   wire [3:0] valid_4 = {_valid_T_158,_valid_T_169,_valid_T_176,_valid_T_179}; // @[Cat.scala 31:58]
-  wire  _GEN_1096 = valid_4[2] ? 1'h0 : valid_4[3]; // @[Fifo4.scala 131:30 59:16]
-  wire  _GEN_1134 = valid_4[1] ? 1'h0 : valid_4[2]; // @[Fifo4.scala 129:30 59:16]
-  wire  _GEN_1153 = valid_4[1] ? 1'h0 : _GEN_1096; // @[Fifo4.scala 129:30 59:16]
-  wire  _GEN_1191 = valid_4[0] ? 1'h0 : valid_4[1]; // @[Fifo4.scala 127:23 59:16]
-  wire  _GEN_1210 = valid_4[0] ? 1'h0 : _GEN_1134; // @[Fifo4.scala 127:23 59:16]
-  wire  _GEN_1229 = valid_4[0] ? 1'h0 : _GEN_1153; // @[Fifo4.scala 127:23 59:16]
+  wire  _GEN_1038 = valid_4[2] ? 1'h0 : valid_4[3]; // @[Fifo4.scala 131:30 59:16]
+  wire  _GEN_1074 = valid_4[1] ? 1'h0 : valid_4[2]; // @[Fifo4.scala 129:30 59:16]
+  wire  _GEN_1092 = valid_4[1] ? 1'h0 : _GEN_1038; // @[Fifo4.scala 129:30 59:16]
+  wire  _GEN_1128 = valid_4[0] ? 1'h0 : valid_4[1]; // @[Fifo4.scala 127:23 59:16]
+  wire  _GEN_1146 = valid_4[0] ? 1'h0 : _GEN_1074; // @[Fifo4.scala 127:23 59:16]
+  wire  _GEN_1164 = valid_4[0] ? 1'h0 : _GEN_1092; // @[Fifo4.scala 127:23 59:16]
   wire  _valid_T_180 = in0pos == 3'h5; // @[Fifo4.scala 105:28]
   wire  _valid_T_183 = in1pos == 3'h5; // @[Fifo4.scala 106:28]
   wire  _valid_T_185 = in1pos == 3'h5 & in1valid[3]; // @[Fifo4.scala 106:36]
@@ -17307,12 +15953,12 @@
   wire  _valid_T_212 = _valid_T_180 & in0valid[1] | _valid_T_211; // @[Fifo4.scala 112:51]
   wire  _valid_T_215 = _valid_T_180 & in0valid[0]; // @[Fifo4.scala 114:36]
   wire [3:0] valid_5 = {_valid_T_194,_valid_T_205,_valid_T_212,_valid_T_215}; // @[Cat.scala 31:58]
-  wire  _GEN_1362 = valid_5[2] ? 1'h0 : valid_5[3]; // @[Fifo4.scala 131:30 59:16]
-  wire  _GEN_1400 = valid_5[1] ? 1'h0 : valid_5[2]; // @[Fifo4.scala 129:30 59:16]
-  wire  _GEN_1419 = valid_5[1] ? 1'h0 : _GEN_1362; // @[Fifo4.scala 129:30 59:16]
-  wire  _GEN_1457 = valid_5[0] ? 1'h0 : valid_5[1]; // @[Fifo4.scala 127:23 59:16]
-  wire  _GEN_1476 = valid_5[0] ? 1'h0 : _GEN_1400; // @[Fifo4.scala 127:23 59:16]
-  wire  _GEN_1495 = valid_5[0] ? 1'h0 : _GEN_1419; // @[Fifo4.scala 127:23 59:16]
+  wire  _GEN_1290 = valid_5[2] ? 1'h0 : valid_5[3]; // @[Fifo4.scala 131:30 59:16]
+  wire  _GEN_1326 = valid_5[1] ? 1'h0 : valid_5[2]; // @[Fifo4.scala 129:30 59:16]
+  wire  _GEN_1344 = valid_5[1] ? 1'h0 : _GEN_1290; // @[Fifo4.scala 129:30 59:16]
+  wire  _GEN_1380 = valid_5[0] ? 1'h0 : valid_5[1]; // @[Fifo4.scala 127:23 59:16]
+  wire  _GEN_1398 = valid_5[0] ? 1'h0 : _GEN_1326; // @[Fifo4.scala 127:23 59:16]
+  wire  _GEN_1416 = valid_5[0] ? 1'h0 : _GEN_1344; // @[Fifo4.scala 127:23 59:16]
   wire  _valid_T_216 = in0pos == 3'h6; // @[Fifo4.scala 105:28]
   wire  _valid_T_219 = in1pos == 3'h6; // @[Fifo4.scala 106:28]
   wire  _valid_T_221 = in1pos == 3'h6 & in1valid[3]; // @[Fifo4.scala 106:36]
@@ -17330,91 +15976,86 @@
   wire  _valid_T_248 = _valid_T_216 & in0valid[1] | _valid_T_247; // @[Fifo4.scala 112:51]
   wire  _valid_T_251 = _valid_T_216 & in0valid[0]; // @[Fifo4.scala 114:36]
   wire [3:0] valid_6 = {_valid_T_230,_valid_T_241,_valid_T_248,_valid_T_251}; // @[Cat.scala 31:58]
-  wire  _GEN_1628 = valid_6[2] ? 1'h0 : valid_6[3]; // @[Fifo4.scala 131:30 59:16]
-  wire  _GEN_1666 = valid_6[1] ? 1'h0 : valid_6[2]; // @[Fifo4.scala 129:30 59:16]
-  wire  _GEN_1685 = valid_6[1] ? 1'h0 : _GEN_1628; // @[Fifo4.scala 129:30 59:16]
-  wire  _GEN_1723 = valid_6[0] ? 1'h0 : valid_6[1]; // @[Fifo4.scala 127:23 59:16]
-  wire  _GEN_1742 = valid_6[0] ? 1'h0 : _GEN_1666; // @[Fifo4.scala 127:23 59:16]
-  wire  _GEN_1761 = valid_6[0] ? 1'h0 : _GEN_1685; // @[Fifo4.scala 127:23 59:16]
+  wire  _GEN_1542 = valid_6[2] ? 1'h0 : valid_6[3]; // @[Fifo4.scala 131:30 59:16]
+  wire  _GEN_1578 = valid_6[1] ? 1'h0 : valid_6[2]; // @[Fifo4.scala 129:30 59:16]
+  wire  _GEN_1596 = valid_6[1] ? 1'h0 : _GEN_1542; // @[Fifo4.scala 129:30 59:16]
+  wire  _GEN_1632 = valid_6[0] ? 1'h0 : valid_6[1]; // @[Fifo4.scala 127:23 59:16]
+  wire  _GEN_1650 = valid_6[0] ? 1'h0 : _GEN_1578; // @[Fifo4.scala 127:23 59:16]
+  wire  _GEN_1668 = valid_6[0] ? 1'h0 : _GEN_1596; // @[Fifo4.scala 127:23 59:16]
   wire  _T_29 = mcount > 4'h0; // @[Fifo4.scala 142:16]
   wire  _T_31 = ivalid & iactive != 4'h0; // @[Fifo4.scala 147:18]
-  wire  _GEN_1857 = iactive[3] ? io_in_bits_3_bits_suncd : io_in_bits_0_bits_suncd; // @[Fifo4.scala 140:21 162:30 163:25]
-  wire  _GEN_1858 = iactive[3] ? io_in_bits_3_bits_vldst : io_in_bits_0_bits_vldst; // @[Fifo4.scala 140:21 162:30 163:25]
-  wire  _GEN_1859 = iactive[3] ? io_in_bits_3_bits_sldst : io_in_bits_0_bits_sldst; // @[Fifo4.scala 140:21 162:30 163:25]
-  wire  _GEN_1860 = iactive[3] ? io_in_bits_3_bits_flushall : io_in_bits_0_bits_flushall; // @[Fifo4.scala 140:21 162:30 163:25]
-  wire  _GEN_1861 = iactive[3] ? io_in_bits_3_bits_flushat : io_in_bits_0_bits_flushat; // @[Fifo4.scala 140:21 162:30 163:25]
-  wire  _GEN_1862 = iactive[3] ? io_in_bits_3_bits_fencei : io_in_bits_0_bits_fencei; // @[Fifo4.scala 140:21 162:30 163:25]
-  wire  _GEN_1863 = iactive[3] ? io_in_bits_3_bits_iload : io_in_bits_0_bits_iload; // @[Fifo4.scala 140:21 162:30 163:25]
-  wire  _GEN_1864 = iactive[3] ? io_in_bits_3_bits_fload : io_in_bits_0_bits_fload; // @[Fifo4.scala 140:21 162:30 163:25]
-  wire  _GEN_1865 = iactive[3] ? io_in_bits_3_bits_sext : io_in_bits_0_bits_sext; // @[Fifo4.scala 140:21 162:30 163:25]
-  wire  _GEN_1866 = iactive[3] ? io_in_bits_3_bits_write : io_in_bits_0_bits_write; // @[Fifo4.scala 140:21 162:30 163:25]
-  wire [5:0] _GEN_1867 = iactive[3] ? io_in_bits_3_bits_size : io_in_bits_0_bits_size; // @[Fifo4.scala 140:21 162:30 163:25]
-  wire [4:0] _GEN_1868 = iactive[3] ? io_in_bits_3_bits_index : io_in_bits_0_bits_index; // @[Fifo4.scala 140:21 162:30 163:25]
-  wire [31:0] _GEN_1869 = iactive[3] ? io_in_bits_3_bits_data : io_in_bits_0_bits_data; // @[Fifo4.scala 140:21 162:30 163:25]
-  wire [31:0] _GEN_1870 = iactive[3] ? io_in_bits_3_bits_adrx : io_in_bits_0_bits_adrx; // @[Fifo4.scala 140:21 162:30 163:25]
-  wire [31:0] _GEN_1871 = iactive[3] ? io_in_bits_3_bits_addr : io_in_bits_0_bits_addr; // @[Fifo4.scala 140:21 162:30 163:25]
-  wire  _GEN_1872 = iactive[2] ? io_in_bits_2_bits_suncd : _GEN_1857; // @[Fifo4.scala 160:30 161:25]
-  wire  _GEN_1873 = iactive[2] ? io_in_bits_2_bits_vldst : _GEN_1858; // @[Fifo4.scala 160:30 161:25]
-  wire  _GEN_1874 = iactive[2] ? io_in_bits_2_bits_sldst : _GEN_1859; // @[Fifo4.scala 160:30 161:25]
-  wire  _GEN_1875 = iactive[2] ? io_in_bits_2_bits_flushall : _GEN_1860; // @[Fifo4.scala 160:30 161:25]
-  wire  _GEN_1876 = iactive[2] ? io_in_bits_2_bits_flushat : _GEN_1861; // @[Fifo4.scala 160:30 161:25]
-  wire  _GEN_1877 = iactive[2] ? io_in_bits_2_bits_fencei : _GEN_1862; // @[Fifo4.scala 160:30 161:25]
-  wire  _GEN_1878 = iactive[2] ? io_in_bits_2_bits_iload : _GEN_1863; // @[Fifo4.scala 160:30 161:25]
-  wire  _GEN_1879 = iactive[2] ? io_in_bits_2_bits_fload : _GEN_1864; // @[Fifo4.scala 160:30 161:25]
-  wire  _GEN_1880 = iactive[2] ? io_in_bits_2_bits_sext : _GEN_1865; // @[Fifo4.scala 160:30 161:25]
-  wire  _GEN_1881 = iactive[2] ? io_in_bits_2_bits_write : _GEN_1866; // @[Fifo4.scala 160:30 161:25]
-  wire [5:0] _GEN_1882 = iactive[2] ? io_in_bits_2_bits_size : _GEN_1867; // @[Fifo4.scala 160:30 161:25]
-  wire [4:0] _GEN_1883 = iactive[2] ? io_in_bits_2_bits_index : _GEN_1868; // @[Fifo4.scala 160:30 161:25]
-  wire [31:0] _GEN_1884 = iactive[2] ? io_in_bits_2_bits_data : _GEN_1869; // @[Fifo4.scala 160:30 161:25]
-  wire [31:0] _GEN_1885 = iactive[2] ? io_in_bits_2_bits_adrx : _GEN_1870; // @[Fifo4.scala 160:30 161:25]
-  wire [31:0] _GEN_1886 = iactive[2] ? io_in_bits_2_bits_addr : _GEN_1871; // @[Fifo4.scala 160:30 161:25]
-  wire  _GEN_1887 = iactive[1] ? io_in_bits_1_bits_suncd : _GEN_1872; // @[Fifo4.scala 158:30 159:25]
-  wire  _GEN_1888 = iactive[1] ? io_in_bits_1_bits_vldst : _GEN_1873; // @[Fifo4.scala 158:30 159:25]
-  wire  _GEN_1889 = iactive[1] ? io_in_bits_1_bits_sldst : _GEN_1874; // @[Fifo4.scala 158:30 159:25]
-  wire  _GEN_1890 = iactive[1] ? io_in_bits_1_bits_flushall : _GEN_1875; // @[Fifo4.scala 158:30 159:25]
-  wire  _GEN_1891 = iactive[1] ? io_in_bits_1_bits_flushat : _GEN_1876; // @[Fifo4.scala 158:30 159:25]
-  wire  _GEN_1892 = iactive[1] ? io_in_bits_1_bits_fencei : _GEN_1877; // @[Fifo4.scala 158:30 159:25]
-  wire  _GEN_1893 = iactive[1] ? io_in_bits_1_bits_iload : _GEN_1878; // @[Fifo4.scala 158:30 159:25]
-  wire  _GEN_1894 = iactive[1] ? io_in_bits_1_bits_fload : _GEN_1879; // @[Fifo4.scala 158:30 159:25]
-  wire  _GEN_1895 = iactive[1] ? io_in_bits_1_bits_sext : _GEN_1880; // @[Fifo4.scala 158:30 159:25]
-  wire  _GEN_1896 = iactive[1] ? io_in_bits_1_bits_write : _GEN_1881; // @[Fifo4.scala 158:30 159:25]
-  wire [5:0] _GEN_1897 = iactive[1] ? io_in_bits_1_bits_size : _GEN_1882; // @[Fifo4.scala 158:30 159:25]
-  wire [4:0] _GEN_1898 = iactive[1] ? io_in_bits_1_bits_index : _GEN_1883; // @[Fifo4.scala 158:30 159:25]
-  wire [31:0] _GEN_1899 = iactive[1] ? io_in_bits_1_bits_data : _GEN_1884; // @[Fifo4.scala 158:30 159:25]
-  wire [31:0] _GEN_1900 = iactive[1] ? io_in_bits_1_bits_adrx : _GEN_1885; // @[Fifo4.scala 158:30 159:25]
-  wire [31:0] _GEN_1901 = iactive[1] ? io_in_bits_1_bits_addr : _GEN_1886; // @[Fifo4.scala 158:30 159:25]
-  wire  _GEN_1902 = iactive[0] ? io_in_bits_0_bits_suncd : _GEN_1887; // @[Fifo4.scala 156:23 157:25]
-  wire  _GEN_1903 = iactive[0] ? io_in_bits_0_bits_vldst : _GEN_1888; // @[Fifo4.scala 156:23 157:25]
-  wire  _GEN_1904 = iactive[0] ? io_in_bits_0_bits_sldst : _GEN_1889; // @[Fifo4.scala 156:23 157:25]
-  wire  _GEN_1905 = iactive[0] ? io_in_bits_0_bits_flushall : _GEN_1890; // @[Fifo4.scala 156:23 157:25]
-  wire  _GEN_1906 = iactive[0] ? io_in_bits_0_bits_flushat : _GEN_1891; // @[Fifo4.scala 156:23 157:25]
-  wire  _GEN_1907 = iactive[0] ? io_in_bits_0_bits_fencei : _GEN_1892; // @[Fifo4.scala 156:23 157:25]
-  wire  _GEN_1908 = iactive[0] ? io_in_bits_0_bits_iload : _GEN_1893; // @[Fifo4.scala 156:23 157:25]
-  wire  _GEN_1909 = iactive[0] ? io_in_bits_0_bits_fload : _GEN_1894; // @[Fifo4.scala 156:23 157:25]
-  wire  _GEN_1910 = iactive[0] ? io_in_bits_0_bits_sext : _GEN_1895; // @[Fifo4.scala 156:23 157:25]
-  wire  _GEN_1911 = iactive[0] ? io_in_bits_0_bits_write : _GEN_1896; // @[Fifo4.scala 156:23 157:25]
-  wire [5:0] _GEN_1912 = iactive[0] ? io_in_bits_0_bits_size : _GEN_1897; // @[Fifo4.scala 156:23 157:25]
-  wire [4:0] _GEN_1913 = iactive[0] ? io_in_bits_0_bits_index : _GEN_1898; // @[Fifo4.scala 156:23 157:25]
-  wire [31:0] _GEN_1914 = iactive[0] ? io_in_bits_0_bits_data : _GEN_1899; // @[Fifo4.scala 156:23 157:25]
-  wire [31:0] _GEN_1915 = iactive[0] ? io_in_bits_0_bits_adrx : _GEN_1900; // @[Fifo4.scala 156:23 157:25]
-  wire [31:0] _GEN_1916 = iactive[0] ? io_in_bits_0_bits_addr : _GEN_1901; // @[Fifo4.scala 156:23 157:25]
-  wire  _GEN_1917 = ivalid ? _GEN_1902 : io_in_bits_0_bits_suncd; // @[Fifo4.scala 140:21 154:24]
-  wire  _GEN_1918 = ivalid ? _GEN_1903 : io_in_bits_0_bits_vldst; // @[Fifo4.scala 140:21 154:24]
-  wire  _GEN_1919 = ivalid ? _GEN_1904 : io_in_bits_0_bits_sldst; // @[Fifo4.scala 140:21 154:24]
-  wire  _GEN_1920 = ivalid ? _GEN_1905 : io_in_bits_0_bits_flushall; // @[Fifo4.scala 140:21 154:24]
-  wire  _GEN_1921 = ivalid ? _GEN_1906 : io_in_bits_0_bits_flushat; // @[Fifo4.scala 140:21 154:24]
-  wire  _GEN_1922 = ivalid ? _GEN_1907 : io_in_bits_0_bits_fencei; // @[Fifo4.scala 140:21 154:24]
-  wire  _GEN_1923 = ivalid ? _GEN_1908 : io_in_bits_0_bits_iload; // @[Fifo4.scala 140:21 154:24]
-  wire  _GEN_1924 = ivalid ? _GEN_1909 : io_in_bits_0_bits_fload; // @[Fifo4.scala 140:21 154:24]
-  wire  _GEN_1925 = ivalid ? _GEN_1910 : io_in_bits_0_bits_sext; // @[Fifo4.scala 140:21 154:24]
-  wire  _GEN_1926 = ivalid ? _GEN_1911 : io_in_bits_0_bits_write; // @[Fifo4.scala 140:21 154:24]
-  wire [5:0] _GEN_1927 = ivalid ? _GEN_1912 : io_in_bits_0_bits_size; // @[Fifo4.scala 140:21 154:24]
-  wire [4:0] _GEN_1928 = ivalid ? _GEN_1913 : io_in_bits_0_bits_index; // @[Fifo4.scala 140:21 154:24]
-  wire [31:0] _GEN_1929 = ivalid ? _GEN_1914 : io_in_bits_0_bits_data; // @[Fifo4.scala 140:21 154:24]
-  wire [31:0] _GEN_1930 = ivalid ? _GEN_1915 : io_in_bits_0_bits_adrx; // @[Fifo4.scala 140:21 154:24]
-  wire [31:0] _GEN_1931 = ivalid ? _GEN_1916 : io_in_bits_0_bits_addr; // @[Fifo4.scala 140:21 154:24]
+  wire  _GEN_1759 = iactive[3] ? io_in_bits_3_bits_suncd : io_in_bits_0_bits_suncd; // @[Fifo4.scala 140:21 162:30 163:25]
+  wire  _GEN_1760 = iactive[3] ? io_in_bits_3_bits_vldst : io_in_bits_0_bits_vldst; // @[Fifo4.scala 140:21 162:30 163:25]
+  wire  _GEN_1761 = iactive[3] ? io_in_bits_3_bits_sldst : io_in_bits_0_bits_sldst; // @[Fifo4.scala 140:21 162:30 163:25]
+  wire  _GEN_1762 = iactive[3] ? io_in_bits_3_bits_flushall : io_in_bits_0_bits_flushall; // @[Fifo4.scala 140:21 162:30 163:25]
+  wire  _GEN_1763 = iactive[3] ? io_in_bits_3_bits_flushat : io_in_bits_0_bits_flushat; // @[Fifo4.scala 140:21 162:30 163:25]
+  wire  _GEN_1764 = iactive[3] ? io_in_bits_3_bits_fencei : io_in_bits_0_bits_fencei; // @[Fifo4.scala 140:21 162:30 163:25]
+  wire  _GEN_1765 = iactive[3] ? io_in_bits_3_bits_iload : io_in_bits_0_bits_iload; // @[Fifo4.scala 140:21 162:30 163:25]
+  wire  _GEN_1766 = iactive[3] ? io_in_bits_3_bits_sext : io_in_bits_0_bits_sext; // @[Fifo4.scala 140:21 162:30 163:25]
+  wire  _GEN_1767 = iactive[3] ? io_in_bits_3_bits_write : io_in_bits_0_bits_write; // @[Fifo4.scala 140:21 162:30 163:25]
+  wire [5:0] _GEN_1768 = iactive[3] ? io_in_bits_3_bits_size : io_in_bits_0_bits_size; // @[Fifo4.scala 140:21 162:30 163:25]
+  wire [4:0] _GEN_1769 = iactive[3] ? io_in_bits_3_bits_index : io_in_bits_0_bits_index; // @[Fifo4.scala 140:21 162:30 163:25]
+  wire [31:0] _GEN_1770 = iactive[3] ? io_in_bits_3_bits_data : io_in_bits_0_bits_data; // @[Fifo4.scala 140:21 162:30 163:25]
+  wire [31:0] _GEN_1771 = iactive[3] ? io_in_bits_3_bits_adrx : io_in_bits_0_bits_adrx; // @[Fifo4.scala 140:21 162:30 163:25]
+  wire [31:0] _GEN_1772 = iactive[3] ? io_in_bits_3_bits_addr : io_in_bits_0_bits_addr; // @[Fifo4.scala 140:21 162:30 163:25]
+  wire  _GEN_1773 = iactive[2] ? io_in_bits_2_bits_suncd : _GEN_1759; // @[Fifo4.scala 160:30 161:25]
+  wire  _GEN_1774 = iactive[2] ? io_in_bits_2_bits_vldst : _GEN_1760; // @[Fifo4.scala 160:30 161:25]
+  wire  _GEN_1775 = iactive[2] ? io_in_bits_2_bits_sldst : _GEN_1761; // @[Fifo4.scala 160:30 161:25]
+  wire  _GEN_1776 = iactive[2] ? io_in_bits_2_bits_flushall : _GEN_1762; // @[Fifo4.scala 160:30 161:25]
+  wire  _GEN_1777 = iactive[2] ? io_in_bits_2_bits_flushat : _GEN_1763; // @[Fifo4.scala 160:30 161:25]
+  wire  _GEN_1778 = iactive[2] ? io_in_bits_2_bits_fencei : _GEN_1764; // @[Fifo4.scala 160:30 161:25]
+  wire  _GEN_1779 = iactive[2] ? io_in_bits_2_bits_iload : _GEN_1765; // @[Fifo4.scala 160:30 161:25]
+  wire  _GEN_1780 = iactive[2] ? io_in_bits_2_bits_sext : _GEN_1766; // @[Fifo4.scala 160:30 161:25]
+  wire  _GEN_1781 = iactive[2] ? io_in_bits_2_bits_write : _GEN_1767; // @[Fifo4.scala 160:30 161:25]
+  wire [5:0] _GEN_1782 = iactive[2] ? io_in_bits_2_bits_size : _GEN_1768; // @[Fifo4.scala 160:30 161:25]
+  wire [4:0] _GEN_1783 = iactive[2] ? io_in_bits_2_bits_index : _GEN_1769; // @[Fifo4.scala 160:30 161:25]
+  wire [31:0] _GEN_1784 = iactive[2] ? io_in_bits_2_bits_data : _GEN_1770; // @[Fifo4.scala 160:30 161:25]
+  wire [31:0] _GEN_1785 = iactive[2] ? io_in_bits_2_bits_adrx : _GEN_1771; // @[Fifo4.scala 160:30 161:25]
+  wire [31:0] _GEN_1786 = iactive[2] ? io_in_bits_2_bits_addr : _GEN_1772; // @[Fifo4.scala 160:30 161:25]
+  wire  _GEN_1787 = iactive[1] ? io_in_bits_1_bits_suncd : _GEN_1773; // @[Fifo4.scala 158:30 159:25]
+  wire  _GEN_1788 = iactive[1] ? io_in_bits_1_bits_vldst : _GEN_1774; // @[Fifo4.scala 158:30 159:25]
+  wire  _GEN_1789 = iactive[1] ? io_in_bits_1_bits_sldst : _GEN_1775; // @[Fifo4.scala 158:30 159:25]
+  wire  _GEN_1790 = iactive[1] ? io_in_bits_1_bits_flushall : _GEN_1776; // @[Fifo4.scala 158:30 159:25]
+  wire  _GEN_1791 = iactive[1] ? io_in_bits_1_bits_flushat : _GEN_1777; // @[Fifo4.scala 158:30 159:25]
+  wire  _GEN_1792 = iactive[1] ? io_in_bits_1_bits_fencei : _GEN_1778; // @[Fifo4.scala 158:30 159:25]
+  wire  _GEN_1793 = iactive[1] ? io_in_bits_1_bits_iload : _GEN_1779; // @[Fifo4.scala 158:30 159:25]
+  wire  _GEN_1794 = iactive[1] ? io_in_bits_1_bits_sext : _GEN_1780; // @[Fifo4.scala 158:30 159:25]
+  wire  _GEN_1795 = iactive[1] ? io_in_bits_1_bits_write : _GEN_1781; // @[Fifo4.scala 158:30 159:25]
+  wire [5:0] _GEN_1796 = iactive[1] ? io_in_bits_1_bits_size : _GEN_1782; // @[Fifo4.scala 158:30 159:25]
+  wire [4:0] _GEN_1797 = iactive[1] ? io_in_bits_1_bits_index : _GEN_1783; // @[Fifo4.scala 158:30 159:25]
+  wire [31:0] _GEN_1798 = iactive[1] ? io_in_bits_1_bits_data : _GEN_1784; // @[Fifo4.scala 158:30 159:25]
+  wire [31:0] _GEN_1799 = iactive[1] ? io_in_bits_1_bits_adrx : _GEN_1785; // @[Fifo4.scala 158:30 159:25]
+  wire [31:0] _GEN_1800 = iactive[1] ? io_in_bits_1_bits_addr : _GEN_1786; // @[Fifo4.scala 158:30 159:25]
+  wire  _GEN_1801 = iactive[0] ? io_in_bits_0_bits_suncd : _GEN_1787; // @[Fifo4.scala 156:23 157:25]
+  wire  _GEN_1802 = iactive[0] ? io_in_bits_0_bits_vldst : _GEN_1788; // @[Fifo4.scala 156:23 157:25]
+  wire  _GEN_1803 = iactive[0] ? io_in_bits_0_bits_sldst : _GEN_1789; // @[Fifo4.scala 156:23 157:25]
+  wire  _GEN_1804 = iactive[0] ? io_in_bits_0_bits_flushall : _GEN_1790; // @[Fifo4.scala 156:23 157:25]
+  wire  _GEN_1805 = iactive[0] ? io_in_bits_0_bits_flushat : _GEN_1791; // @[Fifo4.scala 156:23 157:25]
+  wire  _GEN_1806 = iactive[0] ? io_in_bits_0_bits_fencei : _GEN_1792; // @[Fifo4.scala 156:23 157:25]
+  wire  _GEN_1807 = iactive[0] ? io_in_bits_0_bits_iload : _GEN_1793; // @[Fifo4.scala 156:23 157:25]
+  wire  _GEN_1808 = iactive[0] ? io_in_bits_0_bits_sext : _GEN_1794; // @[Fifo4.scala 156:23 157:25]
+  wire  _GEN_1809 = iactive[0] ? io_in_bits_0_bits_write : _GEN_1795; // @[Fifo4.scala 156:23 157:25]
+  wire [5:0] _GEN_1810 = iactive[0] ? io_in_bits_0_bits_size : _GEN_1796; // @[Fifo4.scala 156:23 157:25]
+  wire [4:0] _GEN_1811 = iactive[0] ? io_in_bits_0_bits_index : _GEN_1797; // @[Fifo4.scala 156:23 157:25]
+  wire [31:0] _GEN_1812 = iactive[0] ? io_in_bits_0_bits_data : _GEN_1798; // @[Fifo4.scala 156:23 157:25]
+  wire [31:0] _GEN_1813 = iactive[0] ? io_in_bits_0_bits_adrx : _GEN_1799; // @[Fifo4.scala 156:23 157:25]
+  wire [31:0] _GEN_1814 = iactive[0] ? io_in_bits_0_bits_addr : _GEN_1800; // @[Fifo4.scala 156:23 157:25]
+  wire  _GEN_1815 = ivalid ? _GEN_1801 : io_in_bits_0_bits_suncd; // @[Fifo4.scala 140:21 154:24]
+  wire  _GEN_1816 = ivalid ? _GEN_1802 : io_in_bits_0_bits_vldst; // @[Fifo4.scala 140:21 154:24]
+  wire  _GEN_1817 = ivalid ? _GEN_1803 : io_in_bits_0_bits_sldst; // @[Fifo4.scala 140:21 154:24]
+  wire  _GEN_1818 = ivalid ? _GEN_1804 : io_in_bits_0_bits_flushall; // @[Fifo4.scala 140:21 154:24]
+  wire  _GEN_1819 = ivalid ? _GEN_1805 : io_in_bits_0_bits_flushat; // @[Fifo4.scala 140:21 154:24]
+  wire  _GEN_1820 = ivalid ? _GEN_1806 : io_in_bits_0_bits_fencei; // @[Fifo4.scala 140:21 154:24]
+  wire  _GEN_1821 = ivalid ? _GEN_1807 : io_in_bits_0_bits_iload; // @[Fifo4.scala 140:21 154:24]
+  wire  _GEN_1822 = ivalid ? _GEN_1808 : io_in_bits_0_bits_sext; // @[Fifo4.scala 140:21 154:24]
+  wire  _GEN_1823 = ivalid ? _GEN_1809 : io_in_bits_0_bits_write; // @[Fifo4.scala 140:21 154:24]
+  wire [5:0] _GEN_1824 = ivalid ? _GEN_1810 : io_in_bits_0_bits_size; // @[Fifo4.scala 140:21 154:24]
+  wire [4:0] _GEN_1825 = ivalid ? _GEN_1811 : io_in_bits_0_bits_index; // @[Fifo4.scala 140:21 154:24]
+  wire [31:0] _GEN_1826 = ivalid ? _GEN_1812 : io_in_bits_0_bits_data; // @[Fifo4.scala 140:21 154:24]
+  wire [31:0] _GEN_1827 = ivalid ? _GEN_1813 : io_in_bits_0_bits_adrx; // @[Fifo4.scala 140:21 154:24]
+  wire [31:0] _GEN_1828 = ivalid ? _GEN_1814 : io_in_bits_0_bits_addr; // @[Fifo4.scala 140:21 154:24]
   wire [2:0] _io_in_ready_T_1 = 3'h7 - icount; // @[Fifo4.scala 181:33]
-  wire [3:0] _GEN_1957 = {{1'd0}, _io_in_ready_T_1}; // @[Fifo4.scala 181:25]
+  wire [3:0] _GEN_1853 = {{1'd0}, _io_in_ready_T_1}; // @[Fifo4.scala 181:25]
   Slice_1 mslice ( // @[Slice.scala 9:11]
     .clock(mslice_clock),
     .reset(mslice_reset),
@@ -17427,7 +16068,6 @@
     .io_in_bits_size(mslice_io_in_bits_size),
     .io_in_bits_write(mslice_io_in_bits_write),
     .io_in_bits_sext(mslice_io_in_bits_sext),
-    .io_in_bits_fload(mslice_io_in_bits_fload),
     .io_in_bits_iload(mslice_io_in_bits_iload),
     .io_in_bits_fencei(mslice_io_in_bits_fencei),
     .io_in_bits_flushat(mslice_io_in_bits_flushat),
@@ -17444,7 +16084,6 @@
     .io_out_bits_size(mslice_io_out_bits_size),
     .io_out_bits_write(mslice_io_out_bits_write),
     .io_out_bits_sext(mslice_io_out_bits_sext),
-    .io_out_bits_fload(mslice_io_out_bits_fload),
     .io_out_bits_iload(mslice_io_out_bits_iload),
     .io_out_bits_fencei(mslice_io_out_bits_fencei),
     .io_out_bits_flushat(mslice_io_out_bits_flushat),
@@ -17468,15 +16107,15 @@
   assign mem_addr_MPORT_1_data = io_in_bits_1_bits_addr;
   assign mem_addr_MPORT_1_addr = 3'h0;
   assign mem_addr_MPORT_1_mask = 1'h1;
-  assign mem_addr_MPORT_1_en = ivalid & _GEN_141;
+  assign mem_addr_MPORT_1_en = ivalid & _GEN_134;
   assign mem_addr_MPORT_2_data = io_in_bits_2_bits_addr;
   assign mem_addr_MPORT_2_addr = 3'h0;
   assign mem_addr_MPORT_2_mask = 1'h1;
-  assign mem_addr_MPORT_2_en = ivalid & _GEN_160;
+  assign mem_addr_MPORT_2_en = ivalid & _GEN_152;
   assign mem_addr_MPORT_3_data = io_in_bits_3_bits_addr;
   assign mem_addr_MPORT_3_addr = 3'h0;
   assign mem_addr_MPORT_3_mask = 1'h1;
-  assign mem_addr_MPORT_3_en = ivalid & _GEN_179;
+  assign mem_addr_MPORT_3_en = ivalid & _GEN_170;
   assign mem_addr_MPORT_4_data = io_in_bits_0_bits_addr;
   assign mem_addr_MPORT_4_addr = 3'h1;
   assign mem_addr_MPORT_4_mask = 1'h1;
@@ -17484,15 +16123,15 @@
   assign mem_addr_MPORT_5_data = io_in_bits_1_bits_addr;
   assign mem_addr_MPORT_5_addr = 3'h1;
   assign mem_addr_MPORT_5_mask = 1'h1;
-  assign mem_addr_MPORT_5_en = ivalid & _GEN_400;
+  assign mem_addr_MPORT_5_en = ivalid & _GEN_379;
   assign mem_addr_MPORT_6_data = io_in_bits_2_bits_addr;
   assign mem_addr_MPORT_6_addr = 3'h1;
   assign mem_addr_MPORT_6_mask = 1'h1;
-  assign mem_addr_MPORT_6_en = ivalid & _GEN_418;
+  assign mem_addr_MPORT_6_en = ivalid & _GEN_396;
   assign mem_addr_MPORT_7_data = io_in_bits_3_bits_addr;
   assign mem_addr_MPORT_7_addr = 3'h1;
   assign mem_addr_MPORT_7_mask = 1'h1;
-  assign mem_addr_MPORT_7_en = ivalid & _GEN_436;
+  assign mem_addr_MPORT_7_en = ivalid & _GEN_413;
   assign mem_addr_MPORT_8_data = io_in_bits_0_bits_addr;
   assign mem_addr_MPORT_8_addr = 3'h2;
   assign mem_addr_MPORT_8_mask = 1'h1;
@@ -17500,15 +16139,15 @@
   assign mem_addr_MPORT_9_data = io_in_bits_1_bits_addr;
   assign mem_addr_MPORT_9_addr = 3'h2;
   assign mem_addr_MPORT_9_mask = 1'h1;
-  assign mem_addr_MPORT_9_en = ivalid & _GEN_659;
+  assign mem_addr_MPORT_9_en = ivalid & _GEN_624;
   assign mem_addr_MPORT_10_data = io_in_bits_2_bits_addr;
   assign mem_addr_MPORT_10_addr = 3'h2;
   assign mem_addr_MPORT_10_mask = 1'h1;
-  assign mem_addr_MPORT_10_en = ivalid & _GEN_678;
+  assign mem_addr_MPORT_10_en = ivalid & _GEN_642;
   assign mem_addr_MPORT_11_data = io_in_bits_3_bits_addr;
   assign mem_addr_MPORT_11_addr = 3'h2;
   assign mem_addr_MPORT_11_mask = 1'h1;
-  assign mem_addr_MPORT_11_en = ivalid & _GEN_697;
+  assign mem_addr_MPORT_11_en = ivalid & _GEN_660;
   assign mem_addr_MPORT_12_data = io_in_bits_0_bits_addr;
   assign mem_addr_MPORT_12_addr = 3'h3;
   assign mem_addr_MPORT_12_mask = 1'h1;
@@ -17516,15 +16155,15 @@
   assign mem_addr_MPORT_13_data = io_in_bits_1_bits_addr;
   assign mem_addr_MPORT_13_addr = 3'h3;
   assign mem_addr_MPORT_13_mask = 1'h1;
-  assign mem_addr_MPORT_13_en = ivalid & _GEN_925;
+  assign mem_addr_MPORT_13_en = ivalid & _GEN_876;
   assign mem_addr_MPORT_14_data = io_in_bits_2_bits_addr;
   assign mem_addr_MPORT_14_addr = 3'h3;
   assign mem_addr_MPORT_14_mask = 1'h1;
-  assign mem_addr_MPORT_14_en = ivalid & _GEN_944;
+  assign mem_addr_MPORT_14_en = ivalid & _GEN_894;
   assign mem_addr_MPORT_15_data = io_in_bits_3_bits_addr;
   assign mem_addr_MPORT_15_addr = 3'h3;
   assign mem_addr_MPORT_15_mask = 1'h1;
-  assign mem_addr_MPORT_15_en = ivalid & _GEN_963;
+  assign mem_addr_MPORT_15_en = ivalid & _GEN_912;
   assign mem_addr_MPORT_16_data = io_in_bits_0_bits_addr;
   assign mem_addr_MPORT_16_addr = 3'h4;
   assign mem_addr_MPORT_16_mask = 1'h1;
@@ -17532,15 +16171,15 @@
   assign mem_addr_MPORT_17_data = io_in_bits_1_bits_addr;
   assign mem_addr_MPORT_17_addr = 3'h4;
   assign mem_addr_MPORT_17_mask = 1'h1;
-  assign mem_addr_MPORT_17_en = ivalid & _GEN_1191;
+  assign mem_addr_MPORT_17_en = ivalid & _GEN_1128;
   assign mem_addr_MPORT_18_data = io_in_bits_2_bits_addr;
   assign mem_addr_MPORT_18_addr = 3'h4;
   assign mem_addr_MPORT_18_mask = 1'h1;
-  assign mem_addr_MPORT_18_en = ivalid & _GEN_1210;
+  assign mem_addr_MPORT_18_en = ivalid & _GEN_1146;
   assign mem_addr_MPORT_19_data = io_in_bits_3_bits_addr;
   assign mem_addr_MPORT_19_addr = 3'h4;
   assign mem_addr_MPORT_19_mask = 1'h1;
-  assign mem_addr_MPORT_19_en = ivalid & _GEN_1229;
+  assign mem_addr_MPORT_19_en = ivalid & _GEN_1164;
   assign mem_addr_MPORT_20_data = io_in_bits_0_bits_addr;
   assign mem_addr_MPORT_20_addr = 3'h5;
   assign mem_addr_MPORT_20_mask = 1'h1;
@@ -17548,15 +16187,15 @@
   assign mem_addr_MPORT_21_data = io_in_bits_1_bits_addr;
   assign mem_addr_MPORT_21_addr = 3'h5;
   assign mem_addr_MPORT_21_mask = 1'h1;
-  assign mem_addr_MPORT_21_en = ivalid & _GEN_1457;
+  assign mem_addr_MPORT_21_en = ivalid & _GEN_1380;
   assign mem_addr_MPORT_22_data = io_in_bits_2_bits_addr;
   assign mem_addr_MPORT_22_addr = 3'h5;
   assign mem_addr_MPORT_22_mask = 1'h1;
-  assign mem_addr_MPORT_22_en = ivalid & _GEN_1476;
+  assign mem_addr_MPORT_22_en = ivalid & _GEN_1398;
   assign mem_addr_MPORT_23_data = io_in_bits_3_bits_addr;
   assign mem_addr_MPORT_23_addr = 3'h5;
   assign mem_addr_MPORT_23_mask = 1'h1;
-  assign mem_addr_MPORT_23_en = ivalid & _GEN_1495;
+  assign mem_addr_MPORT_23_en = ivalid & _GEN_1416;
   assign mem_addr_MPORT_24_data = io_in_bits_0_bits_addr;
   assign mem_addr_MPORT_24_addr = 3'h6;
   assign mem_addr_MPORT_24_mask = 1'h1;
@@ -17564,15 +16203,15 @@
   assign mem_addr_MPORT_25_data = io_in_bits_1_bits_addr;
   assign mem_addr_MPORT_25_addr = 3'h6;
   assign mem_addr_MPORT_25_mask = 1'h1;
-  assign mem_addr_MPORT_25_en = ivalid & _GEN_1723;
+  assign mem_addr_MPORT_25_en = ivalid & _GEN_1632;
   assign mem_addr_MPORT_26_data = io_in_bits_2_bits_addr;
   assign mem_addr_MPORT_26_addr = 3'h6;
   assign mem_addr_MPORT_26_mask = 1'h1;
-  assign mem_addr_MPORT_26_en = ivalid & _GEN_1742;
+  assign mem_addr_MPORT_26_en = ivalid & _GEN_1650;
   assign mem_addr_MPORT_27_data = io_in_bits_3_bits_addr;
   assign mem_addr_MPORT_27_addr = 3'h6;
   assign mem_addr_MPORT_27_mask = 1'h1;
-  assign mem_addr_MPORT_27_en = ivalid & _GEN_1761;
+  assign mem_addr_MPORT_27_en = ivalid & _GEN_1668;
   assign mem_adrx_mslice_io_in_bits_MPORT_en = mcount > 4'h0;
   assign mem_adrx_mslice_io_in_bits_MPORT_addr = outpos;
   `ifndef RANDOMIZE_GARBAGE_ASSIGN
@@ -17588,15 +16227,15 @@
   assign mem_adrx_MPORT_1_data = io_in_bits_1_bits_adrx;
   assign mem_adrx_MPORT_1_addr = 3'h0;
   assign mem_adrx_MPORT_1_mask = 1'h1;
-  assign mem_adrx_MPORT_1_en = ivalid & _GEN_141;
+  assign mem_adrx_MPORT_1_en = ivalid & _GEN_134;
   assign mem_adrx_MPORT_2_data = io_in_bits_2_bits_adrx;
   assign mem_adrx_MPORT_2_addr = 3'h0;
   assign mem_adrx_MPORT_2_mask = 1'h1;
-  assign mem_adrx_MPORT_2_en = ivalid & _GEN_160;
+  assign mem_adrx_MPORT_2_en = ivalid & _GEN_152;
   assign mem_adrx_MPORT_3_data = io_in_bits_3_bits_adrx;
   assign mem_adrx_MPORT_3_addr = 3'h0;
   assign mem_adrx_MPORT_3_mask = 1'h1;
-  assign mem_adrx_MPORT_3_en = ivalid & _GEN_179;
+  assign mem_adrx_MPORT_3_en = ivalid & _GEN_170;
   assign mem_adrx_MPORT_4_data = io_in_bits_0_bits_adrx;
   assign mem_adrx_MPORT_4_addr = 3'h1;
   assign mem_adrx_MPORT_4_mask = 1'h1;
@@ -17604,15 +16243,15 @@
   assign mem_adrx_MPORT_5_data = io_in_bits_1_bits_adrx;
   assign mem_adrx_MPORT_5_addr = 3'h1;
   assign mem_adrx_MPORT_5_mask = 1'h1;
-  assign mem_adrx_MPORT_5_en = ivalid & _GEN_400;
+  assign mem_adrx_MPORT_5_en = ivalid & _GEN_379;
   assign mem_adrx_MPORT_6_data = io_in_bits_2_bits_adrx;
   assign mem_adrx_MPORT_6_addr = 3'h1;
   assign mem_adrx_MPORT_6_mask = 1'h1;
-  assign mem_adrx_MPORT_6_en = ivalid & _GEN_418;
+  assign mem_adrx_MPORT_6_en = ivalid & _GEN_396;
   assign mem_adrx_MPORT_7_data = io_in_bits_3_bits_adrx;
   assign mem_adrx_MPORT_7_addr = 3'h1;
   assign mem_adrx_MPORT_7_mask = 1'h1;
-  assign mem_adrx_MPORT_7_en = ivalid & _GEN_436;
+  assign mem_adrx_MPORT_7_en = ivalid & _GEN_413;
   assign mem_adrx_MPORT_8_data = io_in_bits_0_bits_adrx;
   assign mem_adrx_MPORT_8_addr = 3'h2;
   assign mem_adrx_MPORT_8_mask = 1'h1;
@@ -17620,15 +16259,15 @@
   assign mem_adrx_MPORT_9_data = io_in_bits_1_bits_adrx;
   assign mem_adrx_MPORT_9_addr = 3'h2;
   assign mem_adrx_MPORT_9_mask = 1'h1;
-  assign mem_adrx_MPORT_9_en = ivalid & _GEN_659;
+  assign mem_adrx_MPORT_9_en = ivalid & _GEN_624;
   assign mem_adrx_MPORT_10_data = io_in_bits_2_bits_adrx;
   assign mem_adrx_MPORT_10_addr = 3'h2;
   assign mem_adrx_MPORT_10_mask = 1'h1;
-  assign mem_adrx_MPORT_10_en = ivalid & _GEN_678;
+  assign mem_adrx_MPORT_10_en = ivalid & _GEN_642;
   assign mem_adrx_MPORT_11_data = io_in_bits_3_bits_adrx;
   assign mem_adrx_MPORT_11_addr = 3'h2;
   assign mem_adrx_MPORT_11_mask = 1'h1;
-  assign mem_adrx_MPORT_11_en = ivalid & _GEN_697;
+  assign mem_adrx_MPORT_11_en = ivalid & _GEN_660;
   assign mem_adrx_MPORT_12_data = io_in_bits_0_bits_adrx;
   assign mem_adrx_MPORT_12_addr = 3'h3;
   assign mem_adrx_MPORT_12_mask = 1'h1;
@@ -17636,15 +16275,15 @@
   assign mem_adrx_MPORT_13_data = io_in_bits_1_bits_adrx;
   assign mem_adrx_MPORT_13_addr = 3'h3;
   assign mem_adrx_MPORT_13_mask = 1'h1;
-  assign mem_adrx_MPORT_13_en = ivalid & _GEN_925;
+  assign mem_adrx_MPORT_13_en = ivalid & _GEN_876;
   assign mem_adrx_MPORT_14_data = io_in_bits_2_bits_adrx;
   assign mem_adrx_MPORT_14_addr = 3'h3;
   assign mem_adrx_MPORT_14_mask = 1'h1;
-  assign mem_adrx_MPORT_14_en = ivalid & _GEN_944;
+  assign mem_adrx_MPORT_14_en = ivalid & _GEN_894;
   assign mem_adrx_MPORT_15_data = io_in_bits_3_bits_adrx;
   assign mem_adrx_MPORT_15_addr = 3'h3;
   assign mem_adrx_MPORT_15_mask = 1'h1;
-  assign mem_adrx_MPORT_15_en = ivalid & _GEN_963;
+  assign mem_adrx_MPORT_15_en = ivalid & _GEN_912;
   assign mem_adrx_MPORT_16_data = io_in_bits_0_bits_adrx;
   assign mem_adrx_MPORT_16_addr = 3'h4;
   assign mem_adrx_MPORT_16_mask = 1'h1;
@@ -17652,15 +16291,15 @@
   assign mem_adrx_MPORT_17_data = io_in_bits_1_bits_adrx;
   assign mem_adrx_MPORT_17_addr = 3'h4;
   assign mem_adrx_MPORT_17_mask = 1'h1;
-  assign mem_adrx_MPORT_17_en = ivalid & _GEN_1191;
+  assign mem_adrx_MPORT_17_en = ivalid & _GEN_1128;
   assign mem_adrx_MPORT_18_data = io_in_bits_2_bits_adrx;
   assign mem_adrx_MPORT_18_addr = 3'h4;
   assign mem_adrx_MPORT_18_mask = 1'h1;
-  assign mem_adrx_MPORT_18_en = ivalid & _GEN_1210;
+  assign mem_adrx_MPORT_18_en = ivalid & _GEN_1146;
   assign mem_adrx_MPORT_19_data = io_in_bits_3_bits_adrx;
   assign mem_adrx_MPORT_19_addr = 3'h4;
   assign mem_adrx_MPORT_19_mask = 1'h1;
-  assign mem_adrx_MPORT_19_en = ivalid & _GEN_1229;
+  assign mem_adrx_MPORT_19_en = ivalid & _GEN_1164;
   assign mem_adrx_MPORT_20_data = io_in_bits_0_bits_adrx;
   assign mem_adrx_MPORT_20_addr = 3'h5;
   assign mem_adrx_MPORT_20_mask = 1'h1;
@@ -17668,15 +16307,15 @@
   assign mem_adrx_MPORT_21_data = io_in_bits_1_bits_adrx;
   assign mem_adrx_MPORT_21_addr = 3'h5;
   assign mem_adrx_MPORT_21_mask = 1'h1;
-  assign mem_adrx_MPORT_21_en = ivalid & _GEN_1457;
+  assign mem_adrx_MPORT_21_en = ivalid & _GEN_1380;
   assign mem_adrx_MPORT_22_data = io_in_bits_2_bits_adrx;
   assign mem_adrx_MPORT_22_addr = 3'h5;
   assign mem_adrx_MPORT_22_mask = 1'h1;
-  assign mem_adrx_MPORT_22_en = ivalid & _GEN_1476;
+  assign mem_adrx_MPORT_22_en = ivalid & _GEN_1398;
   assign mem_adrx_MPORT_23_data = io_in_bits_3_bits_adrx;
   assign mem_adrx_MPORT_23_addr = 3'h5;
   assign mem_adrx_MPORT_23_mask = 1'h1;
-  assign mem_adrx_MPORT_23_en = ivalid & _GEN_1495;
+  assign mem_adrx_MPORT_23_en = ivalid & _GEN_1416;
   assign mem_adrx_MPORT_24_data = io_in_bits_0_bits_adrx;
   assign mem_adrx_MPORT_24_addr = 3'h6;
   assign mem_adrx_MPORT_24_mask = 1'h1;
@@ -17684,15 +16323,15 @@
   assign mem_adrx_MPORT_25_data = io_in_bits_1_bits_adrx;
   assign mem_adrx_MPORT_25_addr = 3'h6;
   assign mem_adrx_MPORT_25_mask = 1'h1;
-  assign mem_adrx_MPORT_25_en = ivalid & _GEN_1723;
+  assign mem_adrx_MPORT_25_en = ivalid & _GEN_1632;
   assign mem_adrx_MPORT_26_data = io_in_bits_2_bits_adrx;
   assign mem_adrx_MPORT_26_addr = 3'h6;
   assign mem_adrx_MPORT_26_mask = 1'h1;
-  assign mem_adrx_MPORT_26_en = ivalid & _GEN_1742;
+  assign mem_adrx_MPORT_26_en = ivalid & _GEN_1650;
   assign mem_adrx_MPORT_27_data = io_in_bits_3_bits_adrx;
   assign mem_adrx_MPORT_27_addr = 3'h6;
   assign mem_adrx_MPORT_27_mask = 1'h1;
-  assign mem_adrx_MPORT_27_en = ivalid & _GEN_1761;
+  assign mem_adrx_MPORT_27_en = ivalid & _GEN_1668;
   assign mem_data_mslice_io_in_bits_MPORT_en = mcount > 4'h0;
   assign mem_data_mslice_io_in_bits_MPORT_addr = outpos;
   `ifndef RANDOMIZE_GARBAGE_ASSIGN
@@ -17708,15 +16347,15 @@
   assign mem_data_MPORT_1_data = io_in_bits_1_bits_data;
   assign mem_data_MPORT_1_addr = 3'h0;
   assign mem_data_MPORT_1_mask = 1'h1;
-  assign mem_data_MPORT_1_en = ivalid & _GEN_141;
+  assign mem_data_MPORT_1_en = ivalid & _GEN_134;
   assign mem_data_MPORT_2_data = io_in_bits_2_bits_data;
   assign mem_data_MPORT_2_addr = 3'h0;
   assign mem_data_MPORT_2_mask = 1'h1;
-  assign mem_data_MPORT_2_en = ivalid & _GEN_160;
+  assign mem_data_MPORT_2_en = ivalid & _GEN_152;
   assign mem_data_MPORT_3_data = io_in_bits_3_bits_data;
   assign mem_data_MPORT_3_addr = 3'h0;
   assign mem_data_MPORT_3_mask = 1'h1;
-  assign mem_data_MPORT_3_en = ivalid & _GEN_179;
+  assign mem_data_MPORT_3_en = ivalid & _GEN_170;
   assign mem_data_MPORT_4_data = io_in_bits_0_bits_data;
   assign mem_data_MPORT_4_addr = 3'h1;
   assign mem_data_MPORT_4_mask = 1'h1;
@@ -17724,15 +16363,15 @@
   assign mem_data_MPORT_5_data = io_in_bits_1_bits_data;
   assign mem_data_MPORT_5_addr = 3'h1;
   assign mem_data_MPORT_5_mask = 1'h1;
-  assign mem_data_MPORT_5_en = ivalid & _GEN_400;
+  assign mem_data_MPORT_5_en = ivalid & _GEN_379;
   assign mem_data_MPORT_6_data = io_in_bits_2_bits_data;
   assign mem_data_MPORT_6_addr = 3'h1;
   assign mem_data_MPORT_6_mask = 1'h1;
-  assign mem_data_MPORT_6_en = ivalid & _GEN_418;
+  assign mem_data_MPORT_6_en = ivalid & _GEN_396;
   assign mem_data_MPORT_7_data = io_in_bits_3_bits_data;
   assign mem_data_MPORT_7_addr = 3'h1;
   assign mem_data_MPORT_7_mask = 1'h1;
-  assign mem_data_MPORT_7_en = ivalid & _GEN_436;
+  assign mem_data_MPORT_7_en = ivalid & _GEN_413;
   assign mem_data_MPORT_8_data = io_in_bits_0_bits_data;
   assign mem_data_MPORT_8_addr = 3'h2;
   assign mem_data_MPORT_8_mask = 1'h1;
@@ -17740,15 +16379,15 @@
   assign mem_data_MPORT_9_data = io_in_bits_1_bits_data;
   assign mem_data_MPORT_9_addr = 3'h2;
   assign mem_data_MPORT_9_mask = 1'h1;
-  assign mem_data_MPORT_9_en = ivalid & _GEN_659;
+  assign mem_data_MPORT_9_en = ivalid & _GEN_624;
   assign mem_data_MPORT_10_data = io_in_bits_2_bits_data;
   assign mem_data_MPORT_10_addr = 3'h2;
   assign mem_data_MPORT_10_mask = 1'h1;
-  assign mem_data_MPORT_10_en = ivalid & _GEN_678;
+  assign mem_data_MPORT_10_en = ivalid & _GEN_642;
   assign mem_data_MPORT_11_data = io_in_bits_3_bits_data;
   assign mem_data_MPORT_11_addr = 3'h2;
   assign mem_data_MPORT_11_mask = 1'h1;
-  assign mem_data_MPORT_11_en = ivalid & _GEN_697;
+  assign mem_data_MPORT_11_en = ivalid & _GEN_660;
   assign mem_data_MPORT_12_data = io_in_bits_0_bits_data;
   assign mem_data_MPORT_12_addr = 3'h3;
   assign mem_data_MPORT_12_mask = 1'h1;
@@ -17756,15 +16395,15 @@
   assign mem_data_MPORT_13_data = io_in_bits_1_bits_data;
   assign mem_data_MPORT_13_addr = 3'h3;
   assign mem_data_MPORT_13_mask = 1'h1;
-  assign mem_data_MPORT_13_en = ivalid & _GEN_925;
+  assign mem_data_MPORT_13_en = ivalid & _GEN_876;
   assign mem_data_MPORT_14_data = io_in_bits_2_bits_data;
   assign mem_data_MPORT_14_addr = 3'h3;
   assign mem_data_MPORT_14_mask = 1'h1;
-  assign mem_data_MPORT_14_en = ivalid & _GEN_944;
+  assign mem_data_MPORT_14_en = ivalid & _GEN_894;
   assign mem_data_MPORT_15_data = io_in_bits_3_bits_data;
   assign mem_data_MPORT_15_addr = 3'h3;
   assign mem_data_MPORT_15_mask = 1'h1;
-  assign mem_data_MPORT_15_en = ivalid & _GEN_963;
+  assign mem_data_MPORT_15_en = ivalid & _GEN_912;
   assign mem_data_MPORT_16_data = io_in_bits_0_bits_data;
   assign mem_data_MPORT_16_addr = 3'h4;
   assign mem_data_MPORT_16_mask = 1'h1;
@@ -17772,15 +16411,15 @@
   assign mem_data_MPORT_17_data = io_in_bits_1_bits_data;
   assign mem_data_MPORT_17_addr = 3'h4;
   assign mem_data_MPORT_17_mask = 1'h1;
-  assign mem_data_MPORT_17_en = ivalid & _GEN_1191;
+  assign mem_data_MPORT_17_en = ivalid & _GEN_1128;
   assign mem_data_MPORT_18_data = io_in_bits_2_bits_data;
   assign mem_data_MPORT_18_addr = 3'h4;
   assign mem_data_MPORT_18_mask = 1'h1;
-  assign mem_data_MPORT_18_en = ivalid & _GEN_1210;
+  assign mem_data_MPORT_18_en = ivalid & _GEN_1146;
   assign mem_data_MPORT_19_data = io_in_bits_3_bits_data;
   assign mem_data_MPORT_19_addr = 3'h4;
   assign mem_data_MPORT_19_mask = 1'h1;
-  assign mem_data_MPORT_19_en = ivalid & _GEN_1229;
+  assign mem_data_MPORT_19_en = ivalid & _GEN_1164;
   assign mem_data_MPORT_20_data = io_in_bits_0_bits_data;
   assign mem_data_MPORT_20_addr = 3'h5;
   assign mem_data_MPORT_20_mask = 1'h1;
@@ -17788,15 +16427,15 @@
   assign mem_data_MPORT_21_data = io_in_bits_1_bits_data;
   assign mem_data_MPORT_21_addr = 3'h5;
   assign mem_data_MPORT_21_mask = 1'h1;
-  assign mem_data_MPORT_21_en = ivalid & _GEN_1457;
+  assign mem_data_MPORT_21_en = ivalid & _GEN_1380;
   assign mem_data_MPORT_22_data = io_in_bits_2_bits_data;
   assign mem_data_MPORT_22_addr = 3'h5;
   assign mem_data_MPORT_22_mask = 1'h1;
-  assign mem_data_MPORT_22_en = ivalid & _GEN_1476;
+  assign mem_data_MPORT_22_en = ivalid & _GEN_1398;
   assign mem_data_MPORT_23_data = io_in_bits_3_bits_data;
   assign mem_data_MPORT_23_addr = 3'h5;
   assign mem_data_MPORT_23_mask = 1'h1;
-  assign mem_data_MPORT_23_en = ivalid & _GEN_1495;
+  assign mem_data_MPORT_23_en = ivalid & _GEN_1416;
   assign mem_data_MPORT_24_data = io_in_bits_0_bits_data;
   assign mem_data_MPORT_24_addr = 3'h6;
   assign mem_data_MPORT_24_mask = 1'h1;
@@ -17804,15 +16443,15 @@
   assign mem_data_MPORT_25_data = io_in_bits_1_bits_data;
   assign mem_data_MPORT_25_addr = 3'h6;
   assign mem_data_MPORT_25_mask = 1'h1;
-  assign mem_data_MPORT_25_en = ivalid & _GEN_1723;
+  assign mem_data_MPORT_25_en = ivalid & _GEN_1632;
   assign mem_data_MPORT_26_data = io_in_bits_2_bits_data;
   assign mem_data_MPORT_26_addr = 3'h6;
   assign mem_data_MPORT_26_mask = 1'h1;
-  assign mem_data_MPORT_26_en = ivalid & _GEN_1742;
+  assign mem_data_MPORT_26_en = ivalid & _GEN_1650;
   assign mem_data_MPORT_27_data = io_in_bits_3_bits_data;
   assign mem_data_MPORT_27_addr = 3'h6;
   assign mem_data_MPORT_27_mask = 1'h1;
-  assign mem_data_MPORT_27_en = ivalid & _GEN_1761;
+  assign mem_data_MPORT_27_en = ivalid & _GEN_1668;
   assign mem_index_mslice_io_in_bits_MPORT_en = mcount > 4'h0;
   assign mem_index_mslice_io_in_bits_MPORT_addr = outpos;
   `ifndef RANDOMIZE_GARBAGE_ASSIGN
@@ -17828,15 +16467,15 @@
   assign mem_index_MPORT_1_data = io_in_bits_1_bits_index;
   assign mem_index_MPORT_1_addr = 3'h0;
   assign mem_index_MPORT_1_mask = 1'h1;
-  assign mem_index_MPORT_1_en = ivalid & _GEN_141;
+  assign mem_index_MPORT_1_en = ivalid & _GEN_134;
   assign mem_index_MPORT_2_data = io_in_bits_2_bits_index;
   assign mem_index_MPORT_2_addr = 3'h0;
   assign mem_index_MPORT_2_mask = 1'h1;
-  assign mem_index_MPORT_2_en = ivalid & _GEN_160;
+  assign mem_index_MPORT_2_en = ivalid & _GEN_152;
   assign mem_index_MPORT_3_data = io_in_bits_3_bits_index;
   assign mem_index_MPORT_3_addr = 3'h0;
   assign mem_index_MPORT_3_mask = 1'h1;
-  assign mem_index_MPORT_3_en = ivalid & _GEN_179;
+  assign mem_index_MPORT_3_en = ivalid & _GEN_170;
   assign mem_index_MPORT_4_data = io_in_bits_0_bits_index;
   assign mem_index_MPORT_4_addr = 3'h1;
   assign mem_index_MPORT_4_mask = 1'h1;
@@ -17844,15 +16483,15 @@
   assign mem_index_MPORT_5_data = io_in_bits_1_bits_index;
   assign mem_index_MPORT_5_addr = 3'h1;
   assign mem_index_MPORT_5_mask = 1'h1;
-  assign mem_index_MPORT_5_en = ivalid & _GEN_400;
+  assign mem_index_MPORT_5_en = ivalid & _GEN_379;
   assign mem_index_MPORT_6_data = io_in_bits_2_bits_index;
   assign mem_index_MPORT_6_addr = 3'h1;
   assign mem_index_MPORT_6_mask = 1'h1;
-  assign mem_index_MPORT_6_en = ivalid & _GEN_418;
+  assign mem_index_MPORT_6_en = ivalid & _GEN_396;
   assign mem_index_MPORT_7_data = io_in_bits_3_bits_index;
   assign mem_index_MPORT_7_addr = 3'h1;
   assign mem_index_MPORT_7_mask = 1'h1;
-  assign mem_index_MPORT_7_en = ivalid & _GEN_436;
+  assign mem_index_MPORT_7_en = ivalid & _GEN_413;
   assign mem_index_MPORT_8_data = io_in_bits_0_bits_index;
   assign mem_index_MPORT_8_addr = 3'h2;
   assign mem_index_MPORT_8_mask = 1'h1;
@@ -17860,15 +16499,15 @@
   assign mem_index_MPORT_9_data = io_in_bits_1_bits_index;
   assign mem_index_MPORT_9_addr = 3'h2;
   assign mem_index_MPORT_9_mask = 1'h1;
-  assign mem_index_MPORT_9_en = ivalid & _GEN_659;
+  assign mem_index_MPORT_9_en = ivalid & _GEN_624;
   assign mem_index_MPORT_10_data = io_in_bits_2_bits_index;
   assign mem_index_MPORT_10_addr = 3'h2;
   assign mem_index_MPORT_10_mask = 1'h1;
-  assign mem_index_MPORT_10_en = ivalid & _GEN_678;
+  assign mem_index_MPORT_10_en = ivalid & _GEN_642;
   assign mem_index_MPORT_11_data = io_in_bits_3_bits_index;
   assign mem_index_MPORT_11_addr = 3'h2;
   assign mem_index_MPORT_11_mask = 1'h1;
-  assign mem_index_MPORT_11_en = ivalid & _GEN_697;
+  assign mem_index_MPORT_11_en = ivalid & _GEN_660;
   assign mem_index_MPORT_12_data = io_in_bits_0_bits_index;
   assign mem_index_MPORT_12_addr = 3'h3;
   assign mem_index_MPORT_12_mask = 1'h1;
@@ -17876,15 +16515,15 @@
   assign mem_index_MPORT_13_data = io_in_bits_1_bits_index;
   assign mem_index_MPORT_13_addr = 3'h3;
   assign mem_index_MPORT_13_mask = 1'h1;
-  assign mem_index_MPORT_13_en = ivalid & _GEN_925;
+  assign mem_index_MPORT_13_en = ivalid & _GEN_876;
   assign mem_index_MPORT_14_data = io_in_bits_2_bits_index;
   assign mem_index_MPORT_14_addr = 3'h3;
   assign mem_index_MPORT_14_mask = 1'h1;
-  assign mem_index_MPORT_14_en = ivalid & _GEN_944;
+  assign mem_index_MPORT_14_en = ivalid & _GEN_894;
   assign mem_index_MPORT_15_data = io_in_bits_3_bits_index;
   assign mem_index_MPORT_15_addr = 3'h3;
   assign mem_index_MPORT_15_mask = 1'h1;
-  assign mem_index_MPORT_15_en = ivalid & _GEN_963;
+  assign mem_index_MPORT_15_en = ivalid & _GEN_912;
   assign mem_index_MPORT_16_data = io_in_bits_0_bits_index;
   assign mem_index_MPORT_16_addr = 3'h4;
   assign mem_index_MPORT_16_mask = 1'h1;
@@ -17892,15 +16531,15 @@
   assign mem_index_MPORT_17_data = io_in_bits_1_bits_index;
   assign mem_index_MPORT_17_addr = 3'h4;
   assign mem_index_MPORT_17_mask = 1'h1;
-  assign mem_index_MPORT_17_en = ivalid & _GEN_1191;
+  assign mem_index_MPORT_17_en = ivalid & _GEN_1128;
   assign mem_index_MPORT_18_data = io_in_bits_2_bits_index;
   assign mem_index_MPORT_18_addr = 3'h4;
   assign mem_index_MPORT_18_mask = 1'h1;
-  assign mem_index_MPORT_18_en = ivalid & _GEN_1210;
+  assign mem_index_MPORT_18_en = ivalid & _GEN_1146;
   assign mem_index_MPORT_19_data = io_in_bits_3_bits_index;
   assign mem_index_MPORT_19_addr = 3'h4;
   assign mem_index_MPORT_19_mask = 1'h1;
-  assign mem_index_MPORT_19_en = ivalid & _GEN_1229;
+  assign mem_index_MPORT_19_en = ivalid & _GEN_1164;
   assign mem_index_MPORT_20_data = io_in_bits_0_bits_index;
   assign mem_index_MPORT_20_addr = 3'h5;
   assign mem_index_MPORT_20_mask = 1'h1;
@@ -17908,15 +16547,15 @@
   assign mem_index_MPORT_21_data = io_in_bits_1_bits_index;
   assign mem_index_MPORT_21_addr = 3'h5;
   assign mem_index_MPORT_21_mask = 1'h1;
-  assign mem_index_MPORT_21_en = ivalid & _GEN_1457;
+  assign mem_index_MPORT_21_en = ivalid & _GEN_1380;
   assign mem_index_MPORT_22_data = io_in_bits_2_bits_index;
   assign mem_index_MPORT_22_addr = 3'h5;
   assign mem_index_MPORT_22_mask = 1'h1;
-  assign mem_index_MPORT_22_en = ivalid & _GEN_1476;
+  assign mem_index_MPORT_22_en = ivalid & _GEN_1398;
   assign mem_index_MPORT_23_data = io_in_bits_3_bits_index;
   assign mem_index_MPORT_23_addr = 3'h5;
   assign mem_index_MPORT_23_mask = 1'h1;
-  assign mem_index_MPORT_23_en = ivalid & _GEN_1495;
+  assign mem_index_MPORT_23_en = ivalid & _GEN_1416;
   assign mem_index_MPORT_24_data = io_in_bits_0_bits_index;
   assign mem_index_MPORT_24_addr = 3'h6;
   assign mem_index_MPORT_24_mask = 1'h1;
@@ -17924,15 +16563,15 @@
   assign mem_index_MPORT_25_data = io_in_bits_1_bits_index;
   assign mem_index_MPORT_25_addr = 3'h6;
   assign mem_index_MPORT_25_mask = 1'h1;
-  assign mem_index_MPORT_25_en = ivalid & _GEN_1723;
+  assign mem_index_MPORT_25_en = ivalid & _GEN_1632;
   assign mem_index_MPORT_26_data = io_in_bits_2_bits_index;
   assign mem_index_MPORT_26_addr = 3'h6;
   assign mem_index_MPORT_26_mask = 1'h1;
-  assign mem_index_MPORT_26_en = ivalid & _GEN_1742;
+  assign mem_index_MPORT_26_en = ivalid & _GEN_1650;
   assign mem_index_MPORT_27_data = io_in_bits_3_bits_index;
   assign mem_index_MPORT_27_addr = 3'h6;
   assign mem_index_MPORT_27_mask = 1'h1;
-  assign mem_index_MPORT_27_en = ivalid & _GEN_1761;
+  assign mem_index_MPORT_27_en = ivalid & _GEN_1668;
   assign mem_size_mslice_io_in_bits_MPORT_en = mcount > 4'h0;
   assign mem_size_mslice_io_in_bits_MPORT_addr = outpos;
   `ifndef RANDOMIZE_GARBAGE_ASSIGN
@@ -17948,15 +16587,15 @@
   assign mem_size_MPORT_1_data = io_in_bits_1_bits_size;
   assign mem_size_MPORT_1_addr = 3'h0;
   assign mem_size_MPORT_1_mask = 1'h1;
-  assign mem_size_MPORT_1_en = ivalid & _GEN_141;
+  assign mem_size_MPORT_1_en = ivalid & _GEN_134;
   assign mem_size_MPORT_2_data = io_in_bits_2_bits_size;
   assign mem_size_MPORT_2_addr = 3'h0;
   assign mem_size_MPORT_2_mask = 1'h1;
-  assign mem_size_MPORT_2_en = ivalid & _GEN_160;
+  assign mem_size_MPORT_2_en = ivalid & _GEN_152;
   assign mem_size_MPORT_3_data = io_in_bits_3_bits_size;
   assign mem_size_MPORT_3_addr = 3'h0;
   assign mem_size_MPORT_3_mask = 1'h1;
-  assign mem_size_MPORT_3_en = ivalid & _GEN_179;
+  assign mem_size_MPORT_3_en = ivalid & _GEN_170;
   assign mem_size_MPORT_4_data = io_in_bits_0_bits_size;
   assign mem_size_MPORT_4_addr = 3'h1;
   assign mem_size_MPORT_4_mask = 1'h1;
@@ -17964,15 +16603,15 @@
   assign mem_size_MPORT_5_data = io_in_bits_1_bits_size;
   assign mem_size_MPORT_5_addr = 3'h1;
   assign mem_size_MPORT_5_mask = 1'h1;
-  assign mem_size_MPORT_5_en = ivalid & _GEN_400;
+  assign mem_size_MPORT_5_en = ivalid & _GEN_379;
   assign mem_size_MPORT_6_data = io_in_bits_2_bits_size;
   assign mem_size_MPORT_6_addr = 3'h1;
   assign mem_size_MPORT_6_mask = 1'h1;
-  assign mem_size_MPORT_6_en = ivalid & _GEN_418;
+  assign mem_size_MPORT_6_en = ivalid & _GEN_396;
   assign mem_size_MPORT_7_data = io_in_bits_3_bits_size;
   assign mem_size_MPORT_7_addr = 3'h1;
   assign mem_size_MPORT_7_mask = 1'h1;
-  assign mem_size_MPORT_7_en = ivalid & _GEN_436;
+  assign mem_size_MPORT_7_en = ivalid & _GEN_413;
   assign mem_size_MPORT_8_data = io_in_bits_0_bits_size;
   assign mem_size_MPORT_8_addr = 3'h2;
   assign mem_size_MPORT_8_mask = 1'h1;
@@ -17980,15 +16619,15 @@
   assign mem_size_MPORT_9_data = io_in_bits_1_bits_size;
   assign mem_size_MPORT_9_addr = 3'h2;
   assign mem_size_MPORT_9_mask = 1'h1;
-  assign mem_size_MPORT_9_en = ivalid & _GEN_659;
+  assign mem_size_MPORT_9_en = ivalid & _GEN_624;
   assign mem_size_MPORT_10_data = io_in_bits_2_bits_size;
   assign mem_size_MPORT_10_addr = 3'h2;
   assign mem_size_MPORT_10_mask = 1'h1;
-  assign mem_size_MPORT_10_en = ivalid & _GEN_678;
+  assign mem_size_MPORT_10_en = ivalid & _GEN_642;
   assign mem_size_MPORT_11_data = io_in_bits_3_bits_size;
   assign mem_size_MPORT_11_addr = 3'h2;
   assign mem_size_MPORT_11_mask = 1'h1;
-  assign mem_size_MPORT_11_en = ivalid & _GEN_697;
+  assign mem_size_MPORT_11_en = ivalid & _GEN_660;
   assign mem_size_MPORT_12_data = io_in_bits_0_bits_size;
   assign mem_size_MPORT_12_addr = 3'h3;
   assign mem_size_MPORT_12_mask = 1'h1;
@@ -17996,15 +16635,15 @@
   assign mem_size_MPORT_13_data = io_in_bits_1_bits_size;
   assign mem_size_MPORT_13_addr = 3'h3;
   assign mem_size_MPORT_13_mask = 1'h1;
-  assign mem_size_MPORT_13_en = ivalid & _GEN_925;
+  assign mem_size_MPORT_13_en = ivalid & _GEN_876;
   assign mem_size_MPORT_14_data = io_in_bits_2_bits_size;
   assign mem_size_MPORT_14_addr = 3'h3;
   assign mem_size_MPORT_14_mask = 1'h1;
-  assign mem_size_MPORT_14_en = ivalid & _GEN_944;
+  assign mem_size_MPORT_14_en = ivalid & _GEN_894;
   assign mem_size_MPORT_15_data = io_in_bits_3_bits_size;
   assign mem_size_MPORT_15_addr = 3'h3;
   assign mem_size_MPORT_15_mask = 1'h1;
-  assign mem_size_MPORT_15_en = ivalid & _GEN_963;
+  assign mem_size_MPORT_15_en = ivalid & _GEN_912;
   assign mem_size_MPORT_16_data = io_in_bits_0_bits_size;
   assign mem_size_MPORT_16_addr = 3'h4;
   assign mem_size_MPORT_16_mask = 1'h1;
@@ -18012,15 +16651,15 @@
   assign mem_size_MPORT_17_data = io_in_bits_1_bits_size;
   assign mem_size_MPORT_17_addr = 3'h4;
   assign mem_size_MPORT_17_mask = 1'h1;
-  assign mem_size_MPORT_17_en = ivalid & _GEN_1191;
+  assign mem_size_MPORT_17_en = ivalid & _GEN_1128;
   assign mem_size_MPORT_18_data = io_in_bits_2_bits_size;
   assign mem_size_MPORT_18_addr = 3'h4;
   assign mem_size_MPORT_18_mask = 1'h1;
-  assign mem_size_MPORT_18_en = ivalid & _GEN_1210;
+  assign mem_size_MPORT_18_en = ivalid & _GEN_1146;
   assign mem_size_MPORT_19_data = io_in_bits_3_bits_size;
   assign mem_size_MPORT_19_addr = 3'h4;
   assign mem_size_MPORT_19_mask = 1'h1;
-  assign mem_size_MPORT_19_en = ivalid & _GEN_1229;
+  assign mem_size_MPORT_19_en = ivalid & _GEN_1164;
   assign mem_size_MPORT_20_data = io_in_bits_0_bits_size;
   assign mem_size_MPORT_20_addr = 3'h5;
   assign mem_size_MPORT_20_mask = 1'h1;
@@ -18028,15 +16667,15 @@
   assign mem_size_MPORT_21_data = io_in_bits_1_bits_size;
   assign mem_size_MPORT_21_addr = 3'h5;
   assign mem_size_MPORT_21_mask = 1'h1;
-  assign mem_size_MPORT_21_en = ivalid & _GEN_1457;
+  assign mem_size_MPORT_21_en = ivalid & _GEN_1380;
   assign mem_size_MPORT_22_data = io_in_bits_2_bits_size;
   assign mem_size_MPORT_22_addr = 3'h5;
   assign mem_size_MPORT_22_mask = 1'h1;
-  assign mem_size_MPORT_22_en = ivalid & _GEN_1476;
+  assign mem_size_MPORT_22_en = ivalid & _GEN_1398;
   assign mem_size_MPORT_23_data = io_in_bits_3_bits_size;
   assign mem_size_MPORT_23_addr = 3'h5;
   assign mem_size_MPORT_23_mask = 1'h1;
-  assign mem_size_MPORT_23_en = ivalid & _GEN_1495;
+  assign mem_size_MPORT_23_en = ivalid & _GEN_1416;
   assign mem_size_MPORT_24_data = io_in_bits_0_bits_size;
   assign mem_size_MPORT_24_addr = 3'h6;
   assign mem_size_MPORT_24_mask = 1'h1;
@@ -18044,15 +16683,15 @@
   assign mem_size_MPORT_25_data = io_in_bits_1_bits_size;
   assign mem_size_MPORT_25_addr = 3'h6;
   assign mem_size_MPORT_25_mask = 1'h1;
-  assign mem_size_MPORT_25_en = ivalid & _GEN_1723;
+  assign mem_size_MPORT_25_en = ivalid & _GEN_1632;
   assign mem_size_MPORT_26_data = io_in_bits_2_bits_size;
   assign mem_size_MPORT_26_addr = 3'h6;
   assign mem_size_MPORT_26_mask = 1'h1;
-  assign mem_size_MPORT_26_en = ivalid & _GEN_1742;
+  assign mem_size_MPORT_26_en = ivalid & _GEN_1650;
   assign mem_size_MPORT_27_data = io_in_bits_3_bits_size;
   assign mem_size_MPORT_27_addr = 3'h6;
   assign mem_size_MPORT_27_mask = 1'h1;
-  assign mem_size_MPORT_27_en = ivalid & _GEN_1761;
+  assign mem_size_MPORT_27_en = ivalid & _GEN_1668;
   assign mem_write_mslice_io_in_bits_MPORT_en = mcount > 4'h0;
   assign mem_write_mslice_io_in_bits_MPORT_addr = outpos;
   `ifndef RANDOMIZE_GARBAGE_ASSIGN
@@ -18068,15 +16707,15 @@
   assign mem_write_MPORT_1_data = io_in_bits_1_bits_write;
   assign mem_write_MPORT_1_addr = 3'h0;
   assign mem_write_MPORT_1_mask = 1'h1;
-  assign mem_write_MPORT_1_en = ivalid & _GEN_141;
+  assign mem_write_MPORT_1_en = ivalid & _GEN_134;
   assign mem_write_MPORT_2_data = io_in_bits_2_bits_write;
   assign mem_write_MPORT_2_addr = 3'h0;
   assign mem_write_MPORT_2_mask = 1'h1;
-  assign mem_write_MPORT_2_en = ivalid & _GEN_160;
+  assign mem_write_MPORT_2_en = ivalid & _GEN_152;
   assign mem_write_MPORT_3_data = io_in_bits_3_bits_write;
   assign mem_write_MPORT_3_addr = 3'h0;
   assign mem_write_MPORT_3_mask = 1'h1;
-  assign mem_write_MPORT_3_en = ivalid & _GEN_179;
+  assign mem_write_MPORT_3_en = ivalid & _GEN_170;
   assign mem_write_MPORT_4_data = io_in_bits_0_bits_write;
   assign mem_write_MPORT_4_addr = 3'h1;
   assign mem_write_MPORT_4_mask = 1'h1;
@@ -18084,15 +16723,15 @@
   assign mem_write_MPORT_5_data = io_in_bits_1_bits_write;
   assign mem_write_MPORT_5_addr = 3'h1;
   assign mem_write_MPORT_5_mask = 1'h1;
-  assign mem_write_MPORT_5_en = ivalid & _GEN_400;
+  assign mem_write_MPORT_5_en = ivalid & _GEN_379;
   assign mem_write_MPORT_6_data = io_in_bits_2_bits_write;
   assign mem_write_MPORT_6_addr = 3'h1;
   assign mem_write_MPORT_6_mask = 1'h1;
-  assign mem_write_MPORT_6_en = ivalid & _GEN_418;
+  assign mem_write_MPORT_6_en = ivalid & _GEN_396;
   assign mem_write_MPORT_7_data = io_in_bits_3_bits_write;
   assign mem_write_MPORT_7_addr = 3'h1;
   assign mem_write_MPORT_7_mask = 1'h1;
-  assign mem_write_MPORT_7_en = ivalid & _GEN_436;
+  assign mem_write_MPORT_7_en = ivalid & _GEN_413;
   assign mem_write_MPORT_8_data = io_in_bits_0_bits_write;
   assign mem_write_MPORT_8_addr = 3'h2;
   assign mem_write_MPORT_8_mask = 1'h1;
@@ -18100,15 +16739,15 @@
   assign mem_write_MPORT_9_data = io_in_bits_1_bits_write;
   assign mem_write_MPORT_9_addr = 3'h2;
   assign mem_write_MPORT_9_mask = 1'h1;
-  assign mem_write_MPORT_9_en = ivalid & _GEN_659;
+  assign mem_write_MPORT_9_en = ivalid & _GEN_624;
   assign mem_write_MPORT_10_data = io_in_bits_2_bits_write;
   assign mem_write_MPORT_10_addr = 3'h2;
   assign mem_write_MPORT_10_mask = 1'h1;
-  assign mem_write_MPORT_10_en = ivalid & _GEN_678;
+  assign mem_write_MPORT_10_en = ivalid & _GEN_642;
   assign mem_write_MPORT_11_data = io_in_bits_3_bits_write;
   assign mem_write_MPORT_11_addr = 3'h2;
   assign mem_write_MPORT_11_mask = 1'h1;
-  assign mem_write_MPORT_11_en = ivalid & _GEN_697;
+  assign mem_write_MPORT_11_en = ivalid & _GEN_660;
   assign mem_write_MPORT_12_data = io_in_bits_0_bits_write;
   assign mem_write_MPORT_12_addr = 3'h3;
   assign mem_write_MPORT_12_mask = 1'h1;
@@ -18116,15 +16755,15 @@
   assign mem_write_MPORT_13_data = io_in_bits_1_bits_write;
   assign mem_write_MPORT_13_addr = 3'h3;
   assign mem_write_MPORT_13_mask = 1'h1;
-  assign mem_write_MPORT_13_en = ivalid & _GEN_925;
+  assign mem_write_MPORT_13_en = ivalid & _GEN_876;
   assign mem_write_MPORT_14_data = io_in_bits_2_bits_write;
   assign mem_write_MPORT_14_addr = 3'h3;
   assign mem_write_MPORT_14_mask = 1'h1;
-  assign mem_write_MPORT_14_en = ivalid & _GEN_944;
+  assign mem_write_MPORT_14_en = ivalid & _GEN_894;
   assign mem_write_MPORT_15_data = io_in_bits_3_bits_write;
   assign mem_write_MPORT_15_addr = 3'h3;
   assign mem_write_MPORT_15_mask = 1'h1;
-  assign mem_write_MPORT_15_en = ivalid & _GEN_963;
+  assign mem_write_MPORT_15_en = ivalid & _GEN_912;
   assign mem_write_MPORT_16_data = io_in_bits_0_bits_write;
   assign mem_write_MPORT_16_addr = 3'h4;
   assign mem_write_MPORT_16_mask = 1'h1;
@@ -18132,15 +16771,15 @@
   assign mem_write_MPORT_17_data = io_in_bits_1_bits_write;
   assign mem_write_MPORT_17_addr = 3'h4;
   assign mem_write_MPORT_17_mask = 1'h1;
-  assign mem_write_MPORT_17_en = ivalid & _GEN_1191;
+  assign mem_write_MPORT_17_en = ivalid & _GEN_1128;
   assign mem_write_MPORT_18_data = io_in_bits_2_bits_write;
   assign mem_write_MPORT_18_addr = 3'h4;
   assign mem_write_MPORT_18_mask = 1'h1;
-  assign mem_write_MPORT_18_en = ivalid & _GEN_1210;
+  assign mem_write_MPORT_18_en = ivalid & _GEN_1146;
   assign mem_write_MPORT_19_data = io_in_bits_3_bits_write;
   assign mem_write_MPORT_19_addr = 3'h4;
   assign mem_write_MPORT_19_mask = 1'h1;
-  assign mem_write_MPORT_19_en = ivalid & _GEN_1229;
+  assign mem_write_MPORT_19_en = ivalid & _GEN_1164;
   assign mem_write_MPORT_20_data = io_in_bits_0_bits_write;
   assign mem_write_MPORT_20_addr = 3'h5;
   assign mem_write_MPORT_20_mask = 1'h1;
@@ -18148,15 +16787,15 @@
   assign mem_write_MPORT_21_data = io_in_bits_1_bits_write;
   assign mem_write_MPORT_21_addr = 3'h5;
   assign mem_write_MPORT_21_mask = 1'h1;
-  assign mem_write_MPORT_21_en = ivalid & _GEN_1457;
+  assign mem_write_MPORT_21_en = ivalid & _GEN_1380;
   assign mem_write_MPORT_22_data = io_in_bits_2_bits_write;
   assign mem_write_MPORT_22_addr = 3'h5;
   assign mem_write_MPORT_22_mask = 1'h1;
-  assign mem_write_MPORT_22_en = ivalid & _GEN_1476;
+  assign mem_write_MPORT_22_en = ivalid & _GEN_1398;
   assign mem_write_MPORT_23_data = io_in_bits_3_bits_write;
   assign mem_write_MPORT_23_addr = 3'h5;
   assign mem_write_MPORT_23_mask = 1'h1;
-  assign mem_write_MPORT_23_en = ivalid & _GEN_1495;
+  assign mem_write_MPORT_23_en = ivalid & _GEN_1416;
   assign mem_write_MPORT_24_data = io_in_bits_0_bits_write;
   assign mem_write_MPORT_24_addr = 3'h6;
   assign mem_write_MPORT_24_mask = 1'h1;
@@ -18164,15 +16803,15 @@
   assign mem_write_MPORT_25_data = io_in_bits_1_bits_write;
   assign mem_write_MPORT_25_addr = 3'h6;
   assign mem_write_MPORT_25_mask = 1'h1;
-  assign mem_write_MPORT_25_en = ivalid & _GEN_1723;
+  assign mem_write_MPORT_25_en = ivalid & _GEN_1632;
   assign mem_write_MPORT_26_data = io_in_bits_2_bits_write;
   assign mem_write_MPORT_26_addr = 3'h6;
   assign mem_write_MPORT_26_mask = 1'h1;
-  assign mem_write_MPORT_26_en = ivalid & _GEN_1742;
+  assign mem_write_MPORT_26_en = ivalid & _GEN_1650;
   assign mem_write_MPORT_27_data = io_in_bits_3_bits_write;
   assign mem_write_MPORT_27_addr = 3'h6;
   assign mem_write_MPORT_27_mask = 1'h1;
-  assign mem_write_MPORT_27_en = ivalid & _GEN_1761;
+  assign mem_write_MPORT_27_en = ivalid & _GEN_1668;
   assign mem_sext_mslice_io_in_bits_MPORT_en = mcount > 4'h0;
   assign mem_sext_mslice_io_in_bits_MPORT_addr = outpos;
   `ifndef RANDOMIZE_GARBAGE_ASSIGN
@@ -18188,15 +16827,15 @@
   assign mem_sext_MPORT_1_data = io_in_bits_1_bits_sext;
   assign mem_sext_MPORT_1_addr = 3'h0;
   assign mem_sext_MPORT_1_mask = 1'h1;
-  assign mem_sext_MPORT_1_en = ivalid & _GEN_141;
+  assign mem_sext_MPORT_1_en = ivalid & _GEN_134;
   assign mem_sext_MPORT_2_data = io_in_bits_2_bits_sext;
   assign mem_sext_MPORT_2_addr = 3'h0;
   assign mem_sext_MPORT_2_mask = 1'h1;
-  assign mem_sext_MPORT_2_en = ivalid & _GEN_160;
+  assign mem_sext_MPORT_2_en = ivalid & _GEN_152;
   assign mem_sext_MPORT_3_data = io_in_bits_3_bits_sext;
   assign mem_sext_MPORT_3_addr = 3'h0;
   assign mem_sext_MPORT_3_mask = 1'h1;
-  assign mem_sext_MPORT_3_en = ivalid & _GEN_179;
+  assign mem_sext_MPORT_3_en = ivalid & _GEN_170;
   assign mem_sext_MPORT_4_data = io_in_bits_0_bits_sext;
   assign mem_sext_MPORT_4_addr = 3'h1;
   assign mem_sext_MPORT_4_mask = 1'h1;
@@ -18204,15 +16843,15 @@
   assign mem_sext_MPORT_5_data = io_in_bits_1_bits_sext;
   assign mem_sext_MPORT_5_addr = 3'h1;
   assign mem_sext_MPORT_5_mask = 1'h1;
-  assign mem_sext_MPORT_5_en = ivalid & _GEN_400;
+  assign mem_sext_MPORT_5_en = ivalid & _GEN_379;
   assign mem_sext_MPORT_6_data = io_in_bits_2_bits_sext;
   assign mem_sext_MPORT_6_addr = 3'h1;
   assign mem_sext_MPORT_6_mask = 1'h1;
-  assign mem_sext_MPORT_6_en = ivalid & _GEN_418;
+  assign mem_sext_MPORT_6_en = ivalid & _GEN_396;
   assign mem_sext_MPORT_7_data = io_in_bits_3_bits_sext;
   assign mem_sext_MPORT_7_addr = 3'h1;
   assign mem_sext_MPORT_7_mask = 1'h1;
-  assign mem_sext_MPORT_7_en = ivalid & _GEN_436;
+  assign mem_sext_MPORT_7_en = ivalid & _GEN_413;
   assign mem_sext_MPORT_8_data = io_in_bits_0_bits_sext;
   assign mem_sext_MPORT_8_addr = 3'h2;
   assign mem_sext_MPORT_8_mask = 1'h1;
@@ -18220,15 +16859,15 @@
   assign mem_sext_MPORT_9_data = io_in_bits_1_bits_sext;
   assign mem_sext_MPORT_9_addr = 3'h2;
   assign mem_sext_MPORT_9_mask = 1'h1;
-  assign mem_sext_MPORT_9_en = ivalid & _GEN_659;
+  assign mem_sext_MPORT_9_en = ivalid & _GEN_624;
   assign mem_sext_MPORT_10_data = io_in_bits_2_bits_sext;
   assign mem_sext_MPORT_10_addr = 3'h2;
   assign mem_sext_MPORT_10_mask = 1'h1;
-  assign mem_sext_MPORT_10_en = ivalid & _GEN_678;
+  assign mem_sext_MPORT_10_en = ivalid & _GEN_642;
   assign mem_sext_MPORT_11_data = io_in_bits_3_bits_sext;
   assign mem_sext_MPORT_11_addr = 3'h2;
   assign mem_sext_MPORT_11_mask = 1'h1;
-  assign mem_sext_MPORT_11_en = ivalid & _GEN_697;
+  assign mem_sext_MPORT_11_en = ivalid & _GEN_660;
   assign mem_sext_MPORT_12_data = io_in_bits_0_bits_sext;
   assign mem_sext_MPORT_12_addr = 3'h3;
   assign mem_sext_MPORT_12_mask = 1'h1;
@@ -18236,15 +16875,15 @@
   assign mem_sext_MPORT_13_data = io_in_bits_1_bits_sext;
   assign mem_sext_MPORT_13_addr = 3'h3;
   assign mem_sext_MPORT_13_mask = 1'h1;
-  assign mem_sext_MPORT_13_en = ivalid & _GEN_925;
+  assign mem_sext_MPORT_13_en = ivalid & _GEN_876;
   assign mem_sext_MPORT_14_data = io_in_bits_2_bits_sext;
   assign mem_sext_MPORT_14_addr = 3'h3;
   assign mem_sext_MPORT_14_mask = 1'h1;
-  assign mem_sext_MPORT_14_en = ivalid & _GEN_944;
+  assign mem_sext_MPORT_14_en = ivalid & _GEN_894;
   assign mem_sext_MPORT_15_data = io_in_bits_3_bits_sext;
   assign mem_sext_MPORT_15_addr = 3'h3;
   assign mem_sext_MPORT_15_mask = 1'h1;
-  assign mem_sext_MPORT_15_en = ivalid & _GEN_963;
+  assign mem_sext_MPORT_15_en = ivalid & _GEN_912;
   assign mem_sext_MPORT_16_data = io_in_bits_0_bits_sext;
   assign mem_sext_MPORT_16_addr = 3'h4;
   assign mem_sext_MPORT_16_mask = 1'h1;
@@ -18252,15 +16891,15 @@
   assign mem_sext_MPORT_17_data = io_in_bits_1_bits_sext;
   assign mem_sext_MPORT_17_addr = 3'h4;
   assign mem_sext_MPORT_17_mask = 1'h1;
-  assign mem_sext_MPORT_17_en = ivalid & _GEN_1191;
+  assign mem_sext_MPORT_17_en = ivalid & _GEN_1128;
   assign mem_sext_MPORT_18_data = io_in_bits_2_bits_sext;
   assign mem_sext_MPORT_18_addr = 3'h4;
   assign mem_sext_MPORT_18_mask = 1'h1;
-  assign mem_sext_MPORT_18_en = ivalid & _GEN_1210;
+  assign mem_sext_MPORT_18_en = ivalid & _GEN_1146;
   assign mem_sext_MPORT_19_data = io_in_bits_3_bits_sext;
   assign mem_sext_MPORT_19_addr = 3'h4;
   assign mem_sext_MPORT_19_mask = 1'h1;
-  assign mem_sext_MPORT_19_en = ivalid & _GEN_1229;
+  assign mem_sext_MPORT_19_en = ivalid & _GEN_1164;
   assign mem_sext_MPORT_20_data = io_in_bits_0_bits_sext;
   assign mem_sext_MPORT_20_addr = 3'h5;
   assign mem_sext_MPORT_20_mask = 1'h1;
@@ -18268,15 +16907,15 @@
   assign mem_sext_MPORT_21_data = io_in_bits_1_bits_sext;
   assign mem_sext_MPORT_21_addr = 3'h5;
   assign mem_sext_MPORT_21_mask = 1'h1;
-  assign mem_sext_MPORT_21_en = ivalid & _GEN_1457;
+  assign mem_sext_MPORT_21_en = ivalid & _GEN_1380;
   assign mem_sext_MPORT_22_data = io_in_bits_2_bits_sext;
   assign mem_sext_MPORT_22_addr = 3'h5;
   assign mem_sext_MPORT_22_mask = 1'h1;
-  assign mem_sext_MPORT_22_en = ivalid & _GEN_1476;
+  assign mem_sext_MPORT_22_en = ivalid & _GEN_1398;
   assign mem_sext_MPORT_23_data = io_in_bits_3_bits_sext;
   assign mem_sext_MPORT_23_addr = 3'h5;
   assign mem_sext_MPORT_23_mask = 1'h1;
-  assign mem_sext_MPORT_23_en = ivalid & _GEN_1495;
+  assign mem_sext_MPORT_23_en = ivalid & _GEN_1416;
   assign mem_sext_MPORT_24_data = io_in_bits_0_bits_sext;
   assign mem_sext_MPORT_24_addr = 3'h6;
   assign mem_sext_MPORT_24_mask = 1'h1;
@@ -18284,141 +16923,21 @@
   assign mem_sext_MPORT_25_data = io_in_bits_1_bits_sext;
   assign mem_sext_MPORT_25_addr = 3'h6;
   assign mem_sext_MPORT_25_mask = 1'h1;
-  assign mem_sext_MPORT_25_en = ivalid & _GEN_1723;
+  assign mem_sext_MPORT_25_en = ivalid & _GEN_1632;
   assign mem_sext_MPORT_26_data = io_in_bits_2_bits_sext;
   assign mem_sext_MPORT_26_addr = 3'h6;
   assign mem_sext_MPORT_26_mask = 1'h1;
-  assign mem_sext_MPORT_26_en = ivalid & _GEN_1742;
+  assign mem_sext_MPORT_26_en = ivalid & _GEN_1650;
   assign mem_sext_MPORT_27_data = io_in_bits_3_bits_sext;
   assign mem_sext_MPORT_27_addr = 3'h6;
   assign mem_sext_MPORT_27_mask = 1'h1;
-  assign mem_sext_MPORT_27_en = ivalid & _GEN_1761;
-  assign mem_fload_mslice_io_in_bits_MPORT_en = mcount > 4'h0;
-  assign mem_fload_mslice_io_in_bits_MPORT_addr = outpos;
-  `ifndef RANDOMIZE_GARBAGE_ASSIGN
-  assign mem_fload_mslice_io_in_bits_MPORT_data = mem_fload[mem_fload_mslice_io_in_bits_MPORT_addr]; // @[Fifo4.scala 59:16]
-  `else
-  assign mem_fload_mslice_io_in_bits_MPORT_data = mem_fload_mslice_io_in_bits_MPORT_addr >= 3'h7 ? _RAND_15[0:0] :
-    mem_fload[mem_fload_mslice_io_in_bits_MPORT_addr]; // @[Fifo4.scala 59:16]
-  `endif // RANDOMIZE_GARBAGE_ASSIGN
-  assign mem_fload_MPORT_data = io_in_bits_0_bits_fload;
-  assign mem_fload_MPORT_addr = 3'h0;
-  assign mem_fload_MPORT_mask = 1'h1;
-  assign mem_fload_MPORT_en = ivalid & valid[0];
-  assign mem_fload_MPORT_1_data = io_in_bits_1_bits_fload;
-  assign mem_fload_MPORT_1_addr = 3'h0;
-  assign mem_fload_MPORT_1_mask = 1'h1;
-  assign mem_fload_MPORT_1_en = ivalid & _GEN_141;
-  assign mem_fload_MPORT_2_data = io_in_bits_2_bits_fload;
-  assign mem_fload_MPORT_2_addr = 3'h0;
-  assign mem_fload_MPORT_2_mask = 1'h1;
-  assign mem_fload_MPORT_2_en = ivalid & _GEN_160;
-  assign mem_fload_MPORT_3_data = io_in_bits_3_bits_fload;
-  assign mem_fload_MPORT_3_addr = 3'h0;
-  assign mem_fload_MPORT_3_mask = 1'h1;
-  assign mem_fload_MPORT_3_en = ivalid & _GEN_179;
-  assign mem_fload_MPORT_4_data = io_in_bits_0_bits_fload;
-  assign mem_fload_MPORT_4_addr = 3'h1;
-  assign mem_fload_MPORT_4_mask = 1'h1;
-  assign mem_fload_MPORT_4_en = ivalid & valid_1[0];
-  assign mem_fload_MPORT_5_data = io_in_bits_1_bits_fload;
-  assign mem_fload_MPORT_5_addr = 3'h1;
-  assign mem_fload_MPORT_5_mask = 1'h1;
-  assign mem_fload_MPORT_5_en = ivalid & _GEN_400;
-  assign mem_fload_MPORT_6_data = io_in_bits_2_bits_fload;
-  assign mem_fload_MPORT_6_addr = 3'h1;
-  assign mem_fload_MPORT_6_mask = 1'h1;
-  assign mem_fload_MPORT_6_en = ivalid & _GEN_418;
-  assign mem_fload_MPORT_7_data = io_in_bits_3_bits_fload;
-  assign mem_fload_MPORT_7_addr = 3'h1;
-  assign mem_fload_MPORT_7_mask = 1'h1;
-  assign mem_fload_MPORT_7_en = ivalid & _GEN_436;
-  assign mem_fload_MPORT_8_data = io_in_bits_0_bits_fload;
-  assign mem_fload_MPORT_8_addr = 3'h2;
-  assign mem_fload_MPORT_8_mask = 1'h1;
-  assign mem_fload_MPORT_8_en = ivalid & valid_2[0];
-  assign mem_fload_MPORT_9_data = io_in_bits_1_bits_fload;
-  assign mem_fload_MPORT_9_addr = 3'h2;
-  assign mem_fload_MPORT_9_mask = 1'h1;
-  assign mem_fload_MPORT_9_en = ivalid & _GEN_659;
-  assign mem_fload_MPORT_10_data = io_in_bits_2_bits_fload;
-  assign mem_fload_MPORT_10_addr = 3'h2;
-  assign mem_fload_MPORT_10_mask = 1'h1;
-  assign mem_fload_MPORT_10_en = ivalid & _GEN_678;
-  assign mem_fload_MPORT_11_data = io_in_bits_3_bits_fload;
-  assign mem_fload_MPORT_11_addr = 3'h2;
-  assign mem_fload_MPORT_11_mask = 1'h1;
-  assign mem_fload_MPORT_11_en = ivalid & _GEN_697;
-  assign mem_fload_MPORT_12_data = io_in_bits_0_bits_fload;
-  assign mem_fload_MPORT_12_addr = 3'h3;
-  assign mem_fload_MPORT_12_mask = 1'h1;
-  assign mem_fload_MPORT_12_en = ivalid & valid_3[0];
-  assign mem_fload_MPORT_13_data = io_in_bits_1_bits_fload;
-  assign mem_fload_MPORT_13_addr = 3'h3;
-  assign mem_fload_MPORT_13_mask = 1'h1;
-  assign mem_fload_MPORT_13_en = ivalid & _GEN_925;
-  assign mem_fload_MPORT_14_data = io_in_bits_2_bits_fload;
-  assign mem_fload_MPORT_14_addr = 3'h3;
-  assign mem_fload_MPORT_14_mask = 1'h1;
-  assign mem_fload_MPORT_14_en = ivalid & _GEN_944;
-  assign mem_fload_MPORT_15_data = io_in_bits_3_bits_fload;
-  assign mem_fload_MPORT_15_addr = 3'h3;
-  assign mem_fload_MPORT_15_mask = 1'h1;
-  assign mem_fload_MPORT_15_en = ivalid & _GEN_963;
-  assign mem_fload_MPORT_16_data = io_in_bits_0_bits_fload;
-  assign mem_fload_MPORT_16_addr = 3'h4;
-  assign mem_fload_MPORT_16_mask = 1'h1;
-  assign mem_fload_MPORT_16_en = ivalid & valid_4[0];
-  assign mem_fload_MPORT_17_data = io_in_bits_1_bits_fload;
-  assign mem_fload_MPORT_17_addr = 3'h4;
-  assign mem_fload_MPORT_17_mask = 1'h1;
-  assign mem_fload_MPORT_17_en = ivalid & _GEN_1191;
-  assign mem_fload_MPORT_18_data = io_in_bits_2_bits_fload;
-  assign mem_fload_MPORT_18_addr = 3'h4;
-  assign mem_fload_MPORT_18_mask = 1'h1;
-  assign mem_fload_MPORT_18_en = ivalid & _GEN_1210;
-  assign mem_fload_MPORT_19_data = io_in_bits_3_bits_fload;
-  assign mem_fload_MPORT_19_addr = 3'h4;
-  assign mem_fload_MPORT_19_mask = 1'h1;
-  assign mem_fload_MPORT_19_en = ivalid & _GEN_1229;
-  assign mem_fload_MPORT_20_data = io_in_bits_0_bits_fload;
-  assign mem_fload_MPORT_20_addr = 3'h5;
-  assign mem_fload_MPORT_20_mask = 1'h1;
-  assign mem_fload_MPORT_20_en = ivalid & valid_5[0];
-  assign mem_fload_MPORT_21_data = io_in_bits_1_bits_fload;
-  assign mem_fload_MPORT_21_addr = 3'h5;
-  assign mem_fload_MPORT_21_mask = 1'h1;
-  assign mem_fload_MPORT_21_en = ivalid & _GEN_1457;
-  assign mem_fload_MPORT_22_data = io_in_bits_2_bits_fload;
-  assign mem_fload_MPORT_22_addr = 3'h5;
-  assign mem_fload_MPORT_22_mask = 1'h1;
-  assign mem_fload_MPORT_22_en = ivalid & _GEN_1476;
-  assign mem_fload_MPORT_23_data = io_in_bits_3_bits_fload;
-  assign mem_fload_MPORT_23_addr = 3'h5;
-  assign mem_fload_MPORT_23_mask = 1'h1;
-  assign mem_fload_MPORT_23_en = ivalid & _GEN_1495;
-  assign mem_fload_MPORT_24_data = io_in_bits_0_bits_fload;
-  assign mem_fload_MPORT_24_addr = 3'h6;
-  assign mem_fload_MPORT_24_mask = 1'h1;
-  assign mem_fload_MPORT_24_en = ivalid & valid_6[0];
-  assign mem_fload_MPORT_25_data = io_in_bits_1_bits_fload;
-  assign mem_fload_MPORT_25_addr = 3'h6;
-  assign mem_fload_MPORT_25_mask = 1'h1;
-  assign mem_fload_MPORT_25_en = ivalid & _GEN_1723;
-  assign mem_fload_MPORT_26_data = io_in_bits_2_bits_fload;
-  assign mem_fload_MPORT_26_addr = 3'h6;
-  assign mem_fload_MPORT_26_mask = 1'h1;
-  assign mem_fload_MPORT_26_en = ivalid & _GEN_1742;
-  assign mem_fload_MPORT_27_data = io_in_bits_3_bits_fload;
-  assign mem_fload_MPORT_27_addr = 3'h6;
-  assign mem_fload_MPORT_27_mask = 1'h1;
-  assign mem_fload_MPORT_27_en = ivalid & _GEN_1761;
+  assign mem_sext_MPORT_27_en = ivalid & _GEN_1668;
   assign mem_iload_mslice_io_in_bits_MPORT_en = mcount > 4'h0;
   assign mem_iload_mslice_io_in_bits_MPORT_addr = outpos;
   `ifndef RANDOMIZE_GARBAGE_ASSIGN
   assign mem_iload_mslice_io_in_bits_MPORT_data = mem_iload[mem_iload_mslice_io_in_bits_MPORT_addr]; // @[Fifo4.scala 59:16]
   `else
-  assign mem_iload_mslice_io_in_bits_MPORT_data = mem_iload_mslice_io_in_bits_MPORT_addr >= 3'h7 ? _RAND_17[0:0] :
+  assign mem_iload_mslice_io_in_bits_MPORT_data = mem_iload_mslice_io_in_bits_MPORT_addr >= 3'h7 ? _RAND_15[0:0] :
     mem_iload[mem_iload_mslice_io_in_bits_MPORT_addr]; // @[Fifo4.scala 59:16]
   `endif // RANDOMIZE_GARBAGE_ASSIGN
   assign mem_iload_MPORT_data = io_in_bits_0_bits_iload;
@@ -18428,15 +16947,15 @@
   assign mem_iload_MPORT_1_data = io_in_bits_1_bits_iload;
   assign mem_iload_MPORT_1_addr = 3'h0;
   assign mem_iload_MPORT_1_mask = 1'h1;
-  assign mem_iload_MPORT_1_en = ivalid & _GEN_141;
+  assign mem_iload_MPORT_1_en = ivalid & _GEN_134;
   assign mem_iload_MPORT_2_data = io_in_bits_2_bits_iload;
   assign mem_iload_MPORT_2_addr = 3'h0;
   assign mem_iload_MPORT_2_mask = 1'h1;
-  assign mem_iload_MPORT_2_en = ivalid & _GEN_160;
+  assign mem_iload_MPORT_2_en = ivalid & _GEN_152;
   assign mem_iload_MPORT_3_data = io_in_bits_3_bits_iload;
   assign mem_iload_MPORT_3_addr = 3'h0;
   assign mem_iload_MPORT_3_mask = 1'h1;
-  assign mem_iload_MPORT_3_en = ivalid & _GEN_179;
+  assign mem_iload_MPORT_3_en = ivalid & _GEN_170;
   assign mem_iload_MPORT_4_data = io_in_bits_0_bits_iload;
   assign mem_iload_MPORT_4_addr = 3'h1;
   assign mem_iload_MPORT_4_mask = 1'h1;
@@ -18444,15 +16963,15 @@
   assign mem_iload_MPORT_5_data = io_in_bits_1_bits_iload;
   assign mem_iload_MPORT_5_addr = 3'h1;
   assign mem_iload_MPORT_5_mask = 1'h1;
-  assign mem_iload_MPORT_5_en = ivalid & _GEN_400;
+  assign mem_iload_MPORT_5_en = ivalid & _GEN_379;
   assign mem_iload_MPORT_6_data = io_in_bits_2_bits_iload;
   assign mem_iload_MPORT_6_addr = 3'h1;
   assign mem_iload_MPORT_6_mask = 1'h1;
-  assign mem_iload_MPORT_6_en = ivalid & _GEN_418;
+  assign mem_iload_MPORT_6_en = ivalid & _GEN_396;
   assign mem_iload_MPORT_7_data = io_in_bits_3_bits_iload;
   assign mem_iload_MPORT_7_addr = 3'h1;
   assign mem_iload_MPORT_7_mask = 1'h1;
-  assign mem_iload_MPORT_7_en = ivalid & _GEN_436;
+  assign mem_iload_MPORT_7_en = ivalid & _GEN_413;
   assign mem_iload_MPORT_8_data = io_in_bits_0_bits_iload;
   assign mem_iload_MPORT_8_addr = 3'h2;
   assign mem_iload_MPORT_8_mask = 1'h1;
@@ -18460,15 +16979,15 @@
   assign mem_iload_MPORT_9_data = io_in_bits_1_bits_iload;
   assign mem_iload_MPORT_9_addr = 3'h2;
   assign mem_iload_MPORT_9_mask = 1'h1;
-  assign mem_iload_MPORT_9_en = ivalid & _GEN_659;
+  assign mem_iload_MPORT_9_en = ivalid & _GEN_624;
   assign mem_iload_MPORT_10_data = io_in_bits_2_bits_iload;
   assign mem_iload_MPORT_10_addr = 3'h2;
   assign mem_iload_MPORT_10_mask = 1'h1;
-  assign mem_iload_MPORT_10_en = ivalid & _GEN_678;
+  assign mem_iload_MPORT_10_en = ivalid & _GEN_642;
   assign mem_iload_MPORT_11_data = io_in_bits_3_bits_iload;
   assign mem_iload_MPORT_11_addr = 3'h2;
   assign mem_iload_MPORT_11_mask = 1'h1;
-  assign mem_iload_MPORT_11_en = ivalid & _GEN_697;
+  assign mem_iload_MPORT_11_en = ivalid & _GEN_660;
   assign mem_iload_MPORT_12_data = io_in_bits_0_bits_iload;
   assign mem_iload_MPORT_12_addr = 3'h3;
   assign mem_iload_MPORT_12_mask = 1'h1;
@@ -18476,15 +16995,15 @@
   assign mem_iload_MPORT_13_data = io_in_bits_1_bits_iload;
   assign mem_iload_MPORT_13_addr = 3'h3;
   assign mem_iload_MPORT_13_mask = 1'h1;
-  assign mem_iload_MPORT_13_en = ivalid & _GEN_925;
+  assign mem_iload_MPORT_13_en = ivalid & _GEN_876;
   assign mem_iload_MPORT_14_data = io_in_bits_2_bits_iload;
   assign mem_iload_MPORT_14_addr = 3'h3;
   assign mem_iload_MPORT_14_mask = 1'h1;
-  assign mem_iload_MPORT_14_en = ivalid & _GEN_944;
+  assign mem_iload_MPORT_14_en = ivalid & _GEN_894;
   assign mem_iload_MPORT_15_data = io_in_bits_3_bits_iload;
   assign mem_iload_MPORT_15_addr = 3'h3;
   assign mem_iload_MPORT_15_mask = 1'h1;
-  assign mem_iload_MPORT_15_en = ivalid & _GEN_963;
+  assign mem_iload_MPORT_15_en = ivalid & _GEN_912;
   assign mem_iload_MPORT_16_data = io_in_bits_0_bits_iload;
   assign mem_iload_MPORT_16_addr = 3'h4;
   assign mem_iload_MPORT_16_mask = 1'h1;
@@ -18492,15 +17011,15 @@
   assign mem_iload_MPORT_17_data = io_in_bits_1_bits_iload;
   assign mem_iload_MPORT_17_addr = 3'h4;
   assign mem_iload_MPORT_17_mask = 1'h1;
-  assign mem_iload_MPORT_17_en = ivalid & _GEN_1191;
+  assign mem_iload_MPORT_17_en = ivalid & _GEN_1128;
   assign mem_iload_MPORT_18_data = io_in_bits_2_bits_iload;
   assign mem_iload_MPORT_18_addr = 3'h4;
   assign mem_iload_MPORT_18_mask = 1'h1;
-  assign mem_iload_MPORT_18_en = ivalid & _GEN_1210;
+  assign mem_iload_MPORT_18_en = ivalid & _GEN_1146;
   assign mem_iload_MPORT_19_data = io_in_bits_3_bits_iload;
   assign mem_iload_MPORT_19_addr = 3'h4;
   assign mem_iload_MPORT_19_mask = 1'h1;
-  assign mem_iload_MPORT_19_en = ivalid & _GEN_1229;
+  assign mem_iload_MPORT_19_en = ivalid & _GEN_1164;
   assign mem_iload_MPORT_20_data = io_in_bits_0_bits_iload;
   assign mem_iload_MPORT_20_addr = 3'h5;
   assign mem_iload_MPORT_20_mask = 1'h1;
@@ -18508,15 +17027,15 @@
   assign mem_iload_MPORT_21_data = io_in_bits_1_bits_iload;
   assign mem_iload_MPORT_21_addr = 3'h5;
   assign mem_iload_MPORT_21_mask = 1'h1;
-  assign mem_iload_MPORT_21_en = ivalid & _GEN_1457;
+  assign mem_iload_MPORT_21_en = ivalid & _GEN_1380;
   assign mem_iload_MPORT_22_data = io_in_bits_2_bits_iload;
   assign mem_iload_MPORT_22_addr = 3'h5;
   assign mem_iload_MPORT_22_mask = 1'h1;
-  assign mem_iload_MPORT_22_en = ivalid & _GEN_1476;
+  assign mem_iload_MPORT_22_en = ivalid & _GEN_1398;
   assign mem_iload_MPORT_23_data = io_in_bits_3_bits_iload;
   assign mem_iload_MPORT_23_addr = 3'h5;
   assign mem_iload_MPORT_23_mask = 1'h1;
-  assign mem_iload_MPORT_23_en = ivalid & _GEN_1495;
+  assign mem_iload_MPORT_23_en = ivalid & _GEN_1416;
   assign mem_iload_MPORT_24_data = io_in_bits_0_bits_iload;
   assign mem_iload_MPORT_24_addr = 3'h6;
   assign mem_iload_MPORT_24_mask = 1'h1;
@@ -18524,21 +17043,21 @@
   assign mem_iload_MPORT_25_data = io_in_bits_1_bits_iload;
   assign mem_iload_MPORT_25_addr = 3'h6;
   assign mem_iload_MPORT_25_mask = 1'h1;
-  assign mem_iload_MPORT_25_en = ivalid & _GEN_1723;
+  assign mem_iload_MPORT_25_en = ivalid & _GEN_1632;
   assign mem_iload_MPORT_26_data = io_in_bits_2_bits_iload;
   assign mem_iload_MPORT_26_addr = 3'h6;
   assign mem_iload_MPORT_26_mask = 1'h1;
-  assign mem_iload_MPORT_26_en = ivalid & _GEN_1742;
+  assign mem_iload_MPORT_26_en = ivalid & _GEN_1650;
   assign mem_iload_MPORT_27_data = io_in_bits_3_bits_iload;
   assign mem_iload_MPORT_27_addr = 3'h6;
   assign mem_iload_MPORT_27_mask = 1'h1;
-  assign mem_iload_MPORT_27_en = ivalid & _GEN_1761;
+  assign mem_iload_MPORT_27_en = ivalid & _GEN_1668;
   assign mem_fencei_mslice_io_in_bits_MPORT_en = mcount > 4'h0;
   assign mem_fencei_mslice_io_in_bits_MPORT_addr = outpos;
   `ifndef RANDOMIZE_GARBAGE_ASSIGN
   assign mem_fencei_mslice_io_in_bits_MPORT_data = mem_fencei[mem_fencei_mslice_io_in_bits_MPORT_addr]; // @[Fifo4.scala 59:16]
   `else
-  assign mem_fencei_mslice_io_in_bits_MPORT_data = mem_fencei_mslice_io_in_bits_MPORT_addr >= 3'h7 ? _RAND_19[0:0] :
+  assign mem_fencei_mslice_io_in_bits_MPORT_data = mem_fencei_mslice_io_in_bits_MPORT_addr >= 3'h7 ? _RAND_17[0:0] :
     mem_fencei[mem_fencei_mslice_io_in_bits_MPORT_addr]; // @[Fifo4.scala 59:16]
   `endif // RANDOMIZE_GARBAGE_ASSIGN
   assign mem_fencei_MPORT_data = io_in_bits_0_bits_fencei;
@@ -18548,15 +17067,15 @@
   assign mem_fencei_MPORT_1_data = io_in_bits_1_bits_fencei;
   assign mem_fencei_MPORT_1_addr = 3'h0;
   assign mem_fencei_MPORT_1_mask = 1'h1;
-  assign mem_fencei_MPORT_1_en = ivalid & _GEN_141;
+  assign mem_fencei_MPORT_1_en = ivalid & _GEN_134;
   assign mem_fencei_MPORT_2_data = io_in_bits_2_bits_fencei;
   assign mem_fencei_MPORT_2_addr = 3'h0;
   assign mem_fencei_MPORT_2_mask = 1'h1;
-  assign mem_fencei_MPORT_2_en = ivalid & _GEN_160;
+  assign mem_fencei_MPORT_2_en = ivalid & _GEN_152;
   assign mem_fencei_MPORT_3_data = io_in_bits_3_bits_fencei;
   assign mem_fencei_MPORT_3_addr = 3'h0;
   assign mem_fencei_MPORT_3_mask = 1'h1;
-  assign mem_fencei_MPORT_3_en = ivalid & _GEN_179;
+  assign mem_fencei_MPORT_3_en = ivalid & _GEN_170;
   assign mem_fencei_MPORT_4_data = io_in_bits_0_bits_fencei;
   assign mem_fencei_MPORT_4_addr = 3'h1;
   assign mem_fencei_MPORT_4_mask = 1'h1;
@@ -18564,15 +17083,15 @@
   assign mem_fencei_MPORT_5_data = io_in_bits_1_bits_fencei;
   assign mem_fencei_MPORT_5_addr = 3'h1;
   assign mem_fencei_MPORT_5_mask = 1'h1;
-  assign mem_fencei_MPORT_5_en = ivalid & _GEN_400;
+  assign mem_fencei_MPORT_5_en = ivalid & _GEN_379;
   assign mem_fencei_MPORT_6_data = io_in_bits_2_bits_fencei;
   assign mem_fencei_MPORT_6_addr = 3'h1;
   assign mem_fencei_MPORT_6_mask = 1'h1;
-  assign mem_fencei_MPORT_6_en = ivalid & _GEN_418;
+  assign mem_fencei_MPORT_6_en = ivalid & _GEN_396;
   assign mem_fencei_MPORT_7_data = io_in_bits_3_bits_fencei;
   assign mem_fencei_MPORT_7_addr = 3'h1;
   assign mem_fencei_MPORT_7_mask = 1'h1;
-  assign mem_fencei_MPORT_7_en = ivalid & _GEN_436;
+  assign mem_fencei_MPORT_7_en = ivalid & _GEN_413;
   assign mem_fencei_MPORT_8_data = io_in_bits_0_bits_fencei;
   assign mem_fencei_MPORT_8_addr = 3'h2;
   assign mem_fencei_MPORT_8_mask = 1'h1;
@@ -18580,15 +17099,15 @@
   assign mem_fencei_MPORT_9_data = io_in_bits_1_bits_fencei;
   assign mem_fencei_MPORT_9_addr = 3'h2;
   assign mem_fencei_MPORT_9_mask = 1'h1;
-  assign mem_fencei_MPORT_9_en = ivalid & _GEN_659;
+  assign mem_fencei_MPORT_9_en = ivalid & _GEN_624;
   assign mem_fencei_MPORT_10_data = io_in_bits_2_bits_fencei;
   assign mem_fencei_MPORT_10_addr = 3'h2;
   assign mem_fencei_MPORT_10_mask = 1'h1;
-  assign mem_fencei_MPORT_10_en = ivalid & _GEN_678;
+  assign mem_fencei_MPORT_10_en = ivalid & _GEN_642;
   assign mem_fencei_MPORT_11_data = io_in_bits_3_bits_fencei;
   assign mem_fencei_MPORT_11_addr = 3'h2;
   assign mem_fencei_MPORT_11_mask = 1'h1;
-  assign mem_fencei_MPORT_11_en = ivalid & _GEN_697;
+  assign mem_fencei_MPORT_11_en = ivalid & _GEN_660;
   assign mem_fencei_MPORT_12_data = io_in_bits_0_bits_fencei;
   assign mem_fencei_MPORT_12_addr = 3'h3;
   assign mem_fencei_MPORT_12_mask = 1'h1;
@@ -18596,15 +17115,15 @@
   assign mem_fencei_MPORT_13_data = io_in_bits_1_bits_fencei;
   assign mem_fencei_MPORT_13_addr = 3'h3;
   assign mem_fencei_MPORT_13_mask = 1'h1;
-  assign mem_fencei_MPORT_13_en = ivalid & _GEN_925;
+  assign mem_fencei_MPORT_13_en = ivalid & _GEN_876;
   assign mem_fencei_MPORT_14_data = io_in_bits_2_bits_fencei;
   assign mem_fencei_MPORT_14_addr = 3'h3;
   assign mem_fencei_MPORT_14_mask = 1'h1;
-  assign mem_fencei_MPORT_14_en = ivalid & _GEN_944;
+  assign mem_fencei_MPORT_14_en = ivalid & _GEN_894;
   assign mem_fencei_MPORT_15_data = io_in_bits_3_bits_fencei;
   assign mem_fencei_MPORT_15_addr = 3'h3;
   assign mem_fencei_MPORT_15_mask = 1'h1;
-  assign mem_fencei_MPORT_15_en = ivalid & _GEN_963;
+  assign mem_fencei_MPORT_15_en = ivalid & _GEN_912;
   assign mem_fencei_MPORT_16_data = io_in_bits_0_bits_fencei;
   assign mem_fencei_MPORT_16_addr = 3'h4;
   assign mem_fencei_MPORT_16_mask = 1'h1;
@@ -18612,15 +17131,15 @@
   assign mem_fencei_MPORT_17_data = io_in_bits_1_bits_fencei;
   assign mem_fencei_MPORT_17_addr = 3'h4;
   assign mem_fencei_MPORT_17_mask = 1'h1;
-  assign mem_fencei_MPORT_17_en = ivalid & _GEN_1191;
+  assign mem_fencei_MPORT_17_en = ivalid & _GEN_1128;
   assign mem_fencei_MPORT_18_data = io_in_bits_2_bits_fencei;
   assign mem_fencei_MPORT_18_addr = 3'h4;
   assign mem_fencei_MPORT_18_mask = 1'h1;
-  assign mem_fencei_MPORT_18_en = ivalid & _GEN_1210;
+  assign mem_fencei_MPORT_18_en = ivalid & _GEN_1146;
   assign mem_fencei_MPORT_19_data = io_in_bits_3_bits_fencei;
   assign mem_fencei_MPORT_19_addr = 3'h4;
   assign mem_fencei_MPORT_19_mask = 1'h1;
-  assign mem_fencei_MPORT_19_en = ivalid & _GEN_1229;
+  assign mem_fencei_MPORT_19_en = ivalid & _GEN_1164;
   assign mem_fencei_MPORT_20_data = io_in_bits_0_bits_fencei;
   assign mem_fencei_MPORT_20_addr = 3'h5;
   assign mem_fencei_MPORT_20_mask = 1'h1;
@@ -18628,15 +17147,15 @@
   assign mem_fencei_MPORT_21_data = io_in_bits_1_bits_fencei;
   assign mem_fencei_MPORT_21_addr = 3'h5;
   assign mem_fencei_MPORT_21_mask = 1'h1;
-  assign mem_fencei_MPORT_21_en = ivalid & _GEN_1457;
+  assign mem_fencei_MPORT_21_en = ivalid & _GEN_1380;
   assign mem_fencei_MPORT_22_data = io_in_bits_2_bits_fencei;
   assign mem_fencei_MPORT_22_addr = 3'h5;
   assign mem_fencei_MPORT_22_mask = 1'h1;
-  assign mem_fencei_MPORT_22_en = ivalid & _GEN_1476;
+  assign mem_fencei_MPORT_22_en = ivalid & _GEN_1398;
   assign mem_fencei_MPORT_23_data = io_in_bits_3_bits_fencei;
   assign mem_fencei_MPORT_23_addr = 3'h5;
   assign mem_fencei_MPORT_23_mask = 1'h1;
-  assign mem_fencei_MPORT_23_en = ivalid & _GEN_1495;
+  assign mem_fencei_MPORT_23_en = ivalid & _GEN_1416;
   assign mem_fencei_MPORT_24_data = io_in_bits_0_bits_fencei;
   assign mem_fencei_MPORT_24_addr = 3'h6;
   assign mem_fencei_MPORT_24_mask = 1'h1;
@@ -18644,21 +17163,21 @@
   assign mem_fencei_MPORT_25_data = io_in_bits_1_bits_fencei;
   assign mem_fencei_MPORT_25_addr = 3'h6;
   assign mem_fencei_MPORT_25_mask = 1'h1;
-  assign mem_fencei_MPORT_25_en = ivalid & _GEN_1723;
+  assign mem_fencei_MPORT_25_en = ivalid & _GEN_1632;
   assign mem_fencei_MPORT_26_data = io_in_bits_2_bits_fencei;
   assign mem_fencei_MPORT_26_addr = 3'h6;
   assign mem_fencei_MPORT_26_mask = 1'h1;
-  assign mem_fencei_MPORT_26_en = ivalid & _GEN_1742;
+  assign mem_fencei_MPORT_26_en = ivalid & _GEN_1650;
   assign mem_fencei_MPORT_27_data = io_in_bits_3_bits_fencei;
   assign mem_fencei_MPORT_27_addr = 3'h6;
   assign mem_fencei_MPORT_27_mask = 1'h1;
-  assign mem_fencei_MPORT_27_en = ivalid & _GEN_1761;
+  assign mem_fencei_MPORT_27_en = ivalid & _GEN_1668;
   assign mem_flushat_mslice_io_in_bits_MPORT_en = mcount > 4'h0;
   assign mem_flushat_mslice_io_in_bits_MPORT_addr = outpos;
   `ifndef RANDOMIZE_GARBAGE_ASSIGN
   assign mem_flushat_mslice_io_in_bits_MPORT_data = mem_flushat[mem_flushat_mslice_io_in_bits_MPORT_addr]; // @[Fifo4.scala 59:16]
   `else
-  assign mem_flushat_mslice_io_in_bits_MPORT_data = mem_flushat_mslice_io_in_bits_MPORT_addr >= 3'h7 ? _RAND_21[0:0] :
+  assign mem_flushat_mslice_io_in_bits_MPORT_data = mem_flushat_mslice_io_in_bits_MPORT_addr >= 3'h7 ? _RAND_19[0:0] :
     mem_flushat[mem_flushat_mslice_io_in_bits_MPORT_addr]; // @[Fifo4.scala 59:16]
   `endif // RANDOMIZE_GARBAGE_ASSIGN
   assign mem_flushat_MPORT_data = io_in_bits_0_bits_flushat;
@@ -18668,15 +17187,15 @@
   assign mem_flushat_MPORT_1_data = io_in_bits_1_bits_flushat;
   assign mem_flushat_MPORT_1_addr = 3'h0;
   assign mem_flushat_MPORT_1_mask = 1'h1;
-  assign mem_flushat_MPORT_1_en = ivalid & _GEN_141;
+  assign mem_flushat_MPORT_1_en = ivalid & _GEN_134;
   assign mem_flushat_MPORT_2_data = io_in_bits_2_bits_flushat;
   assign mem_flushat_MPORT_2_addr = 3'h0;
   assign mem_flushat_MPORT_2_mask = 1'h1;
-  assign mem_flushat_MPORT_2_en = ivalid & _GEN_160;
+  assign mem_flushat_MPORT_2_en = ivalid & _GEN_152;
   assign mem_flushat_MPORT_3_data = io_in_bits_3_bits_flushat;
   assign mem_flushat_MPORT_3_addr = 3'h0;
   assign mem_flushat_MPORT_3_mask = 1'h1;
-  assign mem_flushat_MPORT_3_en = ivalid & _GEN_179;
+  assign mem_flushat_MPORT_3_en = ivalid & _GEN_170;
   assign mem_flushat_MPORT_4_data = io_in_bits_0_bits_flushat;
   assign mem_flushat_MPORT_4_addr = 3'h1;
   assign mem_flushat_MPORT_4_mask = 1'h1;
@@ -18684,15 +17203,15 @@
   assign mem_flushat_MPORT_5_data = io_in_bits_1_bits_flushat;
   assign mem_flushat_MPORT_5_addr = 3'h1;
   assign mem_flushat_MPORT_5_mask = 1'h1;
-  assign mem_flushat_MPORT_5_en = ivalid & _GEN_400;
+  assign mem_flushat_MPORT_5_en = ivalid & _GEN_379;
   assign mem_flushat_MPORT_6_data = io_in_bits_2_bits_flushat;
   assign mem_flushat_MPORT_6_addr = 3'h1;
   assign mem_flushat_MPORT_6_mask = 1'h1;
-  assign mem_flushat_MPORT_6_en = ivalid & _GEN_418;
+  assign mem_flushat_MPORT_6_en = ivalid & _GEN_396;
   assign mem_flushat_MPORT_7_data = io_in_bits_3_bits_flushat;
   assign mem_flushat_MPORT_7_addr = 3'h1;
   assign mem_flushat_MPORT_7_mask = 1'h1;
-  assign mem_flushat_MPORT_7_en = ivalid & _GEN_436;
+  assign mem_flushat_MPORT_7_en = ivalid & _GEN_413;
   assign mem_flushat_MPORT_8_data = io_in_bits_0_bits_flushat;
   assign mem_flushat_MPORT_8_addr = 3'h2;
   assign mem_flushat_MPORT_8_mask = 1'h1;
@@ -18700,15 +17219,15 @@
   assign mem_flushat_MPORT_9_data = io_in_bits_1_bits_flushat;
   assign mem_flushat_MPORT_9_addr = 3'h2;
   assign mem_flushat_MPORT_9_mask = 1'h1;
-  assign mem_flushat_MPORT_9_en = ivalid & _GEN_659;
+  assign mem_flushat_MPORT_9_en = ivalid & _GEN_624;
   assign mem_flushat_MPORT_10_data = io_in_bits_2_bits_flushat;
   assign mem_flushat_MPORT_10_addr = 3'h2;
   assign mem_flushat_MPORT_10_mask = 1'h1;
-  assign mem_flushat_MPORT_10_en = ivalid & _GEN_678;
+  assign mem_flushat_MPORT_10_en = ivalid & _GEN_642;
   assign mem_flushat_MPORT_11_data = io_in_bits_3_bits_flushat;
   assign mem_flushat_MPORT_11_addr = 3'h2;
   assign mem_flushat_MPORT_11_mask = 1'h1;
-  assign mem_flushat_MPORT_11_en = ivalid & _GEN_697;
+  assign mem_flushat_MPORT_11_en = ivalid & _GEN_660;
   assign mem_flushat_MPORT_12_data = io_in_bits_0_bits_flushat;
   assign mem_flushat_MPORT_12_addr = 3'h3;
   assign mem_flushat_MPORT_12_mask = 1'h1;
@@ -18716,15 +17235,15 @@
   assign mem_flushat_MPORT_13_data = io_in_bits_1_bits_flushat;
   assign mem_flushat_MPORT_13_addr = 3'h3;
   assign mem_flushat_MPORT_13_mask = 1'h1;
-  assign mem_flushat_MPORT_13_en = ivalid & _GEN_925;
+  assign mem_flushat_MPORT_13_en = ivalid & _GEN_876;
   assign mem_flushat_MPORT_14_data = io_in_bits_2_bits_flushat;
   assign mem_flushat_MPORT_14_addr = 3'h3;
   assign mem_flushat_MPORT_14_mask = 1'h1;
-  assign mem_flushat_MPORT_14_en = ivalid & _GEN_944;
+  assign mem_flushat_MPORT_14_en = ivalid & _GEN_894;
   assign mem_flushat_MPORT_15_data = io_in_bits_3_bits_flushat;
   assign mem_flushat_MPORT_15_addr = 3'h3;
   assign mem_flushat_MPORT_15_mask = 1'h1;
-  assign mem_flushat_MPORT_15_en = ivalid & _GEN_963;
+  assign mem_flushat_MPORT_15_en = ivalid & _GEN_912;
   assign mem_flushat_MPORT_16_data = io_in_bits_0_bits_flushat;
   assign mem_flushat_MPORT_16_addr = 3'h4;
   assign mem_flushat_MPORT_16_mask = 1'h1;
@@ -18732,15 +17251,15 @@
   assign mem_flushat_MPORT_17_data = io_in_bits_1_bits_flushat;
   assign mem_flushat_MPORT_17_addr = 3'h4;
   assign mem_flushat_MPORT_17_mask = 1'h1;
-  assign mem_flushat_MPORT_17_en = ivalid & _GEN_1191;
+  assign mem_flushat_MPORT_17_en = ivalid & _GEN_1128;
   assign mem_flushat_MPORT_18_data = io_in_bits_2_bits_flushat;
   assign mem_flushat_MPORT_18_addr = 3'h4;
   assign mem_flushat_MPORT_18_mask = 1'h1;
-  assign mem_flushat_MPORT_18_en = ivalid & _GEN_1210;
+  assign mem_flushat_MPORT_18_en = ivalid & _GEN_1146;
   assign mem_flushat_MPORT_19_data = io_in_bits_3_bits_flushat;
   assign mem_flushat_MPORT_19_addr = 3'h4;
   assign mem_flushat_MPORT_19_mask = 1'h1;
-  assign mem_flushat_MPORT_19_en = ivalid & _GEN_1229;
+  assign mem_flushat_MPORT_19_en = ivalid & _GEN_1164;
   assign mem_flushat_MPORT_20_data = io_in_bits_0_bits_flushat;
   assign mem_flushat_MPORT_20_addr = 3'h5;
   assign mem_flushat_MPORT_20_mask = 1'h1;
@@ -18748,15 +17267,15 @@
   assign mem_flushat_MPORT_21_data = io_in_bits_1_bits_flushat;
   assign mem_flushat_MPORT_21_addr = 3'h5;
   assign mem_flushat_MPORT_21_mask = 1'h1;
-  assign mem_flushat_MPORT_21_en = ivalid & _GEN_1457;
+  assign mem_flushat_MPORT_21_en = ivalid & _GEN_1380;
   assign mem_flushat_MPORT_22_data = io_in_bits_2_bits_flushat;
   assign mem_flushat_MPORT_22_addr = 3'h5;
   assign mem_flushat_MPORT_22_mask = 1'h1;
-  assign mem_flushat_MPORT_22_en = ivalid & _GEN_1476;
+  assign mem_flushat_MPORT_22_en = ivalid & _GEN_1398;
   assign mem_flushat_MPORT_23_data = io_in_bits_3_bits_flushat;
   assign mem_flushat_MPORT_23_addr = 3'h5;
   assign mem_flushat_MPORT_23_mask = 1'h1;
-  assign mem_flushat_MPORT_23_en = ivalid & _GEN_1495;
+  assign mem_flushat_MPORT_23_en = ivalid & _GEN_1416;
   assign mem_flushat_MPORT_24_data = io_in_bits_0_bits_flushat;
   assign mem_flushat_MPORT_24_addr = 3'h6;
   assign mem_flushat_MPORT_24_mask = 1'h1;
@@ -18764,21 +17283,21 @@
   assign mem_flushat_MPORT_25_data = io_in_bits_1_bits_flushat;
   assign mem_flushat_MPORT_25_addr = 3'h6;
   assign mem_flushat_MPORT_25_mask = 1'h1;
-  assign mem_flushat_MPORT_25_en = ivalid & _GEN_1723;
+  assign mem_flushat_MPORT_25_en = ivalid & _GEN_1632;
   assign mem_flushat_MPORT_26_data = io_in_bits_2_bits_flushat;
   assign mem_flushat_MPORT_26_addr = 3'h6;
   assign mem_flushat_MPORT_26_mask = 1'h1;
-  assign mem_flushat_MPORT_26_en = ivalid & _GEN_1742;
+  assign mem_flushat_MPORT_26_en = ivalid & _GEN_1650;
   assign mem_flushat_MPORT_27_data = io_in_bits_3_bits_flushat;
   assign mem_flushat_MPORT_27_addr = 3'h6;
   assign mem_flushat_MPORT_27_mask = 1'h1;
-  assign mem_flushat_MPORT_27_en = ivalid & _GEN_1761;
+  assign mem_flushat_MPORT_27_en = ivalid & _GEN_1668;
   assign mem_flushall_mslice_io_in_bits_MPORT_en = mcount > 4'h0;
   assign mem_flushall_mslice_io_in_bits_MPORT_addr = outpos;
   `ifndef RANDOMIZE_GARBAGE_ASSIGN
   assign mem_flushall_mslice_io_in_bits_MPORT_data = mem_flushall[mem_flushall_mslice_io_in_bits_MPORT_addr]; // @[Fifo4.scala 59:16]
   `else
-  assign mem_flushall_mslice_io_in_bits_MPORT_data = mem_flushall_mslice_io_in_bits_MPORT_addr >= 3'h7 ? _RAND_23[0:0]
+  assign mem_flushall_mslice_io_in_bits_MPORT_data = mem_flushall_mslice_io_in_bits_MPORT_addr >= 3'h7 ? _RAND_21[0:0]
      : mem_flushall[mem_flushall_mslice_io_in_bits_MPORT_addr]; // @[Fifo4.scala 59:16]
   `endif // RANDOMIZE_GARBAGE_ASSIGN
   assign mem_flushall_MPORT_data = io_in_bits_0_bits_flushall;
@@ -18788,15 +17307,15 @@
   assign mem_flushall_MPORT_1_data = io_in_bits_1_bits_flushall;
   assign mem_flushall_MPORT_1_addr = 3'h0;
   assign mem_flushall_MPORT_1_mask = 1'h1;
-  assign mem_flushall_MPORT_1_en = ivalid & _GEN_141;
+  assign mem_flushall_MPORT_1_en = ivalid & _GEN_134;
   assign mem_flushall_MPORT_2_data = io_in_bits_2_bits_flushall;
   assign mem_flushall_MPORT_2_addr = 3'h0;
   assign mem_flushall_MPORT_2_mask = 1'h1;
-  assign mem_flushall_MPORT_2_en = ivalid & _GEN_160;
+  assign mem_flushall_MPORT_2_en = ivalid & _GEN_152;
   assign mem_flushall_MPORT_3_data = io_in_bits_3_bits_flushall;
   assign mem_flushall_MPORT_3_addr = 3'h0;
   assign mem_flushall_MPORT_3_mask = 1'h1;
-  assign mem_flushall_MPORT_3_en = ivalid & _GEN_179;
+  assign mem_flushall_MPORT_3_en = ivalid & _GEN_170;
   assign mem_flushall_MPORT_4_data = io_in_bits_0_bits_flushall;
   assign mem_flushall_MPORT_4_addr = 3'h1;
   assign mem_flushall_MPORT_4_mask = 1'h1;
@@ -18804,15 +17323,15 @@
   assign mem_flushall_MPORT_5_data = io_in_bits_1_bits_flushall;
   assign mem_flushall_MPORT_5_addr = 3'h1;
   assign mem_flushall_MPORT_5_mask = 1'h1;
-  assign mem_flushall_MPORT_5_en = ivalid & _GEN_400;
+  assign mem_flushall_MPORT_5_en = ivalid & _GEN_379;
   assign mem_flushall_MPORT_6_data = io_in_bits_2_bits_flushall;
   assign mem_flushall_MPORT_6_addr = 3'h1;
   assign mem_flushall_MPORT_6_mask = 1'h1;
-  assign mem_flushall_MPORT_6_en = ivalid & _GEN_418;
+  assign mem_flushall_MPORT_6_en = ivalid & _GEN_396;
   assign mem_flushall_MPORT_7_data = io_in_bits_3_bits_flushall;
   assign mem_flushall_MPORT_7_addr = 3'h1;
   assign mem_flushall_MPORT_7_mask = 1'h1;
-  assign mem_flushall_MPORT_7_en = ivalid & _GEN_436;
+  assign mem_flushall_MPORT_7_en = ivalid & _GEN_413;
   assign mem_flushall_MPORT_8_data = io_in_bits_0_bits_flushall;
   assign mem_flushall_MPORT_8_addr = 3'h2;
   assign mem_flushall_MPORT_8_mask = 1'h1;
@@ -18820,15 +17339,15 @@
   assign mem_flushall_MPORT_9_data = io_in_bits_1_bits_flushall;
   assign mem_flushall_MPORT_9_addr = 3'h2;
   assign mem_flushall_MPORT_9_mask = 1'h1;
-  assign mem_flushall_MPORT_9_en = ivalid & _GEN_659;
+  assign mem_flushall_MPORT_9_en = ivalid & _GEN_624;
   assign mem_flushall_MPORT_10_data = io_in_bits_2_bits_flushall;
   assign mem_flushall_MPORT_10_addr = 3'h2;
   assign mem_flushall_MPORT_10_mask = 1'h1;
-  assign mem_flushall_MPORT_10_en = ivalid & _GEN_678;
+  assign mem_flushall_MPORT_10_en = ivalid & _GEN_642;
   assign mem_flushall_MPORT_11_data = io_in_bits_3_bits_flushall;
   assign mem_flushall_MPORT_11_addr = 3'h2;
   assign mem_flushall_MPORT_11_mask = 1'h1;
-  assign mem_flushall_MPORT_11_en = ivalid & _GEN_697;
+  assign mem_flushall_MPORT_11_en = ivalid & _GEN_660;
   assign mem_flushall_MPORT_12_data = io_in_bits_0_bits_flushall;
   assign mem_flushall_MPORT_12_addr = 3'h3;
   assign mem_flushall_MPORT_12_mask = 1'h1;
@@ -18836,15 +17355,15 @@
   assign mem_flushall_MPORT_13_data = io_in_bits_1_bits_flushall;
   assign mem_flushall_MPORT_13_addr = 3'h3;
   assign mem_flushall_MPORT_13_mask = 1'h1;
-  assign mem_flushall_MPORT_13_en = ivalid & _GEN_925;
+  assign mem_flushall_MPORT_13_en = ivalid & _GEN_876;
   assign mem_flushall_MPORT_14_data = io_in_bits_2_bits_flushall;
   assign mem_flushall_MPORT_14_addr = 3'h3;
   assign mem_flushall_MPORT_14_mask = 1'h1;
-  assign mem_flushall_MPORT_14_en = ivalid & _GEN_944;
+  assign mem_flushall_MPORT_14_en = ivalid & _GEN_894;
   assign mem_flushall_MPORT_15_data = io_in_bits_3_bits_flushall;
   assign mem_flushall_MPORT_15_addr = 3'h3;
   assign mem_flushall_MPORT_15_mask = 1'h1;
-  assign mem_flushall_MPORT_15_en = ivalid & _GEN_963;
+  assign mem_flushall_MPORT_15_en = ivalid & _GEN_912;
   assign mem_flushall_MPORT_16_data = io_in_bits_0_bits_flushall;
   assign mem_flushall_MPORT_16_addr = 3'h4;
   assign mem_flushall_MPORT_16_mask = 1'h1;
@@ -18852,15 +17371,15 @@
   assign mem_flushall_MPORT_17_data = io_in_bits_1_bits_flushall;
   assign mem_flushall_MPORT_17_addr = 3'h4;
   assign mem_flushall_MPORT_17_mask = 1'h1;
-  assign mem_flushall_MPORT_17_en = ivalid & _GEN_1191;
+  assign mem_flushall_MPORT_17_en = ivalid & _GEN_1128;
   assign mem_flushall_MPORT_18_data = io_in_bits_2_bits_flushall;
   assign mem_flushall_MPORT_18_addr = 3'h4;
   assign mem_flushall_MPORT_18_mask = 1'h1;
-  assign mem_flushall_MPORT_18_en = ivalid & _GEN_1210;
+  assign mem_flushall_MPORT_18_en = ivalid & _GEN_1146;
   assign mem_flushall_MPORT_19_data = io_in_bits_3_bits_flushall;
   assign mem_flushall_MPORT_19_addr = 3'h4;
   assign mem_flushall_MPORT_19_mask = 1'h1;
-  assign mem_flushall_MPORT_19_en = ivalid & _GEN_1229;
+  assign mem_flushall_MPORT_19_en = ivalid & _GEN_1164;
   assign mem_flushall_MPORT_20_data = io_in_bits_0_bits_flushall;
   assign mem_flushall_MPORT_20_addr = 3'h5;
   assign mem_flushall_MPORT_20_mask = 1'h1;
@@ -18868,15 +17387,15 @@
   assign mem_flushall_MPORT_21_data = io_in_bits_1_bits_flushall;
   assign mem_flushall_MPORT_21_addr = 3'h5;
   assign mem_flushall_MPORT_21_mask = 1'h1;
-  assign mem_flushall_MPORT_21_en = ivalid & _GEN_1457;
+  assign mem_flushall_MPORT_21_en = ivalid & _GEN_1380;
   assign mem_flushall_MPORT_22_data = io_in_bits_2_bits_flushall;
   assign mem_flushall_MPORT_22_addr = 3'h5;
   assign mem_flushall_MPORT_22_mask = 1'h1;
-  assign mem_flushall_MPORT_22_en = ivalid & _GEN_1476;
+  assign mem_flushall_MPORT_22_en = ivalid & _GEN_1398;
   assign mem_flushall_MPORT_23_data = io_in_bits_3_bits_flushall;
   assign mem_flushall_MPORT_23_addr = 3'h5;
   assign mem_flushall_MPORT_23_mask = 1'h1;
-  assign mem_flushall_MPORT_23_en = ivalid & _GEN_1495;
+  assign mem_flushall_MPORT_23_en = ivalid & _GEN_1416;
   assign mem_flushall_MPORT_24_data = io_in_bits_0_bits_flushall;
   assign mem_flushall_MPORT_24_addr = 3'h6;
   assign mem_flushall_MPORT_24_mask = 1'h1;
@@ -18884,21 +17403,21 @@
   assign mem_flushall_MPORT_25_data = io_in_bits_1_bits_flushall;
   assign mem_flushall_MPORT_25_addr = 3'h6;
   assign mem_flushall_MPORT_25_mask = 1'h1;
-  assign mem_flushall_MPORT_25_en = ivalid & _GEN_1723;
+  assign mem_flushall_MPORT_25_en = ivalid & _GEN_1632;
   assign mem_flushall_MPORT_26_data = io_in_bits_2_bits_flushall;
   assign mem_flushall_MPORT_26_addr = 3'h6;
   assign mem_flushall_MPORT_26_mask = 1'h1;
-  assign mem_flushall_MPORT_26_en = ivalid & _GEN_1742;
+  assign mem_flushall_MPORT_26_en = ivalid & _GEN_1650;
   assign mem_flushall_MPORT_27_data = io_in_bits_3_bits_flushall;
   assign mem_flushall_MPORT_27_addr = 3'h6;
   assign mem_flushall_MPORT_27_mask = 1'h1;
-  assign mem_flushall_MPORT_27_en = ivalid & _GEN_1761;
+  assign mem_flushall_MPORT_27_en = ivalid & _GEN_1668;
   assign mem_sldst_mslice_io_in_bits_MPORT_en = mcount > 4'h0;
   assign mem_sldst_mslice_io_in_bits_MPORT_addr = outpos;
   `ifndef RANDOMIZE_GARBAGE_ASSIGN
   assign mem_sldst_mslice_io_in_bits_MPORT_data = mem_sldst[mem_sldst_mslice_io_in_bits_MPORT_addr]; // @[Fifo4.scala 59:16]
   `else
-  assign mem_sldst_mslice_io_in_bits_MPORT_data = mem_sldst_mslice_io_in_bits_MPORT_addr >= 3'h7 ? _RAND_25[0:0] :
+  assign mem_sldst_mslice_io_in_bits_MPORT_data = mem_sldst_mslice_io_in_bits_MPORT_addr >= 3'h7 ? _RAND_23[0:0] :
     mem_sldst[mem_sldst_mslice_io_in_bits_MPORT_addr]; // @[Fifo4.scala 59:16]
   `endif // RANDOMIZE_GARBAGE_ASSIGN
   assign mem_sldst_MPORT_data = io_in_bits_0_bits_sldst;
@@ -18908,15 +17427,15 @@
   assign mem_sldst_MPORT_1_data = io_in_bits_1_bits_sldst;
   assign mem_sldst_MPORT_1_addr = 3'h0;
   assign mem_sldst_MPORT_1_mask = 1'h1;
-  assign mem_sldst_MPORT_1_en = ivalid & _GEN_141;
+  assign mem_sldst_MPORT_1_en = ivalid & _GEN_134;
   assign mem_sldst_MPORT_2_data = io_in_bits_2_bits_sldst;
   assign mem_sldst_MPORT_2_addr = 3'h0;
   assign mem_sldst_MPORT_2_mask = 1'h1;
-  assign mem_sldst_MPORT_2_en = ivalid & _GEN_160;
+  assign mem_sldst_MPORT_2_en = ivalid & _GEN_152;
   assign mem_sldst_MPORT_3_data = io_in_bits_3_bits_sldst;
   assign mem_sldst_MPORT_3_addr = 3'h0;
   assign mem_sldst_MPORT_3_mask = 1'h1;
-  assign mem_sldst_MPORT_3_en = ivalid & _GEN_179;
+  assign mem_sldst_MPORT_3_en = ivalid & _GEN_170;
   assign mem_sldst_MPORT_4_data = io_in_bits_0_bits_sldst;
   assign mem_sldst_MPORT_4_addr = 3'h1;
   assign mem_sldst_MPORT_4_mask = 1'h1;
@@ -18924,15 +17443,15 @@
   assign mem_sldst_MPORT_5_data = io_in_bits_1_bits_sldst;
   assign mem_sldst_MPORT_5_addr = 3'h1;
   assign mem_sldst_MPORT_5_mask = 1'h1;
-  assign mem_sldst_MPORT_5_en = ivalid & _GEN_400;
+  assign mem_sldst_MPORT_5_en = ivalid & _GEN_379;
   assign mem_sldst_MPORT_6_data = io_in_bits_2_bits_sldst;
   assign mem_sldst_MPORT_6_addr = 3'h1;
   assign mem_sldst_MPORT_6_mask = 1'h1;
-  assign mem_sldst_MPORT_6_en = ivalid & _GEN_418;
+  assign mem_sldst_MPORT_6_en = ivalid & _GEN_396;
   assign mem_sldst_MPORT_7_data = io_in_bits_3_bits_sldst;
   assign mem_sldst_MPORT_7_addr = 3'h1;
   assign mem_sldst_MPORT_7_mask = 1'h1;
-  assign mem_sldst_MPORT_7_en = ivalid & _GEN_436;
+  assign mem_sldst_MPORT_7_en = ivalid & _GEN_413;
   assign mem_sldst_MPORT_8_data = io_in_bits_0_bits_sldst;
   assign mem_sldst_MPORT_8_addr = 3'h2;
   assign mem_sldst_MPORT_8_mask = 1'h1;
@@ -18940,15 +17459,15 @@
   assign mem_sldst_MPORT_9_data = io_in_bits_1_bits_sldst;
   assign mem_sldst_MPORT_9_addr = 3'h2;
   assign mem_sldst_MPORT_9_mask = 1'h1;
-  assign mem_sldst_MPORT_9_en = ivalid & _GEN_659;
+  assign mem_sldst_MPORT_9_en = ivalid & _GEN_624;
   assign mem_sldst_MPORT_10_data = io_in_bits_2_bits_sldst;
   assign mem_sldst_MPORT_10_addr = 3'h2;
   assign mem_sldst_MPORT_10_mask = 1'h1;
-  assign mem_sldst_MPORT_10_en = ivalid & _GEN_678;
+  assign mem_sldst_MPORT_10_en = ivalid & _GEN_642;
   assign mem_sldst_MPORT_11_data = io_in_bits_3_bits_sldst;
   assign mem_sldst_MPORT_11_addr = 3'h2;
   assign mem_sldst_MPORT_11_mask = 1'h1;
-  assign mem_sldst_MPORT_11_en = ivalid & _GEN_697;
+  assign mem_sldst_MPORT_11_en = ivalid & _GEN_660;
   assign mem_sldst_MPORT_12_data = io_in_bits_0_bits_sldst;
   assign mem_sldst_MPORT_12_addr = 3'h3;
   assign mem_sldst_MPORT_12_mask = 1'h1;
@@ -18956,15 +17475,15 @@
   assign mem_sldst_MPORT_13_data = io_in_bits_1_bits_sldst;
   assign mem_sldst_MPORT_13_addr = 3'h3;
   assign mem_sldst_MPORT_13_mask = 1'h1;
-  assign mem_sldst_MPORT_13_en = ivalid & _GEN_925;
+  assign mem_sldst_MPORT_13_en = ivalid & _GEN_876;
   assign mem_sldst_MPORT_14_data = io_in_bits_2_bits_sldst;
   assign mem_sldst_MPORT_14_addr = 3'h3;
   assign mem_sldst_MPORT_14_mask = 1'h1;
-  assign mem_sldst_MPORT_14_en = ivalid & _GEN_944;
+  assign mem_sldst_MPORT_14_en = ivalid & _GEN_894;
   assign mem_sldst_MPORT_15_data = io_in_bits_3_bits_sldst;
   assign mem_sldst_MPORT_15_addr = 3'h3;
   assign mem_sldst_MPORT_15_mask = 1'h1;
-  assign mem_sldst_MPORT_15_en = ivalid & _GEN_963;
+  assign mem_sldst_MPORT_15_en = ivalid & _GEN_912;
   assign mem_sldst_MPORT_16_data = io_in_bits_0_bits_sldst;
   assign mem_sldst_MPORT_16_addr = 3'h4;
   assign mem_sldst_MPORT_16_mask = 1'h1;
@@ -18972,15 +17491,15 @@
   assign mem_sldst_MPORT_17_data = io_in_bits_1_bits_sldst;
   assign mem_sldst_MPORT_17_addr = 3'h4;
   assign mem_sldst_MPORT_17_mask = 1'h1;
-  assign mem_sldst_MPORT_17_en = ivalid & _GEN_1191;
+  assign mem_sldst_MPORT_17_en = ivalid & _GEN_1128;
   assign mem_sldst_MPORT_18_data = io_in_bits_2_bits_sldst;
   assign mem_sldst_MPORT_18_addr = 3'h4;
   assign mem_sldst_MPORT_18_mask = 1'h1;
-  assign mem_sldst_MPORT_18_en = ivalid & _GEN_1210;
+  assign mem_sldst_MPORT_18_en = ivalid & _GEN_1146;
   assign mem_sldst_MPORT_19_data = io_in_bits_3_bits_sldst;
   assign mem_sldst_MPORT_19_addr = 3'h4;
   assign mem_sldst_MPORT_19_mask = 1'h1;
-  assign mem_sldst_MPORT_19_en = ivalid & _GEN_1229;
+  assign mem_sldst_MPORT_19_en = ivalid & _GEN_1164;
   assign mem_sldst_MPORT_20_data = io_in_bits_0_bits_sldst;
   assign mem_sldst_MPORT_20_addr = 3'h5;
   assign mem_sldst_MPORT_20_mask = 1'h1;
@@ -18988,15 +17507,15 @@
   assign mem_sldst_MPORT_21_data = io_in_bits_1_bits_sldst;
   assign mem_sldst_MPORT_21_addr = 3'h5;
   assign mem_sldst_MPORT_21_mask = 1'h1;
-  assign mem_sldst_MPORT_21_en = ivalid & _GEN_1457;
+  assign mem_sldst_MPORT_21_en = ivalid & _GEN_1380;
   assign mem_sldst_MPORT_22_data = io_in_bits_2_bits_sldst;
   assign mem_sldst_MPORT_22_addr = 3'h5;
   assign mem_sldst_MPORT_22_mask = 1'h1;
-  assign mem_sldst_MPORT_22_en = ivalid & _GEN_1476;
+  assign mem_sldst_MPORT_22_en = ivalid & _GEN_1398;
   assign mem_sldst_MPORT_23_data = io_in_bits_3_bits_sldst;
   assign mem_sldst_MPORT_23_addr = 3'h5;
   assign mem_sldst_MPORT_23_mask = 1'h1;
-  assign mem_sldst_MPORT_23_en = ivalid & _GEN_1495;
+  assign mem_sldst_MPORT_23_en = ivalid & _GEN_1416;
   assign mem_sldst_MPORT_24_data = io_in_bits_0_bits_sldst;
   assign mem_sldst_MPORT_24_addr = 3'h6;
   assign mem_sldst_MPORT_24_mask = 1'h1;
@@ -19004,21 +17523,21 @@
   assign mem_sldst_MPORT_25_data = io_in_bits_1_bits_sldst;
   assign mem_sldst_MPORT_25_addr = 3'h6;
   assign mem_sldst_MPORT_25_mask = 1'h1;
-  assign mem_sldst_MPORT_25_en = ivalid & _GEN_1723;
+  assign mem_sldst_MPORT_25_en = ivalid & _GEN_1632;
   assign mem_sldst_MPORT_26_data = io_in_bits_2_bits_sldst;
   assign mem_sldst_MPORT_26_addr = 3'h6;
   assign mem_sldst_MPORT_26_mask = 1'h1;
-  assign mem_sldst_MPORT_26_en = ivalid & _GEN_1742;
+  assign mem_sldst_MPORT_26_en = ivalid & _GEN_1650;
   assign mem_sldst_MPORT_27_data = io_in_bits_3_bits_sldst;
   assign mem_sldst_MPORT_27_addr = 3'h6;
   assign mem_sldst_MPORT_27_mask = 1'h1;
-  assign mem_sldst_MPORT_27_en = ivalid & _GEN_1761;
+  assign mem_sldst_MPORT_27_en = ivalid & _GEN_1668;
   assign mem_vldst_mslice_io_in_bits_MPORT_en = mcount > 4'h0;
   assign mem_vldst_mslice_io_in_bits_MPORT_addr = outpos;
   `ifndef RANDOMIZE_GARBAGE_ASSIGN
   assign mem_vldst_mslice_io_in_bits_MPORT_data = mem_vldst[mem_vldst_mslice_io_in_bits_MPORT_addr]; // @[Fifo4.scala 59:16]
   `else
-  assign mem_vldst_mslice_io_in_bits_MPORT_data = mem_vldst_mslice_io_in_bits_MPORT_addr >= 3'h7 ? _RAND_27[0:0] :
+  assign mem_vldst_mslice_io_in_bits_MPORT_data = mem_vldst_mslice_io_in_bits_MPORT_addr >= 3'h7 ? _RAND_25[0:0] :
     mem_vldst[mem_vldst_mslice_io_in_bits_MPORT_addr]; // @[Fifo4.scala 59:16]
   `endif // RANDOMIZE_GARBAGE_ASSIGN
   assign mem_vldst_MPORT_data = io_in_bits_0_bits_vldst;
@@ -19028,15 +17547,15 @@
   assign mem_vldst_MPORT_1_data = io_in_bits_1_bits_vldst;
   assign mem_vldst_MPORT_1_addr = 3'h0;
   assign mem_vldst_MPORT_1_mask = 1'h1;
-  assign mem_vldst_MPORT_1_en = ivalid & _GEN_141;
+  assign mem_vldst_MPORT_1_en = ivalid & _GEN_134;
   assign mem_vldst_MPORT_2_data = io_in_bits_2_bits_vldst;
   assign mem_vldst_MPORT_2_addr = 3'h0;
   assign mem_vldst_MPORT_2_mask = 1'h1;
-  assign mem_vldst_MPORT_2_en = ivalid & _GEN_160;
+  assign mem_vldst_MPORT_2_en = ivalid & _GEN_152;
   assign mem_vldst_MPORT_3_data = io_in_bits_3_bits_vldst;
   assign mem_vldst_MPORT_3_addr = 3'h0;
   assign mem_vldst_MPORT_3_mask = 1'h1;
-  assign mem_vldst_MPORT_3_en = ivalid & _GEN_179;
+  assign mem_vldst_MPORT_3_en = ivalid & _GEN_170;
   assign mem_vldst_MPORT_4_data = io_in_bits_0_bits_vldst;
   assign mem_vldst_MPORT_4_addr = 3'h1;
   assign mem_vldst_MPORT_4_mask = 1'h1;
@@ -19044,15 +17563,15 @@
   assign mem_vldst_MPORT_5_data = io_in_bits_1_bits_vldst;
   assign mem_vldst_MPORT_5_addr = 3'h1;
   assign mem_vldst_MPORT_5_mask = 1'h1;
-  assign mem_vldst_MPORT_5_en = ivalid & _GEN_400;
+  assign mem_vldst_MPORT_5_en = ivalid & _GEN_379;
   assign mem_vldst_MPORT_6_data = io_in_bits_2_bits_vldst;
   assign mem_vldst_MPORT_6_addr = 3'h1;
   assign mem_vldst_MPORT_6_mask = 1'h1;
-  assign mem_vldst_MPORT_6_en = ivalid & _GEN_418;
+  assign mem_vldst_MPORT_6_en = ivalid & _GEN_396;
   assign mem_vldst_MPORT_7_data = io_in_bits_3_bits_vldst;
   assign mem_vldst_MPORT_7_addr = 3'h1;
   assign mem_vldst_MPORT_7_mask = 1'h1;
-  assign mem_vldst_MPORT_7_en = ivalid & _GEN_436;
+  assign mem_vldst_MPORT_7_en = ivalid & _GEN_413;
   assign mem_vldst_MPORT_8_data = io_in_bits_0_bits_vldst;
   assign mem_vldst_MPORT_8_addr = 3'h2;
   assign mem_vldst_MPORT_8_mask = 1'h1;
@@ -19060,15 +17579,15 @@
   assign mem_vldst_MPORT_9_data = io_in_bits_1_bits_vldst;
   assign mem_vldst_MPORT_9_addr = 3'h2;
   assign mem_vldst_MPORT_9_mask = 1'h1;
-  assign mem_vldst_MPORT_9_en = ivalid & _GEN_659;
+  assign mem_vldst_MPORT_9_en = ivalid & _GEN_624;
   assign mem_vldst_MPORT_10_data = io_in_bits_2_bits_vldst;
   assign mem_vldst_MPORT_10_addr = 3'h2;
   assign mem_vldst_MPORT_10_mask = 1'h1;
-  assign mem_vldst_MPORT_10_en = ivalid & _GEN_678;
+  assign mem_vldst_MPORT_10_en = ivalid & _GEN_642;
   assign mem_vldst_MPORT_11_data = io_in_bits_3_bits_vldst;
   assign mem_vldst_MPORT_11_addr = 3'h2;
   assign mem_vldst_MPORT_11_mask = 1'h1;
-  assign mem_vldst_MPORT_11_en = ivalid & _GEN_697;
+  assign mem_vldst_MPORT_11_en = ivalid & _GEN_660;
   assign mem_vldst_MPORT_12_data = io_in_bits_0_bits_vldst;
   assign mem_vldst_MPORT_12_addr = 3'h3;
   assign mem_vldst_MPORT_12_mask = 1'h1;
@@ -19076,15 +17595,15 @@
   assign mem_vldst_MPORT_13_data = io_in_bits_1_bits_vldst;
   assign mem_vldst_MPORT_13_addr = 3'h3;
   assign mem_vldst_MPORT_13_mask = 1'h1;
-  assign mem_vldst_MPORT_13_en = ivalid & _GEN_925;
+  assign mem_vldst_MPORT_13_en = ivalid & _GEN_876;
   assign mem_vldst_MPORT_14_data = io_in_bits_2_bits_vldst;
   assign mem_vldst_MPORT_14_addr = 3'h3;
   assign mem_vldst_MPORT_14_mask = 1'h1;
-  assign mem_vldst_MPORT_14_en = ivalid & _GEN_944;
+  assign mem_vldst_MPORT_14_en = ivalid & _GEN_894;
   assign mem_vldst_MPORT_15_data = io_in_bits_3_bits_vldst;
   assign mem_vldst_MPORT_15_addr = 3'h3;
   assign mem_vldst_MPORT_15_mask = 1'h1;
-  assign mem_vldst_MPORT_15_en = ivalid & _GEN_963;
+  assign mem_vldst_MPORT_15_en = ivalid & _GEN_912;
   assign mem_vldst_MPORT_16_data = io_in_bits_0_bits_vldst;
   assign mem_vldst_MPORT_16_addr = 3'h4;
   assign mem_vldst_MPORT_16_mask = 1'h1;
@@ -19092,15 +17611,15 @@
   assign mem_vldst_MPORT_17_data = io_in_bits_1_bits_vldst;
   assign mem_vldst_MPORT_17_addr = 3'h4;
   assign mem_vldst_MPORT_17_mask = 1'h1;
-  assign mem_vldst_MPORT_17_en = ivalid & _GEN_1191;
+  assign mem_vldst_MPORT_17_en = ivalid & _GEN_1128;
   assign mem_vldst_MPORT_18_data = io_in_bits_2_bits_vldst;
   assign mem_vldst_MPORT_18_addr = 3'h4;
   assign mem_vldst_MPORT_18_mask = 1'h1;
-  assign mem_vldst_MPORT_18_en = ivalid & _GEN_1210;
+  assign mem_vldst_MPORT_18_en = ivalid & _GEN_1146;
   assign mem_vldst_MPORT_19_data = io_in_bits_3_bits_vldst;
   assign mem_vldst_MPORT_19_addr = 3'h4;
   assign mem_vldst_MPORT_19_mask = 1'h1;
-  assign mem_vldst_MPORT_19_en = ivalid & _GEN_1229;
+  assign mem_vldst_MPORT_19_en = ivalid & _GEN_1164;
   assign mem_vldst_MPORT_20_data = io_in_bits_0_bits_vldst;
   assign mem_vldst_MPORT_20_addr = 3'h5;
   assign mem_vldst_MPORT_20_mask = 1'h1;
@@ -19108,15 +17627,15 @@
   assign mem_vldst_MPORT_21_data = io_in_bits_1_bits_vldst;
   assign mem_vldst_MPORT_21_addr = 3'h5;
   assign mem_vldst_MPORT_21_mask = 1'h1;
-  assign mem_vldst_MPORT_21_en = ivalid & _GEN_1457;
+  assign mem_vldst_MPORT_21_en = ivalid & _GEN_1380;
   assign mem_vldst_MPORT_22_data = io_in_bits_2_bits_vldst;
   assign mem_vldst_MPORT_22_addr = 3'h5;
   assign mem_vldst_MPORT_22_mask = 1'h1;
-  assign mem_vldst_MPORT_22_en = ivalid & _GEN_1476;
+  assign mem_vldst_MPORT_22_en = ivalid & _GEN_1398;
   assign mem_vldst_MPORT_23_data = io_in_bits_3_bits_vldst;
   assign mem_vldst_MPORT_23_addr = 3'h5;
   assign mem_vldst_MPORT_23_mask = 1'h1;
-  assign mem_vldst_MPORT_23_en = ivalid & _GEN_1495;
+  assign mem_vldst_MPORT_23_en = ivalid & _GEN_1416;
   assign mem_vldst_MPORT_24_data = io_in_bits_0_bits_vldst;
   assign mem_vldst_MPORT_24_addr = 3'h6;
   assign mem_vldst_MPORT_24_mask = 1'h1;
@@ -19124,21 +17643,21 @@
   assign mem_vldst_MPORT_25_data = io_in_bits_1_bits_vldst;
   assign mem_vldst_MPORT_25_addr = 3'h6;
   assign mem_vldst_MPORT_25_mask = 1'h1;
-  assign mem_vldst_MPORT_25_en = ivalid & _GEN_1723;
+  assign mem_vldst_MPORT_25_en = ivalid & _GEN_1632;
   assign mem_vldst_MPORT_26_data = io_in_bits_2_bits_vldst;
   assign mem_vldst_MPORT_26_addr = 3'h6;
   assign mem_vldst_MPORT_26_mask = 1'h1;
-  assign mem_vldst_MPORT_26_en = ivalid & _GEN_1742;
+  assign mem_vldst_MPORT_26_en = ivalid & _GEN_1650;
   assign mem_vldst_MPORT_27_data = io_in_bits_3_bits_vldst;
   assign mem_vldst_MPORT_27_addr = 3'h6;
   assign mem_vldst_MPORT_27_mask = 1'h1;
-  assign mem_vldst_MPORT_27_en = ivalid & _GEN_1761;
+  assign mem_vldst_MPORT_27_en = ivalid & _GEN_1668;
   assign mem_suncd_mslice_io_in_bits_MPORT_en = mcount > 4'h0;
   assign mem_suncd_mslice_io_in_bits_MPORT_addr = outpos;
   `ifndef RANDOMIZE_GARBAGE_ASSIGN
   assign mem_suncd_mslice_io_in_bits_MPORT_data = mem_suncd[mem_suncd_mslice_io_in_bits_MPORT_addr]; // @[Fifo4.scala 59:16]
   `else
-  assign mem_suncd_mslice_io_in_bits_MPORT_data = mem_suncd_mslice_io_in_bits_MPORT_addr >= 3'h7 ? _RAND_29[0:0] :
+  assign mem_suncd_mslice_io_in_bits_MPORT_data = mem_suncd_mslice_io_in_bits_MPORT_addr >= 3'h7 ? _RAND_27[0:0] :
     mem_suncd[mem_suncd_mslice_io_in_bits_MPORT_addr]; // @[Fifo4.scala 59:16]
   `endif // RANDOMIZE_GARBAGE_ASSIGN
   assign mem_suncd_MPORT_data = io_in_bits_0_bits_suncd;
@@ -19148,15 +17667,15 @@
   assign mem_suncd_MPORT_1_data = io_in_bits_1_bits_suncd;
   assign mem_suncd_MPORT_1_addr = 3'h0;
   assign mem_suncd_MPORT_1_mask = 1'h1;
-  assign mem_suncd_MPORT_1_en = ivalid & _GEN_141;
+  assign mem_suncd_MPORT_1_en = ivalid & _GEN_134;
   assign mem_suncd_MPORT_2_data = io_in_bits_2_bits_suncd;
   assign mem_suncd_MPORT_2_addr = 3'h0;
   assign mem_suncd_MPORT_2_mask = 1'h1;
-  assign mem_suncd_MPORT_2_en = ivalid & _GEN_160;
+  assign mem_suncd_MPORT_2_en = ivalid & _GEN_152;
   assign mem_suncd_MPORT_3_data = io_in_bits_3_bits_suncd;
   assign mem_suncd_MPORT_3_addr = 3'h0;
   assign mem_suncd_MPORT_3_mask = 1'h1;
-  assign mem_suncd_MPORT_3_en = ivalid & _GEN_179;
+  assign mem_suncd_MPORT_3_en = ivalid & _GEN_170;
   assign mem_suncd_MPORT_4_data = io_in_bits_0_bits_suncd;
   assign mem_suncd_MPORT_4_addr = 3'h1;
   assign mem_suncd_MPORT_4_mask = 1'h1;
@@ -19164,15 +17683,15 @@
   assign mem_suncd_MPORT_5_data = io_in_bits_1_bits_suncd;
   assign mem_suncd_MPORT_5_addr = 3'h1;
   assign mem_suncd_MPORT_5_mask = 1'h1;
-  assign mem_suncd_MPORT_5_en = ivalid & _GEN_400;
+  assign mem_suncd_MPORT_5_en = ivalid & _GEN_379;
   assign mem_suncd_MPORT_6_data = io_in_bits_2_bits_suncd;
   assign mem_suncd_MPORT_6_addr = 3'h1;
   assign mem_suncd_MPORT_6_mask = 1'h1;
-  assign mem_suncd_MPORT_6_en = ivalid & _GEN_418;
+  assign mem_suncd_MPORT_6_en = ivalid & _GEN_396;
   assign mem_suncd_MPORT_7_data = io_in_bits_3_bits_suncd;
   assign mem_suncd_MPORT_7_addr = 3'h1;
   assign mem_suncd_MPORT_7_mask = 1'h1;
-  assign mem_suncd_MPORT_7_en = ivalid & _GEN_436;
+  assign mem_suncd_MPORT_7_en = ivalid & _GEN_413;
   assign mem_suncd_MPORT_8_data = io_in_bits_0_bits_suncd;
   assign mem_suncd_MPORT_8_addr = 3'h2;
   assign mem_suncd_MPORT_8_mask = 1'h1;
@@ -19180,15 +17699,15 @@
   assign mem_suncd_MPORT_9_data = io_in_bits_1_bits_suncd;
   assign mem_suncd_MPORT_9_addr = 3'h2;
   assign mem_suncd_MPORT_9_mask = 1'h1;
-  assign mem_suncd_MPORT_9_en = ivalid & _GEN_659;
+  assign mem_suncd_MPORT_9_en = ivalid & _GEN_624;
   assign mem_suncd_MPORT_10_data = io_in_bits_2_bits_suncd;
   assign mem_suncd_MPORT_10_addr = 3'h2;
   assign mem_suncd_MPORT_10_mask = 1'h1;
-  assign mem_suncd_MPORT_10_en = ivalid & _GEN_678;
+  assign mem_suncd_MPORT_10_en = ivalid & _GEN_642;
   assign mem_suncd_MPORT_11_data = io_in_bits_3_bits_suncd;
   assign mem_suncd_MPORT_11_addr = 3'h2;
   assign mem_suncd_MPORT_11_mask = 1'h1;
-  assign mem_suncd_MPORT_11_en = ivalid & _GEN_697;
+  assign mem_suncd_MPORT_11_en = ivalid & _GEN_660;
   assign mem_suncd_MPORT_12_data = io_in_bits_0_bits_suncd;
   assign mem_suncd_MPORT_12_addr = 3'h3;
   assign mem_suncd_MPORT_12_mask = 1'h1;
@@ -19196,15 +17715,15 @@
   assign mem_suncd_MPORT_13_data = io_in_bits_1_bits_suncd;
   assign mem_suncd_MPORT_13_addr = 3'h3;
   assign mem_suncd_MPORT_13_mask = 1'h1;
-  assign mem_suncd_MPORT_13_en = ivalid & _GEN_925;
+  assign mem_suncd_MPORT_13_en = ivalid & _GEN_876;
   assign mem_suncd_MPORT_14_data = io_in_bits_2_bits_suncd;
   assign mem_suncd_MPORT_14_addr = 3'h3;
   assign mem_suncd_MPORT_14_mask = 1'h1;
-  assign mem_suncd_MPORT_14_en = ivalid & _GEN_944;
+  assign mem_suncd_MPORT_14_en = ivalid & _GEN_894;
   assign mem_suncd_MPORT_15_data = io_in_bits_3_bits_suncd;
   assign mem_suncd_MPORT_15_addr = 3'h3;
   assign mem_suncd_MPORT_15_mask = 1'h1;
-  assign mem_suncd_MPORT_15_en = ivalid & _GEN_963;
+  assign mem_suncd_MPORT_15_en = ivalid & _GEN_912;
   assign mem_suncd_MPORT_16_data = io_in_bits_0_bits_suncd;
   assign mem_suncd_MPORT_16_addr = 3'h4;
   assign mem_suncd_MPORT_16_mask = 1'h1;
@@ -19212,15 +17731,15 @@
   assign mem_suncd_MPORT_17_data = io_in_bits_1_bits_suncd;
   assign mem_suncd_MPORT_17_addr = 3'h4;
   assign mem_suncd_MPORT_17_mask = 1'h1;
-  assign mem_suncd_MPORT_17_en = ivalid & _GEN_1191;
+  assign mem_suncd_MPORT_17_en = ivalid & _GEN_1128;
   assign mem_suncd_MPORT_18_data = io_in_bits_2_bits_suncd;
   assign mem_suncd_MPORT_18_addr = 3'h4;
   assign mem_suncd_MPORT_18_mask = 1'h1;
-  assign mem_suncd_MPORT_18_en = ivalid & _GEN_1210;
+  assign mem_suncd_MPORT_18_en = ivalid & _GEN_1146;
   assign mem_suncd_MPORT_19_data = io_in_bits_3_bits_suncd;
   assign mem_suncd_MPORT_19_addr = 3'h4;
   assign mem_suncd_MPORT_19_mask = 1'h1;
-  assign mem_suncd_MPORT_19_en = ivalid & _GEN_1229;
+  assign mem_suncd_MPORT_19_en = ivalid & _GEN_1164;
   assign mem_suncd_MPORT_20_data = io_in_bits_0_bits_suncd;
   assign mem_suncd_MPORT_20_addr = 3'h5;
   assign mem_suncd_MPORT_20_mask = 1'h1;
@@ -19228,15 +17747,15 @@
   assign mem_suncd_MPORT_21_data = io_in_bits_1_bits_suncd;
   assign mem_suncd_MPORT_21_addr = 3'h5;
   assign mem_suncd_MPORT_21_mask = 1'h1;
-  assign mem_suncd_MPORT_21_en = ivalid & _GEN_1457;
+  assign mem_suncd_MPORT_21_en = ivalid & _GEN_1380;
   assign mem_suncd_MPORT_22_data = io_in_bits_2_bits_suncd;
   assign mem_suncd_MPORT_22_addr = 3'h5;
   assign mem_suncd_MPORT_22_mask = 1'h1;
-  assign mem_suncd_MPORT_22_en = ivalid & _GEN_1476;
+  assign mem_suncd_MPORT_22_en = ivalid & _GEN_1398;
   assign mem_suncd_MPORT_23_data = io_in_bits_3_bits_suncd;
   assign mem_suncd_MPORT_23_addr = 3'h5;
   assign mem_suncd_MPORT_23_mask = 1'h1;
-  assign mem_suncd_MPORT_23_en = ivalid & _GEN_1495;
+  assign mem_suncd_MPORT_23_en = ivalid & _GEN_1416;
   assign mem_suncd_MPORT_24_data = io_in_bits_0_bits_suncd;
   assign mem_suncd_MPORT_24_addr = 3'h6;
   assign mem_suncd_MPORT_24_mask = 1'h1;
@@ -19244,16 +17763,16 @@
   assign mem_suncd_MPORT_25_data = io_in_bits_1_bits_suncd;
   assign mem_suncd_MPORT_25_addr = 3'h6;
   assign mem_suncd_MPORT_25_mask = 1'h1;
-  assign mem_suncd_MPORT_25_en = ivalid & _GEN_1723;
+  assign mem_suncd_MPORT_25_en = ivalid & _GEN_1632;
   assign mem_suncd_MPORT_26_data = io_in_bits_2_bits_suncd;
   assign mem_suncd_MPORT_26_addr = 3'h6;
   assign mem_suncd_MPORT_26_mask = 1'h1;
-  assign mem_suncd_MPORT_26_en = ivalid & _GEN_1742;
+  assign mem_suncd_MPORT_26_en = ivalid & _GEN_1650;
   assign mem_suncd_MPORT_27_data = io_in_bits_3_bits_suncd;
   assign mem_suncd_MPORT_27_addr = 3'h6;
   assign mem_suncd_MPORT_27_mask = 1'h1;
-  assign mem_suncd_MPORT_27_en = ivalid & _GEN_1761;
-  assign io_in_ready = mcount <= _GEN_1957; // @[Fifo4.scala 181:25]
+  assign mem_suncd_MPORT_27_en = ivalid & _GEN_1668;
+  assign io_in_ready = mcount <= _GEN_1853; // @[Fifo4.scala 181:25]
   assign io_out_valid = mslice_io_out_valid; // @[Fifo4.scala 182:10]
   assign io_out_bits_addr = mslice_io_out_bits_addr; // @[Fifo4.scala 182:10]
   assign io_out_bits_adrx = mslice_io_out_bits_adrx; // @[Fifo4.scala 182:10]
@@ -19262,7 +17781,6 @@
   assign io_out_bits_size = mslice_io_out_bits_size; // @[Fifo4.scala 182:10]
   assign io_out_bits_write = mslice_io_out_bits_write; // @[Fifo4.scala 182:10]
   assign io_out_bits_sext = mslice_io_out_bits_sext; // @[Fifo4.scala 182:10]
-  assign io_out_bits_fload = mslice_io_out_bits_fload; // @[Fifo4.scala 182:10]
   assign io_out_bits_iload = mslice_io_out_bits_iload; // @[Fifo4.scala 182:10]
   assign io_out_bits_fencei = mslice_io_out_bits_fencei; // @[Fifo4.scala 182:10]
   assign io_out_bits_flushat = mslice_io_out_bits_flushat; // @[Fifo4.scala 182:10]
@@ -19270,25 +17788,24 @@
   assign io_out_bits_sldst = mslice_io_out_bits_sldst; // @[Fifo4.scala 182:10]
   assign io_out_bits_vldst = mslice_io_out_bits_vldst; // @[Fifo4.scala 182:10]
   assign io_out_bits_suncd = mslice_io_out_bits_suncd; // @[Fifo4.scala 182:10]
-  assign io_count = mcount + _GEN_1950; // @[Fifo4.scala 69:22]
+  assign io_count = mcount + _GEN_1846; // @[Fifo4.scala 69:22]
   assign mslice_clock = clock;
   assign mslice_reset = reset;
   assign mslice_io_in_valid = mcount > 4'h0 ? io_out_ready : _T_31; // @[Fifo4.scala 142:23]
-  assign mslice_io_in_bits_addr = _T_29 ? mem_addr_mslice_io_in_bits_MPORT_data : _GEN_1931; // @[Fifo4.scala 152:23 153:23]
-  assign mslice_io_in_bits_adrx = _T_29 ? mem_adrx_mslice_io_in_bits_MPORT_data : _GEN_1930; // @[Fifo4.scala 152:23 153:23]
-  assign mslice_io_in_bits_data = _T_29 ? mem_data_mslice_io_in_bits_MPORT_data : _GEN_1929; // @[Fifo4.scala 152:23 153:23]
-  assign mslice_io_in_bits_index = _T_29 ? mem_index_mslice_io_in_bits_MPORT_data : _GEN_1928; // @[Fifo4.scala 152:23 153:23]
-  assign mslice_io_in_bits_size = _T_29 ? mem_size_mslice_io_in_bits_MPORT_data : _GEN_1927; // @[Fifo4.scala 152:23 153:23]
-  assign mslice_io_in_bits_write = _T_29 ? mem_write_mslice_io_in_bits_MPORT_data : _GEN_1926; // @[Fifo4.scala 152:23 153:23]
-  assign mslice_io_in_bits_sext = _T_29 ? mem_sext_mslice_io_in_bits_MPORT_data : _GEN_1925; // @[Fifo4.scala 152:23 153:23]
-  assign mslice_io_in_bits_fload = _T_29 ? mem_fload_mslice_io_in_bits_MPORT_data : _GEN_1924; // @[Fifo4.scala 152:23 153:23]
-  assign mslice_io_in_bits_iload = _T_29 ? mem_iload_mslice_io_in_bits_MPORT_data : _GEN_1923; // @[Fifo4.scala 152:23 153:23]
-  assign mslice_io_in_bits_fencei = _T_29 ? mem_fencei_mslice_io_in_bits_MPORT_data : _GEN_1922; // @[Fifo4.scala 152:23 153:23]
-  assign mslice_io_in_bits_flushat = _T_29 ? mem_flushat_mslice_io_in_bits_MPORT_data : _GEN_1921; // @[Fifo4.scala 152:23 153:23]
-  assign mslice_io_in_bits_flushall = _T_29 ? mem_flushall_mslice_io_in_bits_MPORT_data : _GEN_1920; // @[Fifo4.scala 152:23 153:23]
-  assign mslice_io_in_bits_sldst = _T_29 ? mem_sldst_mslice_io_in_bits_MPORT_data : _GEN_1919; // @[Fifo4.scala 152:23 153:23]
-  assign mslice_io_in_bits_vldst = _T_29 ? mem_vldst_mslice_io_in_bits_MPORT_data : _GEN_1918; // @[Fifo4.scala 152:23 153:23]
-  assign mslice_io_in_bits_suncd = _T_29 ? mem_suncd_mslice_io_in_bits_MPORT_data : _GEN_1917; // @[Fifo4.scala 152:23 153:23]
+  assign mslice_io_in_bits_addr = _T_29 ? mem_addr_mslice_io_in_bits_MPORT_data : _GEN_1828; // @[Fifo4.scala 152:23 153:23]
+  assign mslice_io_in_bits_adrx = _T_29 ? mem_adrx_mslice_io_in_bits_MPORT_data : _GEN_1827; // @[Fifo4.scala 152:23 153:23]
+  assign mslice_io_in_bits_data = _T_29 ? mem_data_mslice_io_in_bits_MPORT_data : _GEN_1826; // @[Fifo4.scala 152:23 153:23]
+  assign mslice_io_in_bits_index = _T_29 ? mem_index_mslice_io_in_bits_MPORT_data : _GEN_1825; // @[Fifo4.scala 152:23 153:23]
+  assign mslice_io_in_bits_size = _T_29 ? mem_size_mslice_io_in_bits_MPORT_data : _GEN_1824; // @[Fifo4.scala 152:23 153:23]
+  assign mslice_io_in_bits_write = _T_29 ? mem_write_mslice_io_in_bits_MPORT_data : _GEN_1823; // @[Fifo4.scala 152:23 153:23]
+  assign mslice_io_in_bits_sext = _T_29 ? mem_sext_mslice_io_in_bits_MPORT_data : _GEN_1822; // @[Fifo4.scala 152:23 153:23]
+  assign mslice_io_in_bits_iload = _T_29 ? mem_iload_mslice_io_in_bits_MPORT_data : _GEN_1821; // @[Fifo4.scala 152:23 153:23]
+  assign mslice_io_in_bits_fencei = _T_29 ? mem_fencei_mslice_io_in_bits_MPORT_data : _GEN_1820; // @[Fifo4.scala 152:23 153:23]
+  assign mslice_io_in_bits_flushat = _T_29 ? mem_flushat_mslice_io_in_bits_MPORT_data : _GEN_1819; // @[Fifo4.scala 152:23 153:23]
+  assign mslice_io_in_bits_flushall = _T_29 ? mem_flushall_mslice_io_in_bits_MPORT_data : _GEN_1818; // @[Fifo4.scala 152:23 153:23]
+  assign mslice_io_in_bits_sldst = _T_29 ? mem_sldst_mslice_io_in_bits_MPORT_data : _GEN_1817; // @[Fifo4.scala 152:23 153:23]
+  assign mslice_io_in_bits_vldst = _T_29 ? mem_vldst_mslice_io_in_bits_MPORT_data : _GEN_1816; // @[Fifo4.scala 152:23 153:23]
+  assign mslice_io_in_bits_suncd = _T_29 ? mem_suncd_mslice_io_in_bits_MPORT_data : _GEN_1815; // @[Fifo4.scala 152:23 153:23]
   assign mslice_io_out_ready = io_out_ready; // @[Fifo4.scala 182:10]
   always @(posedge clock) begin
     if (mem_addr_MPORT_en & mem_addr_MPORT_mask) begin
@@ -19879,90 +18396,6 @@
     if (mem_sext_MPORT_27_en & mem_sext_MPORT_27_mask) begin
       mem_sext[mem_sext_MPORT_27_addr] <= mem_sext_MPORT_27_data; // @[Fifo4.scala 59:16]
     end
-    if (mem_fload_MPORT_en & mem_fload_MPORT_mask) begin
-      mem_fload[mem_fload_MPORT_addr] <= mem_fload_MPORT_data; // @[Fifo4.scala 59:16]
-    end
-    if (mem_fload_MPORT_1_en & mem_fload_MPORT_1_mask) begin
-      mem_fload[mem_fload_MPORT_1_addr] <= mem_fload_MPORT_1_data; // @[Fifo4.scala 59:16]
-    end
-    if (mem_fload_MPORT_2_en & mem_fload_MPORT_2_mask) begin
-      mem_fload[mem_fload_MPORT_2_addr] <= mem_fload_MPORT_2_data; // @[Fifo4.scala 59:16]
-    end
-    if (mem_fload_MPORT_3_en & mem_fload_MPORT_3_mask) begin
-      mem_fload[mem_fload_MPORT_3_addr] <= mem_fload_MPORT_3_data; // @[Fifo4.scala 59:16]
-    end
-    if (mem_fload_MPORT_4_en & mem_fload_MPORT_4_mask) begin
-      mem_fload[mem_fload_MPORT_4_addr] <= mem_fload_MPORT_4_data; // @[Fifo4.scala 59:16]
-    end
-    if (mem_fload_MPORT_5_en & mem_fload_MPORT_5_mask) begin
-      mem_fload[mem_fload_MPORT_5_addr] <= mem_fload_MPORT_5_data; // @[Fifo4.scala 59:16]
-    end
-    if (mem_fload_MPORT_6_en & mem_fload_MPORT_6_mask) begin
-      mem_fload[mem_fload_MPORT_6_addr] <= mem_fload_MPORT_6_data; // @[Fifo4.scala 59:16]
-    end
-    if (mem_fload_MPORT_7_en & mem_fload_MPORT_7_mask) begin
-      mem_fload[mem_fload_MPORT_7_addr] <= mem_fload_MPORT_7_data; // @[Fifo4.scala 59:16]
-    end
-    if (mem_fload_MPORT_8_en & mem_fload_MPORT_8_mask) begin
-      mem_fload[mem_fload_MPORT_8_addr] <= mem_fload_MPORT_8_data; // @[Fifo4.scala 59:16]
-    end
-    if (mem_fload_MPORT_9_en & mem_fload_MPORT_9_mask) begin
-      mem_fload[mem_fload_MPORT_9_addr] <= mem_fload_MPORT_9_data; // @[Fifo4.scala 59:16]
-    end
-    if (mem_fload_MPORT_10_en & mem_fload_MPORT_10_mask) begin
-      mem_fload[mem_fload_MPORT_10_addr] <= mem_fload_MPORT_10_data; // @[Fifo4.scala 59:16]
-    end
-    if (mem_fload_MPORT_11_en & mem_fload_MPORT_11_mask) begin
-      mem_fload[mem_fload_MPORT_11_addr] <= mem_fload_MPORT_11_data; // @[Fifo4.scala 59:16]
-    end
-    if (mem_fload_MPORT_12_en & mem_fload_MPORT_12_mask) begin
-      mem_fload[mem_fload_MPORT_12_addr] <= mem_fload_MPORT_12_data; // @[Fifo4.scala 59:16]
-    end
-    if (mem_fload_MPORT_13_en & mem_fload_MPORT_13_mask) begin
-      mem_fload[mem_fload_MPORT_13_addr] <= mem_fload_MPORT_13_data; // @[Fifo4.scala 59:16]
-    end
-    if (mem_fload_MPORT_14_en & mem_fload_MPORT_14_mask) begin
-      mem_fload[mem_fload_MPORT_14_addr] <= mem_fload_MPORT_14_data; // @[Fifo4.scala 59:16]
-    end
-    if (mem_fload_MPORT_15_en & mem_fload_MPORT_15_mask) begin
-      mem_fload[mem_fload_MPORT_15_addr] <= mem_fload_MPORT_15_data; // @[Fifo4.scala 59:16]
-    end
-    if (mem_fload_MPORT_16_en & mem_fload_MPORT_16_mask) begin
-      mem_fload[mem_fload_MPORT_16_addr] <= mem_fload_MPORT_16_data; // @[Fifo4.scala 59:16]
-    end
-    if (mem_fload_MPORT_17_en & mem_fload_MPORT_17_mask) begin
-      mem_fload[mem_fload_MPORT_17_addr] <= mem_fload_MPORT_17_data; // @[Fifo4.scala 59:16]
-    end
-    if (mem_fload_MPORT_18_en & mem_fload_MPORT_18_mask) begin
-      mem_fload[mem_fload_MPORT_18_addr] <= mem_fload_MPORT_18_data; // @[Fifo4.scala 59:16]
-    end
-    if (mem_fload_MPORT_19_en & mem_fload_MPORT_19_mask) begin
-      mem_fload[mem_fload_MPORT_19_addr] <= mem_fload_MPORT_19_data; // @[Fifo4.scala 59:16]
-    end
-    if (mem_fload_MPORT_20_en & mem_fload_MPORT_20_mask) begin
-      mem_fload[mem_fload_MPORT_20_addr] <= mem_fload_MPORT_20_data; // @[Fifo4.scala 59:16]
-    end
-    if (mem_fload_MPORT_21_en & mem_fload_MPORT_21_mask) begin
-      mem_fload[mem_fload_MPORT_21_addr] <= mem_fload_MPORT_21_data; // @[Fifo4.scala 59:16]
-    end
-    if (mem_fload_MPORT_22_en & mem_fload_MPORT_22_mask) begin
-      mem_fload[mem_fload_MPORT_22_addr] <= mem_fload_MPORT_22_data; // @[Fifo4.scala 59:16]
-    end
-    if (mem_fload_MPORT_23_en & mem_fload_MPORT_23_mask) begin
-      mem_fload[mem_fload_MPORT_23_addr] <= mem_fload_MPORT_23_data; // @[Fifo4.scala 59:16]
-    end
-    if (mem_fload_MPORT_24_en & mem_fload_MPORT_24_mask) begin
-      mem_fload[mem_fload_MPORT_24_addr] <= mem_fload_MPORT_24_data; // @[Fifo4.scala 59:16]
-    end
-    if (mem_fload_MPORT_25_en & mem_fload_MPORT_25_mask) begin
-      mem_fload[mem_fload_MPORT_25_addr] <= mem_fload_MPORT_25_data; // @[Fifo4.scala 59:16]
-    end
-    if (mem_fload_MPORT_26_en & mem_fload_MPORT_26_mask) begin
-      mem_fload[mem_fload_MPORT_26_addr] <= mem_fload_MPORT_26_data; // @[Fifo4.scala 59:16]
-    end
-    if (mem_fload_MPORT_27_en & mem_fload_MPORT_27_mask) begin
-      mem_fload[mem_fload_MPORT_27_addr] <= mem_fload_MPORT_27_data; // @[Fifo4.scala 59:16]
-    end
     if (mem_iload_MPORT_en & mem_iload_MPORT_mask) begin
       mem_iload[mem_iload_MPORT_addr] <= mem_iload_MPORT_data; // @[Fifo4.scala 59:16]
     end
@@ -20666,7 +19099,6 @@
   _RAND_23 = {1{`RANDOM}};
   _RAND_25 = {1{`RANDOM}};
   _RAND_27 = {1{`RANDOM}};
-  _RAND_29 = {1{`RANDOM}};
 `endif // RANDOMIZE_GARBAGE_ASSIGN
 `ifdef RANDOMIZE_MEM_INIT
   _RAND_0 = {1{`RANDOM}};
@@ -20692,42 +19124,39 @@
     mem_sext[initvar] = _RAND_12[0:0];
   _RAND_14 = {1{`RANDOM}};
   for (initvar = 0; initvar < 7; initvar = initvar+1)
-    mem_fload[initvar] = _RAND_14[0:0];
+    mem_iload[initvar] = _RAND_14[0:0];
   _RAND_16 = {1{`RANDOM}};
   for (initvar = 0; initvar < 7; initvar = initvar+1)
-    mem_iload[initvar] = _RAND_16[0:0];
+    mem_fencei[initvar] = _RAND_16[0:0];
   _RAND_18 = {1{`RANDOM}};
   for (initvar = 0; initvar < 7; initvar = initvar+1)
-    mem_fencei[initvar] = _RAND_18[0:0];
+    mem_flushat[initvar] = _RAND_18[0:0];
   _RAND_20 = {1{`RANDOM}};
   for (initvar = 0; initvar < 7; initvar = initvar+1)
-    mem_flushat[initvar] = _RAND_20[0:0];
+    mem_flushall[initvar] = _RAND_20[0:0];
   _RAND_22 = {1{`RANDOM}};
   for (initvar = 0; initvar < 7; initvar = initvar+1)
-    mem_flushall[initvar] = _RAND_22[0:0];
+    mem_sldst[initvar] = _RAND_22[0:0];
   _RAND_24 = {1{`RANDOM}};
   for (initvar = 0; initvar < 7; initvar = initvar+1)
-    mem_sldst[initvar] = _RAND_24[0:0];
+    mem_vldst[initvar] = _RAND_24[0:0];
   _RAND_26 = {1{`RANDOM}};
   for (initvar = 0; initvar < 7; initvar = initvar+1)
-    mem_vldst[initvar] = _RAND_26[0:0];
-  _RAND_28 = {1{`RANDOM}};
-  for (initvar = 0; initvar < 7; initvar = initvar+1)
-    mem_suncd[initvar] = _RAND_28[0:0];
+    mem_suncd[initvar] = _RAND_26[0:0];
 `endif // RANDOMIZE_MEM_INIT
 `ifdef RANDOMIZE_REG_INIT
+  _RAND_28 = {1{`RANDOM}};
+  in0pos = _RAND_28[2:0];
+  _RAND_29 = {1{`RANDOM}};
+  in1pos = _RAND_29[2:0];
   _RAND_30 = {1{`RANDOM}};
-  in0pos = _RAND_30[2:0];
+  in2pos = _RAND_30[2:0];
   _RAND_31 = {1{`RANDOM}};
-  in1pos = _RAND_31[2:0];
+  in3pos = _RAND_31[2:0];
   _RAND_32 = {1{`RANDOM}};
-  in2pos = _RAND_32[2:0];
+  outpos = _RAND_32[2:0];
   _RAND_33 = {1{`RANDOM}};
-  in3pos = _RAND_33[2:0];
-  _RAND_34 = {1{`RANDOM}};
-  outpos = _RAND_34[2:0];
-  _RAND_35 = {1{`RANDOM}};
-  mcount = _RAND_35[3:0];
+  mcount = _RAND_33[3:0];
 `endif // RANDOMIZE_REG_INIT
   if (reset) begin
     in0pos = 3'h0;
@@ -20763,7 +19192,6 @@
   input  [4:0]  io_in_bits_index,
   input  [5:0]  io_in_bits_size,
   input         io_in_bits_sext,
-  input         io_in_bits_fload,
   input         io_in_bits_iload,
   input         io_in_bits_sldst,
   input         io_in_bits_suncd,
@@ -20772,7 +19200,6 @@
   output [4:0]  io_out_bits_index,
   output [5:0]  io_out_bits_size,
   output        io_out_bits_sext,
-  output        io_out_bits_fload,
   output        io_out_bits_iload,
   output        io_out_bits_sldst,
   output        io_out_bits_suncd
@@ -20794,8 +19221,6 @@
   reg [31:0] _RAND_13;
   reg [31:0] _RAND_14;
   reg [31:0] _RAND_15;
-  reg [31:0] _RAND_16;
-  reg [31:0] _RAND_17;
 `endif // RANDOMIZE_REG_INIT
   reg [1:0] ipos; // @[Slice.scala 24:21]
   reg [1:0] opos; // @[Slice.scala 25:21]
@@ -20803,7 +19228,6 @@
   reg [4:0] mem_0_index; // @[Slice.scala 27:16]
   reg [5:0] mem_0_size; // @[Slice.scala 27:16]
   reg  mem_0_sext; // @[Slice.scala 27:16]
-  reg  mem_0_fload; // @[Slice.scala 27:16]
   reg  mem_0_iload; // @[Slice.scala 27:16]
   reg  mem_0_sldst; // @[Slice.scala 27:16]
   reg  mem_0_suncd; // @[Slice.scala 27:16]
@@ -20811,7 +19235,6 @@
   reg [4:0] mem_1_index; // @[Slice.scala 27:16]
   reg [5:0] mem_1_size; // @[Slice.scala 27:16]
   reg  mem_1_sext; // @[Slice.scala 27:16]
-  reg  mem_1_fload; // @[Slice.scala 27:16]
   reg  mem_1_iload; // @[Slice.scala 27:16]
   reg  mem_1_sldst; // @[Slice.scala 27:16]
   reg  mem_1_suncd; // @[Slice.scala 27:16]
@@ -20833,7 +19256,6 @@
   assign io_out_bits_index = mem_0_index; // @[Slice.scala 89:18]
   assign io_out_bits_size = mem_0_size; // @[Slice.scala 89:18]
   assign io_out_bits_sext = mem_0_sext; // @[Slice.scala 89:18]
-  assign io_out_bits_fload = mem_0_fload; // @[Slice.scala 89:18]
   assign io_out_bits_iload = mem_0_iload; // @[Slice.scala 89:18]
   assign io_out_bits_sldst = mem_0_sldst; // @[Slice.scala 89:18]
   assign io_out_bits_suncd = mem_0_suncd; // @[Slice.scala 89:18]
@@ -20859,11 +19281,6 @@
       mem_0_sext <= mem_1_sext; // @[Slice.scala 55:14]
     end
     if (_T_8) begin // @[Slice.scala 59:38]
-      mem_0_fload <= io_in_bits_fload; // @[Slice.scala 60:14]
-    end else if (io_out_valid & full) begin // @[Slice.scala 54:27]
-      mem_0_fload <= mem_1_fload; // @[Slice.scala 55:14]
-    end
-    if (_T_8) begin // @[Slice.scala 59:38]
       mem_0_iload <= io_in_bits_iload; // @[Slice.scala 60:14]
     end else if (io_out_valid & full) begin // @[Slice.scala 54:27]
       mem_0_iload <= mem_1_iload; // @[Slice.scala 55:14]
@@ -20891,9 +19308,6 @@
       mem_1_sext <= io_in_bits_sext; // @[Slice.scala 65:14]
     end
     if (_T_15) begin // @[Slice.scala 64:37]
-      mem_1_fload <= io_in_bits_fload; // @[Slice.scala 65:14]
-    end
-    if (_T_15) begin // @[Slice.scala 64:37]
       mem_1_iload <= io_in_bits_iload; // @[Slice.scala 65:14]
     end
     if (_T_15) begin // @[Slice.scala 64:37]
@@ -20966,29 +19380,25 @@
   _RAND_5 = {1{`RANDOM}};
   mem_0_sext = _RAND_5[0:0];
   _RAND_6 = {1{`RANDOM}};
-  mem_0_fload = _RAND_6[0:0];
+  mem_0_iload = _RAND_6[0:0];
   _RAND_7 = {1{`RANDOM}};
-  mem_0_iload = _RAND_7[0:0];
+  mem_0_sldst = _RAND_7[0:0];
   _RAND_8 = {1{`RANDOM}};
-  mem_0_sldst = _RAND_8[0:0];
+  mem_0_suncd = _RAND_8[0:0];
   _RAND_9 = {1{`RANDOM}};
-  mem_0_suncd = _RAND_9[0:0];
+  mem_1_addr = _RAND_9[31:0];
   _RAND_10 = {1{`RANDOM}};
-  mem_1_addr = _RAND_10[31:0];
+  mem_1_index = _RAND_10[4:0];
   _RAND_11 = {1{`RANDOM}};
-  mem_1_index = _RAND_11[4:0];
+  mem_1_size = _RAND_11[5:0];
   _RAND_12 = {1{`RANDOM}};
-  mem_1_size = _RAND_12[5:0];
+  mem_1_sext = _RAND_12[0:0];
   _RAND_13 = {1{`RANDOM}};
-  mem_1_sext = _RAND_13[0:0];
+  mem_1_iload = _RAND_13[0:0];
   _RAND_14 = {1{`RANDOM}};
-  mem_1_fload = _RAND_14[0:0];
+  mem_1_sldst = _RAND_14[0:0];
   _RAND_15 = {1{`RANDOM}};
-  mem_1_iload = _RAND_15[0:0];
-  _RAND_16 = {1{`RANDOM}};
-  mem_1_sldst = _RAND_16[0:0];
-  _RAND_17 = {1{`RANDOM}};
-  mem_1_suncd = _RAND_17[0:0];
+  mem_1_suncd = _RAND_15[0:0];
 `endif // RANDOMIZE_REG_INIT
   if (reset) begin
     ipos = 2'h0;
@@ -21009,19 +19419,19 @@
   input          io_req_0_valid,
   output         io_req_0_ready,
   input  [4:0]   io_req_0_addr,
-  input  [13:0]  io_req_0_op,
+  input  [11:0]  io_req_0_op,
   input          io_req_1_valid,
   output         io_req_1_ready,
   input  [4:0]   io_req_1_addr,
-  input  [13:0]  io_req_1_op,
+  input  [11:0]  io_req_1_op,
   input          io_req_2_valid,
   output         io_req_2_ready,
   input  [4:0]   io_req_2_addr,
-  input  [13:0]  io_req_2_op,
+  input  [11:0]  io_req_2_op,
   input          io_req_3_valid,
   output         io_req_3_ready,
   input  [4:0]   io_req_3_addr,
-  input  [13:0]  io_req_3_op,
+  input  [11:0]  io_req_3_op,
   input  [31:0]  io_busPort_addr_0,
   input  [31:0]  io_busPort_addr_1,
   input  [31:0]  io_busPort_addr_2,
@@ -21030,13 +19440,9 @@
   input  [31:0]  io_busPort_data_1,
   input  [31:0]  io_busPort_data_2,
   input  [31:0]  io_busPort_data_3,
-  input  [31:0]  io_fbusPort_data,
   output         io_rd_valid,
   output [4:0]   io_rd_addr,
   output [31:0]  io_rd_data,
-  output         io_fd_valid,
-  output [4:0]   io_fd_addr,
-  output [31:0]  io_fd_data,
   output         io_dbus_valid,
   input          io_dbus_ready,
   output         io_dbus_write,
@@ -21071,7 +19477,6 @@
   wire [5:0] ctrl_io_in_bits_0_bits_size; // @[Fifo4.scala 8:11]
   wire  ctrl_io_in_bits_0_bits_write; // @[Fifo4.scala 8:11]
   wire  ctrl_io_in_bits_0_bits_sext; // @[Fifo4.scala 8:11]
-  wire  ctrl_io_in_bits_0_bits_fload; // @[Fifo4.scala 8:11]
   wire  ctrl_io_in_bits_0_bits_iload; // @[Fifo4.scala 8:11]
   wire  ctrl_io_in_bits_0_bits_fencei; // @[Fifo4.scala 8:11]
   wire  ctrl_io_in_bits_0_bits_flushat; // @[Fifo4.scala 8:11]
@@ -21087,7 +19492,6 @@
   wire [5:0] ctrl_io_in_bits_1_bits_size; // @[Fifo4.scala 8:11]
   wire  ctrl_io_in_bits_1_bits_write; // @[Fifo4.scala 8:11]
   wire  ctrl_io_in_bits_1_bits_sext; // @[Fifo4.scala 8:11]
-  wire  ctrl_io_in_bits_1_bits_fload; // @[Fifo4.scala 8:11]
   wire  ctrl_io_in_bits_1_bits_iload; // @[Fifo4.scala 8:11]
   wire  ctrl_io_in_bits_1_bits_fencei; // @[Fifo4.scala 8:11]
   wire  ctrl_io_in_bits_1_bits_flushat; // @[Fifo4.scala 8:11]
@@ -21103,7 +19507,6 @@
   wire [5:0] ctrl_io_in_bits_2_bits_size; // @[Fifo4.scala 8:11]
   wire  ctrl_io_in_bits_2_bits_write; // @[Fifo4.scala 8:11]
   wire  ctrl_io_in_bits_2_bits_sext; // @[Fifo4.scala 8:11]
-  wire  ctrl_io_in_bits_2_bits_fload; // @[Fifo4.scala 8:11]
   wire  ctrl_io_in_bits_2_bits_iload; // @[Fifo4.scala 8:11]
   wire  ctrl_io_in_bits_2_bits_fencei; // @[Fifo4.scala 8:11]
   wire  ctrl_io_in_bits_2_bits_flushat; // @[Fifo4.scala 8:11]
@@ -21119,7 +19522,6 @@
   wire [5:0] ctrl_io_in_bits_3_bits_size; // @[Fifo4.scala 8:11]
   wire  ctrl_io_in_bits_3_bits_write; // @[Fifo4.scala 8:11]
   wire  ctrl_io_in_bits_3_bits_sext; // @[Fifo4.scala 8:11]
-  wire  ctrl_io_in_bits_3_bits_fload; // @[Fifo4.scala 8:11]
   wire  ctrl_io_in_bits_3_bits_iload; // @[Fifo4.scala 8:11]
   wire  ctrl_io_in_bits_3_bits_fencei; // @[Fifo4.scala 8:11]
   wire  ctrl_io_in_bits_3_bits_flushat; // @[Fifo4.scala 8:11]
@@ -21136,7 +19538,6 @@
   wire [5:0] ctrl_io_out_bits_size; // @[Fifo4.scala 8:11]
   wire  ctrl_io_out_bits_write; // @[Fifo4.scala 8:11]
   wire  ctrl_io_out_bits_sext; // @[Fifo4.scala 8:11]
-  wire  ctrl_io_out_bits_fload; // @[Fifo4.scala 8:11]
   wire  ctrl_io_out_bits_iload; // @[Fifo4.scala 8:11]
   wire  ctrl_io_out_bits_fencei; // @[Fifo4.scala 8:11]
   wire  ctrl_io_out_bits_flushat; // @[Fifo4.scala 8:11]
@@ -21153,7 +19554,6 @@
   wire [4:0] data_io_in_bits_index; // @[Slice.scala 9:11]
   wire [5:0] data_io_in_bits_size; // @[Slice.scala 9:11]
   wire  data_io_in_bits_sext; // @[Slice.scala 9:11]
-  wire  data_io_in_bits_fload; // @[Slice.scala 9:11]
   wire  data_io_in_bits_iload; // @[Slice.scala 9:11]
   wire  data_io_in_bits_sldst; // @[Slice.scala 9:11]
   wire  data_io_in_bits_suncd; // @[Slice.scala 9:11]
@@ -21162,454 +19562,445 @@
   wire [4:0] data_io_out_bits_index; // @[Slice.scala 9:11]
   wire [5:0] data_io_out_bits_size; // @[Slice.scala 9:11]
   wire  data_io_out_bits_sext; // @[Slice.scala 9:11]
-  wire  data_io_out_bits_fload; // @[Slice.scala 9:11]
   wire  data_io_out_bits_iload; // @[Slice.scala 9:11]
   wire  data_io_out_bits_sldst; // @[Slice.scala 9:11]
   wire  data_io_out_bits_suncd; // @[Slice.scala 9:11]
-  wire  _ctrlready_T = ctrl_io_count <= 4'h4; // @[Lsu.scala 112:37]
-  wire  _ctrlready_T_1 = ctrl_io_count <= 4'h5; // @[Lsu.scala 113:37]
-  wire  _ctrlready_T_2 = ctrl_io_count <= 4'h6; // @[Lsu.scala 114:37]
-  wire  _ctrlready_T_3 = ctrl_io_count <= 4'h7; // @[Lsu.scala 115:37]
+  wire  _ctrlready_T = ctrl_io_count <= 4'h4; // @[Lsu.scala 106:37]
+  wire  _ctrlready_T_1 = ctrl_io_count <= 4'h5; // @[Lsu.scala 107:37]
+  wire  _ctrlready_T_2 = ctrl_io_count <= 4'h6; // @[Lsu.scala 108:37]
+  wire  _ctrlready_T_3 = ctrl_io_count <= 4'h7; // @[Lsu.scala 109:37]
   wire [3:0] ctrlready = {_ctrlready_T,_ctrlready_T_1,_ctrlready_T_2,_ctrlready_T_3}; // @[Cat.scala 31:58]
-  wire  _ctrl_io_in_valid_T_1 = io_req_0_valid | io_req_1_valid | io_req_2_valid; // @[Lsu.scala 128:58]
-  wire  uncached = io_busPort_addr_0[31]; // @[Lsu.scala 132:38]
-  wire  opstore = io_req_0_op[7] | io_req_0_op[6] | io_req_0_op[5] | io_req_0_op[9]; // @[Lsu.scala 134:88]
-  wire  opiload = io_req_0_op[2] | io_req_0_op[1] | io_req_0_op[0] | io_req_0_op[4] | io_req_0_op[3]; // @[Lsu.scala 135:113]
-  wire  opfload = io_req_0_op[8]; // @[Lsu.scala 136:31]
-  wire  opload = opiload | opfload; // @[Lsu.scala 137:27]
-  wire  opsldst = opstore | opload; // @[Lsu.scala 141:27]
-  wire  opvldst = io_req_0_op[13]; // @[Lsu.scala 142:31]
-  wire  _opsize_T_6 = io_req_0_op[2] | io_req_0_op[7] | opfload | io_req_0_op[9]; // @[Lsu.scala 144:92]
-  wire  _opsize_T_11 = io_req_0_op[1] | io_req_0_op[4] | io_req_0_op[6]; // @[Lsu.scala 145:68]
-  wire  _opsize_T_16 = io_req_0_op[0] | io_req_0_op[3] | io_req_0_op[5]; // @[Lsu.scala 146:68]
-  wire [2:0] opsize = {_opsize_T_6,_opsize_T_11,_opsize_T_16}; // @[Cat.scala 31:58]
-  wire  uncached_1 = io_busPort_addr_1[31]; // @[Lsu.scala 132:38]
-  wire  opstore_1 = io_req_1_op[7] | io_req_1_op[6] | io_req_1_op[5] | io_req_1_op[9]; // @[Lsu.scala 134:88]
-  wire  opiload_1 = io_req_1_op[2] | io_req_1_op[1] | io_req_1_op[0] | io_req_1_op[4] | io_req_1_op[3]; // @[Lsu.scala 135:113]
-  wire  opfload_1 = io_req_1_op[8]; // @[Lsu.scala 136:31]
-  wire  opload_1 = opiload_1 | opfload_1; // @[Lsu.scala 137:27]
-  wire  opsldst_1 = opstore_1 | opload_1; // @[Lsu.scala 141:27]
-  wire  opvldst_1 = io_req_1_op[13]; // @[Lsu.scala 142:31]
-  wire  _opsize_T_23 = io_req_1_op[2] | io_req_1_op[7] | opfload_1 | io_req_1_op[9]; // @[Lsu.scala 144:92]
-  wire  _opsize_T_28 = io_req_1_op[1] | io_req_1_op[4] | io_req_1_op[6]; // @[Lsu.scala 145:68]
-  wire  _opsize_T_33 = io_req_1_op[0] | io_req_1_op[3] | io_req_1_op[5]; // @[Lsu.scala 146:68]
-  wire [2:0] opsize_1 = {_opsize_T_23,_opsize_T_28,_opsize_T_33}; // @[Cat.scala 31:58]
-  wire  uncached_2 = io_busPort_addr_2[31]; // @[Lsu.scala 132:38]
-  wire  opstore_2 = io_req_2_op[7] | io_req_2_op[6] | io_req_2_op[5] | io_req_2_op[9]; // @[Lsu.scala 134:88]
-  wire  opiload_2 = io_req_2_op[2] | io_req_2_op[1] | io_req_2_op[0] | io_req_2_op[4] | io_req_2_op[3]; // @[Lsu.scala 135:113]
-  wire  opfload_2 = io_req_2_op[8]; // @[Lsu.scala 136:31]
-  wire  opload_2 = opiload_2 | opfload_2; // @[Lsu.scala 137:27]
-  wire  opsldst_2 = opstore_2 | opload_2; // @[Lsu.scala 141:27]
-  wire  opvldst_2 = io_req_2_op[13]; // @[Lsu.scala 142:31]
-  wire  _opsize_T_40 = io_req_2_op[2] | io_req_2_op[7] | opfload_2 | io_req_2_op[9]; // @[Lsu.scala 144:92]
-  wire  _opsize_T_45 = io_req_2_op[1] | io_req_2_op[4] | io_req_2_op[6]; // @[Lsu.scala 145:68]
-  wire  _opsize_T_50 = io_req_2_op[0] | io_req_2_op[3] | io_req_2_op[5]; // @[Lsu.scala 146:68]
-  wire [2:0] opsize_2 = {_opsize_T_40,_opsize_T_45,_opsize_T_50}; // @[Cat.scala 31:58]
-  wire  uncached_3 = io_busPort_addr_3[31]; // @[Lsu.scala 132:38]
-  wire  opstore_3 = io_req_3_op[7] | io_req_3_op[6] | io_req_3_op[5] | io_req_3_op[9]; // @[Lsu.scala 134:88]
-  wire  opiload_3 = io_req_3_op[2] | io_req_3_op[1] | io_req_3_op[0] | io_req_3_op[4] | io_req_3_op[3]; // @[Lsu.scala 135:113]
-  wire  opfload_3 = io_req_3_op[8]; // @[Lsu.scala 136:31]
-  wire  opload_3 = opiload_3 | opfload_3; // @[Lsu.scala 137:27]
-  wire  opsldst_3 = opstore_3 | opload_3; // @[Lsu.scala 141:27]
-  wire  opvldst_3 = io_req_3_op[13]; // @[Lsu.scala 142:31]
-  wire  _opsize_T_57 = io_req_3_op[2] | io_req_3_op[7] | opfload_3 | io_req_3_op[9]; // @[Lsu.scala 144:92]
-  wire  _opsize_T_62 = io_req_3_op[1] | io_req_3_op[4] | io_req_3_op[6]; // @[Lsu.scala 145:68]
-  wire  _opsize_T_67 = io_req_3_op[0] | io_req_3_op[3] | io_req_3_op[5]; // @[Lsu.scala 146:68]
-  wire [2:0] opsize_3 = {_opsize_T_57,_opsize_T_62,_opsize_T_67}; // @[Cat.scala 31:58]
-  wire [1:0] wsel = ctrl_io_out_bits_addr[1:0]; // @[Lsu.scala 169:35]
-  wire  _wdataS_T = wsel == 2'h0; // @[Lsu.scala 172:16]
-  wire [31:0] _wdataS_T_1 = ctrl_io_out_bits_data; // @[Lsu.scala 172:28]
+  wire  _ctrl_io_in_valid_T_1 = io_req_0_valid | io_req_1_valid | io_req_2_valid; // @[Lsu.scala 122:58]
+  wire  uncached = io_busPort_addr_0[31]; // @[Lsu.scala 126:38]
+  wire  opstore = io_req_0_op[7] | io_req_0_op[6] | io_req_0_op[5]; // @[Lsu.scala 128:64]
+  wire  opiload = io_req_0_op[2] | io_req_0_op[1] | io_req_0_op[0] | io_req_0_op[4] | io_req_0_op[3]; // @[Lsu.scala 129:113]
+  wire  opsldst = opstore | opiload; // @[Lsu.scala 134:27]
+  wire  opvldst = io_req_0_op[11]; // @[Lsu.scala 135:31]
+  wire  _opsize_T_2 = io_req_0_op[2] | io_req_0_op[7]; // @[Lsu.scala 137:43]
+  wire  _opsize_T_7 = io_req_0_op[1] | io_req_0_op[4] | io_req_0_op[6]; // @[Lsu.scala 138:68]
+  wire  _opsize_T_12 = io_req_0_op[0] | io_req_0_op[3] | io_req_0_op[5]; // @[Lsu.scala 139:68]
+  wire [2:0] opsize = {_opsize_T_2,_opsize_T_7,_opsize_T_12}; // @[Cat.scala 31:58]
+  wire  uncached_1 = io_busPort_addr_1[31]; // @[Lsu.scala 126:38]
+  wire  opstore_1 = io_req_1_op[7] | io_req_1_op[6] | io_req_1_op[5]; // @[Lsu.scala 128:64]
+  wire  opiload_1 = io_req_1_op[2] | io_req_1_op[1] | io_req_1_op[0] | io_req_1_op[4] | io_req_1_op[3]; // @[Lsu.scala 129:113]
+  wire  opsldst_1 = opstore_1 | opiload_1; // @[Lsu.scala 134:27]
+  wire  opvldst_1 = io_req_1_op[11]; // @[Lsu.scala 135:31]
+  wire  _opsize_T_15 = io_req_1_op[2] | io_req_1_op[7]; // @[Lsu.scala 137:43]
+  wire  _opsize_T_20 = io_req_1_op[1] | io_req_1_op[4] | io_req_1_op[6]; // @[Lsu.scala 138:68]
+  wire  _opsize_T_25 = io_req_1_op[0] | io_req_1_op[3] | io_req_1_op[5]; // @[Lsu.scala 139:68]
+  wire [2:0] opsize_1 = {_opsize_T_15,_opsize_T_20,_opsize_T_25}; // @[Cat.scala 31:58]
+  wire  uncached_2 = io_busPort_addr_2[31]; // @[Lsu.scala 126:38]
+  wire  opstore_2 = io_req_2_op[7] | io_req_2_op[6] | io_req_2_op[5]; // @[Lsu.scala 128:64]
+  wire  opiload_2 = io_req_2_op[2] | io_req_2_op[1] | io_req_2_op[0] | io_req_2_op[4] | io_req_2_op[3]; // @[Lsu.scala 129:113]
+  wire  opsldst_2 = opstore_2 | opiload_2; // @[Lsu.scala 134:27]
+  wire  opvldst_2 = io_req_2_op[11]; // @[Lsu.scala 135:31]
+  wire  _opsize_T_28 = io_req_2_op[2] | io_req_2_op[7]; // @[Lsu.scala 137:43]
+  wire  _opsize_T_33 = io_req_2_op[1] | io_req_2_op[4] | io_req_2_op[6]; // @[Lsu.scala 138:68]
+  wire  _opsize_T_38 = io_req_2_op[0] | io_req_2_op[3] | io_req_2_op[5]; // @[Lsu.scala 139:68]
+  wire [2:0] opsize_2 = {_opsize_T_28,_opsize_T_33,_opsize_T_38}; // @[Cat.scala 31:58]
+  wire  uncached_3 = io_busPort_addr_3[31]; // @[Lsu.scala 126:38]
+  wire  opstore_3 = io_req_3_op[7] | io_req_3_op[6] | io_req_3_op[5]; // @[Lsu.scala 128:64]
+  wire  opiload_3 = io_req_3_op[2] | io_req_3_op[1] | io_req_3_op[0] | io_req_3_op[4] | io_req_3_op[3]; // @[Lsu.scala 129:113]
+  wire  opsldst_3 = opstore_3 | opiload_3; // @[Lsu.scala 134:27]
+  wire  opvldst_3 = io_req_3_op[11]; // @[Lsu.scala 135:31]
+  wire  _opsize_T_41 = io_req_3_op[2] | io_req_3_op[7]; // @[Lsu.scala 137:43]
+  wire  _opsize_T_46 = io_req_3_op[1] | io_req_3_op[4] | io_req_3_op[6]; // @[Lsu.scala 138:68]
+  wire  _opsize_T_51 = io_req_3_op[0] | io_req_3_op[3] | io_req_3_op[5]; // @[Lsu.scala 139:68]
+  wire [2:0] opsize_3 = {_opsize_T_41,_opsize_T_46,_opsize_T_51}; // @[Cat.scala 31:58]
+  wire [1:0] wsel = ctrl_io_out_bits_addr[1:0]; // @[Lsu.scala 161:35]
+  wire  _wdataS_T = wsel == 2'h0; // @[Lsu.scala 164:16]
+  wire [31:0] _wdataS_T_1 = ctrl_io_out_bits_data; // @[Lsu.scala 164:28]
   wire [31:0] _wdataS_T_2 = _wdataS_T ? _wdataS_T_1 : 32'h0; // @[Library.scala 8:8]
-  wire  _wdataS_T_3 = wsel == 2'h1; // @[Lsu.scala 173:16]
+  wire  _wdataS_T_3 = wsel == 2'h1; // @[Lsu.scala 165:16]
   wire [31:0] _wdataS_T_8 = {ctrl_io_out_bits_data[23:16],ctrl_io_out_bits_data[15:8],ctrl_io_out_bits_data[7:0],
     ctrl_io_out_bits_data[31:24]}; // @[Cat.scala 31:58]
   wire [31:0] _wdataS_T_9 = _wdataS_T_3 ? _wdataS_T_8 : 32'h0; // @[Library.scala 8:8]
-  wire [31:0] _wdataS_T_10 = _wdataS_T_2 | _wdataS_T_9; // @[Lsu.scala 172:36]
-  wire  _wdataS_T_11 = wsel == 2'h2; // @[Lsu.scala 174:16]
+  wire [31:0] _wdataS_T_10 = _wdataS_T_2 | _wdataS_T_9; // @[Lsu.scala 164:36]
+  wire  _wdataS_T_11 = wsel == 2'h2; // @[Lsu.scala 166:16]
   wire [31:0] _wdataS_T_16 = {ctrl_io_out_bits_data[15:8],ctrl_io_out_bits_data[7:0],ctrl_io_out_bits_data[31:24],
     ctrl_io_out_bits_data[23:16]}; // @[Cat.scala 31:58]
   wire [31:0] _wdataS_T_17 = _wdataS_T_11 ? _wdataS_T_16 : 32'h0; // @[Library.scala 8:8]
-  wire [31:0] _wdataS_T_18 = _wdataS_T_10 | _wdataS_T_17; // @[Lsu.scala 173:75]
-  wire  _wdataS_T_19 = wsel == 2'h3; // @[Lsu.scala 175:16]
+  wire [31:0] _wdataS_T_18 = _wdataS_T_10 | _wdataS_T_17; // @[Lsu.scala 165:75]
+  wire  _wdataS_T_19 = wsel == 2'h3; // @[Lsu.scala 167:16]
   wire [31:0] _wdataS_T_24 = {ctrl_io_out_bits_data[7:0],ctrl_io_out_bits_data[31:24],ctrl_io_out_bits_data[23:16],
     ctrl_io_out_bits_data[15:8]}; // @[Cat.scala 31:58]
   wire [31:0] _wdataS_T_25 = _wdataS_T_19 ? _wdataS_T_24 : 32'h0; // @[Library.scala 8:8]
-  wire [31:0] wdataS = _wdataS_T_18 | _wdataS_T_25; // @[Lsu.scala 174:75]
-  wire [5:0] _wmaskT_T_2 = 6'h20 - ctrl_io_out_bits_size; // @[Lsu.scala 177:46]
-  wire [31:0] wmaskT = 32'hffffffff >> _wmaskT_T_2; // @[Lsu.scala 177:33]
-  wire [62:0] _GEN_34 = {{31'd0}, wmaskT}; // @[Lsu.scala 178:24]
-  wire [62:0] _wmaskS_T_1 = _GEN_34 << ctrl_io_out_bits_addr[4:0]; // @[Lsu.scala 178:24]
-  wire [5:0] _GEN_0 = {{1'd0}, ctrl_io_out_bits_addr[4:0]}; // @[Lsu.scala 179:41]
-  wire [5:0] _wmaskS_T_4 = 6'h20 - _GEN_0; // @[Lsu.scala 179:41]
-  wire [31:0] _wmaskS_T_5 = wmaskT >> _wmaskS_T_4; // @[Lsu.scala 179:24]
-  wire [62:0] _GEN_1 = {{31'd0}, _wmaskS_T_5}; // @[Lsu.scala 178:63]
-  wire [62:0] wmaskS = _wmaskS_T_1 | _GEN_1; // @[Lsu.scala 178:63]
+  wire [31:0] wdataS = _wdataS_T_18 | _wdataS_T_25; // @[Lsu.scala 166:75]
+  wire [5:0] _wmaskT_T_2 = 6'h20 - ctrl_io_out_bits_size; // @[Lsu.scala 169:46]
+  wire [31:0] wmaskT = 32'hffffffff >> _wmaskT_T_2; // @[Lsu.scala 169:33]
+  wire [62:0] _GEN_34 = {{31'd0}, wmaskT}; // @[Lsu.scala 170:24]
+  wire [62:0] _wmaskS_T_1 = _GEN_34 << ctrl_io_out_bits_addr[4:0]; // @[Lsu.scala 170:24]
+  wire [5:0] _GEN_0 = {{1'd0}, ctrl_io_out_bits_addr[4:0]}; // @[Lsu.scala 171:41]
+  wire [5:0] _wmaskS_T_4 = 6'h20 - _GEN_0; // @[Lsu.scala 171:41]
+  wire [31:0] _wmaskS_T_5 = wmaskT >> _wmaskS_T_4; // @[Lsu.scala 171:24]
+  wire [62:0] _GEN_1 = {{31'd0}, _wmaskS_T_5}; // @[Lsu.scala 170:63]
+  wire [62:0] wmaskS = _wmaskS_T_1 | _GEN_1; // @[Lsu.scala 170:63]
   wire [127:0] wdata_lo = {wdataS,wdataS,wdataS,wdataS}; // @[Cat.scala 31:58]
-  wire  _T_4 = ~reset; // @[Lsu.scala 204:9]
-  wire  _ctrl_io_out_ready_T_1 = io_dbus_valid & io_dbus_ready; // @[Lsu.scala 225:38]
-  wire  _ctrl_io_out_ready_T_2 = io_flush_valid & io_flush_ready | _ctrl_io_out_ready_T_1; // @[Lsu.scala 224:57]
-  wire  _ctrl_io_out_ready_T_3 = io_ubus_valid & io_ubus_ready; // @[Lsu.scala 226:38]
-  wire  _ctrl_io_out_ready_T_4 = _ctrl_io_out_ready_T_2 | _ctrl_io_out_ready_T_3; // @[Lsu.scala 225:55]
-  wire  _ctrl_io_out_ready_T_5 = ctrl_io_out_bits_vldst & io_dbus_ready; // @[Lsu.scala 227:47]
-  wire  _data_io_in_valid_T_5 = _ctrl_io_out_ready_T_3 & ~io_ubus_write; // @[Lsu.scala 234:54]
-  wire [4:0] rsel = data_io_out_bits_addr[4:0]; // @[Lsu.scala 254:36]
+  wire  _T_4 = ~reset; // @[Lsu.scala 196:9]
+  wire  _ctrl_io_out_ready_T_1 = io_dbus_valid & io_dbus_ready; // @[Lsu.scala 217:38]
+  wire  _ctrl_io_out_ready_T_2 = io_flush_valid & io_flush_ready | _ctrl_io_out_ready_T_1; // @[Lsu.scala 216:57]
+  wire  _ctrl_io_out_ready_T_3 = io_ubus_valid & io_ubus_ready; // @[Lsu.scala 218:38]
+  wire  _ctrl_io_out_ready_T_4 = _ctrl_io_out_ready_T_2 | _ctrl_io_out_ready_T_3; // @[Lsu.scala 217:55]
+  wire  _ctrl_io_out_ready_T_5 = ctrl_io_out_bits_vldst & io_dbus_ready; // @[Lsu.scala 219:47]
+  wire  _data_io_in_valid_T_5 = _ctrl_io_out_ready_T_3 & ~io_ubus_write; // @[Lsu.scala 226:54]
+  wire [4:0] rsel = data_io_out_bits_addr[4:0]; // @[Lsu.scala 245:36]
   wire [255:0] _rdata_T = data_io_out_bits_sldst ? io_dbus_rdata : 256'h0; // @[Library.scala 8:8]
   wire [255:0] _rdata_T_1 = data_io_out_bits_suncd ? io_ubus_rdata : 256'h0; // @[Library.scala 8:8]
-  wire [255:0] _rdata_T_2 = _rdata_T | _rdata_T_1; // @[Lsu.scala 289:71]
+  wire [255:0] _rdata_T_2 = _rdata_T | _rdata_T_1; // @[Lsu.scala 278:71]
   wire [31:0] rdata_rdata = {_rdata_T_2[31:24],_rdata_T_2[23:16],_rdata_T_2[15:8],_rdata_T_2[7:0]}; // @[Cat.scala 31:58]
-  wire  _rdata_sizeMask_T_2 = data_io_out_bits_size == 6'h2; // @[Lsu.scala 270:32]
-  wire [31:0] _rdata_sizeMask_T_3 = data_io_out_bits_size == 6'h2 ? 32'hffff : 32'hff; // @[Lsu.scala 270:25]
-  wire [31:0] rdata_sizeMask = data_io_out_bits_size == 6'h4 ? 32'hffffffff : _rdata_sizeMask_T_3; // @[Lsu.scala 269:25]
-  wire [31:0] _rdata_signExtend_T_3 = rdata_rdata[15] ? 32'hffff0000 : 32'h0; // @[Lsu.scala 274:31]
-  wire [31:0] _rdata_signExtend_T_6 = rdata_rdata[7] ? 32'hffffff00 : 32'h0; // @[Lsu.scala 275:31]
-  wire [31:0] _rdata_signExtend_T_7 = _rdata_sizeMask_T_2 ? _rdata_signExtend_T_3 : _rdata_signExtend_T_6; // @[Lsu.scala 273:29]
-  wire [31:0] rdata_signExtend = data_io_out_bits_sext ? _rdata_signExtend_T_7 : 32'h0; // @[Lsu.scala 272:27]
-  wire  _rdata_sdata_T = rsel == 5'h0; // @[Lsu.scala 280:30]
-  wire [31:0] _rdata_sdata_T_1 = rdata_rdata & rdata_sizeMask; // @[Lsu.scala 280:45]
-  wire [31:0] _rdata_sdata_T_2 = _rdata_sdata_T_1 | rdata_signExtend; // @[Lsu.scala 280:56]
+  wire  _rdata_sizeMask_T_2 = data_io_out_bits_size == 6'h2; // @[Lsu.scala 261:32]
+  wire [31:0] _rdata_sizeMask_T_3 = data_io_out_bits_size == 6'h2 ? 32'hffff : 32'hff; // @[Lsu.scala 261:25]
+  wire [31:0] rdata_sizeMask = data_io_out_bits_size == 6'h4 ? 32'hffffffff : _rdata_sizeMask_T_3; // @[Lsu.scala 260:25]
+  wire [31:0] _rdata_signExtend_T_3 = rdata_rdata[15] ? 32'hffff0000 : 32'h0; // @[Lsu.scala 265:31]
+  wire [31:0] _rdata_signExtend_T_6 = rdata_rdata[7] ? 32'hffffff00 : 32'h0; // @[Lsu.scala 266:31]
+  wire [31:0] _rdata_signExtend_T_7 = _rdata_sizeMask_T_2 ? _rdata_signExtend_T_3 : _rdata_signExtend_T_6; // @[Lsu.scala 264:29]
+  wire [31:0] rdata_signExtend = data_io_out_bits_sext ? _rdata_signExtend_T_7 : 32'h0; // @[Lsu.scala 263:27]
+  wire  _rdata_sdata_T = rsel == 5'h0; // @[Lsu.scala 271:30]
+  wire [31:0] _rdata_sdata_T_1 = rdata_rdata & rdata_sizeMask; // @[Lsu.scala 271:45]
+  wire [31:0] _rdata_sdata_T_2 = _rdata_sdata_T_1 | rdata_signExtend; // @[Lsu.scala 271:56]
   wire [31:0] rdata_sdata = _rdata_sdata_T ? _rdata_sdata_T_2 : 32'h0; // @[Library.scala 8:8]
-  wire [255:0] _rdata_T_3 = {{224'd0}, rdata_sdata}; // @[Lsu.scala 281:34]
+  wire [255:0] _rdata_T_3 = {{224'd0}, rdata_sdata}; // @[Lsu.scala 272:34]
   wire [31:0] rdata_rdata_1 = {_rdata_T_2[39:32],_rdata_T_2[31:24],_rdata_T_2[23:16],_rdata_T_2[15:8]}; // @[Cat.scala 31:58]
-  wire [31:0] _rdata_signExtend_T_11 = rdata_rdata_1[15] ? 32'hffff0000 : 32'h0; // @[Lsu.scala 274:31]
-  wire [31:0] _rdata_signExtend_T_14 = rdata_rdata_1[7] ? 32'hffffff00 : 32'h0; // @[Lsu.scala 275:31]
-  wire [31:0] _rdata_signExtend_T_15 = _rdata_sizeMask_T_2 ? _rdata_signExtend_T_11 : _rdata_signExtend_T_14; // @[Lsu.scala 273:29]
-  wire [31:0] rdata_signExtend_1 = data_io_out_bits_sext ? _rdata_signExtend_T_15 : 32'h0; // @[Lsu.scala 272:27]
-  wire  _rdata_sdata_T_3 = rsel == 5'h1; // @[Lsu.scala 280:30]
-  wire [31:0] _rdata_sdata_T_4 = rdata_rdata_1 & rdata_sizeMask; // @[Lsu.scala 280:45]
-  wire [31:0] _rdata_sdata_T_5 = _rdata_sdata_T_4 | rdata_signExtend_1; // @[Lsu.scala 280:56]
+  wire [31:0] _rdata_signExtend_T_11 = rdata_rdata_1[15] ? 32'hffff0000 : 32'h0; // @[Lsu.scala 265:31]
+  wire [31:0] _rdata_signExtend_T_14 = rdata_rdata_1[7] ? 32'hffffff00 : 32'h0; // @[Lsu.scala 266:31]
+  wire [31:0] _rdata_signExtend_T_15 = _rdata_sizeMask_T_2 ? _rdata_signExtend_T_11 : _rdata_signExtend_T_14; // @[Lsu.scala 264:29]
+  wire [31:0] rdata_signExtend_1 = data_io_out_bits_sext ? _rdata_signExtend_T_15 : 32'h0; // @[Lsu.scala 263:27]
+  wire  _rdata_sdata_T_3 = rsel == 5'h1; // @[Lsu.scala 271:30]
+  wire [31:0] _rdata_sdata_T_4 = rdata_rdata_1 & rdata_sizeMask; // @[Lsu.scala 271:45]
+  wire [31:0] _rdata_sdata_T_5 = _rdata_sdata_T_4 | rdata_signExtend_1; // @[Lsu.scala 271:56]
   wire [31:0] rdata_sdata_1 = _rdata_sdata_T_3 ? _rdata_sdata_T_5 : 32'h0; // @[Library.scala 8:8]
-  wire [255:0] _GEN_2 = {{224'd0}, rdata_sdata_1}; // @[Lsu.scala 281:34]
-  wire [255:0] _rdata_T_4 = _rdata_T_3 | _GEN_2; // @[Lsu.scala 281:34]
+  wire [255:0] _GEN_2 = {{224'd0}, rdata_sdata_1}; // @[Lsu.scala 272:34]
+  wire [255:0] _rdata_T_4 = _rdata_T_3 | _GEN_2; // @[Lsu.scala 272:34]
   wire [31:0] rdata_rdata_2 = {_rdata_T_2[47:40],_rdata_T_2[39:32],_rdata_T_2[31:24],_rdata_T_2[23:16]}; // @[Cat.scala 31:58]
-  wire [31:0] _rdata_signExtend_T_19 = rdata_rdata_2[15] ? 32'hffff0000 : 32'h0; // @[Lsu.scala 274:31]
-  wire [31:0] _rdata_signExtend_T_22 = rdata_rdata_2[7] ? 32'hffffff00 : 32'h0; // @[Lsu.scala 275:31]
-  wire [31:0] _rdata_signExtend_T_23 = _rdata_sizeMask_T_2 ? _rdata_signExtend_T_19 : _rdata_signExtend_T_22; // @[Lsu.scala 273:29]
-  wire [31:0] rdata_signExtend_2 = data_io_out_bits_sext ? _rdata_signExtend_T_23 : 32'h0; // @[Lsu.scala 272:27]
-  wire  _rdata_sdata_T_6 = rsel == 5'h2; // @[Lsu.scala 280:30]
-  wire [31:0] _rdata_sdata_T_7 = rdata_rdata_2 & rdata_sizeMask; // @[Lsu.scala 280:45]
-  wire [31:0] _rdata_sdata_T_8 = _rdata_sdata_T_7 | rdata_signExtend_2; // @[Lsu.scala 280:56]
+  wire [31:0] _rdata_signExtend_T_19 = rdata_rdata_2[15] ? 32'hffff0000 : 32'h0; // @[Lsu.scala 265:31]
+  wire [31:0] _rdata_signExtend_T_22 = rdata_rdata_2[7] ? 32'hffffff00 : 32'h0; // @[Lsu.scala 266:31]
+  wire [31:0] _rdata_signExtend_T_23 = _rdata_sizeMask_T_2 ? _rdata_signExtend_T_19 : _rdata_signExtend_T_22; // @[Lsu.scala 264:29]
+  wire [31:0] rdata_signExtend_2 = data_io_out_bits_sext ? _rdata_signExtend_T_23 : 32'h0; // @[Lsu.scala 263:27]
+  wire  _rdata_sdata_T_6 = rsel == 5'h2; // @[Lsu.scala 271:30]
+  wire [31:0] _rdata_sdata_T_7 = rdata_rdata_2 & rdata_sizeMask; // @[Lsu.scala 271:45]
+  wire [31:0] _rdata_sdata_T_8 = _rdata_sdata_T_7 | rdata_signExtend_2; // @[Lsu.scala 271:56]
   wire [31:0] rdata_sdata_2 = _rdata_sdata_T_6 ? _rdata_sdata_T_8 : 32'h0; // @[Library.scala 8:8]
-  wire [255:0] _GEN_3 = {{224'd0}, rdata_sdata_2}; // @[Lsu.scala 281:34]
-  wire [255:0] _rdata_T_5 = _rdata_T_4 | _GEN_3; // @[Lsu.scala 281:34]
+  wire [255:0] _GEN_3 = {{224'd0}, rdata_sdata_2}; // @[Lsu.scala 272:34]
+  wire [255:0] _rdata_T_5 = _rdata_T_4 | _GEN_3; // @[Lsu.scala 272:34]
   wire [31:0] rdata_rdata_3 = {_rdata_T_2[55:48],_rdata_T_2[47:40],_rdata_T_2[39:32],_rdata_T_2[31:24]}; // @[Cat.scala 31:58]
-  wire [31:0] _rdata_signExtend_T_27 = rdata_rdata_3[15] ? 32'hffff0000 : 32'h0; // @[Lsu.scala 274:31]
-  wire [31:0] _rdata_signExtend_T_30 = rdata_rdata_3[7] ? 32'hffffff00 : 32'h0; // @[Lsu.scala 275:31]
-  wire [31:0] _rdata_signExtend_T_31 = _rdata_sizeMask_T_2 ? _rdata_signExtend_T_27 : _rdata_signExtend_T_30; // @[Lsu.scala 273:29]
-  wire [31:0] rdata_signExtend_3 = data_io_out_bits_sext ? _rdata_signExtend_T_31 : 32'h0; // @[Lsu.scala 272:27]
-  wire  _rdata_sdata_T_9 = rsel == 5'h3; // @[Lsu.scala 280:30]
-  wire [31:0] _rdata_sdata_T_10 = rdata_rdata_3 & rdata_sizeMask; // @[Lsu.scala 280:45]
-  wire [31:0] _rdata_sdata_T_11 = _rdata_sdata_T_10 | rdata_signExtend_3; // @[Lsu.scala 280:56]
+  wire [31:0] _rdata_signExtend_T_27 = rdata_rdata_3[15] ? 32'hffff0000 : 32'h0; // @[Lsu.scala 265:31]
+  wire [31:0] _rdata_signExtend_T_30 = rdata_rdata_3[7] ? 32'hffffff00 : 32'h0; // @[Lsu.scala 266:31]
+  wire [31:0] _rdata_signExtend_T_31 = _rdata_sizeMask_T_2 ? _rdata_signExtend_T_27 : _rdata_signExtend_T_30; // @[Lsu.scala 264:29]
+  wire [31:0] rdata_signExtend_3 = data_io_out_bits_sext ? _rdata_signExtend_T_31 : 32'h0; // @[Lsu.scala 263:27]
+  wire  _rdata_sdata_T_9 = rsel == 5'h3; // @[Lsu.scala 271:30]
+  wire [31:0] _rdata_sdata_T_10 = rdata_rdata_3 & rdata_sizeMask; // @[Lsu.scala 271:45]
+  wire [31:0] _rdata_sdata_T_11 = _rdata_sdata_T_10 | rdata_signExtend_3; // @[Lsu.scala 271:56]
   wire [31:0] rdata_sdata_3 = _rdata_sdata_T_9 ? _rdata_sdata_T_11 : 32'h0; // @[Library.scala 8:8]
-  wire [255:0] _GEN_4 = {{224'd0}, rdata_sdata_3}; // @[Lsu.scala 281:34]
-  wire [255:0] _rdata_T_6 = _rdata_T_5 | _GEN_4; // @[Lsu.scala 281:34]
+  wire [255:0] _GEN_4 = {{224'd0}, rdata_sdata_3}; // @[Lsu.scala 272:34]
+  wire [255:0] _rdata_T_6 = _rdata_T_5 | _GEN_4; // @[Lsu.scala 272:34]
   wire [31:0] rdata_rdata_4 = {_rdata_T_2[63:56],_rdata_T_2[55:48],_rdata_T_2[47:40],_rdata_T_2[39:32]}; // @[Cat.scala 31:58]
-  wire [31:0] _rdata_signExtend_T_35 = rdata_rdata_4[15] ? 32'hffff0000 : 32'h0; // @[Lsu.scala 274:31]
-  wire [31:0] _rdata_signExtend_T_38 = rdata_rdata_4[7] ? 32'hffffff00 : 32'h0; // @[Lsu.scala 275:31]
-  wire [31:0] _rdata_signExtend_T_39 = _rdata_sizeMask_T_2 ? _rdata_signExtend_T_35 : _rdata_signExtend_T_38; // @[Lsu.scala 273:29]
-  wire [31:0] rdata_signExtend_4 = data_io_out_bits_sext ? _rdata_signExtend_T_39 : 32'h0; // @[Lsu.scala 272:27]
-  wire  _rdata_sdata_T_12 = rsel == 5'h4; // @[Lsu.scala 280:30]
-  wire [31:0] _rdata_sdata_T_13 = rdata_rdata_4 & rdata_sizeMask; // @[Lsu.scala 280:45]
-  wire [31:0] _rdata_sdata_T_14 = _rdata_sdata_T_13 | rdata_signExtend_4; // @[Lsu.scala 280:56]
+  wire [31:0] _rdata_signExtend_T_35 = rdata_rdata_4[15] ? 32'hffff0000 : 32'h0; // @[Lsu.scala 265:31]
+  wire [31:0] _rdata_signExtend_T_38 = rdata_rdata_4[7] ? 32'hffffff00 : 32'h0; // @[Lsu.scala 266:31]
+  wire [31:0] _rdata_signExtend_T_39 = _rdata_sizeMask_T_2 ? _rdata_signExtend_T_35 : _rdata_signExtend_T_38; // @[Lsu.scala 264:29]
+  wire [31:0] rdata_signExtend_4 = data_io_out_bits_sext ? _rdata_signExtend_T_39 : 32'h0; // @[Lsu.scala 263:27]
+  wire  _rdata_sdata_T_12 = rsel == 5'h4; // @[Lsu.scala 271:30]
+  wire [31:0] _rdata_sdata_T_13 = rdata_rdata_4 & rdata_sizeMask; // @[Lsu.scala 271:45]
+  wire [31:0] _rdata_sdata_T_14 = _rdata_sdata_T_13 | rdata_signExtend_4; // @[Lsu.scala 271:56]
   wire [31:0] rdata_sdata_4 = _rdata_sdata_T_12 ? _rdata_sdata_T_14 : 32'h0; // @[Library.scala 8:8]
-  wire [255:0] _GEN_5 = {{224'd0}, rdata_sdata_4}; // @[Lsu.scala 281:34]
-  wire [255:0] _rdata_T_7 = _rdata_T_6 | _GEN_5; // @[Lsu.scala 281:34]
+  wire [255:0] _GEN_5 = {{224'd0}, rdata_sdata_4}; // @[Lsu.scala 272:34]
+  wire [255:0] _rdata_T_7 = _rdata_T_6 | _GEN_5; // @[Lsu.scala 272:34]
   wire [31:0] rdata_rdata_5 = {_rdata_T_2[71:64],_rdata_T_2[63:56],_rdata_T_2[55:48],_rdata_T_2[47:40]}; // @[Cat.scala 31:58]
-  wire [31:0] _rdata_signExtend_T_43 = rdata_rdata_5[15] ? 32'hffff0000 : 32'h0; // @[Lsu.scala 274:31]
-  wire [31:0] _rdata_signExtend_T_46 = rdata_rdata_5[7] ? 32'hffffff00 : 32'h0; // @[Lsu.scala 275:31]
-  wire [31:0] _rdata_signExtend_T_47 = _rdata_sizeMask_T_2 ? _rdata_signExtend_T_43 : _rdata_signExtend_T_46; // @[Lsu.scala 273:29]
-  wire [31:0] rdata_signExtend_5 = data_io_out_bits_sext ? _rdata_signExtend_T_47 : 32'h0; // @[Lsu.scala 272:27]
-  wire  _rdata_sdata_T_15 = rsel == 5'h5; // @[Lsu.scala 280:30]
-  wire [31:0] _rdata_sdata_T_16 = rdata_rdata_5 & rdata_sizeMask; // @[Lsu.scala 280:45]
-  wire [31:0] _rdata_sdata_T_17 = _rdata_sdata_T_16 | rdata_signExtend_5; // @[Lsu.scala 280:56]
+  wire [31:0] _rdata_signExtend_T_43 = rdata_rdata_5[15] ? 32'hffff0000 : 32'h0; // @[Lsu.scala 265:31]
+  wire [31:0] _rdata_signExtend_T_46 = rdata_rdata_5[7] ? 32'hffffff00 : 32'h0; // @[Lsu.scala 266:31]
+  wire [31:0] _rdata_signExtend_T_47 = _rdata_sizeMask_T_2 ? _rdata_signExtend_T_43 : _rdata_signExtend_T_46; // @[Lsu.scala 264:29]
+  wire [31:0] rdata_signExtend_5 = data_io_out_bits_sext ? _rdata_signExtend_T_47 : 32'h0; // @[Lsu.scala 263:27]
+  wire  _rdata_sdata_T_15 = rsel == 5'h5; // @[Lsu.scala 271:30]
+  wire [31:0] _rdata_sdata_T_16 = rdata_rdata_5 & rdata_sizeMask; // @[Lsu.scala 271:45]
+  wire [31:0] _rdata_sdata_T_17 = _rdata_sdata_T_16 | rdata_signExtend_5; // @[Lsu.scala 271:56]
   wire [31:0] rdata_sdata_5 = _rdata_sdata_T_15 ? _rdata_sdata_T_17 : 32'h0; // @[Library.scala 8:8]
-  wire [255:0] _GEN_6 = {{224'd0}, rdata_sdata_5}; // @[Lsu.scala 281:34]
-  wire [255:0] _rdata_T_8 = _rdata_T_7 | _GEN_6; // @[Lsu.scala 281:34]
+  wire [255:0] _GEN_6 = {{224'd0}, rdata_sdata_5}; // @[Lsu.scala 272:34]
+  wire [255:0] _rdata_T_8 = _rdata_T_7 | _GEN_6; // @[Lsu.scala 272:34]
   wire [31:0] rdata_rdata_6 = {_rdata_T_2[79:72],_rdata_T_2[71:64],_rdata_T_2[63:56],_rdata_T_2[55:48]}; // @[Cat.scala 31:58]
-  wire [31:0] _rdata_signExtend_T_51 = rdata_rdata_6[15] ? 32'hffff0000 : 32'h0; // @[Lsu.scala 274:31]
-  wire [31:0] _rdata_signExtend_T_54 = rdata_rdata_6[7] ? 32'hffffff00 : 32'h0; // @[Lsu.scala 275:31]
-  wire [31:0] _rdata_signExtend_T_55 = _rdata_sizeMask_T_2 ? _rdata_signExtend_T_51 : _rdata_signExtend_T_54; // @[Lsu.scala 273:29]
-  wire [31:0] rdata_signExtend_6 = data_io_out_bits_sext ? _rdata_signExtend_T_55 : 32'h0; // @[Lsu.scala 272:27]
-  wire  _rdata_sdata_T_18 = rsel == 5'h6; // @[Lsu.scala 280:30]
-  wire [31:0] _rdata_sdata_T_19 = rdata_rdata_6 & rdata_sizeMask; // @[Lsu.scala 280:45]
-  wire [31:0] _rdata_sdata_T_20 = _rdata_sdata_T_19 | rdata_signExtend_6; // @[Lsu.scala 280:56]
+  wire [31:0] _rdata_signExtend_T_51 = rdata_rdata_6[15] ? 32'hffff0000 : 32'h0; // @[Lsu.scala 265:31]
+  wire [31:0] _rdata_signExtend_T_54 = rdata_rdata_6[7] ? 32'hffffff00 : 32'h0; // @[Lsu.scala 266:31]
+  wire [31:0] _rdata_signExtend_T_55 = _rdata_sizeMask_T_2 ? _rdata_signExtend_T_51 : _rdata_signExtend_T_54; // @[Lsu.scala 264:29]
+  wire [31:0] rdata_signExtend_6 = data_io_out_bits_sext ? _rdata_signExtend_T_55 : 32'h0; // @[Lsu.scala 263:27]
+  wire  _rdata_sdata_T_18 = rsel == 5'h6; // @[Lsu.scala 271:30]
+  wire [31:0] _rdata_sdata_T_19 = rdata_rdata_6 & rdata_sizeMask; // @[Lsu.scala 271:45]
+  wire [31:0] _rdata_sdata_T_20 = _rdata_sdata_T_19 | rdata_signExtend_6; // @[Lsu.scala 271:56]
   wire [31:0] rdata_sdata_6 = _rdata_sdata_T_18 ? _rdata_sdata_T_20 : 32'h0; // @[Library.scala 8:8]
-  wire [255:0] _GEN_7 = {{224'd0}, rdata_sdata_6}; // @[Lsu.scala 281:34]
-  wire [255:0] _rdata_T_9 = _rdata_T_8 | _GEN_7; // @[Lsu.scala 281:34]
+  wire [255:0] _GEN_7 = {{224'd0}, rdata_sdata_6}; // @[Lsu.scala 272:34]
+  wire [255:0] _rdata_T_9 = _rdata_T_8 | _GEN_7; // @[Lsu.scala 272:34]
   wire [31:0] rdata_rdata_7 = {_rdata_T_2[87:80],_rdata_T_2[79:72],_rdata_T_2[71:64],_rdata_T_2[63:56]}; // @[Cat.scala 31:58]
-  wire [31:0] _rdata_signExtend_T_59 = rdata_rdata_7[15] ? 32'hffff0000 : 32'h0; // @[Lsu.scala 274:31]
-  wire [31:0] _rdata_signExtend_T_62 = rdata_rdata_7[7] ? 32'hffffff00 : 32'h0; // @[Lsu.scala 275:31]
-  wire [31:0] _rdata_signExtend_T_63 = _rdata_sizeMask_T_2 ? _rdata_signExtend_T_59 : _rdata_signExtend_T_62; // @[Lsu.scala 273:29]
-  wire [31:0] rdata_signExtend_7 = data_io_out_bits_sext ? _rdata_signExtend_T_63 : 32'h0; // @[Lsu.scala 272:27]
-  wire  _rdata_sdata_T_21 = rsel == 5'h7; // @[Lsu.scala 280:30]
-  wire [31:0] _rdata_sdata_T_22 = rdata_rdata_7 & rdata_sizeMask; // @[Lsu.scala 280:45]
-  wire [31:0] _rdata_sdata_T_23 = _rdata_sdata_T_22 | rdata_signExtend_7; // @[Lsu.scala 280:56]
+  wire [31:0] _rdata_signExtend_T_59 = rdata_rdata_7[15] ? 32'hffff0000 : 32'h0; // @[Lsu.scala 265:31]
+  wire [31:0] _rdata_signExtend_T_62 = rdata_rdata_7[7] ? 32'hffffff00 : 32'h0; // @[Lsu.scala 266:31]
+  wire [31:0] _rdata_signExtend_T_63 = _rdata_sizeMask_T_2 ? _rdata_signExtend_T_59 : _rdata_signExtend_T_62; // @[Lsu.scala 264:29]
+  wire [31:0] rdata_signExtend_7 = data_io_out_bits_sext ? _rdata_signExtend_T_63 : 32'h0; // @[Lsu.scala 263:27]
+  wire  _rdata_sdata_T_21 = rsel == 5'h7; // @[Lsu.scala 271:30]
+  wire [31:0] _rdata_sdata_T_22 = rdata_rdata_7 & rdata_sizeMask; // @[Lsu.scala 271:45]
+  wire [31:0] _rdata_sdata_T_23 = _rdata_sdata_T_22 | rdata_signExtend_7; // @[Lsu.scala 271:56]
   wire [31:0] rdata_sdata_7 = _rdata_sdata_T_21 ? _rdata_sdata_T_23 : 32'h0; // @[Library.scala 8:8]
-  wire [255:0] _GEN_8 = {{224'd0}, rdata_sdata_7}; // @[Lsu.scala 281:34]
-  wire [255:0] _rdata_T_10 = _rdata_T_9 | _GEN_8; // @[Lsu.scala 281:34]
+  wire [255:0] _GEN_8 = {{224'd0}, rdata_sdata_7}; // @[Lsu.scala 272:34]
+  wire [255:0] _rdata_T_10 = _rdata_T_9 | _GEN_8; // @[Lsu.scala 272:34]
   wire [31:0] rdata_rdata_8 = {_rdata_T_2[95:88],_rdata_T_2[87:80],_rdata_T_2[79:72],_rdata_T_2[71:64]}; // @[Cat.scala 31:58]
-  wire [31:0] _rdata_signExtend_T_67 = rdata_rdata_8[15] ? 32'hffff0000 : 32'h0; // @[Lsu.scala 274:31]
-  wire [31:0] _rdata_signExtend_T_70 = rdata_rdata_8[7] ? 32'hffffff00 : 32'h0; // @[Lsu.scala 275:31]
-  wire [31:0] _rdata_signExtend_T_71 = _rdata_sizeMask_T_2 ? _rdata_signExtend_T_67 : _rdata_signExtend_T_70; // @[Lsu.scala 273:29]
-  wire [31:0] rdata_signExtend_8 = data_io_out_bits_sext ? _rdata_signExtend_T_71 : 32'h0; // @[Lsu.scala 272:27]
-  wire  _rdata_sdata_T_24 = rsel == 5'h8; // @[Lsu.scala 280:30]
-  wire [31:0] _rdata_sdata_T_25 = rdata_rdata_8 & rdata_sizeMask; // @[Lsu.scala 280:45]
-  wire [31:0] _rdata_sdata_T_26 = _rdata_sdata_T_25 | rdata_signExtend_8; // @[Lsu.scala 280:56]
+  wire [31:0] _rdata_signExtend_T_67 = rdata_rdata_8[15] ? 32'hffff0000 : 32'h0; // @[Lsu.scala 265:31]
+  wire [31:0] _rdata_signExtend_T_70 = rdata_rdata_8[7] ? 32'hffffff00 : 32'h0; // @[Lsu.scala 266:31]
+  wire [31:0] _rdata_signExtend_T_71 = _rdata_sizeMask_T_2 ? _rdata_signExtend_T_67 : _rdata_signExtend_T_70; // @[Lsu.scala 264:29]
+  wire [31:0] rdata_signExtend_8 = data_io_out_bits_sext ? _rdata_signExtend_T_71 : 32'h0; // @[Lsu.scala 263:27]
+  wire  _rdata_sdata_T_24 = rsel == 5'h8; // @[Lsu.scala 271:30]
+  wire [31:0] _rdata_sdata_T_25 = rdata_rdata_8 & rdata_sizeMask; // @[Lsu.scala 271:45]
+  wire [31:0] _rdata_sdata_T_26 = _rdata_sdata_T_25 | rdata_signExtend_8; // @[Lsu.scala 271:56]
   wire [31:0] rdata_sdata_8 = _rdata_sdata_T_24 ? _rdata_sdata_T_26 : 32'h0; // @[Library.scala 8:8]
-  wire [255:0] _GEN_9 = {{224'd0}, rdata_sdata_8}; // @[Lsu.scala 281:34]
-  wire [255:0] _rdata_T_11 = _rdata_T_10 | _GEN_9; // @[Lsu.scala 281:34]
+  wire [255:0] _GEN_9 = {{224'd0}, rdata_sdata_8}; // @[Lsu.scala 272:34]
+  wire [255:0] _rdata_T_11 = _rdata_T_10 | _GEN_9; // @[Lsu.scala 272:34]
   wire [31:0] rdata_rdata_9 = {_rdata_T_2[103:96],_rdata_T_2[95:88],_rdata_T_2[87:80],_rdata_T_2[79:72]}; // @[Cat.scala 31:58]
-  wire [31:0] _rdata_signExtend_T_75 = rdata_rdata_9[15] ? 32'hffff0000 : 32'h0; // @[Lsu.scala 274:31]
-  wire [31:0] _rdata_signExtend_T_78 = rdata_rdata_9[7] ? 32'hffffff00 : 32'h0; // @[Lsu.scala 275:31]
-  wire [31:0] _rdata_signExtend_T_79 = _rdata_sizeMask_T_2 ? _rdata_signExtend_T_75 : _rdata_signExtend_T_78; // @[Lsu.scala 273:29]
-  wire [31:0] rdata_signExtend_9 = data_io_out_bits_sext ? _rdata_signExtend_T_79 : 32'h0; // @[Lsu.scala 272:27]
-  wire  _rdata_sdata_T_27 = rsel == 5'h9; // @[Lsu.scala 280:30]
-  wire [31:0] _rdata_sdata_T_28 = rdata_rdata_9 & rdata_sizeMask; // @[Lsu.scala 280:45]
-  wire [31:0] _rdata_sdata_T_29 = _rdata_sdata_T_28 | rdata_signExtend_9; // @[Lsu.scala 280:56]
+  wire [31:0] _rdata_signExtend_T_75 = rdata_rdata_9[15] ? 32'hffff0000 : 32'h0; // @[Lsu.scala 265:31]
+  wire [31:0] _rdata_signExtend_T_78 = rdata_rdata_9[7] ? 32'hffffff00 : 32'h0; // @[Lsu.scala 266:31]
+  wire [31:0] _rdata_signExtend_T_79 = _rdata_sizeMask_T_2 ? _rdata_signExtend_T_75 : _rdata_signExtend_T_78; // @[Lsu.scala 264:29]
+  wire [31:0] rdata_signExtend_9 = data_io_out_bits_sext ? _rdata_signExtend_T_79 : 32'h0; // @[Lsu.scala 263:27]
+  wire  _rdata_sdata_T_27 = rsel == 5'h9; // @[Lsu.scala 271:30]
+  wire [31:0] _rdata_sdata_T_28 = rdata_rdata_9 & rdata_sizeMask; // @[Lsu.scala 271:45]
+  wire [31:0] _rdata_sdata_T_29 = _rdata_sdata_T_28 | rdata_signExtend_9; // @[Lsu.scala 271:56]
   wire [31:0] rdata_sdata_9 = _rdata_sdata_T_27 ? _rdata_sdata_T_29 : 32'h0; // @[Library.scala 8:8]
-  wire [255:0] _GEN_10 = {{224'd0}, rdata_sdata_9}; // @[Lsu.scala 281:34]
-  wire [255:0] _rdata_T_12 = _rdata_T_11 | _GEN_10; // @[Lsu.scala 281:34]
+  wire [255:0] _GEN_10 = {{224'd0}, rdata_sdata_9}; // @[Lsu.scala 272:34]
+  wire [255:0] _rdata_T_12 = _rdata_T_11 | _GEN_10; // @[Lsu.scala 272:34]
   wire [31:0] rdata_rdata_10 = {_rdata_T_2[111:104],_rdata_T_2[103:96],_rdata_T_2[95:88],_rdata_T_2[87:80]}; // @[Cat.scala 31:58]
-  wire [31:0] _rdata_signExtend_T_83 = rdata_rdata_10[15] ? 32'hffff0000 : 32'h0; // @[Lsu.scala 274:31]
-  wire [31:0] _rdata_signExtend_T_86 = rdata_rdata_10[7] ? 32'hffffff00 : 32'h0; // @[Lsu.scala 275:31]
-  wire [31:0] _rdata_signExtend_T_87 = _rdata_sizeMask_T_2 ? _rdata_signExtend_T_83 : _rdata_signExtend_T_86; // @[Lsu.scala 273:29]
-  wire [31:0] rdata_signExtend_10 = data_io_out_bits_sext ? _rdata_signExtend_T_87 : 32'h0; // @[Lsu.scala 272:27]
-  wire  _rdata_sdata_T_30 = rsel == 5'ha; // @[Lsu.scala 280:30]
-  wire [31:0] _rdata_sdata_T_31 = rdata_rdata_10 & rdata_sizeMask; // @[Lsu.scala 280:45]
-  wire [31:0] _rdata_sdata_T_32 = _rdata_sdata_T_31 | rdata_signExtend_10; // @[Lsu.scala 280:56]
+  wire [31:0] _rdata_signExtend_T_83 = rdata_rdata_10[15] ? 32'hffff0000 : 32'h0; // @[Lsu.scala 265:31]
+  wire [31:0] _rdata_signExtend_T_86 = rdata_rdata_10[7] ? 32'hffffff00 : 32'h0; // @[Lsu.scala 266:31]
+  wire [31:0] _rdata_signExtend_T_87 = _rdata_sizeMask_T_2 ? _rdata_signExtend_T_83 : _rdata_signExtend_T_86; // @[Lsu.scala 264:29]
+  wire [31:0] rdata_signExtend_10 = data_io_out_bits_sext ? _rdata_signExtend_T_87 : 32'h0; // @[Lsu.scala 263:27]
+  wire  _rdata_sdata_T_30 = rsel == 5'ha; // @[Lsu.scala 271:30]
+  wire [31:0] _rdata_sdata_T_31 = rdata_rdata_10 & rdata_sizeMask; // @[Lsu.scala 271:45]
+  wire [31:0] _rdata_sdata_T_32 = _rdata_sdata_T_31 | rdata_signExtend_10; // @[Lsu.scala 271:56]
   wire [31:0] rdata_sdata_10 = _rdata_sdata_T_30 ? _rdata_sdata_T_32 : 32'h0; // @[Library.scala 8:8]
-  wire [255:0] _GEN_11 = {{224'd0}, rdata_sdata_10}; // @[Lsu.scala 281:34]
-  wire [255:0] _rdata_T_13 = _rdata_T_12 | _GEN_11; // @[Lsu.scala 281:34]
+  wire [255:0] _GEN_11 = {{224'd0}, rdata_sdata_10}; // @[Lsu.scala 272:34]
+  wire [255:0] _rdata_T_13 = _rdata_T_12 | _GEN_11; // @[Lsu.scala 272:34]
   wire [31:0] rdata_rdata_11 = {_rdata_T_2[119:112],_rdata_T_2[111:104],_rdata_T_2[103:96],_rdata_T_2[95:88]}; // @[Cat.scala 31:58]
-  wire [31:0] _rdata_signExtend_T_91 = rdata_rdata_11[15] ? 32'hffff0000 : 32'h0; // @[Lsu.scala 274:31]
-  wire [31:0] _rdata_signExtend_T_94 = rdata_rdata_11[7] ? 32'hffffff00 : 32'h0; // @[Lsu.scala 275:31]
-  wire [31:0] _rdata_signExtend_T_95 = _rdata_sizeMask_T_2 ? _rdata_signExtend_T_91 : _rdata_signExtend_T_94; // @[Lsu.scala 273:29]
-  wire [31:0] rdata_signExtend_11 = data_io_out_bits_sext ? _rdata_signExtend_T_95 : 32'h0; // @[Lsu.scala 272:27]
-  wire  _rdata_sdata_T_33 = rsel == 5'hb; // @[Lsu.scala 280:30]
-  wire [31:0] _rdata_sdata_T_34 = rdata_rdata_11 & rdata_sizeMask; // @[Lsu.scala 280:45]
-  wire [31:0] _rdata_sdata_T_35 = _rdata_sdata_T_34 | rdata_signExtend_11; // @[Lsu.scala 280:56]
+  wire [31:0] _rdata_signExtend_T_91 = rdata_rdata_11[15] ? 32'hffff0000 : 32'h0; // @[Lsu.scala 265:31]
+  wire [31:0] _rdata_signExtend_T_94 = rdata_rdata_11[7] ? 32'hffffff00 : 32'h0; // @[Lsu.scala 266:31]
+  wire [31:0] _rdata_signExtend_T_95 = _rdata_sizeMask_T_2 ? _rdata_signExtend_T_91 : _rdata_signExtend_T_94; // @[Lsu.scala 264:29]
+  wire [31:0] rdata_signExtend_11 = data_io_out_bits_sext ? _rdata_signExtend_T_95 : 32'h0; // @[Lsu.scala 263:27]
+  wire  _rdata_sdata_T_33 = rsel == 5'hb; // @[Lsu.scala 271:30]
+  wire [31:0] _rdata_sdata_T_34 = rdata_rdata_11 & rdata_sizeMask; // @[Lsu.scala 271:45]
+  wire [31:0] _rdata_sdata_T_35 = _rdata_sdata_T_34 | rdata_signExtend_11; // @[Lsu.scala 271:56]
   wire [31:0] rdata_sdata_11 = _rdata_sdata_T_33 ? _rdata_sdata_T_35 : 32'h0; // @[Library.scala 8:8]
-  wire [255:0] _GEN_12 = {{224'd0}, rdata_sdata_11}; // @[Lsu.scala 281:34]
-  wire [255:0] _rdata_T_14 = _rdata_T_13 | _GEN_12; // @[Lsu.scala 281:34]
+  wire [255:0] _GEN_12 = {{224'd0}, rdata_sdata_11}; // @[Lsu.scala 272:34]
+  wire [255:0] _rdata_T_14 = _rdata_T_13 | _GEN_12; // @[Lsu.scala 272:34]
   wire [31:0] rdata_rdata_12 = {_rdata_T_2[127:120],_rdata_T_2[119:112],_rdata_T_2[111:104],_rdata_T_2[103:96]}; // @[Cat.scala 31:58]
-  wire [31:0] _rdata_signExtend_T_99 = rdata_rdata_12[15] ? 32'hffff0000 : 32'h0; // @[Lsu.scala 274:31]
-  wire [31:0] _rdata_signExtend_T_102 = rdata_rdata_12[7] ? 32'hffffff00 : 32'h0; // @[Lsu.scala 275:31]
-  wire [31:0] _rdata_signExtend_T_103 = _rdata_sizeMask_T_2 ? _rdata_signExtend_T_99 : _rdata_signExtend_T_102; // @[Lsu.scala 273:29]
-  wire [31:0] rdata_signExtend_12 = data_io_out_bits_sext ? _rdata_signExtend_T_103 : 32'h0; // @[Lsu.scala 272:27]
-  wire  _rdata_sdata_T_36 = rsel == 5'hc; // @[Lsu.scala 280:30]
-  wire [31:0] _rdata_sdata_T_37 = rdata_rdata_12 & rdata_sizeMask; // @[Lsu.scala 280:45]
-  wire [31:0] _rdata_sdata_T_38 = _rdata_sdata_T_37 | rdata_signExtend_12; // @[Lsu.scala 280:56]
+  wire [31:0] _rdata_signExtend_T_99 = rdata_rdata_12[15] ? 32'hffff0000 : 32'h0; // @[Lsu.scala 265:31]
+  wire [31:0] _rdata_signExtend_T_102 = rdata_rdata_12[7] ? 32'hffffff00 : 32'h0; // @[Lsu.scala 266:31]
+  wire [31:0] _rdata_signExtend_T_103 = _rdata_sizeMask_T_2 ? _rdata_signExtend_T_99 : _rdata_signExtend_T_102; // @[Lsu.scala 264:29]
+  wire [31:0] rdata_signExtend_12 = data_io_out_bits_sext ? _rdata_signExtend_T_103 : 32'h0; // @[Lsu.scala 263:27]
+  wire  _rdata_sdata_T_36 = rsel == 5'hc; // @[Lsu.scala 271:30]
+  wire [31:0] _rdata_sdata_T_37 = rdata_rdata_12 & rdata_sizeMask; // @[Lsu.scala 271:45]
+  wire [31:0] _rdata_sdata_T_38 = _rdata_sdata_T_37 | rdata_signExtend_12; // @[Lsu.scala 271:56]
   wire [31:0] rdata_sdata_12 = _rdata_sdata_T_36 ? _rdata_sdata_T_38 : 32'h0; // @[Library.scala 8:8]
-  wire [255:0] _GEN_13 = {{224'd0}, rdata_sdata_12}; // @[Lsu.scala 281:34]
-  wire [255:0] _rdata_T_15 = _rdata_T_14 | _GEN_13; // @[Lsu.scala 281:34]
+  wire [255:0] _GEN_13 = {{224'd0}, rdata_sdata_12}; // @[Lsu.scala 272:34]
+  wire [255:0] _rdata_T_15 = _rdata_T_14 | _GEN_13; // @[Lsu.scala 272:34]
   wire [31:0] rdata_rdata_13 = {_rdata_T_2[135:128],_rdata_T_2[127:120],_rdata_T_2[119:112],_rdata_T_2[111:104]}; // @[Cat.scala 31:58]
-  wire [31:0] _rdata_signExtend_T_107 = rdata_rdata_13[15] ? 32'hffff0000 : 32'h0; // @[Lsu.scala 274:31]
-  wire [31:0] _rdata_signExtend_T_110 = rdata_rdata_13[7] ? 32'hffffff00 : 32'h0; // @[Lsu.scala 275:31]
-  wire [31:0] _rdata_signExtend_T_111 = _rdata_sizeMask_T_2 ? _rdata_signExtend_T_107 : _rdata_signExtend_T_110; // @[Lsu.scala 273:29]
-  wire [31:0] rdata_signExtend_13 = data_io_out_bits_sext ? _rdata_signExtend_T_111 : 32'h0; // @[Lsu.scala 272:27]
-  wire  _rdata_sdata_T_39 = rsel == 5'hd; // @[Lsu.scala 280:30]
-  wire [31:0] _rdata_sdata_T_40 = rdata_rdata_13 & rdata_sizeMask; // @[Lsu.scala 280:45]
-  wire [31:0] _rdata_sdata_T_41 = _rdata_sdata_T_40 | rdata_signExtend_13; // @[Lsu.scala 280:56]
+  wire [31:0] _rdata_signExtend_T_107 = rdata_rdata_13[15] ? 32'hffff0000 : 32'h0; // @[Lsu.scala 265:31]
+  wire [31:0] _rdata_signExtend_T_110 = rdata_rdata_13[7] ? 32'hffffff00 : 32'h0; // @[Lsu.scala 266:31]
+  wire [31:0] _rdata_signExtend_T_111 = _rdata_sizeMask_T_2 ? _rdata_signExtend_T_107 : _rdata_signExtend_T_110; // @[Lsu.scala 264:29]
+  wire [31:0] rdata_signExtend_13 = data_io_out_bits_sext ? _rdata_signExtend_T_111 : 32'h0; // @[Lsu.scala 263:27]
+  wire  _rdata_sdata_T_39 = rsel == 5'hd; // @[Lsu.scala 271:30]
+  wire [31:0] _rdata_sdata_T_40 = rdata_rdata_13 & rdata_sizeMask; // @[Lsu.scala 271:45]
+  wire [31:0] _rdata_sdata_T_41 = _rdata_sdata_T_40 | rdata_signExtend_13; // @[Lsu.scala 271:56]
   wire [31:0] rdata_sdata_13 = _rdata_sdata_T_39 ? _rdata_sdata_T_41 : 32'h0; // @[Library.scala 8:8]
-  wire [255:0] _GEN_14 = {{224'd0}, rdata_sdata_13}; // @[Lsu.scala 281:34]
-  wire [255:0] _rdata_T_16 = _rdata_T_15 | _GEN_14; // @[Lsu.scala 281:34]
+  wire [255:0] _GEN_14 = {{224'd0}, rdata_sdata_13}; // @[Lsu.scala 272:34]
+  wire [255:0] _rdata_T_16 = _rdata_T_15 | _GEN_14; // @[Lsu.scala 272:34]
   wire [31:0] rdata_rdata_14 = {_rdata_T_2[143:136],_rdata_T_2[135:128],_rdata_T_2[127:120],_rdata_T_2[119:112]}; // @[Cat.scala 31:58]
-  wire [31:0] _rdata_signExtend_T_115 = rdata_rdata_14[15] ? 32'hffff0000 : 32'h0; // @[Lsu.scala 274:31]
-  wire [31:0] _rdata_signExtend_T_118 = rdata_rdata_14[7] ? 32'hffffff00 : 32'h0; // @[Lsu.scala 275:31]
-  wire [31:0] _rdata_signExtend_T_119 = _rdata_sizeMask_T_2 ? _rdata_signExtend_T_115 : _rdata_signExtend_T_118; // @[Lsu.scala 273:29]
-  wire [31:0] rdata_signExtend_14 = data_io_out_bits_sext ? _rdata_signExtend_T_119 : 32'h0; // @[Lsu.scala 272:27]
-  wire  _rdata_sdata_T_42 = rsel == 5'he; // @[Lsu.scala 280:30]
-  wire [31:0] _rdata_sdata_T_43 = rdata_rdata_14 & rdata_sizeMask; // @[Lsu.scala 280:45]
-  wire [31:0] _rdata_sdata_T_44 = _rdata_sdata_T_43 | rdata_signExtend_14; // @[Lsu.scala 280:56]
+  wire [31:0] _rdata_signExtend_T_115 = rdata_rdata_14[15] ? 32'hffff0000 : 32'h0; // @[Lsu.scala 265:31]
+  wire [31:0] _rdata_signExtend_T_118 = rdata_rdata_14[7] ? 32'hffffff00 : 32'h0; // @[Lsu.scala 266:31]
+  wire [31:0] _rdata_signExtend_T_119 = _rdata_sizeMask_T_2 ? _rdata_signExtend_T_115 : _rdata_signExtend_T_118; // @[Lsu.scala 264:29]
+  wire [31:0] rdata_signExtend_14 = data_io_out_bits_sext ? _rdata_signExtend_T_119 : 32'h0; // @[Lsu.scala 263:27]
+  wire  _rdata_sdata_T_42 = rsel == 5'he; // @[Lsu.scala 271:30]
+  wire [31:0] _rdata_sdata_T_43 = rdata_rdata_14 & rdata_sizeMask; // @[Lsu.scala 271:45]
+  wire [31:0] _rdata_sdata_T_44 = _rdata_sdata_T_43 | rdata_signExtend_14; // @[Lsu.scala 271:56]
   wire [31:0] rdata_sdata_14 = _rdata_sdata_T_42 ? _rdata_sdata_T_44 : 32'h0; // @[Library.scala 8:8]
-  wire [255:0] _GEN_15 = {{224'd0}, rdata_sdata_14}; // @[Lsu.scala 281:34]
-  wire [255:0] _rdata_T_17 = _rdata_T_16 | _GEN_15; // @[Lsu.scala 281:34]
+  wire [255:0] _GEN_15 = {{224'd0}, rdata_sdata_14}; // @[Lsu.scala 272:34]
+  wire [255:0] _rdata_T_17 = _rdata_T_16 | _GEN_15; // @[Lsu.scala 272:34]
   wire [31:0] rdata_rdata_15 = {_rdata_T_2[151:144],_rdata_T_2[143:136],_rdata_T_2[135:128],_rdata_T_2[127:120]}; // @[Cat.scala 31:58]
-  wire [31:0] _rdata_signExtend_T_123 = rdata_rdata_15[15] ? 32'hffff0000 : 32'h0; // @[Lsu.scala 274:31]
-  wire [31:0] _rdata_signExtend_T_126 = rdata_rdata_15[7] ? 32'hffffff00 : 32'h0; // @[Lsu.scala 275:31]
-  wire [31:0] _rdata_signExtend_T_127 = _rdata_sizeMask_T_2 ? _rdata_signExtend_T_123 : _rdata_signExtend_T_126; // @[Lsu.scala 273:29]
-  wire [31:0] rdata_signExtend_15 = data_io_out_bits_sext ? _rdata_signExtend_T_127 : 32'h0; // @[Lsu.scala 272:27]
-  wire  _rdata_sdata_T_45 = rsel == 5'hf; // @[Lsu.scala 280:30]
-  wire [31:0] _rdata_sdata_T_46 = rdata_rdata_15 & rdata_sizeMask; // @[Lsu.scala 280:45]
-  wire [31:0] _rdata_sdata_T_47 = _rdata_sdata_T_46 | rdata_signExtend_15; // @[Lsu.scala 280:56]
+  wire [31:0] _rdata_signExtend_T_123 = rdata_rdata_15[15] ? 32'hffff0000 : 32'h0; // @[Lsu.scala 265:31]
+  wire [31:0] _rdata_signExtend_T_126 = rdata_rdata_15[7] ? 32'hffffff00 : 32'h0; // @[Lsu.scala 266:31]
+  wire [31:0] _rdata_signExtend_T_127 = _rdata_sizeMask_T_2 ? _rdata_signExtend_T_123 : _rdata_signExtend_T_126; // @[Lsu.scala 264:29]
+  wire [31:0] rdata_signExtend_15 = data_io_out_bits_sext ? _rdata_signExtend_T_127 : 32'h0; // @[Lsu.scala 263:27]
+  wire  _rdata_sdata_T_45 = rsel == 5'hf; // @[Lsu.scala 271:30]
+  wire [31:0] _rdata_sdata_T_46 = rdata_rdata_15 & rdata_sizeMask; // @[Lsu.scala 271:45]
+  wire [31:0] _rdata_sdata_T_47 = _rdata_sdata_T_46 | rdata_signExtend_15; // @[Lsu.scala 271:56]
   wire [31:0] rdata_sdata_15 = _rdata_sdata_T_45 ? _rdata_sdata_T_47 : 32'h0; // @[Library.scala 8:8]
-  wire [255:0] _GEN_16 = {{224'd0}, rdata_sdata_15}; // @[Lsu.scala 281:34]
-  wire [255:0] _rdata_T_18 = _rdata_T_17 | _GEN_16; // @[Lsu.scala 281:34]
+  wire [255:0] _GEN_16 = {{224'd0}, rdata_sdata_15}; // @[Lsu.scala 272:34]
+  wire [255:0] _rdata_T_18 = _rdata_T_17 | _GEN_16; // @[Lsu.scala 272:34]
   wire [31:0] rdata_rdata_16 = {_rdata_T_2[159:152],_rdata_T_2[151:144],_rdata_T_2[143:136],_rdata_T_2[135:128]}; // @[Cat.scala 31:58]
-  wire [31:0] _rdata_signExtend_T_131 = rdata_rdata_16[15] ? 32'hffff0000 : 32'h0; // @[Lsu.scala 274:31]
-  wire [31:0] _rdata_signExtend_T_134 = rdata_rdata_16[7] ? 32'hffffff00 : 32'h0; // @[Lsu.scala 275:31]
-  wire [31:0] _rdata_signExtend_T_135 = _rdata_sizeMask_T_2 ? _rdata_signExtend_T_131 : _rdata_signExtend_T_134; // @[Lsu.scala 273:29]
-  wire [31:0] rdata_signExtend_16 = data_io_out_bits_sext ? _rdata_signExtend_T_135 : 32'h0; // @[Lsu.scala 272:27]
-  wire  _rdata_sdata_T_48 = rsel == 5'h10; // @[Lsu.scala 280:30]
-  wire [31:0] _rdata_sdata_T_49 = rdata_rdata_16 & rdata_sizeMask; // @[Lsu.scala 280:45]
-  wire [31:0] _rdata_sdata_T_50 = _rdata_sdata_T_49 | rdata_signExtend_16; // @[Lsu.scala 280:56]
+  wire [31:0] _rdata_signExtend_T_131 = rdata_rdata_16[15] ? 32'hffff0000 : 32'h0; // @[Lsu.scala 265:31]
+  wire [31:0] _rdata_signExtend_T_134 = rdata_rdata_16[7] ? 32'hffffff00 : 32'h0; // @[Lsu.scala 266:31]
+  wire [31:0] _rdata_signExtend_T_135 = _rdata_sizeMask_T_2 ? _rdata_signExtend_T_131 : _rdata_signExtend_T_134; // @[Lsu.scala 264:29]
+  wire [31:0] rdata_signExtend_16 = data_io_out_bits_sext ? _rdata_signExtend_T_135 : 32'h0; // @[Lsu.scala 263:27]
+  wire  _rdata_sdata_T_48 = rsel == 5'h10; // @[Lsu.scala 271:30]
+  wire [31:0] _rdata_sdata_T_49 = rdata_rdata_16 & rdata_sizeMask; // @[Lsu.scala 271:45]
+  wire [31:0] _rdata_sdata_T_50 = _rdata_sdata_T_49 | rdata_signExtend_16; // @[Lsu.scala 271:56]
   wire [31:0] rdata_sdata_16 = _rdata_sdata_T_48 ? _rdata_sdata_T_50 : 32'h0; // @[Library.scala 8:8]
-  wire [255:0] _GEN_17 = {{224'd0}, rdata_sdata_16}; // @[Lsu.scala 281:34]
-  wire [255:0] _rdata_T_19 = _rdata_T_18 | _GEN_17; // @[Lsu.scala 281:34]
+  wire [255:0] _GEN_17 = {{224'd0}, rdata_sdata_16}; // @[Lsu.scala 272:34]
+  wire [255:0] _rdata_T_19 = _rdata_T_18 | _GEN_17; // @[Lsu.scala 272:34]
   wire [31:0] rdata_rdata_17 = {_rdata_T_2[167:160],_rdata_T_2[159:152],_rdata_T_2[151:144],_rdata_T_2[143:136]}; // @[Cat.scala 31:58]
-  wire [31:0] _rdata_signExtend_T_139 = rdata_rdata_17[15] ? 32'hffff0000 : 32'h0; // @[Lsu.scala 274:31]
-  wire [31:0] _rdata_signExtend_T_142 = rdata_rdata_17[7] ? 32'hffffff00 : 32'h0; // @[Lsu.scala 275:31]
-  wire [31:0] _rdata_signExtend_T_143 = _rdata_sizeMask_T_2 ? _rdata_signExtend_T_139 : _rdata_signExtend_T_142; // @[Lsu.scala 273:29]
-  wire [31:0] rdata_signExtend_17 = data_io_out_bits_sext ? _rdata_signExtend_T_143 : 32'h0; // @[Lsu.scala 272:27]
-  wire  _rdata_sdata_T_51 = rsel == 5'h11; // @[Lsu.scala 280:30]
-  wire [31:0] _rdata_sdata_T_52 = rdata_rdata_17 & rdata_sizeMask; // @[Lsu.scala 280:45]
-  wire [31:0] _rdata_sdata_T_53 = _rdata_sdata_T_52 | rdata_signExtend_17; // @[Lsu.scala 280:56]
+  wire [31:0] _rdata_signExtend_T_139 = rdata_rdata_17[15] ? 32'hffff0000 : 32'h0; // @[Lsu.scala 265:31]
+  wire [31:0] _rdata_signExtend_T_142 = rdata_rdata_17[7] ? 32'hffffff00 : 32'h0; // @[Lsu.scala 266:31]
+  wire [31:0] _rdata_signExtend_T_143 = _rdata_sizeMask_T_2 ? _rdata_signExtend_T_139 : _rdata_signExtend_T_142; // @[Lsu.scala 264:29]
+  wire [31:0] rdata_signExtend_17 = data_io_out_bits_sext ? _rdata_signExtend_T_143 : 32'h0; // @[Lsu.scala 263:27]
+  wire  _rdata_sdata_T_51 = rsel == 5'h11; // @[Lsu.scala 271:30]
+  wire [31:0] _rdata_sdata_T_52 = rdata_rdata_17 & rdata_sizeMask; // @[Lsu.scala 271:45]
+  wire [31:0] _rdata_sdata_T_53 = _rdata_sdata_T_52 | rdata_signExtend_17; // @[Lsu.scala 271:56]
   wire [31:0] rdata_sdata_17 = _rdata_sdata_T_51 ? _rdata_sdata_T_53 : 32'h0; // @[Library.scala 8:8]
-  wire [255:0] _GEN_18 = {{224'd0}, rdata_sdata_17}; // @[Lsu.scala 281:34]
-  wire [255:0] _rdata_T_20 = _rdata_T_19 | _GEN_18; // @[Lsu.scala 281:34]
+  wire [255:0] _GEN_18 = {{224'd0}, rdata_sdata_17}; // @[Lsu.scala 272:34]
+  wire [255:0] _rdata_T_20 = _rdata_T_19 | _GEN_18; // @[Lsu.scala 272:34]
   wire [31:0] rdata_rdata_18 = {_rdata_T_2[175:168],_rdata_T_2[167:160],_rdata_T_2[159:152],_rdata_T_2[151:144]}; // @[Cat.scala 31:58]
-  wire [31:0] _rdata_signExtend_T_147 = rdata_rdata_18[15] ? 32'hffff0000 : 32'h0; // @[Lsu.scala 274:31]
-  wire [31:0] _rdata_signExtend_T_150 = rdata_rdata_18[7] ? 32'hffffff00 : 32'h0; // @[Lsu.scala 275:31]
-  wire [31:0] _rdata_signExtend_T_151 = _rdata_sizeMask_T_2 ? _rdata_signExtend_T_147 : _rdata_signExtend_T_150; // @[Lsu.scala 273:29]
-  wire [31:0] rdata_signExtend_18 = data_io_out_bits_sext ? _rdata_signExtend_T_151 : 32'h0; // @[Lsu.scala 272:27]
-  wire  _rdata_sdata_T_54 = rsel == 5'h12; // @[Lsu.scala 280:30]
-  wire [31:0] _rdata_sdata_T_55 = rdata_rdata_18 & rdata_sizeMask; // @[Lsu.scala 280:45]
-  wire [31:0] _rdata_sdata_T_56 = _rdata_sdata_T_55 | rdata_signExtend_18; // @[Lsu.scala 280:56]
+  wire [31:0] _rdata_signExtend_T_147 = rdata_rdata_18[15] ? 32'hffff0000 : 32'h0; // @[Lsu.scala 265:31]
+  wire [31:0] _rdata_signExtend_T_150 = rdata_rdata_18[7] ? 32'hffffff00 : 32'h0; // @[Lsu.scala 266:31]
+  wire [31:0] _rdata_signExtend_T_151 = _rdata_sizeMask_T_2 ? _rdata_signExtend_T_147 : _rdata_signExtend_T_150; // @[Lsu.scala 264:29]
+  wire [31:0] rdata_signExtend_18 = data_io_out_bits_sext ? _rdata_signExtend_T_151 : 32'h0; // @[Lsu.scala 263:27]
+  wire  _rdata_sdata_T_54 = rsel == 5'h12; // @[Lsu.scala 271:30]
+  wire [31:0] _rdata_sdata_T_55 = rdata_rdata_18 & rdata_sizeMask; // @[Lsu.scala 271:45]
+  wire [31:0] _rdata_sdata_T_56 = _rdata_sdata_T_55 | rdata_signExtend_18; // @[Lsu.scala 271:56]
   wire [31:0] rdata_sdata_18 = _rdata_sdata_T_54 ? _rdata_sdata_T_56 : 32'h0; // @[Library.scala 8:8]
-  wire [255:0] _GEN_19 = {{224'd0}, rdata_sdata_18}; // @[Lsu.scala 281:34]
-  wire [255:0] _rdata_T_21 = _rdata_T_20 | _GEN_19; // @[Lsu.scala 281:34]
+  wire [255:0] _GEN_19 = {{224'd0}, rdata_sdata_18}; // @[Lsu.scala 272:34]
+  wire [255:0] _rdata_T_21 = _rdata_T_20 | _GEN_19; // @[Lsu.scala 272:34]
   wire [31:0] rdata_rdata_19 = {_rdata_T_2[183:176],_rdata_T_2[175:168],_rdata_T_2[167:160],_rdata_T_2[159:152]}; // @[Cat.scala 31:58]
-  wire [31:0] _rdata_signExtend_T_155 = rdata_rdata_19[15] ? 32'hffff0000 : 32'h0; // @[Lsu.scala 274:31]
-  wire [31:0] _rdata_signExtend_T_158 = rdata_rdata_19[7] ? 32'hffffff00 : 32'h0; // @[Lsu.scala 275:31]
-  wire [31:0] _rdata_signExtend_T_159 = _rdata_sizeMask_T_2 ? _rdata_signExtend_T_155 : _rdata_signExtend_T_158; // @[Lsu.scala 273:29]
-  wire [31:0] rdata_signExtend_19 = data_io_out_bits_sext ? _rdata_signExtend_T_159 : 32'h0; // @[Lsu.scala 272:27]
-  wire  _rdata_sdata_T_57 = rsel == 5'h13; // @[Lsu.scala 280:30]
-  wire [31:0] _rdata_sdata_T_58 = rdata_rdata_19 & rdata_sizeMask; // @[Lsu.scala 280:45]
-  wire [31:0] _rdata_sdata_T_59 = _rdata_sdata_T_58 | rdata_signExtend_19; // @[Lsu.scala 280:56]
+  wire [31:0] _rdata_signExtend_T_155 = rdata_rdata_19[15] ? 32'hffff0000 : 32'h0; // @[Lsu.scala 265:31]
+  wire [31:0] _rdata_signExtend_T_158 = rdata_rdata_19[7] ? 32'hffffff00 : 32'h0; // @[Lsu.scala 266:31]
+  wire [31:0] _rdata_signExtend_T_159 = _rdata_sizeMask_T_2 ? _rdata_signExtend_T_155 : _rdata_signExtend_T_158; // @[Lsu.scala 264:29]
+  wire [31:0] rdata_signExtend_19 = data_io_out_bits_sext ? _rdata_signExtend_T_159 : 32'h0; // @[Lsu.scala 263:27]
+  wire  _rdata_sdata_T_57 = rsel == 5'h13; // @[Lsu.scala 271:30]
+  wire [31:0] _rdata_sdata_T_58 = rdata_rdata_19 & rdata_sizeMask; // @[Lsu.scala 271:45]
+  wire [31:0] _rdata_sdata_T_59 = _rdata_sdata_T_58 | rdata_signExtend_19; // @[Lsu.scala 271:56]
   wire [31:0] rdata_sdata_19 = _rdata_sdata_T_57 ? _rdata_sdata_T_59 : 32'h0; // @[Library.scala 8:8]
-  wire [255:0] _GEN_20 = {{224'd0}, rdata_sdata_19}; // @[Lsu.scala 281:34]
-  wire [255:0] _rdata_T_22 = _rdata_T_21 | _GEN_20; // @[Lsu.scala 281:34]
+  wire [255:0] _GEN_20 = {{224'd0}, rdata_sdata_19}; // @[Lsu.scala 272:34]
+  wire [255:0] _rdata_T_22 = _rdata_T_21 | _GEN_20; // @[Lsu.scala 272:34]
   wire [31:0] rdata_rdata_20 = {_rdata_T_2[191:184],_rdata_T_2[183:176],_rdata_T_2[175:168],_rdata_T_2[167:160]}; // @[Cat.scala 31:58]
-  wire [31:0] _rdata_signExtend_T_163 = rdata_rdata_20[15] ? 32'hffff0000 : 32'h0; // @[Lsu.scala 274:31]
-  wire [31:0] _rdata_signExtend_T_166 = rdata_rdata_20[7] ? 32'hffffff00 : 32'h0; // @[Lsu.scala 275:31]
-  wire [31:0] _rdata_signExtend_T_167 = _rdata_sizeMask_T_2 ? _rdata_signExtend_T_163 : _rdata_signExtend_T_166; // @[Lsu.scala 273:29]
-  wire [31:0] rdata_signExtend_20 = data_io_out_bits_sext ? _rdata_signExtend_T_167 : 32'h0; // @[Lsu.scala 272:27]
-  wire  _rdata_sdata_T_60 = rsel == 5'h14; // @[Lsu.scala 280:30]
-  wire [31:0] _rdata_sdata_T_61 = rdata_rdata_20 & rdata_sizeMask; // @[Lsu.scala 280:45]
-  wire [31:0] _rdata_sdata_T_62 = _rdata_sdata_T_61 | rdata_signExtend_20; // @[Lsu.scala 280:56]
+  wire [31:0] _rdata_signExtend_T_163 = rdata_rdata_20[15] ? 32'hffff0000 : 32'h0; // @[Lsu.scala 265:31]
+  wire [31:0] _rdata_signExtend_T_166 = rdata_rdata_20[7] ? 32'hffffff00 : 32'h0; // @[Lsu.scala 266:31]
+  wire [31:0] _rdata_signExtend_T_167 = _rdata_sizeMask_T_2 ? _rdata_signExtend_T_163 : _rdata_signExtend_T_166; // @[Lsu.scala 264:29]
+  wire [31:0] rdata_signExtend_20 = data_io_out_bits_sext ? _rdata_signExtend_T_167 : 32'h0; // @[Lsu.scala 263:27]
+  wire  _rdata_sdata_T_60 = rsel == 5'h14; // @[Lsu.scala 271:30]
+  wire [31:0] _rdata_sdata_T_61 = rdata_rdata_20 & rdata_sizeMask; // @[Lsu.scala 271:45]
+  wire [31:0] _rdata_sdata_T_62 = _rdata_sdata_T_61 | rdata_signExtend_20; // @[Lsu.scala 271:56]
   wire [31:0] rdata_sdata_20 = _rdata_sdata_T_60 ? _rdata_sdata_T_62 : 32'h0; // @[Library.scala 8:8]
-  wire [255:0] _GEN_21 = {{224'd0}, rdata_sdata_20}; // @[Lsu.scala 281:34]
-  wire [255:0] _rdata_T_23 = _rdata_T_22 | _GEN_21; // @[Lsu.scala 281:34]
+  wire [255:0] _GEN_21 = {{224'd0}, rdata_sdata_20}; // @[Lsu.scala 272:34]
+  wire [255:0] _rdata_T_23 = _rdata_T_22 | _GEN_21; // @[Lsu.scala 272:34]
   wire [31:0] rdata_rdata_21 = {_rdata_T_2[199:192],_rdata_T_2[191:184],_rdata_T_2[183:176],_rdata_T_2[175:168]}; // @[Cat.scala 31:58]
-  wire [31:0] _rdata_signExtend_T_171 = rdata_rdata_21[15] ? 32'hffff0000 : 32'h0; // @[Lsu.scala 274:31]
-  wire [31:0] _rdata_signExtend_T_174 = rdata_rdata_21[7] ? 32'hffffff00 : 32'h0; // @[Lsu.scala 275:31]
-  wire [31:0] _rdata_signExtend_T_175 = _rdata_sizeMask_T_2 ? _rdata_signExtend_T_171 : _rdata_signExtend_T_174; // @[Lsu.scala 273:29]
-  wire [31:0] rdata_signExtend_21 = data_io_out_bits_sext ? _rdata_signExtend_T_175 : 32'h0; // @[Lsu.scala 272:27]
-  wire  _rdata_sdata_T_63 = rsel == 5'h15; // @[Lsu.scala 280:30]
-  wire [31:0] _rdata_sdata_T_64 = rdata_rdata_21 & rdata_sizeMask; // @[Lsu.scala 280:45]
-  wire [31:0] _rdata_sdata_T_65 = _rdata_sdata_T_64 | rdata_signExtend_21; // @[Lsu.scala 280:56]
+  wire [31:0] _rdata_signExtend_T_171 = rdata_rdata_21[15] ? 32'hffff0000 : 32'h0; // @[Lsu.scala 265:31]
+  wire [31:0] _rdata_signExtend_T_174 = rdata_rdata_21[7] ? 32'hffffff00 : 32'h0; // @[Lsu.scala 266:31]
+  wire [31:0] _rdata_signExtend_T_175 = _rdata_sizeMask_T_2 ? _rdata_signExtend_T_171 : _rdata_signExtend_T_174; // @[Lsu.scala 264:29]
+  wire [31:0] rdata_signExtend_21 = data_io_out_bits_sext ? _rdata_signExtend_T_175 : 32'h0; // @[Lsu.scala 263:27]
+  wire  _rdata_sdata_T_63 = rsel == 5'h15; // @[Lsu.scala 271:30]
+  wire [31:0] _rdata_sdata_T_64 = rdata_rdata_21 & rdata_sizeMask; // @[Lsu.scala 271:45]
+  wire [31:0] _rdata_sdata_T_65 = _rdata_sdata_T_64 | rdata_signExtend_21; // @[Lsu.scala 271:56]
   wire [31:0] rdata_sdata_21 = _rdata_sdata_T_63 ? _rdata_sdata_T_65 : 32'h0; // @[Library.scala 8:8]
-  wire [255:0] _GEN_22 = {{224'd0}, rdata_sdata_21}; // @[Lsu.scala 281:34]
-  wire [255:0] _rdata_T_24 = _rdata_T_23 | _GEN_22; // @[Lsu.scala 281:34]
+  wire [255:0] _GEN_22 = {{224'd0}, rdata_sdata_21}; // @[Lsu.scala 272:34]
+  wire [255:0] _rdata_T_24 = _rdata_T_23 | _GEN_22; // @[Lsu.scala 272:34]
   wire [31:0] rdata_rdata_22 = {_rdata_T_2[207:200],_rdata_T_2[199:192],_rdata_T_2[191:184],_rdata_T_2[183:176]}; // @[Cat.scala 31:58]
-  wire [31:0] _rdata_signExtend_T_179 = rdata_rdata_22[15] ? 32'hffff0000 : 32'h0; // @[Lsu.scala 274:31]
-  wire [31:0] _rdata_signExtend_T_182 = rdata_rdata_22[7] ? 32'hffffff00 : 32'h0; // @[Lsu.scala 275:31]
-  wire [31:0] _rdata_signExtend_T_183 = _rdata_sizeMask_T_2 ? _rdata_signExtend_T_179 : _rdata_signExtend_T_182; // @[Lsu.scala 273:29]
-  wire [31:0] rdata_signExtend_22 = data_io_out_bits_sext ? _rdata_signExtend_T_183 : 32'h0; // @[Lsu.scala 272:27]
-  wire  _rdata_sdata_T_66 = rsel == 5'h16; // @[Lsu.scala 280:30]
-  wire [31:0] _rdata_sdata_T_67 = rdata_rdata_22 & rdata_sizeMask; // @[Lsu.scala 280:45]
-  wire [31:0] _rdata_sdata_T_68 = _rdata_sdata_T_67 | rdata_signExtend_22; // @[Lsu.scala 280:56]
+  wire [31:0] _rdata_signExtend_T_179 = rdata_rdata_22[15] ? 32'hffff0000 : 32'h0; // @[Lsu.scala 265:31]
+  wire [31:0] _rdata_signExtend_T_182 = rdata_rdata_22[7] ? 32'hffffff00 : 32'h0; // @[Lsu.scala 266:31]
+  wire [31:0] _rdata_signExtend_T_183 = _rdata_sizeMask_T_2 ? _rdata_signExtend_T_179 : _rdata_signExtend_T_182; // @[Lsu.scala 264:29]
+  wire [31:0] rdata_signExtend_22 = data_io_out_bits_sext ? _rdata_signExtend_T_183 : 32'h0; // @[Lsu.scala 263:27]
+  wire  _rdata_sdata_T_66 = rsel == 5'h16; // @[Lsu.scala 271:30]
+  wire [31:0] _rdata_sdata_T_67 = rdata_rdata_22 & rdata_sizeMask; // @[Lsu.scala 271:45]
+  wire [31:0] _rdata_sdata_T_68 = _rdata_sdata_T_67 | rdata_signExtend_22; // @[Lsu.scala 271:56]
   wire [31:0] rdata_sdata_22 = _rdata_sdata_T_66 ? _rdata_sdata_T_68 : 32'h0; // @[Library.scala 8:8]
-  wire [255:0] _GEN_23 = {{224'd0}, rdata_sdata_22}; // @[Lsu.scala 281:34]
-  wire [255:0] _rdata_T_25 = _rdata_T_24 | _GEN_23; // @[Lsu.scala 281:34]
+  wire [255:0] _GEN_23 = {{224'd0}, rdata_sdata_22}; // @[Lsu.scala 272:34]
+  wire [255:0] _rdata_T_25 = _rdata_T_24 | _GEN_23; // @[Lsu.scala 272:34]
   wire [31:0] rdata_rdata_23 = {_rdata_T_2[215:208],_rdata_T_2[207:200],_rdata_T_2[199:192],_rdata_T_2[191:184]}; // @[Cat.scala 31:58]
-  wire [31:0] _rdata_signExtend_T_187 = rdata_rdata_23[15] ? 32'hffff0000 : 32'h0; // @[Lsu.scala 274:31]
-  wire [31:0] _rdata_signExtend_T_190 = rdata_rdata_23[7] ? 32'hffffff00 : 32'h0; // @[Lsu.scala 275:31]
-  wire [31:0] _rdata_signExtend_T_191 = _rdata_sizeMask_T_2 ? _rdata_signExtend_T_187 : _rdata_signExtend_T_190; // @[Lsu.scala 273:29]
-  wire [31:0] rdata_signExtend_23 = data_io_out_bits_sext ? _rdata_signExtend_T_191 : 32'h0; // @[Lsu.scala 272:27]
-  wire  _rdata_sdata_T_69 = rsel == 5'h17; // @[Lsu.scala 280:30]
-  wire [31:0] _rdata_sdata_T_70 = rdata_rdata_23 & rdata_sizeMask; // @[Lsu.scala 280:45]
-  wire [31:0] _rdata_sdata_T_71 = _rdata_sdata_T_70 | rdata_signExtend_23; // @[Lsu.scala 280:56]
+  wire [31:0] _rdata_signExtend_T_187 = rdata_rdata_23[15] ? 32'hffff0000 : 32'h0; // @[Lsu.scala 265:31]
+  wire [31:0] _rdata_signExtend_T_190 = rdata_rdata_23[7] ? 32'hffffff00 : 32'h0; // @[Lsu.scala 266:31]
+  wire [31:0] _rdata_signExtend_T_191 = _rdata_sizeMask_T_2 ? _rdata_signExtend_T_187 : _rdata_signExtend_T_190; // @[Lsu.scala 264:29]
+  wire [31:0] rdata_signExtend_23 = data_io_out_bits_sext ? _rdata_signExtend_T_191 : 32'h0; // @[Lsu.scala 263:27]
+  wire  _rdata_sdata_T_69 = rsel == 5'h17; // @[Lsu.scala 271:30]
+  wire [31:0] _rdata_sdata_T_70 = rdata_rdata_23 & rdata_sizeMask; // @[Lsu.scala 271:45]
+  wire [31:0] _rdata_sdata_T_71 = _rdata_sdata_T_70 | rdata_signExtend_23; // @[Lsu.scala 271:56]
   wire [31:0] rdata_sdata_23 = _rdata_sdata_T_69 ? _rdata_sdata_T_71 : 32'h0; // @[Library.scala 8:8]
-  wire [255:0] _GEN_24 = {{224'd0}, rdata_sdata_23}; // @[Lsu.scala 281:34]
-  wire [255:0] _rdata_T_26 = _rdata_T_25 | _GEN_24; // @[Lsu.scala 281:34]
+  wire [255:0] _GEN_24 = {{224'd0}, rdata_sdata_23}; // @[Lsu.scala 272:34]
+  wire [255:0] _rdata_T_26 = _rdata_T_25 | _GEN_24; // @[Lsu.scala 272:34]
   wire [31:0] rdata_rdata_24 = {_rdata_T_2[223:216],_rdata_T_2[215:208],_rdata_T_2[207:200],_rdata_T_2[199:192]}; // @[Cat.scala 31:58]
-  wire [31:0] _rdata_signExtend_T_195 = rdata_rdata_24[15] ? 32'hffff0000 : 32'h0; // @[Lsu.scala 274:31]
-  wire [31:0] _rdata_signExtend_T_198 = rdata_rdata_24[7] ? 32'hffffff00 : 32'h0; // @[Lsu.scala 275:31]
-  wire [31:0] _rdata_signExtend_T_199 = _rdata_sizeMask_T_2 ? _rdata_signExtend_T_195 : _rdata_signExtend_T_198; // @[Lsu.scala 273:29]
-  wire [31:0] rdata_signExtend_24 = data_io_out_bits_sext ? _rdata_signExtend_T_199 : 32'h0; // @[Lsu.scala 272:27]
-  wire  _rdata_sdata_T_72 = rsel == 5'h18; // @[Lsu.scala 280:30]
-  wire [31:0] _rdata_sdata_T_73 = rdata_rdata_24 & rdata_sizeMask; // @[Lsu.scala 280:45]
-  wire [31:0] _rdata_sdata_T_74 = _rdata_sdata_T_73 | rdata_signExtend_24; // @[Lsu.scala 280:56]
+  wire [31:0] _rdata_signExtend_T_195 = rdata_rdata_24[15] ? 32'hffff0000 : 32'h0; // @[Lsu.scala 265:31]
+  wire [31:0] _rdata_signExtend_T_198 = rdata_rdata_24[7] ? 32'hffffff00 : 32'h0; // @[Lsu.scala 266:31]
+  wire [31:0] _rdata_signExtend_T_199 = _rdata_sizeMask_T_2 ? _rdata_signExtend_T_195 : _rdata_signExtend_T_198; // @[Lsu.scala 264:29]
+  wire [31:0] rdata_signExtend_24 = data_io_out_bits_sext ? _rdata_signExtend_T_199 : 32'h0; // @[Lsu.scala 263:27]
+  wire  _rdata_sdata_T_72 = rsel == 5'h18; // @[Lsu.scala 271:30]
+  wire [31:0] _rdata_sdata_T_73 = rdata_rdata_24 & rdata_sizeMask; // @[Lsu.scala 271:45]
+  wire [31:0] _rdata_sdata_T_74 = _rdata_sdata_T_73 | rdata_signExtend_24; // @[Lsu.scala 271:56]
   wire [31:0] rdata_sdata_24 = _rdata_sdata_T_72 ? _rdata_sdata_T_74 : 32'h0; // @[Library.scala 8:8]
-  wire [255:0] _GEN_25 = {{224'd0}, rdata_sdata_24}; // @[Lsu.scala 281:34]
-  wire [255:0] _rdata_T_27 = _rdata_T_26 | _GEN_25; // @[Lsu.scala 281:34]
+  wire [255:0] _GEN_25 = {{224'd0}, rdata_sdata_24}; // @[Lsu.scala 272:34]
+  wire [255:0] _rdata_T_27 = _rdata_T_26 | _GEN_25; // @[Lsu.scala 272:34]
   wire [31:0] rdata_rdata_25 = {_rdata_T_2[231:224],_rdata_T_2[223:216],_rdata_T_2[215:208],_rdata_T_2[207:200]}; // @[Cat.scala 31:58]
-  wire [31:0] _rdata_signExtend_T_203 = rdata_rdata_25[15] ? 32'hffff0000 : 32'h0; // @[Lsu.scala 274:31]
-  wire [31:0] _rdata_signExtend_T_206 = rdata_rdata_25[7] ? 32'hffffff00 : 32'h0; // @[Lsu.scala 275:31]
-  wire [31:0] _rdata_signExtend_T_207 = _rdata_sizeMask_T_2 ? _rdata_signExtend_T_203 : _rdata_signExtend_T_206; // @[Lsu.scala 273:29]
-  wire [31:0] rdata_signExtend_25 = data_io_out_bits_sext ? _rdata_signExtend_T_207 : 32'h0; // @[Lsu.scala 272:27]
-  wire  _rdata_sdata_T_75 = rsel == 5'h19; // @[Lsu.scala 280:30]
-  wire [31:0] _rdata_sdata_T_76 = rdata_rdata_25 & rdata_sizeMask; // @[Lsu.scala 280:45]
-  wire [31:0] _rdata_sdata_T_77 = _rdata_sdata_T_76 | rdata_signExtend_25; // @[Lsu.scala 280:56]
+  wire [31:0] _rdata_signExtend_T_203 = rdata_rdata_25[15] ? 32'hffff0000 : 32'h0; // @[Lsu.scala 265:31]
+  wire [31:0] _rdata_signExtend_T_206 = rdata_rdata_25[7] ? 32'hffffff00 : 32'h0; // @[Lsu.scala 266:31]
+  wire [31:0] _rdata_signExtend_T_207 = _rdata_sizeMask_T_2 ? _rdata_signExtend_T_203 : _rdata_signExtend_T_206; // @[Lsu.scala 264:29]
+  wire [31:0] rdata_signExtend_25 = data_io_out_bits_sext ? _rdata_signExtend_T_207 : 32'h0; // @[Lsu.scala 263:27]
+  wire  _rdata_sdata_T_75 = rsel == 5'h19; // @[Lsu.scala 271:30]
+  wire [31:0] _rdata_sdata_T_76 = rdata_rdata_25 & rdata_sizeMask; // @[Lsu.scala 271:45]
+  wire [31:0] _rdata_sdata_T_77 = _rdata_sdata_T_76 | rdata_signExtend_25; // @[Lsu.scala 271:56]
   wire [31:0] rdata_sdata_25 = _rdata_sdata_T_75 ? _rdata_sdata_T_77 : 32'h0; // @[Library.scala 8:8]
-  wire [255:0] _GEN_26 = {{224'd0}, rdata_sdata_25}; // @[Lsu.scala 281:34]
-  wire [255:0] _rdata_T_28 = _rdata_T_27 | _GEN_26; // @[Lsu.scala 281:34]
+  wire [255:0] _GEN_26 = {{224'd0}, rdata_sdata_25}; // @[Lsu.scala 272:34]
+  wire [255:0] _rdata_T_28 = _rdata_T_27 | _GEN_26; // @[Lsu.scala 272:34]
   wire [31:0] rdata_rdata_26 = {_rdata_T_2[239:232],_rdata_T_2[231:224],_rdata_T_2[223:216],_rdata_T_2[215:208]}; // @[Cat.scala 31:58]
-  wire [31:0] _rdata_signExtend_T_211 = rdata_rdata_26[15] ? 32'hffff0000 : 32'h0; // @[Lsu.scala 274:31]
-  wire [31:0] _rdata_signExtend_T_214 = rdata_rdata_26[7] ? 32'hffffff00 : 32'h0; // @[Lsu.scala 275:31]
-  wire [31:0] _rdata_signExtend_T_215 = _rdata_sizeMask_T_2 ? _rdata_signExtend_T_211 : _rdata_signExtend_T_214; // @[Lsu.scala 273:29]
-  wire [31:0] rdata_signExtend_26 = data_io_out_bits_sext ? _rdata_signExtend_T_215 : 32'h0; // @[Lsu.scala 272:27]
-  wire  _rdata_sdata_T_78 = rsel == 5'h1a; // @[Lsu.scala 280:30]
-  wire [31:0] _rdata_sdata_T_79 = rdata_rdata_26 & rdata_sizeMask; // @[Lsu.scala 280:45]
-  wire [31:0] _rdata_sdata_T_80 = _rdata_sdata_T_79 | rdata_signExtend_26; // @[Lsu.scala 280:56]
+  wire [31:0] _rdata_signExtend_T_211 = rdata_rdata_26[15] ? 32'hffff0000 : 32'h0; // @[Lsu.scala 265:31]
+  wire [31:0] _rdata_signExtend_T_214 = rdata_rdata_26[7] ? 32'hffffff00 : 32'h0; // @[Lsu.scala 266:31]
+  wire [31:0] _rdata_signExtend_T_215 = _rdata_sizeMask_T_2 ? _rdata_signExtend_T_211 : _rdata_signExtend_T_214; // @[Lsu.scala 264:29]
+  wire [31:0] rdata_signExtend_26 = data_io_out_bits_sext ? _rdata_signExtend_T_215 : 32'h0; // @[Lsu.scala 263:27]
+  wire  _rdata_sdata_T_78 = rsel == 5'h1a; // @[Lsu.scala 271:30]
+  wire [31:0] _rdata_sdata_T_79 = rdata_rdata_26 & rdata_sizeMask; // @[Lsu.scala 271:45]
+  wire [31:0] _rdata_sdata_T_80 = _rdata_sdata_T_79 | rdata_signExtend_26; // @[Lsu.scala 271:56]
   wire [31:0] rdata_sdata_26 = _rdata_sdata_T_78 ? _rdata_sdata_T_80 : 32'h0; // @[Library.scala 8:8]
-  wire [255:0] _GEN_27 = {{224'd0}, rdata_sdata_26}; // @[Lsu.scala 281:34]
-  wire [255:0] _rdata_T_29 = _rdata_T_28 | _GEN_27; // @[Lsu.scala 281:34]
+  wire [255:0] _GEN_27 = {{224'd0}, rdata_sdata_26}; // @[Lsu.scala 272:34]
+  wire [255:0] _rdata_T_29 = _rdata_T_28 | _GEN_27; // @[Lsu.scala 272:34]
   wire [31:0] rdata_rdata_27 = {_rdata_T_2[247:240],_rdata_T_2[239:232],_rdata_T_2[231:224],_rdata_T_2[223:216]}; // @[Cat.scala 31:58]
-  wire [31:0] _rdata_signExtend_T_219 = rdata_rdata_27[15] ? 32'hffff0000 : 32'h0; // @[Lsu.scala 274:31]
-  wire [31:0] _rdata_signExtend_T_222 = rdata_rdata_27[7] ? 32'hffffff00 : 32'h0; // @[Lsu.scala 275:31]
-  wire [31:0] _rdata_signExtend_T_223 = _rdata_sizeMask_T_2 ? _rdata_signExtend_T_219 : _rdata_signExtend_T_222; // @[Lsu.scala 273:29]
-  wire [31:0] rdata_signExtend_27 = data_io_out_bits_sext ? _rdata_signExtend_T_223 : 32'h0; // @[Lsu.scala 272:27]
-  wire  _rdata_sdata_T_81 = rsel == 5'h1b; // @[Lsu.scala 280:30]
-  wire [31:0] _rdata_sdata_T_82 = rdata_rdata_27 & rdata_sizeMask; // @[Lsu.scala 280:45]
-  wire [31:0] _rdata_sdata_T_83 = _rdata_sdata_T_82 | rdata_signExtend_27; // @[Lsu.scala 280:56]
+  wire [31:0] _rdata_signExtend_T_219 = rdata_rdata_27[15] ? 32'hffff0000 : 32'h0; // @[Lsu.scala 265:31]
+  wire [31:0] _rdata_signExtend_T_222 = rdata_rdata_27[7] ? 32'hffffff00 : 32'h0; // @[Lsu.scala 266:31]
+  wire [31:0] _rdata_signExtend_T_223 = _rdata_sizeMask_T_2 ? _rdata_signExtend_T_219 : _rdata_signExtend_T_222; // @[Lsu.scala 264:29]
+  wire [31:0] rdata_signExtend_27 = data_io_out_bits_sext ? _rdata_signExtend_T_223 : 32'h0; // @[Lsu.scala 263:27]
+  wire  _rdata_sdata_T_81 = rsel == 5'h1b; // @[Lsu.scala 271:30]
+  wire [31:0] _rdata_sdata_T_82 = rdata_rdata_27 & rdata_sizeMask; // @[Lsu.scala 271:45]
+  wire [31:0] _rdata_sdata_T_83 = _rdata_sdata_T_82 | rdata_signExtend_27; // @[Lsu.scala 271:56]
   wire [31:0] rdata_sdata_27 = _rdata_sdata_T_81 ? _rdata_sdata_T_83 : 32'h0; // @[Library.scala 8:8]
-  wire [255:0] _GEN_28 = {{224'd0}, rdata_sdata_27}; // @[Lsu.scala 281:34]
-  wire [255:0] _rdata_T_30 = _rdata_T_29 | _GEN_28; // @[Lsu.scala 281:34]
+  wire [255:0] _GEN_28 = {{224'd0}, rdata_sdata_27}; // @[Lsu.scala 272:34]
+  wire [255:0] _rdata_T_30 = _rdata_T_29 | _GEN_28; // @[Lsu.scala 272:34]
   wire [31:0] rdata_rdata_28 = {_rdata_T_2[255:248],_rdata_T_2[247:240],_rdata_T_2[239:232],_rdata_T_2[231:224]}; // @[Cat.scala 31:58]
-  wire [31:0] _rdata_signExtend_T_227 = rdata_rdata_28[15] ? 32'hffff0000 : 32'h0; // @[Lsu.scala 274:31]
-  wire [31:0] _rdata_signExtend_T_230 = rdata_rdata_28[7] ? 32'hffffff00 : 32'h0; // @[Lsu.scala 275:31]
-  wire [31:0] _rdata_signExtend_T_231 = _rdata_sizeMask_T_2 ? _rdata_signExtend_T_227 : _rdata_signExtend_T_230; // @[Lsu.scala 273:29]
-  wire [31:0] rdata_signExtend_28 = data_io_out_bits_sext ? _rdata_signExtend_T_231 : 32'h0; // @[Lsu.scala 272:27]
-  wire  _rdata_sdata_T_84 = rsel == 5'h1c; // @[Lsu.scala 280:30]
-  wire [31:0] _rdata_sdata_T_85 = rdata_rdata_28 & rdata_sizeMask; // @[Lsu.scala 280:45]
-  wire [31:0] _rdata_sdata_T_86 = _rdata_sdata_T_85 | rdata_signExtend_28; // @[Lsu.scala 280:56]
+  wire [31:0] _rdata_signExtend_T_227 = rdata_rdata_28[15] ? 32'hffff0000 : 32'h0; // @[Lsu.scala 265:31]
+  wire [31:0] _rdata_signExtend_T_230 = rdata_rdata_28[7] ? 32'hffffff00 : 32'h0; // @[Lsu.scala 266:31]
+  wire [31:0] _rdata_signExtend_T_231 = _rdata_sizeMask_T_2 ? _rdata_signExtend_T_227 : _rdata_signExtend_T_230; // @[Lsu.scala 264:29]
+  wire [31:0] rdata_signExtend_28 = data_io_out_bits_sext ? _rdata_signExtend_T_231 : 32'h0; // @[Lsu.scala 263:27]
+  wire  _rdata_sdata_T_84 = rsel == 5'h1c; // @[Lsu.scala 271:30]
+  wire [31:0] _rdata_sdata_T_85 = rdata_rdata_28 & rdata_sizeMask; // @[Lsu.scala 271:45]
+  wire [31:0] _rdata_sdata_T_86 = _rdata_sdata_T_85 | rdata_signExtend_28; // @[Lsu.scala 271:56]
   wire [31:0] rdata_sdata_28 = _rdata_sdata_T_84 ? _rdata_sdata_T_86 : 32'h0; // @[Library.scala 8:8]
-  wire [255:0] _GEN_29 = {{224'd0}, rdata_sdata_28}; // @[Lsu.scala 281:34]
-  wire [255:0] _rdata_T_31 = _rdata_T_30 | _GEN_29; // @[Lsu.scala 281:34]
+  wire [255:0] _GEN_29 = {{224'd0}, rdata_sdata_28}; // @[Lsu.scala 272:34]
+  wire [255:0] _rdata_T_31 = _rdata_T_30 | _GEN_29; // @[Lsu.scala 272:34]
   wire [31:0] rdata_rdata_29 = {_rdata_T_2[7:0],_rdata_T_2[255:248],_rdata_T_2[247:240],_rdata_T_2[239:232]}; // @[Cat.scala 31:58]
-  wire [31:0] _rdata_signExtend_T_235 = rdata_rdata_29[15] ? 32'hffff0000 : 32'h0; // @[Lsu.scala 274:31]
-  wire [31:0] _rdata_signExtend_T_238 = rdata_rdata_29[7] ? 32'hffffff00 : 32'h0; // @[Lsu.scala 275:31]
-  wire [31:0] _rdata_signExtend_T_239 = _rdata_sizeMask_T_2 ? _rdata_signExtend_T_235 : _rdata_signExtend_T_238; // @[Lsu.scala 273:29]
-  wire [31:0] rdata_signExtend_29 = data_io_out_bits_sext ? _rdata_signExtend_T_239 : 32'h0; // @[Lsu.scala 272:27]
-  wire  _rdata_sdata_T_87 = rsel == 5'h1d; // @[Lsu.scala 280:30]
-  wire [31:0] _rdata_sdata_T_88 = rdata_rdata_29 & rdata_sizeMask; // @[Lsu.scala 280:45]
-  wire [31:0] _rdata_sdata_T_89 = _rdata_sdata_T_88 | rdata_signExtend_29; // @[Lsu.scala 280:56]
+  wire [31:0] _rdata_signExtend_T_235 = rdata_rdata_29[15] ? 32'hffff0000 : 32'h0; // @[Lsu.scala 265:31]
+  wire [31:0] _rdata_signExtend_T_238 = rdata_rdata_29[7] ? 32'hffffff00 : 32'h0; // @[Lsu.scala 266:31]
+  wire [31:0] _rdata_signExtend_T_239 = _rdata_sizeMask_T_2 ? _rdata_signExtend_T_235 : _rdata_signExtend_T_238; // @[Lsu.scala 264:29]
+  wire [31:0] rdata_signExtend_29 = data_io_out_bits_sext ? _rdata_signExtend_T_239 : 32'h0; // @[Lsu.scala 263:27]
+  wire  _rdata_sdata_T_87 = rsel == 5'h1d; // @[Lsu.scala 271:30]
+  wire [31:0] _rdata_sdata_T_88 = rdata_rdata_29 & rdata_sizeMask; // @[Lsu.scala 271:45]
+  wire [31:0] _rdata_sdata_T_89 = _rdata_sdata_T_88 | rdata_signExtend_29; // @[Lsu.scala 271:56]
   wire [31:0] rdata_sdata_29 = _rdata_sdata_T_87 ? _rdata_sdata_T_89 : 32'h0; // @[Library.scala 8:8]
-  wire [255:0] _GEN_30 = {{224'd0}, rdata_sdata_29}; // @[Lsu.scala 281:34]
-  wire [255:0] _rdata_T_32 = _rdata_T_31 | _GEN_30; // @[Lsu.scala 281:34]
+  wire [255:0] _GEN_30 = {{224'd0}, rdata_sdata_29}; // @[Lsu.scala 272:34]
+  wire [255:0] _rdata_T_32 = _rdata_T_31 | _GEN_30; // @[Lsu.scala 272:34]
   wire [31:0] rdata_rdata_30 = {_rdata_T_2[15:8],_rdata_T_2[7:0],_rdata_T_2[255:248],_rdata_T_2[247:240]}; // @[Cat.scala 31:58]
-  wire [31:0] _rdata_signExtend_T_243 = rdata_rdata_30[15] ? 32'hffff0000 : 32'h0; // @[Lsu.scala 274:31]
-  wire [31:0] _rdata_signExtend_T_246 = rdata_rdata_30[7] ? 32'hffffff00 : 32'h0; // @[Lsu.scala 275:31]
-  wire [31:0] _rdata_signExtend_T_247 = _rdata_sizeMask_T_2 ? _rdata_signExtend_T_243 : _rdata_signExtend_T_246; // @[Lsu.scala 273:29]
-  wire [31:0] rdata_signExtend_30 = data_io_out_bits_sext ? _rdata_signExtend_T_247 : 32'h0; // @[Lsu.scala 272:27]
-  wire  _rdata_sdata_T_90 = rsel == 5'h1e; // @[Lsu.scala 280:30]
-  wire [31:0] _rdata_sdata_T_91 = rdata_rdata_30 & rdata_sizeMask; // @[Lsu.scala 280:45]
-  wire [31:0] _rdata_sdata_T_92 = _rdata_sdata_T_91 | rdata_signExtend_30; // @[Lsu.scala 280:56]
+  wire [31:0] _rdata_signExtend_T_243 = rdata_rdata_30[15] ? 32'hffff0000 : 32'h0; // @[Lsu.scala 265:31]
+  wire [31:0] _rdata_signExtend_T_246 = rdata_rdata_30[7] ? 32'hffffff00 : 32'h0; // @[Lsu.scala 266:31]
+  wire [31:0] _rdata_signExtend_T_247 = _rdata_sizeMask_T_2 ? _rdata_signExtend_T_243 : _rdata_signExtend_T_246; // @[Lsu.scala 264:29]
+  wire [31:0] rdata_signExtend_30 = data_io_out_bits_sext ? _rdata_signExtend_T_247 : 32'h0; // @[Lsu.scala 263:27]
+  wire  _rdata_sdata_T_90 = rsel == 5'h1e; // @[Lsu.scala 271:30]
+  wire [31:0] _rdata_sdata_T_91 = rdata_rdata_30 & rdata_sizeMask; // @[Lsu.scala 271:45]
+  wire [31:0] _rdata_sdata_T_92 = _rdata_sdata_T_91 | rdata_signExtend_30; // @[Lsu.scala 271:56]
   wire [31:0] rdata_sdata_30 = _rdata_sdata_T_90 ? _rdata_sdata_T_92 : 32'h0; // @[Library.scala 8:8]
-  wire [255:0] _GEN_31 = {{224'd0}, rdata_sdata_30}; // @[Lsu.scala 281:34]
-  wire [255:0] _rdata_T_33 = _rdata_T_32 | _GEN_31; // @[Lsu.scala 281:34]
+  wire [255:0] _GEN_31 = {{224'd0}, rdata_sdata_30}; // @[Lsu.scala 272:34]
+  wire [255:0] _rdata_T_33 = _rdata_T_32 | _GEN_31; // @[Lsu.scala 272:34]
   wire [31:0] rdata_rdata_31 = {_rdata_T_2[23:16],_rdata_T_2[15:8],_rdata_T_2[7:0],_rdata_T_2[255:248]}; // @[Cat.scala 31:58]
-  wire [31:0] _rdata_signExtend_T_251 = rdata_rdata_31[15] ? 32'hffff0000 : 32'h0; // @[Lsu.scala 274:31]
-  wire [31:0] _rdata_signExtend_T_254 = rdata_rdata_31[7] ? 32'hffffff00 : 32'h0; // @[Lsu.scala 275:31]
-  wire [31:0] _rdata_signExtend_T_255 = _rdata_sizeMask_T_2 ? _rdata_signExtend_T_251 : _rdata_signExtend_T_254; // @[Lsu.scala 273:29]
-  wire [31:0] rdata_signExtend_31 = data_io_out_bits_sext ? _rdata_signExtend_T_255 : 32'h0; // @[Lsu.scala 272:27]
-  wire  _rdata_sdata_T_93 = rsel == 5'h1f; // @[Lsu.scala 280:30]
-  wire [31:0] _rdata_sdata_T_94 = rdata_rdata_31 & rdata_sizeMask; // @[Lsu.scala 280:45]
-  wire [31:0] _rdata_sdata_T_95 = _rdata_sdata_T_94 | rdata_signExtend_31; // @[Lsu.scala 280:56]
+  wire [31:0] _rdata_signExtend_T_251 = rdata_rdata_31[15] ? 32'hffff0000 : 32'h0; // @[Lsu.scala 265:31]
+  wire [31:0] _rdata_signExtend_T_254 = rdata_rdata_31[7] ? 32'hffffff00 : 32'h0; // @[Lsu.scala 266:31]
+  wire [31:0] _rdata_signExtend_T_255 = _rdata_sizeMask_T_2 ? _rdata_signExtend_T_251 : _rdata_signExtend_T_254; // @[Lsu.scala 264:29]
+  wire [31:0] rdata_signExtend_31 = data_io_out_bits_sext ? _rdata_signExtend_T_255 : 32'h0; // @[Lsu.scala 263:27]
+  wire  _rdata_sdata_T_93 = rsel == 5'h1f; // @[Lsu.scala 271:30]
+  wire [31:0] _rdata_sdata_T_94 = rdata_rdata_31 & rdata_sizeMask; // @[Lsu.scala 271:45]
+  wire [31:0] _rdata_sdata_T_95 = _rdata_sdata_T_94 | rdata_signExtend_31; // @[Lsu.scala 271:56]
   wire [31:0] rdata_sdata_31 = _rdata_sdata_T_93 ? _rdata_sdata_T_95 : 32'h0; // @[Library.scala 8:8]
-  wire [255:0] _GEN_32 = {{224'd0}, rdata_sdata_31}; // @[Lsu.scala 281:34]
-  wire [255:0] rdata = _rdata_T_33 | _GEN_32; // @[Lsu.scala 281:34]
+  wire [255:0] _GEN_32 = {{224'd0}, rdata_sdata_31}; // @[Lsu.scala 272:34]
+  wire [255:0] rdata = _rdata_T_33 | _GEN_32; // @[Lsu.scala 272:34]
   wire [2:0] _T_44 = {ctrl_io_out_bits_sldst,ctrl_io_out_bits_vldst,ctrl_io_out_bits_suncd}; // @[Cat.scala 31:58]
   wire [1:0] _T_48 = _T_44[1] + _T_44[2]; // @[Bitwise.scala 48:55]
   wire [1:0] _GEN_33 = {{1'd0}, _T_44[0]}; // @[Bitwise.scala 48:55]
@@ -21629,7 +20020,6 @@
     .io_in_bits_0_bits_size(ctrl_io_in_bits_0_bits_size),
     .io_in_bits_0_bits_write(ctrl_io_in_bits_0_bits_write),
     .io_in_bits_0_bits_sext(ctrl_io_in_bits_0_bits_sext),
-    .io_in_bits_0_bits_fload(ctrl_io_in_bits_0_bits_fload),
     .io_in_bits_0_bits_iload(ctrl_io_in_bits_0_bits_iload),
     .io_in_bits_0_bits_fencei(ctrl_io_in_bits_0_bits_fencei),
     .io_in_bits_0_bits_flushat(ctrl_io_in_bits_0_bits_flushat),
@@ -21645,7 +20035,6 @@
     .io_in_bits_1_bits_size(ctrl_io_in_bits_1_bits_size),
     .io_in_bits_1_bits_write(ctrl_io_in_bits_1_bits_write),
     .io_in_bits_1_bits_sext(ctrl_io_in_bits_1_bits_sext),
-    .io_in_bits_1_bits_fload(ctrl_io_in_bits_1_bits_fload),
     .io_in_bits_1_bits_iload(ctrl_io_in_bits_1_bits_iload),
     .io_in_bits_1_bits_fencei(ctrl_io_in_bits_1_bits_fencei),
     .io_in_bits_1_bits_flushat(ctrl_io_in_bits_1_bits_flushat),
@@ -21661,7 +20050,6 @@
     .io_in_bits_2_bits_size(ctrl_io_in_bits_2_bits_size),
     .io_in_bits_2_bits_write(ctrl_io_in_bits_2_bits_write),
     .io_in_bits_2_bits_sext(ctrl_io_in_bits_2_bits_sext),
-    .io_in_bits_2_bits_fload(ctrl_io_in_bits_2_bits_fload),
     .io_in_bits_2_bits_iload(ctrl_io_in_bits_2_bits_iload),
     .io_in_bits_2_bits_fencei(ctrl_io_in_bits_2_bits_fencei),
     .io_in_bits_2_bits_flushat(ctrl_io_in_bits_2_bits_flushat),
@@ -21677,7 +20065,6 @@
     .io_in_bits_3_bits_size(ctrl_io_in_bits_3_bits_size),
     .io_in_bits_3_bits_write(ctrl_io_in_bits_3_bits_write),
     .io_in_bits_3_bits_sext(ctrl_io_in_bits_3_bits_sext),
-    .io_in_bits_3_bits_fload(ctrl_io_in_bits_3_bits_fload),
     .io_in_bits_3_bits_iload(ctrl_io_in_bits_3_bits_iload),
     .io_in_bits_3_bits_fencei(ctrl_io_in_bits_3_bits_fencei),
     .io_in_bits_3_bits_flushat(ctrl_io_in_bits_3_bits_flushat),
@@ -21694,7 +20081,6 @@
     .io_out_bits_size(ctrl_io_out_bits_size),
     .io_out_bits_write(ctrl_io_out_bits_write),
     .io_out_bits_sext(ctrl_io_out_bits_sext),
-    .io_out_bits_fload(ctrl_io_out_bits_fload),
     .io_out_bits_iload(ctrl_io_out_bits_iload),
     .io_out_bits_fencei(ctrl_io_out_bits_fencei),
     .io_out_bits_flushat(ctrl_io_out_bits_flushat),
@@ -21713,7 +20099,6 @@
     .io_in_bits_index(data_io_in_bits_index),
     .io_in_bits_size(data_io_in_bits_size),
     .io_in_bits_sext(data_io_in_bits_sext),
-    .io_in_bits_fload(data_io_in_bits_fload),
     .io_in_bits_iload(data_io_in_bits_iload),
     .io_in_bits_sldst(data_io_in_bits_sldst),
     .io_in_bits_suncd(data_io_in_bits_suncd),
@@ -21722,128 +20107,119 @@
     .io_out_bits_index(data_io_out_bits_index),
     .io_out_bits_size(data_io_out_bits_size),
     .io_out_bits_sext(data_io_out_bits_sext),
-    .io_out_bits_fload(data_io_out_bits_fload),
     .io_out_bits_iload(data_io_out_bits_iload),
     .io_out_bits_sldst(data_io_out_bits_sldst),
     .io_out_bits_suncd(data_io_out_bits_suncd)
   );
-  assign io_req_0_ready = ctrlready[0]; // @[Lsu.scala 117:31]
-  assign io_req_1_ready = ctrlready[1]; // @[Lsu.scala 118:31]
-  assign io_req_2_ready = ctrlready[2]; // @[Lsu.scala 119:31]
-  assign io_req_3_ready = ctrlready[3]; // @[Lsu.scala 120:31]
-  assign io_rd_valid = data_io_out_valid & data_io_out_bits_iload; // @[Lsu.scala 293:25]
-  assign io_rd_addr = data_io_out_bits_index; // @[Lsu.scala 294:15]
-  assign io_rd_data = rdata[31:0]; // @[Lsu.scala 295:15]
-  assign io_fd_valid = data_io_out_valid & data_io_out_bits_fload; // @[Lsu.scala 297:25]
-  assign io_fd_addr = data_io_out_bits_index; // @[Lsu.scala 298:15]
-  assign io_fd_data = rdata[31:0]; // @[Lsu.scala 299:15]
-  assign io_dbus_valid = ctrl_io_out_valid & ctrl_io_out_bits_sldst; // @[Lsu.scala 197:38]
-  assign io_dbus_write = ctrl_io_out_bits_write; // @[Lsu.scala 198:17]
+  assign io_req_0_ready = ctrlready[0]; // @[Lsu.scala 111:31]
+  assign io_req_1_ready = ctrlready[1]; // @[Lsu.scala 112:31]
+  assign io_req_2_ready = ctrlready[2]; // @[Lsu.scala 113:31]
+  assign io_req_3_ready = ctrlready[3]; // @[Lsu.scala 114:31]
+  assign io_rd_valid = data_io_out_valid & data_io_out_bits_iload; // @[Lsu.scala 282:25]
+  assign io_rd_addr = data_io_out_bits_index; // @[Lsu.scala 283:15]
+  assign io_rd_data = rdata[31:0]; // @[Lsu.scala 284:15]
+  assign io_dbus_valid = ctrl_io_out_valid & ctrl_io_out_bits_sldst; // @[Lsu.scala 189:38]
+  assign io_dbus_write = ctrl_io_out_bits_write; // @[Lsu.scala 190:17]
   assign io_dbus_addr = {1'h0,ctrl_io_out_bits_addr[30:0]}; // @[Cat.scala 31:58]
   assign io_dbus_adrx = {1'h0,ctrl_io_out_bits_adrx[30:0]}; // @[Cat.scala 31:58]
-  assign io_dbus_size = ctrl_io_out_bits_size; // @[Lsu.scala 201:17]
+  assign io_dbus_size = ctrl_io_out_bits_size; // @[Lsu.scala 193:17]
   assign io_dbus_wdata = {wdata_lo,wdata_lo}; // @[Cat.scala 31:58]
-  assign io_dbus_wmask = wmaskS[31:0]; // @[Lsu.scala 181:21]
+  assign io_dbus_wmask = wmaskS[31:0]; // @[Lsu.scala 173:21]
   assign io_flush_valid = ctrl_io_out_valid & (ctrl_io_out_bits_fencei | ctrl_io_out_bits_flushat |
-    ctrl_io_out_bits_flushall); // @[Lsu.scala 219:40]
-  assign io_flush_all = ctrl_io_out_bits_fencei | ctrl_io_out_bits_flushall; // @[Lsu.scala 220:46]
-  assign io_flush_fencei = ctrl_io_out_bits_fencei; // @[Lsu.scala 222:19]
-  assign io_ubus_valid = ctrl_io_out_valid & ctrl_io_out_bits_suncd; // @[Lsu.scala 208:38]
-  assign io_ubus_write = ctrl_io_out_bits_write; // @[Lsu.scala 209:17]
+    ctrl_io_out_bits_flushall); // @[Lsu.scala 211:40]
+  assign io_flush_all = ctrl_io_out_bits_fencei | ctrl_io_out_bits_flushall; // @[Lsu.scala 212:46]
+  assign io_flush_fencei = ctrl_io_out_bits_fencei; // @[Lsu.scala 214:19]
+  assign io_ubus_valid = ctrl_io_out_valid & ctrl_io_out_bits_suncd; // @[Lsu.scala 200:38]
+  assign io_ubus_write = ctrl_io_out_bits_write; // @[Lsu.scala 201:17]
   assign io_ubus_addr = {1'h0,ctrl_io_out_bits_addr[30:0]}; // @[Cat.scala 31:58]
   assign io_ubus_wdata = {wdata_lo,wdata_lo}; // @[Cat.scala 31:58]
-  assign io_ubus_wmask = wmaskS[31:0]; // @[Lsu.scala 181:21]
-  assign io_vldst = ctrl_io_out_valid & ctrl_io_out_bits_vldst; // @[Lsu.scala 229:33]
+  assign io_ubus_wmask = wmaskS[31:0]; // @[Lsu.scala 173:21]
+  assign io_vldst = ctrl_io_out_valid & ctrl_io_out_bits_vldst; // @[Lsu.scala 221:33]
   assign ctrl_clock = clock;
   assign ctrl_reset = reset;
-  assign ctrl_io_in_valid = _ctrl_io_in_valid_T_1 | io_req_3_valid; // @[Lsu.scala 129:39]
-  assign ctrl_io_in_bits_0_valid = io_req_0_valid & ctrlready[0] & ~(opvldst & uncached); // @[Lsu.scala 148:65]
-  assign ctrl_io_in_bits_0_bits_addr = io_busPort_addr_0; // @[Lsu.scala 150:34]
-  assign ctrl_io_in_bits_0_bits_adrx = io_busPort_addr_0 + 32'h20; // @[Lsu.scala 151:56]
-  assign ctrl_io_in_bits_0_bits_data = io_req_0_op[9] ? io_fbusPort_data : io_busPort_data_0; // @[Lsu.scala 152:40]
-  assign ctrl_io_in_bits_0_bits_index = io_req_0_addr; // @[Lsu.scala 153:35]
-  assign ctrl_io_in_bits_0_bits_size = {{3'd0}, opsize}; // @[Lsu.scala 155:34]
-  assign ctrl_io_in_bits_0_bits_write = ~opload; // @[Lsu.scala 164:38]
-  assign ctrl_io_in_bits_0_bits_sext = io_req_0_op[0] | io_req_0_op[1]; // @[Lsu.scala 143:39]
-  assign ctrl_io_in_bits_0_bits_fload = io_req_0_op[8]; // @[Lsu.scala 136:31]
+  assign ctrl_io_in_valid = _ctrl_io_in_valid_T_1 | io_req_3_valid; // @[Lsu.scala 123:39]
+  assign ctrl_io_in_bits_0_valid = io_req_0_valid & ctrlready[0] & ~(opvldst & uncached); // @[Lsu.scala 141:65]
+  assign ctrl_io_in_bits_0_bits_addr = io_busPort_addr_0; // @[Lsu.scala 143:34]
+  assign ctrl_io_in_bits_0_bits_adrx = io_busPort_addr_0 + 32'h20; // @[Lsu.scala 144:56]
+  assign ctrl_io_in_bits_0_bits_data = io_busPort_data_0; // @[Lsu.scala 145:34]
+  assign ctrl_io_in_bits_0_bits_index = io_req_0_addr; // @[Lsu.scala 146:35]
+  assign ctrl_io_in_bits_0_bits_size = {{3'd0}, opsize}; // @[Lsu.scala 148:34]
+  assign ctrl_io_in_bits_0_bits_write = ~opiload; // @[Lsu.scala 156:38]
+  assign ctrl_io_in_bits_0_bits_sext = io_req_0_op[0] | io_req_0_op[1]; // @[Lsu.scala 136:39]
   assign ctrl_io_in_bits_0_bits_iload = io_req_0_op[2] | io_req_0_op[1] | io_req_0_op[0] | io_req_0_op[4] | io_req_0_op[
-    3]; // @[Lsu.scala 135:113]
-  assign ctrl_io_in_bits_0_bits_fencei = io_req_0_op[10]; // @[Lsu.scala 138:34]
-  assign ctrl_io_in_bits_0_bits_flushat = io_req_0_op[11]; // @[Lsu.scala 139:34]
-  assign ctrl_io_in_bits_0_bits_flushall = io_req_0_op[12]; // @[Lsu.scala 140:34]
-  assign ctrl_io_in_bits_0_bits_sldst = opsldst & ~uncached; // @[Lsu.scala 161:46]
-  assign ctrl_io_in_bits_0_bits_vldst = io_req_0_op[13]; // @[Lsu.scala 142:31]
-  assign ctrl_io_in_bits_0_bits_suncd = opsldst & uncached; // @[Lsu.scala 163:46]
-  assign ctrl_io_in_bits_1_valid = io_req_1_valid & ctrlready[1] & ~(opvldst_1 & uncached_1); // @[Lsu.scala 148:65]
-  assign ctrl_io_in_bits_1_bits_addr = io_busPort_addr_1; // @[Lsu.scala 150:34]
-  assign ctrl_io_in_bits_1_bits_adrx = io_busPort_addr_1 + 32'h20; // @[Lsu.scala 151:56]
-  assign ctrl_io_in_bits_1_bits_data = io_req_1_op[9] ? io_fbusPort_data : io_busPort_data_1; // @[Lsu.scala 152:40]
-  assign ctrl_io_in_bits_1_bits_index = io_req_1_addr; // @[Lsu.scala 153:35]
-  assign ctrl_io_in_bits_1_bits_size = {{3'd0}, opsize_1}; // @[Lsu.scala 155:34]
-  assign ctrl_io_in_bits_1_bits_write = ~opload_1; // @[Lsu.scala 164:38]
-  assign ctrl_io_in_bits_1_bits_sext = io_req_1_op[0] | io_req_1_op[1]; // @[Lsu.scala 143:39]
-  assign ctrl_io_in_bits_1_bits_fload = io_req_1_op[8]; // @[Lsu.scala 136:31]
+    3]; // @[Lsu.scala 129:113]
+  assign ctrl_io_in_bits_0_bits_fencei = io_req_0_op[8]; // @[Lsu.scala 131:34]
+  assign ctrl_io_in_bits_0_bits_flushat = io_req_0_op[9]; // @[Lsu.scala 132:34]
+  assign ctrl_io_in_bits_0_bits_flushall = io_req_0_op[10]; // @[Lsu.scala 133:34]
+  assign ctrl_io_in_bits_0_bits_sldst = opsldst & ~uncached; // @[Lsu.scala 153:46]
+  assign ctrl_io_in_bits_0_bits_vldst = io_req_0_op[11]; // @[Lsu.scala 135:31]
+  assign ctrl_io_in_bits_0_bits_suncd = opsldst & uncached; // @[Lsu.scala 155:46]
+  assign ctrl_io_in_bits_1_valid = io_req_1_valid & ctrlready[1] & ~(opvldst_1 & uncached_1); // @[Lsu.scala 141:65]
+  assign ctrl_io_in_bits_1_bits_addr = io_busPort_addr_1; // @[Lsu.scala 143:34]
+  assign ctrl_io_in_bits_1_bits_adrx = io_busPort_addr_1 + 32'h20; // @[Lsu.scala 144:56]
+  assign ctrl_io_in_bits_1_bits_data = io_busPort_data_1; // @[Lsu.scala 145:34]
+  assign ctrl_io_in_bits_1_bits_index = io_req_1_addr; // @[Lsu.scala 146:35]
+  assign ctrl_io_in_bits_1_bits_size = {{3'd0}, opsize_1}; // @[Lsu.scala 148:34]
+  assign ctrl_io_in_bits_1_bits_write = ~opiload_1; // @[Lsu.scala 156:38]
+  assign ctrl_io_in_bits_1_bits_sext = io_req_1_op[0] | io_req_1_op[1]; // @[Lsu.scala 136:39]
   assign ctrl_io_in_bits_1_bits_iload = io_req_1_op[2] | io_req_1_op[1] | io_req_1_op[0] | io_req_1_op[4] | io_req_1_op[
-    3]; // @[Lsu.scala 135:113]
-  assign ctrl_io_in_bits_1_bits_fencei = io_req_1_op[10]; // @[Lsu.scala 138:34]
-  assign ctrl_io_in_bits_1_bits_flushat = io_req_1_op[11]; // @[Lsu.scala 139:34]
-  assign ctrl_io_in_bits_1_bits_flushall = io_req_1_op[12]; // @[Lsu.scala 140:34]
-  assign ctrl_io_in_bits_1_bits_sldst = opsldst_1 & ~uncached_1; // @[Lsu.scala 161:46]
-  assign ctrl_io_in_bits_1_bits_vldst = io_req_1_op[13]; // @[Lsu.scala 142:31]
-  assign ctrl_io_in_bits_1_bits_suncd = opsldst_1 & uncached_1; // @[Lsu.scala 163:46]
-  assign ctrl_io_in_bits_2_valid = io_req_2_valid & ctrlready[2] & ~(opvldst_2 & uncached_2); // @[Lsu.scala 148:65]
-  assign ctrl_io_in_bits_2_bits_addr = io_busPort_addr_2; // @[Lsu.scala 150:34]
-  assign ctrl_io_in_bits_2_bits_adrx = io_busPort_addr_2 + 32'h20; // @[Lsu.scala 151:56]
-  assign ctrl_io_in_bits_2_bits_data = io_req_2_op[9] ? io_fbusPort_data : io_busPort_data_2; // @[Lsu.scala 152:40]
-  assign ctrl_io_in_bits_2_bits_index = io_req_2_addr; // @[Lsu.scala 153:35]
-  assign ctrl_io_in_bits_2_bits_size = {{3'd0}, opsize_2}; // @[Lsu.scala 155:34]
-  assign ctrl_io_in_bits_2_bits_write = ~opload_2; // @[Lsu.scala 164:38]
-  assign ctrl_io_in_bits_2_bits_sext = io_req_2_op[0] | io_req_2_op[1]; // @[Lsu.scala 143:39]
-  assign ctrl_io_in_bits_2_bits_fload = io_req_2_op[8]; // @[Lsu.scala 136:31]
+    3]; // @[Lsu.scala 129:113]
+  assign ctrl_io_in_bits_1_bits_fencei = io_req_1_op[8]; // @[Lsu.scala 131:34]
+  assign ctrl_io_in_bits_1_bits_flushat = io_req_1_op[9]; // @[Lsu.scala 132:34]
+  assign ctrl_io_in_bits_1_bits_flushall = io_req_1_op[10]; // @[Lsu.scala 133:34]
+  assign ctrl_io_in_bits_1_bits_sldst = opsldst_1 & ~uncached_1; // @[Lsu.scala 153:46]
+  assign ctrl_io_in_bits_1_bits_vldst = io_req_1_op[11]; // @[Lsu.scala 135:31]
+  assign ctrl_io_in_bits_1_bits_suncd = opsldst_1 & uncached_1; // @[Lsu.scala 155:46]
+  assign ctrl_io_in_bits_2_valid = io_req_2_valid & ctrlready[2] & ~(opvldst_2 & uncached_2); // @[Lsu.scala 141:65]
+  assign ctrl_io_in_bits_2_bits_addr = io_busPort_addr_2; // @[Lsu.scala 143:34]
+  assign ctrl_io_in_bits_2_bits_adrx = io_busPort_addr_2 + 32'h20; // @[Lsu.scala 144:56]
+  assign ctrl_io_in_bits_2_bits_data = io_busPort_data_2; // @[Lsu.scala 145:34]
+  assign ctrl_io_in_bits_2_bits_index = io_req_2_addr; // @[Lsu.scala 146:35]
+  assign ctrl_io_in_bits_2_bits_size = {{3'd0}, opsize_2}; // @[Lsu.scala 148:34]
+  assign ctrl_io_in_bits_2_bits_write = ~opiload_2; // @[Lsu.scala 156:38]
+  assign ctrl_io_in_bits_2_bits_sext = io_req_2_op[0] | io_req_2_op[1]; // @[Lsu.scala 136:39]
   assign ctrl_io_in_bits_2_bits_iload = io_req_2_op[2] | io_req_2_op[1] | io_req_2_op[0] | io_req_2_op[4] | io_req_2_op[
-    3]; // @[Lsu.scala 135:113]
-  assign ctrl_io_in_bits_2_bits_fencei = io_req_2_op[10]; // @[Lsu.scala 138:34]
-  assign ctrl_io_in_bits_2_bits_flushat = io_req_2_op[11]; // @[Lsu.scala 139:34]
-  assign ctrl_io_in_bits_2_bits_flushall = io_req_2_op[12]; // @[Lsu.scala 140:34]
-  assign ctrl_io_in_bits_2_bits_sldst = opsldst_2 & ~uncached_2; // @[Lsu.scala 161:46]
-  assign ctrl_io_in_bits_2_bits_vldst = io_req_2_op[13]; // @[Lsu.scala 142:31]
-  assign ctrl_io_in_bits_2_bits_suncd = opsldst_2 & uncached_2; // @[Lsu.scala 163:46]
-  assign ctrl_io_in_bits_3_valid = io_req_3_valid & ctrlready[3] & ~(opvldst_3 & uncached_3); // @[Lsu.scala 148:65]
-  assign ctrl_io_in_bits_3_bits_addr = io_busPort_addr_3; // @[Lsu.scala 150:34]
-  assign ctrl_io_in_bits_3_bits_adrx = io_busPort_addr_3 + 32'h20; // @[Lsu.scala 151:56]
-  assign ctrl_io_in_bits_3_bits_data = io_req_3_op[9] ? io_fbusPort_data : io_busPort_data_3; // @[Lsu.scala 152:40]
-  assign ctrl_io_in_bits_3_bits_index = io_req_3_addr; // @[Lsu.scala 153:35]
-  assign ctrl_io_in_bits_3_bits_size = {{3'd0}, opsize_3}; // @[Lsu.scala 155:34]
-  assign ctrl_io_in_bits_3_bits_write = ~opload_3; // @[Lsu.scala 164:38]
-  assign ctrl_io_in_bits_3_bits_sext = io_req_3_op[0] | io_req_3_op[1]; // @[Lsu.scala 143:39]
-  assign ctrl_io_in_bits_3_bits_fload = io_req_3_op[8]; // @[Lsu.scala 136:31]
+    3]; // @[Lsu.scala 129:113]
+  assign ctrl_io_in_bits_2_bits_fencei = io_req_2_op[8]; // @[Lsu.scala 131:34]
+  assign ctrl_io_in_bits_2_bits_flushat = io_req_2_op[9]; // @[Lsu.scala 132:34]
+  assign ctrl_io_in_bits_2_bits_flushall = io_req_2_op[10]; // @[Lsu.scala 133:34]
+  assign ctrl_io_in_bits_2_bits_sldst = opsldst_2 & ~uncached_2; // @[Lsu.scala 153:46]
+  assign ctrl_io_in_bits_2_bits_vldst = io_req_2_op[11]; // @[Lsu.scala 135:31]
+  assign ctrl_io_in_bits_2_bits_suncd = opsldst_2 & uncached_2; // @[Lsu.scala 155:46]
+  assign ctrl_io_in_bits_3_valid = io_req_3_valid & ctrlready[3] & ~(opvldst_3 & uncached_3); // @[Lsu.scala 141:65]
+  assign ctrl_io_in_bits_3_bits_addr = io_busPort_addr_3; // @[Lsu.scala 143:34]
+  assign ctrl_io_in_bits_3_bits_adrx = io_busPort_addr_3 + 32'h20; // @[Lsu.scala 144:56]
+  assign ctrl_io_in_bits_3_bits_data = io_busPort_data_3; // @[Lsu.scala 145:34]
+  assign ctrl_io_in_bits_3_bits_index = io_req_3_addr; // @[Lsu.scala 146:35]
+  assign ctrl_io_in_bits_3_bits_size = {{3'd0}, opsize_3}; // @[Lsu.scala 148:34]
+  assign ctrl_io_in_bits_3_bits_write = ~opiload_3; // @[Lsu.scala 156:38]
+  assign ctrl_io_in_bits_3_bits_sext = io_req_3_op[0] | io_req_3_op[1]; // @[Lsu.scala 136:39]
   assign ctrl_io_in_bits_3_bits_iload = io_req_3_op[2] | io_req_3_op[1] | io_req_3_op[0] | io_req_3_op[4] | io_req_3_op[
-    3]; // @[Lsu.scala 135:113]
-  assign ctrl_io_in_bits_3_bits_fencei = io_req_3_op[10]; // @[Lsu.scala 138:34]
-  assign ctrl_io_in_bits_3_bits_flushat = io_req_3_op[11]; // @[Lsu.scala 139:34]
-  assign ctrl_io_in_bits_3_bits_flushall = io_req_3_op[12]; // @[Lsu.scala 140:34]
-  assign ctrl_io_in_bits_3_bits_sldst = opsldst_3 & ~uncached_3; // @[Lsu.scala 161:46]
-  assign ctrl_io_in_bits_3_bits_vldst = io_req_3_op[13]; // @[Lsu.scala 142:31]
-  assign ctrl_io_in_bits_3_bits_suncd = opsldst_3 & uncached_3; // @[Lsu.scala 163:46]
-  assign ctrl_io_out_ready = _ctrl_io_out_ready_T_4 | _ctrl_io_out_ready_T_5; // @[Lsu.scala 226:55]
+    3]; // @[Lsu.scala 129:113]
+  assign ctrl_io_in_bits_3_bits_fencei = io_req_3_op[8]; // @[Lsu.scala 131:34]
+  assign ctrl_io_in_bits_3_bits_flushat = io_req_3_op[9]; // @[Lsu.scala 132:34]
+  assign ctrl_io_in_bits_3_bits_flushall = io_req_3_op[10]; // @[Lsu.scala 133:34]
+  assign ctrl_io_in_bits_3_bits_sldst = opsldst_3 & ~uncached_3; // @[Lsu.scala 153:46]
+  assign ctrl_io_in_bits_3_bits_vldst = io_req_3_op[11]; // @[Lsu.scala 135:31]
+  assign ctrl_io_in_bits_3_bits_suncd = opsldst_3 & uncached_3; // @[Lsu.scala 155:46]
+  assign ctrl_io_out_ready = _ctrl_io_out_ready_T_4 | _ctrl_io_out_ready_T_5; // @[Lsu.scala 218:55]
   assign data_clock = clock;
   assign data_reset = reset;
-  assign data_io_in_valid = _ctrl_io_out_ready_T_1 & ~io_dbus_write | _data_io_in_valid_T_5; // @[Lsu.scala 233:72]
-  assign data_io_in_bits_addr = ctrl_io_out_bits_addr; // @[Lsu.scala 236:25]
-  assign data_io_in_bits_index = ctrl_io_out_bits_index; // @[Lsu.scala 237:25]
-  assign data_io_in_bits_size = ctrl_io_out_bits_size; // @[Lsu.scala 239:25]
-  assign data_io_in_bits_sext = ctrl_io_out_bits_sext; // @[Lsu.scala 238:25]
-  assign data_io_in_bits_fload = ctrl_io_out_bits_fload; // @[Lsu.scala 240:25]
-  assign data_io_in_bits_iload = ctrl_io_out_bits_iload; // @[Lsu.scala 241:25]
-  assign data_io_in_bits_sldst = ctrl_io_out_bits_sldst; // @[Lsu.scala 242:25]
-  assign data_io_in_bits_suncd = ctrl_io_out_bits_suncd; // @[Lsu.scala 243:25]
+  assign data_io_in_valid = _ctrl_io_out_ready_T_1 & ~io_dbus_write | _data_io_in_valid_T_5; // @[Lsu.scala 225:72]
+  assign data_io_in_bits_addr = ctrl_io_out_bits_addr; // @[Lsu.scala 228:25]
+  assign data_io_in_bits_index = ctrl_io_out_bits_index; // @[Lsu.scala 229:25]
+  assign data_io_in_bits_size = ctrl_io_out_bits_size; // @[Lsu.scala 231:25]
+  assign data_io_in_bits_sext = ctrl_io_out_bits_sext; // @[Lsu.scala 230:25]
+  assign data_io_in_bits_iload = ctrl_io_out_bits_iload; // @[Lsu.scala 232:25]
+  assign data_io_in_bits_sldst = ctrl_io_out_bits_sldst; // @[Lsu.scala 233:25]
+  assign data_io_in_bits_suncd = ctrl_io_out_bits_suncd; // @[Lsu.scala 234:25]
   always @(posedge clock) begin
     `ifndef SYNTHESIS
     `ifdef STOP_COND
       if (`STOP_COND) begin
     `endif
         if (~reset & ~(~(io_dbus_valid & ctrl_io_out_bits_addr[31]))) begin
-          $fatal; // @[Lsu.scala 204:9]
+          $fatal; // @[Lsu.scala 196:9]
         end
     `ifdef STOP_COND
       end
@@ -21855,7 +20231,7 @@
     `endif
         if (~reset & ~(~(io_dbus_valid & ctrl_io_out_bits_addr[31]))) begin
           $fwrite(32'h80000002,
-            "Assertion failed\n    at Lsu.scala:204 assert(!(io.dbus.valid && ctrl.io.out.bits.addr(31)))\n"); // @[Lsu.scala 204:9]
+            "Assertion failed\n    at Lsu.scala:196 assert(!(io.dbus.valid && ctrl.io.out.bits.addr(31)))\n"); // @[Lsu.scala 196:9]
         end
     `ifdef PRINTF_COND
       end
@@ -21866,7 +20242,7 @@
       if (`STOP_COND) begin
     `endif
         if (_T_4 & ~(~(io_dbus_valid & io_dbus_addr[31]))) begin
-          $fatal; // @[Lsu.scala 205:9]
+          $fatal; // @[Lsu.scala 197:9]
         end
     `ifdef STOP_COND
       end
@@ -21877,7 +20253,7 @@
       if (`PRINTF_COND) begin
     `endif
         if (_T_4 & ~(~(io_dbus_valid & io_dbus_addr[31]))) begin
-          $fwrite(32'h80000002,"Assertion failed\n    at Lsu.scala:205 assert(!(io.dbus.valid && io.dbus.addr(31)))\n"); // @[Lsu.scala 205:9]
+          $fwrite(32'h80000002,"Assertion failed\n    at Lsu.scala:197 assert(!(io.dbus.valid && io.dbus.addr(31)))\n"); // @[Lsu.scala 197:9]
         end
     `ifdef PRINTF_COND
       end
@@ -21888,7 +20264,7 @@
       if (`STOP_COND) begin
     `endif
         if (_T_4 & ~(~(io_dbus_valid & io_dbus_adrx[31]))) begin
-          $fatal; // @[Lsu.scala 206:9]
+          $fatal; // @[Lsu.scala 198:9]
         end
     `ifdef STOP_COND
       end
@@ -21899,7 +20275,7 @@
       if (`PRINTF_COND) begin
     `endif
         if (_T_4 & ~(~(io_dbus_valid & io_dbus_adrx[31]))) begin
-          $fwrite(32'h80000002,"Assertion failed\n    at Lsu.scala:206 assert(!(io.dbus.valid && io.dbus.adrx(31)))\n"); // @[Lsu.scala 206:9]
+          $fwrite(32'h80000002,"Assertion failed\n    at Lsu.scala:198 assert(!(io.dbus.valid && io.dbus.adrx(31)))\n"); // @[Lsu.scala 198:9]
         end
     `ifdef PRINTF_COND
       end
@@ -21910,7 +20286,7 @@
       if (`STOP_COND) begin
     `endif
         if (_T_4 & ~(~(io_ubus_valid & ~ctrl_io_out_bits_addr[31]))) begin
-          $fatal; // @[Lsu.scala 215:9]
+          $fatal; // @[Lsu.scala 207:9]
         end
     `ifdef STOP_COND
       end
@@ -21922,7 +20298,7 @@
     `endif
         if (_T_4 & ~(~(io_ubus_valid & ~ctrl_io_out_bits_addr[31]))) begin
           $fwrite(32'h80000002,
-            "Assertion failed\n    at Lsu.scala:215 assert(!(io.ubus.valid && !ctrl.io.out.bits.addr(31)))\n"); // @[Lsu.scala 215:9]
+            "Assertion failed\n    at Lsu.scala:207 assert(!(io.ubus.valid && !ctrl.io.out.bits.addr(31)))\n"); // @[Lsu.scala 207:9]
         end
     `ifdef PRINTF_COND
       end
@@ -21933,7 +20309,7 @@
       if (`STOP_COND) begin
     `endif
         if (_T_4 & ~(~(io_ubus_valid & io_dbus_addr[31]))) begin
-          $fatal; // @[Lsu.scala 216:9]
+          $fatal; // @[Lsu.scala 208:9]
         end
     `ifdef STOP_COND
       end
@@ -21944,7 +20320,7 @@
       if (`PRINTF_COND) begin
     `endif
         if (_T_4 & ~(~(io_ubus_valid & io_dbus_addr[31]))) begin
-          $fwrite(32'h80000002,"Assertion failed\n    at Lsu.scala:216 assert(!(io.ubus.valid && io.dbus.addr(31)))\n"); // @[Lsu.scala 216:9]
+          $fwrite(32'h80000002,"Assertion failed\n    at Lsu.scala:208 assert(!(io.ubus.valid && io.dbus.addr(31)))\n"); // @[Lsu.scala 208:9]
         end
     `ifdef PRINTF_COND
       end
@@ -21955,7 +20331,7 @@
       if (`STOP_COND) begin
     `endif
         if (_T_4 & ~(~(io_ubus_valid & io_dbus_adrx[31]))) begin
-          $fatal; // @[Lsu.scala 217:9]
+          $fatal; // @[Lsu.scala 209:9]
         end
     `ifdef STOP_COND
       end
@@ -21966,7 +20342,7 @@
       if (`PRINTF_COND) begin
     `endif
         if (_T_4 & ~(~(io_ubus_valid & io_dbus_adrx[31]))) begin
-          $fwrite(32'h80000002,"Assertion failed\n    at Lsu.scala:217 assert(!(io.ubus.valid && io.dbus.adrx(31)))\n"); // @[Lsu.scala 217:9]
+          $fwrite(32'h80000002,"Assertion failed\n    at Lsu.scala:209 assert(!(io.ubus.valid && io.dbus.adrx(31)))\n"); // @[Lsu.scala 209:9]
         end
     `ifdef PRINTF_COND
       end
@@ -21977,7 +20353,7 @@
       if (`STOP_COND) begin
     `endif
         if (_T_4 & ~(~ctrl_io_out_valid | _T_50[1:0] <= 2'h1)) begin
-          $fatal; // @[Lsu.scala 301:9]
+          $fatal; // @[Lsu.scala 286:9]
         end
     `ifdef STOP_COND
       end
@@ -21989,8 +20365,8 @@
     `endif
         if (_T_4 & ~(~ctrl_io_out_valid | _T_50[1:0] <= 2'h1)) begin
           $fwrite(32'h80000002,
-            "Assertion failed\n    at Lsu.scala:301 assert(!ctrl.io.out.valid || PopCount(Cat(ctrl.io.out.bits.sldst, ctrl.io.out.bits.vldst, ctrl.io.out.bits.suncd)) <= 1.U)\n"
-            ); // @[Lsu.scala 301:9]
+            "Assertion failed\n    at Lsu.scala:286 assert(!ctrl.io.out.valid || PopCount(Cat(ctrl.io.out.bits.sldst, ctrl.io.out.bits.vldst, ctrl.io.out.bits.suncd)) <= 1.U)\n"
+            ); // @[Lsu.scala 286:9]
         end
     `ifdef PRINTF_COND
       end
@@ -22001,7 +20377,7 @@
       if (`STOP_COND) begin
     `endif
         if (_T_4 & ~(~data_io_out_valid | _T_61 <= 2'h1)) begin
-          $fatal; // @[Lsu.scala 302:9]
+          $fatal; // @[Lsu.scala 287:9]
         end
     `ifdef STOP_COND
       end
@@ -22013,8 +20389,8 @@
     `endif
         if (_T_4 & ~(~data_io_out_valid | _T_61 <= 2'h1)) begin
           $fwrite(32'h80000002,
-            "Assertion failed\n    at Lsu.scala:302 assert(!data.io.out.valid || PopCount(Cat(data.io.out.bits.sldst, data.io.out.bits.suncd)) <= 1.U)\n"
-            ); // @[Lsu.scala 302:9]
+            "Assertion failed\n    at Lsu.scala:287 assert(!data.io.out.valid || PopCount(Cat(data.io.out.bits.sldst, data.io.out.bits.suncd)) <= 1.U)\n"
+            ); // @[Lsu.scala 287:9]
         end
     `ifdef PRINTF_COND
       end
@@ -22712,7491 +21088,6 @@
 `endif
 `endif // SYNTHESIS
 endmodule
-module FRegfile(
-  input         clock,
-  input         reset,
-  input         io_freadAddr_0_valid,
-  input  [4:0]  io_freadAddr_0_addr,
-  input         io_freadAddr_1_valid,
-  input  [4:0]  io_freadAddr_1_addr,
-  input         io_freadAddr_2_valid,
-  input  [4:0]  io_freadAddr_2_addr,
-  input         io_freadAddr_3_valid,
-  input  [4:0]  io_freadAddr_3_addr,
-  input         io_freadAddr_4_valid,
-  input  [4:0]  io_freadAddr_4_addr,
-  input         io_freadAddr_5_valid,
-  input  [4:0]  io_freadAddr_5_addr,
-  input         io_fwriteAddr_valid,
-  input  [4:0]  io_fwriteAddr_addr,
-  output [31:0] io_fbusPort_data,
-  output [31:0] io_freadData_0_data,
-  output [31:0] io_freadData_1_data,
-  output [31:0] io_freadData_2_data,
-  output [31:0] io_freadData_3_data,
-  output [31:0] io_freadData_4_data,
-  output [31:0] io_freadData_5_data,
-  input         io_fwriteData_0_valid,
-  input  [4:0]  io_fwriteData_0_addr,
-  input  [31:0] io_fwriteData_0_data,
-  input         io_fwriteData_1_valid,
-  input  [4:0]  io_fwriteData_1_addr,
-  input  [31:0] io_fwriteData_1_data,
-  input         io_fwriteData_2_valid,
-  input  [4:0]  io_fwriteData_2_addr,
-  input  [31:0] io_fwriteData_2_data,
-  input         io_fwriteData_3_valid,
-  input  [4:0]  io_fwriteData_3_addr,
-  input  [31:0] io_fwriteData_3_data,
-  input         io_fwriteData_4_valid,
-  input  [4:0]  io_fwriteData_4_addr,
-  input  [31:0] io_fwriteData_4_data,
-  input         io_fwriteData_5_valid,
-  input  [4:0]  io_fwriteData_5_addr,
-  input  [31:0] io_fwriteData_5_data,
-  output [31:0] io_fscoreboard
-);
-`ifdef RANDOMIZE_REG_INIT
-  reg [31:0] _RAND_0;
-  reg [31:0] _RAND_1;
-  reg [31:0] _RAND_2;
-  reg [31:0] _RAND_3;
-  reg [31:0] _RAND_4;
-  reg [31:0] _RAND_5;
-  reg [31:0] _RAND_6;
-  reg [31:0] _RAND_7;
-  reg [31:0] _RAND_8;
-  reg [31:0] _RAND_9;
-  reg [31:0] _RAND_10;
-  reg [31:0] _RAND_11;
-  reg [31:0] _RAND_12;
-  reg [31:0] _RAND_13;
-  reg [31:0] _RAND_14;
-  reg [31:0] _RAND_15;
-  reg [31:0] _RAND_16;
-  reg [31:0] _RAND_17;
-  reg [31:0] _RAND_18;
-  reg [31:0] _RAND_19;
-  reg [31:0] _RAND_20;
-  reg [31:0] _RAND_21;
-  reg [31:0] _RAND_22;
-  reg [31:0] _RAND_23;
-  reg [31:0] _RAND_24;
-  reg [31:0] _RAND_25;
-  reg [31:0] _RAND_26;
-  reg [31:0] _RAND_27;
-  reg [31:0] _RAND_28;
-  reg [31:0] _RAND_29;
-  reg [31:0] _RAND_30;
-  reg [31:0] _RAND_31;
-  reg [31:0] _RAND_32;
-  reg [31:0] _RAND_33;
-  reg [31:0] _RAND_34;
-  reg [31:0] _RAND_35;
-  reg [31:0] _RAND_36;
-  reg [31:0] _RAND_37;
-  reg [31:0] _RAND_38;
-  reg [31:0] _RAND_39;
-  reg [31:0] _RAND_40;
-`endif // RANDOMIZE_REG_INIT
-  reg [31:0] fregfile_0; // @[FRegfile.scala 55:21]
-  reg [31:0] fregfile_1; // @[FRegfile.scala 55:21]
-  reg [31:0] fregfile_2; // @[FRegfile.scala 55:21]
-  reg [31:0] fregfile_3; // @[FRegfile.scala 55:21]
-  reg [31:0] fregfile_4; // @[FRegfile.scala 55:21]
-  reg [31:0] fregfile_5; // @[FRegfile.scala 55:21]
-  reg [31:0] fregfile_6; // @[FRegfile.scala 55:21]
-  reg [31:0] fregfile_7; // @[FRegfile.scala 55:21]
-  reg [31:0] fregfile_8; // @[FRegfile.scala 55:21]
-  reg [31:0] fregfile_9; // @[FRegfile.scala 55:21]
-  reg [31:0] fregfile_10; // @[FRegfile.scala 55:21]
-  reg [31:0] fregfile_11; // @[FRegfile.scala 55:21]
-  reg [31:0] fregfile_12; // @[FRegfile.scala 55:21]
-  reg [31:0] fregfile_13; // @[FRegfile.scala 55:21]
-  reg [31:0] fregfile_14; // @[FRegfile.scala 55:21]
-  reg [31:0] fregfile_15; // @[FRegfile.scala 55:21]
-  reg [31:0] fregfile_16; // @[FRegfile.scala 55:21]
-  reg [31:0] fregfile_17; // @[FRegfile.scala 55:21]
-  reg [31:0] fregfile_18; // @[FRegfile.scala 55:21]
-  reg [31:0] fregfile_19; // @[FRegfile.scala 55:21]
-  reg [31:0] fregfile_20; // @[FRegfile.scala 55:21]
-  reg [31:0] fregfile_21; // @[FRegfile.scala 55:21]
-  reg [31:0] fregfile_22; // @[FRegfile.scala 55:21]
-  reg [31:0] fregfile_23; // @[FRegfile.scala 55:21]
-  reg [31:0] fregfile_24; // @[FRegfile.scala 55:21]
-  reg [31:0] fregfile_25; // @[FRegfile.scala 55:21]
-  reg [31:0] fregfile_26; // @[FRegfile.scala 55:21]
-  reg [31:0] fregfile_27; // @[FRegfile.scala 55:21]
-  reg [31:0] fregfile_28; // @[FRegfile.scala 55:21]
-  reg [31:0] fregfile_29; // @[FRegfile.scala 55:21]
-  reg [31:0] fregfile_30; // @[FRegfile.scala 55:21]
-  reg [31:0] fregfile_31; // @[FRegfile.scala 55:21]
-  reg [31:0] scoreboard; // @[FRegfile.scala 58:27]
-  wire [31:0] _scoreboard_set_T = 32'h1 << io_fwriteAddr_addr; // @[OneHot.scala 64:12]
-  wire [31:0] scoreboard_set = io_fwriteAddr_valid ? _scoreboard_set_T : 32'h0; // @[FRegfile.scala 61:8]
-  wire [31:0] _scoreboard_clr_T = 32'h1 << io_fwriteData_0_addr; // @[OneHot.scala 64:12]
-  wire [31:0] _scoreboard_clr_T_2 = io_fwriteData_0_valid ? _scoreboard_clr_T : 32'h0; // @[FRegfile.scala 64:8]
-  wire [31:0] _scoreboard_clr_T_3 = 32'h1 << io_fwriteData_1_addr; // @[OneHot.scala 64:12]
-  wire [31:0] _scoreboard_clr_T_5 = io_fwriteData_1_valid ? _scoreboard_clr_T_3 : 32'h0; // @[FRegfile.scala 65:8]
-  wire [31:0] _scoreboard_clr_T_6 = _scoreboard_clr_T_2 | _scoreboard_clr_T_5; // @[FRegfile.scala 64:73]
-  wire [31:0] _scoreboard_clr_T_7 = 32'h1 << io_fwriteData_2_addr; // @[OneHot.scala 64:12]
-  wire [31:0] _scoreboard_clr_T_9 = io_fwriteData_2_valid ? _scoreboard_clr_T_7 : 32'h0; // @[FRegfile.scala 66:8]
-  wire [31:0] _scoreboard_clr_T_10 = _scoreboard_clr_T_6 | _scoreboard_clr_T_9; // @[FRegfile.scala 65:73]
-  wire [31:0] _scoreboard_clr_T_11 = 32'h1 << io_fwriteData_3_addr; // @[OneHot.scala 64:12]
-  wire [31:0] _scoreboard_clr_T_13 = io_fwriteData_3_valid ? _scoreboard_clr_T_11 : 32'h0; // @[FRegfile.scala 67:8]
-  wire [31:0] _scoreboard_clr_T_14 = _scoreboard_clr_T_10 | _scoreboard_clr_T_13; // @[FRegfile.scala 66:73]
-  wire [31:0] _scoreboard_clr_T_15 = 32'h1 << io_fwriteData_4_addr; // @[OneHot.scala 64:12]
-  wire [31:0] _scoreboard_clr_T_17 = io_fwriteData_4_valid ? _scoreboard_clr_T_15 : 32'h0; // @[FRegfile.scala 68:8]
-  wire [31:0] _scoreboard_clr_T_18 = _scoreboard_clr_T_14 | _scoreboard_clr_T_17; // @[FRegfile.scala 67:73]
-  wire [31:0] _scoreboard_clr_T_19 = 32'h1 << io_fwriteData_5_addr; // @[OneHot.scala 64:12]
-  wire [31:0] _scoreboard_clr_T_21 = io_fwriteData_5_valid ? _scoreboard_clr_T_19 : 32'h0; // @[FRegfile.scala 69:8]
-  wire [31:0] scoreboard_clr = _scoreboard_clr_T_18 | _scoreboard_clr_T_21; // @[FRegfile.scala 68:73]
-  wire [31:0] _scoreboard_T = ~scoreboard_clr; // @[FRegfile.scala 72:33]
-  wire [31:0] _scoreboard_T_1 = scoreboard & _scoreboard_T; // @[FRegfile.scala 72:31]
-  wire [31:0] _scoreboard_T_2 = _scoreboard_T_1 | scoreboard_set; // @[FRegfile.scala 72:50]
-  wire  _valid_T_1 = io_fwriteData_5_valid & io_fwriteData_5_addr == 5'h0; // @[FRegfile.scala 82:44]
-  wire  _valid_T_3 = io_fwriteData_4_valid & io_fwriteData_4_addr == 5'h0; // @[FRegfile.scala 83:44]
-  wire  _valid_T_5 = io_fwriteData_3_valid & io_fwriteData_3_addr == 5'h0; // @[FRegfile.scala 84:44]
-  wire  _valid_T_7 = io_fwriteData_2_valid & io_fwriteData_2_addr == 5'h0; // @[FRegfile.scala 85:44]
-  wire  _valid_T_9 = io_fwriteData_1_valid & io_fwriteData_1_addr == 5'h0; // @[FRegfile.scala 86:44]
-  wire  _valid_T_11 = io_fwriteData_0_valid & io_fwriteData_0_addr == 5'h0; // @[FRegfile.scala 87:44]
-  wire [5:0] valid = {_valid_T_1,_valid_T_3,_valid_T_5,_valid_T_7,_valid_T_9,_valid_T_11}; // @[Cat.scala 31:58]
-  wire [31:0] _data_T_1 = valid[0] ? io_fwriteData_0_data : 32'h0; // @[FRegfile.scala 88:20]
-  wire [31:0] _data_T_3 = valid[1] ? io_fwriteData_1_data : 32'h0; // @[FRegfile.scala 89:20]
-  wire [31:0] _data_T_4 = _data_T_1 | _data_T_3; // @[FRegfile.scala 88:59]
-  wire [31:0] _data_T_6 = valid[2] ? io_fwriteData_2_data : 32'h0; // @[FRegfile.scala 90:20]
-  wire [31:0] _data_T_7 = _data_T_4 | _data_T_6; // @[FRegfile.scala 89:59]
-  wire [31:0] _data_T_9 = valid[3] ? io_fwriteData_3_data : 32'h0; // @[FRegfile.scala 91:20]
-  wire [31:0] _data_T_10 = _data_T_7 | _data_T_9; // @[FRegfile.scala 90:59]
-  wire [31:0] _data_T_12 = valid[4] ? io_fwriteData_4_data : 32'h0; // @[FRegfile.scala 92:20]
-  wire [31:0] _data_T_13 = _data_T_10 | _data_T_12; // @[FRegfile.scala 91:59]
-  wire [31:0] _data_T_15 = valid[5] ? io_fwriteData_5_data : 32'h0; // @[FRegfile.scala 93:20]
-  wire [31:0] data = _data_T_13 | _data_T_15; // @[FRegfile.scala 92:59]
-  wire  fwriteValid_0 = valid != 6'h0; // @[FRegfile.scala 95:29]
-  wire [1:0] _T_9 = valid[1] + valid[2]; // @[Bitwise.scala 48:55]
-  wire [1:0] _GEN_39 = {{1'd0}, valid[0]}; // @[Bitwise.scala 48:55]
-  wire [2:0] _T_11 = _GEN_39 + _T_9; // @[Bitwise.scala 48:55]
-  wire [1:0] _T_13 = valid[4] + valid[5]; // @[Bitwise.scala 48:55]
-  wire [1:0] _GEN_40 = {{1'd0}, valid[3]}; // @[Bitwise.scala 48:55]
-  wire [2:0] _T_15 = _GEN_40 + _T_13; // @[Bitwise.scala 48:55]
-  wire [2:0] _T_17 = _T_11[1:0] + _T_15[1:0]; // @[Bitwise.scala 48:55]
-  wire  _T_21 = ~reset; // @[FRegfile.scala 98:11]
-  wire  _valid_T_13 = io_fwriteData_5_valid & io_fwriteData_5_addr == 5'h1; // @[FRegfile.scala 82:44]
-  wire  _valid_T_15 = io_fwriteData_4_valid & io_fwriteData_4_addr == 5'h1; // @[FRegfile.scala 83:44]
-  wire  _valid_T_17 = io_fwriteData_3_valid & io_fwriteData_3_addr == 5'h1; // @[FRegfile.scala 84:44]
-  wire  _valid_T_19 = io_fwriteData_2_valid & io_fwriteData_2_addr == 5'h1; // @[FRegfile.scala 85:44]
-  wire  _valid_T_21 = io_fwriteData_1_valid & io_fwriteData_1_addr == 5'h1; // @[FRegfile.scala 86:44]
-  wire  _valid_T_23 = io_fwriteData_0_valid & io_fwriteData_0_addr == 5'h1; // @[FRegfile.scala 87:44]
-  wire [5:0] valid_1 = {_valid_T_13,_valid_T_15,_valid_T_17,_valid_T_19,_valid_T_21,_valid_T_23}; // @[Cat.scala 31:58]
-  wire [31:0] _data_T_17 = valid_1[0] ? io_fwriteData_0_data : 32'h0; // @[FRegfile.scala 88:20]
-  wire [31:0] _data_T_19 = valid_1[1] ? io_fwriteData_1_data : 32'h0; // @[FRegfile.scala 89:20]
-  wire [31:0] _data_T_20 = _data_T_17 | _data_T_19; // @[FRegfile.scala 88:59]
-  wire [31:0] _data_T_22 = valid_1[2] ? io_fwriteData_2_data : 32'h0; // @[FRegfile.scala 90:20]
-  wire [31:0] _data_T_23 = _data_T_20 | _data_T_22; // @[FRegfile.scala 89:59]
-  wire [31:0] _data_T_25 = valid_1[3] ? io_fwriteData_3_data : 32'h0; // @[FRegfile.scala 91:20]
-  wire [31:0] _data_T_26 = _data_T_23 | _data_T_25; // @[FRegfile.scala 90:59]
-  wire [31:0] _data_T_28 = valid_1[4] ? io_fwriteData_4_data : 32'h0; // @[FRegfile.scala 92:20]
-  wire [31:0] _data_T_29 = _data_T_26 | _data_T_28; // @[FRegfile.scala 91:59]
-  wire [31:0] _data_T_31 = valid_1[5] ? io_fwriteData_5_data : 32'h0; // @[FRegfile.scala 93:20]
-  wire [31:0] data_1 = _data_T_29 | _data_T_31; // @[FRegfile.scala 92:59]
-  wire  fwriteValid_1 = valid_1 != 6'h0; // @[FRegfile.scala 95:29]
-  wire [1:0] _T_29 = valid_1[1] + valid_1[2]; // @[Bitwise.scala 48:55]
-  wire [1:0] _GEN_41 = {{1'd0}, valid_1[0]}; // @[Bitwise.scala 48:55]
-  wire [2:0] _T_31 = _GEN_41 + _T_29; // @[Bitwise.scala 48:55]
-  wire [1:0] _T_33 = valid_1[4] + valid_1[5]; // @[Bitwise.scala 48:55]
-  wire [1:0] _GEN_42 = {{1'd0}, valid_1[3]}; // @[Bitwise.scala 48:55]
-  wire [2:0] _T_35 = _GEN_42 + _T_33; // @[Bitwise.scala 48:55]
-  wire [2:0] _T_37 = _T_31[1:0] + _T_35[1:0]; // @[Bitwise.scala 48:55]
-  wire  _valid_T_25 = io_fwriteData_5_valid & io_fwriteData_5_addr == 5'h2; // @[FRegfile.scala 82:44]
-  wire  _valid_T_27 = io_fwriteData_4_valid & io_fwriteData_4_addr == 5'h2; // @[FRegfile.scala 83:44]
-  wire  _valid_T_29 = io_fwriteData_3_valid & io_fwriteData_3_addr == 5'h2; // @[FRegfile.scala 84:44]
-  wire  _valid_T_31 = io_fwriteData_2_valid & io_fwriteData_2_addr == 5'h2; // @[FRegfile.scala 85:44]
-  wire  _valid_T_33 = io_fwriteData_1_valid & io_fwriteData_1_addr == 5'h2; // @[FRegfile.scala 86:44]
-  wire  _valid_T_35 = io_fwriteData_0_valid & io_fwriteData_0_addr == 5'h2; // @[FRegfile.scala 87:44]
-  wire [5:0] valid_2 = {_valid_T_25,_valid_T_27,_valid_T_29,_valid_T_31,_valid_T_33,_valid_T_35}; // @[Cat.scala 31:58]
-  wire [31:0] _data_T_33 = valid_2[0] ? io_fwriteData_0_data : 32'h0; // @[FRegfile.scala 88:20]
-  wire [31:0] _data_T_35 = valid_2[1] ? io_fwriteData_1_data : 32'h0; // @[FRegfile.scala 89:20]
-  wire [31:0] _data_T_36 = _data_T_33 | _data_T_35; // @[FRegfile.scala 88:59]
-  wire [31:0] _data_T_38 = valid_2[2] ? io_fwriteData_2_data : 32'h0; // @[FRegfile.scala 90:20]
-  wire [31:0] _data_T_39 = _data_T_36 | _data_T_38; // @[FRegfile.scala 89:59]
-  wire [31:0] _data_T_41 = valid_2[3] ? io_fwriteData_3_data : 32'h0; // @[FRegfile.scala 91:20]
-  wire [31:0] _data_T_42 = _data_T_39 | _data_T_41; // @[FRegfile.scala 90:59]
-  wire [31:0] _data_T_44 = valid_2[4] ? io_fwriteData_4_data : 32'h0; // @[FRegfile.scala 92:20]
-  wire [31:0] _data_T_45 = _data_T_42 | _data_T_44; // @[FRegfile.scala 91:59]
-  wire [31:0] _data_T_47 = valid_2[5] ? io_fwriteData_5_data : 32'h0; // @[FRegfile.scala 93:20]
-  wire [31:0] data_2 = _data_T_45 | _data_T_47; // @[FRegfile.scala 92:59]
-  wire  fwriteValid_2 = valid_2 != 6'h0; // @[FRegfile.scala 95:29]
-  wire [1:0] _T_49 = valid_2[1] + valid_2[2]; // @[Bitwise.scala 48:55]
-  wire [1:0] _GEN_43 = {{1'd0}, valid_2[0]}; // @[Bitwise.scala 48:55]
-  wire [2:0] _T_51 = _GEN_43 + _T_49; // @[Bitwise.scala 48:55]
-  wire [1:0] _T_53 = valid_2[4] + valid_2[5]; // @[Bitwise.scala 48:55]
-  wire [1:0] _GEN_44 = {{1'd0}, valid_2[3]}; // @[Bitwise.scala 48:55]
-  wire [2:0] _T_55 = _GEN_44 + _T_53; // @[Bitwise.scala 48:55]
-  wire [2:0] _T_57 = _T_51[1:0] + _T_55[1:0]; // @[Bitwise.scala 48:55]
-  wire  _valid_T_37 = io_fwriteData_5_valid & io_fwriteData_5_addr == 5'h3; // @[FRegfile.scala 82:44]
-  wire  _valid_T_39 = io_fwriteData_4_valid & io_fwriteData_4_addr == 5'h3; // @[FRegfile.scala 83:44]
-  wire  _valid_T_41 = io_fwriteData_3_valid & io_fwriteData_3_addr == 5'h3; // @[FRegfile.scala 84:44]
-  wire  _valid_T_43 = io_fwriteData_2_valid & io_fwriteData_2_addr == 5'h3; // @[FRegfile.scala 85:44]
-  wire  _valid_T_45 = io_fwriteData_1_valid & io_fwriteData_1_addr == 5'h3; // @[FRegfile.scala 86:44]
-  wire  _valid_T_47 = io_fwriteData_0_valid & io_fwriteData_0_addr == 5'h3; // @[FRegfile.scala 87:44]
-  wire [5:0] valid_3 = {_valid_T_37,_valid_T_39,_valid_T_41,_valid_T_43,_valid_T_45,_valid_T_47}; // @[Cat.scala 31:58]
-  wire [31:0] _data_T_49 = valid_3[0] ? io_fwriteData_0_data : 32'h0; // @[FRegfile.scala 88:20]
-  wire [31:0] _data_T_51 = valid_3[1] ? io_fwriteData_1_data : 32'h0; // @[FRegfile.scala 89:20]
-  wire [31:0] _data_T_52 = _data_T_49 | _data_T_51; // @[FRegfile.scala 88:59]
-  wire [31:0] _data_T_54 = valid_3[2] ? io_fwriteData_2_data : 32'h0; // @[FRegfile.scala 90:20]
-  wire [31:0] _data_T_55 = _data_T_52 | _data_T_54; // @[FRegfile.scala 89:59]
-  wire [31:0] _data_T_57 = valid_3[3] ? io_fwriteData_3_data : 32'h0; // @[FRegfile.scala 91:20]
-  wire [31:0] _data_T_58 = _data_T_55 | _data_T_57; // @[FRegfile.scala 90:59]
-  wire [31:0] _data_T_60 = valid_3[4] ? io_fwriteData_4_data : 32'h0; // @[FRegfile.scala 92:20]
-  wire [31:0] _data_T_61 = _data_T_58 | _data_T_60; // @[FRegfile.scala 91:59]
-  wire [31:0] _data_T_63 = valid_3[5] ? io_fwriteData_5_data : 32'h0; // @[FRegfile.scala 93:20]
-  wire [31:0] data_3 = _data_T_61 | _data_T_63; // @[FRegfile.scala 92:59]
-  wire  fwriteValid_3 = valid_3 != 6'h0; // @[FRegfile.scala 95:29]
-  wire [1:0] _T_69 = valid_3[1] + valid_3[2]; // @[Bitwise.scala 48:55]
-  wire [1:0] _GEN_45 = {{1'd0}, valid_3[0]}; // @[Bitwise.scala 48:55]
-  wire [2:0] _T_71 = _GEN_45 + _T_69; // @[Bitwise.scala 48:55]
-  wire [1:0] _T_73 = valid_3[4] + valid_3[5]; // @[Bitwise.scala 48:55]
-  wire [1:0] _GEN_46 = {{1'd0}, valid_3[3]}; // @[Bitwise.scala 48:55]
-  wire [2:0] _T_75 = _GEN_46 + _T_73; // @[Bitwise.scala 48:55]
-  wire [2:0] _T_77 = _T_71[1:0] + _T_75[1:0]; // @[Bitwise.scala 48:55]
-  wire  _valid_T_49 = io_fwriteData_5_valid & io_fwriteData_5_addr == 5'h4; // @[FRegfile.scala 82:44]
-  wire  _valid_T_51 = io_fwriteData_4_valid & io_fwriteData_4_addr == 5'h4; // @[FRegfile.scala 83:44]
-  wire  _valid_T_53 = io_fwriteData_3_valid & io_fwriteData_3_addr == 5'h4; // @[FRegfile.scala 84:44]
-  wire  _valid_T_55 = io_fwriteData_2_valid & io_fwriteData_2_addr == 5'h4; // @[FRegfile.scala 85:44]
-  wire  _valid_T_57 = io_fwriteData_1_valid & io_fwriteData_1_addr == 5'h4; // @[FRegfile.scala 86:44]
-  wire  _valid_T_59 = io_fwriteData_0_valid & io_fwriteData_0_addr == 5'h4; // @[FRegfile.scala 87:44]
-  wire [5:0] valid_4 = {_valid_T_49,_valid_T_51,_valid_T_53,_valid_T_55,_valid_T_57,_valid_T_59}; // @[Cat.scala 31:58]
-  wire [31:0] _data_T_65 = valid_4[0] ? io_fwriteData_0_data : 32'h0; // @[FRegfile.scala 88:20]
-  wire [31:0] _data_T_67 = valid_4[1] ? io_fwriteData_1_data : 32'h0; // @[FRegfile.scala 89:20]
-  wire [31:0] _data_T_68 = _data_T_65 | _data_T_67; // @[FRegfile.scala 88:59]
-  wire [31:0] _data_T_70 = valid_4[2] ? io_fwriteData_2_data : 32'h0; // @[FRegfile.scala 90:20]
-  wire [31:0] _data_T_71 = _data_T_68 | _data_T_70; // @[FRegfile.scala 89:59]
-  wire [31:0] _data_T_73 = valid_4[3] ? io_fwriteData_3_data : 32'h0; // @[FRegfile.scala 91:20]
-  wire [31:0] _data_T_74 = _data_T_71 | _data_T_73; // @[FRegfile.scala 90:59]
-  wire [31:0] _data_T_76 = valid_4[4] ? io_fwriteData_4_data : 32'h0; // @[FRegfile.scala 92:20]
-  wire [31:0] _data_T_77 = _data_T_74 | _data_T_76; // @[FRegfile.scala 91:59]
-  wire [31:0] _data_T_79 = valid_4[5] ? io_fwriteData_5_data : 32'h0; // @[FRegfile.scala 93:20]
-  wire [31:0] data_4 = _data_T_77 | _data_T_79; // @[FRegfile.scala 92:59]
-  wire  fwriteValid_4 = valid_4 != 6'h0; // @[FRegfile.scala 95:29]
-  wire [1:0] _T_89 = valid_4[1] + valid_4[2]; // @[Bitwise.scala 48:55]
-  wire [1:0] _GEN_47 = {{1'd0}, valid_4[0]}; // @[Bitwise.scala 48:55]
-  wire [2:0] _T_91 = _GEN_47 + _T_89; // @[Bitwise.scala 48:55]
-  wire [1:0] _T_93 = valid_4[4] + valid_4[5]; // @[Bitwise.scala 48:55]
-  wire [1:0] _GEN_48 = {{1'd0}, valid_4[3]}; // @[Bitwise.scala 48:55]
-  wire [2:0] _T_95 = _GEN_48 + _T_93; // @[Bitwise.scala 48:55]
-  wire [2:0] _T_97 = _T_91[1:0] + _T_95[1:0]; // @[Bitwise.scala 48:55]
-  wire  _valid_T_61 = io_fwriteData_5_valid & io_fwriteData_5_addr == 5'h5; // @[FRegfile.scala 82:44]
-  wire  _valid_T_63 = io_fwriteData_4_valid & io_fwriteData_4_addr == 5'h5; // @[FRegfile.scala 83:44]
-  wire  _valid_T_65 = io_fwriteData_3_valid & io_fwriteData_3_addr == 5'h5; // @[FRegfile.scala 84:44]
-  wire  _valid_T_67 = io_fwriteData_2_valid & io_fwriteData_2_addr == 5'h5; // @[FRegfile.scala 85:44]
-  wire  _valid_T_69 = io_fwriteData_1_valid & io_fwriteData_1_addr == 5'h5; // @[FRegfile.scala 86:44]
-  wire  _valid_T_71 = io_fwriteData_0_valid & io_fwriteData_0_addr == 5'h5; // @[FRegfile.scala 87:44]
-  wire [5:0] valid_5 = {_valid_T_61,_valid_T_63,_valid_T_65,_valid_T_67,_valid_T_69,_valid_T_71}; // @[Cat.scala 31:58]
-  wire [31:0] _data_T_81 = valid_5[0] ? io_fwriteData_0_data : 32'h0; // @[FRegfile.scala 88:20]
-  wire [31:0] _data_T_83 = valid_5[1] ? io_fwriteData_1_data : 32'h0; // @[FRegfile.scala 89:20]
-  wire [31:0] _data_T_84 = _data_T_81 | _data_T_83; // @[FRegfile.scala 88:59]
-  wire [31:0] _data_T_86 = valid_5[2] ? io_fwriteData_2_data : 32'h0; // @[FRegfile.scala 90:20]
-  wire [31:0] _data_T_87 = _data_T_84 | _data_T_86; // @[FRegfile.scala 89:59]
-  wire [31:0] _data_T_89 = valid_5[3] ? io_fwriteData_3_data : 32'h0; // @[FRegfile.scala 91:20]
-  wire [31:0] _data_T_90 = _data_T_87 | _data_T_89; // @[FRegfile.scala 90:59]
-  wire [31:0] _data_T_92 = valid_5[4] ? io_fwriteData_4_data : 32'h0; // @[FRegfile.scala 92:20]
-  wire [31:0] _data_T_93 = _data_T_90 | _data_T_92; // @[FRegfile.scala 91:59]
-  wire [31:0] _data_T_95 = valid_5[5] ? io_fwriteData_5_data : 32'h0; // @[FRegfile.scala 93:20]
-  wire [31:0] data_5 = _data_T_93 | _data_T_95; // @[FRegfile.scala 92:59]
-  wire  fwriteValid_5 = valid_5 != 6'h0; // @[FRegfile.scala 95:29]
-  wire [1:0] _T_109 = valid_5[1] + valid_5[2]; // @[Bitwise.scala 48:55]
-  wire [1:0] _GEN_49 = {{1'd0}, valid_5[0]}; // @[Bitwise.scala 48:55]
-  wire [2:0] _T_111 = _GEN_49 + _T_109; // @[Bitwise.scala 48:55]
-  wire [1:0] _T_113 = valid_5[4] + valid_5[5]; // @[Bitwise.scala 48:55]
-  wire [1:0] _GEN_50 = {{1'd0}, valid_5[3]}; // @[Bitwise.scala 48:55]
-  wire [2:0] _T_115 = _GEN_50 + _T_113; // @[Bitwise.scala 48:55]
-  wire [2:0] _T_117 = _T_111[1:0] + _T_115[1:0]; // @[Bitwise.scala 48:55]
-  wire  _valid_T_73 = io_fwriteData_5_valid & io_fwriteData_5_addr == 5'h6; // @[FRegfile.scala 82:44]
-  wire  _valid_T_75 = io_fwriteData_4_valid & io_fwriteData_4_addr == 5'h6; // @[FRegfile.scala 83:44]
-  wire  _valid_T_77 = io_fwriteData_3_valid & io_fwriteData_3_addr == 5'h6; // @[FRegfile.scala 84:44]
-  wire  _valid_T_79 = io_fwriteData_2_valid & io_fwriteData_2_addr == 5'h6; // @[FRegfile.scala 85:44]
-  wire  _valid_T_81 = io_fwriteData_1_valid & io_fwriteData_1_addr == 5'h6; // @[FRegfile.scala 86:44]
-  wire  _valid_T_83 = io_fwriteData_0_valid & io_fwriteData_0_addr == 5'h6; // @[FRegfile.scala 87:44]
-  wire [5:0] valid_6 = {_valid_T_73,_valid_T_75,_valid_T_77,_valid_T_79,_valid_T_81,_valid_T_83}; // @[Cat.scala 31:58]
-  wire [31:0] _data_T_97 = valid_6[0] ? io_fwriteData_0_data : 32'h0; // @[FRegfile.scala 88:20]
-  wire [31:0] _data_T_99 = valid_6[1] ? io_fwriteData_1_data : 32'h0; // @[FRegfile.scala 89:20]
-  wire [31:0] _data_T_100 = _data_T_97 | _data_T_99; // @[FRegfile.scala 88:59]
-  wire [31:0] _data_T_102 = valid_6[2] ? io_fwriteData_2_data : 32'h0; // @[FRegfile.scala 90:20]
-  wire [31:0] _data_T_103 = _data_T_100 | _data_T_102; // @[FRegfile.scala 89:59]
-  wire [31:0] _data_T_105 = valid_6[3] ? io_fwriteData_3_data : 32'h0; // @[FRegfile.scala 91:20]
-  wire [31:0] _data_T_106 = _data_T_103 | _data_T_105; // @[FRegfile.scala 90:59]
-  wire [31:0] _data_T_108 = valid_6[4] ? io_fwriteData_4_data : 32'h0; // @[FRegfile.scala 92:20]
-  wire [31:0] _data_T_109 = _data_T_106 | _data_T_108; // @[FRegfile.scala 91:59]
-  wire [31:0] _data_T_111 = valid_6[5] ? io_fwriteData_5_data : 32'h0; // @[FRegfile.scala 93:20]
-  wire [31:0] data_6 = _data_T_109 | _data_T_111; // @[FRegfile.scala 92:59]
-  wire  fwriteValid_6 = valid_6 != 6'h0; // @[FRegfile.scala 95:29]
-  wire [1:0] _T_129 = valid_6[1] + valid_6[2]; // @[Bitwise.scala 48:55]
-  wire [1:0] _GEN_51 = {{1'd0}, valid_6[0]}; // @[Bitwise.scala 48:55]
-  wire [2:0] _T_131 = _GEN_51 + _T_129; // @[Bitwise.scala 48:55]
-  wire [1:0] _T_133 = valid_6[4] + valid_6[5]; // @[Bitwise.scala 48:55]
-  wire [1:0] _GEN_52 = {{1'd0}, valid_6[3]}; // @[Bitwise.scala 48:55]
-  wire [2:0] _T_135 = _GEN_52 + _T_133; // @[Bitwise.scala 48:55]
-  wire [2:0] _T_137 = _T_131[1:0] + _T_135[1:0]; // @[Bitwise.scala 48:55]
-  wire  _valid_T_85 = io_fwriteData_5_valid & io_fwriteData_5_addr == 5'h7; // @[FRegfile.scala 82:44]
-  wire  _valid_T_87 = io_fwriteData_4_valid & io_fwriteData_4_addr == 5'h7; // @[FRegfile.scala 83:44]
-  wire  _valid_T_89 = io_fwriteData_3_valid & io_fwriteData_3_addr == 5'h7; // @[FRegfile.scala 84:44]
-  wire  _valid_T_91 = io_fwriteData_2_valid & io_fwriteData_2_addr == 5'h7; // @[FRegfile.scala 85:44]
-  wire  _valid_T_93 = io_fwriteData_1_valid & io_fwriteData_1_addr == 5'h7; // @[FRegfile.scala 86:44]
-  wire  _valid_T_95 = io_fwriteData_0_valid & io_fwriteData_0_addr == 5'h7; // @[FRegfile.scala 87:44]
-  wire [5:0] valid_7 = {_valid_T_85,_valid_T_87,_valid_T_89,_valid_T_91,_valid_T_93,_valid_T_95}; // @[Cat.scala 31:58]
-  wire [31:0] _data_T_113 = valid_7[0] ? io_fwriteData_0_data : 32'h0; // @[FRegfile.scala 88:20]
-  wire [31:0] _data_T_115 = valid_7[1] ? io_fwriteData_1_data : 32'h0; // @[FRegfile.scala 89:20]
-  wire [31:0] _data_T_116 = _data_T_113 | _data_T_115; // @[FRegfile.scala 88:59]
-  wire [31:0] _data_T_118 = valid_7[2] ? io_fwriteData_2_data : 32'h0; // @[FRegfile.scala 90:20]
-  wire [31:0] _data_T_119 = _data_T_116 | _data_T_118; // @[FRegfile.scala 89:59]
-  wire [31:0] _data_T_121 = valid_7[3] ? io_fwriteData_3_data : 32'h0; // @[FRegfile.scala 91:20]
-  wire [31:0] _data_T_122 = _data_T_119 | _data_T_121; // @[FRegfile.scala 90:59]
-  wire [31:0] _data_T_124 = valid_7[4] ? io_fwriteData_4_data : 32'h0; // @[FRegfile.scala 92:20]
-  wire [31:0] _data_T_125 = _data_T_122 | _data_T_124; // @[FRegfile.scala 91:59]
-  wire [31:0] _data_T_127 = valid_7[5] ? io_fwriteData_5_data : 32'h0; // @[FRegfile.scala 93:20]
-  wire [31:0] data_7 = _data_T_125 | _data_T_127; // @[FRegfile.scala 92:59]
-  wire  fwriteValid_7 = valid_7 != 6'h0; // @[FRegfile.scala 95:29]
-  wire [1:0] _T_149 = valid_7[1] + valid_7[2]; // @[Bitwise.scala 48:55]
-  wire [1:0] _GEN_53 = {{1'd0}, valid_7[0]}; // @[Bitwise.scala 48:55]
-  wire [2:0] _T_151 = _GEN_53 + _T_149; // @[Bitwise.scala 48:55]
-  wire [1:0] _T_153 = valid_7[4] + valid_7[5]; // @[Bitwise.scala 48:55]
-  wire [1:0] _GEN_54 = {{1'd0}, valid_7[3]}; // @[Bitwise.scala 48:55]
-  wire [2:0] _T_155 = _GEN_54 + _T_153; // @[Bitwise.scala 48:55]
-  wire [2:0] _T_157 = _T_151[1:0] + _T_155[1:0]; // @[Bitwise.scala 48:55]
-  wire  _valid_T_97 = io_fwriteData_5_valid & io_fwriteData_5_addr == 5'h8; // @[FRegfile.scala 82:44]
-  wire  _valid_T_99 = io_fwriteData_4_valid & io_fwriteData_4_addr == 5'h8; // @[FRegfile.scala 83:44]
-  wire  _valid_T_101 = io_fwriteData_3_valid & io_fwriteData_3_addr == 5'h8; // @[FRegfile.scala 84:44]
-  wire  _valid_T_103 = io_fwriteData_2_valid & io_fwriteData_2_addr == 5'h8; // @[FRegfile.scala 85:44]
-  wire  _valid_T_105 = io_fwriteData_1_valid & io_fwriteData_1_addr == 5'h8; // @[FRegfile.scala 86:44]
-  wire  _valid_T_107 = io_fwriteData_0_valid & io_fwriteData_0_addr == 5'h8; // @[FRegfile.scala 87:44]
-  wire [5:0] valid_8 = {_valid_T_97,_valid_T_99,_valid_T_101,_valid_T_103,_valid_T_105,_valid_T_107}; // @[Cat.scala 31:58]
-  wire [31:0] _data_T_129 = valid_8[0] ? io_fwriteData_0_data : 32'h0; // @[FRegfile.scala 88:20]
-  wire [31:0] _data_T_131 = valid_8[1] ? io_fwriteData_1_data : 32'h0; // @[FRegfile.scala 89:20]
-  wire [31:0] _data_T_132 = _data_T_129 | _data_T_131; // @[FRegfile.scala 88:59]
-  wire [31:0] _data_T_134 = valid_8[2] ? io_fwriteData_2_data : 32'h0; // @[FRegfile.scala 90:20]
-  wire [31:0] _data_T_135 = _data_T_132 | _data_T_134; // @[FRegfile.scala 89:59]
-  wire [31:0] _data_T_137 = valid_8[3] ? io_fwriteData_3_data : 32'h0; // @[FRegfile.scala 91:20]
-  wire [31:0] _data_T_138 = _data_T_135 | _data_T_137; // @[FRegfile.scala 90:59]
-  wire [31:0] _data_T_140 = valid_8[4] ? io_fwriteData_4_data : 32'h0; // @[FRegfile.scala 92:20]
-  wire [31:0] _data_T_141 = _data_T_138 | _data_T_140; // @[FRegfile.scala 91:59]
-  wire [31:0] _data_T_143 = valid_8[5] ? io_fwriteData_5_data : 32'h0; // @[FRegfile.scala 93:20]
-  wire [31:0] data_8 = _data_T_141 | _data_T_143; // @[FRegfile.scala 92:59]
-  wire  fwriteValid_8 = valid_8 != 6'h0; // @[FRegfile.scala 95:29]
-  wire [1:0] _T_169 = valid_8[1] + valid_8[2]; // @[Bitwise.scala 48:55]
-  wire [1:0] _GEN_55 = {{1'd0}, valid_8[0]}; // @[Bitwise.scala 48:55]
-  wire [2:0] _T_171 = _GEN_55 + _T_169; // @[Bitwise.scala 48:55]
-  wire [1:0] _T_173 = valid_8[4] + valid_8[5]; // @[Bitwise.scala 48:55]
-  wire [1:0] _GEN_56 = {{1'd0}, valid_8[3]}; // @[Bitwise.scala 48:55]
-  wire [2:0] _T_175 = _GEN_56 + _T_173; // @[Bitwise.scala 48:55]
-  wire [2:0] _T_177 = _T_171[1:0] + _T_175[1:0]; // @[Bitwise.scala 48:55]
-  wire  _valid_T_109 = io_fwriteData_5_valid & io_fwriteData_5_addr == 5'h9; // @[FRegfile.scala 82:44]
-  wire  _valid_T_111 = io_fwriteData_4_valid & io_fwriteData_4_addr == 5'h9; // @[FRegfile.scala 83:44]
-  wire  _valid_T_113 = io_fwriteData_3_valid & io_fwriteData_3_addr == 5'h9; // @[FRegfile.scala 84:44]
-  wire  _valid_T_115 = io_fwriteData_2_valid & io_fwriteData_2_addr == 5'h9; // @[FRegfile.scala 85:44]
-  wire  _valid_T_117 = io_fwriteData_1_valid & io_fwriteData_1_addr == 5'h9; // @[FRegfile.scala 86:44]
-  wire  _valid_T_119 = io_fwriteData_0_valid & io_fwriteData_0_addr == 5'h9; // @[FRegfile.scala 87:44]
-  wire [5:0] valid_9 = {_valid_T_109,_valid_T_111,_valid_T_113,_valid_T_115,_valid_T_117,_valid_T_119}; // @[Cat.scala 31:58]
-  wire [31:0] _data_T_145 = valid_9[0] ? io_fwriteData_0_data : 32'h0; // @[FRegfile.scala 88:20]
-  wire [31:0] _data_T_147 = valid_9[1] ? io_fwriteData_1_data : 32'h0; // @[FRegfile.scala 89:20]
-  wire [31:0] _data_T_148 = _data_T_145 | _data_T_147; // @[FRegfile.scala 88:59]
-  wire [31:0] _data_T_150 = valid_9[2] ? io_fwriteData_2_data : 32'h0; // @[FRegfile.scala 90:20]
-  wire [31:0] _data_T_151 = _data_T_148 | _data_T_150; // @[FRegfile.scala 89:59]
-  wire [31:0] _data_T_153 = valid_9[3] ? io_fwriteData_3_data : 32'h0; // @[FRegfile.scala 91:20]
-  wire [31:0] _data_T_154 = _data_T_151 | _data_T_153; // @[FRegfile.scala 90:59]
-  wire [31:0] _data_T_156 = valid_9[4] ? io_fwriteData_4_data : 32'h0; // @[FRegfile.scala 92:20]
-  wire [31:0] _data_T_157 = _data_T_154 | _data_T_156; // @[FRegfile.scala 91:59]
-  wire [31:0] _data_T_159 = valid_9[5] ? io_fwriteData_5_data : 32'h0; // @[FRegfile.scala 93:20]
-  wire [31:0] data_9 = _data_T_157 | _data_T_159; // @[FRegfile.scala 92:59]
-  wire  fwriteValid_9 = valid_9 != 6'h0; // @[FRegfile.scala 95:29]
-  wire [1:0] _T_189 = valid_9[1] + valid_9[2]; // @[Bitwise.scala 48:55]
-  wire [1:0] _GEN_57 = {{1'd0}, valid_9[0]}; // @[Bitwise.scala 48:55]
-  wire [2:0] _T_191 = _GEN_57 + _T_189; // @[Bitwise.scala 48:55]
-  wire [1:0] _T_193 = valid_9[4] + valid_9[5]; // @[Bitwise.scala 48:55]
-  wire [1:0] _GEN_58 = {{1'd0}, valid_9[3]}; // @[Bitwise.scala 48:55]
-  wire [2:0] _T_195 = _GEN_58 + _T_193; // @[Bitwise.scala 48:55]
-  wire [2:0] _T_197 = _T_191[1:0] + _T_195[1:0]; // @[Bitwise.scala 48:55]
-  wire  _valid_T_121 = io_fwriteData_5_valid & io_fwriteData_5_addr == 5'ha; // @[FRegfile.scala 82:44]
-  wire  _valid_T_123 = io_fwriteData_4_valid & io_fwriteData_4_addr == 5'ha; // @[FRegfile.scala 83:44]
-  wire  _valid_T_125 = io_fwriteData_3_valid & io_fwriteData_3_addr == 5'ha; // @[FRegfile.scala 84:44]
-  wire  _valid_T_127 = io_fwriteData_2_valid & io_fwriteData_2_addr == 5'ha; // @[FRegfile.scala 85:44]
-  wire  _valid_T_129 = io_fwriteData_1_valid & io_fwriteData_1_addr == 5'ha; // @[FRegfile.scala 86:44]
-  wire  _valid_T_131 = io_fwriteData_0_valid & io_fwriteData_0_addr == 5'ha; // @[FRegfile.scala 87:44]
-  wire [5:0] valid_10 = {_valid_T_121,_valid_T_123,_valid_T_125,_valid_T_127,_valid_T_129,_valid_T_131}; // @[Cat.scala 31:58]
-  wire [31:0] _data_T_161 = valid_10[0] ? io_fwriteData_0_data : 32'h0; // @[FRegfile.scala 88:20]
-  wire [31:0] _data_T_163 = valid_10[1] ? io_fwriteData_1_data : 32'h0; // @[FRegfile.scala 89:20]
-  wire [31:0] _data_T_164 = _data_T_161 | _data_T_163; // @[FRegfile.scala 88:59]
-  wire [31:0] _data_T_166 = valid_10[2] ? io_fwriteData_2_data : 32'h0; // @[FRegfile.scala 90:20]
-  wire [31:0] _data_T_167 = _data_T_164 | _data_T_166; // @[FRegfile.scala 89:59]
-  wire [31:0] _data_T_169 = valid_10[3] ? io_fwriteData_3_data : 32'h0; // @[FRegfile.scala 91:20]
-  wire [31:0] _data_T_170 = _data_T_167 | _data_T_169; // @[FRegfile.scala 90:59]
-  wire [31:0] _data_T_172 = valid_10[4] ? io_fwriteData_4_data : 32'h0; // @[FRegfile.scala 92:20]
-  wire [31:0] _data_T_173 = _data_T_170 | _data_T_172; // @[FRegfile.scala 91:59]
-  wire [31:0] _data_T_175 = valid_10[5] ? io_fwriteData_5_data : 32'h0; // @[FRegfile.scala 93:20]
-  wire [31:0] data_10 = _data_T_173 | _data_T_175; // @[FRegfile.scala 92:59]
-  wire  fwriteValid_10 = valid_10 != 6'h0; // @[FRegfile.scala 95:29]
-  wire [1:0] _T_209 = valid_10[1] + valid_10[2]; // @[Bitwise.scala 48:55]
-  wire [1:0] _GEN_59 = {{1'd0}, valid_10[0]}; // @[Bitwise.scala 48:55]
-  wire [2:0] _T_211 = _GEN_59 + _T_209; // @[Bitwise.scala 48:55]
-  wire [1:0] _T_213 = valid_10[4] + valid_10[5]; // @[Bitwise.scala 48:55]
-  wire [1:0] _GEN_60 = {{1'd0}, valid_10[3]}; // @[Bitwise.scala 48:55]
-  wire [2:0] _T_215 = _GEN_60 + _T_213; // @[Bitwise.scala 48:55]
-  wire [2:0] _T_217 = _T_211[1:0] + _T_215[1:0]; // @[Bitwise.scala 48:55]
-  wire  _valid_T_133 = io_fwriteData_5_valid & io_fwriteData_5_addr == 5'hb; // @[FRegfile.scala 82:44]
-  wire  _valid_T_135 = io_fwriteData_4_valid & io_fwriteData_4_addr == 5'hb; // @[FRegfile.scala 83:44]
-  wire  _valid_T_137 = io_fwriteData_3_valid & io_fwriteData_3_addr == 5'hb; // @[FRegfile.scala 84:44]
-  wire  _valid_T_139 = io_fwriteData_2_valid & io_fwriteData_2_addr == 5'hb; // @[FRegfile.scala 85:44]
-  wire  _valid_T_141 = io_fwriteData_1_valid & io_fwriteData_1_addr == 5'hb; // @[FRegfile.scala 86:44]
-  wire  _valid_T_143 = io_fwriteData_0_valid & io_fwriteData_0_addr == 5'hb; // @[FRegfile.scala 87:44]
-  wire [5:0] valid_11 = {_valid_T_133,_valid_T_135,_valid_T_137,_valid_T_139,_valid_T_141,_valid_T_143}; // @[Cat.scala 31:58]
-  wire [31:0] _data_T_177 = valid_11[0] ? io_fwriteData_0_data : 32'h0; // @[FRegfile.scala 88:20]
-  wire [31:0] _data_T_179 = valid_11[1] ? io_fwriteData_1_data : 32'h0; // @[FRegfile.scala 89:20]
-  wire [31:0] _data_T_180 = _data_T_177 | _data_T_179; // @[FRegfile.scala 88:59]
-  wire [31:0] _data_T_182 = valid_11[2] ? io_fwriteData_2_data : 32'h0; // @[FRegfile.scala 90:20]
-  wire [31:0] _data_T_183 = _data_T_180 | _data_T_182; // @[FRegfile.scala 89:59]
-  wire [31:0] _data_T_185 = valid_11[3] ? io_fwriteData_3_data : 32'h0; // @[FRegfile.scala 91:20]
-  wire [31:0] _data_T_186 = _data_T_183 | _data_T_185; // @[FRegfile.scala 90:59]
-  wire [31:0] _data_T_188 = valid_11[4] ? io_fwriteData_4_data : 32'h0; // @[FRegfile.scala 92:20]
-  wire [31:0] _data_T_189 = _data_T_186 | _data_T_188; // @[FRegfile.scala 91:59]
-  wire [31:0] _data_T_191 = valid_11[5] ? io_fwriteData_5_data : 32'h0; // @[FRegfile.scala 93:20]
-  wire [31:0] data_11 = _data_T_189 | _data_T_191; // @[FRegfile.scala 92:59]
-  wire  fwriteValid_11 = valid_11 != 6'h0; // @[FRegfile.scala 95:29]
-  wire [1:0] _T_229 = valid_11[1] + valid_11[2]; // @[Bitwise.scala 48:55]
-  wire [1:0] _GEN_61 = {{1'd0}, valid_11[0]}; // @[Bitwise.scala 48:55]
-  wire [2:0] _T_231 = _GEN_61 + _T_229; // @[Bitwise.scala 48:55]
-  wire [1:0] _T_233 = valid_11[4] + valid_11[5]; // @[Bitwise.scala 48:55]
-  wire [1:0] _GEN_62 = {{1'd0}, valid_11[3]}; // @[Bitwise.scala 48:55]
-  wire [2:0] _T_235 = _GEN_62 + _T_233; // @[Bitwise.scala 48:55]
-  wire [2:0] _T_237 = _T_231[1:0] + _T_235[1:0]; // @[Bitwise.scala 48:55]
-  wire  _valid_T_145 = io_fwriteData_5_valid & io_fwriteData_5_addr == 5'hc; // @[FRegfile.scala 82:44]
-  wire  _valid_T_147 = io_fwriteData_4_valid & io_fwriteData_4_addr == 5'hc; // @[FRegfile.scala 83:44]
-  wire  _valid_T_149 = io_fwriteData_3_valid & io_fwriteData_3_addr == 5'hc; // @[FRegfile.scala 84:44]
-  wire  _valid_T_151 = io_fwriteData_2_valid & io_fwriteData_2_addr == 5'hc; // @[FRegfile.scala 85:44]
-  wire  _valid_T_153 = io_fwriteData_1_valid & io_fwriteData_1_addr == 5'hc; // @[FRegfile.scala 86:44]
-  wire  _valid_T_155 = io_fwriteData_0_valid & io_fwriteData_0_addr == 5'hc; // @[FRegfile.scala 87:44]
-  wire [5:0] valid_12 = {_valid_T_145,_valid_T_147,_valid_T_149,_valid_T_151,_valid_T_153,_valid_T_155}; // @[Cat.scala 31:58]
-  wire [31:0] _data_T_193 = valid_12[0] ? io_fwriteData_0_data : 32'h0; // @[FRegfile.scala 88:20]
-  wire [31:0] _data_T_195 = valid_12[1] ? io_fwriteData_1_data : 32'h0; // @[FRegfile.scala 89:20]
-  wire [31:0] _data_T_196 = _data_T_193 | _data_T_195; // @[FRegfile.scala 88:59]
-  wire [31:0] _data_T_198 = valid_12[2] ? io_fwriteData_2_data : 32'h0; // @[FRegfile.scala 90:20]
-  wire [31:0] _data_T_199 = _data_T_196 | _data_T_198; // @[FRegfile.scala 89:59]
-  wire [31:0] _data_T_201 = valid_12[3] ? io_fwriteData_3_data : 32'h0; // @[FRegfile.scala 91:20]
-  wire [31:0] _data_T_202 = _data_T_199 | _data_T_201; // @[FRegfile.scala 90:59]
-  wire [31:0] _data_T_204 = valid_12[4] ? io_fwriteData_4_data : 32'h0; // @[FRegfile.scala 92:20]
-  wire [31:0] _data_T_205 = _data_T_202 | _data_T_204; // @[FRegfile.scala 91:59]
-  wire [31:0] _data_T_207 = valid_12[5] ? io_fwriteData_5_data : 32'h0; // @[FRegfile.scala 93:20]
-  wire [31:0] data_12 = _data_T_205 | _data_T_207; // @[FRegfile.scala 92:59]
-  wire  fwriteValid_12 = valid_12 != 6'h0; // @[FRegfile.scala 95:29]
-  wire [1:0] _T_249 = valid_12[1] + valid_12[2]; // @[Bitwise.scala 48:55]
-  wire [1:0] _GEN_63 = {{1'd0}, valid_12[0]}; // @[Bitwise.scala 48:55]
-  wire [2:0] _T_251 = _GEN_63 + _T_249; // @[Bitwise.scala 48:55]
-  wire [1:0] _T_253 = valid_12[4] + valid_12[5]; // @[Bitwise.scala 48:55]
-  wire [1:0] _GEN_64 = {{1'd0}, valid_12[3]}; // @[Bitwise.scala 48:55]
-  wire [2:0] _T_255 = _GEN_64 + _T_253; // @[Bitwise.scala 48:55]
-  wire [2:0] _T_257 = _T_251[1:0] + _T_255[1:0]; // @[Bitwise.scala 48:55]
-  wire  _valid_T_157 = io_fwriteData_5_valid & io_fwriteData_5_addr == 5'hd; // @[FRegfile.scala 82:44]
-  wire  _valid_T_159 = io_fwriteData_4_valid & io_fwriteData_4_addr == 5'hd; // @[FRegfile.scala 83:44]
-  wire  _valid_T_161 = io_fwriteData_3_valid & io_fwriteData_3_addr == 5'hd; // @[FRegfile.scala 84:44]
-  wire  _valid_T_163 = io_fwriteData_2_valid & io_fwriteData_2_addr == 5'hd; // @[FRegfile.scala 85:44]
-  wire  _valid_T_165 = io_fwriteData_1_valid & io_fwriteData_1_addr == 5'hd; // @[FRegfile.scala 86:44]
-  wire  _valid_T_167 = io_fwriteData_0_valid & io_fwriteData_0_addr == 5'hd; // @[FRegfile.scala 87:44]
-  wire [5:0] valid_13 = {_valid_T_157,_valid_T_159,_valid_T_161,_valid_T_163,_valid_T_165,_valid_T_167}; // @[Cat.scala 31:58]
-  wire [31:0] _data_T_209 = valid_13[0] ? io_fwriteData_0_data : 32'h0; // @[FRegfile.scala 88:20]
-  wire [31:0] _data_T_211 = valid_13[1] ? io_fwriteData_1_data : 32'h0; // @[FRegfile.scala 89:20]
-  wire [31:0] _data_T_212 = _data_T_209 | _data_T_211; // @[FRegfile.scala 88:59]
-  wire [31:0] _data_T_214 = valid_13[2] ? io_fwriteData_2_data : 32'h0; // @[FRegfile.scala 90:20]
-  wire [31:0] _data_T_215 = _data_T_212 | _data_T_214; // @[FRegfile.scala 89:59]
-  wire [31:0] _data_T_217 = valid_13[3] ? io_fwriteData_3_data : 32'h0; // @[FRegfile.scala 91:20]
-  wire [31:0] _data_T_218 = _data_T_215 | _data_T_217; // @[FRegfile.scala 90:59]
-  wire [31:0] _data_T_220 = valid_13[4] ? io_fwriteData_4_data : 32'h0; // @[FRegfile.scala 92:20]
-  wire [31:0] _data_T_221 = _data_T_218 | _data_T_220; // @[FRegfile.scala 91:59]
-  wire [31:0] _data_T_223 = valid_13[5] ? io_fwriteData_5_data : 32'h0; // @[FRegfile.scala 93:20]
-  wire [31:0] data_13 = _data_T_221 | _data_T_223; // @[FRegfile.scala 92:59]
-  wire  fwriteValid_13 = valid_13 != 6'h0; // @[FRegfile.scala 95:29]
-  wire [1:0] _T_269 = valid_13[1] + valid_13[2]; // @[Bitwise.scala 48:55]
-  wire [1:0] _GEN_65 = {{1'd0}, valid_13[0]}; // @[Bitwise.scala 48:55]
-  wire [2:0] _T_271 = _GEN_65 + _T_269; // @[Bitwise.scala 48:55]
-  wire [1:0] _T_273 = valid_13[4] + valid_13[5]; // @[Bitwise.scala 48:55]
-  wire [1:0] _GEN_66 = {{1'd0}, valid_13[3]}; // @[Bitwise.scala 48:55]
-  wire [2:0] _T_275 = _GEN_66 + _T_273; // @[Bitwise.scala 48:55]
-  wire [2:0] _T_277 = _T_271[1:0] + _T_275[1:0]; // @[Bitwise.scala 48:55]
-  wire  _valid_T_169 = io_fwriteData_5_valid & io_fwriteData_5_addr == 5'he; // @[FRegfile.scala 82:44]
-  wire  _valid_T_171 = io_fwriteData_4_valid & io_fwriteData_4_addr == 5'he; // @[FRegfile.scala 83:44]
-  wire  _valid_T_173 = io_fwriteData_3_valid & io_fwriteData_3_addr == 5'he; // @[FRegfile.scala 84:44]
-  wire  _valid_T_175 = io_fwriteData_2_valid & io_fwriteData_2_addr == 5'he; // @[FRegfile.scala 85:44]
-  wire  _valid_T_177 = io_fwriteData_1_valid & io_fwriteData_1_addr == 5'he; // @[FRegfile.scala 86:44]
-  wire  _valid_T_179 = io_fwriteData_0_valid & io_fwriteData_0_addr == 5'he; // @[FRegfile.scala 87:44]
-  wire [5:0] valid_14 = {_valid_T_169,_valid_T_171,_valid_T_173,_valid_T_175,_valid_T_177,_valid_T_179}; // @[Cat.scala 31:58]
-  wire [31:0] _data_T_225 = valid_14[0] ? io_fwriteData_0_data : 32'h0; // @[FRegfile.scala 88:20]
-  wire [31:0] _data_T_227 = valid_14[1] ? io_fwriteData_1_data : 32'h0; // @[FRegfile.scala 89:20]
-  wire [31:0] _data_T_228 = _data_T_225 | _data_T_227; // @[FRegfile.scala 88:59]
-  wire [31:0] _data_T_230 = valid_14[2] ? io_fwriteData_2_data : 32'h0; // @[FRegfile.scala 90:20]
-  wire [31:0] _data_T_231 = _data_T_228 | _data_T_230; // @[FRegfile.scala 89:59]
-  wire [31:0] _data_T_233 = valid_14[3] ? io_fwriteData_3_data : 32'h0; // @[FRegfile.scala 91:20]
-  wire [31:0] _data_T_234 = _data_T_231 | _data_T_233; // @[FRegfile.scala 90:59]
-  wire [31:0] _data_T_236 = valid_14[4] ? io_fwriteData_4_data : 32'h0; // @[FRegfile.scala 92:20]
-  wire [31:0] _data_T_237 = _data_T_234 | _data_T_236; // @[FRegfile.scala 91:59]
-  wire [31:0] _data_T_239 = valid_14[5] ? io_fwriteData_5_data : 32'h0; // @[FRegfile.scala 93:20]
-  wire [31:0] data_14 = _data_T_237 | _data_T_239; // @[FRegfile.scala 92:59]
-  wire  fwriteValid_14 = valid_14 != 6'h0; // @[FRegfile.scala 95:29]
-  wire [1:0] _T_289 = valid_14[1] + valid_14[2]; // @[Bitwise.scala 48:55]
-  wire [1:0] _GEN_67 = {{1'd0}, valid_14[0]}; // @[Bitwise.scala 48:55]
-  wire [2:0] _T_291 = _GEN_67 + _T_289; // @[Bitwise.scala 48:55]
-  wire [1:0] _T_293 = valid_14[4] + valid_14[5]; // @[Bitwise.scala 48:55]
-  wire [1:0] _GEN_68 = {{1'd0}, valid_14[3]}; // @[Bitwise.scala 48:55]
-  wire [2:0] _T_295 = _GEN_68 + _T_293; // @[Bitwise.scala 48:55]
-  wire [2:0] _T_297 = _T_291[1:0] + _T_295[1:0]; // @[Bitwise.scala 48:55]
-  wire  _valid_T_181 = io_fwriteData_5_valid & io_fwriteData_5_addr == 5'hf; // @[FRegfile.scala 82:44]
-  wire  _valid_T_183 = io_fwriteData_4_valid & io_fwriteData_4_addr == 5'hf; // @[FRegfile.scala 83:44]
-  wire  _valid_T_185 = io_fwriteData_3_valid & io_fwriteData_3_addr == 5'hf; // @[FRegfile.scala 84:44]
-  wire  _valid_T_187 = io_fwriteData_2_valid & io_fwriteData_2_addr == 5'hf; // @[FRegfile.scala 85:44]
-  wire  _valid_T_189 = io_fwriteData_1_valid & io_fwriteData_1_addr == 5'hf; // @[FRegfile.scala 86:44]
-  wire  _valid_T_191 = io_fwriteData_0_valid & io_fwriteData_0_addr == 5'hf; // @[FRegfile.scala 87:44]
-  wire [5:0] valid_15 = {_valid_T_181,_valid_T_183,_valid_T_185,_valid_T_187,_valid_T_189,_valid_T_191}; // @[Cat.scala 31:58]
-  wire [31:0] _data_T_241 = valid_15[0] ? io_fwriteData_0_data : 32'h0; // @[FRegfile.scala 88:20]
-  wire [31:0] _data_T_243 = valid_15[1] ? io_fwriteData_1_data : 32'h0; // @[FRegfile.scala 89:20]
-  wire [31:0] _data_T_244 = _data_T_241 | _data_T_243; // @[FRegfile.scala 88:59]
-  wire [31:0] _data_T_246 = valid_15[2] ? io_fwriteData_2_data : 32'h0; // @[FRegfile.scala 90:20]
-  wire [31:0] _data_T_247 = _data_T_244 | _data_T_246; // @[FRegfile.scala 89:59]
-  wire [31:0] _data_T_249 = valid_15[3] ? io_fwriteData_3_data : 32'h0; // @[FRegfile.scala 91:20]
-  wire [31:0] _data_T_250 = _data_T_247 | _data_T_249; // @[FRegfile.scala 90:59]
-  wire [31:0] _data_T_252 = valid_15[4] ? io_fwriteData_4_data : 32'h0; // @[FRegfile.scala 92:20]
-  wire [31:0] _data_T_253 = _data_T_250 | _data_T_252; // @[FRegfile.scala 91:59]
-  wire [31:0] _data_T_255 = valid_15[5] ? io_fwriteData_5_data : 32'h0; // @[FRegfile.scala 93:20]
-  wire [31:0] data_15 = _data_T_253 | _data_T_255; // @[FRegfile.scala 92:59]
-  wire  fwriteValid_15 = valid_15 != 6'h0; // @[FRegfile.scala 95:29]
-  wire [1:0] _T_309 = valid_15[1] + valid_15[2]; // @[Bitwise.scala 48:55]
-  wire [1:0] _GEN_69 = {{1'd0}, valid_15[0]}; // @[Bitwise.scala 48:55]
-  wire [2:0] _T_311 = _GEN_69 + _T_309; // @[Bitwise.scala 48:55]
-  wire [1:0] _T_313 = valid_15[4] + valid_15[5]; // @[Bitwise.scala 48:55]
-  wire [1:0] _GEN_70 = {{1'd0}, valid_15[3]}; // @[Bitwise.scala 48:55]
-  wire [2:0] _T_315 = _GEN_70 + _T_313; // @[Bitwise.scala 48:55]
-  wire [2:0] _T_317 = _T_311[1:0] + _T_315[1:0]; // @[Bitwise.scala 48:55]
-  wire  _valid_T_193 = io_fwriteData_5_valid & io_fwriteData_5_addr == 5'h10; // @[FRegfile.scala 82:44]
-  wire  _valid_T_195 = io_fwriteData_4_valid & io_fwriteData_4_addr == 5'h10; // @[FRegfile.scala 83:44]
-  wire  _valid_T_197 = io_fwriteData_3_valid & io_fwriteData_3_addr == 5'h10; // @[FRegfile.scala 84:44]
-  wire  _valid_T_199 = io_fwriteData_2_valid & io_fwriteData_2_addr == 5'h10; // @[FRegfile.scala 85:44]
-  wire  _valid_T_201 = io_fwriteData_1_valid & io_fwriteData_1_addr == 5'h10; // @[FRegfile.scala 86:44]
-  wire  _valid_T_203 = io_fwriteData_0_valid & io_fwriteData_0_addr == 5'h10; // @[FRegfile.scala 87:44]
-  wire [5:0] valid_16 = {_valid_T_193,_valid_T_195,_valid_T_197,_valid_T_199,_valid_T_201,_valid_T_203}; // @[Cat.scala 31:58]
-  wire [31:0] _data_T_257 = valid_16[0] ? io_fwriteData_0_data : 32'h0; // @[FRegfile.scala 88:20]
-  wire [31:0] _data_T_259 = valid_16[1] ? io_fwriteData_1_data : 32'h0; // @[FRegfile.scala 89:20]
-  wire [31:0] _data_T_260 = _data_T_257 | _data_T_259; // @[FRegfile.scala 88:59]
-  wire [31:0] _data_T_262 = valid_16[2] ? io_fwriteData_2_data : 32'h0; // @[FRegfile.scala 90:20]
-  wire [31:0] _data_T_263 = _data_T_260 | _data_T_262; // @[FRegfile.scala 89:59]
-  wire [31:0] _data_T_265 = valid_16[3] ? io_fwriteData_3_data : 32'h0; // @[FRegfile.scala 91:20]
-  wire [31:0] _data_T_266 = _data_T_263 | _data_T_265; // @[FRegfile.scala 90:59]
-  wire [31:0] _data_T_268 = valid_16[4] ? io_fwriteData_4_data : 32'h0; // @[FRegfile.scala 92:20]
-  wire [31:0] _data_T_269 = _data_T_266 | _data_T_268; // @[FRegfile.scala 91:59]
-  wire [31:0] _data_T_271 = valid_16[5] ? io_fwriteData_5_data : 32'h0; // @[FRegfile.scala 93:20]
-  wire [31:0] data_16 = _data_T_269 | _data_T_271; // @[FRegfile.scala 92:59]
-  wire  fwriteValid_16 = valid_16 != 6'h0; // @[FRegfile.scala 95:29]
-  wire [1:0] _T_329 = valid_16[1] + valid_16[2]; // @[Bitwise.scala 48:55]
-  wire [1:0] _GEN_71 = {{1'd0}, valid_16[0]}; // @[Bitwise.scala 48:55]
-  wire [2:0] _T_331 = _GEN_71 + _T_329; // @[Bitwise.scala 48:55]
-  wire [1:0] _T_333 = valid_16[4] + valid_16[5]; // @[Bitwise.scala 48:55]
-  wire [1:0] _GEN_72 = {{1'd0}, valid_16[3]}; // @[Bitwise.scala 48:55]
-  wire [2:0] _T_335 = _GEN_72 + _T_333; // @[Bitwise.scala 48:55]
-  wire [2:0] _T_337 = _T_331[1:0] + _T_335[1:0]; // @[Bitwise.scala 48:55]
-  wire  _valid_T_205 = io_fwriteData_5_valid & io_fwriteData_5_addr == 5'h11; // @[FRegfile.scala 82:44]
-  wire  _valid_T_207 = io_fwriteData_4_valid & io_fwriteData_4_addr == 5'h11; // @[FRegfile.scala 83:44]
-  wire  _valid_T_209 = io_fwriteData_3_valid & io_fwriteData_3_addr == 5'h11; // @[FRegfile.scala 84:44]
-  wire  _valid_T_211 = io_fwriteData_2_valid & io_fwriteData_2_addr == 5'h11; // @[FRegfile.scala 85:44]
-  wire  _valid_T_213 = io_fwriteData_1_valid & io_fwriteData_1_addr == 5'h11; // @[FRegfile.scala 86:44]
-  wire  _valid_T_215 = io_fwriteData_0_valid & io_fwriteData_0_addr == 5'h11; // @[FRegfile.scala 87:44]
-  wire [5:0] valid_17 = {_valid_T_205,_valid_T_207,_valid_T_209,_valid_T_211,_valid_T_213,_valid_T_215}; // @[Cat.scala 31:58]
-  wire [31:0] _data_T_273 = valid_17[0] ? io_fwriteData_0_data : 32'h0; // @[FRegfile.scala 88:20]
-  wire [31:0] _data_T_275 = valid_17[1] ? io_fwriteData_1_data : 32'h0; // @[FRegfile.scala 89:20]
-  wire [31:0] _data_T_276 = _data_T_273 | _data_T_275; // @[FRegfile.scala 88:59]
-  wire [31:0] _data_T_278 = valid_17[2] ? io_fwriteData_2_data : 32'h0; // @[FRegfile.scala 90:20]
-  wire [31:0] _data_T_279 = _data_T_276 | _data_T_278; // @[FRegfile.scala 89:59]
-  wire [31:0] _data_T_281 = valid_17[3] ? io_fwriteData_3_data : 32'h0; // @[FRegfile.scala 91:20]
-  wire [31:0] _data_T_282 = _data_T_279 | _data_T_281; // @[FRegfile.scala 90:59]
-  wire [31:0] _data_T_284 = valid_17[4] ? io_fwriteData_4_data : 32'h0; // @[FRegfile.scala 92:20]
-  wire [31:0] _data_T_285 = _data_T_282 | _data_T_284; // @[FRegfile.scala 91:59]
-  wire [31:0] _data_T_287 = valid_17[5] ? io_fwriteData_5_data : 32'h0; // @[FRegfile.scala 93:20]
-  wire [31:0] data_17 = _data_T_285 | _data_T_287; // @[FRegfile.scala 92:59]
-  wire  fwriteValid_17 = valid_17 != 6'h0; // @[FRegfile.scala 95:29]
-  wire [1:0] _T_349 = valid_17[1] + valid_17[2]; // @[Bitwise.scala 48:55]
-  wire [1:0] _GEN_73 = {{1'd0}, valid_17[0]}; // @[Bitwise.scala 48:55]
-  wire [2:0] _T_351 = _GEN_73 + _T_349; // @[Bitwise.scala 48:55]
-  wire [1:0] _T_353 = valid_17[4] + valid_17[5]; // @[Bitwise.scala 48:55]
-  wire [1:0] _GEN_74 = {{1'd0}, valid_17[3]}; // @[Bitwise.scala 48:55]
-  wire [2:0] _T_355 = _GEN_74 + _T_353; // @[Bitwise.scala 48:55]
-  wire [2:0] _T_357 = _T_351[1:0] + _T_355[1:0]; // @[Bitwise.scala 48:55]
-  wire  _valid_T_217 = io_fwriteData_5_valid & io_fwriteData_5_addr == 5'h12; // @[FRegfile.scala 82:44]
-  wire  _valid_T_219 = io_fwriteData_4_valid & io_fwriteData_4_addr == 5'h12; // @[FRegfile.scala 83:44]
-  wire  _valid_T_221 = io_fwriteData_3_valid & io_fwriteData_3_addr == 5'h12; // @[FRegfile.scala 84:44]
-  wire  _valid_T_223 = io_fwriteData_2_valid & io_fwriteData_2_addr == 5'h12; // @[FRegfile.scala 85:44]
-  wire  _valid_T_225 = io_fwriteData_1_valid & io_fwriteData_1_addr == 5'h12; // @[FRegfile.scala 86:44]
-  wire  _valid_T_227 = io_fwriteData_0_valid & io_fwriteData_0_addr == 5'h12; // @[FRegfile.scala 87:44]
-  wire [5:0] valid_18 = {_valid_T_217,_valid_T_219,_valid_T_221,_valid_T_223,_valid_T_225,_valid_T_227}; // @[Cat.scala 31:58]
-  wire [31:0] _data_T_289 = valid_18[0] ? io_fwriteData_0_data : 32'h0; // @[FRegfile.scala 88:20]
-  wire [31:0] _data_T_291 = valid_18[1] ? io_fwriteData_1_data : 32'h0; // @[FRegfile.scala 89:20]
-  wire [31:0] _data_T_292 = _data_T_289 | _data_T_291; // @[FRegfile.scala 88:59]
-  wire [31:0] _data_T_294 = valid_18[2] ? io_fwriteData_2_data : 32'h0; // @[FRegfile.scala 90:20]
-  wire [31:0] _data_T_295 = _data_T_292 | _data_T_294; // @[FRegfile.scala 89:59]
-  wire [31:0] _data_T_297 = valid_18[3] ? io_fwriteData_3_data : 32'h0; // @[FRegfile.scala 91:20]
-  wire [31:0] _data_T_298 = _data_T_295 | _data_T_297; // @[FRegfile.scala 90:59]
-  wire [31:0] _data_T_300 = valid_18[4] ? io_fwriteData_4_data : 32'h0; // @[FRegfile.scala 92:20]
-  wire [31:0] _data_T_301 = _data_T_298 | _data_T_300; // @[FRegfile.scala 91:59]
-  wire [31:0] _data_T_303 = valid_18[5] ? io_fwriteData_5_data : 32'h0; // @[FRegfile.scala 93:20]
-  wire [31:0] data_18 = _data_T_301 | _data_T_303; // @[FRegfile.scala 92:59]
-  wire  fwriteValid_18 = valid_18 != 6'h0; // @[FRegfile.scala 95:29]
-  wire [1:0] _T_369 = valid_18[1] + valid_18[2]; // @[Bitwise.scala 48:55]
-  wire [1:0] _GEN_75 = {{1'd0}, valid_18[0]}; // @[Bitwise.scala 48:55]
-  wire [2:0] _T_371 = _GEN_75 + _T_369; // @[Bitwise.scala 48:55]
-  wire [1:0] _T_373 = valid_18[4] + valid_18[5]; // @[Bitwise.scala 48:55]
-  wire [1:0] _GEN_76 = {{1'd0}, valid_18[3]}; // @[Bitwise.scala 48:55]
-  wire [2:0] _T_375 = _GEN_76 + _T_373; // @[Bitwise.scala 48:55]
-  wire [2:0] _T_377 = _T_371[1:0] + _T_375[1:0]; // @[Bitwise.scala 48:55]
-  wire  _valid_T_229 = io_fwriteData_5_valid & io_fwriteData_5_addr == 5'h13; // @[FRegfile.scala 82:44]
-  wire  _valid_T_231 = io_fwriteData_4_valid & io_fwriteData_4_addr == 5'h13; // @[FRegfile.scala 83:44]
-  wire  _valid_T_233 = io_fwriteData_3_valid & io_fwriteData_3_addr == 5'h13; // @[FRegfile.scala 84:44]
-  wire  _valid_T_235 = io_fwriteData_2_valid & io_fwriteData_2_addr == 5'h13; // @[FRegfile.scala 85:44]
-  wire  _valid_T_237 = io_fwriteData_1_valid & io_fwriteData_1_addr == 5'h13; // @[FRegfile.scala 86:44]
-  wire  _valid_T_239 = io_fwriteData_0_valid & io_fwriteData_0_addr == 5'h13; // @[FRegfile.scala 87:44]
-  wire [5:0] valid_19 = {_valid_T_229,_valid_T_231,_valid_T_233,_valid_T_235,_valid_T_237,_valid_T_239}; // @[Cat.scala 31:58]
-  wire [31:0] _data_T_305 = valid_19[0] ? io_fwriteData_0_data : 32'h0; // @[FRegfile.scala 88:20]
-  wire [31:0] _data_T_307 = valid_19[1] ? io_fwriteData_1_data : 32'h0; // @[FRegfile.scala 89:20]
-  wire [31:0] _data_T_308 = _data_T_305 | _data_T_307; // @[FRegfile.scala 88:59]
-  wire [31:0] _data_T_310 = valid_19[2] ? io_fwriteData_2_data : 32'h0; // @[FRegfile.scala 90:20]
-  wire [31:0] _data_T_311 = _data_T_308 | _data_T_310; // @[FRegfile.scala 89:59]
-  wire [31:0] _data_T_313 = valid_19[3] ? io_fwriteData_3_data : 32'h0; // @[FRegfile.scala 91:20]
-  wire [31:0] _data_T_314 = _data_T_311 | _data_T_313; // @[FRegfile.scala 90:59]
-  wire [31:0] _data_T_316 = valid_19[4] ? io_fwriteData_4_data : 32'h0; // @[FRegfile.scala 92:20]
-  wire [31:0] _data_T_317 = _data_T_314 | _data_T_316; // @[FRegfile.scala 91:59]
-  wire [31:0] _data_T_319 = valid_19[5] ? io_fwriteData_5_data : 32'h0; // @[FRegfile.scala 93:20]
-  wire [31:0] data_19 = _data_T_317 | _data_T_319; // @[FRegfile.scala 92:59]
-  wire  fwriteValid_19 = valid_19 != 6'h0; // @[FRegfile.scala 95:29]
-  wire [1:0] _T_389 = valid_19[1] + valid_19[2]; // @[Bitwise.scala 48:55]
-  wire [1:0] _GEN_77 = {{1'd0}, valid_19[0]}; // @[Bitwise.scala 48:55]
-  wire [2:0] _T_391 = _GEN_77 + _T_389; // @[Bitwise.scala 48:55]
-  wire [1:0] _T_393 = valid_19[4] + valid_19[5]; // @[Bitwise.scala 48:55]
-  wire [1:0] _GEN_78 = {{1'd0}, valid_19[3]}; // @[Bitwise.scala 48:55]
-  wire [2:0] _T_395 = _GEN_78 + _T_393; // @[Bitwise.scala 48:55]
-  wire [2:0] _T_397 = _T_391[1:0] + _T_395[1:0]; // @[Bitwise.scala 48:55]
-  wire  _valid_T_241 = io_fwriteData_5_valid & io_fwriteData_5_addr == 5'h14; // @[FRegfile.scala 82:44]
-  wire  _valid_T_243 = io_fwriteData_4_valid & io_fwriteData_4_addr == 5'h14; // @[FRegfile.scala 83:44]
-  wire  _valid_T_245 = io_fwriteData_3_valid & io_fwriteData_3_addr == 5'h14; // @[FRegfile.scala 84:44]
-  wire  _valid_T_247 = io_fwriteData_2_valid & io_fwriteData_2_addr == 5'h14; // @[FRegfile.scala 85:44]
-  wire  _valid_T_249 = io_fwriteData_1_valid & io_fwriteData_1_addr == 5'h14; // @[FRegfile.scala 86:44]
-  wire  _valid_T_251 = io_fwriteData_0_valid & io_fwriteData_0_addr == 5'h14; // @[FRegfile.scala 87:44]
-  wire [5:0] valid_20 = {_valid_T_241,_valid_T_243,_valid_T_245,_valid_T_247,_valid_T_249,_valid_T_251}; // @[Cat.scala 31:58]
-  wire [31:0] _data_T_321 = valid_20[0] ? io_fwriteData_0_data : 32'h0; // @[FRegfile.scala 88:20]
-  wire [31:0] _data_T_323 = valid_20[1] ? io_fwriteData_1_data : 32'h0; // @[FRegfile.scala 89:20]
-  wire [31:0] _data_T_324 = _data_T_321 | _data_T_323; // @[FRegfile.scala 88:59]
-  wire [31:0] _data_T_326 = valid_20[2] ? io_fwriteData_2_data : 32'h0; // @[FRegfile.scala 90:20]
-  wire [31:0] _data_T_327 = _data_T_324 | _data_T_326; // @[FRegfile.scala 89:59]
-  wire [31:0] _data_T_329 = valid_20[3] ? io_fwriteData_3_data : 32'h0; // @[FRegfile.scala 91:20]
-  wire [31:0] _data_T_330 = _data_T_327 | _data_T_329; // @[FRegfile.scala 90:59]
-  wire [31:0] _data_T_332 = valid_20[4] ? io_fwriteData_4_data : 32'h0; // @[FRegfile.scala 92:20]
-  wire [31:0] _data_T_333 = _data_T_330 | _data_T_332; // @[FRegfile.scala 91:59]
-  wire [31:0] _data_T_335 = valid_20[5] ? io_fwriteData_5_data : 32'h0; // @[FRegfile.scala 93:20]
-  wire [31:0] data_20 = _data_T_333 | _data_T_335; // @[FRegfile.scala 92:59]
-  wire  fwriteValid_20 = valid_20 != 6'h0; // @[FRegfile.scala 95:29]
-  wire [1:0] _T_409 = valid_20[1] + valid_20[2]; // @[Bitwise.scala 48:55]
-  wire [1:0] _GEN_79 = {{1'd0}, valid_20[0]}; // @[Bitwise.scala 48:55]
-  wire [2:0] _T_411 = _GEN_79 + _T_409; // @[Bitwise.scala 48:55]
-  wire [1:0] _T_413 = valid_20[4] + valid_20[5]; // @[Bitwise.scala 48:55]
-  wire [1:0] _GEN_80 = {{1'd0}, valid_20[3]}; // @[Bitwise.scala 48:55]
-  wire [2:0] _T_415 = _GEN_80 + _T_413; // @[Bitwise.scala 48:55]
-  wire [2:0] _T_417 = _T_411[1:0] + _T_415[1:0]; // @[Bitwise.scala 48:55]
-  wire  _valid_T_253 = io_fwriteData_5_valid & io_fwriteData_5_addr == 5'h15; // @[FRegfile.scala 82:44]
-  wire  _valid_T_255 = io_fwriteData_4_valid & io_fwriteData_4_addr == 5'h15; // @[FRegfile.scala 83:44]
-  wire  _valid_T_257 = io_fwriteData_3_valid & io_fwriteData_3_addr == 5'h15; // @[FRegfile.scala 84:44]
-  wire  _valid_T_259 = io_fwriteData_2_valid & io_fwriteData_2_addr == 5'h15; // @[FRegfile.scala 85:44]
-  wire  _valid_T_261 = io_fwriteData_1_valid & io_fwriteData_1_addr == 5'h15; // @[FRegfile.scala 86:44]
-  wire  _valid_T_263 = io_fwriteData_0_valid & io_fwriteData_0_addr == 5'h15; // @[FRegfile.scala 87:44]
-  wire [5:0] valid_21 = {_valid_T_253,_valid_T_255,_valid_T_257,_valid_T_259,_valid_T_261,_valid_T_263}; // @[Cat.scala 31:58]
-  wire [31:0] _data_T_337 = valid_21[0] ? io_fwriteData_0_data : 32'h0; // @[FRegfile.scala 88:20]
-  wire [31:0] _data_T_339 = valid_21[1] ? io_fwriteData_1_data : 32'h0; // @[FRegfile.scala 89:20]
-  wire [31:0] _data_T_340 = _data_T_337 | _data_T_339; // @[FRegfile.scala 88:59]
-  wire [31:0] _data_T_342 = valid_21[2] ? io_fwriteData_2_data : 32'h0; // @[FRegfile.scala 90:20]
-  wire [31:0] _data_T_343 = _data_T_340 | _data_T_342; // @[FRegfile.scala 89:59]
-  wire [31:0] _data_T_345 = valid_21[3] ? io_fwriteData_3_data : 32'h0; // @[FRegfile.scala 91:20]
-  wire [31:0] _data_T_346 = _data_T_343 | _data_T_345; // @[FRegfile.scala 90:59]
-  wire [31:0] _data_T_348 = valid_21[4] ? io_fwriteData_4_data : 32'h0; // @[FRegfile.scala 92:20]
-  wire [31:0] _data_T_349 = _data_T_346 | _data_T_348; // @[FRegfile.scala 91:59]
-  wire [31:0] _data_T_351 = valid_21[5] ? io_fwriteData_5_data : 32'h0; // @[FRegfile.scala 93:20]
-  wire [31:0] data_21 = _data_T_349 | _data_T_351; // @[FRegfile.scala 92:59]
-  wire  fwriteValid_21 = valid_21 != 6'h0; // @[FRegfile.scala 95:29]
-  wire [1:0] _T_429 = valid_21[1] + valid_21[2]; // @[Bitwise.scala 48:55]
-  wire [1:0] _GEN_81 = {{1'd0}, valid_21[0]}; // @[Bitwise.scala 48:55]
-  wire [2:0] _T_431 = _GEN_81 + _T_429; // @[Bitwise.scala 48:55]
-  wire [1:0] _T_433 = valid_21[4] + valid_21[5]; // @[Bitwise.scala 48:55]
-  wire [1:0] _GEN_82 = {{1'd0}, valid_21[3]}; // @[Bitwise.scala 48:55]
-  wire [2:0] _T_435 = _GEN_82 + _T_433; // @[Bitwise.scala 48:55]
-  wire [2:0] _T_437 = _T_431[1:0] + _T_435[1:0]; // @[Bitwise.scala 48:55]
-  wire  _valid_T_265 = io_fwriteData_5_valid & io_fwriteData_5_addr == 5'h16; // @[FRegfile.scala 82:44]
-  wire  _valid_T_267 = io_fwriteData_4_valid & io_fwriteData_4_addr == 5'h16; // @[FRegfile.scala 83:44]
-  wire  _valid_T_269 = io_fwriteData_3_valid & io_fwriteData_3_addr == 5'h16; // @[FRegfile.scala 84:44]
-  wire  _valid_T_271 = io_fwriteData_2_valid & io_fwriteData_2_addr == 5'h16; // @[FRegfile.scala 85:44]
-  wire  _valid_T_273 = io_fwriteData_1_valid & io_fwriteData_1_addr == 5'h16; // @[FRegfile.scala 86:44]
-  wire  _valid_T_275 = io_fwriteData_0_valid & io_fwriteData_0_addr == 5'h16; // @[FRegfile.scala 87:44]
-  wire [5:0] valid_22 = {_valid_T_265,_valid_T_267,_valid_T_269,_valid_T_271,_valid_T_273,_valid_T_275}; // @[Cat.scala 31:58]
-  wire [31:0] _data_T_353 = valid_22[0] ? io_fwriteData_0_data : 32'h0; // @[FRegfile.scala 88:20]
-  wire [31:0] _data_T_355 = valid_22[1] ? io_fwriteData_1_data : 32'h0; // @[FRegfile.scala 89:20]
-  wire [31:0] _data_T_356 = _data_T_353 | _data_T_355; // @[FRegfile.scala 88:59]
-  wire [31:0] _data_T_358 = valid_22[2] ? io_fwriteData_2_data : 32'h0; // @[FRegfile.scala 90:20]
-  wire [31:0] _data_T_359 = _data_T_356 | _data_T_358; // @[FRegfile.scala 89:59]
-  wire [31:0] _data_T_361 = valid_22[3] ? io_fwriteData_3_data : 32'h0; // @[FRegfile.scala 91:20]
-  wire [31:0] _data_T_362 = _data_T_359 | _data_T_361; // @[FRegfile.scala 90:59]
-  wire [31:0] _data_T_364 = valid_22[4] ? io_fwriteData_4_data : 32'h0; // @[FRegfile.scala 92:20]
-  wire [31:0] _data_T_365 = _data_T_362 | _data_T_364; // @[FRegfile.scala 91:59]
-  wire [31:0] _data_T_367 = valid_22[5] ? io_fwriteData_5_data : 32'h0; // @[FRegfile.scala 93:20]
-  wire [31:0] data_22 = _data_T_365 | _data_T_367; // @[FRegfile.scala 92:59]
-  wire  fwriteValid_22 = valid_22 != 6'h0; // @[FRegfile.scala 95:29]
-  wire [1:0] _T_449 = valid_22[1] + valid_22[2]; // @[Bitwise.scala 48:55]
-  wire [1:0] _GEN_83 = {{1'd0}, valid_22[0]}; // @[Bitwise.scala 48:55]
-  wire [2:0] _T_451 = _GEN_83 + _T_449; // @[Bitwise.scala 48:55]
-  wire [1:0] _T_453 = valid_22[4] + valid_22[5]; // @[Bitwise.scala 48:55]
-  wire [1:0] _GEN_84 = {{1'd0}, valid_22[3]}; // @[Bitwise.scala 48:55]
-  wire [2:0] _T_455 = _GEN_84 + _T_453; // @[Bitwise.scala 48:55]
-  wire [2:0] _T_457 = _T_451[1:0] + _T_455[1:0]; // @[Bitwise.scala 48:55]
-  wire  _valid_T_277 = io_fwriteData_5_valid & io_fwriteData_5_addr == 5'h17; // @[FRegfile.scala 82:44]
-  wire  _valid_T_279 = io_fwriteData_4_valid & io_fwriteData_4_addr == 5'h17; // @[FRegfile.scala 83:44]
-  wire  _valid_T_281 = io_fwriteData_3_valid & io_fwriteData_3_addr == 5'h17; // @[FRegfile.scala 84:44]
-  wire  _valid_T_283 = io_fwriteData_2_valid & io_fwriteData_2_addr == 5'h17; // @[FRegfile.scala 85:44]
-  wire  _valid_T_285 = io_fwriteData_1_valid & io_fwriteData_1_addr == 5'h17; // @[FRegfile.scala 86:44]
-  wire  _valid_T_287 = io_fwriteData_0_valid & io_fwriteData_0_addr == 5'h17; // @[FRegfile.scala 87:44]
-  wire [5:0] valid_23 = {_valid_T_277,_valid_T_279,_valid_T_281,_valid_T_283,_valid_T_285,_valid_T_287}; // @[Cat.scala 31:58]
-  wire [31:0] _data_T_369 = valid_23[0] ? io_fwriteData_0_data : 32'h0; // @[FRegfile.scala 88:20]
-  wire [31:0] _data_T_371 = valid_23[1] ? io_fwriteData_1_data : 32'h0; // @[FRegfile.scala 89:20]
-  wire [31:0] _data_T_372 = _data_T_369 | _data_T_371; // @[FRegfile.scala 88:59]
-  wire [31:0] _data_T_374 = valid_23[2] ? io_fwriteData_2_data : 32'h0; // @[FRegfile.scala 90:20]
-  wire [31:0] _data_T_375 = _data_T_372 | _data_T_374; // @[FRegfile.scala 89:59]
-  wire [31:0] _data_T_377 = valid_23[3] ? io_fwriteData_3_data : 32'h0; // @[FRegfile.scala 91:20]
-  wire [31:0] _data_T_378 = _data_T_375 | _data_T_377; // @[FRegfile.scala 90:59]
-  wire [31:0] _data_T_380 = valid_23[4] ? io_fwriteData_4_data : 32'h0; // @[FRegfile.scala 92:20]
-  wire [31:0] _data_T_381 = _data_T_378 | _data_T_380; // @[FRegfile.scala 91:59]
-  wire [31:0] _data_T_383 = valid_23[5] ? io_fwriteData_5_data : 32'h0; // @[FRegfile.scala 93:20]
-  wire [31:0] data_23 = _data_T_381 | _data_T_383; // @[FRegfile.scala 92:59]
-  wire  fwriteValid_23 = valid_23 != 6'h0; // @[FRegfile.scala 95:29]
-  wire [1:0] _T_469 = valid_23[1] + valid_23[2]; // @[Bitwise.scala 48:55]
-  wire [1:0] _GEN_85 = {{1'd0}, valid_23[0]}; // @[Bitwise.scala 48:55]
-  wire [2:0] _T_471 = _GEN_85 + _T_469; // @[Bitwise.scala 48:55]
-  wire [1:0] _T_473 = valid_23[4] + valid_23[5]; // @[Bitwise.scala 48:55]
-  wire [1:0] _GEN_86 = {{1'd0}, valid_23[3]}; // @[Bitwise.scala 48:55]
-  wire [2:0] _T_475 = _GEN_86 + _T_473; // @[Bitwise.scala 48:55]
-  wire [2:0] _T_477 = _T_471[1:0] + _T_475[1:0]; // @[Bitwise.scala 48:55]
-  wire  _valid_T_289 = io_fwriteData_5_valid & io_fwriteData_5_addr == 5'h18; // @[FRegfile.scala 82:44]
-  wire  _valid_T_291 = io_fwriteData_4_valid & io_fwriteData_4_addr == 5'h18; // @[FRegfile.scala 83:44]
-  wire  _valid_T_293 = io_fwriteData_3_valid & io_fwriteData_3_addr == 5'h18; // @[FRegfile.scala 84:44]
-  wire  _valid_T_295 = io_fwriteData_2_valid & io_fwriteData_2_addr == 5'h18; // @[FRegfile.scala 85:44]
-  wire  _valid_T_297 = io_fwriteData_1_valid & io_fwriteData_1_addr == 5'h18; // @[FRegfile.scala 86:44]
-  wire  _valid_T_299 = io_fwriteData_0_valid & io_fwriteData_0_addr == 5'h18; // @[FRegfile.scala 87:44]
-  wire [5:0] valid_24 = {_valid_T_289,_valid_T_291,_valid_T_293,_valid_T_295,_valid_T_297,_valid_T_299}; // @[Cat.scala 31:58]
-  wire [31:0] _data_T_385 = valid_24[0] ? io_fwriteData_0_data : 32'h0; // @[FRegfile.scala 88:20]
-  wire [31:0] _data_T_387 = valid_24[1] ? io_fwriteData_1_data : 32'h0; // @[FRegfile.scala 89:20]
-  wire [31:0] _data_T_388 = _data_T_385 | _data_T_387; // @[FRegfile.scala 88:59]
-  wire [31:0] _data_T_390 = valid_24[2] ? io_fwriteData_2_data : 32'h0; // @[FRegfile.scala 90:20]
-  wire [31:0] _data_T_391 = _data_T_388 | _data_T_390; // @[FRegfile.scala 89:59]
-  wire [31:0] _data_T_393 = valid_24[3] ? io_fwriteData_3_data : 32'h0; // @[FRegfile.scala 91:20]
-  wire [31:0] _data_T_394 = _data_T_391 | _data_T_393; // @[FRegfile.scala 90:59]
-  wire [31:0] _data_T_396 = valid_24[4] ? io_fwriteData_4_data : 32'h0; // @[FRegfile.scala 92:20]
-  wire [31:0] _data_T_397 = _data_T_394 | _data_T_396; // @[FRegfile.scala 91:59]
-  wire [31:0] _data_T_399 = valid_24[5] ? io_fwriteData_5_data : 32'h0; // @[FRegfile.scala 93:20]
-  wire [31:0] data_24 = _data_T_397 | _data_T_399; // @[FRegfile.scala 92:59]
-  wire  fwriteValid_24 = valid_24 != 6'h0; // @[FRegfile.scala 95:29]
-  wire [1:0] _T_489 = valid_24[1] + valid_24[2]; // @[Bitwise.scala 48:55]
-  wire [1:0] _GEN_87 = {{1'd0}, valid_24[0]}; // @[Bitwise.scala 48:55]
-  wire [2:0] _T_491 = _GEN_87 + _T_489; // @[Bitwise.scala 48:55]
-  wire [1:0] _T_493 = valid_24[4] + valid_24[5]; // @[Bitwise.scala 48:55]
-  wire [1:0] _GEN_88 = {{1'd0}, valid_24[3]}; // @[Bitwise.scala 48:55]
-  wire [2:0] _T_495 = _GEN_88 + _T_493; // @[Bitwise.scala 48:55]
-  wire [2:0] _T_497 = _T_491[1:0] + _T_495[1:0]; // @[Bitwise.scala 48:55]
-  wire  _valid_T_301 = io_fwriteData_5_valid & io_fwriteData_5_addr == 5'h19; // @[FRegfile.scala 82:44]
-  wire  _valid_T_303 = io_fwriteData_4_valid & io_fwriteData_4_addr == 5'h19; // @[FRegfile.scala 83:44]
-  wire  _valid_T_305 = io_fwriteData_3_valid & io_fwriteData_3_addr == 5'h19; // @[FRegfile.scala 84:44]
-  wire  _valid_T_307 = io_fwriteData_2_valid & io_fwriteData_2_addr == 5'h19; // @[FRegfile.scala 85:44]
-  wire  _valid_T_309 = io_fwriteData_1_valid & io_fwriteData_1_addr == 5'h19; // @[FRegfile.scala 86:44]
-  wire  _valid_T_311 = io_fwriteData_0_valid & io_fwriteData_0_addr == 5'h19; // @[FRegfile.scala 87:44]
-  wire [5:0] valid_25 = {_valid_T_301,_valid_T_303,_valid_T_305,_valid_T_307,_valid_T_309,_valid_T_311}; // @[Cat.scala 31:58]
-  wire [31:0] _data_T_401 = valid_25[0] ? io_fwriteData_0_data : 32'h0; // @[FRegfile.scala 88:20]
-  wire [31:0] _data_T_403 = valid_25[1] ? io_fwriteData_1_data : 32'h0; // @[FRegfile.scala 89:20]
-  wire [31:0] _data_T_404 = _data_T_401 | _data_T_403; // @[FRegfile.scala 88:59]
-  wire [31:0] _data_T_406 = valid_25[2] ? io_fwriteData_2_data : 32'h0; // @[FRegfile.scala 90:20]
-  wire [31:0] _data_T_407 = _data_T_404 | _data_T_406; // @[FRegfile.scala 89:59]
-  wire [31:0] _data_T_409 = valid_25[3] ? io_fwriteData_3_data : 32'h0; // @[FRegfile.scala 91:20]
-  wire [31:0] _data_T_410 = _data_T_407 | _data_T_409; // @[FRegfile.scala 90:59]
-  wire [31:0] _data_T_412 = valid_25[4] ? io_fwriteData_4_data : 32'h0; // @[FRegfile.scala 92:20]
-  wire [31:0] _data_T_413 = _data_T_410 | _data_T_412; // @[FRegfile.scala 91:59]
-  wire [31:0] _data_T_415 = valid_25[5] ? io_fwriteData_5_data : 32'h0; // @[FRegfile.scala 93:20]
-  wire [31:0] data_25 = _data_T_413 | _data_T_415; // @[FRegfile.scala 92:59]
-  wire  fwriteValid_25 = valid_25 != 6'h0; // @[FRegfile.scala 95:29]
-  wire [1:0] _T_509 = valid_25[1] + valid_25[2]; // @[Bitwise.scala 48:55]
-  wire [1:0] _GEN_89 = {{1'd0}, valid_25[0]}; // @[Bitwise.scala 48:55]
-  wire [2:0] _T_511 = _GEN_89 + _T_509; // @[Bitwise.scala 48:55]
-  wire [1:0] _T_513 = valid_25[4] + valid_25[5]; // @[Bitwise.scala 48:55]
-  wire [1:0] _GEN_90 = {{1'd0}, valid_25[3]}; // @[Bitwise.scala 48:55]
-  wire [2:0] _T_515 = _GEN_90 + _T_513; // @[Bitwise.scala 48:55]
-  wire [2:0] _T_517 = _T_511[1:0] + _T_515[1:0]; // @[Bitwise.scala 48:55]
-  wire  _valid_T_313 = io_fwriteData_5_valid & io_fwriteData_5_addr == 5'h1a; // @[FRegfile.scala 82:44]
-  wire  _valid_T_315 = io_fwriteData_4_valid & io_fwriteData_4_addr == 5'h1a; // @[FRegfile.scala 83:44]
-  wire  _valid_T_317 = io_fwriteData_3_valid & io_fwriteData_3_addr == 5'h1a; // @[FRegfile.scala 84:44]
-  wire  _valid_T_319 = io_fwriteData_2_valid & io_fwriteData_2_addr == 5'h1a; // @[FRegfile.scala 85:44]
-  wire  _valid_T_321 = io_fwriteData_1_valid & io_fwriteData_1_addr == 5'h1a; // @[FRegfile.scala 86:44]
-  wire  _valid_T_323 = io_fwriteData_0_valid & io_fwriteData_0_addr == 5'h1a; // @[FRegfile.scala 87:44]
-  wire [5:0] valid_26 = {_valid_T_313,_valid_T_315,_valid_T_317,_valid_T_319,_valid_T_321,_valid_T_323}; // @[Cat.scala 31:58]
-  wire [31:0] _data_T_417 = valid_26[0] ? io_fwriteData_0_data : 32'h0; // @[FRegfile.scala 88:20]
-  wire [31:0] _data_T_419 = valid_26[1] ? io_fwriteData_1_data : 32'h0; // @[FRegfile.scala 89:20]
-  wire [31:0] _data_T_420 = _data_T_417 | _data_T_419; // @[FRegfile.scala 88:59]
-  wire [31:0] _data_T_422 = valid_26[2] ? io_fwriteData_2_data : 32'h0; // @[FRegfile.scala 90:20]
-  wire [31:0] _data_T_423 = _data_T_420 | _data_T_422; // @[FRegfile.scala 89:59]
-  wire [31:0] _data_T_425 = valid_26[3] ? io_fwriteData_3_data : 32'h0; // @[FRegfile.scala 91:20]
-  wire [31:0] _data_T_426 = _data_T_423 | _data_T_425; // @[FRegfile.scala 90:59]
-  wire [31:0] _data_T_428 = valid_26[4] ? io_fwriteData_4_data : 32'h0; // @[FRegfile.scala 92:20]
-  wire [31:0] _data_T_429 = _data_T_426 | _data_T_428; // @[FRegfile.scala 91:59]
-  wire [31:0] _data_T_431 = valid_26[5] ? io_fwriteData_5_data : 32'h0; // @[FRegfile.scala 93:20]
-  wire [31:0] data_26 = _data_T_429 | _data_T_431; // @[FRegfile.scala 92:59]
-  wire  fwriteValid_26 = valid_26 != 6'h0; // @[FRegfile.scala 95:29]
-  wire [1:0] _T_529 = valid_26[1] + valid_26[2]; // @[Bitwise.scala 48:55]
-  wire [1:0] _GEN_91 = {{1'd0}, valid_26[0]}; // @[Bitwise.scala 48:55]
-  wire [2:0] _T_531 = _GEN_91 + _T_529; // @[Bitwise.scala 48:55]
-  wire [1:0] _T_533 = valid_26[4] + valid_26[5]; // @[Bitwise.scala 48:55]
-  wire [1:0] _GEN_92 = {{1'd0}, valid_26[3]}; // @[Bitwise.scala 48:55]
-  wire [2:0] _T_535 = _GEN_92 + _T_533; // @[Bitwise.scala 48:55]
-  wire [2:0] _T_537 = _T_531[1:0] + _T_535[1:0]; // @[Bitwise.scala 48:55]
-  wire  _valid_T_325 = io_fwriteData_5_valid & io_fwriteData_5_addr == 5'h1b; // @[FRegfile.scala 82:44]
-  wire  _valid_T_327 = io_fwriteData_4_valid & io_fwriteData_4_addr == 5'h1b; // @[FRegfile.scala 83:44]
-  wire  _valid_T_329 = io_fwriteData_3_valid & io_fwriteData_3_addr == 5'h1b; // @[FRegfile.scala 84:44]
-  wire  _valid_T_331 = io_fwriteData_2_valid & io_fwriteData_2_addr == 5'h1b; // @[FRegfile.scala 85:44]
-  wire  _valid_T_333 = io_fwriteData_1_valid & io_fwriteData_1_addr == 5'h1b; // @[FRegfile.scala 86:44]
-  wire  _valid_T_335 = io_fwriteData_0_valid & io_fwriteData_0_addr == 5'h1b; // @[FRegfile.scala 87:44]
-  wire [5:0] valid_27 = {_valid_T_325,_valid_T_327,_valid_T_329,_valid_T_331,_valid_T_333,_valid_T_335}; // @[Cat.scala 31:58]
-  wire [31:0] _data_T_433 = valid_27[0] ? io_fwriteData_0_data : 32'h0; // @[FRegfile.scala 88:20]
-  wire [31:0] _data_T_435 = valid_27[1] ? io_fwriteData_1_data : 32'h0; // @[FRegfile.scala 89:20]
-  wire [31:0] _data_T_436 = _data_T_433 | _data_T_435; // @[FRegfile.scala 88:59]
-  wire [31:0] _data_T_438 = valid_27[2] ? io_fwriteData_2_data : 32'h0; // @[FRegfile.scala 90:20]
-  wire [31:0] _data_T_439 = _data_T_436 | _data_T_438; // @[FRegfile.scala 89:59]
-  wire [31:0] _data_T_441 = valid_27[3] ? io_fwriteData_3_data : 32'h0; // @[FRegfile.scala 91:20]
-  wire [31:0] _data_T_442 = _data_T_439 | _data_T_441; // @[FRegfile.scala 90:59]
-  wire [31:0] _data_T_444 = valid_27[4] ? io_fwriteData_4_data : 32'h0; // @[FRegfile.scala 92:20]
-  wire [31:0] _data_T_445 = _data_T_442 | _data_T_444; // @[FRegfile.scala 91:59]
-  wire [31:0] _data_T_447 = valid_27[5] ? io_fwriteData_5_data : 32'h0; // @[FRegfile.scala 93:20]
-  wire [31:0] data_27 = _data_T_445 | _data_T_447; // @[FRegfile.scala 92:59]
-  wire  fwriteValid_27 = valid_27 != 6'h0; // @[FRegfile.scala 95:29]
-  wire [1:0] _T_549 = valid_27[1] + valid_27[2]; // @[Bitwise.scala 48:55]
-  wire [1:0] _GEN_93 = {{1'd0}, valid_27[0]}; // @[Bitwise.scala 48:55]
-  wire [2:0] _T_551 = _GEN_93 + _T_549; // @[Bitwise.scala 48:55]
-  wire [1:0] _T_553 = valid_27[4] + valid_27[5]; // @[Bitwise.scala 48:55]
-  wire [1:0] _GEN_94 = {{1'd0}, valid_27[3]}; // @[Bitwise.scala 48:55]
-  wire [2:0] _T_555 = _GEN_94 + _T_553; // @[Bitwise.scala 48:55]
-  wire [2:0] _T_557 = _T_551[1:0] + _T_555[1:0]; // @[Bitwise.scala 48:55]
-  wire  _valid_T_337 = io_fwriteData_5_valid & io_fwriteData_5_addr == 5'h1c; // @[FRegfile.scala 82:44]
-  wire  _valid_T_339 = io_fwriteData_4_valid & io_fwriteData_4_addr == 5'h1c; // @[FRegfile.scala 83:44]
-  wire  _valid_T_341 = io_fwriteData_3_valid & io_fwriteData_3_addr == 5'h1c; // @[FRegfile.scala 84:44]
-  wire  _valid_T_343 = io_fwriteData_2_valid & io_fwriteData_2_addr == 5'h1c; // @[FRegfile.scala 85:44]
-  wire  _valid_T_345 = io_fwriteData_1_valid & io_fwriteData_1_addr == 5'h1c; // @[FRegfile.scala 86:44]
-  wire  _valid_T_347 = io_fwriteData_0_valid & io_fwriteData_0_addr == 5'h1c; // @[FRegfile.scala 87:44]
-  wire [5:0] valid_28 = {_valid_T_337,_valid_T_339,_valid_T_341,_valid_T_343,_valid_T_345,_valid_T_347}; // @[Cat.scala 31:58]
-  wire [31:0] _data_T_449 = valid_28[0] ? io_fwriteData_0_data : 32'h0; // @[FRegfile.scala 88:20]
-  wire [31:0] _data_T_451 = valid_28[1] ? io_fwriteData_1_data : 32'h0; // @[FRegfile.scala 89:20]
-  wire [31:0] _data_T_452 = _data_T_449 | _data_T_451; // @[FRegfile.scala 88:59]
-  wire [31:0] _data_T_454 = valid_28[2] ? io_fwriteData_2_data : 32'h0; // @[FRegfile.scala 90:20]
-  wire [31:0] _data_T_455 = _data_T_452 | _data_T_454; // @[FRegfile.scala 89:59]
-  wire [31:0] _data_T_457 = valid_28[3] ? io_fwriteData_3_data : 32'h0; // @[FRegfile.scala 91:20]
-  wire [31:0] _data_T_458 = _data_T_455 | _data_T_457; // @[FRegfile.scala 90:59]
-  wire [31:0] _data_T_460 = valid_28[4] ? io_fwriteData_4_data : 32'h0; // @[FRegfile.scala 92:20]
-  wire [31:0] _data_T_461 = _data_T_458 | _data_T_460; // @[FRegfile.scala 91:59]
-  wire [31:0] _data_T_463 = valid_28[5] ? io_fwriteData_5_data : 32'h0; // @[FRegfile.scala 93:20]
-  wire [31:0] data_28 = _data_T_461 | _data_T_463; // @[FRegfile.scala 92:59]
-  wire  fwriteValid_28 = valid_28 != 6'h0; // @[FRegfile.scala 95:29]
-  wire [1:0] _T_569 = valid_28[1] + valid_28[2]; // @[Bitwise.scala 48:55]
-  wire [1:0] _GEN_95 = {{1'd0}, valid_28[0]}; // @[Bitwise.scala 48:55]
-  wire [2:0] _T_571 = _GEN_95 + _T_569; // @[Bitwise.scala 48:55]
-  wire [1:0] _T_573 = valid_28[4] + valid_28[5]; // @[Bitwise.scala 48:55]
-  wire [1:0] _GEN_96 = {{1'd0}, valid_28[3]}; // @[Bitwise.scala 48:55]
-  wire [2:0] _T_575 = _GEN_96 + _T_573; // @[Bitwise.scala 48:55]
-  wire [2:0] _T_577 = _T_571[1:0] + _T_575[1:0]; // @[Bitwise.scala 48:55]
-  wire  _valid_T_349 = io_fwriteData_5_valid & io_fwriteData_5_addr == 5'h1d; // @[FRegfile.scala 82:44]
-  wire  _valid_T_351 = io_fwriteData_4_valid & io_fwriteData_4_addr == 5'h1d; // @[FRegfile.scala 83:44]
-  wire  _valid_T_353 = io_fwriteData_3_valid & io_fwriteData_3_addr == 5'h1d; // @[FRegfile.scala 84:44]
-  wire  _valid_T_355 = io_fwriteData_2_valid & io_fwriteData_2_addr == 5'h1d; // @[FRegfile.scala 85:44]
-  wire  _valid_T_357 = io_fwriteData_1_valid & io_fwriteData_1_addr == 5'h1d; // @[FRegfile.scala 86:44]
-  wire  _valid_T_359 = io_fwriteData_0_valid & io_fwriteData_0_addr == 5'h1d; // @[FRegfile.scala 87:44]
-  wire [5:0] valid_29 = {_valid_T_349,_valid_T_351,_valid_T_353,_valid_T_355,_valid_T_357,_valid_T_359}; // @[Cat.scala 31:58]
-  wire [31:0] _data_T_465 = valid_29[0] ? io_fwriteData_0_data : 32'h0; // @[FRegfile.scala 88:20]
-  wire [31:0] _data_T_467 = valid_29[1] ? io_fwriteData_1_data : 32'h0; // @[FRegfile.scala 89:20]
-  wire [31:0] _data_T_468 = _data_T_465 | _data_T_467; // @[FRegfile.scala 88:59]
-  wire [31:0] _data_T_470 = valid_29[2] ? io_fwriteData_2_data : 32'h0; // @[FRegfile.scala 90:20]
-  wire [31:0] _data_T_471 = _data_T_468 | _data_T_470; // @[FRegfile.scala 89:59]
-  wire [31:0] _data_T_473 = valid_29[3] ? io_fwriteData_3_data : 32'h0; // @[FRegfile.scala 91:20]
-  wire [31:0] _data_T_474 = _data_T_471 | _data_T_473; // @[FRegfile.scala 90:59]
-  wire [31:0] _data_T_476 = valid_29[4] ? io_fwriteData_4_data : 32'h0; // @[FRegfile.scala 92:20]
-  wire [31:0] _data_T_477 = _data_T_474 | _data_T_476; // @[FRegfile.scala 91:59]
-  wire [31:0] _data_T_479 = valid_29[5] ? io_fwriteData_5_data : 32'h0; // @[FRegfile.scala 93:20]
-  wire [31:0] data_29 = _data_T_477 | _data_T_479; // @[FRegfile.scala 92:59]
-  wire  fwriteValid_29 = valid_29 != 6'h0; // @[FRegfile.scala 95:29]
-  wire [1:0] _T_589 = valid_29[1] + valid_29[2]; // @[Bitwise.scala 48:55]
-  wire [1:0] _GEN_97 = {{1'd0}, valid_29[0]}; // @[Bitwise.scala 48:55]
-  wire [2:0] _T_591 = _GEN_97 + _T_589; // @[Bitwise.scala 48:55]
-  wire [1:0] _T_593 = valid_29[4] + valid_29[5]; // @[Bitwise.scala 48:55]
-  wire [1:0] _GEN_98 = {{1'd0}, valid_29[3]}; // @[Bitwise.scala 48:55]
-  wire [2:0] _T_595 = _GEN_98 + _T_593; // @[Bitwise.scala 48:55]
-  wire [2:0] _T_597 = _T_591[1:0] + _T_595[1:0]; // @[Bitwise.scala 48:55]
-  wire  _valid_T_361 = io_fwriteData_5_valid & io_fwriteData_5_addr == 5'h1e; // @[FRegfile.scala 82:44]
-  wire  _valid_T_363 = io_fwriteData_4_valid & io_fwriteData_4_addr == 5'h1e; // @[FRegfile.scala 83:44]
-  wire  _valid_T_365 = io_fwriteData_3_valid & io_fwriteData_3_addr == 5'h1e; // @[FRegfile.scala 84:44]
-  wire  _valid_T_367 = io_fwriteData_2_valid & io_fwriteData_2_addr == 5'h1e; // @[FRegfile.scala 85:44]
-  wire  _valid_T_369 = io_fwriteData_1_valid & io_fwriteData_1_addr == 5'h1e; // @[FRegfile.scala 86:44]
-  wire  _valid_T_371 = io_fwriteData_0_valid & io_fwriteData_0_addr == 5'h1e; // @[FRegfile.scala 87:44]
-  wire [5:0] valid_30 = {_valid_T_361,_valid_T_363,_valid_T_365,_valid_T_367,_valid_T_369,_valid_T_371}; // @[Cat.scala 31:58]
-  wire [31:0] _data_T_481 = valid_30[0] ? io_fwriteData_0_data : 32'h0; // @[FRegfile.scala 88:20]
-  wire [31:0] _data_T_483 = valid_30[1] ? io_fwriteData_1_data : 32'h0; // @[FRegfile.scala 89:20]
-  wire [31:0] _data_T_484 = _data_T_481 | _data_T_483; // @[FRegfile.scala 88:59]
-  wire [31:0] _data_T_486 = valid_30[2] ? io_fwriteData_2_data : 32'h0; // @[FRegfile.scala 90:20]
-  wire [31:0] _data_T_487 = _data_T_484 | _data_T_486; // @[FRegfile.scala 89:59]
-  wire [31:0] _data_T_489 = valid_30[3] ? io_fwriteData_3_data : 32'h0; // @[FRegfile.scala 91:20]
-  wire [31:0] _data_T_490 = _data_T_487 | _data_T_489; // @[FRegfile.scala 90:59]
-  wire [31:0] _data_T_492 = valid_30[4] ? io_fwriteData_4_data : 32'h0; // @[FRegfile.scala 92:20]
-  wire [31:0] _data_T_493 = _data_T_490 | _data_T_492; // @[FRegfile.scala 91:59]
-  wire [31:0] _data_T_495 = valid_30[5] ? io_fwriteData_5_data : 32'h0; // @[FRegfile.scala 93:20]
-  wire [31:0] data_30 = _data_T_493 | _data_T_495; // @[FRegfile.scala 92:59]
-  wire  fwriteValid_30 = valid_30 != 6'h0; // @[FRegfile.scala 95:29]
-  wire [1:0] _T_609 = valid_30[1] + valid_30[2]; // @[Bitwise.scala 48:55]
-  wire [1:0] _GEN_99 = {{1'd0}, valid_30[0]}; // @[Bitwise.scala 48:55]
-  wire [2:0] _T_611 = _GEN_99 + _T_609; // @[Bitwise.scala 48:55]
-  wire [1:0] _T_613 = valid_30[4] + valid_30[5]; // @[Bitwise.scala 48:55]
-  wire [1:0] _GEN_100 = {{1'd0}, valid_30[3]}; // @[Bitwise.scala 48:55]
-  wire [2:0] _T_615 = _GEN_100 + _T_613; // @[Bitwise.scala 48:55]
-  wire [2:0] _T_617 = _T_611[1:0] + _T_615[1:0]; // @[Bitwise.scala 48:55]
-  wire  _valid_T_373 = io_fwriteData_5_valid & io_fwriteData_5_addr == 5'h1f; // @[FRegfile.scala 82:44]
-  wire  _valid_T_375 = io_fwriteData_4_valid & io_fwriteData_4_addr == 5'h1f; // @[FRegfile.scala 83:44]
-  wire  _valid_T_377 = io_fwriteData_3_valid & io_fwriteData_3_addr == 5'h1f; // @[FRegfile.scala 84:44]
-  wire  _valid_T_379 = io_fwriteData_2_valid & io_fwriteData_2_addr == 5'h1f; // @[FRegfile.scala 85:44]
-  wire  _valid_T_381 = io_fwriteData_1_valid & io_fwriteData_1_addr == 5'h1f; // @[FRegfile.scala 86:44]
-  wire  _valid_T_383 = io_fwriteData_0_valid & io_fwriteData_0_addr == 5'h1f; // @[FRegfile.scala 87:44]
-  wire [5:0] valid_31 = {_valid_T_373,_valid_T_375,_valid_T_377,_valid_T_379,_valid_T_381,_valid_T_383}; // @[Cat.scala 31:58]
-  wire [31:0] _data_T_497 = valid_31[0] ? io_fwriteData_0_data : 32'h0; // @[FRegfile.scala 88:20]
-  wire [31:0] _data_T_499 = valid_31[1] ? io_fwriteData_1_data : 32'h0; // @[FRegfile.scala 89:20]
-  wire [31:0] _data_T_500 = _data_T_497 | _data_T_499; // @[FRegfile.scala 88:59]
-  wire [31:0] _data_T_502 = valid_31[2] ? io_fwriteData_2_data : 32'h0; // @[FRegfile.scala 90:20]
-  wire [31:0] _data_T_503 = _data_T_500 | _data_T_502; // @[FRegfile.scala 89:59]
-  wire [31:0] _data_T_505 = valid_31[3] ? io_fwriteData_3_data : 32'h0; // @[FRegfile.scala 91:20]
-  wire [31:0] _data_T_506 = _data_T_503 | _data_T_505; // @[FRegfile.scala 90:59]
-  wire [31:0] _data_T_508 = valid_31[4] ? io_fwriteData_4_data : 32'h0; // @[FRegfile.scala 92:20]
-  wire [31:0] _data_T_509 = _data_T_506 | _data_T_508; // @[FRegfile.scala 91:59]
-  wire [31:0] _data_T_511 = valid_31[5] ? io_fwriteData_5_data : 32'h0; // @[FRegfile.scala 93:20]
-  wire [31:0] data_31 = _data_T_509 | _data_T_511; // @[FRegfile.scala 92:59]
-  wire  fwriteValid_31 = valid_31 != 6'h0; // @[FRegfile.scala 95:29]
-  wire [1:0] _T_629 = valid_31[1] + valid_31[2]; // @[Bitwise.scala 48:55]
-  wire [1:0] _GEN_101 = {{1'd0}, valid_31[0]}; // @[Bitwise.scala 48:55]
-  wire [2:0] _T_631 = _GEN_101 + _T_629; // @[Bitwise.scala 48:55]
-  wire [1:0] _T_633 = valid_31[4] + valid_31[5]; // @[Bitwise.scala 48:55]
-  wire [1:0] _GEN_102 = {{1'd0}, valid_31[3]}; // @[Bitwise.scala 48:55]
-  wire [2:0] _T_635 = _GEN_102 + _T_633; // @[Bitwise.scala 48:55]
-  wire [2:0] _T_637 = _T_631[1:0] + _T_635[1:0]; // @[Bitwise.scala 48:55]
-  reg [31:0] readDataBits_0; // @[FRegfile.scala 109:26]
-  reg [31:0] readDataBits_1; // @[FRegfile.scala 109:26]
-  reg [31:0] readDataBits_2; // @[FRegfile.scala 109:26]
-  reg [31:0] readDataBits_3; // @[FRegfile.scala 109:26]
-  reg [31:0] readDataBits_4; // @[FRegfile.scala 109:26]
-  reg [31:0] readDataBits_5; // @[FRegfile.scala 109:26]
-  wire  write_value__0 = 5'h0 == io_freadAddr_0_addr & fwriteValid_0; // @[Library.scala 101:22]
-  wire  write_value__1 = 5'h1 == io_freadAddr_0_addr & fwriteValid_1; // @[Library.scala 101:22]
-  wire  write_value__2 = 5'h2 == io_freadAddr_0_addr & fwriteValid_2; // @[Library.scala 101:22]
-  wire  write_value__3 = 5'h3 == io_freadAddr_0_addr & fwriteValid_3; // @[Library.scala 101:22]
-  wire  write_value__4 = 5'h4 == io_freadAddr_0_addr & fwriteValid_4; // @[Library.scala 101:22]
-  wire  write_value__5 = 5'h5 == io_freadAddr_0_addr & fwriteValid_5; // @[Library.scala 101:22]
-  wire  write_value__6 = 5'h6 == io_freadAddr_0_addr & fwriteValid_6; // @[Library.scala 101:22]
-  wire  write_value__7 = 5'h7 == io_freadAddr_0_addr & fwriteValid_7; // @[Library.scala 101:22]
-  wire  write_value__8 = 5'h8 == io_freadAddr_0_addr & fwriteValid_8; // @[Library.scala 101:22]
-  wire  write_value__9 = 5'h9 == io_freadAddr_0_addr & fwriteValid_9; // @[Library.scala 101:22]
-  wire  write_value__10 = 5'ha == io_freadAddr_0_addr & fwriteValid_10; // @[Library.scala 101:22]
-  wire  write_value__11 = 5'hb == io_freadAddr_0_addr & fwriteValid_11; // @[Library.scala 101:22]
-  wire  write_value__12 = 5'hc == io_freadAddr_0_addr & fwriteValid_12; // @[Library.scala 101:22]
-  wire  write_value__13 = 5'hd == io_freadAddr_0_addr & fwriteValid_13; // @[Library.scala 101:22]
-  wire  write_value__14 = 5'he == io_freadAddr_0_addr & fwriteValid_14; // @[Library.scala 101:22]
-  wire  write_value__15 = 5'hf == io_freadAddr_0_addr & fwriteValid_15; // @[Library.scala 101:22]
-  wire  write_value__16 = 5'h10 == io_freadAddr_0_addr & fwriteValid_16; // @[Library.scala 101:22]
-  wire  write_value__17 = 5'h11 == io_freadAddr_0_addr & fwriteValid_17; // @[Library.scala 101:22]
-  wire  write_value__18 = 5'h12 == io_freadAddr_0_addr & fwriteValid_18; // @[Library.scala 101:22]
-  wire  write_value__19 = 5'h13 == io_freadAddr_0_addr & fwriteValid_19; // @[Library.scala 101:22]
-  wire  write_value__20 = 5'h14 == io_freadAddr_0_addr & fwriteValid_20; // @[Library.scala 101:22]
-  wire  write_value__21 = 5'h15 == io_freadAddr_0_addr & fwriteValid_21; // @[Library.scala 101:22]
-  wire  write_value__22 = 5'h16 == io_freadAddr_0_addr & fwriteValid_22; // @[Library.scala 101:22]
-  wire  write_value__23 = 5'h17 == io_freadAddr_0_addr & fwriteValid_23; // @[Library.scala 101:22]
-  wire  write_value__24 = 5'h18 == io_freadAddr_0_addr & fwriteValid_24; // @[Library.scala 101:22]
-  wire  write_value__25 = 5'h19 == io_freadAddr_0_addr & fwriteValid_25; // @[Library.scala 101:22]
-  wire  write_value__26 = 5'h1a == io_freadAddr_0_addr & fwriteValid_26; // @[Library.scala 101:22]
-  wire  write_value__27 = 5'h1b == io_freadAddr_0_addr & fwriteValid_27; // @[Library.scala 101:22]
-  wire  write_value__28 = 5'h1c == io_freadAddr_0_addr & fwriteValid_28; // @[Library.scala 101:22]
-  wire  write_value__29 = 5'h1d == io_freadAddr_0_addr & fwriteValid_29; // @[Library.scala 101:22]
-  wire  write_value__30 = 5'h1e == io_freadAddr_0_addr & fwriteValid_30; // @[Library.scala 101:22]
-  wire  write_value__31 = 5'h1f == io_freadAddr_0_addr & fwriteValid_31; // @[Library.scala 101:22]
-  wire  write_value_1_0 = write_value__0 | write_value__1; // @[Library.scala 115:37]
-  wire  write_value_1_1 = write_value__2 | write_value__3; // @[Library.scala 115:37]
-  wire  write_value_1_2 = write_value__4 | write_value__5; // @[Library.scala 115:37]
-  wire  write_value_1_3 = write_value__6 | write_value__7; // @[Library.scala 115:37]
-  wire  write_value_1_4 = write_value__8 | write_value__9; // @[Library.scala 115:37]
-  wire  write_value_1_5 = write_value__10 | write_value__11; // @[Library.scala 115:37]
-  wire  write_value_1_6 = write_value__12 | write_value__13; // @[Library.scala 115:37]
-  wire  write_value_1_7 = write_value__14 | write_value__15; // @[Library.scala 115:37]
-  wire  write_value_1_8 = write_value__16 | write_value__17; // @[Library.scala 115:37]
-  wire  write_value_1_9 = write_value__18 | write_value__19; // @[Library.scala 115:37]
-  wire  write_value_1_10 = write_value__20 | write_value__21; // @[Library.scala 115:37]
-  wire  write_value_1_11 = write_value__22 | write_value__23; // @[Library.scala 115:37]
-  wire  write_value_1_12 = write_value__24 | write_value__25; // @[Library.scala 115:37]
-  wire  write_value_1_13 = write_value__26 | write_value__27; // @[Library.scala 115:37]
-  wire  write_value_1_14 = write_value__28 | write_value__29; // @[Library.scala 115:37]
-  wire  write_value_1_15 = write_value__30 | write_value__31; // @[Library.scala 115:37]
-  wire  write_value_2_0 = write_value_1_0 | write_value_1_1; // @[Library.scala 115:37]
-  wire  write_value_2_1 = write_value_1_2 | write_value_1_3; // @[Library.scala 115:37]
-  wire  write_value_2_2 = write_value_1_4 | write_value_1_5; // @[Library.scala 115:37]
-  wire  write_value_2_3 = write_value_1_6 | write_value_1_7; // @[Library.scala 115:37]
-  wire  write_value_2_4 = write_value_1_8 | write_value_1_9; // @[Library.scala 115:37]
-  wire  write_value_2_5 = write_value_1_10 | write_value_1_11; // @[Library.scala 115:37]
-  wire  write_value_2_6 = write_value_1_12 | write_value_1_13; // @[Library.scala 115:37]
-  wire  write_value_2_7 = write_value_1_14 | write_value_1_15; // @[Library.scala 115:37]
-  wire  write_value_3_0 = write_value_2_0 | write_value_2_1; // @[Library.scala 115:37]
-  wire  write_value_3_1 = write_value_2_2 | write_value_2_3; // @[Library.scala 115:37]
-  wire  write_value_3_2 = write_value_2_4 | write_value_2_5; // @[Library.scala 115:37]
-  wire  write_value_3_3 = write_value_2_6 | write_value_2_7; // @[Library.scala 115:37]
-  wire  write_value_4_0 = write_value_3_0 | write_value_3_1; // @[Library.scala 115:37]
-  wire  write_value_4_1 = write_value_3_2 | write_value_3_3; // @[Library.scala 115:37]
-  wire  write_value_5_0 = write_value_4_0 | write_value_4_1; // @[Library.scala 115:37]
-  wire [31:0] rdata_value__0 = 5'h0 == io_freadAddr_0_addr ? fregfile_0 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] rdata_value__1 = 5'h1 == io_freadAddr_0_addr ? fregfile_1 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] rdata_value__2 = 5'h2 == io_freadAddr_0_addr ? fregfile_2 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] rdata_value__3 = 5'h3 == io_freadAddr_0_addr ? fregfile_3 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] rdata_value__4 = 5'h4 == io_freadAddr_0_addr ? fregfile_4 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] rdata_value__5 = 5'h5 == io_freadAddr_0_addr ? fregfile_5 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] rdata_value__6 = 5'h6 == io_freadAddr_0_addr ? fregfile_6 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] rdata_value__7 = 5'h7 == io_freadAddr_0_addr ? fregfile_7 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] rdata_value__8 = 5'h8 == io_freadAddr_0_addr ? fregfile_8 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] rdata_value__9 = 5'h9 == io_freadAddr_0_addr ? fregfile_9 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] rdata_value__10 = 5'ha == io_freadAddr_0_addr ? fregfile_10 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] rdata_value__11 = 5'hb == io_freadAddr_0_addr ? fregfile_11 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] rdata_value__12 = 5'hc == io_freadAddr_0_addr ? fregfile_12 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] rdata_value__13 = 5'hd == io_freadAddr_0_addr ? fregfile_13 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] rdata_value__14 = 5'he == io_freadAddr_0_addr ? fregfile_14 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] rdata_value__15 = 5'hf == io_freadAddr_0_addr ? fregfile_15 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] rdata_value__16 = 5'h10 == io_freadAddr_0_addr ? fregfile_16 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] rdata_value__17 = 5'h11 == io_freadAddr_0_addr ? fregfile_17 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] rdata_value__18 = 5'h12 == io_freadAddr_0_addr ? fregfile_18 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] rdata_value__19 = 5'h13 == io_freadAddr_0_addr ? fregfile_19 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] rdata_value__20 = 5'h14 == io_freadAddr_0_addr ? fregfile_20 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] rdata_value__21 = 5'h15 == io_freadAddr_0_addr ? fregfile_21 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] rdata_value__22 = 5'h16 == io_freadAddr_0_addr ? fregfile_22 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] rdata_value__23 = 5'h17 == io_freadAddr_0_addr ? fregfile_23 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] rdata_value__24 = 5'h18 == io_freadAddr_0_addr ? fregfile_24 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] rdata_value__25 = 5'h19 == io_freadAddr_0_addr ? fregfile_25 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] rdata_value__26 = 5'h1a == io_freadAddr_0_addr ? fregfile_26 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] rdata_value__27 = 5'h1b == io_freadAddr_0_addr ? fregfile_27 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] rdata_value__28 = 5'h1c == io_freadAddr_0_addr ? fregfile_28 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] rdata_value__29 = 5'h1d == io_freadAddr_0_addr ? fregfile_29 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] rdata_value__30 = 5'h1e == io_freadAddr_0_addr ? fregfile_30 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] rdata_value__31 = 5'h1f == io_freadAddr_0_addr ? fregfile_31 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] rdata_value_1_0 = rdata_value__0 | rdata_value__1; // @[Library.scala 115:37]
-  wire [31:0] rdata_value_1_1 = rdata_value__2 | rdata_value__3; // @[Library.scala 115:37]
-  wire [31:0] rdata_value_1_2 = rdata_value__4 | rdata_value__5; // @[Library.scala 115:37]
-  wire [31:0] rdata_value_1_3 = rdata_value__6 | rdata_value__7; // @[Library.scala 115:37]
-  wire [31:0] rdata_value_1_4 = rdata_value__8 | rdata_value__9; // @[Library.scala 115:37]
-  wire [31:0] rdata_value_1_5 = rdata_value__10 | rdata_value__11; // @[Library.scala 115:37]
-  wire [31:0] rdata_value_1_6 = rdata_value__12 | rdata_value__13; // @[Library.scala 115:37]
-  wire [31:0] rdata_value_1_7 = rdata_value__14 | rdata_value__15; // @[Library.scala 115:37]
-  wire [31:0] rdata_value_1_8 = rdata_value__16 | rdata_value__17; // @[Library.scala 115:37]
-  wire [31:0] rdata_value_1_9 = rdata_value__18 | rdata_value__19; // @[Library.scala 115:37]
-  wire [31:0] rdata_value_1_10 = rdata_value__20 | rdata_value__21; // @[Library.scala 115:37]
-  wire [31:0] rdata_value_1_11 = rdata_value__22 | rdata_value__23; // @[Library.scala 115:37]
-  wire [31:0] rdata_value_1_12 = rdata_value__24 | rdata_value__25; // @[Library.scala 115:37]
-  wire [31:0] rdata_value_1_13 = rdata_value__26 | rdata_value__27; // @[Library.scala 115:37]
-  wire [31:0] rdata_value_1_14 = rdata_value__28 | rdata_value__29; // @[Library.scala 115:37]
-  wire [31:0] rdata_value_1_15 = rdata_value__30 | rdata_value__31; // @[Library.scala 115:37]
-  wire [31:0] rdata_value_2_0 = rdata_value_1_0 | rdata_value_1_1; // @[Library.scala 115:37]
-  wire [31:0] rdata_value_2_1 = rdata_value_1_2 | rdata_value_1_3; // @[Library.scala 115:37]
-  wire [31:0] rdata_value_2_2 = rdata_value_1_4 | rdata_value_1_5; // @[Library.scala 115:37]
-  wire [31:0] rdata_value_2_3 = rdata_value_1_6 | rdata_value_1_7; // @[Library.scala 115:37]
-  wire [31:0] rdata_value_2_4 = rdata_value_1_8 | rdata_value_1_9; // @[Library.scala 115:37]
-  wire [31:0] rdata_value_2_5 = rdata_value_1_10 | rdata_value_1_11; // @[Library.scala 115:37]
-  wire [31:0] rdata_value_2_6 = rdata_value_1_12 | rdata_value_1_13; // @[Library.scala 115:37]
-  wire [31:0] rdata_value_2_7 = rdata_value_1_14 | rdata_value_1_15; // @[Library.scala 115:37]
-  wire [31:0] rdata_value_3_0 = rdata_value_2_0 | rdata_value_2_1; // @[Library.scala 115:37]
-  wire [31:0] rdata_value_3_1 = rdata_value_2_2 | rdata_value_2_3; // @[Library.scala 115:37]
-  wire [31:0] rdata_value_3_2 = rdata_value_2_4 | rdata_value_2_5; // @[Library.scala 115:37]
-  wire [31:0] rdata_value_3_3 = rdata_value_2_6 | rdata_value_2_7; // @[Library.scala 115:37]
-  wire [31:0] rdata_value_4_0 = rdata_value_3_0 | rdata_value_3_1; // @[Library.scala 115:37]
-  wire [31:0] rdata_value_4_1 = rdata_value_3_2 | rdata_value_3_3; // @[Library.scala 115:37]
-  wire [31:0] rdata_value_5_0 = rdata_value_4_0 | rdata_value_4_1; // @[Library.scala 115:37]
-  wire [31:0] wdata_value__0 = 5'h0 == io_freadAddr_0_addr ? data : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] wdata_value__1 = 5'h1 == io_freadAddr_0_addr ? data_1 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] wdata_value__2 = 5'h2 == io_freadAddr_0_addr ? data_2 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] wdata_value__3 = 5'h3 == io_freadAddr_0_addr ? data_3 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] wdata_value__4 = 5'h4 == io_freadAddr_0_addr ? data_4 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] wdata_value__5 = 5'h5 == io_freadAddr_0_addr ? data_5 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] wdata_value__6 = 5'h6 == io_freadAddr_0_addr ? data_6 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] wdata_value__7 = 5'h7 == io_freadAddr_0_addr ? data_7 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] wdata_value__8 = 5'h8 == io_freadAddr_0_addr ? data_8 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] wdata_value__9 = 5'h9 == io_freadAddr_0_addr ? data_9 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] wdata_value__10 = 5'ha == io_freadAddr_0_addr ? data_10 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] wdata_value__11 = 5'hb == io_freadAddr_0_addr ? data_11 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] wdata_value__12 = 5'hc == io_freadAddr_0_addr ? data_12 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] wdata_value__13 = 5'hd == io_freadAddr_0_addr ? data_13 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] wdata_value__14 = 5'he == io_freadAddr_0_addr ? data_14 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] wdata_value__15 = 5'hf == io_freadAddr_0_addr ? data_15 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] wdata_value__16 = 5'h10 == io_freadAddr_0_addr ? data_16 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] wdata_value__17 = 5'h11 == io_freadAddr_0_addr ? data_17 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] wdata_value__18 = 5'h12 == io_freadAddr_0_addr ? data_18 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] wdata_value__19 = 5'h13 == io_freadAddr_0_addr ? data_19 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] wdata_value__20 = 5'h14 == io_freadAddr_0_addr ? data_20 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] wdata_value__21 = 5'h15 == io_freadAddr_0_addr ? data_21 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] wdata_value__22 = 5'h16 == io_freadAddr_0_addr ? data_22 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] wdata_value__23 = 5'h17 == io_freadAddr_0_addr ? data_23 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] wdata_value__24 = 5'h18 == io_freadAddr_0_addr ? data_24 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] wdata_value__25 = 5'h19 == io_freadAddr_0_addr ? data_25 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] wdata_value__26 = 5'h1a == io_freadAddr_0_addr ? data_26 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] wdata_value__27 = 5'h1b == io_freadAddr_0_addr ? data_27 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] wdata_value__28 = 5'h1c == io_freadAddr_0_addr ? data_28 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] wdata_value__29 = 5'h1d == io_freadAddr_0_addr ? data_29 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] wdata_value__30 = 5'h1e == io_freadAddr_0_addr ? data_30 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] wdata_value__31 = 5'h1f == io_freadAddr_0_addr ? data_31 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] wdata_value_1_0 = wdata_value__0 | wdata_value__1; // @[Library.scala 115:37]
-  wire [31:0] wdata_value_1_1 = wdata_value__2 | wdata_value__3; // @[Library.scala 115:37]
-  wire [31:0] wdata_value_1_2 = wdata_value__4 | wdata_value__5; // @[Library.scala 115:37]
-  wire [31:0] wdata_value_1_3 = wdata_value__6 | wdata_value__7; // @[Library.scala 115:37]
-  wire [31:0] wdata_value_1_4 = wdata_value__8 | wdata_value__9; // @[Library.scala 115:37]
-  wire [31:0] wdata_value_1_5 = wdata_value__10 | wdata_value__11; // @[Library.scala 115:37]
-  wire [31:0] wdata_value_1_6 = wdata_value__12 | wdata_value__13; // @[Library.scala 115:37]
-  wire [31:0] wdata_value_1_7 = wdata_value__14 | wdata_value__15; // @[Library.scala 115:37]
-  wire [31:0] wdata_value_1_8 = wdata_value__16 | wdata_value__17; // @[Library.scala 115:37]
-  wire [31:0] wdata_value_1_9 = wdata_value__18 | wdata_value__19; // @[Library.scala 115:37]
-  wire [31:0] wdata_value_1_10 = wdata_value__20 | wdata_value__21; // @[Library.scala 115:37]
-  wire [31:0] wdata_value_1_11 = wdata_value__22 | wdata_value__23; // @[Library.scala 115:37]
-  wire [31:0] wdata_value_1_12 = wdata_value__24 | wdata_value__25; // @[Library.scala 115:37]
-  wire [31:0] wdata_value_1_13 = wdata_value__26 | wdata_value__27; // @[Library.scala 115:37]
-  wire [31:0] wdata_value_1_14 = wdata_value__28 | wdata_value__29; // @[Library.scala 115:37]
-  wire [31:0] wdata_value_1_15 = wdata_value__30 | wdata_value__31; // @[Library.scala 115:37]
-  wire [31:0] wdata_value_2_0 = wdata_value_1_0 | wdata_value_1_1; // @[Library.scala 115:37]
-  wire [31:0] wdata_value_2_1 = wdata_value_1_2 | wdata_value_1_3; // @[Library.scala 115:37]
-  wire [31:0] wdata_value_2_2 = wdata_value_1_4 | wdata_value_1_5; // @[Library.scala 115:37]
-  wire [31:0] wdata_value_2_3 = wdata_value_1_6 | wdata_value_1_7; // @[Library.scala 115:37]
-  wire [31:0] wdata_value_2_4 = wdata_value_1_8 | wdata_value_1_9; // @[Library.scala 115:37]
-  wire [31:0] wdata_value_2_5 = wdata_value_1_10 | wdata_value_1_11; // @[Library.scala 115:37]
-  wire [31:0] wdata_value_2_6 = wdata_value_1_12 | wdata_value_1_13; // @[Library.scala 115:37]
-  wire [31:0] wdata_value_2_7 = wdata_value_1_14 | wdata_value_1_15; // @[Library.scala 115:37]
-  wire [31:0] wdata_value_3_0 = wdata_value_2_0 | wdata_value_2_1; // @[Library.scala 115:37]
-  wire [31:0] wdata_value_3_1 = wdata_value_2_2 | wdata_value_2_3; // @[Library.scala 115:37]
-  wire [31:0] wdata_value_3_2 = wdata_value_2_4 | wdata_value_2_5; // @[Library.scala 115:37]
-  wire [31:0] wdata_value_3_3 = wdata_value_2_6 | wdata_value_2_7; // @[Library.scala 115:37]
-  wire [31:0] wdata_value_4_0 = wdata_value_3_0 | wdata_value_3_1; // @[Library.scala 115:37]
-  wire [31:0] wdata_value_4_1 = wdata_value_3_2 | wdata_value_3_3; // @[Library.scala 115:37]
-  wire [31:0] wdata_value_5_0 = wdata_value_4_0 | wdata_value_4_1; // @[Library.scala 115:37]
-  wire  write_value_6_0 = 5'h0 == io_freadAddr_1_addr & fwriteValid_0; // @[Library.scala 101:22]
-  wire  write_value_6_1 = 5'h1 == io_freadAddr_1_addr & fwriteValid_1; // @[Library.scala 101:22]
-  wire  write_value_6_2 = 5'h2 == io_freadAddr_1_addr & fwriteValid_2; // @[Library.scala 101:22]
-  wire  write_value_6_3 = 5'h3 == io_freadAddr_1_addr & fwriteValid_3; // @[Library.scala 101:22]
-  wire  write_value_6_4 = 5'h4 == io_freadAddr_1_addr & fwriteValid_4; // @[Library.scala 101:22]
-  wire  write_value_6_5 = 5'h5 == io_freadAddr_1_addr & fwriteValid_5; // @[Library.scala 101:22]
-  wire  write_value_6_6 = 5'h6 == io_freadAddr_1_addr & fwriteValid_6; // @[Library.scala 101:22]
-  wire  write_value_6_7 = 5'h7 == io_freadAddr_1_addr & fwriteValid_7; // @[Library.scala 101:22]
-  wire  write_value_6_8 = 5'h8 == io_freadAddr_1_addr & fwriteValid_8; // @[Library.scala 101:22]
-  wire  write_value_6_9 = 5'h9 == io_freadAddr_1_addr & fwriteValid_9; // @[Library.scala 101:22]
-  wire  write_value_6_10 = 5'ha == io_freadAddr_1_addr & fwriteValid_10; // @[Library.scala 101:22]
-  wire  write_value_6_11 = 5'hb == io_freadAddr_1_addr & fwriteValid_11; // @[Library.scala 101:22]
-  wire  write_value_6_12 = 5'hc == io_freadAddr_1_addr & fwriteValid_12; // @[Library.scala 101:22]
-  wire  write_value_6_13 = 5'hd == io_freadAddr_1_addr & fwriteValid_13; // @[Library.scala 101:22]
-  wire  write_value_6_14 = 5'he == io_freadAddr_1_addr & fwriteValid_14; // @[Library.scala 101:22]
-  wire  write_value_6_15 = 5'hf == io_freadAddr_1_addr & fwriteValid_15; // @[Library.scala 101:22]
-  wire  write_value_6_16 = 5'h10 == io_freadAddr_1_addr & fwriteValid_16; // @[Library.scala 101:22]
-  wire  write_value_6_17 = 5'h11 == io_freadAddr_1_addr & fwriteValid_17; // @[Library.scala 101:22]
-  wire  write_value_6_18 = 5'h12 == io_freadAddr_1_addr & fwriteValid_18; // @[Library.scala 101:22]
-  wire  write_value_6_19 = 5'h13 == io_freadAddr_1_addr & fwriteValid_19; // @[Library.scala 101:22]
-  wire  write_value_6_20 = 5'h14 == io_freadAddr_1_addr & fwriteValid_20; // @[Library.scala 101:22]
-  wire  write_value_6_21 = 5'h15 == io_freadAddr_1_addr & fwriteValid_21; // @[Library.scala 101:22]
-  wire  write_value_6_22 = 5'h16 == io_freadAddr_1_addr & fwriteValid_22; // @[Library.scala 101:22]
-  wire  write_value_6_23 = 5'h17 == io_freadAddr_1_addr & fwriteValid_23; // @[Library.scala 101:22]
-  wire  write_value_6_24 = 5'h18 == io_freadAddr_1_addr & fwriteValid_24; // @[Library.scala 101:22]
-  wire  write_value_6_25 = 5'h19 == io_freadAddr_1_addr & fwriteValid_25; // @[Library.scala 101:22]
-  wire  write_value_6_26 = 5'h1a == io_freadAddr_1_addr & fwriteValid_26; // @[Library.scala 101:22]
-  wire  write_value_6_27 = 5'h1b == io_freadAddr_1_addr & fwriteValid_27; // @[Library.scala 101:22]
-  wire  write_value_6_28 = 5'h1c == io_freadAddr_1_addr & fwriteValid_28; // @[Library.scala 101:22]
-  wire  write_value_6_29 = 5'h1d == io_freadAddr_1_addr & fwriteValid_29; // @[Library.scala 101:22]
-  wire  write_value_6_30 = 5'h1e == io_freadAddr_1_addr & fwriteValid_30; // @[Library.scala 101:22]
-  wire  write_value_6_31 = 5'h1f == io_freadAddr_1_addr & fwriteValid_31; // @[Library.scala 101:22]
-  wire  write_value_7_0 = write_value_6_0 | write_value_6_1; // @[Library.scala 115:37]
-  wire  write_value_7_1 = write_value_6_2 | write_value_6_3; // @[Library.scala 115:37]
-  wire  write_value_7_2 = write_value_6_4 | write_value_6_5; // @[Library.scala 115:37]
-  wire  write_value_7_3 = write_value_6_6 | write_value_6_7; // @[Library.scala 115:37]
-  wire  write_value_7_4 = write_value_6_8 | write_value_6_9; // @[Library.scala 115:37]
-  wire  write_value_7_5 = write_value_6_10 | write_value_6_11; // @[Library.scala 115:37]
-  wire  write_value_7_6 = write_value_6_12 | write_value_6_13; // @[Library.scala 115:37]
-  wire  write_value_7_7 = write_value_6_14 | write_value_6_15; // @[Library.scala 115:37]
-  wire  write_value_7_8 = write_value_6_16 | write_value_6_17; // @[Library.scala 115:37]
-  wire  write_value_7_9 = write_value_6_18 | write_value_6_19; // @[Library.scala 115:37]
-  wire  write_value_7_10 = write_value_6_20 | write_value_6_21; // @[Library.scala 115:37]
-  wire  write_value_7_11 = write_value_6_22 | write_value_6_23; // @[Library.scala 115:37]
-  wire  write_value_7_12 = write_value_6_24 | write_value_6_25; // @[Library.scala 115:37]
-  wire  write_value_7_13 = write_value_6_26 | write_value_6_27; // @[Library.scala 115:37]
-  wire  write_value_7_14 = write_value_6_28 | write_value_6_29; // @[Library.scala 115:37]
-  wire  write_value_7_15 = write_value_6_30 | write_value_6_31; // @[Library.scala 115:37]
-  wire  write_value_8_0 = write_value_7_0 | write_value_7_1; // @[Library.scala 115:37]
-  wire  write_value_8_1 = write_value_7_2 | write_value_7_3; // @[Library.scala 115:37]
-  wire  write_value_8_2 = write_value_7_4 | write_value_7_5; // @[Library.scala 115:37]
-  wire  write_value_8_3 = write_value_7_6 | write_value_7_7; // @[Library.scala 115:37]
-  wire  write_value_8_4 = write_value_7_8 | write_value_7_9; // @[Library.scala 115:37]
-  wire  write_value_8_5 = write_value_7_10 | write_value_7_11; // @[Library.scala 115:37]
-  wire  write_value_8_6 = write_value_7_12 | write_value_7_13; // @[Library.scala 115:37]
-  wire  write_value_8_7 = write_value_7_14 | write_value_7_15; // @[Library.scala 115:37]
-  wire  write_value_9_0 = write_value_8_0 | write_value_8_1; // @[Library.scala 115:37]
-  wire  write_value_9_1 = write_value_8_2 | write_value_8_3; // @[Library.scala 115:37]
-  wire  write_value_9_2 = write_value_8_4 | write_value_8_5; // @[Library.scala 115:37]
-  wire  write_value_9_3 = write_value_8_6 | write_value_8_7; // @[Library.scala 115:37]
-  wire  write_value_10_0 = write_value_9_0 | write_value_9_1; // @[Library.scala 115:37]
-  wire  write_value_10_1 = write_value_9_2 | write_value_9_3; // @[Library.scala 115:37]
-  wire  write_value_11_0 = write_value_10_0 | write_value_10_1; // @[Library.scala 115:37]
-  wire [31:0] rdata_value_6_0 = 5'h0 == io_freadAddr_1_addr ? fregfile_0 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] rdata_value_6_1 = 5'h1 == io_freadAddr_1_addr ? fregfile_1 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] rdata_value_6_2 = 5'h2 == io_freadAddr_1_addr ? fregfile_2 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] rdata_value_6_3 = 5'h3 == io_freadAddr_1_addr ? fregfile_3 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] rdata_value_6_4 = 5'h4 == io_freadAddr_1_addr ? fregfile_4 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] rdata_value_6_5 = 5'h5 == io_freadAddr_1_addr ? fregfile_5 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] rdata_value_6_6 = 5'h6 == io_freadAddr_1_addr ? fregfile_6 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] rdata_value_6_7 = 5'h7 == io_freadAddr_1_addr ? fregfile_7 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] rdata_value_6_8 = 5'h8 == io_freadAddr_1_addr ? fregfile_8 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] rdata_value_6_9 = 5'h9 == io_freadAddr_1_addr ? fregfile_9 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] rdata_value_6_10 = 5'ha == io_freadAddr_1_addr ? fregfile_10 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] rdata_value_6_11 = 5'hb == io_freadAddr_1_addr ? fregfile_11 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] rdata_value_6_12 = 5'hc == io_freadAddr_1_addr ? fregfile_12 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] rdata_value_6_13 = 5'hd == io_freadAddr_1_addr ? fregfile_13 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] rdata_value_6_14 = 5'he == io_freadAddr_1_addr ? fregfile_14 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] rdata_value_6_15 = 5'hf == io_freadAddr_1_addr ? fregfile_15 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] rdata_value_6_16 = 5'h10 == io_freadAddr_1_addr ? fregfile_16 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] rdata_value_6_17 = 5'h11 == io_freadAddr_1_addr ? fregfile_17 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] rdata_value_6_18 = 5'h12 == io_freadAddr_1_addr ? fregfile_18 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] rdata_value_6_19 = 5'h13 == io_freadAddr_1_addr ? fregfile_19 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] rdata_value_6_20 = 5'h14 == io_freadAddr_1_addr ? fregfile_20 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] rdata_value_6_21 = 5'h15 == io_freadAddr_1_addr ? fregfile_21 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] rdata_value_6_22 = 5'h16 == io_freadAddr_1_addr ? fregfile_22 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] rdata_value_6_23 = 5'h17 == io_freadAddr_1_addr ? fregfile_23 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] rdata_value_6_24 = 5'h18 == io_freadAddr_1_addr ? fregfile_24 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] rdata_value_6_25 = 5'h19 == io_freadAddr_1_addr ? fregfile_25 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] rdata_value_6_26 = 5'h1a == io_freadAddr_1_addr ? fregfile_26 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] rdata_value_6_27 = 5'h1b == io_freadAddr_1_addr ? fregfile_27 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] rdata_value_6_28 = 5'h1c == io_freadAddr_1_addr ? fregfile_28 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] rdata_value_6_29 = 5'h1d == io_freadAddr_1_addr ? fregfile_29 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] rdata_value_6_30 = 5'h1e == io_freadAddr_1_addr ? fregfile_30 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] rdata_value_6_31 = 5'h1f == io_freadAddr_1_addr ? fregfile_31 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] rdata_value_7_0 = rdata_value_6_0 | rdata_value_6_1; // @[Library.scala 115:37]
-  wire [31:0] rdata_value_7_1 = rdata_value_6_2 | rdata_value_6_3; // @[Library.scala 115:37]
-  wire [31:0] rdata_value_7_2 = rdata_value_6_4 | rdata_value_6_5; // @[Library.scala 115:37]
-  wire [31:0] rdata_value_7_3 = rdata_value_6_6 | rdata_value_6_7; // @[Library.scala 115:37]
-  wire [31:0] rdata_value_7_4 = rdata_value_6_8 | rdata_value_6_9; // @[Library.scala 115:37]
-  wire [31:0] rdata_value_7_5 = rdata_value_6_10 | rdata_value_6_11; // @[Library.scala 115:37]
-  wire [31:0] rdata_value_7_6 = rdata_value_6_12 | rdata_value_6_13; // @[Library.scala 115:37]
-  wire [31:0] rdata_value_7_7 = rdata_value_6_14 | rdata_value_6_15; // @[Library.scala 115:37]
-  wire [31:0] rdata_value_7_8 = rdata_value_6_16 | rdata_value_6_17; // @[Library.scala 115:37]
-  wire [31:0] rdata_value_7_9 = rdata_value_6_18 | rdata_value_6_19; // @[Library.scala 115:37]
-  wire [31:0] rdata_value_7_10 = rdata_value_6_20 | rdata_value_6_21; // @[Library.scala 115:37]
-  wire [31:0] rdata_value_7_11 = rdata_value_6_22 | rdata_value_6_23; // @[Library.scala 115:37]
-  wire [31:0] rdata_value_7_12 = rdata_value_6_24 | rdata_value_6_25; // @[Library.scala 115:37]
-  wire [31:0] rdata_value_7_13 = rdata_value_6_26 | rdata_value_6_27; // @[Library.scala 115:37]
-  wire [31:0] rdata_value_7_14 = rdata_value_6_28 | rdata_value_6_29; // @[Library.scala 115:37]
-  wire [31:0] rdata_value_7_15 = rdata_value_6_30 | rdata_value_6_31; // @[Library.scala 115:37]
-  wire [31:0] rdata_value_8_0 = rdata_value_7_0 | rdata_value_7_1; // @[Library.scala 115:37]
-  wire [31:0] rdata_value_8_1 = rdata_value_7_2 | rdata_value_7_3; // @[Library.scala 115:37]
-  wire [31:0] rdata_value_8_2 = rdata_value_7_4 | rdata_value_7_5; // @[Library.scala 115:37]
-  wire [31:0] rdata_value_8_3 = rdata_value_7_6 | rdata_value_7_7; // @[Library.scala 115:37]
-  wire [31:0] rdata_value_8_4 = rdata_value_7_8 | rdata_value_7_9; // @[Library.scala 115:37]
-  wire [31:0] rdata_value_8_5 = rdata_value_7_10 | rdata_value_7_11; // @[Library.scala 115:37]
-  wire [31:0] rdata_value_8_6 = rdata_value_7_12 | rdata_value_7_13; // @[Library.scala 115:37]
-  wire [31:0] rdata_value_8_7 = rdata_value_7_14 | rdata_value_7_15; // @[Library.scala 115:37]
-  wire [31:0] rdata_value_9_0 = rdata_value_8_0 | rdata_value_8_1; // @[Library.scala 115:37]
-  wire [31:0] rdata_value_9_1 = rdata_value_8_2 | rdata_value_8_3; // @[Library.scala 115:37]
-  wire [31:0] rdata_value_9_2 = rdata_value_8_4 | rdata_value_8_5; // @[Library.scala 115:37]
-  wire [31:0] rdata_value_9_3 = rdata_value_8_6 | rdata_value_8_7; // @[Library.scala 115:37]
-  wire [31:0] rdata_value_10_0 = rdata_value_9_0 | rdata_value_9_1; // @[Library.scala 115:37]
-  wire [31:0] rdata_value_10_1 = rdata_value_9_2 | rdata_value_9_3; // @[Library.scala 115:37]
-  wire [31:0] rdata_value_11_0 = rdata_value_10_0 | rdata_value_10_1; // @[Library.scala 115:37]
-  wire [31:0] wdata_value_6_0 = 5'h0 == io_freadAddr_1_addr ? data : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] wdata_value_6_1 = 5'h1 == io_freadAddr_1_addr ? data_1 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] wdata_value_6_2 = 5'h2 == io_freadAddr_1_addr ? data_2 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] wdata_value_6_3 = 5'h3 == io_freadAddr_1_addr ? data_3 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] wdata_value_6_4 = 5'h4 == io_freadAddr_1_addr ? data_4 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] wdata_value_6_5 = 5'h5 == io_freadAddr_1_addr ? data_5 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] wdata_value_6_6 = 5'h6 == io_freadAddr_1_addr ? data_6 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] wdata_value_6_7 = 5'h7 == io_freadAddr_1_addr ? data_7 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] wdata_value_6_8 = 5'h8 == io_freadAddr_1_addr ? data_8 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] wdata_value_6_9 = 5'h9 == io_freadAddr_1_addr ? data_9 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] wdata_value_6_10 = 5'ha == io_freadAddr_1_addr ? data_10 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] wdata_value_6_11 = 5'hb == io_freadAddr_1_addr ? data_11 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] wdata_value_6_12 = 5'hc == io_freadAddr_1_addr ? data_12 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] wdata_value_6_13 = 5'hd == io_freadAddr_1_addr ? data_13 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] wdata_value_6_14 = 5'he == io_freadAddr_1_addr ? data_14 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] wdata_value_6_15 = 5'hf == io_freadAddr_1_addr ? data_15 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] wdata_value_6_16 = 5'h10 == io_freadAddr_1_addr ? data_16 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] wdata_value_6_17 = 5'h11 == io_freadAddr_1_addr ? data_17 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] wdata_value_6_18 = 5'h12 == io_freadAddr_1_addr ? data_18 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] wdata_value_6_19 = 5'h13 == io_freadAddr_1_addr ? data_19 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] wdata_value_6_20 = 5'h14 == io_freadAddr_1_addr ? data_20 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] wdata_value_6_21 = 5'h15 == io_freadAddr_1_addr ? data_21 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] wdata_value_6_22 = 5'h16 == io_freadAddr_1_addr ? data_22 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] wdata_value_6_23 = 5'h17 == io_freadAddr_1_addr ? data_23 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] wdata_value_6_24 = 5'h18 == io_freadAddr_1_addr ? data_24 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] wdata_value_6_25 = 5'h19 == io_freadAddr_1_addr ? data_25 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] wdata_value_6_26 = 5'h1a == io_freadAddr_1_addr ? data_26 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] wdata_value_6_27 = 5'h1b == io_freadAddr_1_addr ? data_27 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] wdata_value_6_28 = 5'h1c == io_freadAddr_1_addr ? data_28 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] wdata_value_6_29 = 5'h1d == io_freadAddr_1_addr ? data_29 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] wdata_value_6_30 = 5'h1e == io_freadAddr_1_addr ? data_30 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] wdata_value_6_31 = 5'h1f == io_freadAddr_1_addr ? data_31 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] wdata_value_7_0 = wdata_value_6_0 | wdata_value_6_1; // @[Library.scala 115:37]
-  wire [31:0] wdata_value_7_1 = wdata_value_6_2 | wdata_value_6_3; // @[Library.scala 115:37]
-  wire [31:0] wdata_value_7_2 = wdata_value_6_4 | wdata_value_6_5; // @[Library.scala 115:37]
-  wire [31:0] wdata_value_7_3 = wdata_value_6_6 | wdata_value_6_7; // @[Library.scala 115:37]
-  wire [31:0] wdata_value_7_4 = wdata_value_6_8 | wdata_value_6_9; // @[Library.scala 115:37]
-  wire [31:0] wdata_value_7_5 = wdata_value_6_10 | wdata_value_6_11; // @[Library.scala 115:37]
-  wire [31:0] wdata_value_7_6 = wdata_value_6_12 | wdata_value_6_13; // @[Library.scala 115:37]
-  wire [31:0] wdata_value_7_7 = wdata_value_6_14 | wdata_value_6_15; // @[Library.scala 115:37]
-  wire [31:0] wdata_value_7_8 = wdata_value_6_16 | wdata_value_6_17; // @[Library.scala 115:37]
-  wire [31:0] wdata_value_7_9 = wdata_value_6_18 | wdata_value_6_19; // @[Library.scala 115:37]
-  wire [31:0] wdata_value_7_10 = wdata_value_6_20 | wdata_value_6_21; // @[Library.scala 115:37]
-  wire [31:0] wdata_value_7_11 = wdata_value_6_22 | wdata_value_6_23; // @[Library.scala 115:37]
-  wire [31:0] wdata_value_7_12 = wdata_value_6_24 | wdata_value_6_25; // @[Library.scala 115:37]
-  wire [31:0] wdata_value_7_13 = wdata_value_6_26 | wdata_value_6_27; // @[Library.scala 115:37]
-  wire [31:0] wdata_value_7_14 = wdata_value_6_28 | wdata_value_6_29; // @[Library.scala 115:37]
-  wire [31:0] wdata_value_7_15 = wdata_value_6_30 | wdata_value_6_31; // @[Library.scala 115:37]
-  wire [31:0] wdata_value_8_0 = wdata_value_7_0 | wdata_value_7_1; // @[Library.scala 115:37]
-  wire [31:0] wdata_value_8_1 = wdata_value_7_2 | wdata_value_7_3; // @[Library.scala 115:37]
-  wire [31:0] wdata_value_8_2 = wdata_value_7_4 | wdata_value_7_5; // @[Library.scala 115:37]
-  wire [31:0] wdata_value_8_3 = wdata_value_7_6 | wdata_value_7_7; // @[Library.scala 115:37]
-  wire [31:0] wdata_value_8_4 = wdata_value_7_8 | wdata_value_7_9; // @[Library.scala 115:37]
-  wire [31:0] wdata_value_8_5 = wdata_value_7_10 | wdata_value_7_11; // @[Library.scala 115:37]
-  wire [31:0] wdata_value_8_6 = wdata_value_7_12 | wdata_value_7_13; // @[Library.scala 115:37]
-  wire [31:0] wdata_value_8_7 = wdata_value_7_14 | wdata_value_7_15; // @[Library.scala 115:37]
-  wire [31:0] wdata_value_9_0 = wdata_value_8_0 | wdata_value_8_1; // @[Library.scala 115:37]
-  wire [31:0] wdata_value_9_1 = wdata_value_8_2 | wdata_value_8_3; // @[Library.scala 115:37]
-  wire [31:0] wdata_value_9_2 = wdata_value_8_4 | wdata_value_8_5; // @[Library.scala 115:37]
-  wire [31:0] wdata_value_9_3 = wdata_value_8_6 | wdata_value_8_7; // @[Library.scala 115:37]
-  wire [31:0] wdata_value_10_0 = wdata_value_9_0 | wdata_value_9_1; // @[Library.scala 115:37]
-  wire [31:0] wdata_value_10_1 = wdata_value_9_2 | wdata_value_9_3; // @[Library.scala 115:37]
-  wire [31:0] wdata_value_11_0 = wdata_value_10_0 | wdata_value_10_1; // @[Library.scala 115:37]
-  wire  write_value_12_0 = 5'h0 == io_freadAddr_2_addr & fwriteValid_0; // @[Library.scala 101:22]
-  wire  write_value_12_1 = 5'h1 == io_freadAddr_2_addr & fwriteValid_1; // @[Library.scala 101:22]
-  wire  write_value_12_2 = 5'h2 == io_freadAddr_2_addr & fwriteValid_2; // @[Library.scala 101:22]
-  wire  write_value_12_3 = 5'h3 == io_freadAddr_2_addr & fwriteValid_3; // @[Library.scala 101:22]
-  wire  write_value_12_4 = 5'h4 == io_freadAddr_2_addr & fwriteValid_4; // @[Library.scala 101:22]
-  wire  write_value_12_5 = 5'h5 == io_freadAddr_2_addr & fwriteValid_5; // @[Library.scala 101:22]
-  wire  write_value_12_6 = 5'h6 == io_freadAddr_2_addr & fwriteValid_6; // @[Library.scala 101:22]
-  wire  write_value_12_7 = 5'h7 == io_freadAddr_2_addr & fwriteValid_7; // @[Library.scala 101:22]
-  wire  write_value_12_8 = 5'h8 == io_freadAddr_2_addr & fwriteValid_8; // @[Library.scala 101:22]
-  wire  write_value_12_9 = 5'h9 == io_freadAddr_2_addr & fwriteValid_9; // @[Library.scala 101:22]
-  wire  write_value_12_10 = 5'ha == io_freadAddr_2_addr & fwriteValid_10; // @[Library.scala 101:22]
-  wire  write_value_12_11 = 5'hb == io_freadAddr_2_addr & fwriteValid_11; // @[Library.scala 101:22]
-  wire  write_value_12_12 = 5'hc == io_freadAddr_2_addr & fwriteValid_12; // @[Library.scala 101:22]
-  wire  write_value_12_13 = 5'hd == io_freadAddr_2_addr & fwriteValid_13; // @[Library.scala 101:22]
-  wire  write_value_12_14 = 5'he == io_freadAddr_2_addr & fwriteValid_14; // @[Library.scala 101:22]
-  wire  write_value_12_15 = 5'hf == io_freadAddr_2_addr & fwriteValid_15; // @[Library.scala 101:22]
-  wire  write_value_12_16 = 5'h10 == io_freadAddr_2_addr & fwriteValid_16; // @[Library.scala 101:22]
-  wire  write_value_12_17 = 5'h11 == io_freadAddr_2_addr & fwriteValid_17; // @[Library.scala 101:22]
-  wire  write_value_12_18 = 5'h12 == io_freadAddr_2_addr & fwriteValid_18; // @[Library.scala 101:22]
-  wire  write_value_12_19 = 5'h13 == io_freadAddr_2_addr & fwriteValid_19; // @[Library.scala 101:22]
-  wire  write_value_12_20 = 5'h14 == io_freadAddr_2_addr & fwriteValid_20; // @[Library.scala 101:22]
-  wire  write_value_12_21 = 5'h15 == io_freadAddr_2_addr & fwriteValid_21; // @[Library.scala 101:22]
-  wire  write_value_12_22 = 5'h16 == io_freadAddr_2_addr & fwriteValid_22; // @[Library.scala 101:22]
-  wire  write_value_12_23 = 5'h17 == io_freadAddr_2_addr & fwriteValid_23; // @[Library.scala 101:22]
-  wire  write_value_12_24 = 5'h18 == io_freadAddr_2_addr & fwriteValid_24; // @[Library.scala 101:22]
-  wire  write_value_12_25 = 5'h19 == io_freadAddr_2_addr & fwriteValid_25; // @[Library.scala 101:22]
-  wire  write_value_12_26 = 5'h1a == io_freadAddr_2_addr & fwriteValid_26; // @[Library.scala 101:22]
-  wire  write_value_12_27 = 5'h1b == io_freadAddr_2_addr & fwriteValid_27; // @[Library.scala 101:22]
-  wire  write_value_12_28 = 5'h1c == io_freadAddr_2_addr & fwriteValid_28; // @[Library.scala 101:22]
-  wire  write_value_12_29 = 5'h1d == io_freadAddr_2_addr & fwriteValid_29; // @[Library.scala 101:22]
-  wire  write_value_12_30 = 5'h1e == io_freadAddr_2_addr & fwriteValid_30; // @[Library.scala 101:22]
-  wire  write_value_12_31 = 5'h1f == io_freadAddr_2_addr & fwriteValid_31; // @[Library.scala 101:22]
-  wire  write_value_13_0 = write_value_12_0 | write_value_12_1; // @[Library.scala 115:37]
-  wire  write_value_13_1 = write_value_12_2 | write_value_12_3; // @[Library.scala 115:37]
-  wire  write_value_13_2 = write_value_12_4 | write_value_12_5; // @[Library.scala 115:37]
-  wire  write_value_13_3 = write_value_12_6 | write_value_12_7; // @[Library.scala 115:37]
-  wire  write_value_13_4 = write_value_12_8 | write_value_12_9; // @[Library.scala 115:37]
-  wire  write_value_13_5 = write_value_12_10 | write_value_12_11; // @[Library.scala 115:37]
-  wire  write_value_13_6 = write_value_12_12 | write_value_12_13; // @[Library.scala 115:37]
-  wire  write_value_13_7 = write_value_12_14 | write_value_12_15; // @[Library.scala 115:37]
-  wire  write_value_13_8 = write_value_12_16 | write_value_12_17; // @[Library.scala 115:37]
-  wire  write_value_13_9 = write_value_12_18 | write_value_12_19; // @[Library.scala 115:37]
-  wire  write_value_13_10 = write_value_12_20 | write_value_12_21; // @[Library.scala 115:37]
-  wire  write_value_13_11 = write_value_12_22 | write_value_12_23; // @[Library.scala 115:37]
-  wire  write_value_13_12 = write_value_12_24 | write_value_12_25; // @[Library.scala 115:37]
-  wire  write_value_13_13 = write_value_12_26 | write_value_12_27; // @[Library.scala 115:37]
-  wire  write_value_13_14 = write_value_12_28 | write_value_12_29; // @[Library.scala 115:37]
-  wire  write_value_13_15 = write_value_12_30 | write_value_12_31; // @[Library.scala 115:37]
-  wire  write_value_14_0 = write_value_13_0 | write_value_13_1; // @[Library.scala 115:37]
-  wire  write_value_14_1 = write_value_13_2 | write_value_13_3; // @[Library.scala 115:37]
-  wire  write_value_14_2 = write_value_13_4 | write_value_13_5; // @[Library.scala 115:37]
-  wire  write_value_14_3 = write_value_13_6 | write_value_13_7; // @[Library.scala 115:37]
-  wire  write_value_14_4 = write_value_13_8 | write_value_13_9; // @[Library.scala 115:37]
-  wire  write_value_14_5 = write_value_13_10 | write_value_13_11; // @[Library.scala 115:37]
-  wire  write_value_14_6 = write_value_13_12 | write_value_13_13; // @[Library.scala 115:37]
-  wire  write_value_14_7 = write_value_13_14 | write_value_13_15; // @[Library.scala 115:37]
-  wire  write_value_15_0 = write_value_14_0 | write_value_14_1; // @[Library.scala 115:37]
-  wire  write_value_15_1 = write_value_14_2 | write_value_14_3; // @[Library.scala 115:37]
-  wire  write_value_15_2 = write_value_14_4 | write_value_14_5; // @[Library.scala 115:37]
-  wire  write_value_15_3 = write_value_14_6 | write_value_14_7; // @[Library.scala 115:37]
-  wire  write_value_16_0 = write_value_15_0 | write_value_15_1; // @[Library.scala 115:37]
-  wire  write_value_16_1 = write_value_15_2 | write_value_15_3; // @[Library.scala 115:37]
-  wire  write_value_17_0 = write_value_16_0 | write_value_16_1; // @[Library.scala 115:37]
-  wire [31:0] rdata_value_12_0 = 5'h0 == io_freadAddr_2_addr ? fregfile_0 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] rdata_value_12_1 = 5'h1 == io_freadAddr_2_addr ? fregfile_1 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] rdata_value_12_2 = 5'h2 == io_freadAddr_2_addr ? fregfile_2 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] rdata_value_12_3 = 5'h3 == io_freadAddr_2_addr ? fregfile_3 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] rdata_value_12_4 = 5'h4 == io_freadAddr_2_addr ? fregfile_4 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] rdata_value_12_5 = 5'h5 == io_freadAddr_2_addr ? fregfile_5 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] rdata_value_12_6 = 5'h6 == io_freadAddr_2_addr ? fregfile_6 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] rdata_value_12_7 = 5'h7 == io_freadAddr_2_addr ? fregfile_7 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] rdata_value_12_8 = 5'h8 == io_freadAddr_2_addr ? fregfile_8 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] rdata_value_12_9 = 5'h9 == io_freadAddr_2_addr ? fregfile_9 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] rdata_value_12_10 = 5'ha == io_freadAddr_2_addr ? fregfile_10 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] rdata_value_12_11 = 5'hb == io_freadAddr_2_addr ? fregfile_11 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] rdata_value_12_12 = 5'hc == io_freadAddr_2_addr ? fregfile_12 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] rdata_value_12_13 = 5'hd == io_freadAddr_2_addr ? fregfile_13 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] rdata_value_12_14 = 5'he == io_freadAddr_2_addr ? fregfile_14 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] rdata_value_12_15 = 5'hf == io_freadAddr_2_addr ? fregfile_15 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] rdata_value_12_16 = 5'h10 == io_freadAddr_2_addr ? fregfile_16 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] rdata_value_12_17 = 5'h11 == io_freadAddr_2_addr ? fregfile_17 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] rdata_value_12_18 = 5'h12 == io_freadAddr_2_addr ? fregfile_18 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] rdata_value_12_19 = 5'h13 == io_freadAddr_2_addr ? fregfile_19 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] rdata_value_12_20 = 5'h14 == io_freadAddr_2_addr ? fregfile_20 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] rdata_value_12_21 = 5'h15 == io_freadAddr_2_addr ? fregfile_21 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] rdata_value_12_22 = 5'h16 == io_freadAddr_2_addr ? fregfile_22 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] rdata_value_12_23 = 5'h17 == io_freadAddr_2_addr ? fregfile_23 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] rdata_value_12_24 = 5'h18 == io_freadAddr_2_addr ? fregfile_24 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] rdata_value_12_25 = 5'h19 == io_freadAddr_2_addr ? fregfile_25 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] rdata_value_12_26 = 5'h1a == io_freadAddr_2_addr ? fregfile_26 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] rdata_value_12_27 = 5'h1b == io_freadAddr_2_addr ? fregfile_27 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] rdata_value_12_28 = 5'h1c == io_freadAddr_2_addr ? fregfile_28 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] rdata_value_12_29 = 5'h1d == io_freadAddr_2_addr ? fregfile_29 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] rdata_value_12_30 = 5'h1e == io_freadAddr_2_addr ? fregfile_30 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] rdata_value_12_31 = 5'h1f == io_freadAddr_2_addr ? fregfile_31 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] rdata_value_13_0 = rdata_value_12_0 | rdata_value_12_1; // @[Library.scala 115:37]
-  wire [31:0] rdata_value_13_1 = rdata_value_12_2 | rdata_value_12_3; // @[Library.scala 115:37]
-  wire [31:0] rdata_value_13_2 = rdata_value_12_4 | rdata_value_12_5; // @[Library.scala 115:37]
-  wire [31:0] rdata_value_13_3 = rdata_value_12_6 | rdata_value_12_7; // @[Library.scala 115:37]
-  wire [31:0] rdata_value_13_4 = rdata_value_12_8 | rdata_value_12_9; // @[Library.scala 115:37]
-  wire [31:0] rdata_value_13_5 = rdata_value_12_10 | rdata_value_12_11; // @[Library.scala 115:37]
-  wire [31:0] rdata_value_13_6 = rdata_value_12_12 | rdata_value_12_13; // @[Library.scala 115:37]
-  wire [31:0] rdata_value_13_7 = rdata_value_12_14 | rdata_value_12_15; // @[Library.scala 115:37]
-  wire [31:0] rdata_value_13_8 = rdata_value_12_16 | rdata_value_12_17; // @[Library.scala 115:37]
-  wire [31:0] rdata_value_13_9 = rdata_value_12_18 | rdata_value_12_19; // @[Library.scala 115:37]
-  wire [31:0] rdata_value_13_10 = rdata_value_12_20 | rdata_value_12_21; // @[Library.scala 115:37]
-  wire [31:0] rdata_value_13_11 = rdata_value_12_22 | rdata_value_12_23; // @[Library.scala 115:37]
-  wire [31:0] rdata_value_13_12 = rdata_value_12_24 | rdata_value_12_25; // @[Library.scala 115:37]
-  wire [31:0] rdata_value_13_13 = rdata_value_12_26 | rdata_value_12_27; // @[Library.scala 115:37]
-  wire [31:0] rdata_value_13_14 = rdata_value_12_28 | rdata_value_12_29; // @[Library.scala 115:37]
-  wire [31:0] rdata_value_13_15 = rdata_value_12_30 | rdata_value_12_31; // @[Library.scala 115:37]
-  wire [31:0] rdata_value_14_0 = rdata_value_13_0 | rdata_value_13_1; // @[Library.scala 115:37]
-  wire [31:0] rdata_value_14_1 = rdata_value_13_2 | rdata_value_13_3; // @[Library.scala 115:37]
-  wire [31:0] rdata_value_14_2 = rdata_value_13_4 | rdata_value_13_5; // @[Library.scala 115:37]
-  wire [31:0] rdata_value_14_3 = rdata_value_13_6 | rdata_value_13_7; // @[Library.scala 115:37]
-  wire [31:0] rdata_value_14_4 = rdata_value_13_8 | rdata_value_13_9; // @[Library.scala 115:37]
-  wire [31:0] rdata_value_14_5 = rdata_value_13_10 | rdata_value_13_11; // @[Library.scala 115:37]
-  wire [31:0] rdata_value_14_6 = rdata_value_13_12 | rdata_value_13_13; // @[Library.scala 115:37]
-  wire [31:0] rdata_value_14_7 = rdata_value_13_14 | rdata_value_13_15; // @[Library.scala 115:37]
-  wire [31:0] rdata_value_15_0 = rdata_value_14_0 | rdata_value_14_1; // @[Library.scala 115:37]
-  wire [31:0] rdata_value_15_1 = rdata_value_14_2 | rdata_value_14_3; // @[Library.scala 115:37]
-  wire [31:0] rdata_value_15_2 = rdata_value_14_4 | rdata_value_14_5; // @[Library.scala 115:37]
-  wire [31:0] rdata_value_15_3 = rdata_value_14_6 | rdata_value_14_7; // @[Library.scala 115:37]
-  wire [31:0] rdata_value_16_0 = rdata_value_15_0 | rdata_value_15_1; // @[Library.scala 115:37]
-  wire [31:0] rdata_value_16_1 = rdata_value_15_2 | rdata_value_15_3; // @[Library.scala 115:37]
-  wire [31:0] rdata_value_17_0 = rdata_value_16_0 | rdata_value_16_1; // @[Library.scala 115:37]
-  wire [31:0] wdata_value_12_0 = 5'h0 == io_freadAddr_2_addr ? data : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] wdata_value_12_1 = 5'h1 == io_freadAddr_2_addr ? data_1 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] wdata_value_12_2 = 5'h2 == io_freadAddr_2_addr ? data_2 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] wdata_value_12_3 = 5'h3 == io_freadAddr_2_addr ? data_3 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] wdata_value_12_4 = 5'h4 == io_freadAddr_2_addr ? data_4 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] wdata_value_12_5 = 5'h5 == io_freadAddr_2_addr ? data_5 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] wdata_value_12_6 = 5'h6 == io_freadAddr_2_addr ? data_6 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] wdata_value_12_7 = 5'h7 == io_freadAddr_2_addr ? data_7 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] wdata_value_12_8 = 5'h8 == io_freadAddr_2_addr ? data_8 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] wdata_value_12_9 = 5'h9 == io_freadAddr_2_addr ? data_9 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] wdata_value_12_10 = 5'ha == io_freadAddr_2_addr ? data_10 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] wdata_value_12_11 = 5'hb == io_freadAddr_2_addr ? data_11 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] wdata_value_12_12 = 5'hc == io_freadAddr_2_addr ? data_12 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] wdata_value_12_13 = 5'hd == io_freadAddr_2_addr ? data_13 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] wdata_value_12_14 = 5'he == io_freadAddr_2_addr ? data_14 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] wdata_value_12_15 = 5'hf == io_freadAddr_2_addr ? data_15 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] wdata_value_12_16 = 5'h10 == io_freadAddr_2_addr ? data_16 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] wdata_value_12_17 = 5'h11 == io_freadAddr_2_addr ? data_17 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] wdata_value_12_18 = 5'h12 == io_freadAddr_2_addr ? data_18 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] wdata_value_12_19 = 5'h13 == io_freadAddr_2_addr ? data_19 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] wdata_value_12_20 = 5'h14 == io_freadAddr_2_addr ? data_20 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] wdata_value_12_21 = 5'h15 == io_freadAddr_2_addr ? data_21 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] wdata_value_12_22 = 5'h16 == io_freadAddr_2_addr ? data_22 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] wdata_value_12_23 = 5'h17 == io_freadAddr_2_addr ? data_23 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] wdata_value_12_24 = 5'h18 == io_freadAddr_2_addr ? data_24 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] wdata_value_12_25 = 5'h19 == io_freadAddr_2_addr ? data_25 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] wdata_value_12_26 = 5'h1a == io_freadAddr_2_addr ? data_26 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] wdata_value_12_27 = 5'h1b == io_freadAddr_2_addr ? data_27 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] wdata_value_12_28 = 5'h1c == io_freadAddr_2_addr ? data_28 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] wdata_value_12_29 = 5'h1d == io_freadAddr_2_addr ? data_29 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] wdata_value_12_30 = 5'h1e == io_freadAddr_2_addr ? data_30 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] wdata_value_12_31 = 5'h1f == io_freadAddr_2_addr ? data_31 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] wdata_value_13_0 = wdata_value_12_0 | wdata_value_12_1; // @[Library.scala 115:37]
-  wire [31:0] wdata_value_13_1 = wdata_value_12_2 | wdata_value_12_3; // @[Library.scala 115:37]
-  wire [31:0] wdata_value_13_2 = wdata_value_12_4 | wdata_value_12_5; // @[Library.scala 115:37]
-  wire [31:0] wdata_value_13_3 = wdata_value_12_6 | wdata_value_12_7; // @[Library.scala 115:37]
-  wire [31:0] wdata_value_13_4 = wdata_value_12_8 | wdata_value_12_9; // @[Library.scala 115:37]
-  wire [31:0] wdata_value_13_5 = wdata_value_12_10 | wdata_value_12_11; // @[Library.scala 115:37]
-  wire [31:0] wdata_value_13_6 = wdata_value_12_12 | wdata_value_12_13; // @[Library.scala 115:37]
-  wire [31:0] wdata_value_13_7 = wdata_value_12_14 | wdata_value_12_15; // @[Library.scala 115:37]
-  wire [31:0] wdata_value_13_8 = wdata_value_12_16 | wdata_value_12_17; // @[Library.scala 115:37]
-  wire [31:0] wdata_value_13_9 = wdata_value_12_18 | wdata_value_12_19; // @[Library.scala 115:37]
-  wire [31:0] wdata_value_13_10 = wdata_value_12_20 | wdata_value_12_21; // @[Library.scala 115:37]
-  wire [31:0] wdata_value_13_11 = wdata_value_12_22 | wdata_value_12_23; // @[Library.scala 115:37]
-  wire [31:0] wdata_value_13_12 = wdata_value_12_24 | wdata_value_12_25; // @[Library.scala 115:37]
-  wire [31:0] wdata_value_13_13 = wdata_value_12_26 | wdata_value_12_27; // @[Library.scala 115:37]
-  wire [31:0] wdata_value_13_14 = wdata_value_12_28 | wdata_value_12_29; // @[Library.scala 115:37]
-  wire [31:0] wdata_value_13_15 = wdata_value_12_30 | wdata_value_12_31; // @[Library.scala 115:37]
-  wire [31:0] wdata_value_14_0 = wdata_value_13_0 | wdata_value_13_1; // @[Library.scala 115:37]
-  wire [31:0] wdata_value_14_1 = wdata_value_13_2 | wdata_value_13_3; // @[Library.scala 115:37]
-  wire [31:0] wdata_value_14_2 = wdata_value_13_4 | wdata_value_13_5; // @[Library.scala 115:37]
-  wire [31:0] wdata_value_14_3 = wdata_value_13_6 | wdata_value_13_7; // @[Library.scala 115:37]
-  wire [31:0] wdata_value_14_4 = wdata_value_13_8 | wdata_value_13_9; // @[Library.scala 115:37]
-  wire [31:0] wdata_value_14_5 = wdata_value_13_10 | wdata_value_13_11; // @[Library.scala 115:37]
-  wire [31:0] wdata_value_14_6 = wdata_value_13_12 | wdata_value_13_13; // @[Library.scala 115:37]
-  wire [31:0] wdata_value_14_7 = wdata_value_13_14 | wdata_value_13_15; // @[Library.scala 115:37]
-  wire [31:0] wdata_value_15_0 = wdata_value_14_0 | wdata_value_14_1; // @[Library.scala 115:37]
-  wire [31:0] wdata_value_15_1 = wdata_value_14_2 | wdata_value_14_3; // @[Library.scala 115:37]
-  wire [31:0] wdata_value_15_2 = wdata_value_14_4 | wdata_value_14_5; // @[Library.scala 115:37]
-  wire [31:0] wdata_value_15_3 = wdata_value_14_6 | wdata_value_14_7; // @[Library.scala 115:37]
-  wire [31:0] wdata_value_16_0 = wdata_value_15_0 | wdata_value_15_1; // @[Library.scala 115:37]
-  wire [31:0] wdata_value_16_1 = wdata_value_15_2 | wdata_value_15_3; // @[Library.scala 115:37]
-  wire [31:0] wdata_value_17_0 = wdata_value_16_0 | wdata_value_16_1; // @[Library.scala 115:37]
-  wire  write_value_18_0 = 5'h0 == io_freadAddr_3_addr & fwriteValid_0; // @[Library.scala 101:22]
-  wire  write_value_18_1 = 5'h1 == io_freadAddr_3_addr & fwriteValid_1; // @[Library.scala 101:22]
-  wire  write_value_18_2 = 5'h2 == io_freadAddr_3_addr & fwriteValid_2; // @[Library.scala 101:22]
-  wire  write_value_18_3 = 5'h3 == io_freadAddr_3_addr & fwriteValid_3; // @[Library.scala 101:22]
-  wire  write_value_18_4 = 5'h4 == io_freadAddr_3_addr & fwriteValid_4; // @[Library.scala 101:22]
-  wire  write_value_18_5 = 5'h5 == io_freadAddr_3_addr & fwriteValid_5; // @[Library.scala 101:22]
-  wire  write_value_18_6 = 5'h6 == io_freadAddr_3_addr & fwriteValid_6; // @[Library.scala 101:22]
-  wire  write_value_18_7 = 5'h7 == io_freadAddr_3_addr & fwriteValid_7; // @[Library.scala 101:22]
-  wire  write_value_18_8 = 5'h8 == io_freadAddr_3_addr & fwriteValid_8; // @[Library.scala 101:22]
-  wire  write_value_18_9 = 5'h9 == io_freadAddr_3_addr & fwriteValid_9; // @[Library.scala 101:22]
-  wire  write_value_18_10 = 5'ha == io_freadAddr_3_addr & fwriteValid_10; // @[Library.scala 101:22]
-  wire  write_value_18_11 = 5'hb == io_freadAddr_3_addr & fwriteValid_11; // @[Library.scala 101:22]
-  wire  write_value_18_12 = 5'hc == io_freadAddr_3_addr & fwriteValid_12; // @[Library.scala 101:22]
-  wire  write_value_18_13 = 5'hd == io_freadAddr_3_addr & fwriteValid_13; // @[Library.scala 101:22]
-  wire  write_value_18_14 = 5'he == io_freadAddr_3_addr & fwriteValid_14; // @[Library.scala 101:22]
-  wire  write_value_18_15 = 5'hf == io_freadAddr_3_addr & fwriteValid_15; // @[Library.scala 101:22]
-  wire  write_value_18_16 = 5'h10 == io_freadAddr_3_addr & fwriteValid_16; // @[Library.scala 101:22]
-  wire  write_value_18_17 = 5'h11 == io_freadAddr_3_addr & fwriteValid_17; // @[Library.scala 101:22]
-  wire  write_value_18_18 = 5'h12 == io_freadAddr_3_addr & fwriteValid_18; // @[Library.scala 101:22]
-  wire  write_value_18_19 = 5'h13 == io_freadAddr_3_addr & fwriteValid_19; // @[Library.scala 101:22]
-  wire  write_value_18_20 = 5'h14 == io_freadAddr_3_addr & fwriteValid_20; // @[Library.scala 101:22]
-  wire  write_value_18_21 = 5'h15 == io_freadAddr_3_addr & fwriteValid_21; // @[Library.scala 101:22]
-  wire  write_value_18_22 = 5'h16 == io_freadAddr_3_addr & fwriteValid_22; // @[Library.scala 101:22]
-  wire  write_value_18_23 = 5'h17 == io_freadAddr_3_addr & fwriteValid_23; // @[Library.scala 101:22]
-  wire  write_value_18_24 = 5'h18 == io_freadAddr_3_addr & fwriteValid_24; // @[Library.scala 101:22]
-  wire  write_value_18_25 = 5'h19 == io_freadAddr_3_addr & fwriteValid_25; // @[Library.scala 101:22]
-  wire  write_value_18_26 = 5'h1a == io_freadAddr_3_addr & fwriteValid_26; // @[Library.scala 101:22]
-  wire  write_value_18_27 = 5'h1b == io_freadAddr_3_addr & fwriteValid_27; // @[Library.scala 101:22]
-  wire  write_value_18_28 = 5'h1c == io_freadAddr_3_addr & fwriteValid_28; // @[Library.scala 101:22]
-  wire  write_value_18_29 = 5'h1d == io_freadAddr_3_addr & fwriteValid_29; // @[Library.scala 101:22]
-  wire  write_value_18_30 = 5'h1e == io_freadAddr_3_addr & fwriteValid_30; // @[Library.scala 101:22]
-  wire  write_value_18_31 = 5'h1f == io_freadAddr_3_addr & fwriteValid_31; // @[Library.scala 101:22]
-  wire  write_value_19_0 = write_value_18_0 | write_value_18_1; // @[Library.scala 115:37]
-  wire  write_value_19_1 = write_value_18_2 | write_value_18_3; // @[Library.scala 115:37]
-  wire  write_value_19_2 = write_value_18_4 | write_value_18_5; // @[Library.scala 115:37]
-  wire  write_value_19_3 = write_value_18_6 | write_value_18_7; // @[Library.scala 115:37]
-  wire  write_value_19_4 = write_value_18_8 | write_value_18_9; // @[Library.scala 115:37]
-  wire  write_value_19_5 = write_value_18_10 | write_value_18_11; // @[Library.scala 115:37]
-  wire  write_value_19_6 = write_value_18_12 | write_value_18_13; // @[Library.scala 115:37]
-  wire  write_value_19_7 = write_value_18_14 | write_value_18_15; // @[Library.scala 115:37]
-  wire  write_value_19_8 = write_value_18_16 | write_value_18_17; // @[Library.scala 115:37]
-  wire  write_value_19_9 = write_value_18_18 | write_value_18_19; // @[Library.scala 115:37]
-  wire  write_value_19_10 = write_value_18_20 | write_value_18_21; // @[Library.scala 115:37]
-  wire  write_value_19_11 = write_value_18_22 | write_value_18_23; // @[Library.scala 115:37]
-  wire  write_value_19_12 = write_value_18_24 | write_value_18_25; // @[Library.scala 115:37]
-  wire  write_value_19_13 = write_value_18_26 | write_value_18_27; // @[Library.scala 115:37]
-  wire  write_value_19_14 = write_value_18_28 | write_value_18_29; // @[Library.scala 115:37]
-  wire  write_value_19_15 = write_value_18_30 | write_value_18_31; // @[Library.scala 115:37]
-  wire  write_value_20_0 = write_value_19_0 | write_value_19_1; // @[Library.scala 115:37]
-  wire  write_value_20_1 = write_value_19_2 | write_value_19_3; // @[Library.scala 115:37]
-  wire  write_value_20_2 = write_value_19_4 | write_value_19_5; // @[Library.scala 115:37]
-  wire  write_value_20_3 = write_value_19_6 | write_value_19_7; // @[Library.scala 115:37]
-  wire  write_value_20_4 = write_value_19_8 | write_value_19_9; // @[Library.scala 115:37]
-  wire  write_value_20_5 = write_value_19_10 | write_value_19_11; // @[Library.scala 115:37]
-  wire  write_value_20_6 = write_value_19_12 | write_value_19_13; // @[Library.scala 115:37]
-  wire  write_value_20_7 = write_value_19_14 | write_value_19_15; // @[Library.scala 115:37]
-  wire  write_value_21_0 = write_value_20_0 | write_value_20_1; // @[Library.scala 115:37]
-  wire  write_value_21_1 = write_value_20_2 | write_value_20_3; // @[Library.scala 115:37]
-  wire  write_value_21_2 = write_value_20_4 | write_value_20_5; // @[Library.scala 115:37]
-  wire  write_value_21_3 = write_value_20_6 | write_value_20_7; // @[Library.scala 115:37]
-  wire  write_value_22_0 = write_value_21_0 | write_value_21_1; // @[Library.scala 115:37]
-  wire  write_value_22_1 = write_value_21_2 | write_value_21_3; // @[Library.scala 115:37]
-  wire  write_value_23_0 = write_value_22_0 | write_value_22_1; // @[Library.scala 115:37]
-  wire [31:0] rdata_value_18_0 = 5'h0 == io_freadAddr_3_addr ? fregfile_0 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] rdata_value_18_1 = 5'h1 == io_freadAddr_3_addr ? fregfile_1 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] rdata_value_18_2 = 5'h2 == io_freadAddr_3_addr ? fregfile_2 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] rdata_value_18_3 = 5'h3 == io_freadAddr_3_addr ? fregfile_3 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] rdata_value_18_4 = 5'h4 == io_freadAddr_3_addr ? fregfile_4 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] rdata_value_18_5 = 5'h5 == io_freadAddr_3_addr ? fregfile_5 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] rdata_value_18_6 = 5'h6 == io_freadAddr_3_addr ? fregfile_6 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] rdata_value_18_7 = 5'h7 == io_freadAddr_3_addr ? fregfile_7 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] rdata_value_18_8 = 5'h8 == io_freadAddr_3_addr ? fregfile_8 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] rdata_value_18_9 = 5'h9 == io_freadAddr_3_addr ? fregfile_9 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] rdata_value_18_10 = 5'ha == io_freadAddr_3_addr ? fregfile_10 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] rdata_value_18_11 = 5'hb == io_freadAddr_3_addr ? fregfile_11 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] rdata_value_18_12 = 5'hc == io_freadAddr_3_addr ? fregfile_12 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] rdata_value_18_13 = 5'hd == io_freadAddr_3_addr ? fregfile_13 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] rdata_value_18_14 = 5'he == io_freadAddr_3_addr ? fregfile_14 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] rdata_value_18_15 = 5'hf == io_freadAddr_3_addr ? fregfile_15 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] rdata_value_18_16 = 5'h10 == io_freadAddr_3_addr ? fregfile_16 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] rdata_value_18_17 = 5'h11 == io_freadAddr_3_addr ? fregfile_17 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] rdata_value_18_18 = 5'h12 == io_freadAddr_3_addr ? fregfile_18 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] rdata_value_18_19 = 5'h13 == io_freadAddr_3_addr ? fregfile_19 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] rdata_value_18_20 = 5'h14 == io_freadAddr_3_addr ? fregfile_20 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] rdata_value_18_21 = 5'h15 == io_freadAddr_3_addr ? fregfile_21 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] rdata_value_18_22 = 5'h16 == io_freadAddr_3_addr ? fregfile_22 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] rdata_value_18_23 = 5'h17 == io_freadAddr_3_addr ? fregfile_23 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] rdata_value_18_24 = 5'h18 == io_freadAddr_3_addr ? fregfile_24 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] rdata_value_18_25 = 5'h19 == io_freadAddr_3_addr ? fregfile_25 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] rdata_value_18_26 = 5'h1a == io_freadAddr_3_addr ? fregfile_26 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] rdata_value_18_27 = 5'h1b == io_freadAddr_3_addr ? fregfile_27 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] rdata_value_18_28 = 5'h1c == io_freadAddr_3_addr ? fregfile_28 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] rdata_value_18_29 = 5'h1d == io_freadAddr_3_addr ? fregfile_29 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] rdata_value_18_30 = 5'h1e == io_freadAddr_3_addr ? fregfile_30 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] rdata_value_18_31 = 5'h1f == io_freadAddr_3_addr ? fregfile_31 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] rdata_value_19_0 = rdata_value_18_0 | rdata_value_18_1; // @[Library.scala 115:37]
-  wire [31:0] rdata_value_19_1 = rdata_value_18_2 | rdata_value_18_3; // @[Library.scala 115:37]
-  wire [31:0] rdata_value_19_2 = rdata_value_18_4 | rdata_value_18_5; // @[Library.scala 115:37]
-  wire [31:0] rdata_value_19_3 = rdata_value_18_6 | rdata_value_18_7; // @[Library.scala 115:37]
-  wire [31:0] rdata_value_19_4 = rdata_value_18_8 | rdata_value_18_9; // @[Library.scala 115:37]
-  wire [31:0] rdata_value_19_5 = rdata_value_18_10 | rdata_value_18_11; // @[Library.scala 115:37]
-  wire [31:0] rdata_value_19_6 = rdata_value_18_12 | rdata_value_18_13; // @[Library.scala 115:37]
-  wire [31:0] rdata_value_19_7 = rdata_value_18_14 | rdata_value_18_15; // @[Library.scala 115:37]
-  wire [31:0] rdata_value_19_8 = rdata_value_18_16 | rdata_value_18_17; // @[Library.scala 115:37]
-  wire [31:0] rdata_value_19_9 = rdata_value_18_18 | rdata_value_18_19; // @[Library.scala 115:37]
-  wire [31:0] rdata_value_19_10 = rdata_value_18_20 | rdata_value_18_21; // @[Library.scala 115:37]
-  wire [31:0] rdata_value_19_11 = rdata_value_18_22 | rdata_value_18_23; // @[Library.scala 115:37]
-  wire [31:0] rdata_value_19_12 = rdata_value_18_24 | rdata_value_18_25; // @[Library.scala 115:37]
-  wire [31:0] rdata_value_19_13 = rdata_value_18_26 | rdata_value_18_27; // @[Library.scala 115:37]
-  wire [31:0] rdata_value_19_14 = rdata_value_18_28 | rdata_value_18_29; // @[Library.scala 115:37]
-  wire [31:0] rdata_value_19_15 = rdata_value_18_30 | rdata_value_18_31; // @[Library.scala 115:37]
-  wire [31:0] rdata_value_20_0 = rdata_value_19_0 | rdata_value_19_1; // @[Library.scala 115:37]
-  wire [31:0] rdata_value_20_1 = rdata_value_19_2 | rdata_value_19_3; // @[Library.scala 115:37]
-  wire [31:0] rdata_value_20_2 = rdata_value_19_4 | rdata_value_19_5; // @[Library.scala 115:37]
-  wire [31:0] rdata_value_20_3 = rdata_value_19_6 | rdata_value_19_7; // @[Library.scala 115:37]
-  wire [31:0] rdata_value_20_4 = rdata_value_19_8 | rdata_value_19_9; // @[Library.scala 115:37]
-  wire [31:0] rdata_value_20_5 = rdata_value_19_10 | rdata_value_19_11; // @[Library.scala 115:37]
-  wire [31:0] rdata_value_20_6 = rdata_value_19_12 | rdata_value_19_13; // @[Library.scala 115:37]
-  wire [31:0] rdata_value_20_7 = rdata_value_19_14 | rdata_value_19_15; // @[Library.scala 115:37]
-  wire [31:0] rdata_value_21_0 = rdata_value_20_0 | rdata_value_20_1; // @[Library.scala 115:37]
-  wire [31:0] rdata_value_21_1 = rdata_value_20_2 | rdata_value_20_3; // @[Library.scala 115:37]
-  wire [31:0] rdata_value_21_2 = rdata_value_20_4 | rdata_value_20_5; // @[Library.scala 115:37]
-  wire [31:0] rdata_value_21_3 = rdata_value_20_6 | rdata_value_20_7; // @[Library.scala 115:37]
-  wire [31:0] rdata_value_22_0 = rdata_value_21_0 | rdata_value_21_1; // @[Library.scala 115:37]
-  wire [31:0] rdata_value_22_1 = rdata_value_21_2 | rdata_value_21_3; // @[Library.scala 115:37]
-  wire [31:0] rdata_value_23_0 = rdata_value_22_0 | rdata_value_22_1; // @[Library.scala 115:37]
-  wire [31:0] wdata_value_18_0 = 5'h0 == io_freadAddr_3_addr ? data : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] wdata_value_18_1 = 5'h1 == io_freadAddr_3_addr ? data_1 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] wdata_value_18_2 = 5'h2 == io_freadAddr_3_addr ? data_2 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] wdata_value_18_3 = 5'h3 == io_freadAddr_3_addr ? data_3 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] wdata_value_18_4 = 5'h4 == io_freadAddr_3_addr ? data_4 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] wdata_value_18_5 = 5'h5 == io_freadAddr_3_addr ? data_5 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] wdata_value_18_6 = 5'h6 == io_freadAddr_3_addr ? data_6 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] wdata_value_18_7 = 5'h7 == io_freadAddr_3_addr ? data_7 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] wdata_value_18_8 = 5'h8 == io_freadAddr_3_addr ? data_8 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] wdata_value_18_9 = 5'h9 == io_freadAddr_3_addr ? data_9 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] wdata_value_18_10 = 5'ha == io_freadAddr_3_addr ? data_10 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] wdata_value_18_11 = 5'hb == io_freadAddr_3_addr ? data_11 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] wdata_value_18_12 = 5'hc == io_freadAddr_3_addr ? data_12 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] wdata_value_18_13 = 5'hd == io_freadAddr_3_addr ? data_13 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] wdata_value_18_14 = 5'he == io_freadAddr_3_addr ? data_14 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] wdata_value_18_15 = 5'hf == io_freadAddr_3_addr ? data_15 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] wdata_value_18_16 = 5'h10 == io_freadAddr_3_addr ? data_16 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] wdata_value_18_17 = 5'h11 == io_freadAddr_3_addr ? data_17 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] wdata_value_18_18 = 5'h12 == io_freadAddr_3_addr ? data_18 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] wdata_value_18_19 = 5'h13 == io_freadAddr_3_addr ? data_19 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] wdata_value_18_20 = 5'h14 == io_freadAddr_3_addr ? data_20 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] wdata_value_18_21 = 5'h15 == io_freadAddr_3_addr ? data_21 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] wdata_value_18_22 = 5'h16 == io_freadAddr_3_addr ? data_22 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] wdata_value_18_23 = 5'h17 == io_freadAddr_3_addr ? data_23 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] wdata_value_18_24 = 5'h18 == io_freadAddr_3_addr ? data_24 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] wdata_value_18_25 = 5'h19 == io_freadAddr_3_addr ? data_25 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] wdata_value_18_26 = 5'h1a == io_freadAddr_3_addr ? data_26 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] wdata_value_18_27 = 5'h1b == io_freadAddr_3_addr ? data_27 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] wdata_value_18_28 = 5'h1c == io_freadAddr_3_addr ? data_28 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] wdata_value_18_29 = 5'h1d == io_freadAddr_3_addr ? data_29 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] wdata_value_18_30 = 5'h1e == io_freadAddr_3_addr ? data_30 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] wdata_value_18_31 = 5'h1f == io_freadAddr_3_addr ? data_31 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] wdata_value_19_0 = wdata_value_18_0 | wdata_value_18_1; // @[Library.scala 115:37]
-  wire [31:0] wdata_value_19_1 = wdata_value_18_2 | wdata_value_18_3; // @[Library.scala 115:37]
-  wire [31:0] wdata_value_19_2 = wdata_value_18_4 | wdata_value_18_5; // @[Library.scala 115:37]
-  wire [31:0] wdata_value_19_3 = wdata_value_18_6 | wdata_value_18_7; // @[Library.scala 115:37]
-  wire [31:0] wdata_value_19_4 = wdata_value_18_8 | wdata_value_18_9; // @[Library.scala 115:37]
-  wire [31:0] wdata_value_19_5 = wdata_value_18_10 | wdata_value_18_11; // @[Library.scala 115:37]
-  wire [31:0] wdata_value_19_6 = wdata_value_18_12 | wdata_value_18_13; // @[Library.scala 115:37]
-  wire [31:0] wdata_value_19_7 = wdata_value_18_14 | wdata_value_18_15; // @[Library.scala 115:37]
-  wire [31:0] wdata_value_19_8 = wdata_value_18_16 | wdata_value_18_17; // @[Library.scala 115:37]
-  wire [31:0] wdata_value_19_9 = wdata_value_18_18 | wdata_value_18_19; // @[Library.scala 115:37]
-  wire [31:0] wdata_value_19_10 = wdata_value_18_20 | wdata_value_18_21; // @[Library.scala 115:37]
-  wire [31:0] wdata_value_19_11 = wdata_value_18_22 | wdata_value_18_23; // @[Library.scala 115:37]
-  wire [31:0] wdata_value_19_12 = wdata_value_18_24 | wdata_value_18_25; // @[Library.scala 115:37]
-  wire [31:0] wdata_value_19_13 = wdata_value_18_26 | wdata_value_18_27; // @[Library.scala 115:37]
-  wire [31:0] wdata_value_19_14 = wdata_value_18_28 | wdata_value_18_29; // @[Library.scala 115:37]
-  wire [31:0] wdata_value_19_15 = wdata_value_18_30 | wdata_value_18_31; // @[Library.scala 115:37]
-  wire [31:0] wdata_value_20_0 = wdata_value_19_0 | wdata_value_19_1; // @[Library.scala 115:37]
-  wire [31:0] wdata_value_20_1 = wdata_value_19_2 | wdata_value_19_3; // @[Library.scala 115:37]
-  wire [31:0] wdata_value_20_2 = wdata_value_19_4 | wdata_value_19_5; // @[Library.scala 115:37]
-  wire [31:0] wdata_value_20_3 = wdata_value_19_6 | wdata_value_19_7; // @[Library.scala 115:37]
-  wire [31:0] wdata_value_20_4 = wdata_value_19_8 | wdata_value_19_9; // @[Library.scala 115:37]
-  wire [31:0] wdata_value_20_5 = wdata_value_19_10 | wdata_value_19_11; // @[Library.scala 115:37]
-  wire [31:0] wdata_value_20_6 = wdata_value_19_12 | wdata_value_19_13; // @[Library.scala 115:37]
-  wire [31:0] wdata_value_20_7 = wdata_value_19_14 | wdata_value_19_15; // @[Library.scala 115:37]
-  wire [31:0] wdata_value_21_0 = wdata_value_20_0 | wdata_value_20_1; // @[Library.scala 115:37]
-  wire [31:0] wdata_value_21_1 = wdata_value_20_2 | wdata_value_20_3; // @[Library.scala 115:37]
-  wire [31:0] wdata_value_21_2 = wdata_value_20_4 | wdata_value_20_5; // @[Library.scala 115:37]
-  wire [31:0] wdata_value_21_3 = wdata_value_20_6 | wdata_value_20_7; // @[Library.scala 115:37]
-  wire [31:0] wdata_value_22_0 = wdata_value_21_0 | wdata_value_21_1; // @[Library.scala 115:37]
-  wire [31:0] wdata_value_22_1 = wdata_value_21_2 | wdata_value_21_3; // @[Library.scala 115:37]
-  wire [31:0] wdata_value_23_0 = wdata_value_22_0 | wdata_value_22_1; // @[Library.scala 115:37]
-  wire  write_value_24_0 = 5'h0 == io_freadAddr_4_addr & fwriteValid_0; // @[Library.scala 101:22]
-  wire  write_value_24_1 = 5'h1 == io_freadAddr_4_addr & fwriteValid_1; // @[Library.scala 101:22]
-  wire  write_value_24_2 = 5'h2 == io_freadAddr_4_addr & fwriteValid_2; // @[Library.scala 101:22]
-  wire  write_value_24_3 = 5'h3 == io_freadAddr_4_addr & fwriteValid_3; // @[Library.scala 101:22]
-  wire  write_value_24_4 = 5'h4 == io_freadAddr_4_addr & fwriteValid_4; // @[Library.scala 101:22]
-  wire  write_value_24_5 = 5'h5 == io_freadAddr_4_addr & fwriteValid_5; // @[Library.scala 101:22]
-  wire  write_value_24_6 = 5'h6 == io_freadAddr_4_addr & fwriteValid_6; // @[Library.scala 101:22]
-  wire  write_value_24_7 = 5'h7 == io_freadAddr_4_addr & fwriteValid_7; // @[Library.scala 101:22]
-  wire  write_value_24_8 = 5'h8 == io_freadAddr_4_addr & fwriteValid_8; // @[Library.scala 101:22]
-  wire  write_value_24_9 = 5'h9 == io_freadAddr_4_addr & fwriteValid_9; // @[Library.scala 101:22]
-  wire  write_value_24_10 = 5'ha == io_freadAddr_4_addr & fwriteValid_10; // @[Library.scala 101:22]
-  wire  write_value_24_11 = 5'hb == io_freadAddr_4_addr & fwriteValid_11; // @[Library.scala 101:22]
-  wire  write_value_24_12 = 5'hc == io_freadAddr_4_addr & fwriteValid_12; // @[Library.scala 101:22]
-  wire  write_value_24_13 = 5'hd == io_freadAddr_4_addr & fwriteValid_13; // @[Library.scala 101:22]
-  wire  write_value_24_14 = 5'he == io_freadAddr_4_addr & fwriteValid_14; // @[Library.scala 101:22]
-  wire  write_value_24_15 = 5'hf == io_freadAddr_4_addr & fwriteValid_15; // @[Library.scala 101:22]
-  wire  write_value_24_16 = 5'h10 == io_freadAddr_4_addr & fwriteValid_16; // @[Library.scala 101:22]
-  wire  write_value_24_17 = 5'h11 == io_freadAddr_4_addr & fwriteValid_17; // @[Library.scala 101:22]
-  wire  write_value_24_18 = 5'h12 == io_freadAddr_4_addr & fwriteValid_18; // @[Library.scala 101:22]
-  wire  write_value_24_19 = 5'h13 == io_freadAddr_4_addr & fwriteValid_19; // @[Library.scala 101:22]
-  wire  write_value_24_20 = 5'h14 == io_freadAddr_4_addr & fwriteValid_20; // @[Library.scala 101:22]
-  wire  write_value_24_21 = 5'h15 == io_freadAddr_4_addr & fwriteValid_21; // @[Library.scala 101:22]
-  wire  write_value_24_22 = 5'h16 == io_freadAddr_4_addr & fwriteValid_22; // @[Library.scala 101:22]
-  wire  write_value_24_23 = 5'h17 == io_freadAddr_4_addr & fwriteValid_23; // @[Library.scala 101:22]
-  wire  write_value_24_24 = 5'h18 == io_freadAddr_4_addr & fwriteValid_24; // @[Library.scala 101:22]
-  wire  write_value_24_25 = 5'h19 == io_freadAddr_4_addr & fwriteValid_25; // @[Library.scala 101:22]
-  wire  write_value_24_26 = 5'h1a == io_freadAddr_4_addr & fwriteValid_26; // @[Library.scala 101:22]
-  wire  write_value_24_27 = 5'h1b == io_freadAddr_4_addr & fwriteValid_27; // @[Library.scala 101:22]
-  wire  write_value_24_28 = 5'h1c == io_freadAddr_4_addr & fwriteValid_28; // @[Library.scala 101:22]
-  wire  write_value_24_29 = 5'h1d == io_freadAddr_4_addr & fwriteValid_29; // @[Library.scala 101:22]
-  wire  write_value_24_30 = 5'h1e == io_freadAddr_4_addr & fwriteValid_30; // @[Library.scala 101:22]
-  wire  write_value_24_31 = 5'h1f == io_freadAddr_4_addr & fwriteValid_31; // @[Library.scala 101:22]
-  wire  write_value_25_0 = write_value_24_0 | write_value_24_1; // @[Library.scala 115:37]
-  wire  write_value_25_1 = write_value_24_2 | write_value_24_3; // @[Library.scala 115:37]
-  wire  write_value_25_2 = write_value_24_4 | write_value_24_5; // @[Library.scala 115:37]
-  wire  write_value_25_3 = write_value_24_6 | write_value_24_7; // @[Library.scala 115:37]
-  wire  write_value_25_4 = write_value_24_8 | write_value_24_9; // @[Library.scala 115:37]
-  wire  write_value_25_5 = write_value_24_10 | write_value_24_11; // @[Library.scala 115:37]
-  wire  write_value_25_6 = write_value_24_12 | write_value_24_13; // @[Library.scala 115:37]
-  wire  write_value_25_7 = write_value_24_14 | write_value_24_15; // @[Library.scala 115:37]
-  wire  write_value_25_8 = write_value_24_16 | write_value_24_17; // @[Library.scala 115:37]
-  wire  write_value_25_9 = write_value_24_18 | write_value_24_19; // @[Library.scala 115:37]
-  wire  write_value_25_10 = write_value_24_20 | write_value_24_21; // @[Library.scala 115:37]
-  wire  write_value_25_11 = write_value_24_22 | write_value_24_23; // @[Library.scala 115:37]
-  wire  write_value_25_12 = write_value_24_24 | write_value_24_25; // @[Library.scala 115:37]
-  wire  write_value_25_13 = write_value_24_26 | write_value_24_27; // @[Library.scala 115:37]
-  wire  write_value_25_14 = write_value_24_28 | write_value_24_29; // @[Library.scala 115:37]
-  wire  write_value_25_15 = write_value_24_30 | write_value_24_31; // @[Library.scala 115:37]
-  wire  write_value_26_0 = write_value_25_0 | write_value_25_1; // @[Library.scala 115:37]
-  wire  write_value_26_1 = write_value_25_2 | write_value_25_3; // @[Library.scala 115:37]
-  wire  write_value_26_2 = write_value_25_4 | write_value_25_5; // @[Library.scala 115:37]
-  wire  write_value_26_3 = write_value_25_6 | write_value_25_7; // @[Library.scala 115:37]
-  wire  write_value_26_4 = write_value_25_8 | write_value_25_9; // @[Library.scala 115:37]
-  wire  write_value_26_5 = write_value_25_10 | write_value_25_11; // @[Library.scala 115:37]
-  wire  write_value_26_6 = write_value_25_12 | write_value_25_13; // @[Library.scala 115:37]
-  wire  write_value_26_7 = write_value_25_14 | write_value_25_15; // @[Library.scala 115:37]
-  wire  write_value_27_0 = write_value_26_0 | write_value_26_1; // @[Library.scala 115:37]
-  wire  write_value_27_1 = write_value_26_2 | write_value_26_3; // @[Library.scala 115:37]
-  wire  write_value_27_2 = write_value_26_4 | write_value_26_5; // @[Library.scala 115:37]
-  wire  write_value_27_3 = write_value_26_6 | write_value_26_7; // @[Library.scala 115:37]
-  wire  write_value_28_0 = write_value_27_0 | write_value_27_1; // @[Library.scala 115:37]
-  wire  write_value_28_1 = write_value_27_2 | write_value_27_3; // @[Library.scala 115:37]
-  wire  write_value_29_0 = write_value_28_0 | write_value_28_1; // @[Library.scala 115:37]
-  wire [31:0] rdata_value_24_0 = 5'h0 == io_freadAddr_4_addr ? fregfile_0 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] rdata_value_24_1 = 5'h1 == io_freadAddr_4_addr ? fregfile_1 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] rdata_value_24_2 = 5'h2 == io_freadAddr_4_addr ? fregfile_2 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] rdata_value_24_3 = 5'h3 == io_freadAddr_4_addr ? fregfile_3 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] rdata_value_24_4 = 5'h4 == io_freadAddr_4_addr ? fregfile_4 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] rdata_value_24_5 = 5'h5 == io_freadAddr_4_addr ? fregfile_5 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] rdata_value_24_6 = 5'h6 == io_freadAddr_4_addr ? fregfile_6 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] rdata_value_24_7 = 5'h7 == io_freadAddr_4_addr ? fregfile_7 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] rdata_value_24_8 = 5'h8 == io_freadAddr_4_addr ? fregfile_8 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] rdata_value_24_9 = 5'h9 == io_freadAddr_4_addr ? fregfile_9 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] rdata_value_24_10 = 5'ha == io_freadAddr_4_addr ? fregfile_10 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] rdata_value_24_11 = 5'hb == io_freadAddr_4_addr ? fregfile_11 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] rdata_value_24_12 = 5'hc == io_freadAddr_4_addr ? fregfile_12 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] rdata_value_24_13 = 5'hd == io_freadAddr_4_addr ? fregfile_13 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] rdata_value_24_14 = 5'he == io_freadAddr_4_addr ? fregfile_14 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] rdata_value_24_15 = 5'hf == io_freadAddr_4_addr ? fregfile_15 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] rdata_value_24_16 = 5'h10 == io_freadAddr_4_addr ? fregfile_16 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] rdata_value_24_17 = 5'h11 == io_freadAddr_4_addr ? fregfile_17 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] rdata_value_24_18 = 5'h12 == io_freadAddr_4_addr ? fregfile_18 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] rdata_value_24_19 = 5'h13 == io_freadAddr_4_addr ? fregfile_19 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] rdata_value_24_20 = 5'h14 == io_freadAddr_4_addr ? fregfile_20 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] rdata_value_24_21 = 5'h15 == io_freadAddr_4_addr ? fregfile_21 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] rdata_value_24_22 = 5'h16 == io_freadAddr_4_addr ? fregfile_22 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] rdata_value_24_23 = 5'h17 == io_freadAddr_4_addr ? fregfile_23 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] rdata_value_24_24 = 5'h18 == io_freadAddr_4_addr ? fregfile_24 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] rdata_value_24_25 = 5'h19 == io_freadAddr_4_addr ? fregfile_25 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] rdata_value_24_26 = 5'h1a == io_freadAddr_4_addr ? fregfile_26 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] rdata_value_24_27 = 5'h1b == io_freadAddr_4_addr ? fregfile_27 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] rdata_value_24_28 = 5'h1c == io_freadAddr_4_addr ? fregfile_28 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] rdata_value_24_29 = 5'h1d == io_freadAddr_4_addr ? fregfile_29 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] rdata_value_24_30 = 5'h1e == io_freadAddr_4_addr ? fregfile_30 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] rdata_value_24_31 = 5'h1f == io_freadAddr_4_addr ? fregfile_31 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] rdata_value_25_0 = rdata_value_24_0 | rdata_value_24_1; // @[Library.scala 115:37]
-  wire [31:0] rdata_value_25_1 = rdata_value_24_2 | rdata_value_24_3; // @[Library.scala 115:37]
-  wire [31:0] rdata_value_25_2 = rdata_value_24_4 | rdata_value_24_5; // @[Library.scala 115:37]
-  wire [31:0] rdata_value_25_3 = rdata_value_24_6 | rdata_value_24_7; // @[Library.scala 115:37]
-  wire [31:0] rdata_value_25_4 = rdata_value_24_8 | rdata_value_24_9; // @[Library.scala 115:37]
-  wire [31:0] rdata_value_25_5 = rdata_value_24_10 | rdata_value_24_11; // @[Library.scala 115:37]
-  wire [31:0] rdata_value_25_6 = rdata_value_24_12 | rdata_value_24_13; // @[Library.scala 115:37]
-  wire [31:0] rdata_value_25_7 = rdata_value_24_14 | rdata_value_24_15; // @[Library.scala 115:37]
-  wire [31:0] rdata_value_25_8 = rdata_value_24_16 | rdata_value_24_17; // @[Library.scala 115:37]
-  wire [31:0] rdata_value_25_9 = rdata_value_24_18 | rdata_value_24_19; // @[Library.scala 115:37]
-  wire [31:0] rdata_value_25_10 = rdata_value_24_20 | rdata_value_24_21; // @[Library.scala 115:37]
-  wire [31:0] rdata_value_25_11 = rdata_value_24_22 | rdata_value_24_23; // @[Library.scala 115:37]
-  wire [31:0] rdata_value_25_12 = rdata_value_24_24 | rdata_value_24_25; // @[Library.scala 115:37]
-  wire [31:0] rdata_value_25_13 = rdata_value_24_26 | rdata_value_24_27; // @[Library.scala 115:37]
-  wire [31:0] rdata_value_25_14 = rdata_value_24_28 | rdata_value_24_29; // @[Library.scala 115:37]
-  wire [31:0] rdata_value_25_15 = rdata_value_24_30 | rdata_value_24_31; // @[Library.scala 115:37]
-  wire [31:0] rdata_value_26_0 = rdata_value_25_0 | rdata_value_25_1; // @[Library.scala 115:37]
-  wire [31:0] rdata_value_26_1 = rdata_value_25_2 | rdata_value_25_3; // @[Library.scala 115:37]
-  wire [31:0] rdata_value_26_2 = rdata_value_25_4 | rdata_value_25_5; // @[Library.scala 115:37]
-  wire [31:0] rdata_value_26_3 = rdata_value_25_6 | rdata_value_25_7; // @[Library.scala 115:37]
-  wire [31:0] rdata_value_26_4 = rdata_value_25_8 | rdata_value_25_9; // @[Library.scala 115:37]
-  wire [31:0] rdata_value_26_5 = rdata_value_25_10 | rdata_value_25_11; // @[Library.scala 115:37]
-  wire [31:0] rdata_value_26_6 = rdata_value_25_12 | rdata_value_25_13; // @[Library.scala 115:37]
-  wire [31:0] rdata_value_26_7 = rdata_value_25_14 | rdata_value_25_15; // @[Library.scala 115:37]
-  wire [31:0] rdata_value_27_0 = rdata_value_26_0 | rdata_value_26_1; // @[Library.scala 115:37]
-  wire [31:0] rdata_value_27_1 = rdata_value_26_2 | rdata_value_26_3; // @[Library.scala 115:37]
-  wire [31:0] rdata_value_27_2 = rdata_value_26_4 | rdata_value_26_5; // @[Library.scala 115:37]
-  wire [31:0] rdata_value_27_3 = rdata_value_26_6 | rdata_value_26_7; // @[Library.scala 115:37]
-  wire [31:0] rdata_value_28_0 = rdata_value_27_0 | rdata_value_27_1; // @[Library.scala 115:37]
-  wire [31:0] rdata_value_28_1 = rdata_value_27_2 | rdata_value_27_3; // @[Library.scala 115:37]
-  wire [31:0] rdata_value_29_0 = rdata_value_28_0 | rdata_value_28_1; // @[Library.scala 115:37]
-  wire [31:0] wdata_value_24_0 = 5'h0 == io_freadAddr_4_addr ? data : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] wdata_value_24_1 = 5'h1 == io_freadAddr_4_addr ? data_1 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] wdata_value_24_2 = 5'h2 == io_freadAddr_4_addr ? data_2 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] wdata_value_24_3 = 5'h3 == io_freadAddr_4_addr ? data_3 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] wdata_value_24_4 = 5'h4 == io_freadAddr_4_addr ? data_4 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] wdata_value_24_5 = 5'h5 == io_freadAddr_4_addr ? data_5 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] wdata_value_24_6 = 5'h6 == io_freadAddr_4_addr ? data_6 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] wdata_value_24_7 = 5'h7 == io_freadAddr_4_addr ? data_7 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] wdata_value_24_8 = 5'h8 == io_freadAddr_4_addr ? data_8 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] wdata_value_24_9 = 5'h9 == io_freadAddr_4_addr ? data_9 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] wdata_value_24_10 = 5'ha == io_freadAddr_4_addr ? data_10 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] wdata_value_24_11 = 5'hb == io_freadAddr_4_addr ? data_11 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] wdata_value_24_12 = 5'hc == io_freadAddr_4_addr ? data_12 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] wdata_value_24_13 = 5'hd == io_freadAddr_4_addr ? data_13 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] wdata_value_24_14 = 5'he == io_freadAddr_4_addr ? data_14 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] wdata_value_24_15 = 5'hf == io_freadAddr_4_addr ? data_15 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] wdata_value_24_16 = 5'h10 == io_freadAddr_4_addr ? data_16 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] wdata_value_24_17 = 5'h11 == io_freadAddr_4_addr ? data_17 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] wdata_value_24_18 = 5'h12 == io_freadAddr_4_addr ? data_18 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] wdata_value_24_19 = 5'h13 == io_freadAddr_4_addr ? data_19 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] wdata_value_24_20 = 5'h14 == io_freadAddr_4_addr ? data_20 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] wdata_value_24_21 = 5'h15 == io_freadAddr_4_addr ? data_21 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] wdata_value_24_22 = 5'h16 == io_freadAddr_4_addr ? data_22 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] wdata_value_24_23 = 5'h17 == io_freadAddr_4_addr ? data_23 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] wdata_value_24_24 = 5'h18 == io_freadAddr_4_addr ? data_24 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] wdata_value_24_25 = 5'h19 == io_freadAddr_4_addr ? data_25 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] wdata_value_24_26 = 5'h1a == io_freadAddr_4_addr ? data_26 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] wdata_value_24_27 = 5'h1b == io_freadAddr_4_addr ? data_27 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] wdata_value_24_28 = 5'h1c == io_freadAddr_4_addr ? data_28 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] wdata_value_24_29 = 5'h1d == io_freadAddr_4_addr ? data_29 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] wdata_value_24_30 = 5'h1e == io_freadAddr_4_addr ? data_30 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] wdata_value_24_31 = 5'h1f == io_freadAddr_4_addr ? data_31 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] wdata_value_25_0 = wdata_value_24_0 | wdata_value_24_1; // @[Library.scala 115:37]
-  wire [31:0] wdata_value_25_1 = wdata_value_24_2 | wdata_value_24_3; // @[Library.scala 115:37]
-  wire [31:0] wdata_value_25_2 = wdata_value_24_4 | wdata_value_24_5; // @[Library.scala 115:37]
-  wire [31:0] wdata_value_25_3 = wdata_value_24_6 | wdata_value_24_7; // @[Library.scala 115:37]
-  wire [31:0] wdata_value_25_4 = wdata_value_24_8 | wdata_value_24_9; // @[Library.scala 115:37]
-  wire [31:0] wdata_value_25_5 = wdata_value_24_10 | wdata_value_24_11; // @[Library.scala 115:37]
-  wire [31:0] wdata_value_25_6 = wdata_value_24_12 | wdata_value_24_13; // @[Library.scala 115:37]
-  wire [31:0] wdata_value_25_7 = wdata_value_24_14 | wdata_value_24_15; // @[Library.scala 115:37]
-  wire [31:0] wdata_value_25_8 = wdata_value_24_16 | wdata_value_24_17; // @[Library.scala 115:37]
-  wire [31:0] wdata_value_25_9 = wdata_value_24_18 | wdata_value_24_19; // @[Library.scala 115:37]
-  wire [31:0] wdata_value_25_10 = wdata_value_24_20 | wdata_value_24_21; // @[Library.scala 115:37]
-  wire [31:0] wdata_value_25_11 = wdata_value_24_22 | wdata_value_24_23; // @[Library.scala 115:37]
-  wire [31:0] wdata_value_25_12 = wdata_value_24_24 | wdata_value_24_25; // @[Library.scala 115:37]
-  wire [31:0] wdata_value_25_13 = wdata_value_24_26 | wdata_value_24_27; // @[Library.scala 115:37]
-  wire [31:0] wdata_value_25_14 = wdata_value_24_28 | wdata_value_24_29; // @[Library.scala 115:37]
-  wire [31:0] wdata_value_25_15 = wdata_value_24_30 | wdata_value_24_31; // @[Library.scala 115:37]
-  wire [31:0] wdata_value_26_0 = wdata_value_25_0 | wdata_value_25_1; // @[Library.scala 115:37]
-  wire [31:0] wdata_value_26_1 = wdata_value_25_2 | wdata_value_25_3; // @[Library.scala 115:37]
-  wire [31:0] wdata_value_26_2 = wdata_value_25_4 | wdata_value_25_5; // @[Library.scala 115:37]
-  wire [31:0] wdata_value_26_3 = wdata_value_25_6 | wdata_value_25_7; // @[Library.scala 115:37]
-  wire [31:0] wdata_value_26_4 = wdata_value_25_8 | wdata_value_25_9; // @[Library.scala 115:37]
-  wire [31:0] wdata_value_26_5 = wdata_value_25_10 | wdata_value_25_11; // @[Library.scala 115:37]
-  wire [31:0] wdata_value_26_6 = wdata_value_25_12 | wdata_value_25_13; // @[Library.scala 115:37]
-  wire [31:0] wdata_value_26_7 = wdata_value_25_14 | wdata_value_25_15; // @[Library.scala 115:37]
-  wire [31:0] wdata_value_27_0 = wdata_value_26_0 | wdata_value_26_1; // @[Library.scala 115:37]
-  wire [31:0] wdata_value_27_1 = wdata_value_26_2 | wdata_value_26_3; // @[Library.scala 115:37]
-  wire [31:0] wdata_value_27_2 = wdata_value_26_4 | wdata_value_26_5; // @[Library.scala 115:37]
-  wire [31:0] wdata_value_27_3 = wdata_value_26_6 | wdata_value_26_7; // @[Library.scala 115:37]
-  wire [31:0] wdata_value_28_0 = wdata_value_27_0 | wdata_value_27_1; // @[Library.scala 115:37]
-  wire [31:0] wdata_value_28_1 = wdata_value_27_2 | wdata_value_27_3; // @[Library.scala 115:37]
-  wire [31:0] wdata_value_29_0 = wdata_value_28_0 | wdata_value_28_1; // @[Library.scala 115:37]
-  wire  write_value_30_0 = 5'h0 == io_freadAddr_5_addr & fwriteValid_0; // @[Library.scala 101:22]
-  wire  write_value_30_1 = 5'h1 == io_freadAddr_5_addr & fwriteValid_1; // @[Library.scala 101:22]
-  wire  write_value_30_2 = 5'h2 == io_freadAddr_5_addr & fwriteValid_2; // @[Library.scala 101:22]
-  wire  write_value_30_3 = 5'h3 == io_freadAddr_5_addr & fwriteValid_3; // @[Library.scala 101:22]
-  wire  write_value_30_4 = 5'h4 == io_freadAddr_5_addr & fwriteValid_4; // @[Library.scala 101:22]
-  wire  write_value_30_5 = 5'h5 == io_freadAddr_5_addr & fwriteValid_5; // @[Library.scala 101:22]
-  wire  write_value_30_6 = 5'h6 == io_freadAddr_5_addr & fwriteValid_6; // @[Library.scala 101:22]
-  wire  write_value_30_7 = 5'h7 == io_freadAddr_5_addr & fwriteValid_7; // @[Library.scala 101:22]
-  wire  write_value_30_8 = 5'h8 == io_freadAddr_5_addr & fwriteValid_8; // @[Library.scala 101:22]
-  wire  write_value_30_9 = 5'h9 == io_freadAddr_5_addr & fwriteValid_9; // @[Library.scala 101:22]
-  wire  write_value_30_10 = 5'ha == io_freadAddr_5_addr & fwriteValid_10; // @[Library.scala 101:22]
-  wire  write_value_30_11 = 5'hb == io_freadAddr_5_addr & fwriteValid_11; // @[Library.scala 101:22]
-  wire  write_value_30_12 = 5'hc == io_freadAddr_5_addr & fwriteValid_12; // @[Library.scala 101:22]
-  wire  write_value_30_13 = 5'hd == io_freadAddr_5_addr & fwriteValid_13; // @[Library.scala 101:22]
-  wire  write_value_30_14 = 5'he == io_freadAddr_5_addr & fwriteValid_14; // @[Library.scala 101:22]
-  wire  write_value_30_15 = 5'hf == io_freadAddr_5_addr & fwriteValid_15; // @[Library.scala 101:22]
-  wire  write_value_30_16 = 5'h10 == io_freadAddr_5_addr & fwriteValid_16; // @[Library.scala 101:22]
-  wire  write_value_30_17 = 5'h11 == io_freadAddr_5_addr & fwriteValid_17; // @[Library.scala 101:22]
-  wire  write_value_30_18 = 5'h12 == io_freadAddr_5_addr & fwriteValid_18; // @[Library.scala 101:22]
-  wire  write_value_30_19 = 5'h13 == io_freadAddr_5_addr & fwriteValid_19; // @[Library.scala 101:22]
-  wire  write_value_30_20 = 5'h14 == io_freadAddr_5_addr & fwriteValid_20; // @[Library.scala 101:22]
-  wire  write_value_30_21 = 5'h15 == io_freadAddr_5_addr & fwriteValid_21; // @[Library.scala 101:22]
-  wire  write_value_30_22 = 5'h16 == io_freadAddr_5_addr & fwriteValid_22; // @[Library.scala 101:22]
-  wire  write_value_30_23 = 5'h17 == io_freadAddr_5_addr & fwriteValid_23; // @[Library.scala 101:22]
-  wire  write_value_30_24 = 5'h18 == io_freadAddr_5_addr & fwriteValid_24; // @[Library.scala 101:22]
-  wire  write_value_30_25 = 5'h19 == io_freadAddr_5_addr & fwriteValid_25; // @[Library.scala 101:22]
-  wire  write_value_30_26 = 5'h1a == io_freadAddr_5_addr & fwriteValid_26; // @[Library.scala 101:22]
-  wire  write_value_30_27 = 5'h1b == io_freadAddr_5_addr & fwriteValid_27; // @[Library.scala 101:22]
-  wire  write_value_30_28 = 5'h1c == io_freadAddr_5_addr & fwriteValid_28; // @[Library.scala 101:22]
-  wire  write_value_30_29 = 5'h1d == io_freadAddr_5_addr & fwriteValid_29; // @[Library.scala 101:22]
-  wire  write_value_30_30 = 5'h1e == io_freadAddr_5_addr & fwriteValid_30; // @[Library.scala 101:22]
-  wire  write_value_30_31 = 5'h1f == io_freadAddr_5_addr & fwriteValid_31; // @[Library.scala 101:22]
-  wire  write_value_31_0 = write_value_30_0 | write_value_30_1; // @[Library.scala 115:37]
-  wire  write_value_31_1 = write_value_30_2 | write_value_30_3; // @[Library.scala 115:37]
-  wire  write_value_31_2 = write_value_30_4 | write_value_30_5; // @[Library.scala 115:37]
-  wire  write_value_31_3 = write_value_30_6 | write_value_30_7; // @[Library.scala 115:37]
-  wire  write_value_31_4 = write_value_30_8 | write_value_30_9; // @[Library.scala 115:37]
-  wire  write_value_31_5 = write_value_30_10 | write_value_30_11; // @[Library.scala 115:37]
-  wire  write_value_31_6 = write_value_30_12 | write_value_30_13; // @[Library.scala 115:37]
-  wire  write_value_31_7 = write_value_30_14 | write_value_30_15; // @[Library.scala 115:37]
-  wire  write_value_31_8 = write_value_30_16 | write_value_30_17; // @[Library.scala 115:37]
-  wire  write_value_31_9 = write_value_30_18 | write_value_30_19; // @[Library.scala 115:37]
-  wire  write_value_31_10 = write_value_30_20 | write_value_30_21; // @[Library.scala 115:37]
-  wire  write_value_31_11 = write_value_30_22 | write_value_30_23; // @[Library.scala 115:37]
-  wire  write_value_31_12 = write_value_30_24 | write_value_30_25; // @[Library.scala 115:37]
-  wire  write_value_31_13 = write_value_30_26 | write_value_30_27; // @[Library.scala 115:37]
-  wire  write_value_31_14 = write_value_30_28 | write_value_30_29; // @[Library.scala 115:37]
-  wire  write_value_31_15 = write_value_30_30 | write_value_30_31; // @[Library.scala 115:37]
-  wire  write_value_32_0 = write_value_31_0 | write_value_31_1; // @[Library.scala 115:37]
-  wire  write_value_32_1 = write_value_31_2 | write_value_31_3; // @[Library.scala 115:37]
-  wire  write_value_32_2 = write_value_31_4 | write_value_31_5; // @[Library.scala 115:37]
-  wire  write_value_32_3 = write_value_31_6 | write_value_31_7; // @[Library.scala 115:37]
-  wire  write_value_32_4 = write_value_31_8 | write_value_31_9; // @[Library.scala 115:37]
-  wire  write_value_32_5 = write_value_31_10 | write_value_31_11; // @[Library.scala 115:37]
-  wire  write_value_32_6 = write_value_31_12 | write_value_31_13; // @[Library.scala 115:37]
-  wire  write_value_32_7 = write_value_31_14 | write_value_31_15; // @[Library.scala 115:37]
-  wire  write_value_33_0 = write_value_32_0 | write_value_32_1; // @[Library.scala 115:37]
-  wire  write_value_33_1 = write_value_32_2 | write_value_32_3; // @[Library.scala 115:37]
-  wire  write_value_33_2 = write_value_32_4 | write_value_32_5; // @[Library.scala 115:37]
-  wire  write_value_33_3 = write_value_32_6 | write_value_32_7; // @[Library.scala 115:37]
-  wire  write_value_34_0 = write_value_33_0 | write_value_33_1; // @[Library.scala 115:37]
-  wire  write_value_34_1 = write_value_33_2 | write_value_33_3; // @[Library.scala 115:37]
-  wire  write_value_35_0 = write_value_34_0 | write_value_34_1; // @[Library.scala 115:37]
-  wire [31:0] rdata_value_30_0 = 5'h0 == io_freadAddr_5_addr ? fregfile_0 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] rdata_value_30_1 = 5'h1 == io_freadAddr_5_addr ? fregfile_1 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] rdata_value_30_2 = 5'h2 == io_freadAddr_5_addr ? fregfile_2 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] rdata_value_30_3 = 5'h3 == io_freadAddr_5_addr ? fregfile_3 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] rdata_value_30_4 = 5'h4 == io_freadAddr_5_addr ? fregfile_4 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] rdata_value_30_5 = 5'h5 == io_freadAddr_5_addr ? fregfile_5 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] rdata_value_30_6 = 5'h6 == io_freadAddr_5_addr ? fregfile_6 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] rdata_value_30_7 = 5'h7 == io_freadAddr_5_addr ? fregfile_7 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] rdata_value_30_8 = 5'h8 == io_freadAddr_5_addr ? fregfile_8 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] rdata_value_30_9 = 5'h9 == io_freadAddr_5_addr ? fregfile_9 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] rdata_value_30_10 = 5'ha == io_freadAddr_5_addr ? fregfile_10 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] rdata_value_30_11 = 5'hb == io_freadAddr_5_addr ? fregfile_11 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] rdata_value_30_12 = 5'hc == io_freadAddr_5_addr ? fregfile_12 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] rdata_value_30_13 = 5'hd == io_freadAddr_5_addr ? fregfile_13 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] rdata_value_30_14 = 5'he == io_freadAddr_5_addr ? fregfile_14 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] rdata_value_30_15 = 5'hf == io_freadAddr_5_addr ? fregfile_15 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] rdata_value_30_16 = 5'h10 == io_freadAddr_5_addr ? fregfile_16 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] rdata_value_30_17 = 5'h11 == io_freadAddr_5_addr ? fregfile_17 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] rdata_value_30_18 = 5'h12 == io_freadAddr_5_addr ? fregfile_18 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] rdata_value_30_19 = 5'h13 == io_freadAddr_5_addr ? fregfile_19 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] rdata_value_30_20 = 5'h14 == io_freadAddr_5_addr ? fregfile_20 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] rdata_value_30_21 = 5'h15 == io_freadAddr_5_addr ? fregfile_21 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] rdata_value_30_22 = 5'h16 == io_freadAddr_5_addr ? fregfile_22 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] rdata_value_30_23 = 5'h17 == io_freadAddr_5_addr ? fregfile_23 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] rdata_value_30_24 = 5'h18 == io_freadAddr_5_addr ? fregfile_24 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] rdata_value_30_25 = 5'h19 == io_freadAddr_5_addr ? fregfile_25 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] rdata_value_30_26 = 5'h1a == io_freadAddr_5_addr ? fregfile_26 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] rdata_value_30_27 = 5'h1b == io_freadAddr_5_addr ? fregfile_27 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] rdata_value_30_28 = 5'h1c == io_freadAddr_5_addr ? fregfile_28 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] rdata_value_30_29 = 5'h1d == io_freadAddr_5_addr ? fregfile_29 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] rdata_value_30_30 = 5'h1e == io_freadAddr_5_addr ? fregfile_30 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] rdata_value_30_31 = 5'h1f == io_freadAddr_5_addr ? fregfile_31 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] rdata_value_31_0 = rdata_value_30_0 | rdata_value_30_1; // @[Library.scala 115:37]
-  wire [31:0] rdata_value_31_1 = rdata_value_30_2 | rdata_value_30_3; // @[Library.scala 115:37]
-  wire [31:0] rdata_value_31_2 = rdata_value_30_4 | rdata_value_30_5; // @[Library.scala 115:37]
-  wire [31:0] rdata_value_31_3 = rdata_value_30_6 | rdata_value_30_7; // @[Library.scala 115:37]
-  wire [31:0] rdata_value_31_4 = rdata_value_30_8 | rdata_value_30_9; // @[Library.scala 115:37]
-  wire [31:0] rdata_value_31_5 = rdata_value_30_10 | rdata_value_30_11; // @[Library.scala 115:37]
-  wire [31:0] rdata_value_31_6 = rdata_value_30_12 | rdata_value_30_13; // @[Library.scala 115:37]
-  wire [31:0] rdata_value_31_7 = rdata_value_30_14 | rdata_value_30_15; // @[Library.scala 115:37]
-  wire [31:0] rdata_value_31_8 = rdata_value_30_16 | rdata_value_30_17; // @[Library.scala 115:37]
-  wire [31:0] rdata_value_31_9 = rdata_value_30_18 | rdata_value_30_19; // @[Library.scala 115:37]
-  wire [31:0] rdata_value_31_10 = rdata_value_30_20 | rdata_value_30_21; // @[Library.scala 115:37]
-  wire [31:0] rdata_value_31_11 = rdata_value_30_22 | rdata_value_30_23; // @[Library.scala 115:37]
-  wire [31:0] rdata_value_31_12 = rdata_value_30_24 | rdata_value_30_25; // @[Library.scala 115:37]
-  wire [31:0] rdata_value_31_13 = rdata_value_30_26 | rdata_value_30_27; // @[Library.scala 115:37]
-  wire [31:0] rdata_value_31_14 = rdata_value_30_28 | rdata_value_30_29; // @[Library.scala 115:37]
-  wire [31:0] rdata_value_31_15 = rdata_value_30_30 | rdata_value_30_31; // @[Library.scala 115:37]
-  wire [31:0] rdata_value_32_0 = rdata_value_31_0 | rdata_value_31_1; // @[Library.scala 115:37]
-  wire [31:0] rdata_value_32_1 = rdata_value_31_2 | rdata_value_31_3; // @[Library.scala 115:37]
-  wire [31:0] rdata_value_32_2 = rdata_value_31_4 | rdata_value_31_5; // @[Library.scala 115:37]
-  wire [31:0] rdata_value_32_3 = rdata_value_31_6 | rdata_value_31_7; // @[Library.scala 115:37]
-  wire [31:0] rdata_value_32_4 = rdata_value_31_8 | rdata_value_31_9; // @[Library.scala 115:37]
-  wire [31:0] rdata_value_32_5 = rdata_value_31_10 | rdata_value_31_11; // @[Library.scala 115:37]
-  wire [31:0] rdata_value_32_6 = rdata_value_31_12 | rdata_value_31_13; // @[Library.scala 115:37]
-  wire [31:0] rdata_value_32_7 = rdata_value_31_14 | rdata_value_31_15; // @[Library.scala 115:37]
-  wire [31:0] rdata_value_33_0 = rdata_value_32_0 | rdata_value_32_1; // @[Library.scala 115:37]
-  wire [31:0] rdata_value_33_1 = rdata_value_32_2 | rdata_value_32_3; // @[Library.scala 115:37]
-  wire [31:0] rdata_value_33_2 = rdata_value_32_4 | rdata_value_32_5; // @[Library.scala 115:37]
-  wire [31:0] rdata_value_33_3 = rdata_value_32_6 | rdata_value_32_7; // @[Library.scala 115:37]
-  wire [31:0] rdata_value_34_0 = rdata_value_33_0 | rdata_value_33_1; // @[Library.scala 115:37]
-  wire [31:0] rdata_value_34_1 = rdata_value_33_2 | rdata_value_33_3; // @[Library.scala 115:37]
-  wire [31:0] rdata_value_35_0 = rdata_value_34_0 | rdata_value_34_1; // @[Library.scala 115:37]
-  wire [31:0] wdata_value_30_0 = 5'h0 == io_freadAddr_5_addr ? data : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] wdata_value_30_1 = 5'h1 == io_freadAddr_5_addr ? data_1 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] wdata_value_30_2 = 5'h2 == io_freadAddr_5_addr ? data_2 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] wdata_value_30_3 = 5'h3 == io_freadAddr_5_addr ? data_3 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] wdata_value_30_4 = 5'h4 == io_freadAddr_5_addr ? data_4 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] wdata_value_30_5 = 5'h5 == io_freadAddr_5_addr ? data_5 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] wdata_value_30_6 = 5'h6 == io_freadAddr_5_addr ? data_6 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] wdata_value_30_7 = 5'h7 == io_freadAddr_5_addr ? data_7 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] wdata_value_30_8 = 5'h8 == io_freadAddr_5_addr ? data_8 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] wdata_value_30_9 = 5'h9 == io_freadAddr_5_addr ? data_9 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] wdata_value_30_10 = 5'ha == io_freadAddr_5_addr ? data_10 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] wdata_value_30_11 = 5'hb == io_freadAddr_5_addr ? data_11 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] wdata_value_30_12 = 5'hc == io_freadAddr_5_addr ? data_12 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] wdata_value_30_13 = 5'hd == io_freadAddr_5_addr ? data_13 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] wdata_value_30_14 = 5'he == io_freadAddr_5_addr ? data_14 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] wdata_value_30_15 = 5'hf == io_freadAddr_5_addr ? data_15 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] wdata_value_30_16 = 5'h10 == io_freadAddr_5_addr ? data_16 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] wdata_value_30_17 = 5'h11 == io_freadAddr_5_addr ? data_17 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] wdata_value_30_18 = 5'h12 == io_freadAddr_5_addr ? data_18 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] wdata_value_30_19 = 5'h13 == io_freadAddr_5_addr ? data_19 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] wdata_value_30_20 = 5'h14 == io_freadAddr_5_addr ? data_20 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] wdata_value_30_21 = 5'h15 == io_freadAddr_5_addr ? data_21 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] wdata_value_30_22 = 5'h16 == io_freadAddr_5_addr ? data_22 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] wdata_value_30_23 = 5'h17 == io_freadAddr_5_addr ? data_23 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] wdata_value_30_24 = 5'h18 == io_freadAddr_5_addr ? data_24 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] wdata_value_30_25 = 5'h19 == io_freadAddr_5_addr ? data_25 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] wdata_value_30_26 = 5'h1a == io_freadAddr_5_addr ? data_26 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] wdata_value_30_27 = 5'h1b == io_freadAddr_5_addr ? data_27 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] wdata_value_30_28 = 5'h1c == io_freadAddr_5_addr ? data_28 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] wdata_value_30_29 = 5'h1d == io_freadAddr_5_addr ? data_29 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] wdata_value_30_30 = 5'h1e == io_freadAddr_5_addr ? data_30 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] wdata_value_30_31 = 5'h1f == io_freadAddr_5_addr ? data_31 : 32'h0; // @[Library.scala 101:22]
-  wire [31:0] wdata_value_31_0 = wdata_value_30_0 | wdata_value_30_1; // @[Library.scala 115:37]
-  wire [31:0] wdata_value_31_1 = wdata_value_30_2 | wdata_value_30_3; // @[Library.scala 115:37]
-  wire [31:0] wdata_value_31_2 = wdata_value_30_4 | wdata_value_30_5; // @[Library.scala 115:37]
-  wire [31:0] wdata_value_31_3 = wdata_value_30_6 | wdata_value_30_7; // @[Library.scala 115:37]
-  wire [31:0] wdata_value_31_4 = wdata_value_30_8 | wdata_value_30_9; // @[Library.scala 115:37]
-  wire [31:0] wdata_value_31_5 = wdata_value_30_10 | wdata_value_30_11; // @[Library.scala 115:37]
-  wire [31:0] wdata_value_31_6 = wdata_value_30_12 | wdata_value_30_13; // @[Library.scala 115:37]
-  wire [31:0] wdata_value_31_7 = wdata_value_30_14 | wdata_value_30_15; // @[Library.scala 115:37]
-  wire [31:0] wdata_value_31_8 = wdata_value_30_16 | wdata_value_30_17; // @[Library.scala 115:37]
-  wire [31:0] wdata_value_31_9 = wdata_value_30_18 | wdata_value_30_19; // @[Library.scala 115:37]
-  wire [31:0] wdata_value_31_10 = wdata_value_30_20 | wdata_value_30_21; // @[Library.scala 115:37]
-  wire [31:0] wdata_value_31_11 = wdata_value_30_22 | wdata_value_30_23; // @[Library.scala 115:37]
-  wire [31:0] wdata_value_31_12 = wdata_value_30_24 | wdata_value_30_25; // @[Library.scala 115:37]
-  wire [31:0] wdata_value_31_13 = wdata_value_30_26 | wdata_value_30_27; // @[Library.scala 115:37]
-  wire [31:0] wdata_value_31_14 = wdata_value_30_28 | wdata_value_30_29; // @[Library.scala 115:37]
-  wire [31:0] wdata_value_31_15 = wdata_value_30_30 | wdata_value_30_31; // @[Library.scala 115:37]
-  wire [31:0] wdata_value_32_0 = wdata_value_31_0 | wdata_value_31_1; // @[Library.scala 115:37]
-  wire [31:0] wdata_value_32_1 = wdata_value_31_2 | wdata_value_31_3; // @[Library.scala 115:37]
-  wire [31:0] wdata_value_32_2 = wdata_value_31_4 | wdata_value_31_5; // @[Library.scala 115:37]
-  wire [31:0] wdata_value_32_3 = wdata_value_31_6 | wdata_value_31_7; // @[Library.scala 115:37]
-  wire [31:0] wdata_value_32_4 = wdata_value_31_8 | wdata_value_31_9; // @[Library.scala 115:37]
-  wire [31:0] wdata_value_32_5 = wdata_value_31_10 | wdata_value_31_11; // @[Library.scala 115:37]
-  wire [31:0] wdata_value_32_6 = wdata_value_31_12 | wdata_value_31_13; // @[Library.scala 115:37]
-  wire [31:0] wdata_value_32_7 = wdata_value_31_14 | wdata_value_31_15; // @[Library.scala 115:37]
-  wire [31:0] wdata_value_33_0 = wdata_value_32_0 | wdata_value_32_1; // @[Library.scala 115:37]
-  wire [31:0] wdata_value_33_1 = wdata_value_32_2 | wdata_value_32_3; // @[Library.scala 115:37]
-  wire [31:0] wdata_value_33_2 = wdata_value_32_4 | wdata_value_32_5; // @[Library.scala 115:37]
-  wire [31:0] wdata_value_33_3 = wdata_value_32_6 | wdata_value_32_7; // @[Library.scala 115:37]
-  wire [31:0] wdata_value_34_0 = wdata_value_33_0 | wdata_value_33_1; // @[Library.scala 115:37]
-  wire [31:0] wdata_value_34_1 = wdata_value_33_2 | wdata_value_33_3; // @[Library.scala 115:37]
-  wire [31:0] wdata_value_35_0 = wdata_value_34_0 | wdata_value_34_1; // @[Library.scala 115:37]
-  reg  scoreboard_clr_error; // @[FRegfile.scala 136:37]
-  reg  scoreboard_set_error; // @[FRegfile.scala 137:37]
-  wire [31:0] _scoreboard_clr_error_T = scoreboard & scoreboard_clr; // @[FRegfile.scala 138:39]
-  wire [31:0] _scoreboard_set_error_T = scoreboard & scoreboard_set; // @[FRegfile.scala 139:39]
-  wire [31:0] _scoreboard_set_error_T_2 = _scoreboard_set_error_T & _scoreboard_T; // @[FRegfile.scala 139:56]
-  assign io_fbusPort_data = write_value_11_0 ? wdata_value_11_0 : rdata_value_11_0; // @[FRegfile.scala 123:21]
-  assign io_freadData_0_data = readDataBits_0; // @[FRegfile.scala 113:27]
-  assign io_freadData_1_data = readDataBits_1; // @[FRegfile.scala 113:27]
-  assign io_freadData_2_data = readDataBits_2; // @[FRegfile.scala 113:27]
-  assign io_freadData_3_data = readDataBits_3; // @[FRegfile.scala 113:27]
-  assign io_freadData_4_data = readDataBits_4; // @[FRegfile.scala 113:27]
-  assign io_freadData_5_data = readDataBits_5; // @[FRegfile.scala 113:27]
-  assign io_fscoreboard = scoreboard & _scoreboard_T; // @[FRegfile.scala 75:32]
-  always @(posedge clock) begin
-    if (fwriteValid_0) begin // @[FRegfile.scala 102:27]
-      fregfile_0 <= data; // @[FRegfile.scala 103:19]
-    end
-    if (fwriteValid_1) begin // @[FRegfile.scala 102:27]
-      fregfile_1 <= data_1; // @[FRegfile.scala 103:19]
-    end
-    if (fwriteValid_2) begin // @[FRegfile.scala 102:27]
-      fregfile_2 <= data_2; // @[FRegfile.scala 103:19]
-    end
-    if (fwriteValid_3) begin // @[FRegfile.scala 102:27]
-      fregfile_3 <= data_3; // @[FRegfile.scala 103:19]
-    end
-    if (fwriteValid_4) begin // @[FRegfile.scala 102:27]
-      fregfile_4 <= data_4; // @[FRegfile.scala 103:19]
-    end
-    if (fwriteValid_5) begin // @[FRegfile.scala 102:27]
-      fregfile_5 <= data_5; // @[FRegfile.scala 103:19]
-    end
-    if (fwriteValid_6) begin // @[FRegfile.scala 102:27]
-      fregfile_6 <= data_6; // @[FRegfile.scala 103:19]
-    end
-    if (fwriteValid_7) begin // @[FRegfile.scala 102:27]
-      fregfile_7 <= data_7; // @[FRegfile.scala 103:19]
-    end
-    if (fwriteValid_8) begin // @[FRegfile.scala 102:27]
-      fregfile_8 <= data_8; // @[FRegfile.scala 103:19]
-    end
-    if (fwriteValid_9) begin // @[FRegfile.scala 102:27]
-      fregfile_9 <= data_9; // @[FRegfile.scala 103:19]
-    end
-    if (fwriteValid_10) begin // @[FRegfile.scala 102:27]
-      fregfile_10 <= data_10; // @[FRegfile.scala 103:19]
-    end
-    if (fwriteValid_11) begin // @[FRegfile.scala 102:27]
-      fregfile_11 <= data_11; // @[FRegfile.scala 103:19]
-    end
-    if (fwriteValid_12) begin // @[FRegfile.scala 102:27]
-      fregfile_12 <= data_12; // @[FRegfile.scala 103:19]
-    end
-    if (fwriteValid_13) begin // @[FRegfile.scala 102:27]
-      fregfile_13 <= data_13; // @[FRegfile.scala 103:19]
-    end
-    if (fwriteValid_14) begin // @[FRegfile.scala 102:27]
-      fregfile_14 <= data_14; // @[FRegfile.scala 103:19]
-    end
-    if (fwriteValid_15) begin // @[FRegfile.scala 102:27]
-      fregfile_15 <= data_15; // @[FRegfile.scala 103:19]
-    end
-    if (fwriteValid_16) begin // @[FRegfile.scala 102:27]
-      fregfile_16 <= data_16; // @[FRegfile.scala 103:19]
-    end
-    if (fwriteValid_17) begin // @[FRegfile.scala 102:27]
-      fregfile_17 <= data_17; // @[FRegfile.scala 103:19]
-    end
-    if (fwriteValid_18) begin // @[FRegfile.scala 102:27]
-      fregfile_18 <= data_18; // @[FRegfile.scala 103:19]
-    end
-    if (fwriteValid_19) begin // @[FRegfile.scala 102:27]
-      fregfile_19 <= data_19; // @[FRegfile.scala 103:19]
-    end
-    if (fwriteValid_20) begin // @[FRegfile.scala 102:27]
-      fregfile_20 <= data_20; // @[FRegfile.scala 103:19]
-    end
-    if (fwriteValid_21) begin // @[FRegfile.scala 102:27]
-      fregfile_21 <= data_21; // @[FRegfile.scala 103:19]
-    end
-    if (fwriteValid_22) begin // @[FRegfile.scala 102:27]
-      fregfile_22 <= data_22; // @[FRegfile.scala 103:19]
-    end
-    if (fwriteValid_23) begin // @[FRegfile.scala 102:27]
-      fregfile_23 <= data_23; // @[FRegfile.scala 103:19]
-    end
-    if (fwriteValid_24) begin // @[FRegfile.scala 102:27]
-      fregfile_24 <= data_24; // @[FRegfile.scala 103:19]
-    end
-    if (fwriteValid_25) begin // @[FRegfile.scala 102:27]
-      fregfile_25 <= data_25; // @[FRegfile.scala 103:19]
-    end
-    if (fwriteValid_26) begin // @[FRegfile.scala 102:27]
-      fregfile_26 <= data_26; // @[FRegfile.scala 103:19]
-    end
-    if (fwriteValid_27) begin // @[FRegfile.scala 102:27]
-      fregfile_27 <= data_27; // @[FRegfile.scala 103:19]
-    end
-    if (fwriteValid_28) begin // @[FRegfile.scala 102:27]
-      fregfile_28 <= data_28; // @[FRegfile.scala 103:19]
-    end
-    if (fwriteValid_29) begin // @[FRegfile.scala 102:27]
-      fregfile_29 <= data_29; // @[FRegfile.scala 103:19]
-    end
-    if (fwriteValid_30) begin // @[FRegfile.scala 102:27]
-      fregfile_30 <= data_30; // @[FRegfile.scala 103:19]
-    end
-    if (fwriteValid_31) begin // @[FRegfile.scala 102:27]
-      fregfile_31 <= data_31; // @[FRegfile.scala 103:19]
-    end
-    if (io_freadAddr_0_valid) begin // @[FRegfile.scala 126:18]
-      if (write_value_5_0) begin // @[FRegfile.scala 123:21]
-        readDataBits_0 <= wdata_value_5_0;
-      end else begin
-        readDataBits_0 <= rdata_value_5_0;
-      end
-    end
-    if (io_freadAddr_1_valid) begin // @[FRegfile.scala 126:18]
-      if (write_value_11_0) begin // @[FRegfile.scala 123:21]
-        readDataBits_1 <= wdata_value_11_0;
-      end else begin
-        readDataBits_1 <= rdata_value_11_0;
-      end
-    end
-    if (io_freadAddr_2_valid) begin // @[FRegfile.scala 126:18]
-      if (write_value_17_0) begin // @[FRegfile.scala 123:21]
-        readDataBits_2 <= wdata_value_17_0;
-      end else begin
-        readDataBits_2 <= rdata_value_17_0;
-      end
-    end
-    if (io_freadAddr_3_valid) begin // @[FRegfile.scala 126:18]
-      if (write_value_23_0) begin // @[FRegfile.scala 123:21]
-        readDataBits_3 <= wdata_value_23_0;
-      end else begin
-        readDataBits_3 <= rdata_value_23_0;
-      end
-    end
-    if (io_freadAddr_4_valid) begin // @[FRegfile.scala 126:18]
-      if (write_value_29_0) begin // @[FRegfile.scala 123:21]
-        readDataBits_4 <= wdata_value_29_0;
-      end else begin
-        readDataBits_4 <= rdata_value_29_0;
-      end
-    end
-    if (io_freadAddr_5_valid) begin // @[FRegfile.scala 126:18]
-      if (write_value_35_0) begin // @[FRegfile.scala 123:21]
-        readDataBits_5 <= wdata_value_35_0;
-      end else begin
-        readDataBits_5 <= rdata_value_35_0;
-      end
-    end
-    `ifndef SYNTHESIS
-    `ifdef STOP_COND
-      if (`STOP_COND) begin
-    `endif
-        if (~reset & ~(_T_17 <= 3'h1)) begin
-          $fatal; // @[FRegfile.scala 98:11]
-        end
-    `ifdef STOP_COND
-      end
-    `endif
-    `endif // SYNTHESIS
-    `ifndef SYNTHESIS
-    `ifdef PRINTF_COND
-      if (`PRINTF_COND) begin
-    `endif
-        if (~reset & ~(_T_17 <= 3'h1)) begin
-          $fwrite(32'h80000002,"Assertion failed\n    at FRegfile.scala:98 assert(PopCount(valid) <= 1.U)\n"); // @[FRegfile.scala 98:11]
-        end
-    `ifdef PRINTF_COND
-      end
-    `endif
-    `endif // SYNTHESIS
-    `ifndef SYNTHESIS
-    `ifdef STOP_COND
-      if (`STOP_COND) begin
-    `endif
-        if (~reset & ~(_T_37 <= 3'h1)) begin
-          $fatal; // @[FRegfile.scala 98:11]
-        end
-    `ifdef STOP_COND
-      end
-    `endif
-    `endif // SYNTHESIS
-    `ifndef SYNTHESIS
-    `ifdef PRINTF_COND
-      if (`PRINTF_COND) begin
-    `endif
-        if (~reset & ~(_T_37 <= 3'h1)) begin
-          $fwrite(32'h80000002,"Assertion failed\n    at FRegfile.scala:98 assert(PopCount(valid) <= 1.U)\n"); // @[FRegfile.scala 98:11]
-        end
-    `ifdef PRINTF_COND
-      end
-    `endif
-    `endif // SYNTHESIS
-    `ifndef SYNTHESIS
-    `ifdef STOP_COND
-      if (`STOP_COND) begin
-    `endif
-        if (~reset & ~(_T_57 <= 3'h1)) begin
-          $fatal; // @[FRegfile.scala 98:11]
-        end
-    `ifdef STOP_COND
-      end
-    `endif
-    `endif // SYNTHESIS
-    `ifndef SYNTHESIS
-    `ifdef PRINTF_COND
-      if (`PRINTF_COND) begin
-    `endif
-        if (~reset & ~(_T_57 <= 3'h1)) begin
-          $fwrite(32'h80000002,"Assertion failed\n    at FRegfile.scala:98 assert(PopCount(valid) <= 1.U)\n"); // @[FRegfile.scala 98:11]
-        end
-    `ifdef PRINTF_COND
-      end
-    `endif
-    `endif // SYNTHESIS
-    `ifndef SYNTHESIS
-    `ifdef STOP_COND
-      if (`STOP_COND) begin
-    `endif
-        if (~reset & ~(_T_77 <= 3'h1)) begin
-          $fatal; // @[FRegfile.scala 98:11]
-        end
-    `ifdef STOP_COND
-      end
-    `endif
-    `endif // SYNTHESIS
-    `ifndef SYNTHESIS
-    `ifdef PRINTF_COND
-      if (`PRINTF_COND) begin
-    `endif
-        if (~reset & ~(_T_77 <= 3'h1)) begin
-          $fwrite(32'h80000002,"Assertion failed\n    at FRegfile.scala:98 assert(PopCount(valid) <= 1.U)\n"); // @[FRegfile.scala 98:11]
-        end
-    `ifdef PRINTF_COND
-      end
-    `endif
-    `endif // SYNTHESIS
-    `ifndef SYNTHESIS
-    `ifdef STOP_COND
-      if (`STOP_COND) begin
-    `endif
-        if (~reset & ~(_T_97 <= 3'h1)) begin
-          $fatal; // @[FRegfile.scala 98:11]
-        end
-    `ifdef STOP_COND
-      end
-    `endif
-    `endif // SYNTHESIS
-    `ifndef SYNTHESIS
-    `ifdef PRINTF_COND
-      if (`PRINTF_COND) begin
-    `endif
-        if (~reset & ~(_T_97 <= 3'h1)) begin
-          $fwrite(32'h80000002,"Assertion failed\n    at FRegfile.scala:98 assert(PopCount(valid) <= 1.U)\n"); // @[FRegfile.scala 98:11]
-        end
-    `ifdef PRINTF_COND
-      end
-    `endif
-    `endif // SYNTHESIS
-    `ifndef SYNTHESIS
-    `ifdef STOP_COND
-      if (`STOP_COND) begin
-    `endif
-        if (~reset & ~(_T_117 <= 3'h1)) begin
-          $fatal; // @[FRegfile.scala 98:11]
-        end
-    `ifdef STOP_COND
-      end
-    `endif
-    `endif // SYNTHESIS
-    `ifndef SYNTHESIS
-    `ifdef PRINTF_COND
-      if (`PRINTF_COND) begin
-    `endif
-        if (~reset & ~(_T_117 <= 3'h1)) begin
-          $fwrite(32'h80000002,"Assertion failed\n    at FRegfile.scala:98 assert(PopCount(valid) <= 1.U)\n"); // @[FRegfile.scala 98:11]
-        end
-    `ifdef PRINTF_COND
-      end
-    `endif
-    `endif // SYNTHESIS
-    `ifndef SYNTHESIS
-    `ifdef STOP_COND
-      if (`STOP_COND) begin
-    `endif
-        if (~reset & ~(_T_137 <= 3'h1)) begin
-          $fatal; // @[FRegfile.scala 98:11]
-        end
-    `ifdef STOP_COND
-      end
-    `endif
-    `endif // SYNTHESIS
-    `ifndef SYNTHESIS
-    `ifdef PRINTF_COND
-      if (`PRINTF_COND) begin
-    `endif
-        if (~reset & ~(_T_137 <= 3'h1)) begin
-          $fwrite(32'h80000002,"Assertion failed\n    at FRegfile.scala:98 assert(PopCount(valid) <= 1.U)\n"); // @[FRegfile.scala 98:11]
-        end
-    `ifdef PRINTF_COND
-      end
-    `endif
-    `endif // SYNTHESIS
-    `ifndef SYNTHESIS
-    `ifdef STOP_COND
-      if (`STOP_COND) begin
-    `endif
-        if (~reset & ~(_T_157 <= 3'h1)) begin
-          $fatal; // @[FRegfile.scala 98:11]
-        end
-    `ifdef STOP_COND
-      end
-    `endif
-    `endif // SYNTHESIS
-    `ifndef SYNTHESIS
-    `ifdef PRINTF_COND
-      if (`PRINTF_COND) begin
-    `endif
-        if (~reset & ~(_T_157 <= 3'h1)) begin
-          $fwrite(32'h80000002,"Assertion failed\n    at FRegfile.scala:98 assert(PopCount(valid) <= 1.U)\n"); // @[FRegfile.scala 98:11]
-        end
-    `ifdef PRINTF_COND
-      end
-    `endif
-    `endif // SYNTHESIS
-    `ifndef SYNTHESIS
-    `ifdef STOP_COND
-      if (`STOP_COND) begin
-    `endif
-        if (~reset & ~(_T_177 <= 3'h1)) begin
-          $fatal; // @[FRegfile.scala 98:11]
-        end
-    `ifdef STOP_COND
-      end
-    `endif
-    `endif // SYNTHESIS
-    `ifndef SYNTHESIS
-    `ifdef PRINTF_COND
-      if (`PRINTF_COND) begin
-    `endif
-        if (~reset & ~(_T_177 <= 3'h1)) begin
-          $fwrite(32'h80000002,"Assertion failed\n    at FRegfile.scala:98 assert(PopCount(valid) <= 1.U)\n"); // @[FRegfile.scala 98:11]
-        end
-    `ifdef PRINTF_COND
-      end
-    `endif
-    `endif // SYNTHESIS
-    `ifndef SYNTHESIS
-    `ifdef STOP_COND
-      if (`STOP_COND) begin
-    `endif
-        if (~reset & ~(_T_197 <= 3'h1)) begin
-          $fatal; // @[FRegfile.scala 98:11]
-        end
-    `ifdef STOP_COND
-      end
-    `endif
-    `endif // SYNTHESIS
-    `ifndef SYNTHESIS
-    `ifdef PRINTF_COND
-      if (`PRINTF_COND) begin
-    `endif
-        if (~reset & ~(_T_197 <= 3'h1)) begin
-          $fwrite(32'h80000002,"Assertion failed\n    at FRegfile.scala:98 assert(PopCount(valid) <= 1.U)\n"); // @[FRegfile.scala 98:11]
-        end
-    `ifdef PRINTF_COND
-      end
-    `endif
-    `endif // SYNTHESIS
-    `ifndef SYNTHESIS
-    `ifdef STOP_COND
-      if (`STOP_COND) begin
-    `endif
-        if (~reset & ~(_T_217 <= 3'h1)) begin
-          $fatal; // @[FRegfile.scala 98:11]
-        end
-    `ifdef STOP_COND
-      end
-    `endif
-    `endif // SYNTHESIS
-    `ifndef SYNTHESIS
-    `ifdef PRINTF_COND
-      if (`PRINTF_COND) begin
-    `endif
-        if (~reset & ~(_T_217 <= 3'h1)) begin
-          $fwrite(32'h80000002,"Assertion failed\n    at FRegfile.scala:98 assert(PopCount(valid) <= 1.U)\n"); // @[FRegfile.scala 98:11]
-        end
-    `ifdef PRINTF_COND
-      end
-    `endif
-    `endif // SYNTHESIS
-    `ifndef SYNTHESIS
-    `ifdef STOP_COND
-      if (`STOP_COND) begin
-    `endif
-        if (~reset & ~(_T_237 <= 3'h1)) begin
-          $fatal; // @[FRegfile.scala 98:11]
-        end
-    `ifdef STOP_COND
-      end
-    `endif
-    `endif // SYNTHESIS
-    `ifndef SYNTHESIS
-    `ifdef PRINTF_COND
-      if (`PRINTF_COND) begin
-    `endif
-        if (~reset & ~(_T_237 <= 3'h1)) begin
-          $fwrite(32'h80000002,"Assertion failed\n    at FRegfile.scala:98 assert(PopCount(valid) <= 1.U)\n"); // @[FRegfile.scala 98:11]
-        end
-    `ifdef PRINTF_COND
-      end
-    `endif
-    `endif // SYNTHESIS
-    `ifndef SYNTHESIS
-    `ifdef STOP_COND
-      if (`STOP_COND) begin
-    `endif
-        if (~reset & ~(_T_257 <= 3'h1)) begin
-          $fatal; // @[FRegfile.scala 98:11]
-        end
-    `ifdef STOP_COND
-      end
-    `endif
-    `endif // SYNTHESIS
-    `ifndef SYNTHESIS
-    `ifdef PRINTF_COND
-      if (`PRINTF_COND) begin
-    `endif
-        if (~reset & ~(_T_257 <= 3'h1)) begin
-          $fwrite(32'h80000002,"Assertion failed\n    at FRegfile.scala:98 assert(PopCount(valid) <= 1.U)\n"); // @[FRegfile.scala 98:11]
-        end
-    `ifdef PRINTF_COND
-      end
-    `endif
-    `endif // SYNTHESIS
-    `ifndef SYNTHESIS
-    `ifdef STOP_COND
-      if (`STOP_COND) begin
-    `endif
-        if (~reset & ~(_T_277 <= 3'h1)) begin
-          $fatal; // @[FRegfile.scala 98:11]
-        end
-    `ifdef STOP_COND
-      end
-    `endif
-    `endif // SYNTHESIS
-    `ifndef SYNTHESIS
-    `ifdef PRINTF_COND
-      if (`PRINTF_COND) begin
-    `endif
-        if (~reset & ~(_T_277 <= 3'h1)) begin
-          $fwrite(32'h80000002,"Assertion failed\n    at FRegfile.scala:98 assert(PopCount(valid) <= 1.U)\n"); // @[FRegfile.scala 98:11]
-        end
-    `ifdef PRINTF_COND
-      end
-    `endif
-    `endif // SYNTHESIS
-    `ifndef SYNTHESIS
-    `ifdef STOP_COND
-      if (`STOP_COND) begin
-    `endif
-        if (~reset & ~(_T_297 <= 3'h1)) begin
-          $fatal; // @[FRegfile.scala 98:11]
-        end
-    `ifdef STOP_COND
-      end
-    `endif
-    `endif // SYNTHESIS
-    `ifndef SYNTHESIS
-    `ifdef PRINTF_COND
-      if (`PRINTF_COND) begin
-    `endif
-        if (~reset & ~(_T_297 <= 3'h1)) begin
-          $fwrite(32'h80000002,"Assertion failed\n    at FRegfile.scala:98 assert(PopCount(valid) <= 1.U)\n"); // @[FRegfile.scala 98:11]
-        end
-    `ifdef PRINTF_COND
-      end
-    `endif
-    `endif // SYNTHESIS
-    `ifndef SYNTHESIS
-    `ifdef STOP_COND
-      if (`STOP_COND) begin
-    `endif
-        if (~reset & ~(_T_317 <= 3'h1)) begin
-          $fatal; // @[FRegfile.scala 98:11]
-        end
-    `ifdef STOP_COND
-      end
-    `endif
-    `endif // SYNTHESIS
-    `ifndef SYNTHESIS
-    `ifdef PRINTF_COND
-      if (`PRINTF_COND) begin
-    `endif
-        if (~reset & ~(_T_317 <= 3'h1)) begin
-          $fwrite(32'h80000002,"Assertion failed\n    at FRegfile.scala:98 assert(PopCount(valid) <= 1.U)\n"); // @[FRegfile.scala 98:11]
-        end
-    `ifdef PRINTF_COND
-      end
-    `endif
-    `endif // SYNTHESIS
-    `ifndef SYNTHESIS
-    `ifdef STOP_COND
-      if (`STOP_COND) begin
-    `endif
-        if (~reset & ~(_T_337 <= 3'h1)) begin
-          $fatal; // @[FRegfile.scala 98:11]
-        end
-    `ifdef STOP_COND
-      end
-    `endif
-    `endif // SYNTHESIS
-    `ifndef SYNTHESIS
-    `ifdef PRINTF_COND
-      if (`PRINTF_COND) begin
-    `endif
-        if (~reset & ~(_T_337 <= 3'h1)) begin
-          $fwrite(32'h80000002,"Assertion failed\n    at FRegfile.scala:98 assert(PopCount(valid) <= 1.U)\n"); // @[FRegfile.scala 98:11]
-        end
-    `ifdef PRINTF_COND
-      end
-    `endif
-    `endif // SYNTHESIS
-    `ifndef SYNTHESIS
-    `ifdef STOP_COND
-      if (`STOP_COND) begin
-    `endif
-        if (~reset & ~(_T_357 <= 3'h1)) begin
-          $fatal; // @[FRegfile.scala 98:11]
-        end
-    `ifdef STOP_COND
-      end
-    `endif
-    `endif // SYNTHESIS
-    `ifndef SYNTHESIS
-    `ifdef PRINTF_COND
-      if (`PRINTF_COND) begin
-    `endif
-        if (~reset & ~(_T_357 <= 3'h1)) begin
-          $fwrite(32'h80000002,"Assertion failed\n    at FRegfile.scala:98 assert(PopCount(valid) <= 1.U)\n"); // @[FRegfile.scala 98:11]
-        end
-    `ifdef PRINTF_COND
-      end
-    `endif
-    `endif // SYNTHESIS
-    `ifndef SYNTHESIS
-    `ifdef STOP_COND
-      if (`STOP_COND) begin
-    `endif
-        if (~reset & ~(_T_377 <= 3'h1)) begin
-          $fatal; // @[FRegfile.scala 98:11]
-        end
-    `ifdef STOP_COND
-      end
-    `endif
-    `endif // SYNTHESIS
-    `ifndef SYNTHESIS
-    `ifdef PRINTF_COND
-      if (`PRINTF_COND) begin
-    `endif
-        if (~reset & ~(_T_377 <= 3'h1)) begin
-          $fwrite(32'h80000002,"Assertion failed\n    at FRegfile.scala:98 assert(PopCount(valid) <= 1.U)\n"); // @[FRegfile.scala 98:11]
-        end
-    `ifdef PRINTF_COND
-      end
-    `endif
-    `endif // SYNTHESIS
-    `ifndef SYNTHESIS
-    `ifdef STOP_COND
-      if (`STOP_COND) begin
-    `endif
-        if (~reset & ~(_T_397 <= 3'h1)) begin
-          $fatal; // @[FRegfile.scala 98:11]
-        end
-    `ifdef STOP_COND
-      end
-    `endif
-    `endif // SYNTHESIS
-    `ifndef SYNTHESIS
-    `ifdef PRINTF_COND
-      if (`PRINTF_COND) begin
-    `endif
-        if (~reset & ~(_T_397 <= 3'h1)) begin
-          $fwrite(32'h80000002,"Assertion failed\n    at FRegfile.scala:98 assert(PopCount(valid) <= 1.U)\n"); // @[FRegfile.scala 98:11]
-        end
-    `ifdef PRINTF_COND
-      end
-    `endif
-    `endif // SYNTHESIS
-    `ifndef SYNTHESIS
-    `ifdef STOP_COND
-      if (`STOP_COND) begin
-    `endif
-        if (~reset & ~(_T_417 <= 3'h1)) begin
-          $fatal; // @[FRegfile.scala 98:11]
-        end
-    `ifdef STOP_COND
-      end
-    `endif
-    `endif // SYNTHESIS
-    `ifndef SYNTHESIS
-    `ifdef PRINTF_COND
-      if (`PRINTF_COND) begin
-    `endif
-        if (~reset & ~(_T_417 <= 3'h1)) begin
-          $fwrite(32'h80000002,"Assertion failed\n    at FRegfile.scala:98 assert(PopCount(valid) <= 1.U)\n"); // @[FRegfile.scala 98:11]
-        end
-    `ifdef PRINTF_COND
-      end
-    `endif
-    `endif // SYNTHESIS
-    `ifndef SYNTHESIS
-    `ifdef STOP_COND
-      if (`STOP_COND) begin
-    `endif
-        if (~reset & ~(_T_437 <= 3'h1)) begin
-          $fatal; // @[FRegfile.scala 98:11]
-        end
-    `ifdef STOP_COND
-      end
-    `endif
-    `endif // SYNTHESIS
-    `ifndef SYNTHESIS
-    `ifdef PRINTF_COND
-      if (`PRINTF_COND) begin
-    `endif
-        if (~reset & ~(_T_437 <= 3'h1)) begin
-          $fwrite(32'h80000002,"Assertion failed\n    at FRegfile.scala:98 assert(PopCount(valid) <= 1.U)\n"); // @[FRegfile.scala 98:11]
-        end
-    `ifdef PRINTF_COND
-      end
-    `endif
-    `endif // SYNTHESIS
-    `ifndef SYNTHESIS
-    `ifdef STOP_COND
-      if (`STOP_COND) begin
-    `endif
-        if (~reset & ~(_T_457 <= 3'h1)) begin
-          $fatal; // @[FRegfile.scala 98:11]
-        end
-    `ifdef STOP_COND
-      end
-    `endif
-    `endif // SYNTHESIS
-    `ifndef SYNTHESIS
-    `ifdef PRINTF_COND
-      if (`PRINTF_COND) begin
-    `endif
-        if (~reset & ~(_T_457 <= 3'h1)) begin
-          $fwrite(32'h80000002,"Assertion failed\n    at FRegfile.scala:98 assert(PopCount(valid) <= 1.U)\n"); // @[FRegfile.scala 98:11]
-        end
-    `ifdef PRINTF_COND
-      end
-    `endif
-    `endif // SYNTHESIS
-    `ifndef SYNTHESIS
-    `ifdef STOP_COND
-      if (`STOP_COND) begin
-    `endif
-        if (~reset & ~(_T_477 <= 3'h1)) begin
-          $fatal; // @[FRegfile.scala 98:11]
-        end
-    `ifdef STOP_COND
-      end
-    `endif
-    `endif // SYNTHESIS
-    `ifndef SYNTHESIS
-    `ifdef PRINTF_COND
-      if (`PRINTF_COND) begin
-    `endif
-        if (~reset & ~(_T_477 <= 3'h1)) begin
-          $fwrite(32'h80000002,"Assertion failed\n    at FRegfile.scala:98 assert(PopCount(valid) <= 1.U)\n"); // @[FRegfile.scala 98:11]
-        end
-    `ifdef PRINTF_COND
-      end
-    `endif
-    `endif // SYNTHESIS
-    `ifndef SYNTHESIS
-    `ifdef STOP_COND
-      if (`STOP_COND) begin
-    `endif
-        if (~reset & ~(_T_497 <= 3'h1)) begin
-          $fatal; // @[FRegfile.scala 98:11]
-        end
-    `ifdef STOP_COND
-      end
-    `endif
-    `endif // SYNTHESIS
-    `ifndef SYNTHESIS
-    `ifdef PRINTF_COND
-      if (`PRINTF_COND) begin
-    `endif
-        if (~reset & ~(_T_497 <= 3'h1)) begin
-          $fwrite(32'h80000002,"Assertion failed\n    at FRegfile.scala:98 assert(PopCount(valid) <= 1.U)\n"); // @[FRegfile.scala 98:11]
-        end
-    `ifdef PRINTF_COND
-      end
-    `endif
-    `endif // SYNTHESIS
-    `ifndef SYNTHESIS
-    `ifdef STOP_COND
-      if (`STOP_COND) begin
-    `endif
-        if (~reset & ~(_T_517 <= 3'h1)) begin
-          $fatal; // @[FRegfile.scala 98:11]
-        end
-    `ifdef STOP_COND
-      end
-    `endif
-    `endif // SYNTHESIS
-    `ifndef SYNTHESIS
-    `ifdef PRINTF_COND
-      if (`PRINTF_COND) begin
-    `endif
-        if (~reset & ~(_T_517 <= 3'h1)) begin
-          $fwrite(32'h80000002,"Assertion failed\n    at FRegfile.scala:98 assert(PopCount(valid) <= 1.U)\n"); // @[FRegfile.scala 98:11]
-        end
-    `ifdef PRINTF_COND
-      end
-    `endif
-    `endif // SYNTHESIS
-    `ifndef SYNTHESIS
-    `ifdef STOP_COND
-      if (`STOP_COND) begin
-    `endif
-        if (~reset & ~(_T_537 <= 3'h1)) begin
-          $fatal; // @[FRegfile.scala 98:11]
-        end
-    `ifdef STOP_COND
-      end
-    `endif
-    `endif // SYNTHESIS
-    `ifndef SYNTHESIS
-    `ifdef PRINTF_COND
-      if (`PRINTF_COND) begin
-    `endif
-        if (~reset & ~(_T_537 <= 3'h1)) begin
-          $fwrite(32'h80000002,"Assertion failed\n    at FRegfile.scala:98 assert(PopCount(valid) <= 1.U)\n"); // @[FRegfile.scala 98:11]
-        end
-    `ifdef PRINTF_COND
-      end
-    `endif
-    `endif // SYNTHESIS
-    `ifndef SYNTHESIS
-    `ifdef STOP_COND
-      if (`STOP_COND) begin
-    `endif
-        if (~reset & ~(_T_557 <= 3'h1)) begin
-          $fatal; // @[FRegfile.scala 98:11]
-        end
-    `ifdef STOP_COND
-      end
-    `endif
-    `endif // SYNTHESIS
-    `ifndef SYNTHESIS
-    `ifdef PRINTF_COND
-      if (`PRINTF_COND) begin
-    `endif
-        if (~reset & ~(_T_557 <= 3'h1)) begin
-          $fwrite(32'h80000002,"Assertion failed\n    at FRegfile.scala:98 assert(PopCount(valid) <= 1.U)\n"); // @[FRegfile.scala 98:11]
-        end
-    `ifdef PRINTF_COND
-      end
-    `endif
-    `endif // SYNTHESIS
-    `ifndef SYNTHESIS
-    `ifdef STOP_COND
-      if (`STOP_COND) begin
-    `endif
-        if (~reset & ~(_T_577 <= 3'h1)) begin
-          $fatal; // @[FRegfile.scala 98:11]
-        end
-    `ifdef STOP_COND
-      end
-    `endif
-    `endif // SYNTHESIS
-    `ifndef SYNTHESIS
-    `ifdef PRINTF_COND
-      if (`PRINTF_COND) begin
-    `endif
-        if (~reset & ~(_T_577 <= 3'h1)) begin
-          $fwrite(32'h80000002,"Assertion failed\n    at FRegfile.scala:98 assert(PopCount(valid) <= 1.U)\n"); // @[FRegfile.scala 98:11]
-        end
-    `ifdef PRINTF_COND
-      end
-    `endif
-    `endif // SYNTHESIS
-    `ifndef SYNTHESIS
-    `ifdef STOP_COND
-      if (`STOP_COND) begin
-    `endif
-        if (~reset & ~(_T_597 <= 3'h1)) begin
-          $fatal; // @[FRegfile.scala 98:11]
-        end
-    `ifdef STOP_COND
-      end
-    `endif
-    `endif // SYNTHESIS
-    `ifndef SYNTHESIS
-    `ifdef PRINTF_COND
-      if (`PRINTF_COND) begin
-    `endif
-        if (~reset & ~(_T_597 <= 3'h1)) begin
-          $fwrite(32'h80000002,"Assertion failed\n    at FRegfile.scala:98 assert(PopCount(valid) <= 1.U)\n"); // @[FRegfile.scala 98:11]
-        end
-    `ifdef PRINTF_COND
-      end
-    `endif
-    `endif // SYNTHESIS
-    `ifndef SYNTHESIS
-    `ifdef STOP_COND
-      if (`STOP_COND) begin
-    `endif
-        if (~reset & ~(_T_617 <= 3'h1)) begin
-          $fatal; // @[FRegfile.scala 98:11]
-        end
-    `ifdef STOP_COND
-      end
-    `endif
-    `endif // SYNTHESIS
-    `ifndef SYNTHESIS
-    `ifdef PRINTF_COND
-      if (`PRINTF_COND) begin
-    `endif
-        if (~reset & ~(_T_617 <= 3'h1)) begin
-          $fwrite(32'h80000002,"Assertion failed\n    at FRegfile.scala:98 assert(PopCount(valid) <= 1.U)\n"); // @[FRegfile.scala 98:11]
-        end
-    `ifdef PRINTF_COND
-      end
-    `endif
-    `endif // SYNTHESIS
-    `ifndef SYNTHESIS
-    `ifdef STOP_COND
-      if (`STOP_COND) begin
-    `endif
-        if (~reset & ~(_T_637 <= 3'h1)) begin
-          $fatal; // @[FRegfile.scala 98:11]
-        end
-    `ifdef STOP_COND
-      end
-    `endif
-    `endif // SYNTHESIS
-    `ifndef SYNTHESIS
-    `ifdef PRINTF_COND
-      if (`PRINTF_COND) begin
-    `endif
-        if (~reset & ~(_T_637 <= 3'h1)) begin
-          $fwrite(32'h80000002,"Assertion failed\n    at FRegfile.scala:98 assert(PopCount(valid) <= 1.U)\n"); // @[FRegfile.scala 98:11]
-        end
-    `ifdef PRINTF_COND
-      end
-    `endif
-    `endif // SYNTHESIS
-    `ifndef SYNTHESIS
-    `ifdef STOP_COND
-      if (`STOP_COND) begin
-    `endif
-        if (_T_21 & ~(~scoreboard_clr_error)) begin
-          $fatal; // @[FRegfile.scala 140:9]
-        end
-    `ifdef STOP_COND
-      end
-    `endif
-    `endif // SYNTHESIS
-    `ifndef SYNTHESIS
-    `ifdef PRINTF_COND
-      if (`PRINTF_COND) begin
-    `endif
-        if (_T_21 & ~(~scoreboard_clr_error)) begin
-          $fwrite(32'h80000002,"Assertion failed\n    at FRegfile.scala:140 assert(!scoreboard_clr_error)\n"); // @[FRegfile.scala 140:9]
-        end
-    `ifdef PRINTF_COND
-      end
-    `endif
-    `endif // SYNTHESIS
-    `ifndef SYNTHESIS
-    `ifdef STOP_COND
-      if (`STOP_COND) begin
-    `endif
-        if (_T_21 & ~(~scoreboard_set_error)) begin
-          $fatal; // @[FRegfile.scala 141:9]
-        end
-    `ifdef STOP_COND
-      end
-    `endif
-    `endif // SYNTHESIS
-    `ifndef SYNTHESIS
-    `ifdef PRINTF_COND
-      if (`PRINTF_COND) begin
-    `endif
-        if (_T_21 & ~(~scoreboard_set_error)) begin
-          $fwrite(32'h80000002,"Assertion failed\n    at FRegfile.scala:141 assert(!scoreboard_set_error)\n"); // @[FRegfile.scala 141:9]
-        end
-    `ifdef PRINTF_COND
-      end
-    `endif
-    `endif // SYNTHESIS
-  end
-  always @(posedge clock or posedge reset) begin
-    if (reset) begin // @[FRegfile.scala 71:59]
-      scoreboard <= 32'h0; // @[FRegfile.scala 72:16]
-    end else if (scoreboard_set != 32'h0 | scoreboard_clr != 32'h0) begin // @[FRegfile.scala 58:27]
-      scoreboard <= _scoreboard_T_2;
-    end
-  end
-  always @(posedge clock or posedge reset) begin
-    if (reset) begin // @[FRegfile.scala 138:57]
-      scoreboard_clr_error <= 1'h0;
-    end else begin
-      scoreboard_clr_error <= _scoreboard_clr_error_T != scoreboard_clr;
-    end
-  end
-  always @(posedge clock or posedge reset) begin
-    if (reset) begin // @[FRegfile.scala 139:75]
-      scoreboard_set_error <= 1'h0;
-    end else begin
-      scoreboard_set_error <= _scoreboard_set_error_T_2 != 32'h0;
-    end
-  end
-// Register and memory initialization
-`ifdef RANDOMIZE_GARBAGE_ASSIGN
-`define RANDOMIZE
-`endif
-`ifdef RANDOMIZE_INVALID_ASSIGN
-`define RANDOMIZE
-`endif
-`ifdef RANDOMIZE_REG_INIT
-`define RANDOMIZE
-`endif
-`ifdef RANDOMIZE_MEM_INIT
-`define RANDOMIZE
-`endif
-`ifndef RANDOM
-`define RANDOM $random
-`endif
-`ifdef RANDOMIZE_MEM_INIT
-  integer initvar;
-`endif
-`ifndef SYNTHESIS
-`ifdef FIRRTL_BEFORE_INITIAL
-`FIRRTL_BEFORE_INITIAL
-`endif
-initial begin
-  `ifdef RANDOMIZE
-    `ifdef INIT_RANDOM
-      `INIT_RANDOM
-    `endif
-    `ifndef VERILATOR
-      `ifdef RANDOMIZE_DELAY
-        #`RANDOMIZE_DELAY begin end
-      `else
-        #0.002 begin end
-      `endif
-    `endif
-`ifdef RANDOMIZE_REG_INIT
-  _RAND_0 = {1{`RANDOM}};
-  fregfile_0 = _RAND_0[31:0];
-  _RAND_1 = {1{`RANDOM}};
-  fregfile_1 = _RAND_1[31:0];
-  _RAND_2 = {1{`RANDOM}};
-  fregfile_2 = _RAND_2[31:0];
-  _RAND_3 = {1{`RANDOM}};
-  fregfile_3 = _RAND_3[31:0];
-  _RAND_4 = {1{`RANDOM}};
-  fregfile_4 = _RAND_4[31:0];
-  _RAND_5 = {1{`RANDOM}};
-  fregfile_5 = _RAND_5[31:0];
-  _RAND_6 = {1{`RANDOM}};
-  fregfile_6 = _RAND_6[31:0];
-  _RAND_7 = {1{`RANDOM}};
-  fregfile_7 = _RAND_7[31:0];
-  _RAND_8 = {1{`RANDOM}};
-  fregfile_8 = _RAND_8[31:0];
-  _RAND_9 = {1{`RANDOM}};
-  fregfile_9 = _RAND_9[31:0];
-  _RAND_10 = {1{`RANDOM}};
-  fregfile_10 = _RAND_10[31:0];
-  _RAND_11 = {1{`RANDOM}};
-  fregfile_11 = _RAND_11[31:0];
-  _RAND_12 = {1{`RANDOM}};
-  fregfile_12 = _RAND_12[31:0];
-  _RAND_13 = {1{`RANDOM}};
-  fregfile_13 = _RAND_13[31:0];
-  _RAND_14 = {1{`RANDOM}};
-  fregfile_14 = _RAND_14[31:0];
-  _RAND_15 = {1{`RANDOM}};
-  fregfile_15 = _RAND_15[31:0];
-  _RAND_16 = {1{`RANDOM}};
-  fregfile_16 = _RAND_16[31:0];
-  _RAND_17 = {1{`RANDOM}};
-  fregfile_17 = _RAND_17[31:0];
-  _RAND_18 = {1{`RANDOM}};
-  fregfile_18 = _RAND_18[31:0];
-  _RAND_19 = {1{`RANDOM}};
-  fregfile_19 = _RAND_19[31:0];
-  _RAND_20 = {1{`RANDOM}};
-  fregfile_20 = _RAND_20[31:0];
-  _RAND_21 = {1{`RANDOM}};
-  fregfile_21 = _RAND_21[31:0];
-  _RAND_22 = {1{`RANDOM}};
-  fregfile_22 = _RAND_22[31:0];
-  _RAND_23 = {1{`RANDOM}};
-  fregfile_23 = _RAND_23[31:0];
-  _RAND_24 = {1{`RANDOM}};
-  fregfile_24 = _RAND_24[31:0];
-  _RAND_25 = {1{`RANDOM}};
-  fregfile_25 = _RAND_25[31:0];
-  _RAND_26 = {1{`RANDOM}};
-  fregfile_26 = _RAND_26[31:0];
-  _RAND_27 = {1{`RANDOM}};
-  fregfile_27 = _RAND_27[31:0];
-  _RAND_28 = {1{`RANDOM}};
-  fregfile_28 = _RAND_28[31:0];
-  _RAND_29 = {1{`RANDOM}};
-  fregfile_29 = _RAND_29[31:0];
-  _RAND_30 = {1{`RANDOM}};
-  fregfile_30 = _RAND_30[31:0];
-  _RAND_31 = {1{`RANDOM}};
-  fregfile_31 = _RAND_31[31:0];
-  _RAND_32 = {1{`RANDOM}};
-  scoreboard = _RAND_32[31:0];
-  _RAND_33 = {1{`RANDOM}};
-  readDataBits_0 = _RAND_33[31:0];
-  _RAND_34 = {1{`RANDOM}};
-  readDataBits_1 = _RAND_34[31:0];
-  _RAND_35 = {1{`RANDOM}};
-  readDataBits_2 = _RAND_35[31:0];
-  _RAND_36 = {1{`RANDOM}};
-  readDataBits_3 = _RAND_36[31:0];
-  _RAND_37 = {1{`RANDOM}};
-  readDataBits_4 = _RAND_37[31:0];
-  _RAND_38 = {1{`RANDOM}};
-  readDataBits_5 = _RAND_38[31:0];
-  _RAND_39 = {1{`RANDOM}};
-  scoreboard_clr_error = _RAND_39[0:0];
-  _RAND_40 = {1{`RANDOM}};
-  scoreboard_set_error = _RAND_40[0:0];
-`endif // RANDOMIZE_REG_INIT
-  if (reset) begin
-    scoreboard = 32'h0;
-  end
-  if (reset) begin
-    scoreboard_clr_error = 1'h0;
-  end
-  if (reset) begin
-    scoreboard_set_error = 1'h0;
-  end
-  `endif // RANDOMIZE
-end // initial
-`ifdef FIRRTL_AFTER_INITIAL
-`FIRRTL_AFTER_INITIAL
-`endif
-`endif // SYNTHESIS
-endmodule
-module FAdd(
-  input         clock,
-  input         reset,
-  output        io_ina_ready,
-  input         io_ina_valid,
-  input  [31:0] io_ina_bits,
-  output        io_inb_ready,
-  input  [31:0] io_inb_bits,
-  output        io_out_valid,
-  output [31:0] io_out_bits
-);
-`ifdef RANDOMIZE_REG_INIT
-  reg [31:0] _RAND_0;
-  reg [31:0] _RAND_1;
-  reg [31:0] _RAND_2;
-  reg [31:0] _RAND_3;
-  reg [31:0] _RAND_4;
-  reg [31:0] _RAND_5;
-  reg [31:0] _RAND_6;
-  reg [31:0] _RAND_7;
-  reg [31:0] _RAND_8;
-  reg [31:0] _RAND_9;
-  reg [31:0] _RAND_10;
-  reg [31:0] _RAND_11;
-  reg [31:0] _RAND_12;
-  reg [31:0] _RAND_13;
-  reg [31:0] _RAND_14;
-`endif // RANDOMIZE_REG_INIT
-  reg  active1; // @[FAdd.scala 20:24]
-  reg  active2; // @[FAdd.scala 21:24]
-  reg  state1__signa; // @[FAdd.scala 22:19]
-  reg  state1__signb; // @[FAdd.scala 22:19]
-  reg [7:0] state1__exp; // @[FAdd.scala 22:19]
-  reg [23:0] state1__man; // @[FAdd.scala 22:19]
-  reg [28:0] state1__add; // @[FAdd.scala 22:19]
-  reg  state1__zeroa; // @[FAdd.scala 22:19]
-  reg  state1__zerob; // @[FAdd.scala 22:19]
-  reg  state1__infa; // @[FAdd.scala 22:19]
-  reg  state1__infb; // @[FAdd.scala 22:19]
-  reg  state1__nan; // @[FAdd.scala 22:19]
-  reg  state2_sign; // @[FAdd.scala 23:19]
-  reg [7:0] state2_exp; // @[FAdd.scala 23:19]
-  reg [22:0] state2_man; // @[FAdd.scala 23:19]
-  wire  update1 = io_ina_valid & io_ina_ready & io_inb_ready; // @[FAdd.scala 25:62]
-  wire  state1_zeroa = io_ina_bits[30:0] == 31'h0; // @[FBase.scala 76:18]
-  wire  state1_zerob = io_inb_bits[30:0] == 31'h0; // @[FBase.scala 76:18]
-  wire  _state1_infa_T_1 = io_ina_bits[30:23] == 8'hff; // @[FBase.scala 64:19]
-  wire  state1_infa = io_ina_bits[30:23] == 8'hff & io_ina_bits[22:0] == 23'h0; // @[FBase.scala 64:37]
-  wire  _state1_infb_T_1 = io_inb_bits[30:23] == 8'hff; // @[FBase.scala 64:19]
-  wire  state1_infb = io_inb_bits[30:23] == 8'hff & io_inb_bits[22:0] == 23'h0; // @[FBase.scala 64:37]
-  wire  _state1_nana_T_3 = io_ina_bits[22:0] != 23'h0; // @[FBase.scala 68:50]
-  wire  state1_nana = _state1_infa_T_1 & io_ina_bits[22:0] != 23'h0; // @[FBase.scala 68:37]
-  wire  _state1_nanb_T_3 = io_inb_bits[22:0] != 23'h0; // @[FBase.scala 68:50]
-  wire  state1_nanb = _state1_infb_T_1 & io_inb_bits[22:0] != 23'h0; // @[FBase.scala 68:37]
-  wire  state1_subna = io_ina_bits[30:23] == 8'h0 & _state1_nana_T_3; // @[FBase.scala 72:27]
-  wire  state1_subnb = io_inb_bits[30:23] == 8'h0 & _state1_nanb_T_3; // @[FBase.scala 72:27]
-  wire  state1_signa = io_ina_bits[31]; // @[FBase.scala 28:14]
-  wire  state1_signb = io_inb_bits[31]; // @[FBase.scala 28:14]
-  wire [7:0] state1_iexpa = state1_subna ? 8'h1 : io_ina_bits[30:23]; // @[FAdd.scala 104:20]
-  wire [7:0] state1_iexpb = state1_subnb ? 8'h1 : io_inb_bits[30:23]; // @[FAdd.scala 105:20]
-  wire  _state1_imana_T = state1_subna ? 1'h0 : 1'h1; // @[FAdd.scala 106:24]
-  wire  _state1_imanb_T = state1_subnb ? 1'h0 : 1'h1; // @[FAdd.scala 107:24]
-  wire [28:0] state1_adda_cman_a = {2'h0,_state1_imana_T,io_ina_bits[22:0],3'h0}; // @[Cat.scala 31:58]
-  wire [28:0] state1_adda_cman_b = {2'h0,_state1_imanb_T,io_inb_bits[22:0],3'h0}; // @[Cat.scala 31:58]
-  wire  state1_adda_invert = state1_signa != state1_signb; // @[FAdd.scala 143:25]
-  wire [7:0] state1_adda_shift = state1_iexpa - state1_iexpb; // @[FAdd.scala 144:24]
-  wire [56:0] _state1_adda_mask_T_2 = 57'h3ffffff << state1_adda_shift[4:0]; // @[FAdd.scala 146:38]
-  wire [25:0] state1_adda_mask = ~_state1_adda_mask_T_2[25:0]; // @[FAdd.scala 146:19]
-  wire [28:0] _GEN_28 = {{3'd0}, state1_adda_mask}; // @[FAdd.scala 147:25]
-  wire [28:0] _state1_adda_sticky_T = _GEN_28 & state1_adda_cman_b; // @[FAdd.scala 147:25]
-  wire  state1_adda_sticky = _state1_adda_sticky_T != 29'h0; // @[FAdd.scala 147:35]
-  wire [28:0] _state1_adda_shift_b_T_2 = state1_adda_cman_b >> state1_adda_shift[4:0]; // @[FAdd.scala 148:54]
-  wire [28:0] _GEN_29 = {{28'd0}, state1_adda_sticky}; // @[FAdd.scala 148:68]
-  wire [28:0] _state1_adda_shift_b_T_3 = _state1_adda_shift_b_T_2 | _GEN_29; // @[FAdd.scala 148:68]
-  wire [28:0] state1_adda_shift_b = state1_adda_shift >= 8'h1a ? 29'h1 : _state1_adda_shift_b_T_3; // @[FAdd.scala 148:22]
-  wire [28:0] _state1_adda_shift_i_T_1 = 29'h0 - state1_adda_shift_b; // @[FAdd.scala 149:31]
-  wire [28:0] state1_adda_shift_i = state1_adda_invert ? _state1_adda_shift_i_T_1 : state1_adda_shift_b; // @[FAdd.scala 149:22]
-  wire [28:0] state1_adda = state1_adda_cman_a + state1_adda_shift_i; // @[FAdd.scala 151:21]
-  wire  state1_addb_invert = state1_signb != state1_signa; // @[FAdd.scala 143:25]
-  wire [7:0] state1_addb_shift = state1_iexpb - state1_iexpa; // @[FAdd.scala 144:24]
-  wire [56:0] _state1_addb_mask_T_2 = 57'h3ffffff << state1_addb_shift[4:0]; // @[FAdd.scala 146:38]
-  wire [25:0] state1_addb_mask = ~_state1_addb_mask_T_2[25:0]; // @[FAdd.scala 146:19]
-  wire [28:0] _GEN_30 = {{3'd0}, state1_addb_mask}; // @[FAdd.scala 147:25]
-  wire [28:0] _state1_addb_sticky_T = _GEN_30 & state1_adda_cman_a; // @[FAdd.scala 147:25]
-  wire  state1_addb_sticky = _state1_addb_sticky_T != 29'h0; // @[FAdd.scala 147:35]
-  wire [28:0] _state1_addb_shift_b_T_2 = state1_adda_cman_a >> state1_addb_shift[4:0]; // @[FAdd.scala 148:54]
-  wire [28:0] _GEN_31 = {{28'd0}, state1_addb_sticky}; // @[FAdd.scala 148:68]
-  wire [28:0] _state1_addb_shift_b_T_3 = _state1_addb_shift_b_T_2 | _GEN_31; // @[FAdd.scala 148:68]
-  wire [28:0] state1_addb_shift_b = state1_addb_shift >= 8'h1a ? 29'h1 : _state1_addb_shift_b_T_3; // @[FAdd.scala 148:22]
-  wire [28:0] _state1_addb_shift_i_T_1 = 29'h0 - state1_addb_shift_b; // @[FAdd.scala 149:31]
-  wire [28:0] state1_addb_shift_i = state1_addb_invert ? _state1_addb_shift_i_T_1 : state1_addb_shift_b; // @[FAdd.scala 149:22]
-  wire [28:0] state1_addb = state1_adda_cman_b + state1_addb_shift_i; // @[FAdd.scala 151:21]
-  wire  _state1_select0_T = state1_nana | state1_nanb; // @[FAdd.scala 112:28]
-  wire  _state1_select0_T_3 = io_ina_bits[30:0] >= io_inb_bits[30:0]; // @[FAdd.scala 113:38]
-  wire  state1_select0 = state1_nana | state1_nanb ? state1_nana : _state1_select0_T_3; // @[FAdd.scala 112:22]
-  wire [22:0] _state1_state1_man_T = state1_select0 ? io_ina_bits[22:0] : io_inb_bits[22:0]; // @[FAdd.scala 119:24]
-  wire  state1_state1_zeroa = state1_select0 ? state1_zeroa : state1_zerob; // @[FAdd.scala 121:24]
-  wire  state1_state1_zerob = state1_select0 ? state1_zerob : state1_zeroa; // @[FAdd.scala 122:24]
-  wire [23:0] state1_state1_man = {{1'd0}, _state1_state1_man_T}; // @[FAdd.scala 119:18 86:22]
-  wire [28:0] _state2_man_i_T_3 = 29'h0 - state1__add; // @[FAdd.scala 201:38]
-  wire [28:0] state2_man_i = state1__add[28] ? _state2_man_i_T_3 : state1__add; // @[FAdd.scala 201:20]
-  wire [15:0] _GEN_32 = {{8'd0}, state2_man_i[15:8]}; // @[Bitwise.scala 105:31]
-  wire [15:0] _state2_clz_T_5 = _GEN_32 & 16'hff; // @[Bitwise.scala 105:31]
-  wire [15:0] _state2_clz_T_7 = {state2_man_i[7:0], 8'h0}; // @[Bitwise.scala 105:70]
-  wire [15:0] _state2_clz_T_9 = _state2_clz_T_7 & 16'hff00; // @[Bitwise.scala 105:80]
-  wire [15:0] _state2_clz_T_10 = _state2_clz_T_5 | _state2_clz_T_9; // @[Bitwise.scala 105:39]
-  wire [15:0] _GEN_33 = {{4'd0}, _state2_clz_T_10[15:4]}; // @[Bitwise.scala 105:31]
-  wire [15:0] _state2_clz_T_15 = _GEN_33 & 16'hf0f; // @[Bitwise.scala 105:31]
-  wire [15:0] _state2_clz_T_17 = {_state2_clz_T_10[11:0], 4'h0}; // @[Bitwise.scala 105:70]
-  wire [15:0] _state2_clz_T_19 = _state2_clz_T_17 & 16'hf0f0; // @[Bitwise.scala 105:80]
-  wire [15:0] _state2_clz_T_20 = _state2_clz_T_15 | _state2_clz_T_19; // @[Bitwise.scala 105:39]
-  wire [15:0] _GEN_34 = {{2'd0}, _state2_clz_T_20[15:2]}; // @[Bitwise.scala 105:31]
-  wire [15:0] _state2_clz_T_25 = _GEN_34 & 16'h3333; // @[Bitwise.scala 105:31]
-  wire [15:0] _state2_clz_T_27 = {_state2_clz_T_20[13:0], 2'h0}; // @[Bitwise.scala 105:70]
-  wire [15:0] _state2_clz_T_29 = _state2_clz_T_27 & 16'hcccc; // @[Bitwise.scala 105:80]
-  wire [15:0] _state2_clz_T_30 = _state2_clz_T_25 | _state2_clz_T_29; // @[Bitwise.scala 105:39]
-  wire [15:0] _GEN_35 = {{1'd0}, _state2_clz_T_30[15:1]}; // @[Bitwise.scala 105:31]
-  wire [15:0] _state2_clz_T_35 = _GEN_35 & 16'h5555; // @[Bitwise.scala 105:31]
-  wire [15:0] _state2_clz_T_37 = {_state2_clz_T_30[14:0], 1'h0}; // @[Bitwise.scala 105:70]
-  wire [15:0] _state2_clz_T_39 = _state2_clz_T_37 & 16'haaaa; // @[Bitwise.scala 105:80]
-  wire [15:0] _state2_clz_T_40 = _state2_clz_T_35 | _state2_clz_T_39; // @[Bitwise.scala 105:39]
-  wire [7:0] _GEN_36 = {{4'd0}, state2_man_i[23:20]}; // @[Bitwise.scala 105:31]
-  wire [7:0] _state2_clz_T_46 = _GEN_36 & 8'hf; // @[Bitwise.scala 105:31]
-  wire [7:0] _state2_clz_T_48 = {state2_man_i[19:16], 4'h0}; // @[Bitwise.scala 105:70]
-  wire [7:0] _state2_clz_T_50 = _state2_clz_T_48 & 8'hf0; // @[Bitwise.scala 105:80]
-  wire [7:0] _state2_clz_T_51 = _state2_clz_T_46 | _state2_clz_T_50; // @[Bitwise.scala 105:39]
-  wire [7:0] _GEN_37 = {{2'd0}, _state2_clz_T_51[7:2]}; // @[Bitwise.scala 105:31]
-  wire [7:0] _state2_clz_T_56 = _GEN_37 & 8'h33; // @[Bitwise.scala 105:31]
-  wire [7:0] _state2_clz_T_58 = {_state2_clz_T_51[5:0], 2'h0}; // @[Bitwise.scala 105:70]
-  wire [7:0] _state2_clz_T_60 = _state2_clz_T_58 & 8'hcc; // @[Bitwise.scala 105:80]
-  wire [7:0] _state2_clz_T_61 = _state2_clz_T_56 | _state2_clz_T_60; // @[Bitwise.scala 105:39]
-  wire [7:0] _GEN_38 = {{1'd0}, _state2_clz_T_61[7:1]}; // @[Bitwise.scala 105:31]
-  wire [7:0] _state2_clz_T_66 = _GEN_38 & 8'h55; // @[Bitwise.scala 105:31]
-  wire [7:0] _state2_clz_T_68 = {_state2_clz_T_61[6:0], 1'h0}; // @[Bitwise.scala 105:70]
-  wire [7:0] _state2_clz_T_70 = _state2_clz_T_68 & 8'haa; // @[Bitwise.scala 105:80]
-  wire [7:0] _state2_clz_T_71 = _state2_clz_T_66 | _state2_clz_T_70; // @[Bitwise.scala 105:39]
-  wire [26:0] _state2_clz_T_80 = {_state2_clz_T_40,_state2_clz_T_71,state2_man_i[24],state2_man_i[25],state2_man_i[26]}; // @[Cat.scala 31:58]
-  wire [4:0] _state2_clz_T_108 = _state2_clz_T_80[25] ? 5'h19 : 5'h1a; // @[Mux.scala 47:70]
-  wire [4:0] _state2_clz_T_109 = _state2_clz_T_80[24] ? 5'h18 : _state2_clz_T_108; // @[Mux.scala 47:70]
-  wire [4:0] _state2_clz_T_110 = _state2_clz_T_80[23] ? 5'h17 : _state2_clz_T_109; // @[Mux.scala 47:70]
-  wire [4:0] _state2_clz_T_111 = _state2_clz_T_80[22] ? 5'h16 : _state2_clz_T_110; // @[Mux.scala 47:70]
-  wire [4:0] _state2_clz_T_112 = _state2_clz_T_80[21] ? 5'h15 : _state2_clz_T_111; // @[Mux.scala 47:70]
-  wire [4:0] _state2_clz_T_113 = _state2_clz_T_80[20] ? 5'h14 : _state2_clz_T_112; // @[Mux.scala 47:70]
-  wire [4:0] _state2_clz_T_114 = _state2_clz_T_80[19] ? 5'h13 : _state2_clz_T_113; // @[Mux.scala 47:70]
-  wire [4:0] _state2_clz_T_115 = _state2_clz_T_80[18] ? 5'h12 : _state2_clz_T_114; // @[Mux.scala 47:70]
-  wire [4:0] _state2_clz_T_116 = _state2_clz_T_80[17] ? 5'h11 : _state2_clz_T_115; // @[Mux.scala 47:70]
-  wire [4:0] _state2_clz_T_117 = _state2_clz_T_80[16] ? 5'h10 : _state2_clz_T_116; // @[Mux.scala 47:70]
-  wire [4:0] _state2_clz_T_118 = _state2_clz_T_80[15] ? 5'hf : _state2_clz_T_117; // @[Mux.scala 47:70]
-  wire [4:0] _state2_clz_T_119 = _state2_clz_T_80[14] ? 5'he : _state2_clz_T_118; // @[Mux.scala 47:70]
-  wire [4:0] _state2_clz_T_120 = _state2_clz_T_80[13] ? 5'hd : _state2_clz_T_119; // @[Mux.scala 47:70]
-  wire [4:0] _state2_clz_T_121 = _state2_clz_T_80[12] ? 5'hc : _state2_clz_T_120; // @[Mux.scala 47:70]
-  wire [4:0] _state2_clz_T_122 = _state2_clz_T_80[11] ? 5'hb : _state2_clz_T_121; // @[Mux.scala 47:70]
-  wire [4:0] _state2_clz_T_123 = _state2_clz_T_80[10] ? 5'ha : _state2_clz_T_122; // @[Mux.scala 47:70]
-  wire [4:0] _state2_clz_T_124 = _state2_clz_T_80[9] ? 5'h9 : _state2_clz_T_123; // @[Mux.scala 47:70]
-  wire [4:0] _state2_clz_T_125 = _state2_clz_T_80[8] ? 5'h8 : _state2_clz_T_124; // @[Mux.scala 47:70]
-  wire [4:0] _state2_clz_T_126 = _state2_clz_T_80[7] ? 5'h7 : _state2_clz_T_125; // @[Mux.scala 47:70]
-  wire [4:0] _state2_clz_T_127 = _state2_clz_T_80[6] ? 5'h6 : _state2_clz_T_126; // @[Mux.scala 47:70]
-  wire [4:0] _state2_clz_T_128 = _state2_clz_T_80[5] ? 5'h5 : _state2_clz_T_127; // @[Mux.scala 47:70]
-  wire [4:0] _state2_clz_T_129 = _state2_clz_T_80[4] ? 5'h4 : _state2_clz_T_128; // @[Mux.scala 47:70]
-  wire [4:0] _state2_clz_T_130 = _state2_clz_T_80[3] ? 5'h3 : _state2_clz_T_129; // @[Mux.scala 47:70]
-  wire [4:0] _state2_clz_T_131 = _state2_clz_T_80[2] ? 5'h2 : _state2_clz_T_130; // @[Mux.scala 47:70]
-  wire [4:0] _state2_clz_T_132 = _state2_clz_T_80[1] ? 5'h1 : _state2_clz_T_131; // @[Mux.scala 47:70]
-  wire [4:0] state2_clz = _state2_clz_T_80[0] ? 5'h0 : _state2_clz_T_132; // @[Mux.scala 47:70]
-  wire [7:0] _GEN_39 = {{3'd0}, state2_clz}; // @[FAdd.scala 205:22]
-  wire  state2_denorm = _GEN_39 >= state1__exp; // @[FAdd.scala 205:22]
-  wire [7:0] _state2_shift_T_2 = state1__exp - 8'h1; // @[FAdd.scala 206:43]
-  wire [7:0] _state2_shift_T_3 = state1__exp > 8'h0 ? _state2_shift_T_2 : 8'h0; // @[FAdd.scala 206:32]
-  wire [7:0] state2_shift = state2_denorm ? _state2_shift_T_3 : {{3'd0}, state2_clz}; // @[FAdd.scala 206:20]
-  wire [59:0] _GEN_0 = {{31'd0}, state2_man_i}; // @[FAdd.scala 208:24]
-  wire [59:0] _state2_man_s_T_1 = _GEN_0 << state2_shift[4:0]; // @[FAdd.scala 208:24]
-  wire [26:0] state2_man_s = _state2_man_s_T_1[26:0]; // @[FAdd.scala 208:38]
-  wire [7:0] _state2_exp_l_T_2 = state1__exp - state2_shift; // @[FAdd.scala 209:44]
-  wire [7:0] state2_exp_l = state2_denorm ? {{7'd0}, state2_man_s[26]} : _state2_exp_l_T_2; // @[FAdd.scala 209:20]
-  wire  state2_norm = state2_man_i[27]; // @[FAdd.scala 213:22]
-  wire [7:0] _state2_exp_r_T_1 = state1__exp + 8'h1; // @[FAdd.scala 214:28]
-  wire [7:0] state2_exp_r = state2_norm ? _state2_exp_r_T_1 : state1__exp; // @[FAdd.scala 214:20]
-  wire [26:0] _GEN_40 = {{26'd0}, state2_man_i[0]}; // @[FAdd.scala 215:42]
-  wire [26:0] _state2_man_r_T_2 = state2_man_i[27:1] | _GEN_40; // @[FAdd.scala 215:42]
-  wire [26:0] state2_man_r = state2_norm ? _state2_man_r_T_2 : state2_man_i[26:0]; // @[FAdd.scala 215:20]
-  wire  state2_select = state2_man_i[27:26] == 2'h0 | state1__exp == 8'h0; // @[FAdd.scala 218:46]
-  wire [7:0] state2_exp_t = state2_select ? state2_exp_l : state2_exp_r; // @[FAdd.scala 219:20]
-  wire [26:0] state2_man_t = state2_select ? state2_man_s : state2_man_r; // @[FAdd.scala 220:20]
-  wire  _state2_man_d_round_T_1 = state2_man_t[2:0] != 3'h0; // @[FBase.scala 82:30]
-  wire  _state2_man_d_round_T_2 = state2_man_t[2:0] != 3'h0 & state1__signa; // @[FBase.scala 82:38]
-  wire  _state2_man_d_round_T_6 = _state2_man_d_round_T_1 & ~state1__signa; // @[FBase.scala 83:38]
-  wire  _state2_man_d_round_T_11 = state2_man_t[2:0] > 3'h4 | state2_man_t[3:0] == 4'hc; // @[FBase.scala 85:36]
-  wire [3:0] state2_man_d_round = {_state2_man_d_round_T_2,_state2_man_d_round_T_6,1'h0,_state2_man_d_round_T_11}; // @[Cat.scala 31:58]
-  wire [24:0] _state2_man_d_T_5 = state2_man_t[26:3] + 24'h1; // @[FAdd.scala 224:35]
-  wire [24:0] state2_man_d = state2_man_d_round[0] ? _state2_man_d_T_5 : {{1'd0}, state2_man_t[26:3]}; // @[FAdd.scala 223:20]
-  wire [7:0] _state2_exp_d_T_2 = state2_exp_t + 8'h1; // @[FAdd.scala 225:40]
-  wire [7:0] state2_exp_d = state2_man_d[24] ? _state2_exp_d_T_2 : state2_exp_t; // @[FAdd.scala 225:20]
-  wire  state2_is_inf = state2_exp_t == 8'hff; // @[FAdd.scala 228:24]
-  wire [7:0] state2_nexp = state2_is_inf ? 8'hff : state2_exp_d; // @[FAdd.scala 229:20]
-  wire [22:0] state2_nman = state2_is_inf ? 23'h0 : state2_man_d[22:0]; // @[FAdd.scala 230:20]
-  wire  state2_nzero = state1__add == 29'h0; // @[FAdd.scala 163:29]
-  wire [7:0] _GEN_13 = state1__zeroa | state2_nzero ? 8'h0 : state1__exp; // @[FAdd.scala 180:36 181:20 184:20]
-  wire [23:0] _GEN_14 = state1__zeroa | state2_nzero ? 24'h0 : state1__man; // @[FAdd.scala 180:36 182:20 185:20]
-  wire [7:0] _GEN_15 = state1__zerob | state2_nzero ? _GEN_13 : state2_nexp; // @[FAdd.scala 179:41 188:18]
-  wire [23:0] _GEN_16 = state1__zerob | state2_nzero ? _GEN_14 : {{1'd0}, state2_nman}; // @[FAdd.scala 179:41 189:18]
-  wire [23:0] _GEN_18 = state1__infa | state1__infb ? 24'h0 : _GEN_16; // @[FAdd.scala 176:46 178:18]
-  wire [23:0] _GEN_21 = state1__infa & state1__infb & state1__signa != state1__signb ? 24'h400000 : _GEN_18; // @[FAdd.scala 172:79 175:18]
-  wire [23:0] _GEN_24 = state1__nan ? state1__man : _GEN_21; // @[FAdd.scala 168:23 171:18]
-  wire [22:0] state2_state2_man = _GEN_24[22:0]; // @[FAdd.scala 165:22]
-  wire [8:0] io_out_bits_hi = {state2_sign,state2_exp}; // @[Cat.scala 31:58]
-  assign io_ina_ready = 1'h1; // @[FAdd.scala 45:32]
-  assign io_inb_ready = io_ina_valid; // @[FAdd.scala 46:32]
-  assign io_out_valid = active2; // @[FAdd.scala 47:16]
-  assign io_out_bits = {io_out_bits_hi,state2_man}; // @[Cat.scala 31:58]
-  always @(posedge clock) begin
-    if (update1) begin // @[FAdd.scala 36:18]
-      if (state1_select0) begin // @[FAdd.scala 116:24]
-        state1__signa <= state1_signa;
-      end else begin
-        state1__signa <= state1_signb;
-      end
-    end
-    if (update1) begin // @[FAdd.scala 36:18]
-      if (state1_select0) begin // @[FAdd.scala 117:24]
-        state1__signb <= state1_signb;
-      end else begin
-        state1__signb <= state1_signa;
-      end
-    end
-    if (update1) begin // @[FAdd.scala 36:18]
-      if (state1_select0) begin // @[FAdd.scala 118:24]
-        state1__exp <= io_ina_bits[30:23];
-      end else begin
-        state1__exp <= io_inb_bits[30:23];
-      end
-    end
-    if (update1) begin // @[FAdd.scala 36:18]
-      state1__man <= state1_state1_man; // @[FAdd.scala 37:12]
-    end
-    if (update1) begin // @[FAdd.scala 36:18]
-      if (state1_select0) begin // @[FAdd.scala 120:24]
-        state1__add <= state1_adda;
-      end else begin
-        state1__add <= state1_addb;
-      end
-    end
-    if (update1) begin // @[FAdd.scala 36:18]
-      if (state1_select0) begin // @[FAdd.scala 121:24]
-        state1__zeroa <= state1_zeroa;
-      end else begin
-        state1__zeroa <= state1_zerob;
-      end
-    end
-    if (update1) begin // @[FAdd.scala 36:18]
-      if (state1_select0) begin // @[FAdd.scala 122:24]
-        state1__zerob <= state1_zerob;
-      end else begin
-        state1__zerob <= state1_zeroa;
-      end
-    end
-    if (update1) begin // @[FAdd.scala 36:18]
-      state1__infa <= state1_infa; // @[FAdd.scala 37:12]
-    end
-    if (update1) begin // @[FAdd.scala 36:18]
-      state1__infb <= state1_infb; // @[FAdd.scala 37:12]
-    end
-    if (update1) begin // @[FAdd.scala 36:18]
-      state1__nan <= _state1_select0_T; // @[FAdd.scala 37:12]
-    end
-    if (active1) begin // @[FAdd.scala 40:18]
-      if (state1__nan) begin // @[FAdd.scala 168:23]
-        state2_sign <= 1'h0; // @[FAdd.scala 169:19]
-      end else if (state1__infa & state1__infb & state1__signa != state1__signb) begin // @[FAdd.scala 172:79]
-        state2_sign <= 1'h0; // @[FAdd.scala 173:19]
-      end else if (state2_nzero) begin // @[FAdd.scala 167:23]
-        state2_sign <= 1'h0;
-      end else begin
-        state2_sign <= state1__signa;
-      end
-    end
-    if (active1) begin // @[FAdd.scala 40:18]
-      if (state1__nan) begin // @[FAdd.scala 168:23]
-        state2_exp <= state1__exp; // @[FAdd.scala 170:18]
-      end else if (state1__infa & state1__infb & state1__signa != state1__signb) begin // @[FAdd.scala 172:79]
-        state2_exp <= 8'hff; // @[FAdd.scala 174:18]
-      end else if (state1__infa | state1__infb) begin // @[FAdd.scala 176:46]
-        state2_exp <= 8'hff; // @[FAdd.scala 177:18]
-      end else begin
-        state2_exp <= _GEN_15;
-      end
-    end
-    if (active1) begin // @[FAdd.scala 40:18]
-      state2_man <= state2_state2_man; // @[FAdd.scala 41:12]
-    end
-    `ifndef SYNTHESIS
-    `ifdef STOP_COND
-      if (`STOP_COND) begin
-    `endif
-        if (update1 & ~reset & ~(~(state1_state1_zeroa & ~state1_state1_zerob))) begin
-          $fatal; // @[FAdd.scala 127:11]
-        end
-    `ifdef STOP_COND
-      end
-    `endif
-    `endif // SYNTHESIS
-    `ifndef SYNTHESIS
-    `ifdef PRINTF_COND
-      if (`PRINTF_COND) begin
-    `endif
-        if (update1 & ~reset & ~(~(state1_state1_zeroa & ~state1_state1_zerob))) begin
-          $fwrite(32'h80000002,"Assertion failed\n    at FAdd.scala:127 assert(!(state1.zeroa && !state1.zerob))\n"); // @[FAdd.scala 127:11]
-        end
-    `ifdef PRINTF_COND
-      end
-    `endif
-    `endif // SYNTHESIS
-  end
-  always @(posedge clock or posedge reset) begin
-    if (reset) begin // @[FAdd.scala 25:62]
-      active1 <= 1'h0;
-    end else begin
-      active1 <= io_ina_valid & io_ina_ready & io_inb_ready;
-    end
-  end
-  always @(posedge clock or posedge reset) begin
-    if (reset) begin // @[FAdd.scala 32:34]
-      active2 <= 1'h0; // @[FAdd.scala 33:13]
-    end else begin
-      active2 <= active1; // @[FAdd.scala 21:24]
-    end
-  end
-// Register and memory initialization
-`ifdef RANDOMIZE_GARBAGE_ASSIGN
-`define RANDOMIZE
-`endif
-`ifdef RANDOMIZE_INVALID_ASSIGN
-`define RANDOMIZE
-`endif
-`ifdef RANDOMIZE_REG_INIT
-`define RANDOMIZE
-`endif
-`ifdef RANDOMIZE_MEM_INIT
-`define RANDOMIZE
-`endif
-`ifndef RANDOM
-`define RANDOM $random
-`endif
-`ifdef RANDOMIZE_MEM_INIT
-  integer initvar;
-`endif
-`ifndef SYNTHESIS
-`ifdef FIRRTL_BEFORE_INITIAL
-`FIRRTL_BEFORE_INITIAL
-`endif
-initial begin
-  `ifdef RANDOMIZE
-    `ifdef INIT_RANDOM
-      `INIT_RANDOM
-    `endif
-    `ifndef VERILATOR
-      `ifdef RANDOMIZE_DELAY
-        #`RANDOMIZE_DELAY begin end
-      `else
-        #0.002 begin end
-      `endif
-    `endif
-`ifdef RANDOMIZE_REG_INIT
-  _RAND_0 = {1{`RANDOM}};
-  active1 = _RAND_0[0:0];
-  _RAND_1 = {1{`RANDOM}};
-  active2 = _RAND_1[0:0];
-  _RAND_2 = {1{`RANDOM}};
-  state1__signa = _RAND_2[0:0];
-  _RAND_3 = {1{`RANDOM}};
-  state1__signb = _RAND_3[0:0];
-  _RAND_4 = {1{`RANDOM}};
-  state1__exp = _RAND_4[7:0];
-  _RAND_5 = {1{`RANDOM}};
-  state1__man = _RAND_5[23:0];
-  _RAND_6 = {1{`RANDOM}};
-  state1__add = _RAND_6[28:0];
-  _RAND_7 = {1{`RANDOM}};
-  state1__zeroa = _RAND_7[0:0];
-  _RAND_8 = {1{`RANDOM}};
-  state1__zerob = _RAND_8[0:0];
-  _RAND_9 = {1{`RANDOM}};
-  state1__infa = _RAND_9[0:0];
-  _RAND_10 = {1{`RANDOM}};
-  state1__infb = _RAND_10[0:0];
-  _RAND_11 = {1{`RANDOM}};
-  state1__nan = _RAND_11[0:0];
-  _RAND_12 = {1{`RANDOM}};
-  state2_sign = _RAND_12[0:0];
-  _RAND_13 = {1{`RANDOM}};
-  state2_exp = _RAND_13[7:0];
-  _RAND_14 = {1{`RANDOM}};
-  state2_man = _RAND_14[22:0];
-`endif // RANDOMIZE_REG_INIT
-  if (reset) begin
-    active1 = 1'h0;
-  end
-  if (reset) begin
-    active2 = 1'h0;
-  end
-  `endif // RANDOMIZE
-end // initial
-`ifdef FIRRTL_AFTER_INITIAL
-`FIRRTL_AFTER_INITIAL
-`endif
-`endif // SYNTHESIS
-endmodule
-module Fifo(
-  input        clock,
-  input        reset,
-  output       io_in_ready,
-  input        io_in_valid,
-  input  [4:0] io_in_bits,
-  input        io_out_ready,
-  output       io_out_valid,
-  output [4:0] io_out_bits
-);
-`ifdef RANDOMIZE_GARBAGE_ASSIGN
-  reg [31:0] _RAND_1;
-`endif // RANDOMIZE_GARBAGE_ASSIGN
-`ifdef RANDOMIZE_MEM_INIT
-  reg [31:0] _RAND_0;
-`endif // RANDOMIZE_MEM_INIT
-`ifdef RANDOMIZE_REG_INIT
-  reg [31:0] _RAND_2;
-  reg [31:0] _RAND_3;
-  reg [31:0] _RAND_4;
-  reg [31:0] _RAND_5;
-  reg [31:0] _RAND_6;
-  reg [31:0] _RAND_7;
-`endif // RANDOMIZE_REG_INIT
-  reg [4:0] mem [0:2]; // @[Fifo.scala 22:16]
-  wire  mem_rdata_MPORT_en; // @[Fifo.scala 22:16]
-  wire [1:0] mem_rdata_MPORT_addr; // @[Fifo.scala 22:16]
-  wire [4:0] mem_rdata_MPORT_data; // @[Fifo.scala 22:16]
-  wire [4:0] mem_MPORT_data; // @[Fifo.scala 22:16]
-  wire [1:0] mem_MPORT_addr; // @[Fifo.scala 22:16]
-  wire  mem_MPORT_mask; // @[Fifo.scala 22:16]
-  wire  mem_MPORT_en; // @[Fifo.scala 22:16]
-  reg [4:0] rdata; // @[Fifo.scala 23:18]
-  reg  rvalid; // @[Fifo.scala 25:23]
-  reg  wready; // @[Fifo.scala 26:23]
-  reg [1:0] raddr; // @[Fifo.scala 27:22]
-  reg [1:0] waddr; // @[Fifo.scala 28:22]
-  reg [2:0] count; // @[Fifo.scala 29:22]
-  wire  winc = io_in_valid & io_in_ready; // @[Fifo.scala 33:26]
-  wire  rinc = (~rvalid | io_out_ready) & (winc | count > 3'h1); // @[Fifo.scala 34:40]
-  wire [1:0] _waddr_T_2 = waddr + 2'h1; // @[Fifo.scala 37:50]
-  wire [1:0] _raddr_T_2 = raddr + 2'h1; // @[Fifo.scala 41:50]
-  wire  forward = rinc & winc & count <= 3'h1; // @[Fifo.scala 44:30]
-  wire  oen = io_out_valid & io_out_ready; // @[Fifo.scala 49:26]
-  wire  _T_1 = winc & ~oen; // @[Fifo.scala 51:13]
-  wire [2:0] _count_T_1 = count + 3'h1; // @[Fifo.scala 52:20]
-  wire  _T_2 = ~winc; // @[Fifo.scala 53:16]
-  wire [2:0] _count_T_3 = count - 3'h1; // @[Fifo.scala 54:20]
-  wire  _GEN_4 = io_out_ready & count == 3'h1 ? 1'h0 : rvalid; // @[Fifo.scala 59:47 60:12 25:23]
-  wire  _wready_T_5 = count == 3'h3 & ~_T_1; // @[Fifo.scala 64:33]
-  wire  _wready_T_6 = count < 3'h3 | _wready_T_5; // @[Fifo.scala 63:31]
-  wire  _wready_T_8 = oen & _T_2; // @[Fifo.scala 65:18]
-  wire  _T_6 = ~forward; // @[Fifo.scala 69:17]
-  assign mem_rdata_MPORT_en = forward ? 1'h0 : rinc;
-  assign mem_rdata_MPORT_addr = raddr;
-  `ifndef RANDOMIZE_GARBAGE_ASSIGN
-  assign mem_rdata_MPORT_data = mem[mem_rdata_MPORT_addr]; // @[Fifo.scala 22:16]
-  `else
-  assign mem_rdata_MPORT_data = mem_rdata_MPORT_addr >= 2'h3 ? _RAND_1[4:0] : mem[mem_rdata_MPORT_addr]; // @[Fifo.scala 22:16]
-  `endif // RANDOMIZE_GARBAGE_ASSIGN
-  assign mem_MPORT_data = io_in_bits;
-  assign mem_MPORT_addr = waddr;
-  assign mem_MPORT_mask = 1'h1;
-  assign mem_MPORT_en = winc & _T_6;
-  assign io_in_ready = wready | io_out_ready; // @[Fifo.scala 85:27]
-  assign io_out_valid = rvalid; // @[Fifo.scala 81:16]
-  assign io_out_bits = rdata; // @[Fifo.scala 82:15]
-  always @(posedge clock) begin
-    if (mem_MPORT_en & mem_MPORT_mask) begin
-      mem[mem_MPORT_addr] <= mem_MPORT_data; // @[Fifo.scala 22:16]
-    end
-    if (forward) begin // @[Fifo.scala 73:18]
-      rdata <= io_in_bits; // @[Fifo.scala 74:11]
-    end else if (rinc) begin // @[Fifo.scala 75:22]
-      rdata <= mem_rdata_MPORT_data; // @[Fifo.scala 76:11]
-    end
-    `ifndef SYNTHESIS
-    `ifdef STOP_COND
-      if (`STOP_COND) begin
-    `endif
-        if (~reset & ~(count <= 3'h4)) begin
-          $fatal; // @[Fifo.scala 92:9]
-        end
-    `ifdef STOP_COND
-      end
-    `endif
-    `endif // SYNTHESIS
-    `ifndef SYNTHESIS
-    `ifdef PRINTF_COND
-      if (`PRINTF_COND) begin
-    `endif
-        if (~reset & ~(count <= 3'h4)) begin
-          $fwrite(32'h80000002,"Assertion failed\n    at Fifo.scala:92 assert(count <= n.U)\n"); // @[Fifo.scala 92:9]
-        end
-    `ifdef PRINTF_COND
-      end
-    `endif
-    `endif // SYNTHESIS
-  end
-  always @(posedge clock or posedge reset) begin
-    if (reset) begin // @[Fifo.scala 57:14]
-      rvalid <= 1'h0; // @[Fifo.scala 58:12]
-    end else begin
-      rvalid <= winc | _GEN_4;
-    end
-  end
-  always @(posedge clock or posedge reset) begin
-    if (reset) begin // @[Fifo.scala 64:51]
-      wready <= 1'h0;
-    end else begin
-      wready <= _wready_T_6 | _wready_T_8;
-    end
-  end
-  always @(posedge clock or posedge reset) begin
-    if (reset) begin // @[Fifo.scala 40:15]
-      raddr <= 2'h0; // @[Fifo.scala 41:17]
-    end else if (rinc) begin // @[Fifo.scala 27:22]
-      if (raddr == 2'h2) begin
-        raddr <= 2'h0;
-      end else begin
-        raddr <= _raddr_T_2;
-      end
-    end
-  end
-  always @(posedge clock or posedge reset) begin
-    if (reset) begin // @[Fifo.scala 36:15]
-      waddr <= 2'h0; // @[Fifo.scala 37:17]
-    end else if (winc) begin // @[Fifo.scala 28:22]
-      if (waddr == 2'h2) begin
-        waddr <= 2'h0;
-      end else begin
-        waddr <= _waddr_T_2;
-      end
-    end
-  end
-  always @(posedge clock or posedge reset) begin
-    if (reset) begin // @[Fifo.scala 51:22]
-      count <= 3'h0; // @[Fifo.scala 52:11]
-    end else if (winc & ~oen) begin // @[Fifo.scala 53:29]
-      count <= _count_T_1; // @[Fifo.scala 54:11]
-    end else if (~winc & oen) begin // @[Fifo.scala 29:22]
-      count <= _count_T_3;
-    end
-  end
-// Register and memory initialization
-`ifdef RANDOMIZE_GARBAGE_ASSIGN
-`define RANDOMIZE
-`endif
-`ifdef RANDOMIZE_INVALID_ASSIGN
-`define RANDOMIZE
-`endif
-`ifdef RANDOMIZE_REG_INIT
-`define RANDOMIZE
-`endif
-`ifdef RANDOMIZE_MEM_INIT
-`define RANDOMIZE
-`endif
-`ifndef RANDOM
-`define RANDOM $random
-`endif
-`ifdef RANDOMIZE_MEM_INIT
-  integer initvar;
-`endif
-`ifndef SYNTHESIS
-`ifdef FIRRTL_BEFORE_INITIAL
-`FIRRTL_BEFORE_INITIAL
-`endif
-initial begin
-  `ifdef RANDOMIZE
-    `ifdef INIT_RANDOM
-      `INIT_RANDOM
-    `endif
-    `ifndef VERILATOR
-      `ifdef RANDOMIZE_DELAY
-        #`RANDOMIZE_DELAY begin end
-      `else
-        #0.002 begin end
-      `endif
-    `endif
-`ifdef RANDOMIZE_GARBAGE_ASSIGN
-  _RAND_1 = {1{`RANDOM}};
-`endif // RANDOMIZE_GARBAGE_ASSIGN
-`ifdef RANDOMIZE_MEM_INIT
-  _RAND_0 = {1{`RANDOM}};
-  for (initvar = 0; initvar < 3; initvar = initvar+1)
-    mem[initvar] = _RAND_0[4:0];
-`endif // RANDOMIZE_MEM_INIT
-`ifdef RANDOMIZE_REG_INIT
-  _RAND_2 = {1{`RANDOM}};
-  rdata = _RAND_2[4:0];
-  _RAND_3 = {1{`RANDOM}};
-  rvalid = _RAND_3[0:0];
-  _RAND_4 = {1{`RANDOM}};
-  wready = _RAND_4[0:0];
-  _RAND_5 = {1{`RANDOM}};
-  raddr = _RAND_5[1:0];
-  _RAND_6 = {1{`RANDOM}};
-  waddr = _RAND_6[1:0];
-  _RAND_7 = {1{`RANDOM}};
-  count = _RAND_7[2:0];
-`endif // RANDOMIZE_REG_INIT
-  if (reset) begin
-    rvalid = 1'h0;
-  end
-  if (reset) begin
-    wready = 1'h0;
-  end
-  if (reset) begin
-    raddr = 2'h0;
-  end
-  if (reset) begin
-    waddr = 2'h0;
-  end
-  if (reset) begin
-    count = 3'h0;
-  end
-  `endif // RANDOMIZE
-end // initial
-`ifdef FIRRTL_AFTER_INITIAL
-`FIRRTL_AFTER_INITIAL
-`endif
-`endif // SYNTHESIS
-endmodule
-module FAdd_1(
-  input         clock,
-  input         reset,
-  input         io_in_valid,
-  input  [4:0]  io_in_addr,
-  input  [31:0] io_in_fs1,
-  input  [31:0] io_in_fs2,
-  input  [26:0] io_in_op,
-  output        io_out_valid,
-  output [4:0]  io_out_addr,
-  output [31:0] io_out_fd
-);
-  wire  fadd_clock; // @[FAdd.scala 8:18]
-  wire  fadd_reset; // @[FAdd.scala 8:18]
-  wire  fadd_io_ina_ready; // @[FAdd.scala 8:18]
-  wire  fadd_io_ina_valid; // @[FAdd.scala 8:18]
-  wire [31:0] fadd_io_ina_bits; // @[FAdd.scala 8:18]
-  wire  fadd_io_inb_ready; // @[FAdd.scala 8:18]
-  wire [31:0] fadd_io_inb_bits; // @[FAdd.scala 8:18]
-  wire  fadd_io_out_valid; // @[FAdd.scala 8:18]
-  wire [31:0] fadd_io_out_bits; // @[FAdd.scala 8:18]
-  wire  ff_clock; // @[Fifo.scala 8:11]
-  wire  ff_reset; // @[Fifo.scala 8:11]
-  wire  ff_io_in_ready; // @[Fifo.scala 8:11]
-  wire  ff_io_in_valid; // @[Fifo.scala 8:11]
-  wire [4:0] ff_io_in_bits; // @[Fifo.scala 8:11]
-  wire  ff_io_out_ready; // @[Fifo.scala 8:11]
-  wire  ff_io_out_valid; // @[Fifo.scala 8:11]
-  wire [4:0] ff_io_out_bits; // @[Fifo.scala 8:11]
-  wire  _fadd_io_inb_bits_T_2 = io_in_fs2[31] ^ io_in_op[7]; // @[FAdd.scala 38:42]
-  wire  _T_4 = ~reset; // @[FAdd.scala 44:9]
-  FAdd fadd ( // @[FAdd.scala 8:18]
-    .clock(fadd_clock),
-    .reset(fadd_reset),
-    .io_ina_ready(fadd_io_ina_ready),
-    .io_ina_valid(fadd_io_ina_valid),
-    .io_ina_bits(fadd_io_ina_bits),
-    .io_inb_ready(fadd_io_inb_ready),
-    .io_inb_bits(fadd_io_inb_bits),
-    .io_out_valid(fadd_io_out_valid),
-    .io_out_bits(fadd_io_out_bits)
-  );
-  Fifo ff ( // @[Fifo.scala 8:11]
-    .clock(ff_clock),
-    .reset(ff_reset),
-    .io_in_ready(ff_io_in_ready),
-    .io_in_valid(ff_io_in_valid),
-    .io_in_bits(ff_io_in_bits),
-    .io_out_ready(ff_io_out_ready),
-    .io_out_valid(ff_io_out_valid),
-    .io_out_bits(ff_io_out_bits)
-  );
-  assign io_out_valid = fadd_io_out_valid; // @[FAdd.scala 48:16]
-  assign io_out_addr = ff_io_out_bits; // @[FAdd.scala 49:15]
-  assign io_out_fd = fadd_io_out_bits; // @[FAdd.scala 50:13]
-  assign fadd_clock = clock;
-  assign fadd_reset = reset;
-  assign fadd_io_ina_valid = io_in_valid; // @[FAdd.scala 35:21]
-  assign fadd_io_ina_bits = io_in_fs1; // @[FAdd.scala 37:21]
-  assign fadd_io_inb_bits = {_fadd_io_inb_bits_T_2,io_in_fs2[30:0]}; // @[Cat.scala 31:58]
-  assign ff_clock = clock;
-  assign ff_reset = reset;
-  assign ff_io_in_valid = io_in_valid; // @[FAdd.scala 42:18]
-  assign ff_io_in_bits = io_in_addr; // @[FAdd.scala 43:18]
-  assign ff_io_out_ready = fadd_io_out_valid; // @[FAdd.scala 45:19]
-  always @(posedge clock) begin
-    `ifndef SYNTHESIS
-    `ifdef STOP_COND
-      if (`STOP_COND) begin
-    `endif
-        if (~reset & ~(~(ff_io_in_valid & ~ff_io_in_ready))) begin
-          $fatal; // @[FAdd.scala 44:9]
-        end
-    `ifdef STOP_COND
-      end
-    `endif
-    `endif // SYNTHESIS
-    `ifndef SYNTHESIS
-    `ifdef PRINTF_COND
-      if (`PRINTF_COND) begin
-    `endif
-        if (~reset & ~(~(ff_io_in_valid & ~ff_io_in_ready))) begin
-          $fwrite(32'h80000002,"Assertion failed\n    at FAdd.scala:44 assert(!(ff.io.in.valid && !ff.io.in.ready))\n"); // @[FAdd.scala 44:9]
-        end
-    `ifdef PRINTF_COND
-      end
-    `endif
-    `endif // SYNTHESIS
-    `ifndef SYNTHESIS
-    `ifdef STOP_COND
-      if (`STOP_COND) begin
-    `endif
-        if (_T_4 & ~(~(~ff_io_out_valid & ff_io_out_ready))) begin
-          $fatal; // @[FAdd.scala 46:9]
-        end
-    `ifdef STOP_COND
-      end
-    `endif
-    `endif // SYNTHESIS
-    `ifndef SYNTHESIS
-    `ifdef PRINTF_COND
-      if (`PRINTF_COND) begin
-    `endif
-        if (_T_4 & ~(~(~ff_io_out_valid & ff_io_out_ready))) begin
-          $fwrite(32'h80000002,"Assertion failed\n    at FAdd.scala:46 assert(!(!ff.io.out.valid && ff.io.out.ready))\n"
-            ); // @[FAdd.scala 46:9]
-        end
-    `ifdef PRINTF_COND
-      end
-    `endif
-    `endif // SYNTHESIS
-  end
-endmodule
-module FMAdd(
-  input         clock,
-  input         reset,
-  input         io_op_valid,
-  input  [3:0]  io_op_bits,
-  output        io_ina_ready,
-  input         io_ina_valid,
-  input  [31:0] io_ina_bits_0,
-  output        io_inb_ready,
-  input         io_inb_valid,
-  input  [31:0] io_inb_bits_0,
-  output        io_inc_ready,
-  input         io_inc_valid,
-  input  [31:0] io_inc_bits_0,
-  output        io_out_valid,
-  output [31:0] io_out_bits_0
-);
-`ifdef RANDOMIZE_REG_INIT
-  reg [31:0] _RAND_0;
-  reg [31:0] _RAND_1;
-  reg [31:0] _RAND_2;
-  reg [31:0] _RAND_3;
-  reg [31:0] _RAND_4;
-  reg [31:0] _RAND_5;
-  reg [63:0] _RAND_6;
-  reg [31:0] _RAND_7;
-  reg [31:0] _RAND_8;
-  reg [31:0] _RAND_9;
-  reg [31:0] _RAND_10;
-  reg [31:0] _RAND_11;
-  reg [31:0] _RAND_12;
-  reg [63:0] _RAND_13;
-  reg [63:0] _RAND_14;
-  reg [31:0] _RAND_15;
-  reg [31:0] _RAND_16;
-  reg [31:0] _RAND_17;
-  reg [31:0] _RAND_18;
-  reg [31:0] _RAND_19;
-  reg [31:0] _RAND_20;
-`endif // RANDOMIZE_REG_INIT
-  reg  active1; // @[FMAdd.scala 32:24]
-  reg  active2; // @[FMAdd.scala 33:24]
-  reg  active3; // @[FMAdd.scala 34:24]
-  reg [3:0] op1; // @[FMAdd.scala 35:16]
-  reg  state1__0_sign; // @[FMAdd.scala 37:19]
-  reg [9:0] state1__0_exp; // @[FMAdd.scala 37:19]
-  reg [47:0] state1__0_mul; // @[FMAdd.scala 37:19]
-  reg  state1__0_zero; // @[FMAdd.scala 37:19]
-  reg  state1__0_inf_a; // @[FMAdd.scala 37:19]
-  reg  state1__0_inf_b; // @[FMAdd.scala 37:19]
-  reg  state1__0_nan; // @[FMAdd.scala 37:19]
-  reg  state2_0_sign; // @[FMAdd.scala 38:19]
-  reg [9:0] state2_0_exp; // @[FMAdd.scala 38:19]
-  reg [48:0] state2_0_ain; // @[FMAdd.scala 38:19]
-  reg [48:0] state2_0_bin; // @[FMAdd.scala 38:19]
-  reg  state2_0_sel; // @[FMAdd.scala 38:19]
-  reg  state2_0_add; // @[FMAdd.scala 38:19]
-  reg  state2_0_sub; // @[FMAdd.scala 38:19]
-  reg  state3_0_sign; // @[FMAdd.scala 39:19]
-  reg [7:0] state3_0_exp; // @[FMAdd.scala 39:19]
-  reg [22:0] state3_0_man; // @[FMAdd.scala 39:19]
-  wire  _update1_T_3 = ~active1; // @[FMAdd.scala 41:98]
-  wire  update1 = io_ina_valid & io_inb_valid & io_ina_ready & io_inb_ready & (io_inc_ready | ~active1); // @[FMAdd.scala 41:78]
-  wire  update2 = active1 & io_inc_valid & io_inc_ready; // @[FMAdd.scala 42:41]
-  wire  isSub = io_op_bits[2] | io_op_bits[3]; // @[FMAdd.scala 66:42]
-  wire [31:0] mul_ina = io_op_valid ? io_ina_bits_0 : 32'h0; // @[FMAdd.scala 74:22]
-  wire [31:0] mul_inb = io_op_valid ? io_inb_bits_0 : 32'h0; // @[FMAdd.scala 75:22]
-  wire  _mul_sina_T_3 = isSub ? ~mul_ina[31] : mul_ina[31]; // @[FMAdd.scala 80:29]
-  wire [31:0] mul_sina = {_mul_sina_T_3,mul_ina[30:0]}; // @[Cat.scala 31:58]
-  wire  _state1_0_zero_T_1 = mul_sina[30:0] == 31'h0; // @[FBase.scala 76:18]
-  wire  _state1_0_zero_T_3 = mul_inb[30:0] == 31'h0; // @[FBase.scala 76:18]
-  wire  state1_0_zero = _state1_0_zero_T_1 | _state1_0_zero_T_3; // @[FMAdd.scala 157:33]
-  wire  _state1_0_inf_a_T_1 = mul_sina[30:23] == 8'hff; // @[FBase.scala 64:19]
-  wire  state1_0_inf_a = mul_sina[30:23] == 8'hff & mul_sina[22:0] == 23'h0; // @[FBase.scala 64:37]
-  wire  _state1_0_inf_b_T_1 = mul_inb[30:23] == 8'hff; // @[FBase.scala 64:19]
-  wire  state1_0_inf_b = mul_inb[30:23] == 8'hff & mul_inb[22:0] == 23'h0; // @[FBase.scala 64:37]
-  wire  _state1_0_nan_a_T_3 = mul_sina[22:0] != 23'h0; // @[FBase.scala 68:50]
-  wire  state1_0_nan_a = _state1_0_inf_a_T_1 & mul_sina[22:0] != 23'h0; // @[FBase.scala 68:37]
-  wire  _state1_0_nan_b_T_3 = mul_inb[22:0] != 23'h0; // @[FBase.scala 68:50]
-  wire  state1_0_nan_b = _state1_0_inf_b_T_1 & mul_inb[22:0] != 23'h0; // @[FBase.scala 68:37]
-  wire  state1_0_subn_a = mul_sina[30:23] == 8'h0 & _state1_0_nan_a_T_3; // @[FBase.scala 72:27]
-  wire  state1_0_subn_b = mul_inb[30:23] == 8'h0 & _state1_0_nan_b_T_3; // @[FBase.scala 72:27]
-  wire  state1_0_sign_a = mul_sina[31]; // @[FBase.scala 28:14]
-  wire  state1_0_sign_b = mul_inb[31]; // @[FBase.scala 28:14]
-  wire [7:0] state1_0_iexp_a = state1_0_subn_a ? 8'h1 : mul_sina[30:23]; // @[FMAdd.scala 172:21]
-  wire [7:0] state1_0_iexp_b = state1_0_subn_b ? 8'h1 : mul_inb[30:23]; // @[FMAdd.scala 173:21]
-  wire  _state1_0_iman_a_T = state1_0_subn_a ? 1'h0 : 1'h1; // @[FMAdd.scala 174:25]
-  wire [23:0] state1_0_iman_a = {_state1_0_iman_a_T,mul_sina[22:0]}; // @[Cat.scala 31:58]
-  wire  _state1_0_iman_b_T = state1_0_subn_b ? 1'h0 : 1'h1; // @[FMAdd.scala 175:25]
-  wire [23:0] state1_0_iman_b = {_state1_0_iman_b_T,mul_inb[22:0]}; // @[Cat.scala 31:58]
-  wire [9:0] state1_0_nbias = 10'h0 - 10'h7f; // @[FMAdd.scala 205:17]
-  wire  state1_0_sign = state1_0_sign_a ^ state1_0_sign_b; // @[FMAdd.scala 207:23]
-  wire [8:0] _state1_0_exp_T = state1_0_iexp_a + state1_0_iexp_b; // @[FMAdd.scala 208:22]
-  wire [9:0] _GEN_46 = {{1'd0}, _state1_0_exp_T}; // @[FMAdd.scala 208:31]
-  wire [9:0] state1_0_exp = _GEN_46 + state1_0_nbias; // @[FMAdd.scala 208:31]
-  wire [47:0] state1_0_mul = state1_0_iman_a * state1_0_iman_b; // @[FMAdd.scala 209:22]
-  wire  _state1_0_exp_z_T = ~state1_0_zero; // @[FMAdd.scala 181:21]
-  wire  state1_0_state1_nan = state1_0_nan_a | state1_0_nan_b; // @[FMAdd.scala 193:27]
-  wire  csub = op1[1] | op1[3]; // @[FMAdd.scala 85:37]
-  wire  _cm_T_3 = csub ? ~io_inc_bits_0[31] : io_inc_bits_0[31]; // @[FMAdd.scala 86:23]
-  wire [31:0] cm = {_cm_T_3,io_inc_bits_0[30:0]}; // @[Cat.scala 31:58]
-  wire [31:0] _GEN_47 = {{16'd0}, state1__0_mul[31:16]}; // @[Bitwise.scala 105:31]
-  wire [31:0] _state2_0_a_clz_T_4 = _GEN_47 & 32'hffff; // @[Bitwise.scala 105:31]
-  wire [31:0] _state2_0_a_clz_T_6 = {state1__0_mul[15:0], 16'h0}; // @[Bitwise.scala 105:70]
-  wire [31:0] _state2_0_a_clz_T_8 = _state2_0_a_clz_T_6 & 32'hffff0000; // @[Bitwise.scala 105:80]
-  wire [31:0] _state2_0_a_clz_T_9 = _state2_0_a_clz_T_4 | _state2_0_a_clz_T_8; // @[Bitwise.scala 105:39]
-  wire [31:0] _GEN_48 = {{8'd0}, _state2_0_a_clz_T_9[31:8]}; // @[Bitwise.scala 105:31]
-  wire [31:0] _state2_0_a_clz_T_14 = _GEN_48 & 32'hff00ff; // @[Bitwise.scala 105:31]
-  wire [31:0] _state2_0_a_clz_T_16 = {_state2_0_a_clz_T_9[23:0], 8'h0}; // @[Bitwise.scala 105:70]
-  wire [31:0] _state2_0_a_clz_T_18 = _state2_0_a_clz_T_16 & 32'hff00ff00; // @[Bitwise.scala 105:80]
-  wire [31:0] _state2_0_a_clz_T_19 = _state2_0_a_clz_T_14 | _state2_0_a_clz_T_18; // @[Bitwise.scala 105:39]
-  wire [31:0] _GEN_49 = {{4'd0}, _state2_0_a_clz_T_19[31:4]}; // @[Bitwise.scala 105:31]
-  wire [31:0] _state2_0_a_clz_T_24 = _GEN_49 & 32'hf0f0f0f; // @[Bitwise.scala 105:31]
-  wire [31:0] _state2_0_a_clz_T_26 = {_state2_0_a_clz_T_19[27:0], 4'h0}; // @[Bitwise.scala 105:70]
-  wire [31:0] _state2_0_a_clz_T_28 = _state2_0_a_clz_T_26 & 32'hf0f0f0f0; // @[Bitwise.scala 105:80]
-  wire [31:0] _state2_0_a_clz_T_29 = _state2_0_a_clz_T_24 | _state2_0_a_clz_T_28; // @[Bitwise.scala 105:39]
-  wire [31:0] _GEN_50 = {{2'd0}, _state2_0_a_clz_T_29[31:2]}; // @[Bitwise.scala 105:31]
-  wire [31:0] _state2_0_a_clz_T_34 = _GEN_50 & 32'h33333333; // @[Bitwise.scala 105:31]
-  wire [31:0] _state2_0_a_clz_T_36 = {_state2_0_a_clz_T_29[29:0], 2'h0}; // @[Bitwise.scala 105:70]
-  wire [31:0] _state2_0_a_clz_T_38 = _state2_0_a_clz_T_36 & 32'hcccccccc; // @[Bitwise.scala 105:80]
-  wire [31:0] _state2_0_a_clz_T_39 = _state2_0_a_clz_T_34 | _state2_0_a_clz_T_38; // @[Bitwise.scala 105:39]
-  wire [31:0] _GEN_51 = {{1'd0}, _state2_0_a_clz_T_39[31:1]}; // @[Bitwise.scala 105:31]
-  wire [31:0] _state2_0_a_clz_T_44 = _GEN_51 & 32'h55555555; // @[Bitwise.scala 105:31]
-  wire [31:0] _state2_0_a_clz_T_46 = {_state2_0_a_clz_T_39[30:0], 1'h0}; // @[Bitwise.scala 105:70]
-  wire [31:0] _state2_0_a_clz_T_48 = _state2_0_a_clz_T_46 & 32'haaaaaaaa; // @[Bitwise.scala 105:80]
-  wire [31:0] _state2_0_a_clz_T_49 = _state2_0_a_clz_T_44 | _state2_0_a_clz_T_48; // @[Bitwise.scala 105:39]
-  wire [15:0] _GEN_52 = {{8'd0}, state1__0_mul[47:40]}; // @[Bitwise.scala 105:31]
-  wire [15:0] _state2_0_a_clz_T_54 = _GEN_52 & 16'hff; // @[Bitwise.scala 105:31]
-  wire [15:0] _state2_0_a_clz_T_56 = {state1__0_mul[39:32], 8'h0}; // @[Bitwise.scala 105:70]
-  wire [15:0] _state2_0_a_clz_T_58 = _state2_0_a_clz_T_56 & 16'hff00; // @[Bitwise.scala 105:80]
-  wire [15:0] _state2_0_a_clz_T_59 = _state2_0_a_clz_T_54 | _state2_0_a_clz_T_58; // @[Bitwise.scala 105:39]
-  wire [15:0] _GEN_53 = {{4'd0}, _state2_0_a_clz_T_59[15:4]}; // @[Bitwise.scala 105:31]
-  wire [15:0] _state2_0_a_clz_T_64 = _GEN_53 & 16'hf0f; // @[Bitwise.scala 105:31]
-  wire [15:0] _state2_0_a_clz_T_66 = {_state2_0_a_clz_T_59[11:0], 4'h0}; // @[Bitwise.scala 105:70]
-  wire [15:0] _state2_0_a_clz_T_68 = _state2_0_a_clz_T_66 & 16'hf0f0; // @[Bitwise.scala 105:80]
-  wire [15:0] _state2_0_a_clz_T_69 = _state2_0_a_clz_T_64 | _state2_0_a_clz_T_68; // @[Bitwise.scala 105:39]
-  wire [15:0] _GEN_54 = {{2'd0}, _state2_0_a_clz_T_69[15:2]}; // @[Bitwise.scala 105:31]
-  wire [15:0] _state2_0_a_clz_T_74 = _GEN_54 & 16'h3333; // @[Bitwise.scala 105:31]
-  wire [15:0] _state2_0_a_clz_T_76 = {_state2_0_a_clz_T_69[13:0], 2'h0}; // @[Bitwise.scala 105:70]
-  wire [15:0] _state2_0_a_clz_T_78 = _state2_0_a_clz_T_76 & 16'hcccc; // @[Bitwise.scala 105:80]
-  wire [15:0] _state2_0_a_clz_T_79 = _state2_0_a_clz_T_74 | _state2_0_a_clz_T_78; // @[Bitwise.scala 105:39]
-  wire [15:0] _GEN_55 = {{1'd0}, _state2_0_a_clz_T_79[15:1]}; // @[Bitwise.scala 105:31]
-  wire [15:0] _state2_0_a_clz_T_84 = _GEN_55 & 16'h5555; // @[Bitwise.scala 105:31]
-  wire [15:0] _state2_0_a_clz_T_86 = {_state2_0_a_clz_T_79[14:0], 1'h0}; // @[Bitwise.scala 105:70]
-  wire [15:0] _state2_0_a_clz_T_88 = _state2_0_a_clz_T_86 & 16'haaaa; // @[Bitwise.scala 105:80]
-  wire [15:0] _state2_0_a_clz_T_89 = _state2_0_a_clz_T_84 | _state2_0_a_clz_T_88; // @[Bitwise.scala 105:39]
-  wire [47:0] _state2_0_a_clz_T_90 = {_state2_0_a_clz_T_49,_state2_0_a_clz_T_89}; // @[Cat.scala 31:58]
-  wire [5:0] _state2_0_a_clz_T_139 = _state2_0_a_clz_T_90[46] ? 6'h2e : 6'h2f; // @[Mux.scala 47:70]
-  wire [5:0] _state2_0_a_clz_T_140 = _state2_0_a_clz_T_90[45] ? 6'h2d : _state2_0_a_clz_T_139; // @[Mux.scala 47:70]
-  wire [5:0] _state2_0_a_clz_T_141 = _state2_0_a_clz_T_90[44] ? 6'h2c : _state2_0_a_clz_T_140; // @[Mux.scala 47:70]
-  wire [5:0] _state2_0_a_clz_T_142 = _state2_0_a_clz_T_90[43] ? 6'h2b : _state2_0_a_clz_T_141; // @[Mux.scala 47:70]
-  wire [5:0] _state2_0_a_clz_T_143 = _state2_0_a_clz_T_90[42] ? 6'h2a : _state2_0_a_clz_T_142; // @[Mux.scala 47:70]
-  wire [5:0] _state2_0_a_clz_T_144 = _state2_0_a_clz_T_90[41] ? 6'h29 : _state2_0_a_clz_T_143; // @[Mux.scala 47:70]
-  wire [5:0] _state2_0_a_clz_T_145 = _state2_0_a_clz_T_90[40] ? 6'h28 : _state2_0_a_clz_T_144; // @[Mux.scala 47:70]
-  wire [5:0] _state2_0_a_clz_T_146 = _state2_0_a_clz_T_90[39] ? 6'h27 : _state2_0_a_clz_T_145; // @[Mux.scala 47:70]
-  wire [5:0] _state2_0_a_clz_T_147 = _state2_0_a_clz_T_90[38] ? 6'h26 : _state2_0_a_clz_T_146; // @[Mux.scala 47:70]
-  wire [5:0] _state2_0_a_clz_T_148 = _state2_0_a_clz_T_90[37] ? 6'h25 : _state2_0_a_clz_T_147; // @[Mux.scala 47:70]
-  wire [5:0] _state2_0_a_clz_T_149 = _state2_0_a_clz_T_90[36] ? 6'h24 : _state2_0_a_clz_T_148; // @[Mux.scala 47:70]
-  wire [5:0] _state2_0_a_clz_T_150 = _state2_0_a_clz_T_90[35] ? 6'h23 : _state2_0_a_clz_T_149; // @[Mux.scala 47:70]
-  wire [5:0] _state2_0_a_clz_T_151 = _state2_0_a_clz_T_90[34] ? 6'h22 : _state2_0_a_clz_T_150; // @[Mux.scala 47:70]
-  wire [5:0] _state2_0_a_clz_T_152 = _state2_0_a_clz_T_90[33] ? 6'h21 : _state2_0_a_clz_T_151; // @[Mux.scala 47:70]
-  wire [5:0] _state2_0_a_clz_T_153 = _state2_0_a_clz_T_90[32] ? 6'h20 : _state2_0_a_clz_T_152; // @[Mux.scala 47:70]
-  wire [5:0] _state2_0_a_clz_T_154 = _state2_0_a_clz_T_90[31] ? 6'h1f : _state2_0_a_clz_T_153; // @[Mux.scala 47:70]
-  wire [5:0] _state2_0_a_clz_T_155 = _state2_0_a_clz_T_90[30] ? 6'h1e : _state2_0_a_clz_T_154; // @[Mux.scala 47:70]
-  wire [5:0] _state2_0_a_clz_T_156 = _state2_0_a_clz_T_90[29] ? 6'h1d : _state2_0_a_clz_T_155; // @[Mux.scala 47:70]
-  wire [5:0] _state2_0_a_clz_T_157 = _state2_0_a_clz_T_90[28] ? 6'h1c : _state2_0_a_clz_T_156; // @[Mux.scala 47:70]
-  wire [5:0] _state2_0_a_clz_T_158 = _state2_0_a_clz_T_90[27] ? 6'h1b : _state2_0_a_clz_T_157; // @[Mux.scala 47:70]
-  wire [5:0] _state2_0_a_clz_T_159 = _state2_0_a_clz_T_90[26] ? 6'h1a : _state2_0_a_clz_T_158; // @[Mux.scala 47:70]
-  wire [5:0] _state2_0_a_clz_T_160 = _state2_0_a_clz_T_90[25] ? 6'h19 : _state2_0_a_clz_T_159; // @[Mux.scala 47:70]
-  wire [5:0] _state2_0_a_clz_T_161 = _state2_0_a_clz_T_90[24] ? 6'h18 : _state2_0_a_clz_T_160; // @[Mux.scala 47:70]
-  wire [5:0] _state2_0_a_clz_T_162 = _state2_0_a_clz_T_90[23] ? 6'h17 : _state2_0_a_clz_T_161; // @[Mux.scala 47:70]
-  wire [5:0] _state2_0_a_clz_T_163 = _state2_0_a_clz_T_90[22] ? 6'h16 : _state2_0_a_clz_T_162; // @[Mux.scala 47:70]
-  wire [5:0] _state2_0_a_clz_T_164 = _state2_0_a_clz_T_90[21] ? 6'h15 : _state2_0_a_clz_T_163; // @[Mux.scala 47:70]
-  wire [5:0] _state2_0_a_clz_T_165 = _state2_0_a_clz_T_90[20] ? 6'h14 : _state2_0_a_clz_T_164; // @[Mux.scala 47:70]
-  wire [5:0] _state2_0_a_clz_T_166 = _state2_0_a_clz_T_90[19] ? 6'h13 : _state2_0_a_clz_T_165; // @[Mux.scala 47:70]
-  wire [5:0] _state2_0_a_clz_T_167 = _state2_0_a_clz_T_90[18] ? 6'h12 : _state2_0_a_clz_T_166; // @[Mux.scala 47:70]
-  wire [5:0] _state2_0_a_clz_T_168 = _state2_0_a_clz_T_90[17] ? 6'h11 : _state2_0_a_clz_T_167; // @[Mux.scala 47:70]
-  wire [5:0] _state2_0_a_clz_T_169 = _state2_0_a_clz_T_90[16] ? 6'h10 : _state2_0_a_clz_T_168; // @[Mux.scala 47:70]
-  wire [5:0] _state2_0_a_clz_T_170 = _state2_0_a_clz_T_90[15] ? 6'hf : _state2_0_a_clz_T_169; // @[Mux.scala 47:70]
-  wire [5:0] _state2_0_a_clz_T_171 = _state2_0_a_clz_T_90[14] ? 6'he : _state2_0_a_clz_T_170; // @[Mux.scala 47:70]
-  wire [5:0] _state2_0_a_clz_T_172 = _state2_0_a_clz_T_90[13] ? 6'hd : _state2_0_a_clz_T_171; // @[Mux.scala 47:70]
-  wire [5:0] _state2_0_a_clz_T_173 = _state2_0_a_clz_T_90[12] ? 6'hc : _state2_0_a_clz_T_172; // @[Mux.scala 47:70]
-  wire [5:0] _state2_0_a_clz_T_174 = _state2_0_a_clz_T_90[11] ? 6'hb : _state2_0_a_clz_T_173; // @[Mux.scala 47:70]
-  wire [5:0] _state2_0_a_clz_T_175 = _state2_0_a_clz_T_90[10] ? 6'ha : _state2_0_a_clz_T_174; // @[Mux.scala 47:70]
-  wire [5:0] _state2_0_a_clz_T_176 = _state2_0_a_clz_T_90[9] ? 6'h9 : _state2_0_a_clz_T_175; // @[Mux.scala 47:70]
-  wire [5:0] _state2_0_a_clz_T_177 = _state2_0_a_clz_T_90[8] ? 6'h8 : _state2_0_a_clz_T_176; // @[Mux.scala 47:70]
-  wire [5:0] _state2_0_a_clz_T_178 = _state2_0_a_clz_T_90[7] ? 6'h7 : _state2_0_a_clz_T_177; // @[Mux.scala 47:70]
-  wire [5:0] _state2_0_a_clz_T_179 = _state2_0_a_clz_T_90[6] ? 6'h6 : _state2_0_a_clz_T_178; // @[Mux.scala 47:70]
-  wire [5:0] _state2_0_a_clz_T_180 = _state2_0_a_clz_T_90[5] ? 6'h5 : _state2_0_a_clz_T_179; // @[Mux.scala 47:70]
-  wire [5:0] _state2_0_a_clz_T_181 = _state2_0_a_clz_T_90[4] ? 6'h4 : _state2_0_a_clz_T_180; // @[Mux.scala 47:70]
-  wire [5:0] _state2_0_a_clz_T_182 = _state2_0_a_clz_T_90[3] ? 6'h3 : _state2_0_a_clz_T_181; // @[Mux.scala 47:70]
-  wire [5:0] _state2_0_a_clz_T_183 = _state2_0_a_clz_T_90[2] ? 6'h2 : _state2_0_a_clz_T_182; // @[Mux.scala 47:70]
-  wire [5:0] _state2_0_a_clz_T_184 = _state2_0_a_clz_T_90[1] ? 6'h1 : _state2_0_a_clz_T_183; // @[Mux.scala 47:70]
-  wire [5:0] state2_0_a_clz = _state2_0_a_clz_T_90[0] ? 6'h0 : _state2_0_a_clz_T_184; // @[Mux.scala 47:70]
-  wire  _state2_0_b_clz_T_1 = cm[30:23] != 8'h0; // @[FMAdd.scala 228:32]
-  wire [23:0] _state2_0_b_clz_T_3 = {1'h0,cm[22:0]}; // @[Cat.scala 31:58]
-  wire [15:0] _GEN_56 = {{8'd0}, _state2_0_b_clz_T_3[15:8]}; // @[Bitwise.scala 105:31]
-  wire [15:0] _state2_0_b_clz_T_8 = _GEN_56 & 16'hff; // @[Bitwise.scala 105:31]
-  wire [15:0] _state2_0_b_clz_T_10 = {_state2_0_b_clz_T_3[7:0], 8'h0}; // @[Bitwise.scala 105:70]
-  wire [15:0] _state2_0_b_clz_T_12 = _state2_0_b_clz_T_10 & 16'hff00; // @[Bitwise.scala 105:80]
-  wire [15:0] _state2_0_b_clz_T_13 = _state2_0_b_clz_T_8 | _state2_0_b_clz_T_12; // @[Bitwise.scala 105:39]
-  wire [15:0] _GEN_57 = {{4'd0}, _state2_0_b_clz_T_13[15:4]}; // @[Bitwise.scala 105:31]
-  wire [15:0] _state2_0_b_clz_T_18 = _GEN_57 & 16'hf0f; // @[Bitwise.scala 105:31]
-  wire [15:0] _state2_0_b_clz_T_20 = {_state2_0_b_clz_T_13[11:0], 4'h0}; // @[Bitwise.scala 105:70]
-  wire [15:0] _state2_0_b_clz_T_22 = _state2_0_b_clz_T_20 & 16'hf0f0; // @[Bitwise.scala 105:80]
-  wire [15:0] _state2_0_b_clz_T_23 = _state2_0_b_clz_T_18 | _state2_0_b_clz_T_22; // @[Bitwise.scala 105:39]
-  wire [15:0] _GEN_58 = {{2'd0}, _state2_0_b_clz_T_23[15:2]}; // @[Bitwise.scala 105:31]
-  wire [15:0] _state2_0_b_clz_T_28 = _GEN_58 & 16'h3333; // @[Bitwise.scala 105:31]
-  wire [15:0] _state2_0_b_clz_T_30 = {_state2_0_b_clz_T_23[13:0], 2'h0}; // @[Bitwise.scala 105:70]
-  wire [15:0] _state2_0_b_clz_T_32 = _state2_0_b_clz_T_30 & 16'hcccc; // @[Bitwise.scala 105:80]
-  wire [15:0] _state2_0_b_clz_T_33 = _state2_0_b_clz_T_28 | _state2_0_b_clz_T_32; // @[Bitwise.scala 105:39]
-  wire [15:0] _GEN_59 = {{1'd0}, _state2_0_b_clz_T_33[15:1]}; // @[Bitwise.scala 105:31]
-  wire [15:0] _state2_0_b_clz_T_38 = _GEN_59 & 16'h5555; // @[Bitwise.scala 105:31]
-  wire [15:0] _state2_0_b_clz_T_40 = {_state2_0_b_clz_T_33[14:0], 1'h0}; // @[Bitwise.scala 105:70]
-  wire [15:0] _state2_0_b_clz_T_42 = _state2_0_b_clz_T_40 & 16'haaaa; // @[Bitwise.scala 105:80]
-  wire [15:0] _state2_0_b_clz_T_43 = _state2_0_b_clz_T_38 | _state2_0_b_clz_T_42; // @[Bitwise.scala 105:39]
-  wire [7:0] _GEN_60 = {{4'd0}, _state2_0_b_clz_T_3[23:20]}; // @[Bitwise.scala 105:31]
-  wire [7:0] _state2_0_b_clz_T_48 = _GEN_60 & 8'hf; // @[Bitwise.scala 105:31]
-  wire [7:0] _state2_0_b_clz_T_50 = {_state2_0_b_clz_T_3[19:16], 4'h0}; // @[Bitwise.scala 105:70]
-  wire [7:0] _state2_0_b_clz_T_52 = _state2_0_b_clz_T_50 & 8'hf0; // @[Bitwise.scala 105:80]
-  wire [7:0] _state2_0_b_clz_T_53 = _state2_0_b_clz_T_48 | _state2_0_b_clz_T_52; // @[Bitwise.scala 105:39]
-  wire [7:0] _GEN_61 = {{2'd0}, _state2_0_b_clz_T_53[7:2]}; // @[Bitwise.scala 105:31]
-  wire [7:0] _state2_0_b_clz_T_58 = _GEN_61 & 8'h33; // @[Bitwise.scala 105:31]
-  wire [7:0] _state2_0_b_clz_T_60 = {_state2_0_b_clz_T_53[5:0], 2'h0}; // @[Bitwise.scala 105:70]
-  wire [7:0] _state2_0_b_clz_T_62 = _state2_0_b_clz_T_60 & 8'hcc; // @[Bitwise.scala 105:80]
-  wire [7:0] _state2_0_b_clz_T_63 = _state2_0_b_clz_T_58 | _state2_0_b_clz_T_62; // @[Bitwise.scala 105:39]
-  wire [7:0] _GEN_62 = {{1'd0}, _state2_0_b_clz_T_63[7:1]}; // @[Bitwise.scala 105:31]
-  wire [7:0] _state2_0_b_clz_T_68 = _GEN_62 & 8'h55; // @[Bitwise.scala 105:31]
-  wire [7:0] _state2_0_b_clz_T_70 = {_state2_0_b_clz_T_63[6:0], 1'h0}; // @[Bitwise.scala 105:70]
-  wire [7:0] _state2_0_b_clz_T_72 = _state2_0_b_clz_T_70 & 8'haa; // @[Bitwise.scala 105:80]
-  wire [7:0] _state2_0_b_clz_T_73 = _state2_0_b_clz_T_68 | _state2_0_b_clz_T_72; // @[Bitwise.scala 105:39]
-  wire [23:0] _state2_0_b_clz_T_74 = {_state2_0_b_clz_T_43,_state2_0_b_clz_T_73}; // @[Cat.scala 31:58]
-  wire [4:0] _state2_0_b_clz_T_99 = _state2_0_b_clz_T_74[22] ? 5'h16 : 5'h17; // @[Mux.scala 47:70]
-  wire [4:0] _state2_0_b_clz_T_100 = _state2_0_b_clz_T_74[21] ? 5'h15 : _state2_0_b_clz_T_99; // @[Mux.scala 47:70]
-  wire [4:0] _state2_0_b_clz_T_101 = _state2_0_b_clz_T_74[20] ? 5'h14 : _state2_0_b_clz_T_100; // @[Mux.scala 47:70]
-  wire [4:0] _state2_0_b_clz_T_102 = _state2_0_b_clz_T_74[19] ? 5'h13 : _state2_0_b_clz_T_101; // @[Mux.scala 47:70]
-  wire [4:0] _state2_0_b_clz_T_103 = _state2_0_b_clz_T_74[18] ? 5'h12 : _state2_0_b_clz_T_102; // @[Mux.scala 47:70]
-  wire [4:0] _state2_0_b_clz_T_104 = _state2_0_b_clz_T_74[17] ? 5'h11 : _state2_0_b_clz_T_103; // @[Mux.scala 47:70]
-  wire [4:0] _state2_0_b_clz_T_105 = _state2_0_b_clz_T_74[16] ? 5'h10 : _state2_0_b_clz_T_104; // @[Mux.scala 47:70]
-  wire [4:0] _state2_0_b_clz_T_106 = _state2_0_b_clz_T_74[15] ? 5'hf : _state2_0_b_clz_T_105; // @[Mux.scala 47:70]
-  wire [4:0] _state2_0_b_clz_T_107 = _state2_0_b_clz_T_74[14] ? 5'he : _state2_0_b_clz_T_106; // @[Mux.scala 47:70]
-  wire [4:0] _state2_0_b_clz_T_108 = _state2_0_b_clz_T_74[13] ? 5'hd : _state2_0_b_clz_T_107; // @[Mux.scala 47:70]
-  wire [4:0] _state2_0_b_clz_T_109 = _state2_0_b_clz_T_74[12] ? 5'hc : _state2_0_b_clz_T_108; // @[Mux.scala 47:70]
-  wire [4:0] _state2_0_b_clz_T_110 = _state2_0_b_clz_T_74[11] ? 5'hb : _state2_0_b_clz_T_109; // @[Mux.scala 47:70]
-  wire [4:0] _state2_0_b_clz_T_111 = _state2_0_b_clz_T_74[10] ? 5'ha : _state2_0_b_clz_T_110; // @[Mux.scala 47:70]
-  wire [4:0] _state2_0_b_clz_T_112 = _state2_0_b_clz_T_74[9] ? 5'h9 : _state2_0_b_clz_T_111; // @[Mux.scala 47:70]
-  wire [4:0] _state2_0_b_clz_T_113 = _state2_0_b_clz_T_74[8] ? 5'h8 : _state2_0_b_clz_T_112; // @[Mux.scala 47:70]
-  wire [4:0] _state2_0_b_clz_T_114 = _state2_0_b_clz_T_74[7] ? 5'h7 : _state2_0_b_clz_T_113; // @[Mux.scala 47:70]
-  wire [4:0] _state2_0_b_clz_T_115 = _state2_0_b_clz_T_74[6] ? 5'h6 : _state2_0_b_clz_T_114; // @[Mux.scala 47:70]
-  wire [4:0] _state2_0_b_clz_T_116 = _state2_0_b_clz_T_74[5] ? 5'h5 : _state2_0_b_clz_T_115; // @[Mux.scala 47:70]
-  wire [4:0] _state2_0_b_clz_T_117 = _state2_0_b_clz_T_74[4] ? 5'h4 : _state2_0_b_clz_T_116; // @[Mux.scala 47:70]
-  wire [4:0] _state2_0_b_clz_T_118 = _state2_0_b_clz_T_74[3] ? 5'h3 : _state2_0_b_clz_T_117; // @[Mux.scala 47:70]
-  wire [4:0] _state2_0_b_clz_T_119 = _state2_0_b_clz_T_74[2] ? 5'h2 : _state2_0_b_clz_T_118; // @[Mux.scala 47:70]
-  wire [4:0] _state2_0_b_clz_T_120 = _state2_0_b_clz_T_74[1] ? 5'h1 : _state2_0_b_clz_T_119; // @[Mux.scala 47:70]
-  wire [4:0] _state2_0_b_clz_T_121 = _state2_0_b_clz_T_74[0] ? 5'h0 : _state2_0_b_clz_T_120; // @[Mux.scala 47:70]
-  wire [4:0] state2_0_b_clz = cm[30:23] != 8'h0 ? 5'h0 : _state2_0_b_clz_T_121; // @[FMAdd.scala 228:20]
-  wire  state2_0_acm_sign = cm[31]; // @[FMAdd.scala 230:23]
-  wire  _state2_0_acm_exp_T_4 = cm[22:0] != 23'h0; // @[FMAdd.scala 231:69]
-  wire [7:0] state2_0_acm_exp = _state2_0_b_clz_T_1 ? cm[30:23] : {{7'd0}, cm[22:0] != 23'h0}; // @[FMAdd.scala 231:22]
-  wire  _state2_0_b_zero_T_1 = cm[22:0] == 23'h0; // @[FMAdd.scala 235:46]
-  wire  state2_0_b_zero = state2_0_acm_exp == 8'h0 & cm[22:0] == 23'h0; // @[FMAdd.scala 235:34]
-  wire [9:0] _GEN_63 = {{4'd0}, state2_0_a_clz}; // @[FMAdd.scala 240:28]
-  wire [9:0] state2_0_a_exp = state1__0_exp - _GEN_63; // @[FMAdd.scala 240:28]
-  wire [9:0] _state2_0_b_exp_T = {2'h0,state2_0_acm_exp}; // @[Cat.scala 31:58]
-  wire [9:0] _GEN_64 = {{5'd0}, state2_0_b_clz}; // @[FMAdd.scala 241:40]
-  wire [9:0] _state2_0_b_exp_T_2 = _state2_0_b_exp_T - _GEN_64; // @[FMAdd.scala 241:40]
-  wire [9:0] state2_0_b_exp = _state2_0_b_exp_T_2 - 10'h1; // @[FMAdd.scala 241:48]
-  wire [47:0] state2_0_b_man = {_state2_0_b_clz_T_1,cm[22:0],24'h0}; // @[Cat.scala 31:58]
-  wire [110:0] _GEN_0 = {{63'd0}, state1__0_mul}; // @[FMAdd.scala 248:24]
-  wire [110:0] _state2_0_a_shl_T = _GEN_0 << state2_0_a_clz; // @[FMAdd.scala 248:24]
-  wire [47:0] state2_0_a_shl = _state2_0_a_shl_T[47:0]; // @[FMAdd.scala 248:33]
-  wire [78:0] _GEN_1 = {{31'd0}, state2_0_b_man}; // @[FMAdd.scala 249:24]
-  wire [78:0] _state2_0_b_shl_T = _GEN_1 << state2_0_b_clz; // @[FMAdd.scala 249:24]
-  wire [47:0] state2_0_b_shl = _state2_0_b_shl_T[47:0]; // @[FMAdd.scala 249:33]
-  wire  _state2_0_sp_state_c_inf_T_1 = cm[30:23] == 8'hff; // @[FBase.scala 64:19]
-  wire  state2_0_sp_state_c_inf = cm[30:23] == 8'hff & _state2_0_b_zero_T_1; // @[FBase.scala 64:37]
-  wire  state2_0_sp_state_c_nan = _state2_0_sp_state_c_inf_T_1 & _state2_0_acm_exp_T_4; // @[FBase.scala 68:37]
-  wire  _state2_0_sp_state_T_1 = state1__0_inf_a | state1__0_inf_b; // @[FMAdd.scala 295:32]
-  wire  _state2_0_sp_state_T_3 = state1__0_sign != state2_0_acm_sign; // @[FMAdd.scala 295:73]
-  wire  _GEN_13 = _state2_0_sp_state_T_3 ? 1'h0 : state2_0_acm_sign; // @[FMAdd.scala 280:17 303:37 304:21]
-  wire [22:0] _GEN_14 = _state2_0_sp_state_T_3 ? 23'h400000 : 23'h0; // @[FMAdd.scala 303:37 305:20 307:20]
-  wire  _GEN_15 = state1__0_zero ? 1'h0 : state1__0_sign; // @[FMAdd.scala 312:26 313:21 316:21]
-  wire [22:0] _GEN_16 = state1__0_zero ? 23'h400000 : 23'h0; // @[FMAdd.scala 312:26 314:20 317:20]
-  wire  _GEN_18 = state2_0_sp_state_c_inf | state1__0_zero; // @[FMAdd.scala 319:25 320:18]
-  wire  _GEN_19 = _state2_0_sp_state_T_1 | _GEN_18; // @[FMAdd.scala 309:48 310:18]
-  wire [7:0] _GEN_20 = _state2_0_sp_state_T_1 ? 8'hff : cm[30:23]; // @[FMAdd.scala 281:16 309:48 311:18]
-  wire  _GEN_21 = _state2_0_sp_state_T_1 ? _GEN_15 : state2_0_acm_sign; // @[FMAdd.scala 280:17 309:48]
-  wire [22:0] _GEN_22 = _state2_0_sp_state_T_1 ? _GEN_16 : cm[22:0]; // @[FMAdd.scala 282:16 309:48]
-  wire  _GEN_23 = state1__0_inf_a & state1__0_inf_b & state2_0_sp_state_c_inf | _GEN_19; // @[FMAdd.scala 300:57 301:18]
-  wire [7:0] _GEN_24 = state1__0_inf_a & state1__0_inf_b & state2_0_sp_state_c_inf ? 8'hff : _GEN_20; // @[FMAdd.scala 300:57 302:18]
-  wire  _GEN_25 = state1__0_inf_a & state1__0_inf_b & state2_0_sp_state_c_inf ? _GEN_13 : _GEN_21; // @[FMAdd.scala 300:57]
-  wire [22:0] _GEN_26 = state1__0_inf_a & state1__0_inf_b & state2_0_sp_state_c_inf ? _GEN_14 : _GEN_22; // @[FMAdd.scala 300:57]
-  wire  _GEN_28 = (state1__0_inf_a | state1__0_inf_b) & state2_0_sp_state_c_inf & state1__0_sign != state2_0_acm_sign |
-    _GEN_23; // @[FMAdd.scala 295:85 297:18]
-  wire [7:0] _GEN_29 = (state1__0_inf_a | state1__0_inf_b) & state2_0_sp_state_c_inf & state1__0_sign !=
-    state2_0_acm_sign ? 8'hff : _GEN_24; // @[FMAdd.scala 295:85 298:18]
-  wire [22:0] _GEN_30 = (state1__0_inf_a | state1__0_inf_b) & state2_0_sp_state_c_inf & state1__0_sign !=
-    state2_0_acm_sign ? 23'h400000 : _GEN_26; // @[FMAdd.scala 295:85 299:18]
-  wire  state2_0_sp_state_sel = state1__0_nan | state2_0_sp_state_c_nan | _GEN_28; // @[FMAdd.scala 290:32 292:18]
-  wire [7:0] _GEN_33 = state1__0_nan | state2_0_sp_state_c_nan ? 8'hff : _GEN_29; // @[FMAdd.scala 290:32 293:18]
-  wire [22:0] _GEN_34 = state1__0_nan | state2_0_sp_state_c_nan ? 23'h400000 : _GEN_30; // @[FMAdd.scala 290:32 294:18]
-  wire [48:0] state2_0_ab_state_a_shbits = {state2_0_a_shl,1'h0}; // @[Cat.scala 31:58]
-  wire [9:0] state2_0_ab_state_b_shdiff = state2_0_a_exp - state2_0_b_exp; // @[FMAdd.scala 340:26]
-  wire [5:0] state2_0_ab_state_b_shamt = state2_0_ab_state_b_shdiff < 10'h40 ? state2_0_ab_state_b_shdiff[5:0] : 6'h3f; // @[FMAdd.scala 341:22]
-  wire [111:0] _state2_0_ab_state_b_shmask_T_1 = 112'h1ffffffffffff << state2_0_ab_state_b_shamt; // @[FMAdd.scala 344:35]
-  wire [48:0] state2_0_ab_state_b_shmask = ~_state2_0_ab_state_b_shmask_T_1[48:0]; // @[FMAdd.scala 344:20]
-  wire [48:0] _state2_0_ab_state_b_shbits_T = {state2_0_b_shl,1'h0}; // @[Cat.scala 31:58]
-  wire [48:0] _state2_0_ab_state_b_shbits_T_1 = _state2_0_ab_state_b_shbits_T >> state2_0_ab_state_b_shamt; // @[FMAdd.scala 345:42]
-  wire [48:0] _GEN_65 = {{1'd0}, state2_0_b_shl}; // @[FMAdd.scala 345:64]
-  wire [48:0] _state2_0_ab_state_b_shbits_T_2 = _GEN_65 & state2_0_ab_state_b_shmask; // @[FMAdd.scala 345:64]
-  wire [48:0] _GEN_66 = {{48'd0}, _state2_0_ab_state_b_shbits_T_2 != 49'h0}; // @[FMAdd.scala 345:54]
-  wire [48:0] state2_0_ab_state_b_shbits = _state2_0_ab_state_b_shbits_T_1 | _GEN_66; // @[FMAdd.scala 345:54]
-  wire  state2_0_ab_state_add = state1__0_sign == state2_0_acm_sign; // @[FMAdd.scala 355:26]
-  wire [9:0] state2_0_ba_state_b_shdiff = state2_0_b_exp - state2_0_a_exp; // @[FMAdd.scala 340:26]
-  wire [5:0] state2_0_ba_state_b_shamt = state2_0_ba_state_b_shdiff < 10'h40 ? state2_0_ba_state_b_shdiff[5:0] : 6'h3f; // @[FMAdd.scala 341:22]
-  wire [111:0] _state2_0_ba_state_b_shmask_T_1 = 112'h1ffffffffffff << state2_0_ba_state_b_shamt; // @[FMAdd.scala 344:35]
-  wire [48:0] state2_0_ba_state_b_shmask = ~_state2_0_ba_state_b_shmask_T_1[48:0]; // @[FMAdd.scala 344:20]
-  wire [48:0] _state2_0_ba_state_b_shbits_T_1 = state2_0_ab_state_a_shbits >> state2_0_ba_state_b_shamt; // @[FMAdd.scala 345:42]
-  wire [48:0] _GEN_67 = {{1'd0}, state2_0_a_shl}; // @[FMAdd.scala 345:64]
-  wire [48:0] _state2_0_ba_state_b_shbits_T_2 = _GEN_67 & state2_0_ba_state_b_shmask; // @[FMAdd.scala 345:64]
-  wire [48:0] _GEN_68 = {{48'd0}, _state2_0_ba_state_b_shbits_T_2 != 49'h0}; // @[FMAdd.scala 345:54]
-  wire [48:0] state2_0_ba_state_b_shbits = _state2_0_ba_state_b_shbits_T_1 | _GEN_68; // @[FMAdd.scala 345:54]
-  wire  state2_0_ba_state_add = state2_0_acm_sign == state1__0_sign; // @[FMAdd.scala 355:26]
-  wire  state2_0_ba_state_sub = state2_0_acm_sign != state1__0_sign; // @[FMAdd.scala 356:26]
-  wire [9:0] _state2_0_sel_ab_T_1 = state1__0_exp - _GEN_63; // @[FMAdd.scala 258:36]
-  wire [9:0] _state2_0_sel_ab_T_2 = _state2_0_b_exp_T_2 - 10'h1; // @[FMAdd.scala 258:51]
-  wire  state2_0_sel_ab = ~state2_0_sp_state_sel & ($signed(_state2_0_sel_ab_T_1) > $signed(_state2_0_sel_ab_T_2) |
-    state2_0_a_exp == state2_0_b_exp & state2_0_a_shl >= state2_0_b_shl | state2_0_b_zero); // @[FMAdd.scala 258:26]
-  wire [9:0] state2_0_sp_state_exp = {{2'd0}, _GEN_33}; // @[FMAdd.scala 270:22]
-  wire [48:0] state2_0_sp_state_ain = {{26'd0}, _GEN_34}; // @[FMAdd.scala 270:22]
-  wire [49:0] state3_0_add = state2_0_ain + state2_0_bin; // @[FMAdd.scala 373:26]
-  wire [49:0] state3_0_sub = state2_0_ain - state2_0_bin; // @[FMAdd.scala 374:26]
-  wire [48:0] _state3_0_result_man_T = state2_0_sel ? state2_0_ain : 49'h0; // @[FMAdd.scala 378:25]
-  wire [49:0] _state3_0_result_man_T_1 = state2_0_add ? state3_0_add : 50'h0; // @[FMAdd.scala 379:25]
-  wire [49:0] _GEN_69 = {{1'd0}, _state3_0_result_man_T}; // @[FMAdd.scala 378:55]
-  wire [49:0] _state3_0_result_man_T_2 = _GEN_69 | _state3_0_result_man_T_1; // @[FMAdd.scala 378:55]
-  wire [49:0] _state3_0_result_man_T_3 = state2_0_sub ? state3_0_sub : 50'h0; // @[FMAdd.scala 380:25]
-  wire [49:0] state3_0_result_man = _state3_0_result_man_T_2 | _state3_0_result_man_T_3; // @[FMAdd.scala 379:48]
-  wire [2:0] _state3_0_T = {state2_0_sel,state2_0_add,state2_0_sub}; // @[Cat.scala 31:58]
-  wire [1:0] _state3_0_T_4 = _state3_0_T[1] + _state3_0_T[2]; // @[Bitwise.scala 48:55]
-  wire [1:0] _GEN_70 = {{1'd0}, _state3_0_T[0]}; // @[Bitwise.scala 48:55]
-  wire [2:0] _state3_0_T_6 = _GEN_70 + _state3_0_T_4; // @[Bitwise.scala 48:55]
-  wire [31:0] _GEN_71 = {{16'd0}, state3_0_result_man[31:16]}; // @[Bitwise.scala 105:31]
-  wire [31:0] _state3_0_norm_clz_T_7 = _GEN_71 & 32'hffff; // @[Bitwise.scala 105:31]
-  wire [31:0] _state3_0_norm_clz_T_9 = {state3_0_result_man[15:0], 16'h0}; // @[Bitwise.scala 105:70]
-  wire [31:0] _state3_0_norm_clz_T_11 = _state3_0_norm_clz_T_9 & 32'hffff0000; // @[Bitwise.scala 105:80]
-  wire [31:0] _state3_0_norm_clz_T_12 = _state3_0_norm_clz_T_7 | _state3_0_norm_clz_T_11; // @[Bitwise.scala 105:39]
-  wire [31:0] _GEN_72 = {{8'd0}, _state3_0_norm_clz_T_12[31:8]}; // @[Bitwise.scala 105:31]
-  wire [31:0] _state3_0_norm_clz_T_17 = _GEN_72 & 32'hff00ff; // @[Bitwise.scala 105:31]
-  wire [31:0] _state3_0_norm_clz_T_19 = {_state3_0_norm_clz_T_12[23:0], 8'h0}; // @[Bitwise.scala 105:70]
-  wire [31:0] _state3_0_norm_clz_T_21 = _state3_0_norm_clz_T_19 & 32'hff00ff00; // @[Bitwise.scala 105:80]
-  wire [31:0] _state3_0_norm_clz_T_22 = _state3_0_norm_clz_T_17 | _state3_0_norm_clz_T_21; // @[Bitwise.scala 105:39]
-  wire [31:0] _GEN_73 = {{4'd0}, _state3_0_norm_clz_T_22[31:4]}; // @[Bitwise.scala 105:31]
-  wire [31:0] _state3_0_norm_clz_T_27 = _GEN_73 & 32'hf0f0f0f; // @[Bitwise.scala 105:31]
-  wire [31:0] _state3_0_norm_clz_T_29 = {_state3_0_norm_clz_T_22[27:0], 4'h0}; // @[Bitwise.scala 105:70]
-  wire [31:0] _state3_0_norm_clz_T_31 = _state3_0_norm_clz_T_29 & 32'hf0f0f0f0; // @[Bitwise.scala 105:80]
-  wire [31:0] _state3_0_norm_clz_T_32 = _state3_0_norm_clz_T_27 | _state3_0_norm_clz_T_31; // @[Bitwise.scala 105:39]
-  wire [31:0] _GEN_74 = {{2'd0}, _state3_0_norm_clz_T_32[31:2]}; // @[Bitwise.scala 105:31]
-  wire [31:0] _state3_0_norm_clz_T_37 = _GEN_74 & 32'h33333333; // @[Bitwise.scala 105:31]
-  wire [31:0] _state3_0_norm_clz_T_39 = {_state3_0_norm_clz_T_32[29:0], 2'h0}; // @[Bitwise.scala 105:70]
-  wire [31:0] _state3_0_norm_clz_T_41 = _state3_0_norm_clz_T_39 & 32'hcccccccc; // @[Bitwise.scala 105:80]
-  wire [31:0] _state3_0_norm_clz_T_42 = _state3_0_norm_clz_T_37 | _state3_0_norm_clz_T_41; // @[Bitwise.scala 105:39]
-  wire [31:0] _GEN_75 = {{1'd0}, _state3_0_norm_clz_T_42[31:1]}; // @[Bitwise.scala 105:31]
-  wire [31:0] _state3_0_norm_clz_T_47 = _GEN_75 & 32'h55555555; // @[Bitwise.scala 105:31]
-  wire [31:0] _state3_0_norm_clz_T_49 = {_state3_0_norm_clz_T_42[30:0], 1'h0}; // @[Bitwise.scala 105:70]
-  wire [31:0] _state3_0_norm_clz_T_51 = _state3_0_norm_clz_T_49 & 32'haaaaaaaa; // @[Bitwise.scala 105:80]
-  wire [31:0] _state3_0_norm_clz_T_52 = _state3_0_norm_clz_T_47 | _state3_0_norm_clz_T_51; // @[Bitwise.scala 105:39]
-  wire [15:0] _GEN_76 = {{8'd0}, state3_0_result_man[47:40]}; // @[Bitwise.scala 105:31]
-  wire [15:0] _state3_0_norm_clz_T_58 = _GEN_76 & 16'hff; // @[Bitwise.scala 105:31]
-  wire [15:0] _state3_0_norm_clz_T_60 = {state3_0_result_man[39:32], 8'h0}; // @[Bitwise.scala 105:70]
-  wire [15:0] _state3_0_norm_clz_T_62 = _state3_0_norm_clz_T_60 & 16'hff00; // @[Bitwise.scala 105:80]
-  wire [15:0] _state3_0_norm_clz_T_63 = _state3_0_norm_clz_T_58 | _state3_0_norm_clz_T_62; // @[Bitwise.scala 105:39]
-  wire [15:0] _GEN_77 = {{4'd0}, _state3_0_norm_clz_T_63[15:4]}; // @[Bitwise.scala 105:31]
-  wire [15:0] _state3_0_norm_clz_T_68 = _GEN_77 & 16'hf0f; // @[Bitwise.scala 105:31]
-  wire [15:0] _state3_0_norm_clz_T_70 = {_state3_0_norm_clz_T_63[11:0], 4'h0}; // @[Bitwise.scala 105:70]
-  wire [15:0] _state3_0_norm_clz_T_72 = _state3_0_norm_clz_T_70 & 16'hf0f0; // @[Bitwise.scala 105:80]
-  wire [15:0] _state3_0_norm_clz_T_73 = _state3_0_norm_clz_T_68 | _state3_0_norm_clz_T_72; // @[Bitwise.scala 105:39]
-  wire [15:0] _GEN_78 = {{2'd0}, _state3_0_norm_clz_T_73[15:2]}; // @[Bitwise.scala 105:31]
-  wire [15:0] _state3_0_norm_clz_T_78 = _GEN_78 & 16'h3333; // @[Bitwise.scala 105:31]
-  wire [15:0] _state3_0_norm_clz_T_80 = {_state3_0_norm_clz_T_73[13:0], 2'h0}; // @[Bitwise.scala 105:70]
-  wire [15:0] _state3_0_norm_clz_T_82 = _state3_0_norm_clz_T_80 & 16'hcccc; // @[Bitwise.scala 105:80]
-  wire [15:0] _state3_0_norm_clz_T_83 = _state3_0_norm_clz_T_78 | _state3_0_norm_clz_T_82; // @[Bitwise.scala 105:39]
-  wire [15:0] _GEN_79 = {{1'd0}, _state3_0_norm_clz_T_83[15:1]}; // @[Bitwise.scala 105:31]
-  wire [15:0] _state3_0_norm_clz_T_88 = _GEN_79 & 16'h5555; // @[Bitwise.scala 105:31]
-  wire [15:0] _state3_0_norm_clz_T_90 = {_state3_0_norm_clz_T_83[14:0], 1'h0}; // @[Bitwise.scala 105:70]
-  wire [15:0] _state3_0_norm_clz_T_92 = _state3_0_norm_clz_T_90 & 16'haaaa; // @[Bitwise.scala 105:80]
-  wire [15:0] _state3_0_norm_clz_T_93 = _state3_0_norm_clz_T_88 | _state3_0_norm_clz_T_92; // @[Bitwise.scala 105:39]
-  wire [48:0] _state3_0_norm_clz_T_96 = {_state3_0_norm_clz_T_52,_state3_0_norm_clz_T_93,state3_0_result_man[48]}; // @[Cat.scala 31:58]
-  wire [5:0] _state3_0_norm_clz_T_146 = _state3_0_norm_clz_T_96[47] ? 6'h2f : 6'h30; // @[Mux.scala 47:70]
-  wire [5:0] _state3_0_norm_clz_T_147 = _state3_0_norm_clz_T_96[46] ? 6'h2e : _state3_0_norm_clz_T_146; // @[Mux.scala 47:70]
-  wire [5:0] _state3_0_norm_clz_T_148 = _state3_0_norm_clz_T_96[45] ? 6'h2d : _state3_0_norm_clz_T_147; // @[Mux.scala 47:70]
-  wire [5:0] _state3_0_norm_clz_T_149 = _state3_0_norm_clz_T_96[44] ? 6'h2c : _state3_0_norm_clz_T_148; // @[Mux.scala 47:70]
-  wire [5:0] _state3_0_norm_clz_T_150 = _state3_0_norm_clz_T_96[43] ? 6'h2b : _state3_0_norm_clz_T_149; // @[Mux.scala 47:70]
-  wire [5:0] _state3_0_norm_clz_T_151 = _state3_0_norm_clz_T_96[42] ? 6'h2a : _state3_0_norm_clz_T_150; // @[Mux.scala 47:70]
-  wire [5:0] _state3_0_norm_clz_T_152 = _state3_0_norm_clz_T_96[41] ? 6'h29 : _state3_0_norm_clz_T_151; // @[Mux.scala 47:70]
-  wire [5:0] _state3_0_norm_clz_T_153 = _state3_0_norm_clz_T_96[40] ? 6'h28 : _state3_0_norm_clz_T_152; // @[Mux.scala 47:70]
-  wire [5:0] _state3_0_norm_clz_T_154 = _state3_0_norm_clz_T_96[39] ? 6'h27 : _state3_0_norm_clz_T_153; // @[Mux.scala 47:70]
-  wire [5:0] _state3_0_norm_clz_T_155 = _state3_0_norm_clz_T_96[38] ? 6'h26 : _state3_0_norm_clz_T_154; // @[Mux.scala 47:70]
-  wire [5:0] _state3_0_norm_clz_T_156 = _state3_0_norm_clz_T_96[37] ? 6'h25 : _state3_0_norm_clz_T_155; // @[Mux.scala 47:70]
-  wire [5:0] _state3_0_norm_clz_T_157 = _state3_0_norm_clz_T_96[36] ? 6'h24 : _state3_0_norm_clz_T_156; // @[Mux.scala 47:70]
-  wire [5:0] _state3_0_norm_clz_T_158 = _state3_0_norm_clz_T_96[35] ? 6'h23 : _state3_0_norm_clz_T_157; // @[Mux.scala 47:70]
-  wire [5:0] _state3_0_norm_clz_T_159 = _state3_0_norm_clz_T_96[34] ? 6'h22 : _state3_0_norm_clz_T_158; // @[Mux.scala 47:70]
-  wire [5:0] _state3_0_norm_clz_T_160 = _state3_0_norm_clz_T_96[33] ? 6'h21 : _state3_0_norm_clz_T_159; // @[Mux.scala 47:70]
-  wire [5:0] _state3_0_norm_clz_T_161 = _state3_0_norm_clz_T_96[32] ? 6'h20 : _state3_0_norm_clz_T_160; // @[Mux.scala 47:70]
-  wire [5:0] _state3_0_norm_clz_T_162 = _state3_0_norm_clz_T_96[31] ? 6'h1f : _state3_0_norm_clz_T_161; // @[Mux.scala 47:70]
-  wire [5:0] _state3_0_norm_clz_T_163 = _state3_0_norm_clz_T_96[30] ? 6'h1e : _state3_0_norm_clz_T_162; // @[Mux.scala 47:70]
-  wire [5:0] _state3_0_norm_clz_T_164 = _state3_0_norm_clz_T_96[29] ? 6'h1d : _state3_0_norm_clz_T_163; // @[Mux.scala 47:70]
-  wire [5:0] _state3_0_norm_clz_T_165 = _state3_0_norm_clz_T_96[28] ? 6'h1c : _state3_0_norm_clz_T_164; // @[Mux.scala 47:70]
-  wire [5:0] _state3_0_norm_clz_T_166 = _state3_0_norm_clz_T_96[27] ? 6'h1b : _state3_0_norm_clz_T_165; // @[Mux.scala 47:70]
-  wire [5:0] _state3_0_norm_clz_T_167 = _state3_0_norm_clz_T_96[26] ? 6'h1a : _state3_0_norm_clz_T_166; // @[Mux.scala 47:70]
-  wire [5:0] _state3_0_norm_clz_T_168 = _state3_0_norm_clz_T_96[25] ? 6'h19 : _state3_0_norm_clz_T_167; // @[Mux.scala 47:70]
-  wire [5:0] _state3_0_norm_clz_T_169 = _state3_0_norm_clz_T_96[24] ? 6'h18 : _state3_0_norm_clz_T_168; // @[Mux.scala 47:70]
-  wire [5:0] _state3_0_norm_clz_T_170 = _state3_0_norm_clz_T_96[23] ? 6'h17 : _state3_0_norm_clz_T_169; // @[Mux.scala 47:70]
-  wire [5:0] _state3_0_norm_clz_T_171 = _state3_0_norm_clz_T_96[22] ? 6'h16 : _state3_0_norm_clz_T_170; // @[Mux.scala 47:70]
-  wire [5:0] _state3_0_norm_clz_T_172 = _state3_0_norm_clz_T_96[21] ? 6'h15 : _state3_0_norm_clz_T_171; // @[Mux.scala 47:70]
-  wire [5:0] _state3_0_norm_clz_T_173 = _state3_0_norm_clz_T_96[20] ? 6'h14 : _state3_0_norm_clz_T_172; // @[Mux.scala 47:70]
-  wire [5:0] _state3_0_norm_clz_T_174 = _state3_0_norm_clz_T_96[19] ? 6'h13 : _state3_0_norm_clz_T_173; // @[Mux.scala 47:70]
-  wire [5:0] _state3_0_norm_clz_T_175 = _state3_0_norm_clz_T_96[18] ? 6'h12 : _state3_0_norm_clz_T_174; // @[Mux.scala 47:70]
-  wire [5:0] _state3_0_norm_clz_T_176 = _state3_0_norm_clz_T_96[17] ? 6'h11 : _state3_0_norm_clz_T_175; // @[Mux.scala 47:70]
-  wire [5:0] _state3_0_norm_clz_T_177 = _state3_0_norm_clz_T_96[16] ? 6'h10 : _state3_0_norm_clz_T_176; // @[Mux.scala 47:70]
-  wire [5:0] _state3_0_norm_clz_T_178 = _state3_0_norm_clz_T_96[15] ? 6'hf : _state3_0_norm_clz_T_177; // @[Mux.scala 47:70]
-  wire [5:0] _state3_0_norm_clz_T_179 = _state3_0_norm_clz_T_96[14] ? 6'he : _state3_0_norm_clz_T_178; // @[Mux.scala 47:70]
-  wire [5:0] _state3_0_norm_clz_T_180 = _state3_0_norm_clz_T_96[13] ? 6'hd : _state3_0_norm_clz_T_179; // @[Mux.scala 47:70]
-  wire [5:0] _state3_0_norm_clz_T_181 = _state3_0_norm_clz_T_96[12] ? 6'hc : _state3_0_norm_clz_T_180; // @[Mux.scala 47:70]
-  wire [5:0] _state3_0_norm_clz_T_182 = _state3_0_norm_clz_T_96[11] ? 6'hb : _state3_0_norm_clz_T_181; // @[Mux.scala 47:70]
-  wire [5:0] _state3_0_norm_clz_T_183 = _state3_0_norm_clz_T_96[10] ? 6'ha : _state3_0_norm_clz_T_182; // @[Mux.scala 47:70]
-  wire [5:0] _state3_0_norm_clz_T_184 = _state3_0_norm_clz_T_96[9] ? 6'h9 : _state3_0_norm_clz_T_183; // @[Mux.scala 47:70]
-  wire [5:0] _state3_0_norm_clz_T_185 = _state3_0_norm_clz_T_96[8] ? 6'h8 : _state3_0_norm_clz_T_184; // @[Mux.scala 47:70]
-  wire [5:0] _state3_0_norm_clz_T_186 = _state3_0_norm_clz_T_96[7] ? 6'h7 : _state3_0_norm_clz_T_185; // @[Mux.scala 47:70]
-  wire [5:0] _state3_0_norm_clz_T_187 = _state3_0_norm_clz_T_96[6] ? 6'h6 : _state3_0_norm_clz_T_186; // @[Mux.scala 47:70]
-  wire [5:0] _state3_0_norm_clz_T_188 = _state3_0_norm_clz_T_96[5] ? 6'h5 : _state3_0_norm_clz_T_187; // @[Mux.scala 47:70]
-  wire [5:0] _state3_0_norm_clz_T_189 = _state3_0_norm_clz_T_96[4] ? 6'h4 : _state3_0_norm_clz_T_188; // @[Mux.scala 47:70]
-  wire [5:0] _state3_0_norm_clz_T_190 = _state3_0_norm_clz_T_96[3] ? 6'h3 : _state3_0_norm_clz_T_189; // @[Mux.scala 47:70]
-  wire [5:0] _state3_0_norm_clz_T_191 = _state3_0_norm_clz_T_96[2] ? 6'h2 : _state3_0_norm_clz_T_190; // @[Mux.scala 47:70]
-  wire [5:0] _state3_0_norm_clz_T_192 = _state3_0_norm_clz_T_96[1] ? 6'h1 : _state3_0_norm_clz_T_191; // @[Mux.scala 47:70]
-  wire [5:0] _state3_0_norm_clz_T_193 = _state3_0_norm_clz_T_96[0] ? 6'h0 : _state3_0_norm_clz_T_192; // @[Mux.scala 47:70]
-  wire [9:0] state3_0_norm_clz = state3_0_result_man[49] ? 10'h3ff : {{4'd0}, _state3_0_norm_clz_T_193}; // @[FMAdd.scala 386:23]
-  wire [9:0] _state3_0_result_exp_s_T_1 = state2_0_exp - state3_0_norm_clz; // @[FMAdd.scala 391:35]
-  wire [9:0] state3_0_result_exp_s = _state3_0_result_exp_s_T_1 + 10'h1; // @[FMAdd.scala 391:46]
-  wire [8:0] state3_0_result_exp = state3_0_result_exp_s[9] ? 9'h0 : state3_0_result_exp_s[8:0]; // @[FMAdd.scala 394:25]
-  wire  state3_0_result_inf = state3_0_result_exp >= 9'hff; // @[FMAdd.scala 395:33]
-  wire [7:0] state3_0_result_inf_exp = state3_0_result_inf ? 8'hff : 8'h0; // @[FMAdd.scala 396:29]
-  wire [9:0] state3_0_result_shl_amt = state2_0_exp < state3_0_norm_clz ? state2_0_exp : state3_0_norm_clz; // @[FMAdd.scala 451:8]
-  wire [21:0] state3_0_shl_mask = 22'h3fffff >> state3_0_result_shl_amt; // @[FMAdd.scala 401:33]
-  wire [1072:0] _GEN_2 = {{1023'd0}, state3_0_result_man}; // @[FMAdd.scala 404:42]
-  wire [1072:0] _state3_0_result_shl_man_grs_T = _GEN_2 << state3_0_result_shl_amt; // @[FMAdd.scala 404:42]
-  wire [21:0] _state3_0_result_shl_man_grs_T_3 = state3_0_result_man[21:0] & state3_0_shl_mask; // @[FMAdd.scala 405:49]
-  wire  _state3_0_result_shl_man_grs_T_4 = _state3_0_result_shl_man_grs_T_3 != 22'h0; // @[FMAdd.scala 405:61]
-  wire [26:0] _GEN_80 = {{26'd0}, _state3_0_result_shl_man_grs_T_4}; // @[FMAdd.scala 404:68]
-  wire [26:0] state3_0_result_shl_man_grs = _state3_0_result_shl_man_grs_T[48:22] | _GEN_80; // @[FMAdd.scala 404:68]
-  wire  _state3_0_shl_round_round_T_1 = state3_0_result_shl_man_grs[2:0] != 3'h0; // @[FBase.scala 82:30]
-  wire  _state3_0_shl_round_round_T_2 = state3_0_result_shl_man_grs[2:0] != 3'h0 & state2_0_sign; // @[FBase.scala 82:38]
-  wire  _state3_0_shl_round_round_T_6 = _state3_0_shl_round_round_T_1 & ~state2_0_sign; // @[FBase.scala 83:38]
-  wire  _state3_0_shl_round_round_T_11 = state3_0_result_shl_man_grs[2:0] > 3'h4 | state3_0_result_shl_man_grs[3:0] == 4'hc
-    ; // @[FBase.scala 85:36]
-  wire [3:0] state3_0_shl_round_round = {_state3_0_shl_round_round_T_2,_state3_0_shl_round_round_T_6,1'h0,
-    _state3_0_shl_round_round_T_11}; // @[Cat.scala 31:58]
-  wire  state3_0_shl_round = state3_0_shl_round_round[0]; // @[FBase.scala 86:10]
-  wire [23:0] _state3_0_result_shl_man_T_2 = state3_0_result_shl_man_grs[26:3] + 24'h1; // @[FMAdd.scala 409:66]
-  wire [23:0] state3_0_result_shl_man = state3_0_shl_round ? _state3_0_result_shl_man_T_2 : state3_0_result_shl_man_grs[
-    26:3]; // @[FMAdd.scala 409:29]
-  wire [8:0] _state3_0_result_shl_exp_T_5 = state3_0_result_exp + 9'h1; // @[FMAdd.scala 411:41]
-  wire [8:0] state3_0_result_shl_exp = state3_0_shl_round & state3_0_result_shl_man_grs[26:3] == 24'hffffff ?
-    _state3_0_result_shl_exp_T_5 : state3_0_result_exp; // @[FMAdd.scala 410:29]
-  wire [9:0] _state3_0_result_shr_amt_T_1 = 10'h0 - state2_0_exp; // @[FMAdd.scala 414:42]
-  wire [9:0] _state3_0_result_shr_amt_T_3 = 10'h0 - state3_0_norm_clz; // @[FMAdd.scala 414:53]
-  wire [9:0] _state3_0_result_shr_amt_T_4 = 10'h0 - state2_0_exp; // @[FMAdd.scala 455:11]
-  wire [9:0] _state3_0_result_shr_amt_T_5 = 10'h0 - state3_0_norm_clz; // @[FMAdd.scala 455:22]
-  wire [9:0] _state3_0_result_shr_amt_T_7 = $signed(_state3_0_result_shr_amt_T_4) > $signed(_state3_0_result_shr_amt_T_5
-    ) ? _state3_0_result_shr_amt_T_1 : _state3_0_result_shr_amt_T_3; // @[FMAdd.scala 455:8]
-  wire [9:0] state3_0_result_shr_amt = 10'h1b < _state3_0_result_shr_amt_T_7 ? 10'h1b : _state3_0_result_shr_amt_T_7; // @[FMAdd.scala 451:8]
-  wire [1072:0] _state3_0_shr_mask_T_2 = 1073'h3ffffffc00000 << state3_0_result_shr_amt; // @[FMAdd.scala 415:50]
-  wire [49:0] state3_0_shr_mask = ~_state3_0_shr_mask_T_2[49:0]; // @[FMAdd.scala 415:20]
-  wire [27:0] _state3_0_result_shr_man_grs_T_1 = state3_0_result_man[49:22] >> state3_0_result_shr_amt; // @[FMAdd.scala 418:49]
-  wire [49:0] _state3_0_result_shr_man_grs_T_4 = state3_0_result_man & state3_0_shr_mask; // @[FMAdd.scala 419:49]
-  wire  _state3_0_result_shr_man_grs_T_5 = _state3_0_result_shr_man_grs_T_4 != 50'h0; // @[FMAdd.scala 419:61]
-  wire [26:0] _GEN_81 = {{26'd0}, _state3_0_result_shr_man_grs_T_5}; // @[FMAdd.scala 418:74]
-  wire [26:0] state3_0_result_shr_man_grs = _state3_0_result_shr_man_grs_T_1[26:0] | _GEN_81; // @[FMAdd.scala 418:74]
-  wire  _state3_0_shr_round_round_T_1 = state3_0_result_shr_man_grs[2:0] != 3'h0; // @[FBase.scala 82:30]
-  wire  _state3_0_shr_round_round_T_2 = state3_0_result_shr_man_grs[2:0] != 3'h0 & state2_0_sign; // @[FBase.scala 82:38]
-  wire  _state3_0_shr_round_round_T_6 = _state3_0_shr_round_round_T_1 & ~state2_0_sign; // @[FBase.scala 83:38]
-  wire  _state3_0_shr_round_round_T_11 = state3_0_result_shr_man_grs[2:0] > 3'h4 | state3_0_result_shr_man_grs[3:0] == 4'hc
-    ; // @[FBase.scala 85:36]
-  wire [3:0] state3_0_shr_round_round = {_state3_0_shr_round_round_T_2,_state3_0_shr_round_round_T_6,1'h0,
-    _state3_0_shr_round_round_T_11}; // @[Cat.scala 31:58]
-  wire  state3_0_shr_round = state3_0_shr_round_round[0]; // @[FBase.scala 86:10]
-  wire [24:0] _state3_0_result_shr_man_T_1 = state3_0_result_shr_man_grs[26:3] + 24'h1; // @[FMAdd.scala 423:66]
-  wire [24:0] state3_0_result_shr_man = state3_0_shr_round ? _state3_0_result_shr_man_T_1 : {{1'd0},
-    state3_0_result_shr_man_grs[26:3]}; // @[FMAdd.scala 423:29]
-  wire  _state3_0_result_shr_exp_T_2 = state3_0_result_shr_man_grs[25:3] == 23'h7fffff; // @[FMAdd.scala 425:55]
-  wire  _state3_0_result_shr_exp_T_3 = state3_0_shr_round & _state3_0_result_shr_exp_T_2; // @[FMAdd.scala 424:40]
-  wire  _state3_0_result_shr_exp_T_6 = state3_0_result_shr_man_grs[26] | state3_0_result_exp == 9'h0; // @[FMAdd.scala 426:54]
-  wire  _state3_0_result_shr_exp_T_7 = _state3_0_result_shr_exp_T_3 & _state3_0_result_shr_exp_T_6; // @[FMAdd.scala 425:70]
-  wire [8:0] state3_0_result_shr_exp = _state3_0_result_shr_exp_T_7 ? _state3_0_result_shl_exp_T_5 : state3_0_result_exp
-    ; // @[FMAdd.scala 424:29]
-  wire  state3_0_sel_gez = ~state2_0_exp[9] & ~state3_0_norm_clz[9]; // @[FMAdd.scala 430:32]
-  wire  _state3_0_sel_shl_T = ~state2_0_sel; // @[FMAdd.scala 431:19]
-  wire  _state3_0_sel_shl_T_2 = state3_0_result_man != 50'h0; // @[FMAdd.scala 431:54]
-  wire  state3_0_sel_shl = ~state2_0_sel & state3_0_sel_gez & state3_0_result_man != 50'h0; // @[FMAdd.scala 431:40]
-  wire  state3_0_sel_shr = _state3_0_sel_shl_T & ~state3_0_sel_gez & _state3_0_sel_shl_T_2; // @[FMAdd.scala 432:40]
-  wire [2:0] _state3_0_T_12 = {state2_0_sel,state3_0_sel_shl,state3_0_sel_shr}; // @[Cat.scala 31:58]
-  wire [1:0] _state3_0_T_16 = _state3_0_T_12[1] + _state3_0_T_12[2]; // @[Bitwise.scala 48:55]
-  wire [1:0] _GEN_82 = {{1'd0}, _state3_0_T_12[0]}; // @[Bitwise.scala 48:55]
-  wire [2:0] _state3_0_T_18 = _GEN_82 + _state3_0_T_16; // @[Bitwise.scala 48:55]
-  wire [9:0] _state3_0_state3_exp_T = state2_0_sel ? state2_0_exp : 10'h0; // @[FMAdd.scala 436:22]
-  wire [8:0] _GEN_83 = {{1'd0}, state3_0_result_inf_exp}; // @[FMAdd.scala 437:47]
-  wire [8:0] _state3_0_state3_exp_T_1 = state3_0_result_shl_exp | _GEN_83; // @[FMAdd.scala 437:47]
-  wire [8:0] _state3_0_state3_exp_T_2 = state3_0_sel_shl ? _state3_0_state3_exp_T_1 : 9'h0; // @[FMAdd.scala 437:22]
-  wire [9:0] _GEN_84 = {{1'd0}, _state3_0_state3_exp_T_2}; // @[FMAdd.scala 436:49]
-  wire [9:0] _state3_0_state3_exp_T_3 = _state3_0_state3_exp_T | _GEN_84; // @[FMAdd.scala 436:49]
-  wire [8:0] _state3_0_state3_exp_T_4 = state3_0_result_shr_exp | _GEN_83; // @[FMAdd.scala 438:47]
-  wire [8:0] _state3_0_state3_exp_T_5 = state3_0_sel_shr ? _state3_0_state3_exp_T_4 : 9'h0; // @[FMAdd.scala 438:22]
-  wire [9:0] _GEN_86 = {{1'd0}, _state3_0_state3_exp_T_5}; // @[FMAdd.scala 437:70]
-  wire [9:0] _state3_0_state3_exp_T_6 = _state3_0_state3_exp_T_3 | _GEN_86; // @[FMAdd.scala 437:70]
-  wire  _state3_0_state3_man_T_1 = ~state3_0_result_inf; // @[FMAdd.scala 440:34]
-  wire [23:0] _state3_0_state3_man_T_3 = state3_0_sel_shl & ~state3_0_result_inf ? state3_0_result_shl_man : 24'h0; // @[FMAdd.scala 440:22]
-  wire [48:0] _GEN_87 = {{25'd0}, _state3_0_state3_man_T_3}; // @[FMAdd.scala 439:49]
-  wire [48:0] _state3_0_state3_man_T_4 = _state3_0_result_man_T | _GEN_87; // @[FMAdd.scala 439:49]
-  wire [24:0] _state3_0_state3_man_T_7 = state3_0_sel_shr & _state3_0_state3_man_T_1 ? state3_0_result_shr_man : 25'h0; // @[FMAdd.scala 441:22]
-  wire [48:0] _GEN_88 = {{24'd0}, _state3_0_state3_man_T_7}; // @[FMAdd.scala 440:68]
-  wire [48:0] _state3_0_state3_man_T_8 = _state3_0_state3_man_T_4 | _GEN_88; // @[FMAdd.scala 440:68]
-  wire [22:0] state3_0_state3_man = _state3_0_state3_man_T_8[22:0]; // @[FMAdd.scala 367:22 439:16]
-  wire [7:0] state3_0_state3_exp = _state3_0_state3_exp_T_6[7:0]; // @[FMAdd.scala 367:22 436:16]
-  wire  _io_ina_ready_T_2 = _update1_T_3 | io_inc_valid & io_inc_ready; // @[FMAdd.scala 96:45]
-  wire [8:0] io_out_bits_0_hi = {state3_0_sign,state3_0_exp}; // @[Cat.scala 31:58]
-  wire  _GEN_89 = active2 & ~reset; // @[FMAdd.scala 382:11]
-  assign io_ina_ready = io_inb_valid & (_update1_T_3 | io_inc_valid & io_inc_ready); // @[FMAdd.scala 96:32]
-  assign io_inb_ready = io_ina_valid & _io_ina_ready_T_2; // @[FMAdd.scala 97:32]
-  assign io_inc_ready = active1; // @[FMAdd.scala 98:27]
-  assign io_out_valid = active3; // @[FMAdd.scala 100:16]
-  assign io_out_bits_0 = {io_out_bits_0_hi,state3_0_man}; // @[Cat.scala 31:58]
-  always @(posedge clock) begin
-    if (update1) begin // @[FMAdd.scala 57:18]
-      op1 <= io_op_bits; // @[FMAdd.scala 58:9]
-    end
-    if (update1) begin // @[FMAdd.scala 79:20]
-      if (state1_0_nan_a) begin // @[FMAdd.scala 187:24]
-        state1__0_sign <= state1_0_sign_a;
-      end else if (state1_0_nan_b) begin // @[FMAdd.scala 187:43]
-        state1__0_sign <= state1_0_sign_b;
-      end else begin
-        state1__0_sign <= state1_0_sign;
-      end
-    end
-    if (update1) begin // @[FMAdd.scala 79:20]
-      if (state1_0_nan_a) begin // @[FMAdd.scala 188:24]
-        state1__0_exp <= {{2'd0}, mul_sina[30:23]};
-      end else if (state1_0_nan_b) begin // @[FMAdd.scala 188:42]
-        state1__0_exp <= {{2'd0}, mul_sina[30:23]};
-      end else if (~state1_0_zero) begin // @[FMAdd.scala 181:20]
-        state1__0_exp <= state1_0_exp;
-      end else begin
-        state1__0_exp <= 10'h0;
-      end
-    end
-    if (update1) begin // @[FMAdd.scala 79:20]
-      if (state1_0_nan_a) begin // @[FMAdd.scala 189:24]
-        state1__0_mul <= {{25'd0}, mul_sina[22:0]};
-      end else if (state1_0_nan_b) begin // @[FMAdd.scala 189:42]
-        state1__0_mul <= {{25'd0}, mul_inb[22:0]};
-      end else if (_state1_0_exp_z_T) begin // @[FMAdd.scala 182:20]
-        state1__0_mul <= state1_0_mul;
-      end else begin
-        state1__0_mul <= 48'h0;
-      end
-    end
-    if (update1) begin // @[FMAdd.scala 79:20]
-      state1__0_zero <= state1_0_zero; // @[FMAdd.scala 81:11]
-    end
-    if (update1) begin // @[FMAdd.scala 79:20]
-      state1__0_inf_a <= state1_0_inf_a; // @[FMAdd.scala 81:11]
-    end
-    if (update1) begin // @[FMAdd.scala 79:20]
-      state1__0_inf_b <= state1_0_inf_b; // @[FMAdd.scala 81:11]
-    end
-    if (update1) begin // @[FMAdd.scala 79:20]
-      state1__0_nan <= state1_0_state1_nan; // @[FMAdd.scala 81:11]
-    end
-    if (update2) begin // @[FMAdd.scala 84:20]
-      if (state2_0_sp_state_sel) begin // @[FMAdd.scala 259:21]
-        if (state1__0_nan | state2_0_sp_state_c_nan) begin // @[FMAdd.scala 290:32]
-          state2_0_sign <= 1'h0; // @[FMAdd.scala 291:19]
-        end else if ((state1__0_inf_a | state1__0_inf_b) & state2_0_sp_state_c_inf & state1__0_sign != state2_0_acm_sign
-          ) begin // @[FMAdd.scala 295:85]
-          state2_0_sign <= 1'h0; // @[FMAdd.scala 296:19]
-        end else begin
-          state2_0_sign <= _GEN_25;
-        end
-      end else if (state2_0_sel_ab) begin // @[FMAdd.scala 259:43]
-        state2_0_sign <= state1__0_sign;
-      end else begin
-        state2_0_sign <= state2_0_acm_sign;
-      end
-    end
-    if (update2) begin // @[FMAdd.scala 84:20]
-      if (state2_0_sp_state_sel) begin // @[FMAdd.scala 259:21]
-        state2_0_exp <= state2_0_sp_state_exp;
-      end else if (state2_0_sel_ab) begin // @[FMAdd.scala 259:43]
-        state2_0_exp <= state2_0_a_exp;
-      end else begin
-        state2_0_exp <= state2_0_b_exp;
-      end
-    end
-    if (update2) begin // @[FMAdd.scala 84:20]
-      if (state2_0_sp_state_sel) begin // @[FMAdd.scala 259:21]
-        state2_0_ain <= state2_0_sp_state_ain;
-      end else if (state2_0_sel_ab) begin // @[FMAdd.scala 259:43]
-        state2_0_ain <= state2_0_ab_state_a_shbits;
-      end else begin
-        state2_0_ain <= _state2_0_ab_state_b_shbits_T;
-      end
-    end
-    if (update2) begin // @[FMAdd.scala 84:20]
-      if (state2_0_sp_state_sel) begin // @[FMAdd.scala 259:21]
-        state2_0_bin <= 49'h0;
-      end else if (state2_0_sel_ab) begin // @[FMAdd.scala 259:43]
-        state2_0_bin <= state2_0_ab_state_b_shbits;
-      end else begin
-        state2_0_bin <= state2_0_ba_state_b_shbits;
-      end
-    end
-    if (update2) begin // @[FMAdd.scala 84:20]
-      state2_0_sel <= state2_0_sp_state_sel; // @[FMAdd.scala 87:11]
-    end
-    if (update2) begin // @[FMAdd.scala 84:20]
-      if (state2_0_sp_state_sel) begin // @[FMAdd.scala 259:21]
-        state2_0_add <= 1'h0;
-      end else if (state2_0_sel_ab) begin // @[FMAdd.scala 259:43]
-        state2_0_add <= state2_0_ab_state_add;
-      end else begin
-        state2_0_add <= state2_0_ba_state_add;
-      end
-    end
-    if (update2) begin // @[FMAdd.scala 84:20]
-      if (state2_0_sp_state_sel) begin // @[FMAdd.scala 259:21]
-        state2_0_sub <= 1'h0;
-      end else if (state2_0_sel_ab) begin // @[FMAdd.scala 259:43]
-        state2_0_sub <= _state2_0_sp_state_T_3;
-      end else begin
-        state2_0_sub <= state2_0_ba_state_sub;
-      end
-    end
-    if (active2) begin // @[FMAdd.scala 90:20]
-      state3_0_sign <= state2_0_sign; // @[FMAdd.scala 91:11]
-    end
-    if (active2) begin // @[FMAdd.scala 90:20]
-      state3_0_exp <= state3_0_state3_exp; // @[FMAdd.scala 91:11]
-    end
-    if (active2) begin // @[FMAdd.scala 90:20]
-      state3_0_man <= state3_0_state3_man; // @[FMAdd.scala 91:11]
-    end
-    `ifndef SYNTHESIS
-    `ifdef STOP_COND
-      if (`STOP_COND) begin
-    `endif
-        if (active2 & ~reset & ~(_state3_0_T_6[1:0] <= 2'h1)) begin
-          $fatal; // @[FMAdd.scala 382:11]
-        end
-    `ifdef STOP_COND
-      end
-    `endif
-    `endif // SYNTHESIS
-    `ifndef SYNTHESIS
-    `ifdef PRINTF_COND
-      if (`PRINTF_COND) begin
-    `endif
-        if (active2 & ~reset & ~(_state3_0_T_6[1:0] <= 2'h1)) begin
-          $fwrite(32'h80000002,
-            "Assertion failed\n    at FMAdd.scala:382 assert(PopCount(Cat(state2.sel, state2.add, state2.sub)) <= 1.U)\n"
-            ); // @[FMAdd.scala 382:11]
-        end
-    `ifdef PRINTF_COND
-      end
-    `endif
-    `endif // SYNTHESIS
-    `ifndef SYNTHESIS
-    `ifdef STOP_COND
-      if (`STOP_COND) begin
-    `endif
-        if (_GEN_89 & ~(_state3_0_T_18[1:0] <= 2'h1)) begin
-          $fatal; // @[FMAdd.scala 433:11]
-        end
-    `ifdef STOP_COND
-      end
-    `endif
-    `endif // SYNTHESIS
-    `ifndef SYNTHESIS
-    `ifdef PRINTF_COND
-      if (`PRINTF_COND) begin
-    `endif
-        if (_GEN_89 & ~(_state3_0_T_18[1:0] <= 2'h1)) begin
-          $fwrite(32'h80000002,
-            "Assertion failed\n    at FMAdd.scala:433 assert(PopCount(Cat(sel_ain, sel_shl, sel_shr)) <= 1.U)\n"); // @[FMAdd.scala 433:11]
-        end
-    `ifdef PRINTF_COND
-      end
-    `endif
-    `endif // SYNTHESIS
-  end
-  always @(posedge clock or posedge reset) begin
-    if (reset) begin // @[FMAdd.scala 45:29]
-      active1 <= 1'h0; // @[FMAdd.scala 46:13]
-    end else if (update1 | update2) begin // @[FMAdd.scala 32:24]
-      active1 <= update1;
-    end
-  end
-  always @(posedge clock or posedge reset) begin
-    if (reset) begin // @[FMAdd.scala 49:29]
-      active2 <= 1'h0; // @[FMAdd.scala 50:13]
-    end else if (update2 | active2) begin // @[FMAdd.scala 33:24]
-      active2 <= update2;
-    end
-  end
-  always @(posedge clock or posedge reset) begin
-    if (reset) begin // @[FMAdd.scala 53:34]
-      active3 <= 1'h0; // @[FMAdd.scala 54:13]
-    end else begin
-      active3 <= active2; // @[FMAdd.scala 34:24]
-    end
-  end
-// Register and memory initialization
-`ifdef RANDOMIZE_GARBAGE_ASSIGN
-`define RANDOMIZE
-`endif
-`ifdef RANDOMIZE_INVALID_ASSIGN
-`define RANDOMIZE
-`endif
-`ifdef RANDOMIZE_REG_INIT
-`define RANDOMIZE
-`endif
-`ifdef RANDOMIZE_MEM_INIT
-`define RANDOMIZE
-`endif
-`ifndef RANDOM
-`define RANDOM $random
-`endif
-`ifdef RANDOMIZE_MEM_INIT
-  integer initvar;
-`endif
-`ifndef SYNTHESIS
-`ifdef FIRRTL_BEFORE_INITIAL
-`FIRRTL_BEFORE_INITIAL
-`endif
-initial begin
-  `ifdef RANDOMIZE
-    `ifdef INIT_RANDOM
-      `INIT_RANDOM
-    `endif
-    `ifndef VERILATOR
-      `ifdef RANDOMIZE_DELAY
-        #`RANDOMIZE_DELAY begin end
-      `else
-        #0.002 begin end
-      `endif
-    `endif
-`ifdef RANDOMIZE_REG_INIT
-  _RAND_0 = {1{`RANDOM}};
-  active1 = _RAND_0[0:0];
-  _RAND_1 = {1{`RANDOM}};
-  active2 = _RAND_1[0:0];
-  _RAND_2 = {1{`RANDOM}};
-  active3 = _RAND_2[0:0];
-  _RAND_3 = {1{`RANDOM}};
-  op1 = _RAND_3[3:0];
-  _RAND_4 = {1{`RANDOM}};
-  state1__0_sign = _RAND_4[0:0];
-  _RAND_5 = {1{`RANDOM}};
-  state1__0_exp = _RAND_5[9:0];
-  _RAND_6 = {2{`RANDOM}};
-  state1__0_mul = _RAND_6[47:0];
-  _RAND_7 = {1{`RANDOM}};
-  state1__0_zero = _RAND_7[0:0];
-  _RAND_8 = {1{`RANDOM}};
-  state1__0_inf_a = _RAND_8[0:0];
-  _RAND_9 = {1{`RANDOM}};
-  state1__0_inf_b = _RAND_9[0:0];
-  _RAND_10 = {1{`RANDOM}};
-  state1__0_nan = _RAND_10[0:0];
-  _RAND_11 = {1{`RANDOM}};
-  state2_0_sign = _RAND_11[0:0];
-  _RAND_12 = {1{`RANDOM}};
-  state2_0_exp = _RAND_12[9:0];
-  _RAND_13 = {2{`RANDOM}};
-  state2_0_ain = _RAND_13[48:0];
-  _RAND_14 = {2{`RANDOM}};
-  state2_0_bin = _RAND_14[48:0];
-  _RAND_15 = {1{`RANDOM}};
-  state2_0_sel = _RAND_15[0:0];
-  _RAND_16 = {1{`RANDOM}};
-  state2_0_add = _RAND_16[0:0];
-  _RAND_17 = {1{`RANDOM}};
-  state2_0_sub = _RAND_17[0:0];
-  _RAND_18 = {1{`RANDOM}};
-  state3_0_sign = _RAND_18[0:0];
-  _RAND_19 = {1{`RANDOM}};
-  state3_0_exp = _RAND_19[7:0];
-  _RAND_20 = {1{`RANDOM}};
-  state3_0_man = _RAND_20[22:0];
-`endif // RANDOMIZE_REG_INIT
-  if (reset) begin
-    active1 = 1'h0;
-  end
-  if (reset) begin
-    active2 = 1'h0;
-  end
-  if (reset) begin
-    active3 = 1'h0;
-  end
-  `endif // RANDOMIZE
-end // initial
-`ifdef FIRRTL_AFTER_INITIAL
-`FIRRTL_AFTER_INITIAL
-`endif
-`endif // SYNTHESIS
-endmodule
-module Slice_3(
-  input         clock,
-  input         reset,
-  output        io_in_ready,
-  input         io_in_valid,
-  input  [31:0] io_in_bits,
-  output        io_out_valid,
-  output [31:0] io_out_bits
-);
-`ifdef RANDOMIZE_REG_INIT
-  reg [31:0] _RAND_0;
-  reg [31:0] _RAND_1;
-  reg [31:0] _RAND_2;
-`endif // RANDOMIZE_REG_INIT
-  reg  ipos; // @[Slice.scala 24:21]
-  reg  opos; // @[Slice.scala 25:21]
-  reg [31:0] mem_0; // @[Slice.scala 27:16]
-  wire  empty = ipos == opos; // @[Slice.scala 29:20]
-  wire  ivalid = io_in_valid & io_in_ready; // @[Slice.scala 31:28]
-  assign io_in_ready = 1'h1; // @[Slice.scala 74:28]
-  assign io_out_valid = ~empty; // @[Slice.scala 88:21]
-  assign io_out_bits = mem_0; // @[Slice.scala 89:18]
-  always @(posedge clock) begin
-    if (ivalid) begin // @[Slice.scala 79:19]
-      mem_0 <= io_in_bits; // @[Slice.scala 80:14]
-    end
-  end
-  always @(posedge clock or posedge reset) begin
-    if (reset) begin // @[Slice.scala 34:17]
-      ipos <= 1'h0; // @[Slice.scala 35:10]
-    end else if (ivalid) begin // @[Slice.scala 24:21]
-      ipos <= ipos + 1'h1;
-    end
-  end
-  always @(posedge clock or posedge reset) begin
-    if (reset) begin // @[Slice.scala 38:17]
-      opos <= 1'h0; // @[Slice.scala 39:10]
-    end else if (io_out_valid) begin // @[Slice.scala 25:21]
-      opos <= opos + 1'h1;
-    end
-  end
-// Register and memory initialization
-`ifdef RANDOMIZE_GARBAGE_ASSIGN
-`define RANDOMIZE
-`endif
-`ifdef RANDOMIZE_INVALID_ASSIGN
-`define RANDOMIZE
-`endif
-`ifdef RANDOMIZE_REG_INIT
-`define RANDOMIZE
-`endif
-`ifdef RANDOMIZE_MEM_INIT
-`define RANDOMIZE
-`endif
-`ifndef RANDOM
-`define RANDOM $random
-`endif
-`ifdef RANDOMIZE_MEM_INIT
-  integer initvar;
-`endif
-`ifndef SYNTHESIS
-`ifdef FIRRTL_BEFORE_INITIAL
-`FIRRTL_BEFORE_INITIAL
-`endif
-initial begin
-  `ifdef RANDOMIZE
-    `ifdef INIT_RANDOM
-      `INIT_RANDOM
-    `endif
-    `ifndef VERILATOR
-      `ifdef RANDOMIZE_DELAY
-        #`RANDOMIZE_DELAY begin end
-      `else
-        #0.002 begin end
-      `endif
-    `endif
-`ifdef RANDOMIZE_REG_INIT
-  _RAND_0 = {1{`RANDOM}};
-  ipos = _RAND_0[0:0];
-  _RAND_1 = {1{`RANDOM}};
-  opos = _RAND_1[0:0];
-  _RAND_2 = {1{`RANDOM}};
-  mem_0 = _RAND_2[31:0];
-`endif // RANDOMIZE_REG_INIT
-  if (reset) begin
-    ipos = 1'h0;
-  end
-  if (reset) begin
-    opos = 1'h0;
-  end
-  `endif // RANDOMIZE
-end // initial
-`ifdef FIRRTL_AFTER_INITIAL
-`FIRRTL_AFTER_INITIAL
-`endif
-`endif // SYNTHESIS
-endmodule
-module FMAdd_1(
-  input         clock,
-  input         reset,
-  input         io_in_valid,
-  input  [4:0]  io_in_addr,
-  input  [31:0] io_in_fs1,
-  input  [31:0] io_in_fs2,
-  input  [31:0] io_in_fs3,
-  input  [26:0] io_in_op,
-  output        io_out_valid,
-  output [4:0]  io_out_addr,
-  output [31:0] io_out_fd
-);
-  wire  fmadd_clock; // @[FMAdd.scala 8:18]
-  wire  fmadd_reset; // @[FMAdd.scala 8:18]
-  wire  fmadd_io_op_valid; // @[FMAdd.scala 8:18]
-  wire [3:0] fmadd_io_op_bits; // @[FMAdd.scala 8:18]
-  wire  fmadd_io_ina_ready; // @[FMAdd.scala 8:18]
-  wire  fmadd_io_ina_valid; // @[FMAdd.scala 8:18]
-  wire [31:0] fmadd_io_ina_bits_0; // @[FMAdd.scala 8:18]
-  wire  fmadd_io_inb_ready; // @[FMAdd.scala 8:18]
-  wire  fmadd_io_inb_valid; // @[FMAdd.scala 8:18]
-  wire [31:0] fmadd_io_inb_bits_0; // @[FMAdd.scala 8:18]
-  wire  fmadd_io_inc_ready; // @[FMAdd.scala 8:18]
-  wire  fmadd_io_inc_valid; // @[FMAdd.scala 8:18]
-  wire [31:0] fmadd_io_inc_bits_0; // @[FMAdd.scala 8:18]
-  wire  fmadd_io_out_valid; // @[FMAdd.scala 8:18]
-  wire [31:0] fmadd_io_out_bits_0; // @[FMAdd.scala 8:18]
-  wire  addr_clock; // @[Fifo.scala 8:11]
-  wire  addr_reset; // @[Fifo.scala 8:11]
-  wire  addr_io_in_ready; // @[Fifo.scala 8:11]
-  wire  addr_io_in_valid; // @[Fifo.scala 8:11]
-  wire [4:0] addr_io_in_bits; // @[Fifo.scala 8:11]
-  wire  addr_io_out_ready; // @[Fifo.scala 8:11]
-  wire  addr_io_out_valid; // @[Fifo.scala 8:11]
-  wire [4:0] addr_io_out_bits; // @[Fifo.scala 8:11]
-  wire  data_clock; // @[Slice.scala 9:11]
-  wire  data_reset; // @[Slice.scala 9:11]
-  wire  data_io_in_ready; // @[Slice.scala 9:11]
-  wire  data_io_in_valid; // @[Slice.scala 9:11]
-  wire [31:0] data_io_in_bits; // @[Slice.scala 9:11]
-  wire  data_io_out_valid; // @[Slice.scala 9:11]
-  wire [31:0] data_io_out_bits; // @[Slice.scala 9:11]
-  wire  op_0 = io_in_op[2] | io_in_op[8]; // @[FMAdd.scala 38:47]
-  wire  op_1 = io_in_op[3]; // @[FMAdd.scala 39:33]
-  wire  op_2 = io_in_op[4]; // @[FMAdd.scala 40:33]
-  wire  op_3 = io_in_op[5]; // @[FMAdd.scala 41:33]
-  wire [1:0] fmadd_io_op_bits_lo = {op_1,op_0}; // @[FMAdd.scala 44:26]
-  wire [1:0] fmadd_io_op_bits_hi = {op_3,op_2}; // @[FMAdd.scala 44:26]
-  wire  _T_4 = ~reset; // @[FMAdd.scala 69:9]
-  FMAdd fmadd ( // @[FMAdd.scala 8:18]
-    .clock(fmadd_clock),
-    .reset(fmadd_reset),
-    .io_op_valid(fmadd_io_op_valid),
-    .io_op_bits(fmadd_io_op_bits),
-    .io_ina_ready(fmadd_io_ina_ready),
-    .io_ina_valid(fmadd_io_ina_valid),
-    .io_ina_bits_0(fmadd_io_ina_bits_0),
-    .io_inb_ready(fmadd_io_inb_ready),
-    .io_inb_valid(fmadd_io_inb_valid),
-    .io_inb_bits_0(fmadd_io_inb_bits_0),
-    .io_inc_ready(fmadd_io_inc_ready),
-    .io_inc_valid(fmadd_io_inc_valid),
-    .io_inc_bits_0(fmadd_io_inc_bits_0),
-    .io_out_valid(fmadd_io_out_valid),
-    .io_out_bits_0(fmadd_io_out_bits_0)
-  );
-  Fifo addr ( // @[Fifo.scala 8:11]
-    .clock(addr_clock),
-    .reset(addr_reset),
-    .io_in_ready(addr_io_in_ready),
-    .io_in_valid(addr_io_in_valid),
-    .io_in_bits(addr_io_in_bits),
-    .io_out_ready(addr_io_out_ready),
-    .io_out_valid(addr_io_out_valid),
-    .io_out_bits(addr_io_out_bits)
-  );
-  Slice_3 data ( // @[Slice.scala 9:11]
-    .clock(data_clock),
-    .reset(data_reset),
-    .io_in_ready(data_io_in_ready),
-    .io_in_valid(data_io_in_valid),
-    .io_in_bits(data_io_in_bits),
-    .io_out_valid(data_io_out_valid),
-    .io_out_bits(data_io_out_bits)
-  );
-  assign io_out_valid = fmadd_io_out_valid; // @[FMAdd.scala 61:16]
-  assign io_out_addr = addr_io_out_bits; // @[FMAdd.scala 62:15]
-  assign io_out_fd = fmadd_io_out_bits_0; // @[FMAdd.scala 63:13]
-  assign fmadd_clock = clock;
-  assign fmadd_reset = reset;
-  assign fmadd_io_op_valid = io_in_valid; // @[FMAdd.scala 43:21]
-  assign fmadd_io_op_bits = {fmadd_io_op_bits_hi,fmadd_io_op_bits_lo}; // @[FMAdd.scala 44:26]
-  assign fmadd_io_ina_valid = io_in_valid; // @[FMAdd.scala 47:22]
-  assign fmadd_io_ina_bits_0 = io_in_fs1; // @[FMAdd.scala 51:24]
-  assign fmadd_io_inb_valid = io_in_valid; // @[FMAdd.scala 48:22]
-  assign fmadd_io_inb_bits_0 = io_in_fs2; // @[FMAdd.scala 52:24]
-  assign fmadd_io_inc_valid = data_io_out_valid; // @[FMAdd.scala 49:22]
-  assign fmadd_io_inc_bits_0 = data_io_out_bits; // @[FMAdd.scala 53:24]
-  assign addr_clock = clock;
-  assign addr_reset = reset;
-  assign addr_io_in_valid = io_in_valid; // @[FMAdd.scala 55:20]
-  assign addr_io_in_bits = io_in_addr; // @[FMAdd.scala 56:19]
-  assign addr_io_out_ready = io_out_valid; // @[FMAdd.scala 65:21]
-  assign data_clock = clock;
-  assign data_reset = reset;
-  assign data_io_in_valid = io_in_valid; // @[FMAdd.scala 58:20]
-  assign data_io_in_bits = io_in_op[8] ? 32'h0 : io_in_fs3; // @[FMAdd.scala 59:25]
-  always @(posedge clock) begin
-    `ifndef SYNTHESIS
-    `ifdef STOP_COND
-      if (`STOP_COND) begin
-    `endif
-        if (~reset & ~(~(fmadd_io_ina_valid & ~fmadd_io_ina_ready))) begin
-          $fatal; // @[FMAdd.scala 69:9]
-        end
-    `ifdef STOP_COND
-      end
-    `endif
-    `endif // SYNTHESIS
-    `ifndef SYNTHESIS
-    `ifdef PRINTF_COND
-      if (`PRINTF_COND) begin
-    `endif
-        if (~reset & ~(~(fmadd_io_ina_valid & ~fmadd_io_ina_ready))) begin
-          $fwrite(32'h80000002,
-            "Assertion failed\n    at FMAdd.scala:69 assert(!(fmadd.io.ina.valid && !fmadd.io.ina.ready))\n"); // @[FMAdd.scala 69:9]
-        end
-    `ifdef PRINTF_COND
-      end
-    `endif
-    `endif // SYNTHESIS
-    `ifndef SYNTHESIS
-    `ifdef STOP_COND
-      if (`STOP_COND) begin
-    `endif
-        if (_T_4 & ~(~(fmadd_io_inb_valid & ~fmadd_io_inb_ready))) begin
-          $fatal; // @[FMAdd.scala 70:9]
-        end
-    `ifdef STOP_COND
-      end
-    `endif
-    `endif // SYNTHESIS
-    `ifndef SYNTHESIS
-    `ifdef PRINTF_COND
-      if (`PRINTF_COND) begin
-    `endif
-        if (_T_4 & ~(~(fmadd_io_inb_valid & ~fmadd_io_inb_ready))) begin
-          $fwrite(32'h80000002,
-            "Assertion failed\n    at FMAdd.scala:70 assert(!(fmadd.io.inb.valid && !fmadd.io.inb.ready))\n"); // @[FMAdd.scala 70:9]
-        end
-    `ifdef PRINTF_COND
-      end
-    `endif
-    `endif // SYNTHESIS
-    `ifndef SYNTHESIS
-    `ifdef STOP_COND
-      if (`STOP_COND) begin
-    `endif
-        if (_T_4 & ~(~(fmadd_io_inc_valid & ~fmadd_io_inc_ready))) begin
-          $fatal; // @[FMAdd.scala 71:9]
-        end
-    `ifdef STOP_COND
-      end
-    `endif
-    `endif // SYNTHESIS
-    `ifndef SYNTHESIS
-    `ifdef PRINTF_COND
-      if (`PRINTF_COND) begin
-    `endif
-        if (_T_4 & ~(~(fmadd_io_inc_valid & ~fmadd_io_inc_ready))) begin
-          $fwrite(32'h80000002,
-            "Assertion failed\n    at FMAdd.scala:71 assert(!(fmadd.io.inc.valid && !fmadd.io.inc.ready))\n"); // @[FMAdd.scala 71:9]
-        end
-    `ifdef PRINTF_COND
-      end
-    `endif
-    `endif // SYNTHESIS
-    `ifndef SYNTHESIS
-    `ifdef STOP_COND
-      if (`STOP_COND) begin
-    `endif
-        if (_T_4 & ~(~(addr_io_in_valid & ~addr_io_in_ready))) begin
-          $fatal; // @[FMAdd.scala 72:9]
-        end
-    `ifdef STOP_COND
-      end
-    `endif
-    `endif // SYNTHESIS
-    `ifndef SYNTHESIS
-    `ifdef PRINTF_COND
-      if (`PRINTF_COND) begin
-    `endif
-        if (_T_4 & ~(~(addr_io_in_valid & ~addr_io_in_ready))) begin
-          $fwrite(32'h80000002,
-            "Assertion failed\n    at FMAdd.scala:72 assert(!(addr.io.in.valid && !addr.io.in.ready))\n"); // @[FMAdd.scala 72:9]
-        end
-    `ifdef PRINTF_COND
-      end
-    `endif
-    `endif // SYNTHESIS
-  end
-endmodule
-module FDiv(
-  input         clock,
-  input         reset,
-  output        io_ina_ready,
-  input         io_ina_valid,
-  input  [31:0] io_ina_bits_0,
-  output        io_inb_ready,
-  input  [31:0] io_inb_bits_0,
-  output        io_out_valid,
-  output [31:0] io_out_bits_0
-);
-`ifdef RANDOMIZE_REG_INIT
-  reg [31:0] _RAND_0;
-  reg [31:0] _RAND_1;
-  reg [31:0] _RAND_2;
-  reg [31:0] _RAND_3;
-  reg [31:0] _RAND_4;
-  reg [31:0] _RAND_5;
-  reg [31:0] _RAND_6;
-  reg [31:0] _RAND_7;
-  reg [31:0] _RAND_8;
-`endif // RANDOMIZE_REG_INIT
-  reg  active; // @[FDiv.scala 43:23]
-  reg  result; // @[FDiv.scala 44:23]
-  reg [3:0] count; // @[FDiv.scala 45:18]
-  reg  state_0_oreg; // @[FDiv.scala 46:18]
-  reg  state_0_sreg; // @[FDiv.scala 46:18]
-  reg [9:0] state_0_ereg; // @[FDiv.scala 46:18]
-  reg [27:0] state_0_preg; // @[FDiv.scala 46:18]
-  reg [27:0] state_0_dreg; // @[FDiv.scala 46:18]
-  reg [26:0] state_0_qreg; // @[FDiv.scala 46:18]
-  wire  ivalid = io_ina_valid & io_ina_ready & io_inb_ready; // @[FDiv.scala 49:61]
-  wire  _T = count == 4'he; // @[FDiv.scala 54:32]
-  wire  _T_1 = active & count == 4'he; // @[FDiv.scala 54:23]
-  wire  _GEN_0 = active & count == 4'he ? 1'h0 : active; // @[FDiv.scala 54:49 55:12 43:23]
-  wire  _GEN_2 = _T_1 | result; // @[FDiv.scala 60:49 61:12 44:23]
-  wire [3:0] _count_T_1 = count + 4'h1; // @[FDiv.scala 67:20]
-  wire  _state_0_sn_T_3 = io_ina_bits_0[22:0] != 23'h0; // @[FBase.scala 72:40]
-  wire  state_0_sn = io_ina_bits_0[30:23] == 8'h0 & io_ina_bits_0[22:0] != 23'h0; // @[FBase.scala 72:27]
-  wire [9:0] state_0_en = {2'h0,io_ina_bits_0[30:23]}; // @[Cat.scala 31:58]
-  wire [23:0] state_0_mn = {1'h1,io_ina_bits_0[22:0]}; // @[Cat.scala 31:58]
-  wire [15:0] _GEN_33 = {{8'd0}, io_ina_bits_0[15:8]}; // @[Bitwise.scala 105:31]
-  wire [15:0] _state_0_shift_T_5 = _GEN_33 & 16'hff; // @[Bitwise.scala 105:31]
-  wire [15:0] _state_0_shift_T_7 = {io_ina_bits_0[7:0], 8'h0}; // @[Bitwise.scala 105:70]
-  wire [15:0] _state_0_shift_T_9 = _state_0_shift_T_7 & 16'hff00; // @[Bitwise.scala 105:80]
-  wire [15:0] _state_0_shift_T_10 = _state_0_shift_T_5 | _state_0_shift_T_9; // @[Bitwise.scala 105:39]
-  wire [15:0] _GEN_34 = {{4'd0}, _state_0_shift_T_10[15:4]}; // @[Bitwise.scala 105:31]
-  wire [15:0] _state_0_shift_T_15 = _GEN_34 & 16'hf0f; // @[Bitwise.scala 105:31]
-  wire [15:0] _state_0_shift_T_17 = {_state_0_shift_T_10[11:0], 4'h0}; // @[Bitwise.scala 105:70]
-  wire [15:0] _state_0_shift_T_19 = _state_0_shift_T_17 & 16'hf0f0; // @[Bitwise.scala 105:80]
-  wire [15:0] _state_0_shift_T_20 = _state_0_shift_T_15 | _state_0_shift_T_19; // @[Bitwise.scala 105:39]
-  wire [15:0] _GEN_35 = {{2'd0}, _state_0_shift_T_20[15:2]}; // @[Bitwise.scala 105:31]
-  wire [15:0] _state_0_shift_T_25 = _GEN_35 & 16'h3333; // @[Bitwise.scala 105:31]
-  wire [15:0] _state_0_shift_T_27 = {_state_0_shift_T_20[13:0], 2'h0}; // @[Bitwise.scala 105:70]
-  wire [15:0] _state_0_shift_T_29 = _state_0_shift_T_27 & 16'hcccc; // @[Bitwise.scala 105:80]
-  wire [15:0] _state_0_shift_T_30 = _state_0_shift_T_25 | _state_0_shift_T_29; // @[Bitwise.scala 105:39]
-  wire [15:0] _GEN_36 = {{1'd0}, _state_0_shift_T_30[15:1]}; // @[Bitwise.scala 105:31]
-  wire [15:0] _state_0_shift_T_35 = _GEN_36 & 16'h5555; // @[Bitwise.scala 105:31]
-  wire [15:0] _state_0_shift_T_37 = {_state_0_shift_T_30[14:0], 1'h0}; // @[Bitwise.scala 105:70]
-  wire [15:0] _state_0_shift_T_39 = _state_0_shift_T_37 & 16'haaaa; // @[Bitwise.scala 105:80]
-  wire [15:0] _state_0_shift_T_40 = _state_0_shift_T_35 | _state_0_shift_T_39; // @[Bitwise.scala 105:39]
-  wire [22:0] _state_0_shift_T_60 = {_state_0_shift_T_40,io_ina_bits_0[16],io_ina_bits_0[17],io_ina_bits_0[18],
-    io_ina_bits_0[19],io_ina_bits_0[20],io_ina_bits_0[21],io_ina_bits_0[22]}; // @[Cat.scala 31:58]
-  wire [4:0] _state_0_shift_T_84 = _state_0_shift_T_60[21] ? 5'h15 : 5'h16; // @[Mux.scala 47:70]
-  wire [4:0] _state_0_shift_T_85 = _state_0_shift_T_60[20] ? 5'h14 : _state_0_shift_T_84; // @[Mux.scala 47:70]
-  wire [4:0] _state_0_shift_T_86 = _state_0_shift_T_60[19] ? 5'h13 : _state_0_shift_T_85; // @[Mux.scala 47:70]
-  wire [4:0] _state_0_shift_T_87 = _state_0_shift_T_60[18] ? 5'h12 : _state_0_shift_T_86; // @[Mux.scala 47:70]
-  wire [4:0] _state_0_shift_T_88 = _state_0_shift_T_60[17] ? 5'h11 : _state_0_shift_T_87; // @[Mux.scala 47:70]
-  wire [4:0] _state_0_shift_T_89 = _state_0_shift_T_60[16] ? 5'h10 : _state_0_shift_T_88; // @[Mux.scala 47:70]
-  wire [4:0] _state_0_shift_T_90 = _state_0_shift_T_60[15] ? 5'hf : _state_0_shift_T_89; // @[Mux.scala 47:70]
-  wire [4:0] _state_0_shift_T_91 = _state_0_shift_T_60[14] ? 5'he : _state_0_shift_T_90; // @[Mux.scala 47:70]
-  wire [4:0] _state_0_shift_T_92 = _state_0_shift_T_60[13] ? 5'hd : _state_0_shift_T_91; // @[Mux.scala 47:70]
-  wire [4:0] _state_0_shift_T_93 = _state_0_shift_T_60[12] ? 5'hc : _state_0_shift_T_92; // @[Mux.scala 47:70]
-  wire [4:0] _state_0_shift_T_94 = _state_0_shift_T_60[11] ? 5'hb : _state_0_shift_T_93; // @[Mux.scala 47:70]
-  wire [4:0] _state_0_shift_T_95 = _state_0_shift_T_60[10] ? 5'ha : _state_0_shift_T_94; // @[Mux.scala 47:70]
-  wire [4:0] _state_0_shift_T_96 = _state_0_shift_T_60[9] ? 5'h9 : _state_0_shift_T_95; // @[Mux.scala 47:70]
-  wire [4:0] _state_0_shift_T_97 = _state_0_shift_T_60[8] ? 5'h8 : _state_0_shift_T_96; // @[Mux.scala 47:70]
-  wire [4:0] _state_0_shift_T_98 = _state_0_shift_T_60[7] ? 5'h7 : _state_0_shift_T_97; // @[Mux.scala 47:70]
-  wire [4:0] _state_0_shift_T_99 = _state_0_shift_T_60[6] ? 5'h6 : _state_0_shift_T_98; // @[Mux.scala 47:70]
-  wire [4:0] _state_0_shift_T_100 = _state_0_shift_T_60[5] ? 5'h5 : _state_0_shift_T_99; // @[Mux.scala 47:70]
-  wire [4:0] _state_0_shift_T_101 = _state_0_shift_T_60[4] ? 5'h4 : _state_0_shift_T_100; // @[Mux.scala 47:70]
-  wire [4:0] _state_0_shift_T_102 = _state_0_shift_T_60[3] ? 5'h3 : _state_0_shift_T_101; // @[Mux.scala 47:70]
-  wire [4:0] _state_0_shift_T_103 = _state_0_shift_T_60[2] ? 5'h2 : _state_0_shift_T_102; // @[Mux.scala 47:70]
-  wire [4:0] _state_0_shift_T_104 = _state_0_shift_T_60[1] ? 5'h1 : _state_0_shift_T_103; // @[Mux.scala 47:70]
-  wire [4:0] _state_0_shift_T_105 = _state_0_shift_T_60[0] ? 5'h0 : _state_0_shift_T_104; // @[Mux.scala 47:70]
-  wire [4:0] state_0_shift = 5'h1 + _state_0_shift_T_105; // @[FBase.scala 39:21]
-  wire [9:0] _GEN_37 = {{5'd0}, state_0_shift}; // @[FBase.scala 40:28]
-  wire [9:0] state_0_es = 10'h1 - _GEN_37; // @[FBase.scala 40:28]
-  wire [53:0] _GEN_1 = {{31'd0}, io_ina_bits_0[22:0]}; // @[FBase.scala 41:19]
-  wire [53:0] _state_0_ms_T = _GEN_1 << state_0_shift; // @[FBase.scala 41:19]
-  wire [23:0] state_0_ms = _state_0_ms_T[23:0]; // @[FBase.scala 41:28]
-  wire [9:0] state_0_iexp_a = state_0_sn ? state_0_es : state_0_en; // @[FBase.scala 43:16]
-  wire [23:0] state_0_m = state_0_sn ? state_0_ms : state_0_mn; // @[FBase.scala 44:16]
-  wire [27:0] state_0_iman_a = {2'h0,state_0_m,2'h0}; // @[Cat.scala 31:58]
-  wire  _state_0_sn_T_7 = io_inb_bits_0[22:0] != 23'h0; // @[FBase.scala 72:40]
-  wire  state_0_sn_1 = io_inb_bits_0[30:23] == 8'h0 & io_inb_bits_0[22:0] != 23'h0; // @[FBase.scala 72:27]
-  wire [9:0] state_0_en_1 = {2'h0,io_inb_bits_0[30:23]}; // @[Cat.scala 31:58]
-  wire [23:0] state_0_mn_1 = {1'h1,io_inb_bits_0[22:0]}; // @[Cat.scala 31:58]
-  wire [15:0] _GEN_38 = {{8'd0}, io_inb_bits_0[15:8]}; // @[Bitwise.scala 105:31]
-  wire [15:0] _state_0_shift_T_112 = _GEN_38 & 16'hff; // @[Bitwise.scala 105:31]
-  wire [15:0] _state_0_shift_T_114 = {io_inb_bits_0[7:0], 8'h0}; // @[Bitwise.scala 105:70]
-  wire [15:0] _state_0_shift_T_116 = _state_0_shift_T_114 & 16'hff00; // @[Bitwise.scala 105:80]
-  wire [15:0] _state_0_shift_T_117 = _state_0_shift_T_112 | _state_0_shift_T_116; // @[Bitwise.scala 105:39]
-  wire [15:0] _GEN_39 = {{4'd0}, _state_0_shift_T_117[15:4]}; // @[Bitwise.scala 105:31]
-  wire [15:0] _state_0_shift_T_122 = _GEN_39 & 16'hf0f; // @[Bitwise.scala 105:31]
-  wire [15:0] _state_0_shift_T_124 = {_state_0_shift_T_117[11:0], 4'h0}; // @[Bitwise.scala 105:70]
-  wire [15:0] _state_0_shift_T_126 = _state_0_shift_T_124 & 16'hf0f0; // @[Bitwise.scala 105:80]
-  wire [15:0] _state_0_shift_T_127 = _state_0_shift_T_122 | _state_0_shift_T_126; // @[Bitwise.scala 105:39]
-  wire [15:0] _GEN_40 = {{2'd0}, _state_0_shift_T_127[15:2]}; // @[Bitwise.scala 105:31]
-  wire [15:0] _state_0_shift_T_132 = _GEN_40 & 16'h3333; // @[Bitwise.scala 105:31]
-  wire [15:0] _state_0_shift_T_134 = {_state_0_shift_T_127[13:0], 2'h0}; // @[Bitwise.scala 105:70]
-  wire [15:0] _state_0_shift_T_136 = _state_0_shift_T_134 & 16'hcccc; // @[Bitwise.scala 105:80]
-  wire [15:0] _state_0_shift_T_137 = _state_0_shift_T_132 | _state_0_shift_T_136; // @[Bitwise.scala 105:39]
-  wire [15:0] _GEN_41 = {{1'd0}, _state_0_shift_T_137[15:1]}; // @[Bitwise.scala 105:31]
-  wire [15:0] _state_0_shift_T_142 = _GEN_41 & 16'h5555; // @[Bitwise.scala 105:31]
-  wire [15:0] _state_0_shift_T_144 = {_state_0_shift_T_137[14:0], 1'h0}; // @[Bitwise.scala 105:70]
-  wire [15:0] _state_0_shift_T_146 = _state_0_shift_T_144 & 16'haaaa; // @[Bitwise.scala 105:80]
-  wire [15:0] _state_0_shift_T_147 = _state_0_shift_T_142 | _state_0_shift_T_146; // @[Bitwise.scala 105:39]
-  wire [22:0] _state_0_shift_T_167 = {_state_0_shift_T_147,io_inb_bits_0[16],io_inb_bits_0[17],io_inb_bits_0[18],
-    io_inb_bits_0[19],io_inb_bits_0[20],io_inb_bits_0[21],io_inb_bits_0[22]}; // @[Cat.scala 31:58]
-  wire [4:0] _state_0_shift_T_191 = _state_0_shift_T_167[21] ? 5'h15 : 5'h16; // @[Mux.scala 47:70]
-  wire [4:0] _state_0_shift_T_192 = _state_0_shift_T_167[20] ? 5'h14 : _state_0_shift_T_191; // @[Mux.scala 47:70]
-  wire [4:0] _state_0_shift_T_193 = _state_0_shift_T_167[19] ? 5'h13 : _state_0_shift_T_192; // @[Mux.scala 47:70]
-  wire [4:0] _state_0_shift_T_194 = _state_0_shift_T_167[18] ? 5'h12 : _state_0_shift_T_193; // @[Mux.scala 47:70]
-  wire [4:0] _state_0_shift_T_195 = _state_0_shift_T_167[17] ? 5'h11 : _state_0_shift_T_194; // @[Mux.scala 47:70]
-  wire [4:0] _state_0_shift_T_196 = _state_0_shift_T_167[16] ? 5'h10 : _state_0_shift_T_195; // @[Mux.scala 47:70]
-  wire [4:0] _state_0_shift_T_197 = _state_0_shift_T_167[15] ? 5'hf : _state_0_shift_T_196; // @[Mux.scala 47:70]
-  wire [4:0] _state_0_shift_T_198 = _state_0_shift_T_167[14] ? 5'he : _state_0_shift_T_197; // @[Mux.scala 47:70]
-  wire [4:0] _state_0_shift_T_199 = _state_0_shift_T_167[13] ? 5'hd : _state_0_shift_T_198; // @[Mux.scala 47:70]
-  wire [4:0] _state_0_shift_T_200 = _state_0_shift_T_167[12] ? 5'hc : _state_0_shift_T_199; // @[Mux.scala 47:70]
-  wire [4:0] _state_0_shift_T_201 = _state_0_shift_T_167[11] ? 5'hb : _state_0_shift_T_200; // @[Mux.scala 47:70]
-  wire [4:0] _state_0_shift_T_202 = _state_0_shift_T_167[10] ? 5'ha : _state_0_shift_T_201; // @[Mux.scala 47:70]
-  wire [4:0] _state_0_shift_T_203 = _state_0_shift_T_167[9] ? 5'h9 : _state_0_shift_T_202; // @[Mux.scala 47:70]
-  wire [4:0] _state_0_shift_T_204 = _state_0_shift_T_167[8] ? 5'h8 : _state_0_shift_T_203; // @[Mux.scala 47:70]
-  wire [4:0] _state_0_shift_T_205 = _state_0_shift_T_167[7] ? 5'h7 : _state_0_shift_T_204; // @[Mux.scala 47:70]
-  wire [4:0] _state_0_shift_T_206 = _state_0_shift_T_167[6] ? 5'h6 : _state_0_shift_T_205; // @[Mux.scala 47:70]
-  wire [4:0] _state_0_shift_T_207 = _state_0_shift_T_167[5] ? 5'h5 : _state_0_shift_T_206; // @[Mux.scala 47:70]
-  wire [4:0] _state_0_shift_T_208 = _state_0_shift_T_167[4] ? 5'h4 : _state_0_shift_T_207; // @[Mux.scala 47:70]
-  wire [4:0] _state_0_shift_T_209 = _state_0_shift_T_167[3] ? 5'h3 : _state_0_shift_T_208; // @[Mux.scala 47:70]
-  wire [4:0] _state_0_shift_T_210 = _state_0_shift_T_167[2] ? 5'h2 : _state_0_shift_T_209; // @[Mux.scala 47:70]
-  wire [4:0] _state_0_shift_T_211 = _state_0_shift_T_167[1] ? 5'h1 : _state_0_shift_T_210; // @[Mux.scala 47:70]
-  wire [4:0] _state_0_shift_T_212 = _state_0_shift_T_167[0] ? 5'h0 : _state_0_shift_T_211; // @[Mux.scala 47:70]
-  wire [4:0] state_0_shift_1 = 5'h1 + _state_0_shift_T_212; // @[FBase.scala 39:21]
-  wire [9:0] _GEN_42 = {{5'd0}, state_0_shift_1}; // @[FBase.scala 40:28]
-  wire [9:0] state_0_es_1 = 10'h1 - _GEN_42; // @[FBase.scala 40:28]
-  wire [53:0] _GEN_3 = {{31'd0}, io_inb_bits_0[22:0]}; // @[FBase.scala 41:19]
-  wire [53:0] _state_0_ms_T_1 = _GEN_3 << state_0_shift_1; // @[FBase.scala 41:19]
-  wire [23:0] state_0_ms_1 = _state_0_ms_T_1[23:0]; // @[FBase.scala 41:28]
-  wire [9:0] state_0_iexp_b = state_0_sn_1 ? state_0_es_1 : state_0_en_1; // @[FBase.scala 43:16]
-  wire [23:0] state_0_m_1 = state_0_sn_1 ? state_0_ms_1 : state_0_mn_1; // @[FBase.scala 44:16]
-  wire [27:0] state_0_iman_b = {2'h0,state_0_m_1,2'h0}; // @[Cat.scala 31:58]
-  wire  state_0_isign_a = io_ina_bits_0[31]; // @[FBase.scala 28:14]
-  wire  state_0_isign_b = io_inb_bits_0[31]; // @[FBase.scala 28:14]
-  wire  _state_0_inan_a_T_1 = io_ina_bits_0[30:23] == 8'hff; // @[FBase.scala 68:19]
-  wire  state_0_inan_a = io_ina_bits_0[30:23] == 8'hff & _state_0_sn_T_3; // @[FBase.scala 68:37]
-  wire  _state_0_inan_b_T_1 = io_inb_bits_0[30:23] == 8'hff; // @[FBase.scala 68:19]
-  wire  state_0_inan_b = io_inb_bits_0[30:23] == 8'hff & _state_0_sn_T_7; // @[FBase.scala 68:37]
-  wire  state_0_iinf_a = _state_0_inan_a_T_1 & io_ina_bits_0[22:0] == 23'h0; // @[FBase.scala 64:37]
-  wire  state_0_iinf_b = _state_0_inan_b_T_1 & io_inb_bits_0[22:0] == 23'h0; // @[FBase.scala 64:37]
-  wire  state_0_izero_a = io_ina_bits_0[30:0] == 31'h0; // @[FBase.scala 76:18]
-  wire  state_0_izero_b = io_inb_bits_0[30:0] == 31'h0; // @[FBase.scala 76:18]
-  wire  state_0_isign = state_0_isign_a ^ state_0_isign_b; // @[FDiv.scala 117:29]
-  wire [9:0] _state_0_iexp_T_1 = state_0_iexp_a - state_0_iexp_b; // @[FDiv.scala 118:24]
-  wire [9:0] state_0_iexp = _state_0_iexp_T_1 + 10'h7f; // @[FDiv.scala 118:33]
-  wire  state_0_inan = state_0_inan_a | state_0_inan_b | state_0_iinf_a & state_0_iinf_b | state_0_izero_a &
-    state_0_izero_b; // @[FDiv.scala 120:54]
-  wire  state_0_iinf = state_0_iinf_a | state_0_izero_b; // @[FDiv.scala 121:25]
-  wire  state_0_izero = state_0_izero_a | state_0_iinf_b; // @[FDiv.scala 122:26]
-  wire [1:0] _state_0_iop_T_1 = state_0_iinf ? 2'h2 : {{1'd0}, state_0_izero}; // @[Mux.scala 101:16]
-  wire [1:0] state_0_iop = state_0_inan ? 2'h3 : _state_0_iop_T_1; // @[Mux.scala 101:16]
-  wire  state_0_shift_2 = state_0_iman_a < state_0_iman_b; // @[FDiv.scala 128:24]
-  wire  _state_0_sinit_T = state_0_iop == 2'h3; // @[FDiv.scala 130:43]
-  wire  _state_0_einit_T_1 = state_0_iop == 2'h2; // @[FDiv.scala 133:42]
-  wire  _state_0_einit_T_2 = state_0_iop == 2'h1; // @[FDiv.scala 134:42]
-  wire [9:0] _state_0_einit_T_4 = state_0_iexp - 10'h1; // @[FDiv.scala 135:52]
-  wire [9:0] _state_0_einit_T_5 = state_0_shift_2 ? _state_0_einit_T_4 : state_0_iexp; // @[Mux.scala 101:16]
-  wire  _state_0_dinit_T_3 = ~state_0_shift_2; // @[FDiv.scala 140:40]
-  wire [28:0] _state_0_dinit_T_4 = {2'h0,state_0_m_1,2'h0,1'h0}; // @[Cat.scala 31:58]
-  wire [28:0] _state_0_dinit_T_5 = _state_0_dinit_T_3 ? _state_0_dinit_T_4 : {{1'd0}, state_0_iman_b}; // @[Mux.scala 101:16]
-  wire [28:0] _state_0_dinit_T_6 = _state_0_einit_T_2 ? 29'h0 : _state_0_dinit_T_5; // @[Mux.scala 101:16]
-  wire [28:0] _state_0_dinit_T_7 = _state_0_einit_T_1 ? 29'h0 : _state_0_dinit_T_6; // @[Mux.scala 101:16]
-  wire [28:0] state_0_dinit = _state_0_sinit_T ? 29'h400000 : _state_0_dinit_T_7; // @[Mux.scala 101:16]
-  wire  state_0_out_oreg = state_0_iop == 2'h0; // @[FDiv.scala 142:21]
-  wire  state_0_b = $signed(state_0_preg) >= 28'sh0; // @[FDiv.scala 201:23]
-  wire [27:0] _state_0_np_T_1 = {state_0_preg[26:0],1'h0}; // @[Cat.scala 31:58]
-  wire [27:0] _state_0_np_T_3 = 28'h0 - state_0_dreg; // @[FDiv.scala 202:56]
-  wire [27:0] _state_0_np_T_4 = state_0_b ? _state_0_np_T_3 : state_0_dreg; // @[FDiv.scala 202:52]
-  wire [27:0] state_0_p0 = _state_0_np_T_1 + _state_0_np_T_4; // @[FDiv.scala 202:47]
-  wire [1:0] state_0_q0 = {1'h0,state_0_b}; // @[Cat.scala 31:58]
-  wire [27:0] _state_0_b_T_1 = _state_0_np_T_1 + _state_0_np_T_4; // @[FDiv.scala 201:16]
-  wire  state_0_b_1 = $signed(_state_0_b_T_1) >= 28'sh0; // @[FDiv.scala 201:23]
-  wire [27:0] _state_0_np_T_7 = {state_0_p0[26:0],1'h0}; // @[Cat.scala 31:58]
-  wire [27:0] _state_0_np_T_10 = state_0_b_1 ? _state_0_np_T_3 : state_0_dreg; // @[FDiv.scala 202:52]
-  wire [27:0] state_0_p1 = _state_0_np_T_7 + _state_0_np_T_10; // @[FDiv.scala 202:47]
-  wire  state_0_last = count == 4'hd; // @[FDiv.scala 182:26]
-  wire [27:0] _state_0_out_preg_T = state_0_last ? state_0_p0 : state_0_p1; // @[FDiv.scala 183:24]
-  wire [27:0] _state_0_out_qreg_T_1 = {state_0_qreg,state_0_q0[0]}; // @[Cat.scala 31:58]
-  wire [28:0] _state_0_out_qreg_T_2 = {state_0_qreg,state_0_q0[0],state_0_b_1}; // @[Cat.scala 31:58]
-  wire [28:0] _state_0_out_qreg_T_3 = state_0_last ? {{1'd0}, _state_0_out_qreg_T_1} : _state_0_out_qreg_T_2; // @[FDiv.scala 184:24]
-  wire [27:0] _state_0_norem_T_1 = state_0_dreg + state_0_preg; // @[FDiv.scala 216:20]
-  wire  state_0_norem = _state_0_norem_T_1 == 28'h0; // @[FDiv.scala 216:25]
-  wire [26:0] _state_0_rq_T = ~state_0_qreg; // @[FDiv.scala 217:21]
-  wire [26:0] _state_0_rq_T_2 = state_0_qreg - _state_0_rq_T; // @[FDiv.scala 217:18]
-  wire [26:0] _GEN_43 = {{26'd0}, state_0_norem}; // @[FDiv.scala 217:25]
-  wire [26:0] state_0_rq = _state_0_rq_T_2 - _GEN_43; // @[FDiv.scala 217:25]
-  wire [9:0] state_0_ne = 10'h0 - state_0_ereg; // @[FDiv.scala 219:17]
-  wire  state_0_subn = state_0_ereg[9] & state_0_ne < 10'h1a | state_0_ereg == 10'h0; // @[FDiv.scala 220:50]
-  wire [9:0] _state_0_shift_T_215 = 10'h1 + state_0_ne; // @[FDiv.scala 221:31]
-  wire [9:0] state_0_shift_3 = state_0_subn ? _state_0_shift_T_215 : 10'h0; // @[FDiv.scala 221:20]
-  wire  _state_0_zero0_T_1 = ~state_0_subn; // @[FDiv.scala 222:31]
-  wire  state_0_zero0 = state_0_ereg[9] & ~state_0_subn; // @[FDiv.scala 222:28]
-  wire  _state_0_zero0_T_5 = ~state_0_sreg; // @[FDiv.scala 222:56]
-  wire  state_0_isinf = (state_0_ereg[8] | state_0_ereg[7:0] == 8'hff) & ~state_0_zero0 & _state_0_zero0_T_1; // @[FDiv.scala 225:67]
-  wire [1049:0] _state_0_mask_T_1 = 1050'h7ffffff << state_0_shift_3; // @[FDiv.scala 229:40]
-  wire [26:0] state_0_mask = ~_state_0_mask_T_1[26:0]; // @[FDiv.scala 229:16]
-  wire [26:0] _state_0_sticky_T = state_0_rq & state_0_mask; // @[FDiv.scala 230:22]
-  wire  state_0_sticky = _state_0_sticky_T != 27'h0; // @[FDiv.scala 230:30]
-  wire [26:0] _state_0_r_T = state_0_rq >> state_0_shift_3; // @[FDiv.scala 233:17]
-  wire [26:0] _GEN_44 = {{26'd0}, state_0_sticky}; // @[FDiv.scala 233:27]
-  wire [26:0] state_0_r = _state_0_r_T | _GEN_44; // @[FDiv.scala 233:27]
-  wire  _state_0_m_round_T_1 = state_0_r[2:0] != 3'h0; // @[FBase.scala 92:30]
-  wire  _state_0_m_round_T_3 = state_0_r[2:0] != 3'h0 & _state_0_zero0_T_5; // @[FBase.scala 92:38]
-  wire  _state_0_m_round_T_6 = _state_0_m_round_T_1 & state_0_sreg; // @[FBase.scala 93:38]
-  wire  _state_0_m_round_T_11 = state_0_r[2:0] > 3'h4 | state_0_r[3:0] == 4'hc; // @[FBase.scala 95:36]
-  wire [3:0] state_0_m_round = {_state_0_m_round_T_3,_state_0_m_round_T_6,1'h0,_state_0_m_round_T_11}; // @[Cat.scala 31:58]
-  wire [23:0] _state_0_m_T_6 = state_0_r[26:3] + 24'h1; // @[FDiv.scala 234:67]
-  wire [23:0] state_0_m_2 = state_0_m_round[0] ? _state_0_m_T_6 : state_0_r[26:3]; // @[FDiv.scala 234:16]
-  wire [9:0] _state_0_oe_T_1 = state_0_zero0 | state_0_subn ? 10'h0 : state_0_ereg; // @[FDiv.scala 237:57]
-  wire [9:0] state_0_ernd = state_0_isinf ? 10'hff : _state_0_oe_T_1; // @[FDiv.scala 237:17]
-  wire [23:0] state_0_mrnd = state_0_isinf | state_0_zero0 ? 24'h0 : state_0_m_2; // @[FDiv.scala 238:17]
-  wire [9:0] _GEN_7 = _T ? state_0_ernd : state_0_ereg; // @[FDiv.scala 186:41 189:16 168:9]
-  wire [27:0] _GEN_8 = _T ? {{4'd0}, state_0_mrnd} : state_0_dreg; // @[FDiv.scala 186:41 190:16 168:9]
-  wire [28:0] _GEN_10 = count < 4'he ? _state_0_out_qreg_T_3 : {{2'd0}, state_0_qreg}; // @[FDiv.scala 172:39 184:18 168:9]
-  wire [28:0] _GEN_15 = ~state_0_oreg ? {{2'd0}, state_0_qreg} : _GEN_10; // @[FDiv.scala 170:21 168:9]
-  wire [26:0] state_0_out_1_qreg = _GEN_15[26:0]; // @[FDiv.scala 167:19]
-  wire [27:0] state_0_out_dreg = state_0_dinit[27:0]; // @[FDiv.scala 103:19 145:14]
-  wire  _io_ina_ready_T = ~active; // @[FDiv.scala 81:35]
-  wire [8:0] io_out_bits_0_result_hi = {state_0_sreg,state_0_ereg[7:0]}; // @[Cat.scala 31:58]
-  assign io_ina_ready = ~active; // @[FDiv.scala 81:35]
-  assign io_inb_ready = io_ina_valid & _io_ina_ready_T; // @[FDiv.scala 82:32]
-  assign io_out_valid = result; // @[FDiv.scala 84:16]
-  assign io_out_bits_0 = {io_out_bits_0_result_hi,state_0_dreg[22:0]}; // @[Cat.scala 31:58]
-  always @(posedge clock) begin
-    if (ivalid | io_out_valid) begin // @[FDiv.scala 64:27]
-      count <= 4'h0; // @[FDiv.scala 65:11]
-    end else if (active) begin // @[FDiv.scala 66:24]
-      count <= _count_T_1; // @[FDiv.scala 67:11]
-    end
-    if (ivalid) begin // @[FDiv.scala 74:19]
-      state_0_oreg <= state_0_out_oreg; // @[FDiv.scala 75:16]
-    end
-    if (ivalid) begin // @[FDiv.scala 74:19]
-      if (_state_0_sinit_T) begin // @[Mux.scala 101:16]
-        state_0_sreg <= 1'h0;
-      end else begin
-        state_0_sreg <= state_0_isign;
-      end
-    end
-    if (ivalid) begin // @[FDiv.scala 74:19]
-      if (_state_0_sinit_T) begin // @[Mux.scala 101:16]
-        state_0_ereg <= 10'hff;
-      end else if (_state_0_einit_T_1) begin // @[Mux.scala 101:16]
-        state_0_ereg <= 10'hff;
-      end else if (_state_0_einit_T_2) begin // @[Mux.scala 101:16]
-        state_0_ereg <= 10'h0;
-      end else begin
-        state_0_ereg <= _state_0_einit_T_5;
-      end
-    end else if (active) begin // @[FDiv.scala 76:26]
-      if (!(~state_0_oreg)) begin // @[FDiv.scala 170:21]
-        if (!(count < 4'he)) begin // @[FDiv.scala 172:39]
-          state_0_ereg <= _GEN_7;
-        end
-      end
-    end
-    if (ivalid) begin // @[FDiv.scala 74:19]
-      state_0_preg <= state_0_iman_a; // @[FDiv.scala 75:16]
-    end else if (active) begin // @[FDiv.scala 76:26]
-      if (!(~state_0_oreg)) begin // @[FDiv.scala 170:21]
-        if (count < 4'he) begin // @[FDiv.scala 172:39]
-          state_0_preg <= _state_0_out_preg_T; // @[FDiv.scala 183:18]
-        end
-      end
-    end
-    if (ivalid) begin // @[FDiv.scala 74:19]
-      state_0_dreg <= state_0_out_dreg; // @[FDiv.scala 75:16]
-    end else if (active) begin // @[FDiv.scala 76:26]
-      if (!(~state_0_oreg)) begin // @[FDiv.scala 170:21]
-        if (!(count < 4'he)) begin // @[FDiv.scala 172:39]
-          state_0_dreg <= _GEN_8;
-        end
-      end
-    end
-    if (ivalid) begin // @[FDiv.scala 74:19]
-      state_0_qreg <= 27'h0; // @[FDiv.scala 75:16]
-    end else if (active) begin // @[FDiv.scala 76:26]
-      state_0_qreg <= state_0_out_1_qreg; // @[FDiv.scala 77:16]
-    end
-  end
-  always @(posedge clock or posedge reset) begin
-    if (reset) begin // @[FDiv.scala 52:17]
-      active <= 1'h0; // @[FDiv.scala 53:12]
-    end else begin
-      active <= ivalid | _GEN_0;
-    end
-  end
-  always @(posedge clock or posedge reset) begin
-    if (reset) begin // @[FDiv.scala 58:17]
-      result <= 1'h0; // @[FDiv.scala 59:12]
-    end else if (io_out_valid) begin
-      result <= 1'h0;
-    end else begin
-      result <= _GEN_2;
-    end
-  end
-// Register and memory initialization
-`ifdef RANDOMIZE_GARBAGE_ASSIGN
-`define RANDOMIZE
-`endif
-`ifdef RANDOMIZE_INVALID_ASSIGN
-`define RANDOMIZE
-`endif
-`ifdef RANDOMIZE_REG_INIT
-`define RANDOMIZE
-`endif
-`ifdef RANDOMIZE_MEM_INIT
-`define RANDOMIZE
-`endif
-`ifndef RANDOM
-`define RANDOM $random
-`endif
-`ifdef RANDOMIZE_MEM_INIT
-  integer initvar;
-`endif
-`ifndef SYNTHESIS
-`ifdef FIRRTL_BEFORE_INITIAL
-`FIRRTL_BEFORE_INITIAL
-`endif
-initial begin
-  `ifdef RANDOMIZE
-    `ifdef INIT_RANDOM
-      `INIT_RANDOM
-    `endif
-    `ifndef VERILATOR
-      `ifdef RANDOMIZE_DELAY
-        #`RANDOMIZE_DELAY begin end
-      `else
-        #0.002 begin end
-      `endif
-    `endif
-`ifdef RANDOMIZE_REG_INIT
-  _RAND_0 = {1{`RANDOM}};
-  active = _RAND_0[0:0];
-  _RAND_1 = {1{`RANDOM}};
-  result = _RAND_1[0:0];
-  _RAND_2 = {1{`RANDOM}};
-  count = _RAND_2[3:0];
-  _RAND_3 = {1{`RANDOM}};
-  state_0_oreg = _RAND_3[0:0];
-  _RAND_4 = {1{`RANDOM}};
-  state_0_sreg = _RAND_4[0:0];
-  _RAND_5 = {1{`RANDOM}};
-  state_0_ereg = _RAND_5[9:0];
-  _RAND_6 = {1{`RANDOM}};
-  state_0_preg = _RAND_6[27:0];
-  _RAND_7 = {1{`RANDOM}};
-  state_0_dreg = _RAND_7[27:0];
-  _RAND_8 = {1{`RANDOM}};
-  state_0_qreg = _RAND_8[26:0];
-`endif // RANDOMIZE_REG_INIT
-  if (reset) begin
-    active = 1'h0;
-  end
-  if (reset) begin
-    result = 1'h0;
-  end
-  `endif // RANDOMIZE
-end // initial
-`ifdef FIRRTL_AFTER_INITIAL
-`FIRRTL_AFTER_INITIAL
-`endif
-`endif // SYNTHESIS
-endmodule
-module FDiv_1(
-  input         clock,
-  input         reset,
-  input         io_in_valid,
-  output        io_in_ready,
-  input  [4:0]  io_in_addr,
-  input  [31:0] io_in_fs1,
-  input  [31:0] io_in_fs2,
-  output        io_out_valid,
-  output [4:0]  io_out_addr,
-  output [31:0] io_out_fd
-);
-`ifdef RANDOMIZE_REG_INIT
-  reg [31:0] _RAND_0;
-`endif // RANDOMIZE_REG_INIT
-  wire  fdiv_clock; // @[FDiv.scala 8:18]
-  wire  fdiv_reset; // @[FDiv.scala 8:18]
-  wire  fdiv_io_ina_ready; // @[FDiv.scala 8:18]
-  wire  fdiv_io_ina_valid; // @[FDiv.scala 8:18]
-  wire [31:0] fdiv_io_ina_bits_0; // @[FDiv.scala 8:18]
-  wire  fdiv_io_inb_ready; // @[FDiv.scala 8:18]
-  wire [31:0] fdiv_io_inb_bits_0; // @[FDiv.scala 8:18]
-  wire  fdiv_io_out_valid; // @[FDiv.scala 8:18]
-  wire [31:0] fdiv_io_out_bits_0; // @[FDiv.scala 8:18]
-  reg [4:0] addr; // @[FDiv.scala 30:17]
-  FDiv fdiv ( // @[FDiv.scala 8:18]
-    .clock(fdiv_clock),
-    .reset(fdiv_reset),
-    .io_ina_ready(fdiv_io_ina_ready),
-    .io_ina_valid(fdiv_io_ina_valid),
-    .io_ina_bits_0(fdiv_io_ina_bits_0),
-    .io_inb_ready(fdiv_io_inb_ready),
-    .io_inb_bits_0(fdiv_io_inb_bits_0),
-    .io_out_valid(fdiv_io_out_valid),
-    .io_out_bits_0(fdiv_io_out_bits_0)
-  );
-  assign io_in_ready = fdiv_io_ina_ready; // @[FDiv.scala 32:15]
-  assign io_out_valid = fdiv_io_out_valid; // @[FDiv.scala 45:16]
-  assign io_out_addr = addr; // @[FDiv.scala 46:15]
-  assign io_out_fd = fdiv_io_out_bits_0; // @[FDiv.scala 47:13]
-  assign fdiv_clock = clock;
-  assign fdiv_reset = reset;
-  assign fdiv_io_ina_valid = io_in_valid; // @[FDiv.scala 35:21]
-  assign fdiv_io_ina_bits_0 = io_in_fs1; // @[FDiv.scala 37:23]
-  assign fdiv_io_inb_bits_0 = io_in_fs2; // @[FDiv.scala 38:23]
-  always @(posedge clock) begin
-    if (io_in_valid & io_in_ready) begin // @[FDiv.scala 41:37]
-      addr <= io_in_addr; // @[FDiv.scala 42:10]
-    end
-  end
-// Register and memory initialization
-`ifdef RANDOMIZE_GARBAGE_ASSIGN
-`define RANDOMIZE
-`endif
-`ifdef RANDOMIZE_INVALID_ASSIGN
-`define RANDOMIZE
-`endif
-`ifdef RANDOMIZE_REG_INIT
-`define RANDOMIZE
-`endif
-`ifdef RANDOMIZE_MEM_INIT
-`define RANDOMIZE
-`endif
-`ifndef RANDOM
-`define RANDOM $random
-`endif
-`ifdef RANDOMIZE_MEM_INIT
-  integer initvar;
-`endif
-`ifndef SYNTHESIS
-`ifdef FIRRTL_BEFORE_INITIAL
-`FIRRTL_BEFORE_INITIAL
-`endif
-initial begin
-  `ifdef RANDOMIZE
-    `ifdef INIT_RANDOM
-      `INIT_RANDOM
-    `endif
-    `ifndef VERILATOR
-      `ifdef RANDOMIZE_DELAY
-        #`RANDOMIZE_DELAY begin end
-      `else
-        #0.002 begin end
-      `endif
-    `endif
-`ifdef RANDOMIZE_REG_INIT
-  _RAND_0 = {1{`RANDOM}};
-  addr = _RAND_0[4:0];
-`endif // RANDOMIZE_REG_INIT
-  `endif // RANDOMIZE
-end // initial
-`ifdef FIRRTL_AFTER_INITIAL
-`FIRRTL_AFTER_INITIAL
-`endif
-`endif // SYNTHESIS
-endmodule
-module FSqrt(
-  input         clock,
-  input         reset,
-  output        io_in_ready,
-  input         io_in_valid,
-  input  [31:0] io_in_bits_0,
-  output        io_out_valid,
-  output [31:0] io_out_bits_0
-);
-`ifdef RANDOMIZE_REG_INIT
-  reg [31:0] _RAND_0;
-  reg [31:0] _RAND_1;
-  reg [31:0] _RAND_2;
-  reg [31:0] _RAND_3;
-  reg [31:0] _RAND_4;
-  reg [31:0] _RAND_5;
-  reg [31:0] _RAND_6;
-  reg [31:0] _RAND_7;
-  reg [31:0] _RAND_8;
-`endif // RANDOMIZE_REG_INIT
-  reg  active; // @[FSqrt.scala 31:23]
-  reg  result; // @[FSqrt.scala 32:23]
-  reg [3:0] count; // @[FSqrt.scala 33:18]
-  reg  state_0_nreg; // @[FSqrt.scala 34:18]
-  reg [9:0] state_0_ereg; // @[FSqrt.scala 34:18]
-  reg [26:0] state_0_qreg; // @[FSqrt.scala 34:18]
-  reg [26:0] state_0_mreg; // @[FSqrt.scala 34:18]
-  reg [26:0] state_0_sreg; // @[FSqrt.scala 34:18]
-  reg [1:0] state_0_oreg; // @[FSqrt.scala 34:18]
-  wire  ivalid = io_in_valid & io_in_ready; // @[FSqrt.scala 36:28]
-  wire  _T = count == 4'hd; // @[FSqrt.scala 41:32]
-  wire  _T_1 = active & count == 4'hd; // @[FSqrt.scala 41:23]
-  wire  _GEN_0 = active & count == 4'hd ? 1'h0 : active; // @[FSqrt.scala 41:50 42:12 31:23]
-  wire  _GEN_2 = _T_1 | result; // @[FSqrt.scala 47:50 48:12 32:23]
-  wire [3:0] _count_T_1 = count + 4'h1; // @[FSqrt.scala 54:20]
-  wire  _state_0_sn_T_3 = io_in_bits_0[22:0] != 23'h0; // @[FBase.scala 72:40]
-  wire  state_0_sn = io_in_bits_0[30:23] == 8'h0 & io_in_bits_0[22:0] != 23'h0; // @[FBase.scala 72:27]
-  wire [9:0] state_0_en = {2'h0,io_in_bits_0[30:23]}; // @[Cat.scala 31:58]
-  wire [23:0] state_0_mn = {1'h1,io_in_bits_0[22:0]}; // @[Cat.scala 31:58]
-  wire [15:0] _GEN_35 = {{8'd0}, io_in_bits_0[15:8]}; // @[Bitwise.scala 105:31]
-  wire [15:0] _state_0_shift_T_5 = _GEN_35 & 16'hff; // @[Bitwise.scala 105:31]
-  wire [15:0] _state_0_shift_T_7 = {io_in_bits_0[7:0], 8'h0}; // @[Bitwise.scala 105:70]
-  wire [15:0] _state_0_shift_T_9 = _state_0_shift_T_7 & 16'hff00; // @[Bitwise.scala 105:80]
-  wire [15:0] _state_0_shift_T_10 = _state_0_shift_T_5 | _state_0_shift_T_9; // @[Bitwise.scala 105:39]
-  wire [15:0] _GEN_36 = {{4'd0}, _state_0_shift_T_10[15:4]}; // @[Bitwise.scala 105:31]
-  wire [15:0] _state_0_shift_T_15 = _GEN_36 & 16'hf0f; // @[Bitwise.scala 105:31]
-  wire [15:0] _state_0_shift_T_17 = {_state_0_shift_T_10[11:0], 4'h0}; // @[Bitwise.scala 105:70]
-  wire [15:0] _state_0_shift_T_19 = _state_0_shift_T_17 & 16'hf0f0; // @[Bitwise.scala 105:80]
-  wire [15:0] _state_0_shift_T_20 = _state_0_shift_T_15 | _state_0_shift_T_19; // @[Bitwise.scala 105:39]
-  wire [15:0] _GEN_37 = {{2'd0}, _state_0_shift_T_20[15:2]}; // @[Bitwise.scala 105:31]
-  wire [15:0] _state_0_shift_T_25 = _GEN_37 & 16'h3333; // @[Bitwise.scala 105:31]
-  wire [15:0] _state_0_shift_T_27 = {_state_0_shift_T_20[13:0], 2'h0}; // @[Bitwise.scala 105:70]
-  wire [15:0] _state_0_shift_T_29 = _state_0_shift_T_27 & 16'hcccc; // @[Bitwise.scala 105:80]
-  wire [15:0] _state_0_shift_T_30 = _state_0_shift_T_25 | _state_0_shift_T_29; // @[Bitwise.scala 105:39]
-  wire [15:0] _GEN_38 = {{1'd0}, _state_0_shift_T_30[15:1]}; // @[Bitwise.scala 105:31]
-  wire [15:0] _state_0_shift_T_35 = _GEN_38 & 16'h5555; // @[Bitwise.scala 105:31]
-  wire [15:0] _state_0_shift_T_37 = {_state_0_shift_T_30[14:0], 1'h0}; // @[Bitwise.scala 105:70]
-  wire [15:0] _state_0_shift_T_39 = _state_0_shift_T_37 & 16'haaaa; // @[Bitwise.scala 105:80]
-  wire [15:0] _state_0_shift_T_40 = _state_0_shift_T_35 | _state_0_shift_T_39; // @[Bitwise.scala 105:39]
-  wire [22:0] _state_0_shift_T_60 = {_state_0_shift_T_40,io_in_bits_0[16],io_in_bits_0[17],io_in_bits_0[18],io_in_bits_0
-    [19],io_in_bits_0[20],io_in_bits_0[21],io_in_bits_0[22]}; // @[Cat.scala 31:58]
-  wire [4:0] _state_0_shift_T_84 = _state_0_shift_T_60[21] ? 5'h15 : 5'h16; // @[Mux.scala 47:70]
-  wire [4:0] _state_0_shift_T_85 = _state_0_shift_T_60[20] ? 5'h14 : _state_0_shift_T_84; // @[Mux.scala 47:70]
-  wire [4:0] _state_0_shift_T_86 = _state_0_shift_T_60[19] ? 5'h13 : _state_0_shift_T_85; // @[Mux.scala 47:70]
-  wire [4:0] _state_0_shift_T_87 = _state_0_shift_T_60[18] ? 5'h12 : _state_0_shift_T_86; // @[Mux.scala 47:70]
-  wire [4:0] _state_0_shift_T_88 = _state_0_shift_T_60[17] ? 5'h11 : _state_0_shift_T_87; // @[Mux.scala 47:70]
-  wire [4:0] _state_0_shift_T_89 = _state_0_shift_T_60[16] ? 5'h10 : _state_0_shift_T_88; // @[Mux.scala 47:70]
-  wire [4:0] _state_0_shift_T_90 = _state_0_shift_T_60[15] ? 5'hf : _state_0_shift_T_89; // @[Mux.scala 47:70]
-  wire [4:0] _state_0_shift_T_91 = _state_0_shift_T_60[14] ? 5'he : _state_0_shift_T_90; // @[Mux.scala 47:70]
-  wire [4:0] _state_0_shift_T_92 = _state_0_shift_T_60[13] ? 5'hd : _state_0_shift_T_91; // @[Mux.scala 47:70]
-  wire [4:0] _state_0_shift_T_93 = _state_0_shift_T_60[12] ? 5'hc : _state_0_shift_T_92; // @[Mux.scala 47:70]
-  wire [4:0] _state_0_shift_T_94 = _state_0_shift_T_60[11] ? 5'hb : _state_0_shift_T_93; // @[Mux.scala 47:70]
-  wire [4:0] _state_0_shift_T_95 = _state_0_shift_T_60[10] ? 5'ha : _state_0_shift_T_94; // @[Mux.scala 47:70]
-  wire [4:0] _state_0_shift_T_96 = _state_0_shift_T_60[9] ? 5'h9 : _state_0_shift_T_95; // @[Mux.scala 47:70]
-  wire [4:0] _state_0_shift_T_97 = _state_0_shift_T_60[8] ? 5'h8 : _state_0_shift_T_96; // @[Mux.scala 47:70]
-  wire [4:0] _state_0_shift_T_98 = _state_0_shift_T_60[7] ? 5'h7 : _state_0_shift_T_97; // @[Mux.scala 47:70]
-  wire [4:0] _state_0_shift_T_99 = _state_0_shift_T_60[6] ? 5'h6 : _state_0_shift_T_98; // @[Mux.scala 47:70]
-  wire [4:0] _state_0_shift_T_100 = _state_0_shift_T_60[5] ? 5'h5 : _state_0_shift_T_99; // @[Mux.scala 47:70]
-  wire [4:0] _state_0_shift_T_101 = _state_0_shift_T_60[4] ? 5'h4 : _state_0_shift_T_100; // @[Mux.scala 47:70]
-  wire [4:0] _state_0_shift_T_102 = _state_0_shift_T_60[3] ? 5'h3 : _state_0_shift_T_101; // @[Mux.scala 47:70]
-  wire [4:0] _state_0_shift_T_103 = _state_0_shift_T_60[2] ? 5'h2 : _state_0_shift_T_102; // @[Mux.scala 47:70]
-  wire [4:0] _state_0_shift_T_104 = _state_0_shift_T_60[1] ? 5'h1 : _state_0_shift_T_103; // @[Mux.scala 47:70]
-  wire [4:0] _state_0_shift_T_105 = _state_0_shift_T_60[0] ? 5'h0 : _state_0_shift_T_104; // @[Mux.scala 47:70]
-  wire [4:0] state_0_shift = 5'h1 + _state_0_shift_T_105; // @[FBase.scala 39:21]
-  wire [9:0] _GEN_39 = {{5'd0}, state_0_shift}; // @[FBase.scala 40:28]
-  wire [9:0] state_0_es = 10'h1 - _GEN_39; // @[FBase.scala 40:28]
-  wire [53:0] _GEN_1 = {{31'd0}, io_in_bits_0[22:0]}; // @[FBase.scala 41:19]
-  wire [53:0] _state_0_ms_T = _GEN_1 << state_0_shift; // @[FBase.scala 41:19]
-  wire [23:0] state_0_ms = _state_0_ms_T[23:0]; // @[FBase.scala 41:28]
-  wire [9:0] state_0_e = state_0_sn ? state_0_es : state_0_en; // @[FBase.scala 43:16]
-  wire [23:0] state_0_m = state_0_sn ? state_0_ms : state_0_mn; // @[FBase.scala 44:16]
-  wire [26:0] state_0_r = {2'h0,state_0_m,1'h0}; // @[Cat.scala 31:58]
-  wire [9:0] _state_0_re_T_1 = state_0_e - 10'h7f; // @[FSqrt.scala 121:18]
-  wire [9:0] _state_0_re_T_2 = {{1'd0}, _state_0_re_T_1[9:1]}; // @[FSqrt.scala 121:26]
-  wire [9:0] _state_0_re_T_4 = _state_0_re_T_2 + 10'h7f; // @[FSqrt.scala 121:34]
-  wire [9:0] state_0_iexp = _state_0_re_T_4 - 10'h1; // @[FSqrt.scala 121:41]
-  wire [27:0] _state_0_rm_T_1 = {state_0_r, 1'h0}; // @[FSqrt.scala 122:29]
-  wire [27:0] _state_0_rm_T_2 = state_0_e[0] ? {{1'd0}, state_0_r} : _state_0_rm_T_1; // @[FSqrt.scala 122:17]
-  wire [26:0] state_0_iman = _state_0_rm_T_2[26:0]; // @[FSqrt.scala 122:34]
-  wire  state_0_isign = io_in_bits_0[31]; // @[FBase.scala 28:14]
-  wire  state_0_izero = io_in_bits_0[30:0] == 31'h0; // @[FBase.scala 76:18]
-  wire  _state_0_isnan_T_1 = io_in_bits_0[30:23] == 8'hff; // @[FBase.scala 68:19]
-  wire  _state_0_isnan_T_4 = io_in_bits_0[30:23] == 8'hff & _state_0_sn_T_3; // @[FBase.scala 68:37]
-  wire  _state_0_isnan_T_12 = _state_0_isnan_T_1 & io_in_bits_0[22:0] == 23'h0; // @[FBase.scala 64:37]
-  wire  state_0_isnan = _state_0_isnan_T_4 | state_0_isign & ~state_0_izero | _state_0_isnan_T_12 & state_0_isign; // @[FSqrt.scala 94:49]
-  wire  state_0_isinf = _state_0_isnan_T_12 & ~state_0_isign; // @[FSqrt.scala 95:30]
-  wire  state_0_out_nreg = state_0_isign & ~state_0_isnan; // @[FSqrt.scala 101:23]
-  wire [4:0] _state_0_rreg_T = {count,1'h0}; // @[Cat.scala 31:58]
-  wire [24:0] state_0_rreg = 25'h1000000 >> _state_0_rreg_T; // @[FSqrt.scala 137:30]
-  wire [26:0] _GEN_41 = {{2'd0}, state_0_rreg}; // @[FSqrt.scala 199:17]
-  wire [26:0] state_0_t0 = state_0_sreg + _GEN_41; // @[FSqrt.scala 199:17]
-  wire  state_0_select0 = state_0_t0 <= state_0_mreg; // @[FSqrt.scala 200:22]
-  wire [26:0] _state_0_m1a_T_1 = state_0_mreg - state_0_t0; // @[FSqrt.scala 202:20]
-  wire [27:0] _state_0_m1a_T_2 = {_state_0_m1a_T_1, 1'h0}; // @[FSqrt.scala 202:26]
-  wire [26:0] state_0_m1a = _state_0_m1a_T_2[26:0]; // @[FSqrt.scala 202:31]
-  wire [26:0] state_0_q1a = state_0_qreg + _GEN_41; // @[FSqrt.scala 203:18]
-  wire [24:0] state_0_r1a = {1'h0,state_0_rreg[24:1]}; // @[Cat.scala 31:58]
-  wire [26:0] state_0_s1a = state_0_t0 + _GEN_41; // @[FSqrt.scala 205:18]
-  wire [27:0] _state_0_m1b_T = {state_0_mreg, 1'h0}; // @[FSqrt.scala 207:19]
-  wire [26:0] state_0_m1b = _state_0_m1b_T[26:0]; // @[FSqrt.scala 207:24]
-  wire [26:0] _GEN_44 = {{2'd0}, state_0_r1a}; // @[FSqrt.scala 212:19]
-  wire [26:0] state_0_t1a = state_0_s1a + _GEN_44; // @[FSqrt.scala 212:19]
-  wire  state_0_select1a = state_0_t1a <= state_0_m1a; // @[FSqrt.scala 213:24]
-  wire [26:0] _state_0_m2a_T_1 = state_0_m1a - state_0_t1a; // @[FSqrt.scala 214:34]
-  wire [27:0] _state_0_m2a_T_2 = {_state_0_m2a_T_1, 1'h0}; // @[FSqrt.scala 214:41]
-  wire [27:0] _state_0_m2a_T_3 = {state_0_m1a, 1'h0}; // @[FSqrt.scala 214:51]
-  wire [27:0] _state_0_m2a_T_4 = state_0_select1a ? _state_0_m2a_T_2 : _state_0_m2a_T_3; // @[FSqrt.scala 214:18]
-  wire [26:0] state_0_m2a = _state_0_m2a_T_4[26:0]; // @[FSqrt.scala 214:56]
-  wire [26:0] _state_0_q2a_T_1 = state_0_q1a + _GEN_44; // @[FSqrt.scala 215:33]
-  wire [26:0] state_0_q2a = state_0_select1a ? _state_0_q2a_T_1 : state_0_q1a; // @[FSqrt.scala 215:18]
-  wire [26:0] _state_0_s2a_T_1 = state_0_t1a + _GEN_44; // @[FSqrt.scala 216:33]
-  wire [26:0] state_0_s2a = state_0_select1a ? _state_0_s2a_T_1 : state_0_s1a; // @[FSqrt.scala 216:18]
-  wire [26:0] state_0_t1b = state_0_sreg + _GEN_44; // @[FSqrt.scala 218:19]
-  wire  state_0_select1b = state_0_t1b <= state_0_m1b; // @[FSqrt.scala 219:24]
-  wire [26:0] _state_0_m2b_T_1 = state_0_m1b - state_0_t1b; // @[FSqrt.scala 220:34]
-  wire [27:0] _state_0_m2b_T_2 = {_state_0_m2b_T_1, 1'h0}; // @[FSqrt.scala 220:41]
-  wire [27:0] _state_0_m2b_T_3 = {state_0_m1b, 1'h0}; // @[FSqrt.scala 220:51]
-  wire [27:0] _state_0_m2b_T_4 = state_0_select1b ? _state_0_m2b_T_2 : _state_0_m2b_T_3; // @[FSqrt.scala 220:18]
-  wire [26:0] state_0_m2b = _state_0_m2b_T_4[26:0]; // @[FSqrt.scala 220:56]
-  wire [26:0] _state_0_q2b_T_1 = state_0_qreg + _GEN_44; // @[FSqrt.scala 221:33]
-  wire [26:0] state_0_q2b = state_0_select1b ? _state_0_q2b_T_1 : state_0_qreg; // @[FSqrt.scala 221:18]
-  wire [26:0] _state_0_s2b_T_1 = state_0_t1b + _GEN_44; // @[FSqrt.scala 222:33]
-  wire [26:0] state_0_s2b = state_0_select1b ? _state_0_s2b_T_1 : state_0_sreg; // @[FSqrt.scala 222:18]
-  wire [26:0] state_0_mnxt = state_0_select0 ? state_0_m2a : state_0_m2b; // @[FSqrt.scala 224:17]
-  wire [26:0] state_0_qnxt = state_0_select0 ? state_0_q2a : state_0_q2b; // @[FSqrt.scala 225:17]
-  wire [26:0] state_0_snxt = state_0_select0 ? state_0_s2a : state_0_s2b; // @[FSqrt.scala 226:17]
-  wire  state_0_round = state_0_qreg[0]; // @[FSqrt.scala 170:46]
-  wire [27:0] _state_0_qnxt_T = state_0_qreg + 27'h2; // @[FSqrt.scala 172:39]
-  wire [27:0] state_0_qnxt_1 = state_0_round ? _state_0_qnxt_T : {{1'd0}, state_0_qreg}; // @[FSqrt.scala 172:23]
-  wire [9:0] _GEN_50 = {{8'd0}, state_0_qnxt_1[25:24]}; // @[FSqrt.scala 173:29]
-  wire [9:0] _state_0_out_ereg_T_2 = state_0_ereg + _GEN_50; // @[FSqrt.scala 173:29]
-  wire [9:0] _GEN_9 = state_0_oreg == 2'h1 ? 10'h0 : _state_0_out_ereg_T_2; // @[FSqrt.scala 166:46 167:18 173:18]
-  wire [23:0] _GEN_10 = state_0_oreg == 2'h1 ? 24'h0 : state_0_qnxt_1[24:1]; // @[FSqrt.scala 166:46 168:18 174:18]
-  wire [9:0] _GEN_11 = state_0_oreg == 2'h3 ? 10'hff : _GEN_9; // @[FSqrt.scala 163:45 164:18]
-  wire [23:0] _GEN_12 = state_0_oreg == 2'h3 ? 24'h0 : _GEN_10; // @[FSqrt.scala 163:45 165:18]
-  wire [9:0] _GEN_13 = state_0_oreg == 2'h2 ? 10'hff : _GEN_11; // @[FSqrt.scala 160:38 161:18]
-  wire [23:0] _GEN_14 = state_0_oreg == 2'h2 ? 24'h400000 : _GEN_12; // @[FSqrt.scala 160:38 162:18]
-  wire [8:0] io_out_bits_0_result_hi = {state_0_nreg,state_0_ereg[7:0]}; // @[Cat.scala 31:58]
-  assign io_in_ready = ~active; // @[FSqrt.scala 67:19]
-  assign io_out_valid = result; // @[FSqrt.scala 68:16]
-  assign io_out_bits_0 = {io_out_bits_0_result_hi,state_0_qreg[22:0]}; // @[Cat.scala 31:58]
-  always @(posedge clock) begin
-    if (ivalid | io_out_valid) begin // @[FSqrt.scala 51:27]
-      count <= 4'h0; // @[FSqrt.scala 52:11]
-    end else if (active) begin // @[FSqrt.scala 53:24]
-      count <= _count_T_1; // @[FSqrt.scala 54:11]
-    end
-    if (ivalid) begin // @[FSqrt.scala 60:19]
-      state_0_nreg <= state_0_out_nreg; // @[FSqrt.scala 61:16]
-    end
-    if (ivalid) begin // @[FSqrt.scala 60:19]
-      state_0_ereg <= state_0_iexp; // @[FSqrt.scala 61:16]
-    end else if (active) begin // @[FSqrt.scala 62:26]
-      if (!(count < 4'hd)) begin // @[FSqrt.scala 153:33]
-        if (_T) begin // @[FSqrt.scala 159:42]
-          state_0_ereg <= _GEN_13;
-        end
-      end
-    end
-    if (ivalid) begin // @[FSqrt.scala 60:19]
-      state_0_qreg <= 27'h0; // @[FSqrt.scala 61:16]
-    end else if (active) begin // @[FSqrt.scala 62:26]
-      if (count < 4'hd) begin // @[FSqrt.scala 153:33]
-        if (state_0_oreg == 2'h0) begin // @[FSqrt.scala 154:39]
-          state_0_qreg <= state_0_qnxt; // @[FSqrt.scala 156:18]
-        end
-      end else if (_T) begin // @[FSqrt.scala 159:42]
-        state_0_qreg <= {{3'd0}, _GEN_14};
-      end
-    end
-    if (ivalid) begin // @[FSqrt.scala 60:19]
-      state_0_mreg <= state_0_iman; // @[FSqrt.scala 61:16]
-    end else if (active) begin // @[FSqrt.scala 62:26]
-      if (count < 4'hd) begin // @[FSqrt.scala 153:33]
-        if (state_0_oreg == 2'h0) begin // @[FSqrt.scala 154:39]
-          state_0_mreg <= state_0_mnxt; // @[FSqrt.scala 155:18]
-        end
-      end
-    end
-    if (ivalid) begin // @[FSqrt.scala 60:19]
-      state_0_sreg <= 27'h0; // @[FSqrt.scala 61:16]
-    end else if (active) begin // @[FSqrt.scala 62:26]
-      if (count < 4'hd) begin // @[FSqrt.scala 153:33]
-        if (state_0_oreg == 2'h0) begin // @[FSqrt.scala 154:39]
-          state_0_sreg <= state_0_snxt; // @[FSqrt.scala 157:18]
-        end
-      end
-    end
-    if (ivalid) begin // @[FSqrt.scala 60:19]
-      if (state_0_isinf) begin // @[Mux.scala 101:16]
-        state_0_oreg <= 2'h3;
-      end else if (state_0_isnan) begin // @[Mux.scala 101:16]
-        state_0_oreg <= 2'h2;
-      end else begin
-        state_0_oreg <= {{1'd0}, state_0_izero};
-      end
-    end
-  end
-  always @(posedge clock or posedge reset) begin
-    if (reset) begin // @[FSqrt.scala 39:17]
-      active <= 1'h0; // @[FSqrt.scala 40:12]
-    end else begin
-      active <= ivalid | _GEN_0;
-    end
-  end
-  always @(posedge clock or posedge reset) begin
-    if (reset) begin // @[FSqrt.scala 45:17]
-      result <= 1'h0; // @[FSqrt.scala 46:12]
-    end else if (io_out_valid) begin
-      result <= 1'h0;
-    end else begin
-      result <= _GEN_2;
-    end
-  end
-// Register and memory initialization
-`ifdef RANDOMIZE_GARBAGE_ASSIGN
-`define RANDOMIZE
-`endif
-`ifdef RANDOMIZE_INVALID_ASSIGN
-`define RANDOMIZE
-`endif
-`ifdef RANDOMIZE_REG_INIT
-`define RANDOMIZE
-`endif
-`ifdef RANDOMIZE_MEM_INIT
-`define RANDOMIZE
-`endif
-`ifndef RANDOM
-`define RANDOM $random
-`endif
-`ifdef RANDOMIZE_MEM_INIT
-  integer initvar;
-`endif
-`ifndef SYNTHESIS
-`ifdef FIRRTL_BEFORE_INITIAL
-`FIRRTL_BEFORE_INITIAL
-`endif
-initial begin
-  `ifdef RANDOMIZE
-    `ifdef INIT_RANDOM
-      `INIT_RANDOM
-    `endif
-    `ifndef VERILATOR
-      `ifdef RANDOMIZE_DELAY
-        #`RANDOMIZE_DELAY begin end
-      `else
-        #0.002 begin end
-      `endif
-    `endif
-`ifdef RANDOMIZE_REG_INIT
-  _RAND_0 = {1{`RANDOM}};
-  active = _RAND_0[0:0];
-  _RAND_1 = {1{`RANDOM}};
-  result = _RAND_1[0:0];
-  _RAND_2 = {1{`RANDOM}};
-  count = _RAND_2[3:0];
-  _RAND_3 = {1{`RANDOM}};
-  state_0_nreg = _RAND_3[0:0];
-  _RAND_4 = {1{`RANDOM}};
-  state_0_ereg = _RAND_4[9:0];
-  _RAND_5 = {1{`RANDOM}};
-  state_0_qreg = _RAND_5[26:0];
-  _RAND_6 = {1{`RANDOM}};
-  state_0_mreg = _RAND_6[26:0];
-  _RAND_7 = {1{`RANDOM}};
-  state_0_sreg = _RAND_7[26:0];
-  _RAND_8 = {1{`RANDOM}};
-  state_0_oreg = _RAND_8[1:0];
-`endif // RANDOMIZE_REG_INIT
-  if (reset) begin
-    active = 1'h0;
-  end
-  if (reset) begin
-    result = 1'h0;
-  end
-  `endif // RANDOMIZE
-end // initial
-`ifdef FIRRTL_AFTER_INITIAL
-`FIRRTL_AFTER_INITIAL
-`endif
-`endif // SYNTHESIS
-endmodule
-module FSqrt_1(
-  input         clock,
-  input         reset,
-  input         io_in_valid,
-  output        io_in_ready,
-  input  [4:0]  io_in_addr,
-  input  [31:0] io_in_fs,
-  output        io_out_valid,
-  output [4:0]  io_out_addr,
-  output [31:0] io_out_fd
-);
-`ifdef RANDOMIZE_REG_INIT
-  reg [31:0] _RAND_0;
-`endif // RANDOMIZE_REG_INIT
-  wire  fsqrt_clock; // @[FSqrt.scala 8:18]
-  wire  fsqrt_reset; // @[FSqrt.scala 8:18]
-  wire  fsqrt_io_in_ready; // @[FSqrt.scala 8:18]
-  wire  fsqrt_io_in_valid; // @[FSqrt.scala 8:18]
-  wire [31:0] fsqrt_io_in_bits_0; // @[FSqrt.scala 8:18]
-  wire  fsqrt_io_out_valid; // @[FSqrt.scala 8:18]
-  wire [31:0] fsqrt_io_out_bits_0; // @[FSqrt.scala 8:18]
-  reg [4:0] addr; // @[FSqrt.scala 29:17]
-  FSqrt fsqrt ( // @[FSqrt.scala 8:18]
-    .clock(fsqrt_clock),
-    .reset(fsqrt_reset),
-    .io_in_ready(fsqrt_io_in_ready),
-    .io_in_valid(fsqrt_io_in_valid),
-    .io_in_bits_0(fsqrt_io_in_bits_0),
-    .io_out_valid(fsqrt_io_out_valid),
-    .io_out_bits_0(fsqrt_io_out_bits_0)
-  );
-  assign io_in_ready = fsqrt_io_in_ready; // @[FSqrt.scala 31:15]
-  assign io_out_valid = fsqrt_io_out_valid; // @[FSqrt.scala 42:16]
-  assign io_out_addr = addr; // @[FSqrt.scala 43:15]
-  assign io_out_fd = fsqrt_io_out_bits_0; // @[FSqrt.scala 44:13]
-  assign fsqrt_clock = clock;
-  assign fsqrt_reset = reset;
-  assign fsqrt_io_in_valid = io_in_valid; // @[FSqrt.scala 34:21]
-  assign fsqrt_io_in_bits_0 = io_in_fs; // @[FSqrt.scala 35:23]
-  always @(posedge clock) begin
-    if (io_in_valid & io_in_ready) begin // @[FSqrt.scala 38:37]
-      addr <= io_in_addr; // @[FSqrt.scala 39:10]
-    end
-  end
-// Register and memory initialization
-`ifdef RANDOMIZE_GARBAGE_ASSIGN
-`define RANDOMIZE
-`endif
-`ifdef RANDOMIZE_INVALID_ASSIGN
-`define RANDOMIZE
-`endif
-`ifdef RANDOMIZE_REG_INIT
-`define RANDOMIZE
-`endif
-`ifdef RANDOMIZE_MEM_INIT
-`define RANDOMIZE
-`endif
-`ifndef RANDOM
-`define RANDOM $random
-`endif
-`ifdef RANDOMIZE_MEM_INIT
-  integer initvar;
-`endif
-`ifndef SYNTHESIS
-`ifdef FIRRTL_BEFORE_INITIAL
-`FIRRTL_BEFORE_INITIAL
-`endif
-initial begin
-  `ifdef RANDOMIZE
-    `ifdef INIT_RANDOM
-      `INIT_RANDOM
-    `endif
-    `ifndef VERILATOR
-      `ifdef RANDOMIZE_DELAY
-        #`RANDOMIZE_DELAY begin end
-      `else
-        #0.002 begin end
-      `endif
-    `endif
-`ifdef RANDOMIZE_REG_INIT
-  _RAND_0 = {1{`RANDOM}};
-  addr = _RAND_0[4:0];
-`endif // RANDOMIZE_REG_INIT
-  `endif // RANDOMIZE
-end // initial
-`ifdef FIRRTL_AFTER_INITIAL
-`FIRRTL_AFTER_INITIAL
-`endif
-`endif // SYNTHESIS
-endmodule
-module FCvtsw(
-  input         clock,
-  input         io_unsigned,
-  output        io_in_ready,
-  input         io_in_valid,
-  input  [31:0] io_in_bits,
-  output        io_out_valid,
-  output [31:0] io_out_bits
-);
-`ifdef RANDOMIZE_REG_INIT
-  reg [31:0] _RAND_0;
-  reg [31:0] _RAND_1;
-  reg [31:0] _RAND_2;
-  reg [31:0] _RAND_3;
-  reg [31:0] _RAND_4;
-  reg [31:0] _RAND_5;
-  reg [31:0] _RAND_6;
-  reg [31:0] _RAND_7;
-  reg [31:0] _RAND_8;
-`endif // RANDOMIZE_REG_INIT
-  reg  active1; // @[FCvtsw.scala 23:20]
-  reg  active2; // @[FCvtsw.scala 24:20]
-  reg  state1_zero; // @[FCvtsw.scala 26:19]
-  reg  state1_sign; // @[FCvtsw.scala 26:19]
-  reg [7:0] state1_exp; // @[FCvtsw.scala 26:19]
-  reg [26:0] state1_man; // @[FCvtsw.scala 26:19]
-  reg  state2_sign; // @[FCvtsw.scala 27:19]
-  reg [7:0] state2_exp; // @[FCvtsw.scala 27:19]
-  reg [22:0] state2_man; // @[FCvtsw.scala 27:19]
-  wire  update1 = io_in_valid & io_in_ready; // @[FCvtsw.scala 29:29]
-  wire [31:0] _state1_inu_T_4 = 32'h0 - io_in_bits; // @[FCvtsw.scala 72:44]
-  wire [31:0] state1_inu = io_unsigned | ~io_in_bits[31] ? io_in_bits : _state1_inu_T_4; // @[FCvtsw.scala 72:18]
-  wire [31:0] _GEN_13 = {{16'd0}, state1_inu[31:16]}; // @[Bitwise.scala 105:31]
-  wire [31:0] _state1_clz_T_3 = _GEN_13 & 32'hffff; // @[Bitwise.scala 105:31]
-  wire [31:0] _state1_clz_T_5 = {state1_inu[15:0], 16'h0}; // @[Bitwise.scala 105:70]
-  wire [31:0] _state1_clz_T_7 = _state1_clz_T_5 & 32'hffff0000; // @[Bitwise.scala 105:80]
-  wire [31:0] _state1_clz_T_8 = _state1_clz_T_3 | _state1_clz_T_7; // @[Bitwise.scala 105:39]
-  wire [31:0] _GEN_14 = {{8'd0}, _state1_clz_T_8[31:8]}; // @[Bitwise.scala 105:31]
-  wire [31:0] _state1_clz_T_13 = _GEN_14 & 32'hff00ff; // @[Bitwise.scala 105:31]
-  wire [31:0] _state1_clz_T_15 = {_state1_clz_T_8[23:0], 8'h0}; // @[Bitwise.scala 105:70]
-  wire [31:0] _state1_clz_T_17 = _state1_clz_T_15 & 32'hff00ff00; // @[Bitwise.scala 105:80]
-  wire [31:0] _state1_clz_T_18 = _state1_clz_T_13 | _state1_clz_T_17; // @[Bitwise.scala 105:39]
-  wire [31:0] _GEN_15 = {{4'd0}, _state1_clz_T_18[31:4]}; // @[Bitwise.scala 105:31]
-  wire [31:0] _state1_clz_T_23 = _GEN_15 & 32'hf0f0f0f; // @[Bitwise.scala 105:31]
-  wire [31:0] _state1_clz_T_25 = {_state1_clz_T_18[27:0], 4'h0}; // @[Bitwise.scala 105:70]
-  wire [31:0] _state1_clz_T_27 = _state1_clz_T_25 & 32'hf0f0f0f0; // @[Bitwise.scala 105:80]
-  wire [31:0] _state1_clz_T_28 = _state1_clz_T_23 | _state1_clz_T_27; // @[Bitwise.scala 105:39]
-  wire [31:0] _GEN_16 = {{2'd0}, _state1_clz_T_28[31:2]}; // @[Bitwise.scala 105:31]
-  wire [31:0] _state1_clz_T_33 = _GEN_16 & 32'h33333333; // @[Bitwise.scala 105:31]
-  wire [31:0] _state1_clz_T_35 = {_state1_clz_T_28[29:0], 2'h0}; // @[Bitwise.scala 105:70]
-  wire [31:0] _state1_clz_T_37 = _state1_clz_T_35 & 32'hcccccccc; // @[Bitwise.scala 105:80]
-  wire [31:0] _state1_clz_T_38 = _state1_clz_T_33 | _state1_clz_T_37; // @[Bitwise.scala 105:39]
-  wire [31:0] _GEN_17 = {{1'd0}, _state1_clz_T_38[31:1]}; // @[Bitwise.scala 105:31]
-  wire [31:0] _state1_clz_T_43 = _GEN_17 & 32'h55555555; // @[Bitwise.scala 105:31]
-  wire [31:0] _state1_clz_T_45 = {_state1_clz_T_38[30:0], 1'h0}; // @[Bitwise.scala 105:70]
-  wire [31:0] _state1_clz_T_47 = _state1_clz_T_45 & 32'haaaaaaaa; // @[Bitwise.scala 105:80]
-  wire [31:0] _state1_clz_T_48 = _state1_clz_T_43 | _state1_clz_T_47; // @[Bitwise.scala 105:39]
-  wire [4:0] _state1_clz_T_81 = _state1_clz_T_48[30] ? 5'h1e : 5'h1f; // @[Mux.scala 47:70]
-  wire [4:0] _state1_clz_T_82 = _state1_clz_T_48[29] ? 5'h1d : _state1_clz_T_81; // @[Mux.scala 47:70]
-  wire [4:0] _state1_clz_T_83 = _state1_clz_T_48[28] ? 5'h1c : _state1_clz_T_82; // @[Mux.scala 47:70]
-  wire [4:0] _state1_clz_T_84 = _state1_clz_T_48[27] ? 5'h1b : _state1_clz_T_83; // @[Mux.scala 47:70]
-  wire [4:0] _state1_clz_T_85 = _state1_clz_T_48[26] ? 5'h1a : _state1_clz_T_84; // @[Mux.scala 47:70]
-  wire [4:0] _state1_clz_T_86 = _state1_clz_T_48[25] ? 5'h19 : _state1_clz_T_85; // @[Mux.scala 47:70]
-  wire [4:0] _state1_clz_T_87 = _state1_clz_T_48[24] ? 5'h18 : _state1_clz_T_86; // @[Mux.scala 47:70]
-  wire [4:0] _state1_clz_T_88 = _state1_clz_T_48[23] ? 5'h17 : _state1_clz_T_87; // @[Mux.scala 47:70]
-  wire [4:0] _state1_clz_T_89 = _state1_clz_T_48[22] ? 5'h16 : _state1_clz_T_88; // @[Mux.scala 47:70]
-  wire [4:0] _state1_clz_T_90 = _state1_clz_T_48[21] ? 5'h15 : _state1_clz_T_89; // @[Mux.scala 47:70]
-  wire [4:0] _state1_clz_T_91 = _state1_clz_T_48[20] ? 5'h14 : _state1_clz_T_90; // @[Mux.scala 47:70]
-  wire [4:0] _state1_clz_T_92 = _state1_clz_T_48[19] ? 5'h13 : _state1_clz_T_91; // @[Mux.scala 47:70]
-  wire [4:0] _state1_clz_T_93 = _state1_clz_T_48[18] ? 5'h12 : _state1_clz_T_92; // @[Mux.scala 47:70]
-  wire [4:0] _state1_clz_T_94 = _state1_clz_T_48[17] ? 5'h11 : _state1_clz_T_93; // @[Mux.scala 47:70]
-  wire [4:0] _state1_clz_T_95 = _state1_clz_T_48[16] ? 5'h10 : _state1_clz_T_94; // @[Mux.scala 47:70]
-  wire [4:0] _state1_clz_T_96 = _state1_clz_T_48[15] ? 5'hf : _state1_clz_T_95; // @[Mux.scala 47:70]
-  wire [4:0] _state1_clz_T_97 = _state1_clz_T_48[14] ? 5'he : _state1_clz_T_96; // @[Mux.scala 47:70]
-  wire [4:0] _state1_clz_T_98 = _state1_clz_T_48[13] ? 5'hd : _state1_clz_T_97; // @[Mux.scala 47:70]
-  wire [4:0] _state1_clz_T_99 = _state1_clz_T_48[12] ? 5'hc : _state1_clz_T_98; // @[Mux.scala 47:70]
-  wire [4:0] _state1_clz_T_100 = _state1_clz_T_48[11] ? 5'hb : _state1_clz_T_99; // @[Mux.scala 47:70]
-  wire [4:0] _state1_clz_T_101 = _state1_clz_T_48[10] ? 5'ha : _state1_clz_T_100; // @[Mux.scala 47:70]
-  wire [4:0] _state1_clz_T_102 = _state1_clz_T_48[9] ? 5'h9 : _state1_clz_T_101; // @[Mux.scala 47:70]
-  wire [4:0] _state1_clz_T_103 = _state1_clz_T_48[8] ? 5'h8 : _state1_clz_T_102; // @[Mux.scala 47:70]
-  wire [4:0] _state1_clz_T_104 = _state1_clz_T_48[7] ? 5'h7 : _state1_clz_T_103; // @[Mux.scala 47:70]
-  wire [4:0] _state1_clz_T_105 = _state1_clz_T_48[6] ? 5'h6 : _state1_clz_T_104; // @[Mux.scala 47:70]
-  wire [4:0] _state1_clz_T_106 = _state1_clz_T_48[5] ? 5'h5 : _state1_clz_T_105; // @[Mux.scala 47:70]
-  wire [4:0] _state1_clz_T_107 = _state1_clz_T_48[4] ? 5'h4 : _state1_clz_T_106; // @[Mux.scala 47:70]
-  wire [4:0] _state1_clz_T_108 = _state1_clz_T_48[3] ? 5'h3 : _state1_clz_T_107; // @[Mux.scala 47:70]
-  wire [4:0] _state1_clz_T_109 = _state1_clz_T_48[2] ? 5'h2 : _state1_clz_T_108; // @[Mux.scala 47:70]
-  wire [4:0] _state1_clz_T_110 = _state1_clz_T_48[1] ? 5'h1 : _state1_clz_T_109; // @[Mux.scala 47:70]
-  wire [4:0] state1_clz = _state1_clz_T_48[0] ? 5'h0 : _state1_clz_T_110; // @[Mux.scala 47:70]
-  wire [62:0] _GEN_0 = {{31'd0}, state1_inu}; // @[FCvtsw.scala 74:22]
-  wire [62:0] _state1_man_s_T = _GEN_0 << state1_clz; // @[FCvtsw.scala 74:22]
-  wire [31:0] state1_man_s = _state1_man_s_T[31:0]; // @[FCvtsw.scala 74:29]
-  wire  state1_state1_zero = io_in_bits == 32'h0; // @[FCvtsw.scala 76:23]
-  wire  state1_state1_sign = io_in_bits[31] & ~io_unsigned; // @[FCvtsw.scala 78:27]
-  wire [7:0] _GEN_18 = {{3'd0}, state1_clz}; // @[FCvtsw.scala 79:25]
-  wire [7:0] state1_state1_exp = 8'h9e - _GEN_18; // @[FCvtsw.scala 79:25]
-  wire [26:0] _GEN_19 = {{26'd0}, state1_man_s[4]}; // @[FCvtsw.scala 80:31]
-  wire [26:0] _state1_state1_man_T_2 = state1_man_s[31:5] | _GEN_19; // @[FCvtsw.scala 80:31]
-  wire [26:0] _GEN_20 = {{26'd0}, state1_man_s[3]}; // @[FCvtsw.scala 81:28]
-  wire [26:0] _state1_state1_man_T_4 = _state1_state1_man_T_2 | _GEN_20; // @[FCvtsw.scala 81:28]
-  wire [26:0] _GEN_21 = {{26'd0}, state1_man_s[2]}; // @[FCvtsw.scala 81:39]
-  wire [26:0] _state1_state1_man_T_6 = _state1_state1_man_T_4 | _GEN_21; // @[FCvtsw.scala 81:39]
-  wire [26:0] _GEN_22 = {{26'd0}, state1_man_s[1]}; // @[FCvtsw.scala 81:50]
-  wire [26:0] _state1_state1_man_T_8 = _state1_state1_man_T_6 | _GEN_22; // @[FCvtsw.scala 81:50]
-  wire [26:0] _GEN_23 = {{26'd0}, state1_man_s[0]}; // @[FCvtsw.scala 81:61]
-  wire [26:0] state1_state1_man = _state1_state1_man_T_8 | _GEN_23; // @[FCvtsw.scala 81:61]
-  wire  _state2_man_n_round_T_1 = state1_man[2:0] != 3'h0; // @[FBase.scala 92:30]
-  wire  _state2_man_n_round_T_3 = state1_man[2:0] != 3'h0 & ~state1_sign; // @[FBase.scala 92:38]
-  wire  _state2_man_n_round_T_6 = _state2_man_n_round_T_1 & state1_sign; // @[FBase.scala 93:38]
-  wire  _state2_man_n_round_T_11 = state1_man[2:0] > 3'h4 | state1_man[3:0] == 4'hc; // @[FBase.scala 95:36]
-  wire [3:0] state2_man_n_round = {_state2_man_n_round_T_3,_state2_man_n_round_T_6,1'h0,_state2_man_n_round_T_11}; // @[Cat.scala 31:58]
-  wire [24:0] _state2_man_n_T_5 = state1_man[26:3] + 24'h1; // @[FCvtsw.scala 94:38]
-  wire [24:0] state2_man_n = state2_man_n_round[0] ? _state2_man_n_T_5 : {{1'd0}, state1_man[26:3]}; // @[FCvtsw.scala 93:20]
-  wire [7:0] _state2_exp_n_T_2 = state1_exp + 8'h1; // @[FCvtsw.scala 95:43]
-  wire [8:0] io_out_bits_hi = {state2_sign,state2_exp}; // @[Cat.scala 31:58]
-  assign io_in_ready = 1'h1; // @[FCvtsw.scala 48:43]
-  assign io_out_valid = active2; // @[FCvtsw.scala 49:16]
-  assign io_out_bits = {io_out_bits_hi,state2_man}; // @[Cat.scala 31:58]
-  always @(posedge clock) begin
-    active1 <= io_in_valid & io_in_ready; // @[FCvtsw.scala 29:29]
-    active2 <= active1; // @[FCvtsw.scala 36:34 37:13 24:20]
-    if (update1) begin // @[FCvtsw.scala 40:18]
-      state1_zero <= state1_state1_zero; // @[FCvtsw.scala 41:12]
-    end
-    if (update1) begin // @[FCvtsw.scala 40:18]
-      state1_sign <= state1_state1_sign; // @[FCvtsw.scala 41:12]
-    end
-    if (update1) begin // @[FCvtsw.scala 40:18]
-      state1_exp <= state1_state1_exp; // @[FCvtsw.scala 41:12]
-    end
-    if (update1) begin // @[FCvtsw.scala 40:18]
-      state1_man <= state1_state1_man; // @[FCvtsw.scala 41:12]
-    end
-    if (active1) begin // @[FCvtsw.scala 44:18]
-      if (state1_zero) begin // @[FCvtsw.scala 97:24]
-        state2_sign <= 1'h0; // @[FCvtsw.scala 98:19]
-      end else begin
-        state2_sign <= state1_sign; // @[FCvtsw.scala 102:19]
-      end
-    end
-    if (active1) begin // @[FCvtsw.scala 44:18]
-      if (state1_zero) begin // @[FCvtsw.scala 97:24]
-        state2_exp <= 8'h0; // @[FCvtsw.scala 99:18]
-      end else if (state2_man_n[24]) begin // @[FCvtsw.scala 95:20]
-        state2_exp <= _state2_exp_n_T_2;
-      end else begin
-        state2_exp <= state1_exp;
-      end
-    end
-    if (active1) begin // @[FCvtsw.scala 44:18]
-      if (state1_zero) begin // @[FCvtsw.scala 97:24]
-        state2_man <= 23'h0; // @[FCvtsw.scala 100:18]
-      end else begin
-        state2_man <= state2_man_n[22:0]; // @[FCvtsw.scala 104:18]
-      end
-    end
-  end
-// Register and memory initialization
-`ifdef RANDOMIZE_GARBAGE_ASSIGN
-`define RANDOMIZE
-`endif
-`ifdef RANDOMIZE_INVALID_ASSIGN
-`define RANDOMIZE
-`endif
-`ifdef RANDOMIZE_REG_INIT
-`define RANDOMIZE
-`endif
-`ifdef RANDOMIZE_MEM_INIT
-`define RANDOMIZE
-`endif
-`ifndef RANDOM
-`define RANDOM $random
-`endif
-`ifdef RANDOMIZE_MEM_INIT
-  integer initvar;
-`endif
-`ifndef SYNTHESIS
-`ifdef FIRRTL_BEFORE_INITIAL
-`FIRRTL_BEFORE_INITIAL
-`endif
-initial begin
-  `ifdef RANDOMIZE
-    `ifdef INIT_RANDOM
-      `INIT_RANDOM
-    `endif
-    `ifndef VERILATOR
-      `ifdef RANDOMIZE_DELAY
-        #`RANDOMIZE_DELAY begin end
-      `else
-        #0.002 begin end
-      `endif
-    `endif
-`ifdef RANDOMIZE_REG_INIT
-  _RAND_0 = {1{`RANDOM}};
-  active1 = _RAND_0[0:0];
-  _RAND_1 = {1{`RANDOM}};
-  active2 = _RAND_1[0:0];
-  _RAND_2 = {1{`RANDOM}};
-  state1_zero = _RAND_2[0:0];
-  _RAND_3 = {1{`RANDOM}};
-  state1_sign = _RAND_3[0:0];
-  _RAND_4 = {1{`RANDOM}};
-  state1_exp = _RAND_4[7:0];
-  _RAND_5 = {1{`RANDOM}};
-  state1_man = _RAND_5[26:0];
-  _RAND_6 = {1{`RANDOM}};
-  state2_sign = _RAND_6[0:0];
-  _RAND_7 = {1{`RANDOM}};
-  state2_exp = _RAND_7[7:0];
-  _RAND_8 = {1{`RANDOM}};
-  state2_man = _RAND_8[22:0];
-`endif // RANDOMIZE_REG_INIT
-  `endif // RANDOMIZE
-end // initial
-`ifdef FIRRTL_AFTER_INITIAL
-`FIRRTL_AFTER_INITIAL
-`endif
-`endif // SYNTHESIS
-endmodule
-module Fifo_2(
-  input        clock,
-  input        reset,
-  output       io_in_ready,
-  input        io_in_valid,
-  input  [4:0] io_in_bits,
-  input        io_out_ready,
-  output       io_out_valid,
-  output [4:0] io_out_bits
-);
-`ifdef RANDOMIZE_GARBAGE_ASSIGN
-  reg [31:0] _RAND_1;
-`endif // RANDOMIZE_GARBAGE_ASSIGN
-`ifdef RANDOMIZE_MEM_INIT
-  reg [31:0] _RAND_0;
-`endif // RANDOMIZE_MEM_INIT
-`ifdef RANDOMIZE_REG_INIT
-  reg [31:0] _RAND_2;
-  reg [31:0] _RAND_3;
-  reg [31:0] _RAND_4;
-  reg [31:0] _RAND_5;
-  reg [31:0] _RAND_6;
-  reg [31:0] _RAND_7;
-`endif // RANDOMIZE_REG_INIT
-  reg [4:0] mem [0:2]; // @[Fifo.scala 22:16]
-  wire  mem_rdata_MPORT_en; // @[Fifo.scala 22:16]
-  wire [1:0] mem_rdata_MPORT_addr; // @[Fifo.scala 22:16]
-  wire [4:0] mem_rdata_MPORT_data; // @[Fifo.scala 22:16]
-  wire [4:0] mem_MPORT_data; // @[Fifo.scala 22:16]
-  wire [1:0] mem_MPORT_addr; // @[Fifo.scala 22:16]
-  wire  mem_MPORT_mask; // @[Fifo.scala 22:16]
-  wire  mem_MPORT_en; // @[Fifo.scala 22:16]
-  reg [4:0] rdata; // @[Fifo.scala 23:18]
-  reg  rvalid; // @[Fifo.scala 25:23]
-  reg  wready; // @[Fifo.scala 26:23]
-  reg [1:0] raddr; // @[Fifo.scala 27:22]
-  reg [1:0] waddr; // @[Fifo.scala 28:22]
-  reg [2:0] count; // @[Fifo.scala 29:22]
-  wire  winc = io_in_valid & io_in_ready; // @[Fifo.scala 33:26]
-  wire  rinc = (~rvalid | io_out_ready) & (winc | count > 3'h1); // @[Fifo.scala 34:40]
-  wire [1:0] _waddr_T_2 = waddr + 2'h1; // @[Fifo.scala 37:50]
-  wire [1:0] _raddr_T_2 = raddr + 2'h1; // @[Fifo.scala 41:50]
-  wire  forward = rinc & winc & count <= 3'h1; // @[Fifo.scala 44:30]
-  wire  oen = io_out_valid & io_out_ready; // @[Fifo.scala 49:26]
-  wire  _T_1 = winc & ~oen; // @[Fifo.scala 51:13]
-  wire [2:0] _count_T_1 = count + 3'h1; // @[Fifo.scala 52:20]
-  wire  _T_2 = ~winc; // @[Fifo.scala 53:16]
-  wire [2:0] _count_T_3 = count - 3'h1; // @[Fifo.scala 54:20]
-  wire  _GEN_4 = io_out_ready & count == 3'h1 ? 1'h0 : rvalid; // @[Fifo.scala 59:47 60:12 25:23]
-  wire  _wready_T_5 = count == 3'h3 & ~_T_1; // @[Fifo.scala 64:33]
-  wire  _wready_T_6 = count < 3'h3 | _wready_T_5; // @[Fifo.scala 63:31]
-  wire  _wready_T_8 = oen & _T_2; // @[Fifo.scala 65:18]
-  wire  _T_6 = ~forward; // @[Fifo.scala 69:17]
-  wire  _T_10 = ~reset; // @[Fifo.scala 92:9]
-  assign mem_rdata_MPORT_en = forward ? 1'h0 : rinc;
-  assign mem_rdata_MPORT_addr = raddr;
-  `ifndef RANDOMIZE_GARBAGE_ASSIGN
-  assign mem_rdata_MPORT_data = mem[mem_rdata_MPORT_addr]; // @[Fifo.scala 22:16]
-  `else
-  assign mem_rdata_MPORT_data = mem_rdata_MPORT_addr >= 2'h3 ? _RAND_1[4:0] : mem[mem_rdata_MPORT_addr]; // @[Fifo.scala 22:16]
-  `endif // RANDOMIZE_GARBAGE_ASSIGN
-  assign mem_MPORT_data = io_in_bits;
-  assign mem_MPORT_addr = waddr;
-  assign mem_MPORT_mask = 1'h1;
-  assign mem_MPORT_en = winc & _T_6;
-  assign io_in_ready = wready; // @[Fifo.scala 87:17]
-  assign io_out_valid = rvalid; // @[Fifo.scala 81:16]
-  assign io_out_bits = rdata; // @[Fifo.scala 82:15]
-  always @(posedge clock) begin
-    if (mem_MPORT_en & mem_MPORT_mask) begin
-      mem[mem_MPORT_addr] <= mem_MPORT_data; // @[Fifo.scala 22:16]
-    end
-    if (forward) begin // @[Fifo.scala 73:18]
-      rdata <= io_in_bits; // @[Fifo.scala 74:11]
-    end else if (rinc) begin // @[Fifo.scala 75:22]
-      rdata <= mem_rdata_MPORT_data; // @[Fifo.scala 76:11]
-    end
-    `ifndef SYNTHESIS
-    `ifdef STOP_COND
-      if (`STOP_COND) begin
-    `endif
-        if (~reset & ~(count <= 3'h4)) begin
-          $fatal; // @[Fifo.scala 92:9]
-        end
-    `ifdef STOP_COND
-      end
-    `endif
-    `endif // SYNTHESIS
-    `ifndef SYNTHESIS
-    `ifdef PRINTF_COND
-      if (`PRINTF_COND) begin
-    `endif
-        if (~reset & ~(count <= 3'h4)) begin
-          $fwrite(32'h80000002,"Assertion failed\n    at Fifo.scala:92 assert(count <= n.U)\n"); // @[Fifo.scala 92:9]
-        end
-    `ifdef PRINTF_COND
-      end
-    `endif
-    `endif // SYNTHESIS
-    `ifndef SYNTHESIS
-    `ifdef STOP_COND
-      if (`STOP_COND) begin
-    `endif
-        if (_T_10 & ~(~(io_in_ready & count == 3'h4))) begin
-          $fatal; // @[Fifo.scala 93:9]
-        end
-    `ifdef STOP_COND
-      end
-    `endif
-    `endif // SYNTHESIS
-    `ifndef SYNTHESIS
-    `ifdef PRINTF_COND
-      if (`PRINTF_COND) begin
-    `endif
-        if (_T_10 & ~(~(io_in_ready & count == 3'h4))) begin
-          $fwrite(32'h80000002,
-            "Assertion failed\n    at Fifo.scala:93 assert(!(!passReady.B && io.in.ready && count === n.U))\n"); // @[Fifo.scala 93:9]
-        end
-    `ifdef PRINTF_COND
-      end
-    `endif
-    `endif // SYNTHESIS
-  end
-  always @(posedge clock or posedge reset) begin
-    if (reset) begin // @[Fifo.scala 57:14]
-      rvalid <= 1'h0; // @[Fifo.scala 58:12]
-    end else begin
-      rvalid <= winc | _GEN_4;
-    end
-  end
-  always @(posedge clock or posedge reset) begin
-    if (reset) begin // @[Fifo.scala 64:51]
-      wready <= 1'h0;
-    end else begin
-      wready <= _wready_T_6 | _wready_T_8;
-    end
-  end
-  always @(posedge clock or posedge reset) begin
-    if (reset) begin // @[Fifo.scala 40:15]
-      raddr <= 2'h0; // @[Fifo.scala 41:17]
-    end else if (rinc) begin // @[Fifo.scala 27:22]
-      if (raddr == 2'h2) begin
-        raddr <= 2'h0;
-      end else begin
-        raddr <= _raddr_T_2;
-      end
-    end
-  end
-  always @(posedge clock or posedge reset) begin
-    if (reset) begin // @[Fifo.scala 36:15]
-      waddr <= 2'h0; // @[Fifo.scala 37:17]
-    end else if (winc) begin // @[Fifo.scala 28:22]
-      if (waddr == 2'h2) begin
-        waddr <= 2'h0;
-      end else begin
-        waddr <= _waddr_T_2;
-      end
-    end
-  end
-  always @(posedge clock or posedge reset) begin
-    if (reset) begin // @[Fifo.scala 51:22]
-      count <= 3'h0; // @[Fifo.scala 52:11]
-    end else if (winc & ~oen) begin // @[Fifo.scala 53:29]
-      count <= _count_T_1; // @[Fifo.scala 54:11]
-    end else if (~winc & oen) begin // @[Fifo.scala 29:22]
-      count <= _count_T_3;
-    end
-  end
-// Register and memory initialization
-`ifdef RANDOMIZE_GARBAGE_ASSIGN
-`define RANDOMIZE
-`endif
-`ifdef RANDOMIZE_INVALID_ASSIGN
-`define RANDOMIZE
-`endif
-`ifdef RANDOMIZE_REG_INIT
-`define RANDOMIZE
-`endif
-`ifdef RANDOMIZE_MEM_INIT
-`define RANDOMIZE
-`endif
-`ifndef RANDOM
-`define RANDOM $random
-`endif
-`ifdef RANDOMIZE_MEM_INIT
-  integer initvar;
-`endif
-`ifndef SYNTHESIS
-`ifdef FIRRTL_BEFORE_INITIAL
-`FIRRTL_BEFORE_INITIAL
-`endif
-initial begin
-  `ifdef RANDOMIZE
-    `ifdef INIT_RANDOM
-      `INIT_RANDOM
-    `endif
-    `ifndef VERILATOR
-      `ifdef RANDOMIZE_DELAY
-        #`RANDOMIZE_DELAY begin end
-      `else
-        #0.002 begin end
-      `endif
-    `endif
-`ifdef RANDOMIZE_GARBAGE_ASSIGN
-  _RAND_1 = {1{`RANDOM}};
-`endif // RANDOMIZE_GARBAGE_ASSIGN
-`ifdef RANDOMIZE_MEM_INIT
-  _RAND_0 = {1{`RANDOM}};
-  for (initvar = 0; initvar < 3; initvar = initvar+1)
-    mem[initvar] = _RAND_0[4:0];
-`endif // RANDOMIZE_MEM_INIT
-`ifdef RANDOMIZE_REG_INIT
-  _RAND_2 = {1{`RANDOM}};
-  rdata = _RAND_2[4:0];
-  _RAND_3 = {1{`RANDOM}};
-  rvalid = _RAND_3[0:0];
-  _RAND_4 = {1{`RANDOM}};
-  wready = _RAND_4[0:0];
-  _RAND_5 = {1{`RANDOM}};
-  raddr = _RAND_5[1:0];
-  _RAND_6 = {1{`RANDOM}};
-  waddr = _RAND_6[1:0];
-  _RAND_7 = {1{`RANDOM}};
-  count = _RAND_7[2:0];
-`endif // RANDOMIZE_REG_INIT
-  if (reset) begin
-    rvalid = 1'h0;
-  end
-  if (reset) begin
-    wready = 1'h0;
-  end
-  if (reset) begin
-    raddr = 2'h0;
-  end
-  if (reset) begin
-    waddr = 2'h0;
-  end
-  if (reset) begin
-    count = 3'h0;
-  end
-  `endif // RANDOMIZE
-end // initial
-`ifdef FIRRTL_AFTER_INITIAL
-`FIRRTL_AFTER_INITIAL
-`endif
-`endif // SYNTHESIS
-endmodule
-module FCvtsw_1(
-  input         clock,
-  input         reset,
-  input         io_in_valid,
-  input         io_in_unsigned,
-  input  [4:0]  io_in_addr,
-  input  [31:0] io_in_rs,
-  output        io_out_valid,
-  output [4:0]  io_out_addr,
-  output [31:0] io_out_fd
-);
-  wire  fcvtsw_clock; // @[FCvtsw.scala 8:18]
-  wire  fcvtsw_io_unsigned; // @[FCvtsw.scala 8:18]
-  wire  fcvtsw_io_in_ready; // @[FCvtsw.scala 8:18]
-  wire  fcvtsw_io_in_valid; // @[FCvtsw.scala 8:18]
-  wire [31:0] fcvtsw_io_in_bits; // @[FCvtsw.scala 8:18]
-  wire  fcvtsw_io_out_valid; // @[FCvtsw.scala 8:18]
-  wire [31:0] fcvtsw_io_out_bits; // @[FCvtsw.scala 8:18]
-  wire  ff_clock; // @[Fifo.scala 8:11]
-  wire  ff_reset; // @[Fifo.scala 8:11]
-  wire  ff_io_in_ready; // @[Fifo.scala 8:11]
-  wire  ff_io_in_valid; // @[Fifo.scala 8:11]
-  wire [4:0] ff_io_in_bits; // @[Fifo.scala 8:11]
-  wire  ff_io_out_ready; // @[Fifo.scala 8:11]
-  wire  ff_io_out_valid; // @[Fifo.scala 8:11]
-  wire [4:0] ff_io_out_bits; // @[Fifo.scala 8:11]
-  wire  _T_4 = ~reset; // @[FCvtsw.scala 39:9]
-  FCvtsw fcvtsw ( // @[FCvtsw.scala 8:18]
-    .clock(fcvtsw_clock),
-    .io_unsigned(fcvtsw_io_unsigned),
-    .io_in_ready(fcvtsw_io_in_ready),
-    .io_in_valid(fcvtsw_io_in_valid),
-    .io_in_bits(fcvtsw_io_in_bits),
-    .io_out_valid(fcvtsw_io_out_valid),
-    .io_out_bits(fcvtsw_io_out_bits)
-  );
-  Fifo_2 ff ( // @[Fifo.scala 8:11]
-    .clock(ff_clock),
-    .reset(ff_reset),
-    .io_in_ready(ff_io_in_ready),
-    .io_in_valid(ff_io_in_valid),
-    .io_in_bits(ff_io_in_bits),
-    .io_out_ready(ff_io_out_ready),
-    .io_out_valid(ff_io_out_valid),
-    .io_out_bits(ff_io_out_bits)
-  );
-  assign io_out_valid = fcvtsw_io_out_valid; // @[FCvtsw.scala 43:16]
-  assign io_out_addr = ff_io_out_bits; // @[FCvtsw.scala 44:15]
-  assign io_out_fd = fcvtsw_io_out_bits; // @[FCvtsw.scala 45:13]
-  assign fcvtsw_clock = clock;
-  assign fcvtsw_io_unsigned = io_in_unsigned; // @[FCvtsw.scala 33:22]
-  assign fcvtsw_io_in_valid = io_in_valid; // @[FCvtsw.scala 32:22]
-  assign fcvtsw_io_in_bits = io_in_rs; // @[FCvtsw.scala 34:22]
-  assign ff_clock = clock;
-  assign ff_reset = reset;
-  assign ff_io_in_valid = io_in_valid; // @[FCvtsw.scala 37:18]
-  assign ff_io_in_bits = io_in_addr; // @[FCvtsw.scala 38:18]
-  assign ff_io_out_ready = fcvtsw_io_out_valid; // @[FCvtsw.scala 40:19]
-  always @(posedge clock) begin
-    `ifndef SYNTHESIS
-    `ifdef STOP_COND
-      if (`STOP_COND) begin
-    `endif
-        if (~reset & ~(~(ff_io_in_valid & ~ff_io_in_ready))) begin
-          $fatal; // @[FCvtsw.scala 39:9]
-        end
-    `ifdef STOP_COND
-      end
-    `endif
-    `endif // SYNTHESIS
-    `ifndef SYNTHESIS
-    `ifdef PRINTF_COND
-      if (`PRINTF_COND) begin
-    `endif
-        if (~reset & ~(~(ff_io_in_valid & ~ff_io_in_ready))) begin
-          $fwrite(32'h80000002,"Assertion failed\n    at FCvtsw.scala:39 assert(!(ff.io.in.valid && !ff.io.in.ready))\n"
-            ); // @[FCvtsw.scala 39:9]
-        end
-    `ifdef PRINTF_COND
-      end
-    `endif
-    `endif // SYNTHESIS
-    `ifndef SYNTHESIS
-    `ifdef STOP_COND
-      if (`STOP_COND) begin
-    `endif
-        if (_T_4 & ~(~(~ff_io_out_valid & ff_io_out_ready))) begin
-          $fatal; // @[FCvtsw.scala 41:9]
-        end
-    `ifdef STOP_COND
-      end
-    `endif
-    `endif // SYNTHESIS
-    `ifndef SYNTHESIS
-    `ifdef PRINTF_COND
-      if (`PRINTF_COND) begin
-    `endif
-        if (_T_4 & ~(~(~ff_io_out_valid & ff_io_out_ready))) begin
-          $fwrite(32'h80000002,
-            "Assertion failed\n    at FCvtsw.scala:41 assert(!(!ff.io.out.valid && ff.io.out.ready))\n"); // @[FCvtsw.scala 41:9]
-        end
-    `ifdef PRINTF_COND
-      end
-    `endif
-    `endif // SYNTHESIS
-  end
-endmodule
-module FCvtws(
-  input         clock,
-  input         reset,
-  input         io_unsigned,
-  output        io_in_ready,
-  input         io_in_valid,
-  input  [31:0] io_in_bits,
-  output        io_out_valid,
-  output [31:0] io_out_bits
-);
-`ifdef RANDOMIZE_REG_INIT
-  reg [31:0] _RAND_0;
-  reg [31:0] _RAND_1;
-  reg [31:0] _RAND_2;
-  reg [31:0] _RAND_3;
-  reg [31:0] _RAND_4;
-  reg [31:0] _RAND_5;
-  reg [31:0] _RAND_6;
-  reg [31:0] _RAND_7;
-  reg [31:0] _RAND_8;
-  reg [31:0] _RAND_9;
-`endif // RANDOMIZE_REG_INIT
-  reg  active1; // @[FCvtws.scala 23:20]
-  reg  active2; // @[FCvtws.scala 24:20]
-  reg  state1__sign; // @[FCvtws.scala 26:19]
-  reg  state1__smin; // @[FCvtws.scala 26:19]
-  reg  state1__smax; // @[FCvtws.scala 26:19]
-  reg  state1__umax; // @[FCvtws.scala 26:19]
-  reg  state1__zero; // @[FCvtws.scala 26:19]
-  reg [31:0] state1__int; // @[FCvtws.scala 26:19]
-  reg [2:0] state1__grs; // @[FCvtws.scala 26:19]
-  reg [31:0] state2_int; // @[FCvtws.scala 27:19]
-  wire  update1 = io_in_valid & io_in_ready; // @[FCvtws.scala 29:29]
-  wire  state1_sign = io_in_bits[31]; // @[FCvtws.scala 72:18]
-  wire [7:0] state1_exp = io_in_bits[30:23]; // @[FCvtws.scala 73:17]
-  wire  _state1_man_T = state1_exp != 8'h0; // @[FCvtws.scala 74:33]
-  wire [33:0] state1_man = {2'h0,_state1_man_T,io_in_bits[22:0],8'h0}; // @[Cat.scala 31:58]
-  wire  _state1_smin_T = ~io_unsigned; // @[FCvtws.scala 77:16]
-  wire  _state1_smin_T_2 = ~io_unsigned & state1_exp >= 8'h9e; // @[FCvtws.scala 77:26]
-  wire  _state1_smin_T_8 = state1_exp == 8'hff & io_in_bits[22:0] != 23'h0; // @[FBase.scala 68:37]
-  wire  _state1_smin_T_9 = ~_state1_smin_T_8; // @[FCvtws.scala 77:54]
-  wire  state1_smin = ~io_unsigned & state1_exp >= 8'h9e & state1_sign & ~_state1_smin_T_8; // @[FCvtws.scala 77:51]
-  wire  _state1_smax_T_3 = ~state1_sign; // @[FCvtws.scala 78:45]
-  wire  state1_smax = _state1_smin_T_2 & ~state1_sign | _state1_smin_T_8 & _state1_smin_T; // @[FCvtws.scala 78:51]
-  wire  state1_umax = io_unsigned & state1_exp >= 8'h9f & _state1_smax_T_3 | _state1_smin_T_8 & io_unsigned; // @[FCvtws.scala 79:51]
-  wire  state1_zero = io_unsigned & state1_sign & _state1_smin_T_9; // @[FCvtws.scala 80:34]
-  wire [3:0] _state1_T = {state1_smin,state1_smax,state1_umax,state1_zero}; // @[Cat.scala 31:58]
-  wire [1:0] _state1_T_5 = _state1_T[0] + _state1_T[1]; // @[Bitwise.scala 48:55]
-  wire [1:0] _state1_T_7 = _state1_T[2] + _state1_T[3]; // @[Bitwise.scala 48:55]
-  wire [2:0] _state1_T_9 = _state1_T_5 + _state1_T_7; // @[Bitwise.scala 48:55]
-  wire [7:0] _state1_shf_T_2 = 8'h9e - state1_exp; // @[FCvtws.scala 83:46]
-  wire [5:0] state1_shf = state1_exp <= 8'h7c ? 6'h22 : _state1_shf_T_2[5:0]; // @[FCvtws.scala 83:18]
-  wire [5:0] _state1_shf2_T_2 = state1_shf - 6'h2; // @[FCvtws.scala 84:37]
-  wire [5:0] state1_shf2 = state1_shf >= 6'h2 ? _state1_shf2_T_2 : 6'h0; // @[FCvtws.scala 84:19]
-  wire [62:0] _state1_stickymask_T_4 = 63'hffffffff << state1_shf2[4:0]; // @[FCvtws.scala 85:64]
-  wire [62:0] _state1_stickymask_T_5 = ~_state1_stickymask_T_4; // @[FCvtws.scala 85:49]
-  wire [62:0] state1_stickymask = state1_shf2[5] ? 63'hffffffff : _state1_stickymask_T_5; // @[FCvtws.scala 85:25]
-  wire [33:0] _GEN_11 = {{2'd0}, state1_stickymask[31:0]}; // @[FCvtws.scala 86:23]
-  wire [33:0] _state1_sticky_T_1 = state1_man & _GEN_11; // @[FCvtws.scala 86:23]
-  wire  state1_sticky = _state1_sticky_T_1 != 34'h0; // @[FCvtws.scala 86:43]
-  wire [5:0] _state1_grs_T_1 = state1_shf - 6'h1; // @[FCvtws.scala 87:27]
-  wire [33:0] _state1_grs_T_2 = state1_man >> _state1_grs_T_1; // @[FCvtws.scala 87:22]
-  wire [33:0] _state1_grs_T_6 = state1_man >> _state1_shf2_T_2; // @[FCvtws.scala 87:38]
-  wire [2:0] state1_grs = {_state1_grs_T_2[0],_state1_grs_T_6[0],state1_sticky}; // @[Cat.scala 31:58]
-  wire [33:0] _state1_man_shf_T = state1_man >> state1_shf; // @[FCvtws.scala 89:24]
-  wire [31:0] state1_man_shf = _state1_man_shf_T[31:0]; // @[FCvtws.scala 89:31]
-  wire  state1_state1_sign = _state1_smin_T & state1_sign & ~state1_smin; // @[FCvtws.scala 92:38]
-  wire [3:0] state2_r = {state1__int[0],state1__grs}; // @[Cat.scala 31:58]
-  wire  _state2_round_round_T_1 = state2_r[2:0] != 3'h0; // @[FBase.scala 92:30]
-  wire  _state2_round_round_T_2 = ~state1__sign; // @[FBase.scala 92:41]
-  wire  _state2_round_round_T_3 = state2_r[2:0] != 3'h0 & ~state1__sign; // @[FBase.scala 92:38]
-  wire  _state2_round_round_T_6 = _state2_round_round_T_1 & state1__sign; // @[FBase.scala 93:38]
-  wire  _state2_round_round_T_11 = state2_r[2:0] > 3'h4 | state2_r == 4'hc; // @[FBase.scala 95:36]
-  wire [3:0] state2_round_round = {_state2_round_round_T_3,_state2_round_round_T_6,1'h0,_state2_round_round_T_11}; // @[Cat.scala 31:58]
-  wire  state2_round = state2_round_round[0]; // @[FBase.scala 96:10]
-  wire [31:0] _state2_rint_T_2 = state1__int + 32'h1; // @[FCvtws.scala 112:57]
-  wire [31:0] _state2_rint_T_3 = state2_round ? _state2_rint_T_2 : state1__int; // @[FCvtws.scala 112:37]
-  wire [31:0] _state2_rint_T_5 = 32'h0 - state1__int; // @[FCvtws.scala 113:45]
-  wire [31:0] _state2_rint_T_7 = _state2_rint_T_5 - 32'h1; // @[FCvtws.scala 113:57]
-  wire [31:0] _state2_rint_T_10 = state2_round ? _state2_rint_T_7 : _state2_rint_T_5; // @[FCvtws.scala 113:37]
-  wire [31:0] state2_rint = _state2_round_round_T_2 ? _state2_rint_T_3 : _state2_rint_T_10; // @[FCvtws.scala 112:19]
-  wire [31:0] _state2_state2_int_T_2 = state1__zero ? 32'h0 : state2_rint; // @[FCvtws.scala 117:22]
-  assign io_in_ready = 1'h1; // @[FCvtws.scala 48:43]
-  assign io_out_valid = active2; // @[FCvtws.scala 49:16]
-  assign io_out_bits = state2_int; // @[FCvtws.scala 50:15]
-  always @(posedge clock) begin
-    active1 <= io_in_valid & io_in_ready; // @[FCvtws.scala 29:29]
-    active2 <= active1; // @[FCvtws.scala 36:34 37:13 24:20]
-    if (update1) begin // @[FCvtws.scala 40:18]
-      state1__sign <= state1_state1_sign; // @[FCvtws.scala 41:12]
-    end
-    if (update1) begin // @[FCvtws.scala 40:18]
-      state1__smin <= state1_smin; // @[FCvtws.scala 41:12]
-    end
-    if (update1) begin // @[FCvtws.scala 40:18]
-      state1__smax <= state1_smax; // @[FCvtws.scala 41:12]
-    end
-    if (update1) begin // @[FCvtws.scala 40:18]
-      state1__umax <= state1_umax; // @[FCvtws.scala 41:12]
-    end
-    if (update1) begin // @[FCvtws.scala 40:18]
-      state1__zero <= state1_zero; // @[FCvtws.scala 41:12]
-    end
-    if (update1) begin // @[FCvtws.scala 40:18]
-      state1__int <= state1_man_shf; // @[FCvtws.scala 41:12]
-    end
-    if (update1) begin // @[FCvtws.scala 40:18]
-      state1__grs <= state1_grs; // @[FCvtws.scala 41:12]
-    end
-    if (active1) begin // @[FCvtws.scala 44:18]
-      if (state1__umax) begin // @[FCvtws.scala 114:22]
-        state2_int <= 32'hffffffff;
-      end else if (state1__smin) begin // @[FCvtws.scala 115:22]
-        state2_int <= 32'h80000000;
-      end else if (state1__smax) begin // @[FCvtws.scala 116:22]
-        state2_int <= 32'h7fffffff;
-      end else begin
-        state2_int <= _state2_state2_int_T_2;
-      end
-    end
-    `ifndef SYNTHESIS
-    `ifdef STOP_COND
-      if (`STOP_COND) begin
-    `endif
-        if (update1 & ~reset & ~(_state1_T_9 <= 3'h1)) begin
-          $fatal; // @[FCvtws.scala 81:11]
-        end
-    `ifdef STOP_COND
-      end
-    `endif
-    `endif // SYNTHESIS
-    `ifndef SYNTHESIS
-    `ifdef PRINTF_COND
-      if (`PRINTF_COND) begin
-    `endif
-        if (update1 & ~reset & ~(_state1_T_9 <= 3'h1)) begin
-          $fwrite(32'h80000002,
-            "Assertion failed\n    at FCvtws.scala:81 assert(PopCount(Cat(smin, smax, umax, zero)) <= 1.U)\n"); // @[FCvtws.scala 81:11]
-        end
-    `ifdef PRINTF_COND
-      end
-    `endif
-    `endif // SYNTHESIS
-  end
-// Register and memory initialization
-`ifdef RANDOMIZE_GARBAGE_ASSIGN
-`define RANDOMIZE
-`endif
-`ifdef RANDOMIZE_INVALID_ASSIGN
-`define RANDOMIZE
-`endif
-`ifdef RANDOMIZE_REG_INIT
-`define RANDOMIZE
-`endif
-`ifdef RANDOMIZE_MEM_INIT
-`define RANDOMIZE
-`endif
-`ifndef RANDOM
-`define RANDOM $random
-`endif
-`ifdef RANDOMIZE_MEM_INIT
-  integer initvar;
-`endif
-`ifndef SYNTHESIS
-`ifdef FIRRTL_BEFORE_INITIAL
-`FIRRTL_BEFORE_INITIAL
-`endif
-initial begin
-  `ifdef RANDOMIZE
-    `ifdef INIT_RANDOM
-      `INIT_RANDOM
-    `endif
-    `ifndef VERILATOR
-      `ifdef RANDOMIZE_DELAY
-        #`RANDOMIZE_DELAY begin end
-      `else
-        #0.002 begin end
-      `endif
-    `endif
-`ifdef RANDOMIZE_REG_INIT
-  _RAND_0 = {1{`RANDOM}};
-  active1 = _RAND_0[0:0];
-  _RAND_1 = {1{`RANDOM}};
-  active2 = _RAND_1[0:0];
-  _RAND_2 = {1{`RANDOM}};
-  state1__sign = _RAND_2[0:0];
-  _RAND_3 = {1{`RANDOM}};
-  state1__smin = _RAND_3[0:0];
-  _RAND_4 = {1{`RANDOM}};
-  state1__smax = _RAND_4[0:0];
-  _RAND_5 = {1{`RANDOM}};
-  state1__umax = _RAND_5[0:0];
-  _RAND_6 = {1{`RANDOM}};
-  state1__zero = _RAND_6[0:0];
-  _RAND_7 = {1{`RANDOM}};
-  state1__int = _RAND_7[31:0];
-  _RAND_8 = {1{`RANDOM}};
-  state1__grs = _RAND_8[2:0];
-  _RAND_9 = {1{`RANDOM}};
-  state2_int = _RAND_9[31:0];
-`endif // RANDOMIZE_REG_INIT
-  `endif // RANDOMIZE
-end // initial
-`ifdef FIRRTL_AFTER_INITIAL
-`FIRRTL_AFTER_INITIAL
-`endif
-`endif // SYNTHESIS
-endmodule
-module FCvtws_1(
-  input         clock,
-  input         reset,
-  input         io_in_valid,
-  input         io_in_unsigned,
-  input  [4:0]  io_in_addr,
-  input  [31:0] io_in_fs,
-  output        io_out_valid,
-  output [4:0]  io_out_addr,
-  output [31:0] io_out_rd
-);
-  wire  fcvtws_clock; // @[FCvtws.scala 8:18]
-  wire  fcvtws_reset; // @[FCvtws.scala 8:18]
-  wire  fcvtws_io_unsigned; // @[FCvtws.scala 8:18]
-  wire  fcvtws_io_in_ready; // @[FCvtws.scala 8:18]
-  wire  fcvtws_io_in_valid; // @[FCvtws.scala 8:18]
-  wire [31:0] fcvtws_io_in_bits; // @[FCvtws.scala 8:18]
-  wire  fcvtws_io_out_valid; // @[FCvtws.scala 8:18]
-  wire [31:0] fcvtws_io_out_bits; // @[FCvtws.scala 8:18]
-  wire  ff_clock; // @[Fifo.scala 8:11]
-  wire  ff_reset; // @[Fifo.scala 8:11]
-  wire  ff_io_in_ready; // @[Fifo.scala 8:11]
-  wire  ff_io_in_valid; // @[Fifo.scala 8:11]
-  wire [4:0] ff_io_in_bits; // @[Fifo.scala 8:11]
-  wire  ff_io_out_ready; // @[Fifo.scala 8:11]
-  wire  ff_io_out_valid; // @[Fifo.scala 8:11]
-  wire [4:0] ff_io_out_bits; // @[Fifo.scala 8:11]
-  wire  _T_4 = ~reset; // @[FCvtws.scala 38:9]
-  FCvtws fcvtws ( // @[FCvtws.scala 8:18]
-    .clock(fcvtws_clock),
-    .reset(fcvtws_reset),
-    .io_unsigned(fcvtws_io_unsigned),
-    .io_in_ready(fcvtws_io_in_ready),
-    .io_in_valid(fcvtws_io_in_valid),
-    .io_in_bits(fcvtws_io_in_bits),
-    .io_out_valid(fcvtws_io_out_valid),
-    .io_out_bits(fcvtws_io_out_bits)
-  );
-  Fifo_2 ff ( // @[Fifo.scala 8:11]
-    .clock(ff_clock),
-    .reset(ff_reset),
-    .io_in_ready(ff_io_in_ready),
-    .io_in_valid(ff_io_in_valid),
-    .io_in_bits(ff_io_in_bits),
-    .io_out_ready(ff_io_out_ready),
-    .io_out_valid(ff_io_out_valid),
-    .io_out_bits(ff_io_out_bits)
-  );
-  assign io_out_valid = fcvtws_io_out_valid; // @[FCvtws.scala 42:16]
-  assign io_out_addr = ff_io_out_bits; // @[FCvtws.scala 43:15]
-  assign io_out_rd = fcvtws_io_out_bits; // @[FCvtws.scala 44:13]
-  assign fcvtws_clock = clock;
-  assign fcvtws_reset = reset;
-  assign fcvtws_io_unsigned = io_in_unsigned; // @[FCvtws.scala 31:22]
-  assign fcvtws_io_in_valid = io_in_valid; // @[FCvtws.scala 30:22]
-  assign fcvtws_io_in_bits = io_in_fs; // @[FCvtws.scala 33:22]
-  assign ff_clock = clock;
-  assign ff_reset = reset;
-  assign ff_io_in_valid = io_in_valid; // @[FCvtws.scala 36:18]
-  assign ff_io_in_bits = io_in_addr; // @[FCvtws.scala 37:18]
-  assign ff_io_out_ready = fcvtws_io_out_valid; // @[FCvtws.scala 39:19]
-  always @(posedge clock) begin
-    `ifndef SYNTHESIS
-    `ifdef STOP_COND
-      if (`STOP_COND) begin
-    `endif
-        if (~reset & ~(~(ff_io_in_valid & ~ff_io_in_ready))) begin
-          $fatal; // @[FCvtws.scala 38:9]
-        end
-    `ifdef STOP_COND
-      end
-    `endif
-    `endif // SYNTHESIS
-    `ifndef SYNTHESIS
-    `ifdef PRINTF_COND
-      if (`PRINTF_COND) begin
-    `endif
-        if (~reset & ~(~(ff_io_in_valid & ~ff_io_in_ready))) begin
-          $fwrite(32'h80000002,"Assertion failed\n    at FCvtws.scala:38 assert(!(ff.io.in.valid && !ff.io.in.ready))\n"
-            ); // @[FCvtws.scala 38:9]
-        end
-    `ifdef PRINTF_COND
-      end
-    `endif
-    `endif // SYNTHESIS
-    `ifndef SYNTHESIS
-    `ifdef STOP_COND
-      if (`STOP_COND) begin
-    `endif
-        if (_T_4 & ~(~(~ff_io_out_valid & ff_io_out_ready))) begin
-          $fatal; // @[FCvtws.scala 40:9]
-        end
-    `ifdef STOP_COND
-      end
-    `endif
-    `endif // SYNTHESIS
-    `ifndef SYNTHESIS
-    `ifdef PRINTF_COND
-      if (`PRINTF_COND) begin
-    `endif
-        if (_T_4 & ~(~(~ff_io_out_valid & ff_io_out_ready))) begin
-          $fwrite(32'h80000002,
-            "Assertion failed\n    at FCvtws.scala:40 assert(!(!ff.io.out.valid && ff.io.out.ready))\n"); // @[FCvtws.scala 40:9]
-        end
-    `ifdef PRINTF_COND
-      end
-    `endif
-    `endif // SYNTHESIS
-  end
-endmodule
-module Fpu(
-  input         clock,
-  input         reset,
-  input         io_req_0_valid,
-  input  [4:0]  io_req_0_raddr_0,
-  input  [4:0]  io_req_0_raddr_1,
-  input  [4:0]  io_req_0_raddr_2,
-  input  [4:0]  io_req_0_waddr,
-  input  [26:0] io_req_0_op,
-  output        io_req_0_busyFDiv,
-  output        io_req_0_busyFSqrt,
-  input  [4:0]  io_req_1_raddr_1,
-  input  [26:0] io_req_1_op,
-  input  [4:0]  io_req_2_raddr_1,
-  input  [26:0] io_req_2_op,
-  input  [4:0]  io_req_3_raddr_1,
-  input  [26:0] io_req_3_op,
-  output [31:0] io_fbusPort_data,
-  input         io_fwriteData_valid,
-  input  [4:0]  io_fwriteData_addr,
-  input  [31:0] io_fwriteData_data,
-  input  [31:0] io_readData_data,
-  output        io_writeData_0_valid,
-  output [4:0]  io_writeData_0_addr,
-  output [31:0] io_writeData_0_data,
-  output        io_writeData_1_valid,
-  output [4:0]  io_writeData_1_addr,
-  output [31:0] io_writeData_1_data,
-  output [31:0] io_fs_0_data,
-  output [31:0] io_fs_1_data,
-  output [31:0] io_fs_2_data,
-  output [31:0] io_fs_3_data,
-  output [31:0] io_fscoreboard
-);
-`ifdef RANDOMIZE_REG_INIT
-  reg [31:0] _RAND_0;
-  reg [31:0] _RAND_1;
-  reg [31:0] _RAND_2;
-  reg [31:0] _RAND_3;
-  reg [31:0] _RAND_4;
-  reg [31:0] _RAND_5;
-  reg [31:0] _RAND_6;
-`endif // RANDOMIZE_REG_INIT
-  wire  fregfile_clock; // @[FRegfile.scala 9:18]
-  wire  fregfile_reset; // @[FRegfile.scala 9:18]
-  wire  fregfile_io_freadAddr_0_valid; // @[FRegfile.scala 9:18]
-  wire [4:0] fregfile_io_freadAddr_0_addr; // @[FRegfile.scala 9:18]
-  wire  fregfile_io_freadAddr_1_valid; // @[FRegfile.scala 9:18]
-  wire [4:0] fregfile_io_freadAddr_1_addr; // @[FRegfile.scala 9:18]
-  wire  fregfile_io_freadAddr_2_valid; // @[FRegfile.scala 9:18]
-  wire [4:0] fregfile_io_freadAddr_2_addr; // @[FRegfile.scala 9:18]
-  wire  fregfile_io_freadAddr_3_valid; // @[FRegfile.scala 9:18]
-  wire [4:0] fregfile_io_freadAddr_3_addr; // @[FRegfile.scala 9:18]
-  wire  fregfile_io_freadAddr_4_valid; // @[FRegfile.scala 9:18]
-  wire [4:0] fregfile_io_freadAddr_4_addr; // @[FRegfile.scala 9:18]
-  wire  fregfile_io_freadAddr_5_valid; // @[FRegfile.scala 9:18]
-  wire [4:0] fregfile_io_freadAddr_5_addr; // @[FRegfile.scala 9:18]
-  wire  fregfile_io_fwriteAddr_valid; // @[FRegfile.scala 9:18]
-  wire [4:0] fregfile_io_fwriteAddr_addr; // @[FRegfile.scala 9:18]
-  wire [31:0] fregfile_io_fbusPort_data; // @[FRegfile.scala 9:18]
-  wire [31:0] fregfile_io_freadData_0_data; // @[FRegfile.scala 9:18]
-  wire [31:0] fregfile_io_freadData_1_data; // @[FRegfile.scala 9:18]
-  wire [31:0] fregfile_io_freadData_2_data; // @[FRegfile.scala 9:18]
-  wire [31:0] fregfile_io_freadData_3_data; // @[FRegfile.scala 9:18]
-  wire [31:0] fregfile_io_freadData_4_data; // @[FRegfile.scala 9:18]
-  wire [31:0] fregfile_io_freadData_5_data; // @[FRegfile.scala 9:18]
-  wire  fregfile_io_fwriteData_0_valid; // @[FRegfile.scala 9:18]
-  wire [4:0] fregfile_io_fwriteData_0_addr; // @[FRegfile.scala 9:18]
-  wire [31:0] fregfile_io_fwriteData_0_data; // @[FRegfile.scala 9:18]
-  wire  fregfile_io_fwriteData_1_valid; // @[FRegfile.scala 9:18]
-  wire [4:0] fregfile_io_fwriteData_1_addr; // @[FRegfile.scala 9:18]
-  wire [31:0] fregfile_io_fwriteData_1_data; // @[FRegfile.scala 9:18]
-  wire  fregfile_io_fwriteData_2_valid; // @[FRegfile.scala 9:18]
-  wire [4:0] fregfile_io_fwriteData_2_addr; // @[FRegfile.scala 9:18]
-  wire [31:0] fregfile_io_fwriteData_2_data; // @[FRegfile.scala 9:18]
-  wire  fregfile_io_fwriteData_3_valid; // @[FRegfile.scala 9:18]
-  wire [4:0] fregfile_io_fwriteData_3_addr; // @[FRegfile.scala 9:18]
-  wire [31:0] fregfile_io_fwriteData_3_data; // @[FRegfile.scala 9:18]
-  wire  fregfile_io_fwriteData_4_valid; // @[FRegfile.scala 9:18]
-  wire [4:0] fregfile_io_fwriteData_4_addr; // @[FRegfile.scala 9:18]
-  wire [31:0] fregfile_io_fwriteData_4_data; // @[FRegfile.scala 9:18]
-  wire  fregfile_io_fwriteData_5_valid; // @[FRegfile.scala 9:18]
-  wire [4:0] fregfile_io_fwriteData_5_addr; // @[FRegfile.scala 9:18]
-  wire [31:0] fregfile_io_fwriteData_5_data; // @[FRegfile.scala 9:18]
-  wire [31:0] fregfile_io_fscoreboard; // @[FRegfile.scala 9:18]
-  wire  fadd_clock; // @[FAdd.scala 8:18]
-  wire  fadd_reset; // @[FAdd.scala 8:18]
-  wire  fadd_io_in_valid; // @[FAdd.scala 8:18]
-  wire [4:0] fadd_io_in_addr; // @[FAdd.scala 8:18]
-  wire [31:0] fadd_io_in_fs1; // @[FAdd.scala 8:18]
-  wire [31:0] fadd_io_in_fs2; // @[FAdd.scala 8:18]
-  wire [26:0] fadd_io_in_op; // @[FAdd.scala 8:18]
-  wire  fadd_io_out_valid; // @[FAdd.scala 8:18]
-  wire [4:0] fadd_io_out_addr; // @[FAdd.scala 8:18]
-  wire [31:0] fadd_io_out_fd; // @[FAdd.scala 8:18]
-  wire  fmadd_clock; // @[FMAdd.scala 8:18]
-  wire  fmadd_reset; // @[FMAdd.scala 8:18]
-  wire  fmadd_io_in_valid; // @[FMAdd.scala 8:18]
-  wire [4:0] fmadd_io_in_addr; // @[FMAdd.scala 8:18]
-  wire [31:0] fmadd_io_in_fs1; // @[FMAdd.scala 8:18]
-  wire [31:0] fmadd_io_in_fs2; // @[FMAdd.scala 8:18]
-  wire [31:0] fmadd_io_in_fs3; // @[FMAdd.scala 8:18]
-  wire [26:0] fmadd_io_in_op; // @[FMAdd.scala 8:18]
-  wire  fmadd_io_out_valid; // @[FMAdd.scala 8:18]
-  wire [4:0] fmadd_io_out_addr; // @[FMAdd.scala 8:18]
-  wire [31:0] fmadd_io_out_fd; // @[FMAdd.scala 8:18]
-  wire  fdiv_clock; // @[FDiv.scala 8:18]
-  wire  fdiv_reset; // @[FDiv.scala 8:18]
-  wire  fdiv_io_in_valid; // @[FDiv.scala 8:18]
-  wire  fdiv_io_in_ready; // @[FDiv.scala 8:18]
-  wire [4:0] fdiv_io_in_addr; // @[FDiv.scala 8:18]
-  wire [31:0] fdiv_io_in_fs1; // @[FDiv.scala 8:18]
-  wire [31:0] fdiv_io_in_fs2; // @[FDiv.scala 8:18]
-  wire  fdiv_io_out_valid; // @[FDiv.scala 8:18]
-  wire [4:0] fdiv_io_out_addr; // @[FDiv.scala 8:18]
-  wire [31:0] fdiv_io_out_fd; // @[FDiv.scala 8:18]
-  wire  fsqrt_clock; // @[FSqrt.scala 8:18]
-  wire  fsqrt_reset; // @[FSqrt.scala 8:18]
-  wire  fsqrt_io_in_valid; // @[FSqrt.scala 8:18]
-  wire  fsqrt_io_in_ready; // @[FSqrt.scala 8:18]
-  wire [4:0] fsqrt_io_in_addr; // @[FSqrt.scala 8:18]
-  wire [31:0] fsqrt_io_in_fs; // @[FSqrt.scala 8:18]
-  wire  fsqrt_io_out_valid; // @[FSqrt.scala 8:18]
-  wire [4:0] fsqrt_io_out_addr; // @[FSqrt.scala 8:18]
-  wire [31:0] fsqrt_io_out_fd; // @[FSqrt.scala 8:18]
-  wire  fcvtsw_clock; // @[FCvtsw.scala 8:18]
-  wire  fcvtsw_reset; // @[FCvtsw.scala 8:18]
-  wire  fcvtsw_io_in_valid; // @[FCvtsw.scala 8:18]
-  wire  fcvtsw_io_in_unsigned; // @[FCvtsw.scala 8:18]
-  wire [4:0] fcvtsw_io_in_addr; // @[FCvtsw.scala 8:18]
-  wire [31:0] fcvtsw_io_in_rs; // @[FCvtsw.scala 8:18]
-  wire  fcvtsw_io_out_valid; // @[FCvtsw.scala 8:18]
-  wire [4:0] fcvtsw_io_out_addr; // @[FCvtsw.scala 8:18]
-  wire [31:0] fcvtsw_io_out_fd; // @[FCvtsw.scala 8:18]
-  wire  fcvtws_clock; // @[FCvtws.scala 8:18]
-  wire  fcvtws_reset; // @[FCvtws.scala 8:18]
-  wire  fcvtws_io_in_valid; // @[FCvtws.scala 8:18]
-  wire  fcvtws_io_in_unsigned; // @[FCvtws.scala 8:18]
-  wire [4:0] fcvtws_io_in_addr; // @[FCvtws.scala 8:18]
-  wire [31:0] fcvtws_io_in_fs; // @[FCvtws.scala 8:18]
-  wire  fcvtws_io_out_valid; // @[FCvtws.scala 8:18]
-  wire [4:0] fcvtws_io_out_addr; // @[FCvtws.scala 8:18]
-  wire [31:0] fcvtws_io_out_rd; // @[FCvtws.scala 8:18]
-  reg  valid; // @[Fpu.scala 105:22]
-  reg [4:0] addr; // @[Fpu.scala 106:17]
-  reg [26:0] op; // @[Fpu.scala 107:19]
-  reg  wfvalid; // @[Fpu.scala 109:24]
-  reg  wrvalid; // @[Fpu.scala 110:24]
-  reg [4:0] waddr; // @[Fpu.scala 111:18]
-  reg [31:0] wdata; // @[Fpu.scala 112:18]
-  wire  fopA = io_req_0_op[22]; // @[Fpu.scala 128:26]
-  wire  fopB = io_req_0_op[1] | io_req_0_op[26]; // @[Fpu.scala 130:36]
-  wire  _fopAB_T_6 = io_req_0_op[6] | io_req_0_op[7] | io_req_0_op[8] | io_req_0_op[9]; // @[Fpu.scala 133:82]
-  wire  _fopAB_T_10 = _fopAB_T_6 | io_req_0_op[10] | io_req_0_op[14]; // @[Fpu.scala 134:57]
-  wire  _fopAB_T_14 = _fopAB_T_10 | io_req_0_op[15] | io_req_0_op[19]; // @[Fpu.scala 135:56]
-  wire  _fopAB_T_20 = _fopAB_T_14 | io_req_0_op[20] | io_req_0_op[21] | io_req_0_op[16]; // @[Fpu.scala 136:79]
-  wire  _fopAB_T_26 = _fopAB_T_20 | io_req_0_op[17] | io_req_0_op[18] | io_req_0_op[11]; // @[Fpu.scala 137:88]
-  wire  fopAB = _fopAB_T_26 | io_req_0_op[12] | io_req_0_op[13]; // @[Fpu.scala 138:59]
-  wire  _fopABC_T_4 = io_req_0_op[2] | io_req_0_op[3] | io_req_0_op[4]; // @[Fpu.scala 141:58]
-  wire  fopABC = _fopABC_T_4 | io_req_0_op[5]; // @[Fpu.scala 142:32]
-  wire  _fregfile_io_freadAddr_0_valid_T = fopABC | fopAB; // @[Fpu.scala 144:44]
-  wire  _fregfile_io_fwriteAddr_valid_T_6 = io_req_0_op[0] | io_req_0_op[2] | io_req_0_op[3] | io_req_0_op[4]; // @[Fpu.scala 178:84]
-  wire  _fregfile_io_fwriteAddr_valid_T_10 = _fregfile_io_fwriteAddr_valid_T_6 | io_req_0_op[5] | io_req_0_op[6]; // @[Fpu.scala 179:61]
-  wire  _fregfile_io_fwriteAddr_valid_T_16 = _fregfile_io_fwriteAddr_valid_T_10 | io_req_0_op[7] | io_req_0_op[8] |
-    io_req_0_op[9]; // @[Fpu.scala 180:83]
-  wire  _fregfile_io_fwriteAddr_valid_T_20 = _fregfile_io_fwriteAddr_valid_T_16 | io_req_0_op[10] | io_req_0_op[11]; // @[Fpu.scala 181:58]
-  wire  _fregfile_io_fwriteAddr_valid_T_26 = _fregfile_io_fwriteAddr_valid_T_20 | io_req_0_op[12] | io_req_0_op[13] |
-    io_req_0_op[14]; // @[Fpu.scala 182:88]
-  wire  _fregfile_io_fwriteAddr_valid_T_32 = _fregfile_io_fwriteAddr_valid_T_26 | io_req_0_op[15] | io_req_0_op[25] |
-    io_req_0_op[23]; // @[Fpu.scala 183:84]
-  wire  _fregfile_io_fwriteAddr_valid_T_34 = _fregfile_io_fwriteAddr_valid_T_32 | io_req_0_op[24]; // @[Fpu.scala 184:33]
-  wire  _fmadd_io_in_valid_T_4 = op[2] | op[3] | op[4]; // @[Fpu.scala 198:65]
-  wire  _fmadd_io_in_valid_T_8 = _fmadd_io_in_valid_T_4 | op[5] | op[8]; // @[Fpu.scala 199:59]
-  wire [1:0] _T = fadd_io_out_valid + fcvtsw_io_out_valid; // @[Fpu.scala 223:29]
-  wire  _T_3 = ~reset; // @[Fpu.scala 223:9]
-  wire  equal = fregfile_io_freadData_0_data == fregfile_io_freadData_1_data; // @[FBase.scala 106:24]
-  wire  lessthan = fregfile_io_freadData_0_data < fregfile_io_freadData_1_data; // @[FBase.scala 107:24]
-  wire [30:0] _zeroes_T_2 = fregfile_io_freadData_0_data[30:0] | fregfile_io_freadData_1_data[30:0]; // @[FBase.scala 108:31]
-  wire  zeroes = _zeroes_T_2 == 31'h0; // @[FBase.scala 108:44]
-  wire  sign1 = fregfile_io_freadData_0_data[31]; // @[FBase.scala 110:20]
-  wire  sign2 = fregfile_io_freadData_1_data[31]; // @[FBase.scala 111:20]
-  wire  _nan1_T_1 = fregfile_io_freadData_0_data[30:23] == 8'hff; // @[FBase.scala 113:27]
-  wire  _nan1_T_3 = fregfile_io_freadData_0_data[22:0] != 23'h0; // @[FBase.scala 113:50]
-  wire  nan1 = fregfile_io_freadData_0_data[30:23] == 8'hff & fregfile_io_freadData_0_data[22:0] != 23'h0; // @[FBase.scala 113:37]
-  wire  _nan2_T_1 = fregfile_io_freadData_1_data[30:23] == 8'hff; // @[FBase.scala 114:27]
-  wire  nan2 = fregfile_io_freadData_1_data[30:23] == 8'hff & fregfile_io_freadData_1_data[22:0] != 23'h0; // @[FBase.scala 114:37]
-  wire  nan = nan1 | nan2; // @[FBase.scala 115:20]
-  wire  _flt_T = sign1 != sign2; // @[FBase.scala 117:25]
-  wire  _flt_T_4 = sign1 ^ lessthan; // @[FBase.scala 118:36]
-  wire  _flt_T_5 = ~equal & (sign1 ^ lessthan); // @[FBase.scala 118:26]
-  wire  flt = sign1 != sign2 ? sign1 & ~zeroes : _flt_T_5; // @[FBase.scala 117:18]
-  wire  _fle_T_3 = equal | _flt_T_4; // @[FBase.scala 120:25]
-  wire  fle = _flt_T ? sign1 | zeroes : _fle_T_3; // @[FBase.scala 119:18]
-  wire  feq = equal | zeroes; // @[FBase.scala 121:21]
-  wire  flt_1 = flt & ~nan; // @[FBase.scala 127:10]
-  wire  fle_1 = fle & ~nan; // @[FBase.scala 127:23]
-  wire  feq_1 = feq & ~nan; // @[FBase.scala 127:36]
-  wire  fs1nans = _nan1_T_1 & ~fregfile_io_freadData_0_data[22] & fregfile_io_freadData_0_data[21:0] != 22'h0; // @[FBase.scala 136:47]
-  wire  fs1nanq = _nan1_T_1 & fregfile_io_freadData_0_data[22]; // @[FBase.scala 137:37]
-  wire  fs1zero = fregfile_io_freadData_0_data[30:0] == 31'h0; // @[FBase.scala 138:26]
-  wire [1:0] _T_11 = fs1nans + fs1nanq; // @[FBase.scala 139:28]
-  wire [1:0] _GEN_4 = {{1'd0}, fs1zero}; // @[FBase.scala 139:36]
-  wire [2:0] _T_12 = _T_11 + _GEN_4; // @[FBase.scala 139:36]
-  wire [1:0] _T_16 = _T_12[1] + _T_12[2]; // @[Bitwise.scala 48:55]
-  wire [1:0] _GEN_5 = {{1'd0}, _T_12[0]}; // @[Bitwise.scala 48:55]
-  wire [2:0] _T_18 = _GEN_5 + _T_16; // @[Bitwise.scala 48:55]
-  wire  fs2nans = _nan2_T_1 & ~fregfile_io_freadData_1_data[22] & fregfile_io_freadData_1_data[21:0] != 22'h0; // @[FBase.scala 136:47]
-  wire  fs2nanq = _nan2_T_1 & fregfile_io_freadData_1_data[22]; // @[FBase.scala 137:37]
-  wire  fs2zero = fregfile_io_freadData_1_data[30:0] == 31'h0; // @[FBase.scala 138:26]
-  wire [1:0] _T_24 = fs2nans + fs2nanq; // @[FBase.scala 139:28]
-  wire [1:0] _GEN_6 = {{1'd0}, fs2zero}; // @[FBase.scala 139:36]
-  wire [2:0] _T_25 = _T_24 + _GEN_6; // @[FBase.scala 139:36]
-  wire [1:0] _T_29 = _T_25[1] + _T_25[2]; // @[Bitwise.scala 48:55]
-  wire [1:0] _GEN_7 = {{1'd0}, _T_25[0]}; // @[Bitwise.scala 48:55]
-  wire [2:0] _T_31 = _GEN_7 + _T_29; // @[Bitwise.scala 48:55]
-  wire  _sel_T_2 = ~sign1; // @[FBase.scala 147:43]
-  wire  _sel_T_4 = ~sign2; // @[FBase.scala 147:55]
-  wire  _sel_T_6 = fs1zero & fs2zero & (~sign1 | ~sign2); // @[FBase.scala 147:39]
-  wire  _sel_T_9 = fs1nans | fs2nans | fs1nanq & fs2nanq; // @[FBase.scala 151:39]
-  wire  _sel_T_12 = fs1nanq & ~(fs2nanq | fs2nans); // @[FBase.scala 154:28]
-  wire  _sel_T_15 = fs2nanq & ~(fs1nanq | fs1nans); // @[FBase.scala 155:28]
-  wire [3:0] sel = {_sel_T_6,_sel_T_9,_sel_T_12,_sel_T_15}; // @[Cat.scala 31:58]
-  wire [31:0] _alt_T_1 = sel[2] ? 32'h7fc00000 : 32'h0; // @[FBase.scala 157:18]
-  wire [31:0] _alt_T_3 = sel[1] ? fregfile_io_freadData_1_data : 32'h0; // @[FBase.scala 158:18]
-  wire [31:0] _alt_T_4 = _alt_T_1 | _alt_T_3; // @[FBase.scala 157:52]
-  wire [31:0] _alt_T_6 = sel[0] ? fregfile_io_freadData_0_data : 32'h0; // @[FBase.scala 159:18]
-  wire [31:0] alt = _alt_T_4 | _alt_T_6; // @[FBase.scala 158:37]
-  wire  _fmin_T = sel != 4'h0; // @[FBase.scala 161:24]
-  wire [31:0] _fmin_T_1 = flt_1 ? fregfile_io_freadData_0_data : fregfile_io_freadData_1_data; // @[FBase.scala 161:41]
-  wire [31:0] fmin = sel != 4'h0 ? alt : _fmin_T_1; // @[FBase.scala 161:19]
-  wire [31:0] _fmax_T_1 = flt_1 ? fregfile_io_freadData_1_data : fregfile_io_freadData_0_data; // @[FBase.scala 162:41]
-  wire [31:0] fmax = _fmin_T ? alt : _fmax_T_1; // @[FBase.scala 162:19]
-  wire  _fclass_fclass_T_2 = _nan1_T_1 & fregfile_io_freadData_0_data[22:0] == 23'h400000; // @[FBase.scala 174:36]
-  wire  _fclass_fclass_T_7 = _nan1_T_1 & fregfile_io_freadData_0_data[22:0] != 23'h400000 & _nan1_T_3; // @[FBase.scala 175:58]
-  wire  _fclass_fclass_T_11 = fregfile_io_freadData_0_data[22:0] == 23'h0; // @[FBase.scala 176:52]
-  wire  _fclass_fclass_T_12 = _sel_T_2 & _nan1_T_1 & fregfile_io_freadData_0_data[22:0] == 23'h0; // @[FBase.scala 176:45]
-  wire  _fclass_fclass_T_14 = fregfile_io_freadData_0_data[30:23] < 8'hff; // @[FBase.scala 177:35]
-  wire  _fclass_fclass_T_16 = fregfile_io_freadData_0_data[30:23] > 8'h0; // @[FBase.scala 177:50]
-  wire  _fclass_fclass_T_17 = _sel_T_2 & fregfile_io_freadData_0_data[30:23] < 8'hff & fregfile_io_freadData_0_data[30:
-    23] > 8'h0; // @[FBase.scala 177:43]
-  wire  _fclass_fclass_T_19 = fregfile_io_freadData_0_data[30:23] == 8'h0; // @[FBase.scala 178:35]
-  wire  _fclass_fclass_T_20 = _sel_T_2 & fregfile_io_freadData_0_data[30:23] == 8'h0; // @[FBase.scala 178:28]
-  wire  _fclass_fclass_T_22 = _sel_T_2 & fregfile_io_freadData_0_data[30:23] == 8'h0 & _nan1_T_3; // @[FBase.scala 178:43]
-  wire  _fclass_fclass_T_27 = _fclass_fclass_T_20 & _fclass_fclass_T_11; // @[FBase.scala 179:43]
-  wire  _fclass_fclass_T_29 = sign1 & _fclass_fclass_T_19; // @[FBase.scala 180:28]
-  wire  _fclass_fclass_T_31 = sign1 & _fclass_fclass_T_19 & _fclass_fclass_T_11; // @[FBase.scala 180:43]
-  wire  _fclass_fclass_T_35 = _fclass_fclass_T_29 & _nan1_T_3; // @[FBase.scala 181:43]
-  wire  _fclass_fclass_T_39 = sign1 & _fclass_fclass_T_14 & _fclass_fclass_T_16; // @[FBase.scala 182:43]
-  wire  _fclass_fclass_T_43 = sign1 & _nan1_T_1 & _fclass_fclass_T_11; // @[FBase.scala 183:45]
-  wire [9:0] fclass = {_fclass_fclass_T_2,_fclass_fclass_T_7,_fclass_fclass_T_12,_fclass_fclass_T_17,_fclass_fclass_T_22
-    ,_fclass_fclass_T_27,_fclass_fclass_T_31,_fclass_fclass_T_35,_fclass_fclass_T_39,_fclass_fclass_T_43}; // @[Cat.scala 31:58]
-  wire [1:0] _fclass_T_10 = fclass[0] + fclass[1]; // @[Bitwise.scala 48:55]
-  wire [1:0] _fclass_T_12 = fclass[3] + fclass[4]; // @[Bitwise.scala 48:55]
-  wire [1:0] _GEN_8 = {{1'd0}, fclass[2]}; // @[Bitwise.scala 48:55]
-  wire [2:0] _fclass_T_14 = _GEN_8 + _fclass_T_12; // @[Bitwise.scala 48:55]
-  wire [2:0] _fclass_T_16 = _fclass_T_10 + _fclass_T_14[1:0]; // @[Bitwise.scala 48:55]
-  wire [1:0] _fclass_T_18 = fclass[5] + fclass[6]; // @[Bitwise.scala 48:55]
-  wire [1:0] _fclass_T_20 = fclass[8] + fclass[9]; // @[Bitwise.scala 48:55]
-  wire [1:0] _GEN_9 = {{1'd0}, fclass[7]}; // @[Bitwise.scala 48:55]
-  wire [2:0] _fclass_T_22 = _GEN_9 + _fclass_T_20; // @[Bitwise.scala 48:55]
-  wire [2:0] _fclass_T_24 = _fclass_T_18 + _fclass_T_22[1:0]; // @[Bitwise.scala 48:55]
-  wire [3:0] _fclass_T_26 = _fclass_T_16 + _fclass_T_24; // @[Bitwise.scala 48:55]
-  wire [31:0] _fdata_T_3 = {sign2,fregfile_io_freadData_0_data[30:0]}; // @[Cat.scala 31:58]
-  wire [31:0] _fdata_T_4 = op[11] ? _fdata_T_3 : 32'h0; // @[Library.scala 18:8]
-  wire [31:0] _fdata_T_9 = {_sel_T_4,fregfile_io_freadData_0_data[30:0]}; // @[Cat.scala 31:58]
-  wire [31:0] _fdata_T_10 = op[12] ? _fdata_T_9 : 32'h0; // @[Library.scala 18:8]
-  wire [31:0] _fdata_T_11 = _fdata_T_4 | _fdata_T_10; // @[Fpu.scala 260:61]
-  wire  _fdata_T_15 = sign2 ^ sign1; // @[Fpu.scala 262:49]
-  wire [31:0] _fdata_T_17 = {_fdata_T_15,fregfile_io_freadData_0_data[30:0]}; // @[Cat.scala 31:58]
-  wire [31:0] _fdata_T_18 = op[13] ? _fdata_T_17 : 32'h0; // @[Library.scala 18:8]
-  wire [31:0] _fdata_T_19 = _fdata_T_11 | _fdata_T_18; // @[Fpu.scala 261:63]
-  wire [31:0] _fdata_T_21 = op[14] ? fmin : 32'h0; // @[Library.scala 18:8]
-  wire [31:0] _fdata_T_22 = _fdata_T_19 | _fdata_T_21; // @[Fpu.scala 262:72]
-  wire [31:0] _fdata_T_24 = op[15] ? fmax : 32'h0; // @[Library.scala 18:8]
-  wire [31:0] _fdata_T_25 = _fdata_T_22 | _fdata_T_24; // @[Fpu.scala 263:41]
-  wire [31:0] _fdata_T_27 = op[18] ? fregfile_io_freadData_0_data : 32'h0; // @[Library.scala 18:8]
-  wire [31:0] _fdata_T_28 = _fdata_T_25 | _fdata_T_27; // @[Fpu.scala 264:41]
-  wire  _fdata_T_30 = op[19] & feq_1; // @[Library.scala 22:8]
-  wire [31:0] _GEN_10 = {{31'd0}, _fdata_T_30}; // @[Fpu.scala 265:41]
-  wire [31:0] _fdata_T_31 = _fdata_T_28 | _GEN_10; // @[Fpu.scala 265:41]
-  wire  _fdata_T_33 = op[20] & flt_1; // @[Library.scala 22:8]
-  wire [31:0] _GEN_11 = {{31'd0}, _fdata_T_33}; // @[Fpu.scala 266:39]
-  wire [31:0] _fdata_T_34 = _fdata_T_31 | _GEN_11; // @[Fpu.scala 266:39]
-  wire  _fdata_T_36 = op[21] & fle_1; // @[Library.scala 22:8]
-  wire [31:0] _GEN_12 = {{31'd0}, _fdata_T_36}; // @[Fpu.scala 267:39]
-  wire [31:0] _fdata_T_37 = _fdata_T_34 | _GEN_12; // @[Fpu.scala 267:39]
-  wire [9:0] _fdata_T_39 = op[22] ? fclass : 10'h0; // @[Library.scala 18:8]
-  wire [31:0] _GEN_13 = {{22'd0}, _fdata_T_39}; // @[Fpu.scala 268:39]
-  wire [31:0] fdata = _fdata_T_37 | _GEN_13; // @[Fpu.scala 268:39]
-  wire  _T_41 = op[25] | op[18] | op[11]; // @[Fpu.scala 271:40]
-  wire  _T_47 = _T_41 | op[12] | op[13] | op[14]; // @[Fpu.scala 272:59]
-  wire  _T_51 = _T_47 | op[15] | op[19]; // @[Fpu.scala 273:38]
-  FRegfile fregfile ( // @[FRegfile.scala 9:18]
-    .clock(fregfile_clock),
-    .reset(fregfile_reset),
-    .io_freadAddr_0_valid(fregfile_io_freadAddr_0_valid),
-    .io_freadAddr_0_addr(fregfile_io_freadAddr_0_addr),
-    .io_freadAddr_1_valid(fregfile_io_freadAddr_1_valid),
-    .io_freadAddr_1_addr(fregfile_io_freadAddr_1_addr),
-    .io_freadAddr_2_valid(fregfile_io_freadAddr_2_valid),
-    .io_freadAddr_2_addr(fregfile_io_freadAddr_2_addr),
-    .io_freadAddr_3_valid(fregfile_io_freadAddr_3_valid),
-    .io_freadAddr_3_addr(fregfile_io_freadAddr_3_addr),
-    .io_freadAddr_4_valid(fregfile_io_freadAddr_4_valid),
-    .io_freadAddr_4_addr(fregfile_io_freadAddr_4_addr),
-    .io_freadAddr_5_valid(fregfile_io_freadAddr_5_valid),
-    .io_freadAddr_5_addr(fregfile_io_freadAddr_5_addr),
-    .io_fwriteAddr_valid(fregfile_io_fwriteAddr_valid),
-    .io_fwriteAddr_addr(fregfile_io_fwriteAddr_addr),
-    .io_fbusPort_data(fregfile_io_fbusPort_data),
-    .io_freadData_0_data(fregfile_io_freadData_0_data),
-    .io_freadData_1_data(fregfile_io_freadData_1_data),
-    .io_freadData_2_data(fregfile_io_freadData_2_data),
-    .io_freadData_3_data(fregfile_io_freadData_3_data),
-    .io_freadData_4_data(fregfile_io_freadData_4_data),
-    .io_freadData_5_data(fregfile_io_freadData_5_data),
-    .io_fwriteData_0_valid(fregfile_io_fwriteData_0_valid),
-    .io_fwriteData_0_addr(fregfile_io_fwriteData_0_addr),
-    .io_fwriteData_0_data(fregfile_io_fwriteData_0_data),
-    .io_fwriteData_1_valid(fregfile_io_fwriteData_1_valid),
-    .io_fwriteData_1_addr(fregfile_io_fwriteData_1_addr),
-    .io_fwriteData_1_data(fregfile_io_fwriteData_1_data),
-    .io_fwriteData_2_valid(fregfile_io_fwriteData_2_valid),
-    .io_fwriteData_2_addr(fregfile_io_fwriteData_2_addr),
-    .io_fwriteData_2_data(fregfile_io_fwriteData_2_data),
-    .io_fwriteData_3_valid(fregfile_io_fwriteData_3_valid),
-    .io_fwriteData_3_addr(fregfile_io_fwriteData_3_addr),
-    .io_fwriteData_3_data(fregfile_io_fwriteData_3_data),
-    .io_fwriteData_4_valid(fregfile_io_fwriteData_4_valid),
-    .io_fwriteData_4_addr(fregfile_io_fwriteData_4_addr),
-    .io_fwriteData_4_data(fregfile_io_fwriteData_4_data),
-    .io_fwriteData_5_valid(fregfile_io_fwriteData_5_valid),
-    .io_fwriteData_5_addr(fregfile_io_fwriteData_5_addr),
-    .io_fwriteData_5_data(fregfile_io_fwriteData_5_data),
-    .io_fscoreboard(fregfile_io_fscoreboard)
-  );
-  FAdd_1 fadd ( // @[FAdd.scala 8:18]
-    .clock(fadd_clock),
-    .reset(fadd_reset),
-    .io_in_valid(fadd_io_in_valid),
-    .io_in_addr(fadd_io_in_addr),
-    .io_in_fs1(fadd_io_in_fs1),
-    .io_in_fs2(fadd_io_in_fs2),
-    .io_in_op(fadd_io_in_op),
-    .io_out_valid(fadd_io_out_valid),
-    .io_out_addr(fadd_io_out_addr),
-    .io_out_fd(fadd_io_out_fd)
-  );
-  FMAdd_1 fmadd ( // @[FMAdd.scala 8:18]
-    .clock(fmadd_clock),
-    .reset(fmadd_reset),
-    .io_in_valid(fmadd_io_in_valid),
-    .io_in_addr(fmadd_io_in_addr),
-    .io_in_fs1(fmadd_io_in_fs1),
-    .io_in_fs2(fmadd_io_in_fs2),
-    .io_in_fs3(fmadd_io_in_fs3),
-    .io_in_op(fmadd_io_in_op),
-    .io_out_valid(fmadd_io_out_valid),
-    .io_out_addr(fmadd_io_out_addr),
-    .io_out_fd(fmadd_io_out_fd)
-  );
-  FDiv_1 fdiv ( // @[FDiv.scala 8:18]
-    .clock(fdiv_clock),
-    .reset(fdiv_reset),
-    .io_in_valid(fdiv_io_in_valid),
-    .io_in_ready(fdiv_io_in_ready),
-    .io_in_addr(fdiv_io_in_addr),
-    .io_in_fs1(fdiv_io_in_fs1),
-    .io_in_fs2(fdiv_io_in_fs2),
-    .io_out_valid(fdiv_io_out_valid),
-    .io_out_addr(fdiv_io_out_addr),
-    .io_out_fd(fdiv_io_out_fd)
-  );
-  FSqrt_1 fsqrt ( // @[FSqrt.scala 8:18]
-    .clock(fsqrt_clock),
-    .reset(fsqrt_reset),
-    .io_in_valid(fsqrt_io_in_valid),
-    .io_in_ready(fsqrt_io_in_ready),
-    .io_in_addr(fsqrt_io_in_addr),
-    .io_in_fs(fsqrt_io_in_fs),
-    .io_out_valid(fsqrt_io_out_valid),
-    .io_out_addr(fsqrt_io_out_addr),
-    .io_out_fd(fsqrt_io_out_fd)
-  );
-  FCvtsw_1 fcvtsw ( // @[FCvtsw.scala 8:18]
-    .clock(fcvtsw_clock),
-    .reset(fcvtsw_reset),
-    .io_in_valid(fcvtsw_io_in_valid),
-    .io_in_unsigned(fcvtsw_io_in_unsigned),
-    .io_in_addr(fcvtsw_io_in_addr),
-    .io_in_rs(fcvtsw_io_in_rs),
-    .io_out_valid(fcvtsw_io_out_valid),
-    .io_out_addr(fcvtsw_io_out_addr),
-    .io_out_fd(fcvtsw_io_out_fd)
-  );
-  FCvtws_1 fcvtws ( // @[FCvtws.scala 8:18]
-    .clock(fcvtws_clock),
-    .reset(fcvtws_reset),
-    .io_in_valid(fcvtws_io_in_valid),
-    .io_in_unsigned(fcvtws_io_in_unsigned),
-    .io_in_addr(fcvtws_io_in_addr),
-    .io_in_fs(fcvtws_io_in_fs),
-    .io_out_valid(fcvtws_io_out_valid),
-    .io_out_addr(fcvtws_io_out_addr),
-    .io_out_rd(fcvtws_io_out_rd)
-  );
-  assign io_req_0_busyFDiv = ~fdiv_io_in_ready | fdiv_io_in_valid; // @[Fpu.scala 289:43]
-  assign io_req_0_busyFSqrt = ~fsqrt_io_in_ready | fsqrt_io_in_valid; // @[Fpu.scala 290:45]
-  assign io_fbusPort_data = fregfile_io_fbusPort_data; // @[Fpu.scala 293:15]
-  assign io_writeData_0_valid = wrvalid; // @[Fpu.scala 280:25]
-  assign io_writeData_0_addr = waddr; // @[Fpu.scala 281:25]
-  assign io_writeData_0_data = wdata; // @[Fpu.scala 282:25]
-  assign io_writeData_1_valid = fcvtws_io_out_valid; // @[Fpu.scala 284:25]
-  assign io_writeData_1_addr = fcvtws_io_out_addr; // @[Fpu.scala 285:25]
-  assign io_writeData_1_data = fcvtws_io_out_rd; // @[Fpu.scala 286:25]
-  assign io_fs_0_data = fregfile_io_freadData_1_data; // @[Fpu.scala 171:12]
-  assign io_fs_1_data = fregfile_io_freadData_3_data; // @[Fpu.scala 172:12]
-  assign io_fs_2_data = fregfile_io_freadData_4_data; // @[Fpu.scala 173:12]
-  assign io_fs_3_data = fregfile_io_freadData_5_data; // @[Fpu.scala 174:12]
-  assign io_fscoreboard = fregfile_io_fscoreboard; // @[Fpu.scala 296:18]
-  assign fregfile_clock = clock;
-  assign fregfile_reset = reset;
-  assign fregfile_io_freadAddr_0_valid = fopABC | fopAB | fopA; // @[Fpu.scala 144:53]
-  assign fregfile_io_freadAddr_0_addr = io_req_0_raddr_0; // @[Fpu.scala 148:33]
-  assign fregfile_io_freadAddr_1_valid = _fregfile_io_freadAddr_0_valid_T | fopB; // @[Fpu.scala 145:53]
-  assign fregfile_io_freadAddr_1_addr = io_req_0_raddr_1; // @[Fpu.scala 149:33]
-  assign fregfile_io_freadAddr_2_valid = _fopABC_T_4 | io_req_0_op[5]; // @[Fpu.scala 142:32]
-  assign fregfile_io_freadAddr_2_addr = io_req_0_raddr_2; // @[Fpu.scala 150:33]
-  assign fregfile_io_freadAddr_3_valid = io_req_1_op[26]; // @[Fpu.scala 152:49]
-  assign fregfile_io_freadAddr_3_addr = io_req_1_raddr_1; // @[Fpu.scala 156:33]
-  assign fregfile_io_freadAddr_4_valid = io_req_2_op[26]; // @[Fpu.scala 153:49]
-  assign fregfile_io_freadAddr_4_addr = io_req_2_raddr_1; // @[Fpu.scala 157:33]
-  assign fregfile_io_freadAddr_5_valid = io_req_3_op[26]; // @[Fpu.scala 154:49]
-  assign fregfile_io_freadAddr_5_addr = io_req_3_raddr_1; // @[Fpu.scala 158:33]
-  assign fregfile_io_fwriteAddr_valid = io_req_0_valid & _fregfile_io_fwriteAddr_valid_T_34; // @[Fpu.scala 177:51]
-  assign fregfile_io_fwriteAddr_addr = io_req_0_waddr; // @[Fpu.scala 185:31]
-  assign fregfile_io_fwriteData_0_valid = wfvalid; // @[Fpu.scala 187:35]
-  assign fregfile_io_fwriteData_0_addr = waddr; // @[Fpu.scala 188:35]
-  assign fregfile_io_fwriteData_0_data = wdata; // @[Fpu.scala 189:35]
-  assign fregfile_io_fwriteData_1_valid = fadd_io_out_valid | fcvtsw_io_out_valid; // @[Fpu.scala 217:25]
-  assign fregfile_io_fwriteData_1_addr = fadd_io_out_valid ? fadd_io_out_addr : fcvtsw_io_out_addr; // @[Fpu.scala 219:10]
-  assign fregfile_io_fwriteData_1_data = fadd_io_out_valid ? fadd_io_out_fd : fcvtsw_io_out_fd; // @[Fpu.scala 221:10]
-  assign fregfile_io_fwriteData_2_valid = fmadd_io_out_valid; // @[Fpu.scala 226:35]
-  assign fregfile_io_fwriteData_2_addr = fmadd_io_out_addr; // @[Fpu.scala 227:35]
-  assign fregfile_io_fwriteData_2_data = fmadd_io_out_fd; // @[Fpu.scala 228:35]
-  assign fregfile_io_fwriteData_3_valid = fdiv_io_out_valid; // @[Fpu.scala 236:35]
-  assign fregfile_io_fwriteData_3_addr = fdiv_io_out_addr; // @[Fpu.scala 237:35]
-  assign fregfile_io_fwriteData_3_data = fdiv_io_out_fd; // @[Fpu.scala 238:35]
-  assign fregfile_io_fwriteData_4_valid = fsqrt_io_out_valid; // @[Fpu.scala 245:35]
-  assign fregfile_io_fwriteData_4_addr = fsqrt_io_out_addr; // @[Fpu.scala 246:35]
-  assign fregfile_io_fwriteData_4_data = fsqrt_io_out_fd; // @[Fpu.scala 247:35]
-  assign fregfile_io_fwriteData_5_valid = io_fwriteData_valid; // @[Fpu.scala 250:29]
-  assign fregfile_io_fwriteData_5_addr = io_fwriteData_addr; // @[Fpu.scala 250:29]
-  assign fregfile_io_fwriteData_5_data = io_fwriteData_data; // @[Fpu.scala 250:29]
-  assign fadd_clock = clock;
-  assign fadd_reset = reset;
-  assign fadd_io_in_valid = valid & (op[6] | op[7]); // @[Fpu.scala 192:29]
-  assign fadd_io_in_addr = addr; // @[Fpu.scala 193:19]
-  assign fadd_io_in_fs1 = fregfile_io_freadData_0_data; // @[Fpu.scala 194:18]
-  assign fadd_io_in_fs2 = fregfile_io_freadData_1_data; // @[Fpu.scala 195:18]
-  assign fadd_io_in_op = op; // @[Fpu.scala 196:17]
-  assign fmadd_clock = clock;
-  assign fmadd_reset = reset;
-  assign fmadd_io_in_valid = valid & _fmadd_io_in_valid_T_8; // @[Fpu.scala 198:30]
-  assign fmadd_io_in_addr = addr; // @[Fpu.scala 200:20]
-  assign fmadd_io_in_fs1 = fregfile_io_freadData_0_data; // @[Fpu.scala 201:19]
-  assign fmadd_io_in_fs2 = fregfile_io_freadData_1_data; // @[Fpu.scala 202:19]
-  assign fmadd_io_in_fs3 = fregfile_io_freadData_2_data; // @[Fpu.scala 203:19]
-  assign fmadd_io_in_op = op; // @[Fpu.scala 204:18]
-  assign fdiv_clock = clock;
-  assign fdiv_reset = reset;
-  assign fdiv_io_in_valid = valid & op[9]; // @[Fpu.scala 231:29]
-  assign fdiv_io_in_addr = addr; // @[Fpu.scala 232:19]
-  assign fdiv_io_in_fs1 = fregfile_io_freadData_0_data; // @[Fpu.scala 233:18]
-  assign fdiv_io_in_fs2 = fregfile_io_freadData_1_data; // @[Fpu.scala 234:18]
-  assign fsqrt_clock = clock;
-  assign fsqrt_reset = reset;
-  assign fsqrt_io_in_valid = valid & op[10]; // @[Fpu.scala 241:30]
-  assign fsqrt_io_in_addr = addr; // @[Fpu.scala 242:20]
-  assign fsqrt_io_in_fs = fregfile_io_freadData_0_data; // @[Fpu.scala 243:18]
-  assign fcvtsw_clock = clock;
-  assign fcvtsw_reset = reset;
-  assign fcvtsw_io_in_valid = valid & (op[23] | op[24]); // @[Fpu.scala 206:31]
-  assign fcvtsw_io_in_unsigned = op[24]; // @[Fpu.scala 207:30]
-  assign fcvtsw_io_in_addr = addr; // @[Fpu.scala 208:21]
-  assign fcvtsw_io_in_rs = io_readData_data; // @[Fpu.scala 209:19]
-  assign fcvtws_clock = clock;
-  assign fcvtws_reset = reset;
-  assign fcvtws_io_in_valid = valid & (op[16] | op[17]); // @[Fpu.scala 211:31]
-  assign fcvtws_io_in_unsigned = op[17]; // @[Fpu.scala 212:30]
-  assign fcvtws_io_in_addr = addr; // @[Fpu.scala 213:21]
-  assign fcvtws_io_in_fs = fregfile_io_freadData_0_data; // @[Fpu.scala 214:19]
-  always @(posedge clock) begin
-    if (io_req_0_valid) begin // @[Fpu.scala 162:26]
-      addr <= io_req_0_waddr; // @[Fpu.scala 163:10]
-    end
-    if (_T_51 | op[20] | op[21] | op[22]) begin // @[Fpu.scala 274:70]
-      waddr <= addr; // @[Fpu.scala 275:11]
-    end
-    if (_T_51 | op[20] | op[21] | op[22]) begin // @[Fpu.scala 274:70]
-      if (op[25]) begin // @[Fpu.scala 276:17]
-        wdata <= io_readData_data;
-      end else begin
-        wdata <= fdata;
-      end
-    end
-    `ifndef SYNTHESIS
-    `ifdef STOP_COND
-      if (`STOP_COND) begin
-    `endif
-        if (~reset & ~(_T <= 2'h1)) begin
-          $fatal; // @[Fpu.scala 223:9]
-        end
-    `ifdef STOP_COND
-      end
-    `endif
-    `endif // SYNTHESIS
-    `ifndef SYNTHESIS
-    `ifdef PRINTF_COND
-      if (`PRINTF_COND) begin
-    `endif
-        if (~reset & ~(_T <= 2'h1)) begin
-          $fwrite(32'h80000002,
-            "Assertion failed\n    at Fpu.scala:223 assert((fadd.io.out.valid +& fcvtsw.io.out.valid) <= 1.U)\n"); // @[Fpu.scala 223:9]
-        end
-    `ifdef PRINTF_COND
-      end
-    `endif
-    `endif // SYNTHESIS
-    `ifndef SYNTHESIS
-    `ifdef STOP_COND
-      if (`STOP_COND) begin
-    `endif
-        if (_T_3 & ~(_T_18[1:0] <= 2'h1)) begin
-          $fatal; // @[FBase.scala 139:13]
-        end
-    `ifdef STOP_COND
-      end
-    `endif
-    `endif // SYNTHESIS
-    `ifndef SYNTHESIS
-    `ifdef PRINTF_COND
-      if (`PRINTF_COND) begin
-    `endif
-        if (_T_3 & ~(_T_18[1:0] <= 2'h1)) begin
-          $fwrite(32'h80000002,
-            "Assertion failed\n    at FBase.scala:139 assert(PopCount(nans +& nanq +& zero) <= 1.U)\n"); // @[FBase.scala 139:13]
-        end
-    `ifdef PRINTF_COND
-      end
-    `endif
-    `endif // SYNTHESIS
-    `ifndef SYNTHESIS
-    `ifdef STOP_COND
-      if (`STOP_COND) begin
-    `endif
-        if (_T_3 & ~(_T_31[1:0] <= 2'h1)) begin
-          $fatal; // @[FBase.scala 139:13]
-        end
-    `ifdef STOP_COND
-      end
-    `endif
-    `endif // SYNTHESIS
-    `ifndef SYNTHESIS
-    `ifdef PRINTF_COND
-      if (`PRINTF_COND) begin
-    `endif
-        if (_T_3 & ~(_T_31[1:0] <= 2'h1)) begin
-          $fwrite(32'h80000002,
-            "Assertion failed\n    at FBase.scala:139 assert(PopCount(nans +& nanq +& zero) <= 1.U)\n"); // @[FBase.scala 139:13]
-        end
-    `ifdef PRINTF_COND
-      end
-    `endif
-    `endif // SYNTHESIS
-    `ifndef SYNTHESIS
-    `ifdef STOP_COND
-      if (`STOP_COND) begin
-    `endif
-        if (_T_3 & ~(_fclass_T_26 == 4'h1)) begin
-          $fatal; // @[FBase.scala 184:11]
-        end
-    `ifdef STOP_COND
-      end
-    `endif
-    `endif // SYNTHESIS
-    `ifndef SYNTHESIS
-    `ifdef PRINTF_COND
-      if (`PRINTF_COND) begin
-    `endif
-        if (_T_3 & ~(_fclass_T_26 == 4'h1)) begin
-          $fwrite(32'h80000002,"Assertion failed\n    at FBase.scala:184 assert(PopCount(fclass) === 1.U)\n"); // @[FBase.scala 184:11]
-        end
-    `ifdef PRINTF_COND
-      end
-    `endif
-    `endif // SYNTHESIS
-  end
-  always @(posedge clock or posedge reset) begin
-    if (reset) begin // @[Fpu.scala 105:22]
-      valid <= 1'h0; // @[Fpu.scala 105:22]
-    end else begin
-      valid <= io_req_0_valid; // @[Fpu.scala 160:9]
-    end
-  end
-  always @(posedge clock or posedge reset) begin
-    if (reset) begin // @[Fpu.scala 162:26]
-      op <= 27'h0; // @[Fpu.scala 164:8]
-    end else if (io_req_0_valid) begin // @[Fpu.scala 107:19]
-      op <= io_req_0_op;
-    end
-  end
-  always @(posedge clock or posedge reset) begin
-    if (reset) begin // @[Fpu.scala 253:20]
-      wfvalid <= 1'h0;
-    end else begin
-      wfvalid <= valid & (op[25] | op[11] | op[12] | op[13] | op[14] | op[15]);
-    end
-  end
-  always @(posedge clock or posedge reset) begin
-    if (reset) begin // @[Fpu.scala 254:20]
-      wrvalid <= 1'h0;
-    end else begin
-      wrvalid <= valid & (op[18] | op[19] | op[20] | op[21] | op[22]);
-    end
-  end
-// Register and memory initialization
-`ifdef RANDOMIZE_GARBAGE_ASSIGN
-`define RANDOMIZE
-`endif
-`ifdef RANDOMIZE_INVALID_ASSIGN
-`define RANDOMIZE
-`endif
-`ifdef RANDOMIZE_REG_INIT
-`define RANDOMIZE
-`endif
-`ifdef RANDOMIZE_MEM_INIT
-`define RANDOMIZE
-`endif
-`ifndef RANDOM
-`define RANDOM $random
-`endif
-`ifdef RANDOMIZE_MEM_INIT
-  integer initvar;
-`endif
-`ifndef SYNTHESIS
-`ifdef FIRRTL_BEFORE_INITIAL
-`FIRRTL_BEFORE_INITIAL
-`endif
-initial begin
-  `ifdef RANDOMIZE
-    `ifdef INIT_RANDOM
-      `INIT_RANDOM
-    `endif
-    `ifndef VERILATOR
-      `ifdef RANDOMIZE_DELAY
-        #`RANDOMIZE_DELAY begin end
-      `else
-        #0.002 begin end
-      `endif
-    `endif
-`ifdef RANDOMIZE_REG_INIT
-  _RAND_0 = {1{`RANDOM}};
-  valid = _RAND_0[0:0];
-  _RAND_1 = {1{`RANDOM}};
-  addr = _RAND_1[4:0];
-  _RAND_2 = {1{`RANDOM}};
-  op = _RAND_2[26:0];
-  _RAND_3 = {1{`RANDOM}};
-  wfvalid = _RAND_3[0:0];
-  _RAND_4 = {1{`RANDOM}};
-  wrvalid = _RAND_4[0:0];
-  _RAND_5 = {1{`RANDOM}};
-  waddr = _RAND_5[4:0];
-  _RAND_6 = {1{`RANDOM}};
-  wdata = _RAND_6[31:0];
-`endif // RANDOMIZE_REG_INIT
-  if (reset) begin
-    valid = 1'h0;
-  end
-  if (reset) begin
-    op = 27'h0;
-  end
-  if (reset) begin
-    wfvalid = 1'h0;
-  end
-  if (reset) begin
-    wrvalid = 1'h0;
-  end
-  `endif // RANDOMIZE
-end // initial
-`ifdef FIRRTL_AFTER_INITIAL
-`FIRRTL_AFTER_INITIAL
-`endif
-`endif // SYNTHESIS
-endmodule
 module SCore(
   input          clock,
   input          reset,
@@ -30228,22 +21119,22 @@
   input          io_vcore_vinst_0_ready,
   output [4:0]   io_vcore_vinst_0_addr,
   output [31:0]  io_vcore_vinst_0_inst,
-  output [5:0]   io_vcore_vinst_0_op,
+  output [4:0]   io_vcore_vinst_0_op,
   output         io_vcore_vinst_1_valid,
   input          io_vcore_vinst_1_ready,
   output [4:0]   io_vcore_vinst_1_addr,
   output [31:0]  io_vcore_vinst_1_inst,
-  output [5:0]   io_vcore_vinst_1_op,
+  output [4:0]   io_vcore_vinst_1_op,
   output         io_vcore_vinst_2_valid,
   input          io_vcore_vinst_2_ready,
   output [4:0]   io_vcore_vinst_2_addr,
   output [31:0]  io_vcore_vinst_2_inst,
-  output [5:0]   io_vcore_vinst_2_op,
+  output [4:0]   io_vcore_vinst_2_op,
   output         io_vcore_vinst_3_valid,
   input          io_vcore_vinst_3_ready,
   output [4:0]   io_vcore_vinst_3_addr,
   output [31:0]  io_vcore_vinst_3_inst,
-  output [5:0]   io_vcore_vinst_3_op,
+  output [4:0]   io_vcore_vinst_3_op,
   output [31:0]  io_vcore_rs_0_data,
   output [31:0]  io_vcore_rs_1_data,
   output [31:0]  io_vcore_rs_2_data,
@@ -30264,10 +21155,6 @@
   input          io_vcore_rd_3_valid,
   input  [4:0]   io_vcore_rd_3_addr,
   input  [31:0]  io_vcore_rd_3_data,
-  output [31:0]  io_vcore_fs_0_data,
-  output [31:0]  io_vcore_fs_1_data,
-  output [31:0]  io_vcore_fs_2_data,
-  output [31:0]  io_vcore_fs_3_data,
   input          io_vcore_mactive,
   input          io_vcore_undef,
   output         io_iflush_valid,
@@ -30283,7 +21170,6 @@
   reg [31:0] _RAND_1;
   reg [31:0] _RAND_2;
   reg [31:0] _RAND_3;
-  reg [31:0] _RAND_4;
 `endif // RANDOMIZE_REG_INIT
   wire  regfile_clock; // @[Regfile.scala 9:18]
   wire  regfile_reset; // @[Regfile.scala 9:18]
@@ -30388,6 +21274,7 @@
   wire  regfile_io_writeMask_1_valid; // @[Regfile.scala 9:18]
   wire  regfile_io_writeMask_2_valid; // @[Regfile.scala 9:18]
   wire  regfile_io_writeMask_3_valid; // @[Regfile.scala 9:18]
+  wire  regfile_io_writeMask_4_valid; // @[Regfile.scala 9:18]
   wire [31:0] regfile_io_scoreboard_regd; // @[Regfile.scala 9:18]
   wire [31:0] regfile_io_scoreboard_comb; // @[Regfile.scala 9:18]
   wire  fetch_clock; // @[Fetch.scala 9:18]
@@ -30440,7 +21327,6 @@
   wire [31:0] decode_0_io_scoreboard_regd; // @[Decode.scala 9:18]
   wire [31:0] decode_0_io_scoreboard_comb; // @[Decode.scala 9:18]
   wire [31:0] decode_0_io_scoreboard_spec; // @[Decode.scala 9:18]
-  wire [31:0] decode_0_io_fscoreboard; // @[Decode.scala 9:18]
   wire  decode_0_io_mactive; // @[Decode.scala 9:18]
   wire  decode_0_io_rs1Read_valid; // @[Decode.scala 9:18]
   wire [4:0] decode_0_io_rs1Read_addr; // @[Decode.scala 9:18]
@@ -30457,7 +21343,7 @@
   wire [31:0] decode_0_io_busRead_immed; // @[Decode.scala 9:18]
   wire  decode_0_io_alu_valid; // @[Decode.scala 9:18]
   wire [4:0] decode_0_io_alu_addr; // @[Decode.scala 9:18]
-  wire [18:0] decode_0_io_alu_op; // @[Decode.scala 9:18]
+  wire [17:0] decode_0_io_alu_op; // @[Decode.scala 9:18]
   wire  decode_0_io_bru_valid; // @[Decode.scala 9:18]
   wire  decode_0_io_bru_fwd; // @[Decode.scala 9:18]
   wire [16:0] decode_0_io_bru_op; // @[Decode.scala 9:18]
@@ -30471,7 +21357,7 @@
   wire  decode_0_io_lsu_valid; // @[Decode.scala 9:18]
   wire  decode_0_io_lsu_ready; // @[Decode.scala 9:18]
   wire [4:0] decode_0_io_lsu_addr; // @[Decode.scala 9:18]
-  wire [13:0] decode_0_io_lsu_op; // @[Decode.scala 9:18]
+  wire [11:0] decode_0_io_lsu_op; // @[Decode.scala 9:18]
   wire  decode_0_io_mlu_valid; // @[Decode.scala 9:18]
   wire [4:0] decode_0_io_mlu_addr; // @[Decode.scala 9:18]
   wire [8:0] decode_0_io_mlu_op; // @[Decode.scala 9:18]
@@ -30479,19 +21365,11 @@
   wire  decode_0_io_dvu_ready; // @[Decode.scala 9:18]
   wire [4:0] decode_0_io_dvu_addr; // @[Decode.scala 9:18]
   wire [3:0] decode_0_io_dvu_op; // @[Decode.scala 9:18]
-  wire  decode_0_io_fpu_valid; // @[Decode.scala 9:18]
-  wire [4:0] decode_0_io_fpu_raddr_0; // @[Decode.scala 9:18]
-  wire [4:0] decode_0_io_fpu_raddr_1; // @[Decode.scala 9:18]
-  wire [4:0] decode_0_io_fpu_raddr_2; // @[Decode.scala 9:18]
-  wire [4:0] decode_0_io_fpu_waddr; // @[Decode.scala 9:18]
-  wire [26:0] decode_0_io_fpu_op; // @[Decode.scala 9:18]
-  wire  decode_0_io_fpu_busyFDiv; // @[Decode.scala 9:18]
-  wire  decode_0_io_fpu_busyFSqrt; // @[Decode.scala 9:18]
   wire  decode_0_io_vinst_valid; // @[Decode.scala 9:18]
   wire  decode_0_io_vinst_ready; // @[Decode.scala 9:18]
   wire [4:0] decode_0_io_vinst_addr; // @[Decode.scala 9:18]
   wire [31:0] decode_0_io_vinst_inst; // @[Decode.scala 9:18]
-  wire [5:0] decode_0_io_vinst_op; // @[Decode.scala 9:18]
+  wire [4:0] decode_0_io_vinst_op; // @[Decode.scala 9:18]
   wire  decode_0_io_branchTaken; // @[Decode.scala 9:18]
   wire  decode_0_io_interlock; // @[Decode.scala 9:18]
   wire  decode_0_io_serializeOut_mul; // @[Decode.scala 9:18]
@@ -30509,7 +21387,6 @@
   wire [31:0] decode_1_io_scoreboard_regd; // @[Decode.scala 9:18]
   wire [31:0] decode_1_io_scoreboard_comb; // @[Decode.scala 9:18]
   wire [31:0] decode_1_io_scoreboard_spec; // @[Decode.scala 9:18]
-  wire [31:0] decode_1_io_fscoreboard; // @[Decode.scala 9:18]
   wire  decode_1_io_rs1Read_valid; // @[Decode.scala 9:18]
   wire [4:0] decode_1_io_rs1Read_addr; // @[Decode.scala 9:18]
   wire  decode_1_io_rs1Set_valid; // @[Decode.scala 9:18]
@@ -30524,7 +21401,7 @@
   wire [31:0] decode_1_io_busRead_immed; // @[Decode.scala 9:18]
   wire  decode_1_io_alu_valid; // @[Decode.scala 9:18]
   wire [4:0] decode_1_io_alu_addr; // @[Decode.scala 9:18]
-  wire [18:0] decode_1_io_alu_op; // @[Decode.scala 9:18]
+  wire [17:0] decode_1_io_alu_op; // @[Decode.scala 9:18]
   wire  decode_1_io_bru_valid; // @[Decode.scala 9:18]
   wire  decode_1_io_bru_fwd; // @[Decode.scala 9:18]
   wire [16:0] decode_1_io_bru_op; // @[Decode.scala 9:18]
@@ -30535,18 +21412,16 @@
   wire  decode_1_io_lsu_valid; // @[Decode.scala 9:18]
   wire  decode_1_io_lsu_ready; // @[Decode.scala 9:18]
   wire [4:0] decode_1_io_lsu_addr; // @[Decode.scala 9:18]
-  wire [13:0] decode_1_io_lsu_op; // @[Decode.scala 9:18]
+  wire [11:0] decode_1_io_lsu_op; // @[Decode.scala 9:18]
   wire  decode_1_io_mlu_valid; // @[Decode.scala 9:18]
   wire [4:0] decode_1_io_mlu_addr; // @[Decode.scala 9:18]
   wire [8:0] decode_1_io_mlu_op; // @[Decode.scala 9:18]
   wire [3:0] decode_1_io_dvu_op; // @[Decode.scala 9:18]
-  wire [4:0] decode_1_io_fpu_raddr_1; // @[Decode.scala 9:18]
-  wire [26:0] decode_1_io_fpu_op; // @[Decode.scala 9:18]
   wire  decode_1_io_vinst_valid; // @[Decode.scala 9:18]
   wire  decode_1_io_vinst_ready; // @[Decode.scala 9:18]
   wire [4:0] decode_1_io_vinst_addr; // @[Decode.scala 9:18]
   wire [31:0] decode_1_io_vinst_inst; // @[Decode.scala 9:18]
-  wire [5:0] decode_1_io_vinst_op; // @[Decode.scala 9:18]
+  wire [4:0] decode_1_io_vinst_op; // @[Decode.scala 9:18]
   wire  decode_1_io_branchTaken; // @[Decode.scala 9:18]
   wire  decode_1_io_interlock; // @[Decode.scala 9:18]
   wire  decode_1_io_serializeIn_mul; // @[Decode.scala 9:18]
@@ -30566,7 +21441,6 @@
   wire [31:0] decode_2_io_scoreboard_regd; // @[Decode.scala 9:18]
   wire [31:0] decode_2_io_scoreboard_comb; // @[Decode.scala 9:18]
   wire [31:0] decode_2_io_scoreboard_spec; // @[Decode.scala 9:18]
-  wire [31:0] decode_2_io_fscoreboard; // @[Decode.scala 9:18]
   wire  decode_2_io_rs1Read_valid; // @[Decode.scala 9:18]
   wire [4:0] decode_2_io_rs1Read_addr; // @[Decode.scala 9:18]
   wire  decode_2_io_rs1Set_valid; // @[Decode.scala 9:18]
@@ -30581,7 +21455,7 @@
   wire [31:0] decode_2_io_busRead_immed; // @[Decode.scala 9:18]
   wire  decode_2_io_alu_valid; // @[Decode.scala 9:18]
   wire [4:0] decode_2_io_alu_addr; // @[Decode.scala 9:18]
-  wire [18:0] decode_2_io_alu_op; // @[Decode.scala 9:18]
+  wire [17:0] decode_2_io_alu_op; // @[Decode.scala 9:18]
   wire  decode_2_io_bru_valid; // @[Decode.scala 9:18]
   wire  decode_2_io_bru_fwd; // @[Decode.scala 9:18]
   wire [16:0] decode_2_io_bru_op; // @[Decode.scala 9:18]
@@ -30592,18 +21466,16 @@
   wire  decode_2_io_lsu_valid; // @[Decode.scala 9:18]
   wire  decode_2_io_lsu_ready; // @[Decode.scala 9:18]
   wire [4:0] decode_2_io_lsu_addr; // @[Decode.scala 9:18]
-  wire [13:0] decode_2_io_lsu_op; // @[Decode.scala 9:18]
+  wire [11:0] decode_2_io_lsu_op; // @[Decode.scala 9:18]
   wire  decode_2_io_mlu_valid; // @[Decode.scala 9:18]
   wire [4:0] decode_2_io_mlu_addr; // @[Decode.scala 9:18]
   wire [8:0] decode_2_io_mlu_op; // @[Decode.scala 9:18]
   wire [3:0] decode_2_io_dvu_op; // @[Decode.scala 9:18]
-  wire [4:0] decode_2_io_fpu_raddr_1; // @[Decode.scala 9:18]
-  wire [26:0] decode_2_io_fpu_op; // @[Decode.scala 9:18]
   wire  decode_2_io_vinst_valid; // @[Decode.scala 9:18]
   wire  decode_2_io_vinst_ready; // @[Decode.scala 9:18]
   wire [4:0] decode_2_io_vinst_addr; // @[Decode.scala 9:18]
   wire [31:0] decode_2_io_vinst_inst; // @[Decode.scala 9:18]
-  wire [5:0] decode_2_io_vinst_op; // @[Decode.scala 9:18]
+  wire [4:0] decode_2_io_vinst_op; // @[Decode.scala 9:18]
   wire  decode_2_io_branchTaken; // @[Decode.scala 9:18]
   wire  decode_2_io_interlock; // @[Decode.scala 9:18]
   wire  decode_2_io_serializeIn_mul; // @[Decode.scala 9:18]
@@ -30622,7 +21494,6 @@
   wire  decode_3_io_inst_brchFwd; // @[Decode.scala 9:18]
   wire [31:0] decode_3_io_scoreboard_regd; // @[Decode.scala 9:18]
   wire [31:0] decode_3_io_scoreboard_comb; // @[Decode.scala 9:18]
-  wire [31:0] decode_3_io_fscoreboard; // @[Decode.scala 9:18]
   wire  decode_3_io_rs1Read_valid; // @[Decode.scala 9:18]
   wire [4:0] decode_3_io_rs1Read_addr; // @[Decode.scala 9:18]
   wire  decode_3_io_rs1Set_valid; // @[Decode.scala 9:18]
@@ -30637,7 +21508,7 @@
   wire [31:0] decode_3_io_busRead_immed; // @[Decode.scala 9:18]
   wire  decode_3_io_alu_valid; // @[Decode.scala 9:18]
   wire [4:0] decode_3_io_alu_addr; // @[Decode.scala 9:18]
-  wire [18:0] decode_3_io_alu_op; // @[Decode.scala 9:18]
+  wire [17:0] decode_3_io_alu_op; // @[Decode.scala 9:18]
   wire  decode_3_io_bru_valid; // @[Decode.scala 9:18]
   wire  decode_3_io_bru_fwd; // @[Decode.scala 9:18]
   wire [16:0] decode_3_io_bru_op; // @[Decode.scala 9:18]
@@ -30648,18 +21519,16 @@
   wire  decode_3_io_lsu_valid; // @[Decode.scala 9:18]
   wire  decode_3_io_lsu_ready; // @[Decode.scala 9:18]
   wire [4:0] decode_3_io_lsu_addr; // @[Decode.scala 9:18]
-  wire [13:0] decode_3_io_lsu_op; // @[Decode.scala 9:18]
+  wire [11:0] decode_3_io_lsu_op; // @[Decode.scala 9:18]
   wire  decode_3_io_mlu_valid; // @[Decode.scala 9:18]
   wire [4:0] decode_3_io_mlu_addr; // @[Decode.scala 9:18]
   wire [8:0] decode_3_io_mlu_op; // @[Decode.scala 9:18]
   wire [3:0] decode_3_io_dvu_op; // @[Decode.scala 9:18]
-  wire [4:0] decode_3_io_fpu_raddr_1; // @[Decode.scala 9:18]
-  wire [26:0] decode_3_io_fpu_op; // @[Decode.scala 9:18]
   wire  decode_3_io_vinst_valid; // @[Decode.scala 9:18]
   wire  decode_3_io_vinst_ready; // @[Decode.scala 9:18]
   wire [4:0] decode_3_io_vinst_addr; // @[Decode.scala 9:18]
   wire [31:0] decode_3_io_vinst_inst; // @[Decode.scala 9:18]
-  wire [5:0] decode_3_io_vinst_op; // @[Decode.scala 9:18]
+  wire [4:0] decode_3_io_vinst_op; // @[Decode.scala 9:18]
   wire  decode_3_io_branchTaken; // @[Decode.scala 9:18]
   wire  decode_3_io_interlock; // @[Decode.scala 9:18]
   wire  decode_3_io_serializeIn_mul; // @[Decode.scala 9:18]
@@ -30669,7 +21538,7 @@
   wire  alu_0_reset; // @[Alu.scala 9:18]
   wire  alu_0_io_req_valid; // @[Alu.scala 9:18]
   wire [4:0] alu_0_io_req_addr; // @[Alu.scala 9:18]
-  wire [18:0] alu_0_io_req_op; // @[Alu.scala 9:18]
+  wire [17:0] alu_0_io_req_op; // @[Alu.scala 9:18]
   wire  alu_0_io_rs1_valid; // @[Alu.scala 9:18]
   wire [31:0] alu_0_io_rs1_data; // @[Alu.scala 9:18]
   wire  alu_0_io_rs2_valid; // @[Alu.scala 9:18]
@@ -30681,7 +21550,7 @@
   wire  alu_1_reset; // @[Alu.scala 9:18]
   wire  alu_1_io_req_valid; // @[Alu.scala 9:18]
   wire [4:0] alu_1_io_req_addr; // @[Alu.scala 9:18]
-  wire [18:0] alu_1_io_req_op; // @[Alu.scala 9:18]
+  wire [17:0] alu_1_io_req_op; // @[Alu.scala 9:18]
   wire  alu_1_io_rs1_valid; // @[Alu.scala 9:18]
   wire [31:0] alu_1_io_rs1_data; // @[Alu.scala 9:18]
   wire  alu_1_io_rs2_valid; // @[Alu.scala 9:18]
@@ -30693,7 +21562,7 @@
   wire  alu_2_reset; // @[Alu.scala 9:18]
   wire  alu_2_io_req_valid; // @[Alu.scala 9:18]
   wire [4:0] alu_2_io_req_addr; // @[Alu.scala 9:18]
-  wire [18:0] alu_2_io_req_op; // @[Alu.scala 9:18]
+  wire [17:0] alu_2_io_req_op; // @[Alu.scala 9:18]
   wire  alu_2_io_rs1_valid; // @[Alu.scala 9:18]
   wire [31:0] alu_2_io_rs1_data; // @[Alu.scala 9:18]
   wire  alu_2_io_rs2_valid; // @[Alu.scala 9:18]
@@ -30705,7 +21574,7 @@
   wire  alu_3_reset; // @[Alu.scala 9:18]
   wire  alu_3_io_req_valid; // @[Alu.scala 9:18]
   wire [4:0] alu_3_io_req_addr; // @[Alu.scala 9:18]
-  wire [18:0] alu_3_io_req_op; // @[Alu.scala 9:18]
+  wire [17:0] alu_3_io_req_op; // @[Alu.scala 9:18]
   wire  alu_3_io_rs1_valid; // @[Alu.scala 9:18]
   wire [31:0] alu_3_io_rs1_data; // @[Alu.scala 9:18]
   wire  alu_3_io_rs2_valid; // @[Alu.scala 9:18]
@@ -30878,19 +21747,19 @@
   wire  lsu_io_req_0_valid; // @[Lsu.scala 9:18]
   wire  lsu_io_req_0_ready; // @[Lsu.scala 9:18]
   wire [4:0] lsu_io_req_0_addr; // @[Lsu.scala 9:18]
-  wire [13:0] lsu_io_req_0_op; // @[Lsu.scala 9:18]
+  wire [11:0] lsu_io_req_0_op; // @[Lsu.scala 9:18]
   wire  lsu_io_req_1_valid; // @[Lsu.scala 9:18]
   wire  lsu_io_req_1_ready; // @[Lsu.scala 9:18]
   wire [4:0] lsu_io_req_1_addr; // @[Lsu.scala 9:18]
-  wire [13:0] lsu_io_req_1_op; // @[Lsu.scala 9:18]
+  wire [11:0] lsu_io_req_1_op; // @[Lsu.scala 9:18]
   wire  lsu_io_req_2_valid; // @[Lsu.scala 9:18]
   wire  lsu_io_req_2_ready; // @[Lsu.scala 9:18]
   wire [4:0] lsu_io_req_2_addr; // @[Lsu.scala 9:18]
-  wire [13:0] lsu_io_req_2_op; // @[Lsu.scala 9:18]
+  wire [11:0] lsu_io_req_2_op; // @[Lsu.scala 9:18]
   wire  lsu_io_req_3_valid; // @[Lsu.scala 9:18]
   wire  lsu_io_req_3_ready; // @[Lsu.scala 9:18]
   wire [4:0] lsu_io_req_3_addr; // @[Lsu.scala 9:18]
-  wire [13:0] lsu_io_req_3_op; // @[Lsu.scala 9:18]
+  wire [11:0] lsu_io_req_3_op; // @[Lsu.scala 9:18]
   wire [31:0] lsu_io_busPort_addr_0; // @[Lsu.scala 9:18]
   wire [31:0] lsu_io_busPort_addr_1; // @[Lsu.scala 9:18]
   wire [31:0] lsu_io_busPort_addr_2; // @[Lsu.scala 9:18]
@@ -30899,13 +21768,9 @@
   wire [31:0] lsu_io_busPort_data_1; // @[Lsu.scala 9:18]
   wire [31:0] lsu_io_busPort_data_2; // @[Lsu.scala 9:18]
   wire [31:0] lsu_io_busPort_data_3; // @[Lsu.scala 9:18]
-  wire [31:0] lsu_io_fbusPort_data; // @[Lsu.scala 9:18]
   wire  lsu_io_rd_valid; // @[Lsu.scala 9:18]
   wire [4:0] lsu_io_rd_addr; // @[Lsu.scala 9:18]
   wire [31:0] lsu_io_rd_data; // @[Lsu.scala 9:18]
-  wire  lsu_io_fd_valid; // @[Lsu.scala 9:18]
-  wire [4:0] lsu_io_fd_addr; // @[Lsu.scala 9:18]
-  wire [31:0] lsu_io_fd_data; // @[Lsu.scala 9:18]
   wire  lsu_io_dbus_valid; // @[Lsu.scala 9:18]
   wire  lsu_io_dbus_ready; // @[Lsu.scala 9:18]
   wire  lsu_io_dbus_write; // @[Lsu.scala 9:18]
@@ -30972,141 +21837,84 @@
   wire  dvu_io_rd_ready; // @[Dvu.scala 9:18]
   wire [4:0] dvu_io_rd_addr; // @[Dvu.scala 9:18]
   wire [31:0] dvu_io_rd_data; // @[Dvu.scala 9:18]
-  wire  fpu_clock; // @[Fpu.scala 8:18]
-  wire  fpu_reset; // @[Fpu.scala 8:18]
-  wire  fpu_io_req_0_valid; // @[Fpu.scala 8:18]
-  wire [4:0] fpu_io_req_0_raddr_0; // @[Fpu.scala 8:18]
-  wire [4:0] fpu_io_req_0_raddr_1; // @[Fpu.scala 8:18]
-  wire [4:0] fpu_io_req_0_raddr_2; // @[Fpu.scala 8:18]
-  wire [4:0] fpu_io_req_0_waddr; // @[Fpu.scala 8:18]
-  wire [26:0] fpu_io_req_0_op; // @[Fpu.scala 8:18]
-  wire  fpu_io_req_0_busyFDiv; // @[Fpu.scala 8:18]
-  wire  fpu_io_req_0_busyFSqrt; // @[Fpu.scala 8:18]
-  wire [4:0] fpu_io_req_1_raddr_1; // @[Fpu.scala 8:18]
-  wire [26:0] fpu_io_req_1_op; // @[Fpu.scala 8:18]
-  wire [4:0] fpu_io_req_2_raddr_1; // @[Fpu.scala 8:18]
-  wire [26:0] fpu_io_req_2_op; // @[Fpu.scala 8:18]
-  wire [4:0] fpu_io_req_3_raddr_1; // @[Fpu.scala 8:18]
-  wire [26:0] fpu_io_req_3_op; // @[Fpu.scala 8:18]
-  wire [31:0] fpu_io_fbusPort_data; // @[Fpu.scala 8:18]
-  wire  fpu_io_fwriteData_valid; // @[Fpu.scala 8:18]
-  wire [4:0] fpu_io_fwriteData_addr; // @[Fpu.scala 8:18]
-  wire [31:0] fpu_io_fwriteData_data; // @[Fpu.scala 8:18]
-  wire [31:0] fpu_io_readData_data; // @[Fpu.scala 8:18]
-  wire  fpu_io_writeData_0_valid; // @[Fpu.scala 8:18]
-  wire [4:0] fpu_io_writeData_0_addr; // @[Fpu.scala 8:18]
-  wire [31:0] fpu_io_writeData_0_data; // @[Fpu.scala 8:18]
-  wire  fpu_io_writeData_1_valid; // @[Fpu.scala 8:18]
-  wire [4:0] fpu_io_writeData_1_addr; // @[Fpu.scala 8:18]
-  wire [31:0] fpu_io_writeData_1_data; // @[Fpu.scala 8:18]
-  wire [31:0] fpu_io_fs_0_data; // @[Fpu.scala 8:18]
-  wire [31:0] fpu_io_fs_1_data; // @[Fpu.scala 8:18]
-  wire [31:0] fpu_io_fs_2_data; // @[Fpu.scala 8:18]
-  wire [31:0] fpu_io_fs_3_data; // @[Fpu.scala 8:18]
-  wire [31:0] fpu_io_fscoreboard; // @[Fpu.scala 8:18]
-  wire  _branchTaken_T_1 = bru_0_io_taken_valid | bru_1_io_taken_valid | bru_2_io_taken_valid; // @[SCore.scala 46:68]
-  reg  iflush; // @[SCore.scala 51:23]
-  wire  _T_1 = fetch_io_iflush_ready & lsu_io_flush_ready; // @[SCore.scala 55:57]
-  wire  _GEN_0 = _T_1 & lsu_io_flush_fencei ? 1'h0 : iflush; // @[SCore.scala 56:59 57:12 51:23]
-  wire  _T_5 = ~reset; // @[SCore.scala 65:9]
-  wire  mask_2 = decode_0_io_inst_ready & decode_1_io_inst_ready; // @[SCore.scala 85:46]
-  wire  mask_3 = mask_2 & decode_2_io_inst_ready; // @[SCore.scala 86:73]
-  wire  _fetch_io_inst_lanes_0_ready_T = decode_0_io_inst_ready; // @[SCore.scala 91:61]
-  reg [1:0] interlockPipe2Reg; // @[SCore.scala 103:34]
-  reg  interlockPipe3; // @[SCore.scala 104:34]
-  wire  _interlockPipe2Reg_T_2 = decode_0_io_fpu_op[16] | decode_0_io_fpu_op[17]; // @[SCore.scala 109:42]
-  wire  _interlockPipe2Reg_T_3 = decode_0_io_fpu_valid & _interlockPipe2Reg_T_2; // @[SCore.scala 108:51]
-  wire  interlockPipe2 = interlockPipe2Reg[0]; // @[SCore.scala 116:41]
-  wire [31:0] scoreboard_spec2 = decode_1_io_scoreboard_spec | decode_0_io_scoreboard_spec; // @[SCore.scala 132:55]
-  wire [31:0] scoreboard_spec3 = decode_2_io_scoreboard_spec | scoreboard_spec2; // @[SCore.scala 133:55]
-  wire [4:0] fwriteMask_shiftAmount = decode_0_io_fpu_waddr; // @[OneHot.scala 63:49]
-  wire [31:0] _fwriteMask_T = 32'h1 << fwriteMask_shiftAmount; // @[OneHot.scala 64:12]
-  wire [31:0] fwriteMask = decode_0_io_fpu_valid ? _fwriteMask_T : 32'h0; // @[Library.scala 8:8]
-  wire  _regfile_io_writeData_0_valid_T_2 = csr_io_rd_valid | alu_0_io_rd_valid; // @[SCore.scala 259:74]
+  wire  _branchTaken_T_1 = bru_0_io_taken_valid | bru_1_io_taken_valid | bru_2_io_taken_valid; // @[SCore.scala 45:68]
+  reg  iflush; // @[SCore.scala 50:23]
+  wire  _T_1 = fetch_io_iflush_ready & lsu_io_flush_ready; // @[SCore.scala 54:57]
+  wire  _GEN_0 = _T_1 & lsu_io_flush_fencei ? 1'h0 : iflush; // @[SCore.scala 55:59 56:12 50:23]
+  wire  _T_5 = ~reset; // @[SCore.scala 64:9]
+  wire  mask_2 = decode_0_io_inst_ready & decode_1_io_inst_ready; // @[SCore.scala 84:46]
+  wire  mask_3 = mask_2 & decode_2_io_inst_ready; // @[SCore.scala 85:73]
+  wire  _fetch_io_inst_lanes_0_ready_T = decode_0_io_inst_ready; // @[SCore.scala 90:61]
+  wire [31:0] scoreboard_spec2 = decode_1_io_scoreboard_spec | decode_0_io_scoreboard_spec; // @[SCore.scala 123:55]
+  wire [31:0] scoreboard_spec3 = decode_2_io_scoreboard_spec | scoreboard_spec2; // @[SCore.scala 124:55]
+  reg  mluInvalidate; // @[SCore.scala 210:30]
+  wire  _regfile_io_writeData_0_valid_T = csr_io_rd_valid | alu_0_io_rd_valid; // @[SCore.scala 240:48]
   wire [4:0] _regfile_io_writeData_0_addr_T = csr_io_rd_valid ? csr_io_rd_addr : 5'h0; // @[Library.scala 8:8]
-  wire [4:0] _regfile_io_writeData_0_addr_T_5 = alu_0_io_rd_valid ? alu_0_io_rd_addr : 5'h0; // @[Library.scala 8:8]
-  wire [4:0] _regfile_io_writeData_0_addr_T_6 = _regfile_io_writeData_0_addr_T | _regfile_io_writeData_0_addr_T_5; // @[SCore.scala 266:36]
-  wire [4:0] _regfile_io_writeData_0_addr_T_7 = bru_0_io_rd_valid ? bru_0_io_rd_addr : 5'h0; // @[Library.scala 8:8]
-  wire [4:0] _regfile_io_writeData_0_addr_T_8 = _regfile_io_writeData_0_addr_T_6 | _regfile_io_writeData_0_addr_T_7; // @[SCore.scala 267:54]
-  wire [4:0] _regfile_io_writeData_0_addr_T_9 = io_vcore_rd_0_valid ? io_vcore_rd_0_addr : 5'h0; // @[Library.scala 8:8]
+  wire [4:0] _regfile_io_writeData_0_addr_T_1 = alu_0_io_rd_valid ? alu_0_io_rd_addr : 5'h0; // @[Library.scala 8:8]
+  wire [4:0] _regfile_io_writeData_0_addr_T_2 = _regfile_io_writeData_0_addr_T | _regfile_io_writeData_0_addr_T_1; // @[SCore.scala 245:36]
+  wire [4:0] _regfile_io_writeData_0_addr_T_3 = bru_0_io_rd_valid ? bru_0_io_rd_addr : 5'h0; // @[Library.scala 8:8]
+  wire [4:0] _regfile_io_writeData_0_addr_T_4 = _regfile_io_writeData_0_addr_T_2 | _regfile_io_writeData_0_addr_T_3; // @[SCore.scala 246:54]
+  wire [4:0] _regfile_io_writeData_0_addr_T_5 = io_vcore_rd_0_valid ? io_vcore_rd_0_addr : 5'h0; // @[Library.scala 8:8]
   wire [31:0] _regfile_io_writeData_0_data_T = csr_io_rd_valid ? csr_io_rd_data : 32'h0; // @[Library.scala 8:8]
-  wire [31:0] _regfile_io_writeData_0_data_T_5 = alu_0_io_rd_valid ? alu_0_io_rd_data : 32'h0; // @[Library.scala 8:8]
-  wire [31:0] _regfile_io_writeData_0_data_T_6 = _regfile_io_writeData_0_data_T | _regfile_io_writeData_0_data_T_5; // @[SCore.scala 274:36]
-  wire [31:0] _regfile_io_writeData_0_data_T_7 = bru_0_io_rd_valid ? bru_0_io_rd_data : 32'h0; // @[Library.scala 8:8]
-  wire [31:0] _regfile_io_writeData_0_data_T_8 = _regfile_io_writeData_0_data_T_6 | _regfile_io_writeData_0_data_T_7; // @[SCore.scala 275:54]
-  wire [31:0] _regfile_io_writeData_0_data_T_9 = io_vcore_rd_0_valid ? io_vcore_rd_0_data : 32'h0; // @[Library.scala 8:8]
-  wire [1:0] _T_15 = {{1'd0}, csr_io_rd_valid}; // @[SCore.scala 279:23]
-  wire [2:0] _T_16 = {{1'd0}, _T_15}; // @[SCore.scala 279:36]
-  wire [2:0] _GEN_3 = {{2'd0}, alu_0_io_rd_valid}; // @[SCore.scala 279:49]
-  wire [3:0] _T_17 = _T_16 + _GEN_3; // @[SCore.scala 279:49]
-  wire [3:0] _GEN_4 = {{3'd0}, bru_0_io_rd_valid}; // @[SCore.scala 280:32]
-  wire [4:0] _T_18 = _T_17 + _GEN_4; // @[SCore.scala 280:32]
-  wire [4:0] _GEN_5 = {{4'd0}, io_vcore_rd_0_valid}; // @[SCore.scala 280:54]
-  wire [5:0] _T_19 = _T_18 + _GEN_5; // @[SCore.scala 280:54]
-  wire  _T_20 = _T_19 <= 6'h1; // @[SCore.scala 281:35]
-  wire  _regfile_io_writeData_1_valid_T_2 = alu_1_io_rd_valid; // @[SCore.scala 259:74]
-  wire [4:0] _regfile_io_writeData_1_addr_T_5 = alu_1_io_rd_valid ? alu_1_io_rd_addr : 5'h0; // @[Library.scala 8:8]
-  wire [4:0] _regfile_io_writeData_1_addr_T_7 = bru_1_io_rd_valid ? bru_1_io_rd_addr : 5'h0; // @[Library.scala 8:8]
-  wire [4:0] _regfile_io_writeData_1_addr_T_8 = _regfile_io_writeData_1_addr_T_5 | _regfile_io_writeData_1_addr_T_7; // @[SCore.scala 267:54]
-  wire [4:0] _regfile_io_writeData_1_addr_T_9 = io_vcore_rd_1_valid ? io_vcore_rd_1_addr : 5'h0; // @[Library.scala 8:8]
-  wire [31:0] _regfile_io_writeData_1_data_T_5 = alu_1_io_rd_valid ? alu_1_io_rd_data : 32'h0; // @[Library.scala 8:8]
-  wire [31:0] _regfile_io_writeData_1_data_T_7 = bru_1_io_rd_valid ? bru_1_io_rd_data : 32'h0; // @[Library.scala 8:8]
-  wire [31:0] _regfile_io_writeData_1_data_T_8 = _regfile_io_writeData_1_data_T_5 | _regfile_io_writeData_1_data_T_7; // @[SCore.scala 275:54]
-  wire [31:0] _regfile_io_writeData_1_data_T_9 = io_vcore_rd_1_valid ? io_vcore_rd_1_data : 32'h0; // @[Library.scala 8:8]
-  wire [2:0] _GEN_6 = {{2'd0}, alu_1_io_rd_valid}; // @[SCore.scala 279:49]
-  wire [3:0] _T_26 = {{1'd0}, _GEN_6}; // @[SCore.scala 279:49]
-  wire [3:0] _GEN_7 = {{3'd0}, bru_1_io_rd_valid}; // @[SCore.scala 280:32]
-  wire [4:0] _T_27 = _T_26 + _GEN_7; // @[SCore.scala 280:32]
-  wire [4:0] _GEN_8 = {{4'd0}, io_vcore_rd_1_valid}; // @[SCore.scala 280:54]
-  wire [5:0] _T_28 = _T_27 + _GEN_8; // @[SCore.scala 280:54]
-  wire  _T_29 = _T_28 <= 6'h1; // @[SCore.scala 281:35]
-  wire  _regfile_io_writeData_2_valid_T_2 = fpu_io_writeData_1_valid | alu_2_io_rd_valid; // @[SCore.scala 259:74]
-  wire [4:0] _regfile_io_writeData_2_addr_T_3 = fpu_io_writeData_1_valid ? fpu_io_writeData_1_addr : 5'h0; // @[Library.scala 8:8]
-  wire [4:0] _regfile_io_writeData_2_addr_T_5 = alu_2_io_rd_valid ? alu_2_io_rd_addr : 5'h0; // @[Library.scala 8:8]
-  wire [4:0] _regfile_io_writeData_2_addr_T_6 = _regfile_io_writeData_2_addr_T_3 | _regfile_io_writeData_2_addr_T_5; // @[SCore.scala 266:36]
-  wire [4:0] _regfile_io_writeData_2_addr_T_7 = bru_2_io_rd_valid ? bru_2_io_rd_addr : 5'h0; // @[Library.scala 8:8]
-  wire [4:0] _regfile_io_writeData_2_addr_T_8 = _regfile_io_writeData_2_addr_T_6 | _regfile_io_writeData_2_addr_T_7; // @[SCore.scala 267:54]
-  wire [4:0] _regfile_io_writeData_2_addr_T_9 = io_vcore_rd_2_valid ? io_vcore_rd_2_addr : 5'h0; // @[Library.scala 8:8]
-  wire [31:0] _regfile_io_writeData_2_data_T_3 = fpu_io_writeData_1_valid ? fpu_io_writeData_1_data : 32'h0; // @[Library.scala 8:8]
-  wire [31:0] _regfile_io_writeData_2_data_T_5 = alu_2_io_rd_valid ? alu_2_io_rd_data : 32'h0; // @[Library.scala 8:8]
-  wire [31:0] _regfile_io_writeData_2_data_T_6 = _regfile_io_writeData_2_data_T_3 | _regfile_io_writeData_2_data_T_5; // @[SCore.scala 274:36]
-  wire [31:0] _regfile_io_writeData_2_data_T_7 = bru_2_io_rd_valid ? bru_2_io_rd_data : 32'h0; // @[Library.scala 8:8]
-  wire [31:0] _regfile_io_writeData_2_data_T_8 = _regfile_io_writeData_2_data_T_6 | _regfile_io_writeData_2_data_T_7; // @[SCore.scala 275:54]
-  wire [31:0] _regfile_io_writeData_2_data_T_9 = io_vcore_rd_2_valid ? io_vcore_rd_2_data : 32'h0; // @[Library.scala 8:8]
-  wire [1:0] _GEN_9 = {{1'd0}, fpu_io_writeData_1_valid}; // @[SCore.scala 279:36]
-  wire [2:0] _T_34 = {{1'd0}, _GEN_9}; // @[SCore.scala 279:36]
-  wire [2:0] _GEN_10 = {{2'd0}, alu_2_io_rd_valid}; // @[SCore.scala 279:49]
-  wire [3:0] _T_35 = _T_34 + _GEN_10; // @[SCore.scala 279:49]
-  wire [3:0] _GEN_11 = {{3'd0}, bru_2_io_rd_valid}; // @[SCore.scala 280:32]
-  wire [4:0] _T_36 = _T_35 + _GEN_11; // @[SCore.scala 280:32]
-  wire [4:0] _GEN_12 = {{4'd0}, io_vcore_rd_2_valid}; // @[SCore.scala 280:54]
-  wire [5:0] _T_37 = _T_36 + _GEN_12; // @[SCore.scala 280:54]
-  wire  _T_38 = _T_37 <= 6'h1; // @[SCore.scala 281:35]
-  wire  _regfile_io_writeData_3_valid_T_2 = fpu_io_writeData_0_valid | alu_3_io_rd_valid; // @[SCore.scala 259:74]
-  wire [4:0] _regfile_io_writeData_3_addr_T_1 = fpu_io_writeData_0_valid ? fpu_io_writeData_0_addr : 5'h0; // @[Library.scala 8:8]
-  wire [4:0] _regfile_io_writeData_3_addr_T_5 = alu_3_io_rd_valid ? alu_3_io_rd_addr : 5'h0; // @[Library.scala 8:8]
-  wire [4:0] _regfile_io_writeData_3_addr_T_6 = _regfile_io_writeData_3_addr_T_1 | _regfile_io_writeData_3_addr_T_5; // @[SCore.scala 266:36]
-  wire [4:0] _regfile_io_writeData_3_addr_T_7 = bru_3_io_rd_valid ? bru_3_io_rd_addr : 5'h0; // @[Library.scala 8:8]
-  wire [4:0] _regfile_io_writeData_3_addr_T_8 = _regfile_io_writeData_3_addr_T_6 | _regfile_io_writeData_3_addr_T_7; // @[SCore.scala 267:54]
-  wire [4:0] _regfile_io_writeData_3_addr_T_9 = io_vcore_rd_3_valid ? io_vcore_rd_3_addr : 5'h0; // @[Library.scala 8:8]
-  wire [31:0] _regfile_io_writeData_3_data_T_1 = fpu_io_writeData_0_valid ? fpu_io_writeData_0_data : 32'h0; // @[Library.scala 8:8]
-  wire [31:0] _regfile_io_writeData_3_data_T_5 = alu_3_io_rd_valid ? alu_3_io_rd_data : 32'h0; // @[Library.scala 8:8]
-  wire [31:0] _regfile_io_writeData_3_data_T_6 = _regfile_io_writeData_3_data_T_1 | _regfile_io_writeData_3_data_T_5; // @[SCore.scala 274:36]
-  wire [31:0] _regfile_io_writeData_3_data_T_7 = bru_3_io_rd_valid ? bru_3_io_rd_data : 32'h0; // @[Library.scala 8:8]
-  wire [31:0] _regfile_io_writeData_3_data_T_8 = _regfile_io_writeData_3_data_T_6 | _regfile_io_writeData_3_data_T_7; // @[SCore.scala 275:54]
-  wire [31:0] _regfile_io_writeData_3_data_T_9 = io_vcore_rd_3_valid ? io_vcore_rd_3_data : 32'h0; // @[Library.scala 8:8]
-  wire [1:0] _T_42 = {{1'd0}, fpu_io_writeData_0_valid}; // @[SCore.scala 279:23]
-  wire [2:0] _T_43 = {{1'd0}, _T_42}; // @[SCore.scala 279:36]
-  wire [2:0] _GEN_13 = {{2'd0}, alu_3_io_rd_valid}; // @[SCore.scala 279:49]
-  wire [3:0] _T_44 = _T_43 + _GEN_13; // @[SCore.scala 279:49]
-  wire [3:0] _GEN_14 = {{3'd0}, bru_3_io_rd_valid}; // @[SCore.scala 280:32]
-  wire [4:0] _T_45 = _T_44 + _GEN_14; // @[SCore.scala 280:32]
-  wire [4:0] _GEN_15 = {{4'd0}, io_vcore_rd_3_valid}; // @[SCore.scala 280:54]
-  wire [5:0] _T_46 = _T_45 + _GEN_15; // @[SCore.scala 280:54]
-  wire  _T_47 = _T_46 <= 6'h1; // @[SCore.scala 281:35]
-  reg  slogValid; // @[SCore.scala 344:26]
-  reg [1:0] slogAddr; // @[SCore.scala 345:21]
-  wire [2:0] _GEN_2 = decode_0_io_slog ? decode_0_io_inst_inst[14:12] : {{1'd0}, slogAddr}; // @[SCore.scala 349:17 350:14 345:21]
+  wire [31:0] _regfile_io_writeData_0_data_T_1 = alu_0_io_rd_valid ? alu_0_io_rd_data : 32'h0; // @[Library.scala 8:8]
+  wire [31:0] _regfile_io_writeData_0_data_T_2 = _regfile_io_writeData_0_data_T | _regfile_io_writeData_0_data_T_1; // @[SCore.scala 251:36]
+  wire [31:0] _regfile_io_writeData_0_data_T_3 = bru_0_io_rd_valid ? bru_0_io_rd_data : 32'h0; // @[Library.scala 8:8]
+  wire [31:0] _regfile_io_writeData_0_data_T_4 = _regfile_io_writeData_0_data_T_2 | _regfile_io_writeData_0_data_T_3; // @[SCore.scala 252:54]
+  wire [31:0] _regfile_io_writeData_0_data_T_5 = io_vcore_rd_0_valid ? io_vcore_rd_0_data : 32'h0; // @[Library.scala 8:8]
+  wire [1:0] _T_15 = csr_io_rd_valid + alu_0_io_rd_valid; // @[SCore.scala 256:23]
+  wire [1:0] _GEN_3 = {{1'd0}, bru_0_io_rd_valid}; // @[SCore.scala 257:32]
+  wire [2:0] _T_16 = _T_15 + _GEN_3; // @[SCore.scala 257:32]
+  wire [2:0] _GEN_4 = {{2'd0}, io_vcore_rd_0_valid}; // @[SCore.scala 257:54]
+  wire [3:0] _T_17 = _T_16 + _GEN_4; // @[SCore.scala 257:54]
+  wire  _T_18 = _T_17 <= 4'h1; // @[SCore.scala 258:35]
+  wire  _regfile_io_writeData_1_valid_T = alu_1_io_rd_valid; // @[SCore.scala 240:48]
+  wire [4:0] _regfile_io_writeData_1_addr_T_1 = alu_1_io_rd_valid ? alu_1_io_rd_addr : 5'h0; // @[Library.scala 8:8]
+  wire [4:0] _regfile_io_writeData_1_addr_T_3 = bru_1_io_rd_valid ? bru_1_io_rd_addr : 5'h0; // @[Library.scala 8:8]
+  wire [4:0] _regfile_io_writeData_1_addr_T_4 = _regfile_io_writeData_1_addr_T_1 | _regfile_io_writeData_1_addr_T_3; // @[SCore.scala 246:54]
+  wire [4:0] _regfile_io_writeData_1_addr_T_5 = io_vcore_rd_1_valid ? io_vcore_rd_1_addr : 5'h0; // @[Library.scala 8:8]
+  wire [31:0] _regfile_io_writeData_1_data_T_1 = alu_1_io_rd_valid ? alu_1_io_rd_data : 32'h0; // @[Library.scala 8:8]
+  wire [31:0] _regfile_io_writeData_1_data_T_3 = bru_1_io_rd_valid ? bru_1_io_rd_data : 32'h0; // @[Library.scala 8:8]
+  wire [31:0] _regfile_io_writeData_1_data_T_4 = _regfile_io_writeData_1_data_T_1 | _regfile_io_writeData_1_data_T_3; // @[SCore.scala 252:54]
+  wire [31:0] _regfile_io_writeData_1_data_T_5 = io_vcore_rd_1_valid ? io_vcore_rd_1_data : 32'h0; // @[Library.scala 8:8]
+  wire [1:0] _T_22 = {{1'd0}, alu_1_io_rd_valid}; // @[SCore.scala 256:23]
+  wire [1:0] _GEN_5 = {{1'd0}, bru_1_io_rd_valid}; // @[SCore.scala 257:32]
+  wire [2:0] _T_23 = _T_22 + _GEN_5; // @[SCore.scala 257:32]
+  wire [2:0] _GEN_6 = {{2'd0}, io_vcore_rd_1_valid}; // @[SCore.scala 257:54]
+  wire [3:0] _T_24 = _T_23 + _GEN_6; // @[SCore.scala 257:54]
+  wire  _T_25 = _T_24 <= 4'h1; // @[SCore.scala 258:35]
+  wire  _regfile_io_writeData_2_valid_T = alu_2_io_rd_valid; // @[SCore.scala 240:48]
+  wire [4:0] _regfile_io_writeData_2_addr_T_1 = alu_2_io_rd_valid ? alu_2_io_rd_addr : 5'h0; // @[Library.scala 8:8]
+  wire [4:0] _regfile_io_writeData_2_addr_T_3 = bru_2_io_rd_valid ? bru_2_io_rd_addr : 5'h0; // @[Library.scala 8:8]
+  wire [4:0] _regfile_io_writeData_2_addr_T_4 = _regfile_io_writeData_2_addr_T_1 | _regfile_io_writeData_2_addr_T_3; // @[SCore.scala 246:54]
+  wire [4:0] _regfile_io_writeData_2_addr_T_5 = io_vcore_rd_2_valid ? io_vcore_rd_2_addr : 5'h0; // @[Library.scala 8:8]
+  wire [31:0] _regfile_io_writeData_2_data_T_1 = alu_2_io_rd_valid ? alu_2_io_rd_data : 32'h0; // @[Library.scala 8:8]
+  wire [31:0] _regfile_io_writeData_2_data_T_3 = bru_2_io_rd_valid ? bru_2_io_rd_data : 32'h0; // @[Library.scala 8:8]
+  wire [31:0] _regfile_io_writeData_2_data_T_4 = _regfile_io_writeData_2_data_T_1 | _regfile_io_writeData_2_data_T_3; // @[SCore.scala 252:54]
+  wire [31:0] _regfile_io_writeData_2_data_T_5 = io_vcore_rd_2_valid ? io_vcore_rd_2_data : 32'h0; // @[Library.scala 8:8]
+  wire [1:0] _T_29 = {{1'd0}, alu_2_io_rd_valid}; // @[SCore.scala 256:23]
+  wire [1:0] _GEN_7 = {{1'd0}, bru_2_io_rd_valid}; // @[SCore.scala 257:32]
+  wire [2:0] _T_30 = _T_29 + _GEN_7; // @[SCore.scala 257:32]
+  wire [2:0] _GEN_8 = {{2'd0}, io_vcore_rd_2_valid}; // @[SCore.scala 257:54]
+  wire [3:0] _T_31 = _T_30 + _GEN_8; // @[SCore.scala 257:54]
+  wire  _T_32 = _T_31 <= 4'h1; // @[SCore.scala 258:35]
+  wire  _regfile_io_writeData_3_valid_T = alu_3_io_rd_valid; // @[SCore.scala 240:48]
+  wire [4:0] _regfile_io_writeData_3_addr_T_1 = alu_3_io_rd_valid ? alu_3_io_rd_addr : 5'h0; // @[Library.scala 8:8]
+  wire [4:0] _regfile_io_writeData_3_addr_T_3 = bru_3_io_rd_valid ? bru_3_io_rd_addr : 5'h0; // @[Library.scala 8:8]
+  wire [4:0] _regfile_io_writeData_3_addr_T_4 = _regfile_io_writeData_3_addr_T_1 | _regfile_io_writeData_3_addr_T_3; // @[SCore.scala 246:54]
+  wire [4:0] _regfile_io_writeData_3_addr_T_5 = io_vcore_rd_3_valid ? io_vcore_rd_3_addr : 5'h0; // @[Library.scala 8:8]
+  wire [31:0] _regfile_io_writeData_3_data_T_1 = alu_3_io_rd_valid ? alu_3_io_rd_data : 32'h0; // @[Library.scala 8:8]
+  wire [31:0] _regfile_io_writeData_3_data_T_3 = bru_3_io_rd_valid ? bru_3_io_rd_data : 32'h0; // @[Library.scala 8:8]
+  wire [31:0] _regfile_io_writeData_3_data_T_4 = _regfile_io_writeData_3_data_T_1 | _regfile_io_writeData_3_data_T_3; // @[SCore.scala 252:54]
+  wire [31:0] _regfile_io_writeData_3_data_T_5 = io_vcore_rd_3_valid ? io_vcore_rd_3_data : 32'h0; // @[Library.scala 8:8]
+  wire [1:0] _T_36 = {{1'd0}, alu_3_io_rd_valid}; // @[SCore.scala 256:23]
+  wire [1:0] _GEN_9 = {{1'd0}, bru_3_io_rd_valid}; // @[SCore.scala 257:32]
+  wire [2:0] _T_37 = _T_36 + _GEN_9; // @[SCore.scala 257:32]
+  wire [2:0] _GEN_10 = {{2'd0}, io_vcore_rd_3_valid}; // @[SCore.scala 257:54]
+  wire [3:0] _T_38 = _T_37 + _GEN_10; // @[SCore.scala 257:54]
+  wire  _T_39 = _T_38 <= 4'h1; // @[SCore.scala 258:35]
+  reg  slogValid; // @[SCore.scala 302:26]
+  reg [1:0] slogAddr; // @[SCore.scala 303:21]
+  wire [2:0] _GEN_2 = decode_0_io_slog ? decode_0_io_inst_inst[14:12] : {{1'd0}, slogAddr}; // @[SCore.scala 307:17 308:14 303:21]
   wire [1:0] _io_slog_addr_T = slogValid ? slogAddr : 2'h0; // @[Library.scala 8:8]
   Regfile regfile ( // @[Regfile.scala 9:18]
     .clock(regfile_clock),
@@ -31212,6 +22020,7 @@
     .io_writeMask_1_valid(regfile_io_writeMask_1_valid),
     .io_writeMask_2_valid(regfile_io_writeMask_2_valid),
     .io_writeMask_3_valid(regfile_io_writeMask_3_valid),
+    .io_writeMask_4_valid(regfile_io_writeMask_4_valid),
     .io_scoreboard_regd(regfile_io_scoreboard_regd),
     .io_scoreboard_comb(regfile_io_scoreboard_comb)
   );
@@ -31268,7 +22077,6 @@
     .io_scoreboard_regd(decode_0_io_scoreboard_regd),
     .io_scoreboard_comb(decode_0_io_scoreboard_comb),
     .io_scoreboard_spec(decode_0_io_scoreboard_spec),
-    .io_fscoreboard(decode_0_io_fscoreboard),
     .io_mactive(decode_0_io_mactive),
     .io_rs1Read_valid(decode_0_io_rs1Read_valid),
     .io_rs1Read_addr(decode_0_io_rs1Read_addr),
@@ -31307,14 +22115,6 @@
     .io_dvu_ready(decode_0_io_dvu_ready),
     .io_dvu_addr(decode_0_io_dvu_addr),
     .io_dvu_op(decode_0_io_dvu_op),
-    .io_fpu_valid(decode_0_io_fpu_valid),
-    .io_fpu_raddr_0(decode_0_io_fpu_raddr_0),
-    .io_fpu_raddr_1(decode_0_io_fpu_raddr_1),
-    .io_fpu_raddr_2(decode_0_io_fpu_raddr_2),
-    .io_fpu_waddr(decode_0_io_fpu_waddr),
-    .io_fpu_op(decode_0_io_fpu_op),
-    .io_fpu_busyFDiv(decode_0_io_fpu_busyFDiv),
-    .io_fpu_busyFSqrt(decode_0_io_fpu_busyFSqrt),
     .io_vinst_valid(decode_0_io_vinst_valid),
     .io_vinst_ready(decode_0_io_vinst_ready),
     .io_vinst_addr(decode_0_io_vinst_addr),
@@ -31339,7 +22139,6 @@
     .io_scoreboard_regd(decode_1_io_scoreboard_regd),
     .io_scoreboard_comb(decode_1_io_scoreboard_comb),
     .io_scoreboard_spec(decode_1_io_scoreboard_spec),
-    .io_fscoreboard(decode_1_io_fscoreboard),
     .io_rs1Read_valid(decode_1_io_rs1Read_valid),
     .io_rs1Read_addr(decode_1_io_rs1Read_addr),
     .io_rs1Set_valid(decode_1_io_rs1Set_valid),
@@ -31370,8 +22169,6 @@
     .io_mlu_addr(decode_1_io_mlu_addr),
     .io_mlu_op(decode_1_io_mlu_op),
     .io_dvu_op(decode_1_io_dvu_op),
-    .io_fpu_raddr_1(decode_1_io_fpu_raddr_1),
-    .io_fpu_op(decode_1_io_fpu_op),
     .io_vinst_valid(decode_1_io_vinst_valid),
     .io_vinst_ready(decode_1_io_vinst_ready),
     .io_vinst_addr(decode_1_io_vinst_addr),
@@ -31398,7 +22195,6 @@
     .io_scoreboard_regd(decode_2_io_scoreboard_regd),
     .io_scoreboard_comb(decode_2_io_scoreboard_comb),
     .io_scoreboard_spec(decode_2_io_scoreboard_spec),
-    .io_fscoreboard(decode_2_io_fscoreboard),
     .io_rs1Read_valid(decode_2_io_rs1Read_valid),
     .io_rs1Read_addr(decode_2_io_rs1Read_addr),
     .io_rs1Set_valid(decode_2_io_rs1Set_valid),
@@ -31429,8 +22225,6 @@
     .io_mlu_addr(decode_2_io_mlu_addr),
     .io_mlu_op(decode_2_io_mlu_op),
     .io_dvu_op(decode_2_io_dvu_op),
-    .io_fpu_raddr_1(decode_2_io_fpu_raddr_1),
-    .io_fpu_op(decode_2_io_fpu_op),
     .io_vinst_valid(decode_2_io_vinst_valid),
     .io_vinst_ready(decode_2_io_vinst_ready),
     .io_vinst_addr(decode_2_io_vinst_addr),
@@ -31456,7 +22250,6 @@
     .io_inst_brchFwd(decode_3_io_inst_brchFwd),
     .io_scoreboard_regd(decode_3_io_scoreboard_regd),
     .io_scoreboard_comb(decode_3_io_scoreboard_comb),
-    .io_fscoreboard(decode_3_io_fscoreboard),
     .io_rs1Read_valid(decode_3_io_rs1Read_valid),
     .io_rs1Read_addr(decode_3_io_rs1Read_addr),
     .io_rs1Set_valid(decode_3_io_rs1Set_valid),
@@ -31487,8 +22280,6 @@
     .io_mlu_addr(decode_3_io_mlu_addr),
     .io_mlu_op(decode_3_io_mlu_op),
     .io_dvu_op(decode_3_io_dvu_op),
-    .io_fpu_raddr_1(decode_3_io_fpu_raddr_1),
-    .io_fpu_op(decode_3_io_fpu_op),
     .io_vinst_valid(decode_3_io_vinst_valid),
     .io_vinst_ready(decode_3_io_vinst_ready),
     .io_vinst_addr(decode_3_io_vinst_addr),
@@ -31753,13 +22544,9 @@
     .io_busPort_data_1(lsu_io_busPort_data_1),
     .io_busPort_data_2(lsu_io_busPort_data_2),
     .io_busPort_data_3(lsu_io_busPort_data_3),
-    .io_fbusPort_data(lsu_io_fbusPort_data),
     .io_rd_valid(lsu_io_rd_valid),
     .io_rd_addr(lsu_io_rd_addr),
     .io_rd_data(lsu_io_rd_data),
-    .io_fd_valid(lsu_io_fd_valid),
-    .io_fd_addr(lsu_io_fd_addr),
-    .io_fd_data(lsu_io_fd_data),
     .io_dbus_valid(lsu_io_dbus_valid),
     .io_dbus_ready(lsu_io_dbus_ready),
     .io_dbus_write(lsu_io_dbus_write),
@@ -31831,457 +22618,395 @@
     .io_rd_addr(dvu_io_rd_addr),
     .io_rd_data(dvu_io_rd_data)
   );
-  Fpu fpu ( // @[Fpu.scala 8:18]
-    .clock(fpu_clock),
-    .reset(fpu_reset),
-    .io_req_0_valid(fpu_io_req_0_valid),
-    .io_req_0_raddr_0(fpu_io_req_0_raddr_0),
-    .io_req_0_raddr_1(fpu_io_req_0_raddr_1),
-    .io_req_0_raddr_2(fpu_io_req_0_raddr_2),
-    .io_req_0_waddr(fpu_io_req_0_waddr),
-    .io_req_0_op(fpu_io_req_0_op),
-    .io_req_0_busyFDiv(fpu_io_req_0_busyFDiv),
-    .io_req_0_busyFSqrt(fpu_io_req_0_busyFSqrt),
-    .io_req_1_raddr_1(fpu_io_req_1_raddr_1),
-    .io_req_1_op(fpu_io_req_1_op),
-    .io_req_2_raddr_1(fpu_io_req_2_raddr_1),
-    .io_req_2_op(fpu_io_req_2_op),
-    .io_req_3_raddr_1(fpu_io_req_3_raddr_1),
-    .io_req_3_op(fpu_io_req_3_op),
-    .io_fbusPort_data(fpu_io_fbusPort_data),
-    .io_fwriteData_valid(fpu_io_fwriteData_valid),
-    .io_fwriteData_addr(fpu_io_fwriteData_addr),
-    .io_fwriteData_data(fpu_io_fwriteData_data),
-    .io_readData_data(fpu_io_readData_data),
-    .io_writeData_0_valid(fpu_io_writeData_0_valid),
-    .io_writeData_0_addr(fpu_io_writeData_0_addr),
-    .io_writeData_0_data(fpu_io_writeData_0_data),
-    .io_writeData_1_valid(fpu_io_writeData_1_valid),
-    .io_writeData_1_addr(fpu_io_writeData_1_addr),
-    .io_writeData_1_data(fpu_io_writeData_1_data),
-    .io_fs_0_data(fpu_io_fs_0_data),
-    .io_fs_1_data(fpu_io_fs_1_data),
-    .io_fs_2_data(fpu_io_fs_2_data),
-    .io_fs_3_data(fpu_io_fs_3_data),
-    .io_fscoreboard(fpu_io_fscoreboard)
-  );
-  assign io_halted = csr_io_halted; // @[SCore.scala 194:13]
-  assign io_fault = csr_io_fault; // @[SCore.scala 195:13]
-  assign io_ibus_valid = fetch_io_ibus_valid; // @[SCore.scala 333:11]
-  assign io_ibus_addr = fetch_io_ibus_addr; // @[SCore.scala 333:11]
-  assign io_dbus_valid = lsu_io_dbus_valid; // @[SCore.scala 337:11]
-  assign io_dbus_write = lsu_io_dbus_write; // @[SCore.scala 337:11]
-  assign io_dbus_addr = lsu_io_dbus_addr; // @[SCore.scala 337:11]
-  assign io_dbus_adrx = lsu_io_dbus_adrx; // @[SCore.scala 337:11]
-  assign io_dbus_size = lsu_io_dbus_size; // @[SCore.scala 337:11]
-  assign io_dbus_wdata = lsu_io_dbus_wdata; // @[SCore.scala 337:11]
-  assign io_dbus_wmask = lsu_io_dbus_wmask; // @[SCore.scala 337:11]
-  assign io_ubus_valid = lsu_io_ubus_valid; // @[SCore.scala 338:11]
-  assign io_ubus_write = lsu_io_ubus_write; // @[SCore.scala 338:11]
-  assign io_ubus_addr = lsu_io_ubus_addr; // @[SCore.scala 338:11]
-  assign io_ubus_wdata = lsu_io_ubus_wdata; // @[SCore.scala 338:11]
-  assign io_ubus_wmask = lsu_io_ubus_wmask; // @[SCore.scala 338:11]
-  assign io_vldst = lsu_io_vldst; // @[SCore.scala 340:12]
-  assign io_vcore_vinst_0_valid = decode_0_io_vinst_valid; // @[SCore.scala 320:23]
-  assign io_vcore_vinst_0_addr = decode_0_io_vinst_addr; // @[SCore.scala 320:23]
-  assign io_vcore_vinst_0_inst = decode_0_io_vinst_inst; // @[SCore.scala 320:23]
-  assign io_vcore_vinst_0_op = decode_0_io_vinst_op; // @[SCore.scala 320:23]
-  assign io_vcore_vinst_1_valid = decode_1_io_vinst_valid; // @[SCore.scala 320:23]
-  assign io_vcore_vinst_1_addr = decode_1_io_vinst_addr; // @[SCore.scala 320:23]
-  assign io_vcore_vinst_1_inst = decode_1_io_vinst_inst; // @[SCore.scala 320:23]
-  assign io_vcore_vinst_1_op = decode_1_io_vinst_op; // @[SCore.scala 320:23]
-  assign io_vcore_vinst_2_valid = decode_2_io_vinst_valid; // @[SCore.scala 320:23]
-  assign io_vcore_vinst_2_addr = decode_2_io_vinst_addr; // @[SCore.scala 320:23]
-  assign io_vcore_vinst_2_inst = decode_2_io_vinst_inst; // @[SCore.scala 320:23]
-  assign io_vcore_vinst_2_op = decode_2_io_vinst_op; // @[SCore.scala 320:23]
-  assign io_vcore_vinst_3_valid = decode_3_io_vinst_valid; // @[SCore.scala 320:23]
-  assign io_vcore_vinst_3_addr = decode_3_io_vinst_addr; // @[SCore.scala 320:23]
-  assign io_vcore_vinst_3_inst = decode_3_io_vinst_inst; // @[SCore.scala 320:23]
-  assign io_vcore_vinst_3_op = decode_3_io_vinst_op; // @[SCore.scala 320:23]
-  assign io_vcore_rs_0_data = regfile_io_readData_0_data; // @[SCore.scala 324:20]
-  assign io_vcore_rs_1_data = regfile_io_readData_1_data; // @[SCore.scala 324:20]
-  assign io_vcore_rs_2_data = regfile_io_readData_2_data; // @[SCore.scala 324:20]
-  assign io_vcore_rs_3_data = regfile_io_readData_3_data; // @[SCore.scala 324:20]
-  assign io_vcore_rs_4_data = regfile_io_readData_4_data; // @[SCore.scala 324:20]
-  assign io_vcore_rs_5_data = regfile_io_readData_5_data; // @[SCore.scala 324:20]
-  assign io_vcore_rs_6_data = regfile_io_readData_6_data; // @[SCore.scala 324:20]
-  assign io_vcore_rs_7_data = regfile_io_readData_7_data; // @[SCore.scala 324:20]
-  assign io_vcore_fs_0_data = fpu_io_fs_0_data; // @[SCore.scala 328:20]
-  assign io_vcore_fs_1_data = fpu_io_fs_1_data; // @[SCore.scala 328:20]
-  assign io_vcore_fs_2_data = fpu_io_fs_2_data; // @[SCore.scala 328:20]
-  assign io_vcore_fs_3_data = fpu_io_fs_3_data; // @[SCore.scala 328:20]
-  assign io_iflush_valid = iflush; // @[SCore.scala 181:19]
-  assign io_dflush_valid = lsu_io_flush_valid; // @[SCore.scala 60:19]
-  assign io_dflush_all = lsu_io_flush_all; // @[SCore.scala 61:19]
-  assign io_slog_valid = slogValid; // @[SCore.scala 353:17]
-  assign io_slog_addr = {{3'd0}, _io_slog_addr_T}; // @[SCore.scala 354:17]
+  assign io_halted = csr_io_halted; // @[SCore.scala 179:13]
+  assign io_fault = csr_io_fault; // @[SCore.scala 180:13]
+  assign io_ibus_valid = fetch_io_ibus_valid; // @[SCore.scala 291:11]
+  assign io_ibus_addr = fetch_io_ibus_addr; // @[SCore.scala 291:11]
+  assign io_dbus_valid = lsu_io_dbus_valid; // @[SCore.scala 295:11]
+  assign io_dbus_write = lsu_io_dbus_write; // @[SCore.scala 295:11]
+  assign io_dbus_addr = lsu_io_dbus_addr; // @[SCore.scala 295:11]
+  assign io_dbus_adrx = lsu_io_dbus_adrx; // @[SCore.scala 295:11]
+  assign io_dbus_size = lsu_io_dbus_size; // @[SCore.scala 295:11]
+  assign io_dbus_wdata = lsu_io_dbus_wdata; // @[SCore.scala 295:11]
+  assign io_dbus_wmask = lsu_io_dbus_wmask; // @[SCore.scala 295:11]
+  assign io_ubus_valid = lsu_io_ubus_valid; // @[SCore.scala 296:11]
+  assign io_ubus_write = lsu_io_ubus_write; // @[SCore.scala 296:11]
+  assign io_ubus_addr = lsu_io_ubus_addr; // @[SCore.scala 296:11]
+  assign io_ubus_wdata = lsu_io_ubus_wdata; // @[SCore.scala 296:11]
+  assign io_ubus_wmask = lsu_io_ubus_wmask; // @[SCore.scala 296:11]
+  assign io_vldst = lsu_io_vldst; // @[SCore.scala 298:12]
+  assign io_vcore_vinst_0_valid = decode_0_io_vinst_valid; // @[SCore.scala 282:23]
+  assign io_vcore_vinst_0_addr = decode_0_io_vinst_addr; // @[SCore.scala 282:23]
+  assign io_vcore_vinst_0_inst = decode_0_io_vinst_inst; // @[SCore.scala 282:23]
+  assign io_vcore_vinst_0_op = decode_0_io_vinst_op; // @[SCore.scala 282:23]
+  assign io_vcore_vinst_1_valid = decode_1_io_vinst_valid; // @[SCore.scala 282:23]
+  assign io_vcore_vinst_1_addr = decode_1_io_vinst_addr; // @[SCore.scala 282:23]
+  assign io_vcore_vinst_1_inst = decode_1_io_vinst_inst; // @[SCore.scala 282:23]
+  assign io_vcore_vinst_1_op = decode_1_io_vinst_op; // @[SCore.scala 282:23]
+  assign io_vcore_vinst_2_valid = decode_2_io_vinst_valid; // @[SCore.scala 282:23]
+  assign io_vcore_vinst_2_addr = decode_2_io_vinst_addr; // @[SCore.scala 282:23]
+  assign io_vcore_vinst_2_inst = decode_2_io_vinst_inst; // @[SCore.scala 282:23]
+  assign io_vcore_vinst_2_op = decode_2_io_vinst_op; // @[SCore.scala 282:23]
+  assign io_vcore_vinst_3_valid = decode_3_io_vinst_valid; // @[SCore.scala 282:23]
+  assign io_vcore_vinst_3_addr = decode_3_io_vinst_addr; // @[SCore.scala 282:23]
+  assign io_vcore_vinst_3_inst = decode_3_io_vinst_inst; // @[SCore.scala 282:23]
+  assign io_vcore_vinst_3_op = decode_3_io_vinst_op; // @[SCore.scala 282:23]
+  assign io_vcore_rs_0_data = regfile_io_readData_0_data; // @[SCore.scala 286:20]
+  assign io_vcore_rs_1_data = regfile_io_readData_1_data; // @[SCore.scala 286:20]
+  assign io_vcore_rs_2_data = regfile_io_readData_2_data; // @[SCore.scala 286:20]
+  assign io_vcore_rs_3_data = regfile_io_readData_3_data; // @[SCore.scala 286:20]
+  assign io_vcore_rs_4_data = regfile_io_readData_4_data; // @[SCore.scala 286:20]
+  assign io_vcore_rs_5_data = regfile_io_readData_5_data; // @[SCore.scala 286:20]
+  assign io_vcore_rs_6_data = regfile_io_readData_6_data; // @[SCore.scala 286:20]
+  assign io_vcore_rs_7_data = regfile_io_readData_7_data; // @[SCore.scala 286:20]
+  assign io_iflush_valid = iflush; // @[SCore.scala 166:19]
+  assign io_dflush_valid = lsu_io_flush_valid; // @[SCore.scala 59:19]
+  assign io_dflush_all = lsu_io_flush_all; // @[SCore.scala 60:19]
+  assign io_slog_valid = slogValid; // @[SCore.scala 311:17]
+  assign io_slog_addr = {{3'd0}, _io_slog_addr_T}; // @[SCore.scala 312:17]
   assign io_slog_data = slogValid ? regfile_io_readData_0_data : 32'h0; // @[Library.scala 8:8]
   assign regfile_clock = clock;
   assign regfile_reset = reset;
-  assign regfile_io_readAddr_0_valid = decode_0_io_rs1Read_valid; // @[SCore.scala 240:36]
-  assign regfile_io_readAddr_0_addr = decode_0_io_rs1Read_addr; // @[SCore.scala 240:36]
-  assign regfile_io_readAddr_1_valid = decode_0_io_rs2Read_valid; // @[SCore.scala 241:36]
-  assign regfile_io_readAddr_1_addr = decode_0_io_rs2Read_addr; // @[SCore.scala 241:36]
-  assign regfile_io_readAddr_2_valid = decode_1_io_rs1Read_valid; // @[SCore.scala 240:36]
-  assign regfile_io_readAddr_2_addr = decode_1_io_rs1Read_addr; // @[SCore.scala 240:36]
-  assign regfile_io_readAddr_3_valid = decode_1_io_rs2Read_valid; // @[SCore.scala 241:36]
-  assign regfile_io_readAddr_3_addr = decode_1_io_rs2Read_addr; // @[SCore.scala 241:36]
-  assign regfile_io_readAddr_4_valid = decode_2_io_rs1Read_valid; // @[SCore.scala 240:36]
-  assign regfile_io_readAddr_4_addr = decode_2_io_rs1Read_addr; // @[SCore.scala 240:36]
-  assign regfile_io_readAddr_5_valid = decode_2_io_rs2Read_valid; // @[SCore.scala 241:36]
-  assign regfile_io_readAddr_5_addr = decode_2_io_rs2Read_addr; // @[SCore.scala 241:36]
-  assign regfile_io_readAddr_6_valid = decode_3_io_rs1Read_valid; // @[SCore.scala 240:36]
-  assign regfile_io_readAddr_6_addr = decode_3_io_rs1Read_addr; // @[SCore.scala 240:36]
-  assign regfile_io_readAddr_7_valid = decode_3_io_rs2Read_valid; // @[SCore.scala 241:36]
-  assign regfile_io_readAddr_7_addr = decode_3_io_rs2Read_addr; // @[SCore.scala 241:36]
-  assign regfile_io_readSet_0_valid = decode_0_io_rs1Set_valid; // @[SCore.scala 242:35]
-  assign regfile_io_readSet_0_value = decode_0_io_rs1Set_value; // @[SCore.scala 242:35]
-  assign regfile_io_readSet_1_valid = decode_0_io_rs2Set_valid; // @[SCore.scala 243:35]
-  assign regfile_io_readSet_1_value = decode_0_io_rs2Set_value; // @[SCore.scala 243:35]
-  assign regfile_io_readSet_2_valid = decode_1_io_rs1Set_valid; // @[SCore.scala 242:35]
-  assign regfile_io_readSet_2_value = decode_1_io_rs1Set_value; // @[SCore.scala 242:35]
-  assign regfile_io_readSet_3_valid = decode_1_io_rs2Set_valid; // @[SCore.scala 243:35]
-  assign regfile_io_readSet_3_value = decode_1_io_rs2Set_value; // @[SCore.scala 243:35]
-  assign regfile_io_readSet_4_valid = decode_2_io_rs1Set_valid; // @[SCore.scala 242:35]
-  assign regfile_io_readSet_4_value = decode_2_io_rs1Set_value; // @[SCore.scala 242:35]
-  assign regfile_io_readSet_5_valid = decode_2_io_rs2Set_valid; // @[SCore.scala 243:35]
-  assign regfile_io_readSet_5_value = decode_2_io_rs2Set_value; // @[SCore.scala 243:35]
-  assign regfile_io_readSet_6_valid = decode_3_io_rs1Set_valid; // @[SCore.scala 242:35]
-  assign regfile_io_readSet_6_value = decode_3_io_rs1Set_value; // @[SCore.scala 242:35]
-  assign regfile_io_readSet_7_valid = decode_3_io_rs2Set_valid; // @[SCore.scala 243:35]
-  assign regfile_io_readSet_7_value = decode_3_io_rs2Set_value; // @[SCore.scala 243:35]
-  assign regfile_io_writeAddr_0_valid = decode_0_io_rdMark_valid; // @[SCore.scala 244:29]
-  assign regfile_io_writeAddr_0_addr = decode_0_io_rdMark_addr; // @[SCore.scala 244:29]
-  assign regfile_io_writeAddr_1_valid = decode_1_io_rdMark_valid; // @[SCore.scala 244:29]
-  assign regfile_io_writeAddr_1_addr = decode_1_io_rdMark_addr; // @[SCore.scala 244:29]
-  assign regfile_io_writeAddr_2_valid = decode_2_io_rdMark_valid; // @[SCore.scala 244:29]
-  assign regfile_io_writeAddr_2_addr = decode_2_io_rdMark_addr; // @[SCore.scala 244:29]
-  assign regfile_io_writeAddr_3_valid = decode_3_io_rdMark_valid; // @[SCore.scala 244:29]
-  assign regfile_io_writeAddr_3_addr = decode_3_io_rdMark_addr; // @[SCore.scala 244:29]
-  assign regfile_io_busAddr_0_bypass = decode_0_io_busRead_bypass; // @[SCore.scala 245:27]
-  assign regfile_io_busAddr_0_immen = decode_0_io_busRead_immen; // @[SCore.scala 245:27]
-  assign regfile_io_busAddr_0_immed = decode_0_io_busRead_immed; // @[SCore.scala 245:27]
-  assign regfile_io_busAddr_1_bypass = decode_1_io_busRead_bypass; // @[SCore.scala 245:27]
-  assign regfile_io_busAddr_1_immed = decode_1_io_busRead_immed; // @[SCore.scala 245:27]
-  assign regfile_io_busAddr_2_bypass = decode_2_io_busRead_bypass; // @[SCore.scala 245:27]
-  assign regfile_io_busAddr_2_immed = decode_2_io_busRead_immed; // @[SCore.scala 245:27]
-  assign regfile_io_busAddr_3_bypass = decode_3_io_busRead_bypass; // @[SCore.scala 245:27]
-  assign regfile_io_busAddr_3_immed = decode_3_io_busRead_immed; // @[SCore.scala 245:27]
-  assign regfile_io_writeData_0_valid = _regfile_io_writeData_0_valid_T_2 | bru_0_io_rd_valid | io_vcore_rd_0_valid; // @[SCore.scala 260:79]
-  assign regfile_io_writeData_0_addr = _regfile_io_writeData_0_addr_T_8 | _regfile_io_writeData_0_addr_T_9; // @[SCore.scala 268:54]
-  assign regfile_io_writeData_0_data = _regfile_io_writeData_0_data_T_8 | _regfile_io_writeData_0_data_T_9; // @[SCore.scala 276:54]
-  assign regfile_io_writeData_1_valid = _regfile_io_writeData_1_valid_T_2 | bru_1_io_rd_valid | io_vcore_rd_1_valid; // @[SCore.scala 260:79]
-  assign regfile_io_writeData_1_addr = _regfile_io_writeData_1_addr_T_8 | _regfile_io_writeData_1_addr_T_9; // @[SCore.scala 268:54]
-  assign regfile_io_writeData_1_data = _regfile_io_writeData_1_data_T_8 | _regfile_io_writeData_1_data_T_9; // @[SCore.scala 276:54]
-  assign regfile_io_writeData_2_valid = _regfile_io_writeData_2_valid_T_2 | bru_2_io_rd_valid | io_vcore_rd_2_valid; // @[SCore.scala 260:79]
-  assign regfile_io_writeData_2_addr = _regfile_io_writeData_2_addr_T_8 | _regfile_io_writeData_2_addr_T_9; // @[SCore.scala 268:54]
-  assign regfile_io_writeData_2_data = _regfile_io_writeData_2_data_T_8 | _regfile_io_writeData_2_data_T_9; // @[SCore.scala 276:54]
-  assign regfile_io_writeData_3_valid = _regfile_io_writeData_3_valid_T_2 | bru_3_io_rd_valid | io_vcore_rd_3_valid; // @[SCore.scala 260:79]
-  assign regfile_io_writeData_3_addr = _regfile_io_writeData_3_addr_T_8 | _regfile_io_writeData_3_addr_T_9; // @[SCore.scala 268:54]
-  assign regfile_io_writeData_3_data = _regfile_io_writeData_3_data_T_8 | _regfile_io_writeData_3_data_T_9; // @[SCore.scala 276:54]
-  assign regfile_io_writeData_4_valid = mlu_io_rd_valid | dvu_io_rd_valid; // @[SCore.scala 284:52]
-  assign regfile_io_writeData_4_addr = mlu_io_rd_valid ? mlu_io_rd_addr : dvu_io_rd_addr; // @[SCore.scala 285:38]
-  assign regfile_io_writeData_4_data = mlu_io_rd_valid ? mlu_io_rd_data : dvu_io_rd_data; // @[SCore.scala 286:38]
-  assign regfile_io_writeData_5_valid = lsu_io_rd_valid; // @[SCore.scala 289:33]
-  assign regfile_io_writeData_5_addr = lsu_io_rd_addr; // @[SCore.scala 290:33]
-  assign regfile_io_writeData_5_data = lsu_io_rd_data; // @[SCore.scala 291:33]
-  assign regfile_io_writeMask_0_valid = 1'h0; // @[SCore.scala 293:33]
-  assign regfile_io_writeMask_1_valid = regfile_io_writeMask_0_valid | bru_0_io_taken_valid; // @[SCore.scala 294:66]
-  assign regfile_io_writeMask_2_valid = regfile_io_writeMask_1_valid | bru_1_io_taken_valid; // @[SCore.scala 296:66]
-  assign regfile_io_writeMask_3_valid = regfile_io_writeMask_2_valid | bru_2_io_taken_valid; // @[SCore.scala 298:66]
+  assign regfile_io_readAddr_0_valid = decode_0_io_rs1Read_valid; // @[SCore.scala 228:36]
+  assign regfile_io_readAddr_0_addr = decode_0_io_rs1Read_addr; // @[SCore.scala 228:36]
+  assign regfile_io_readAddr_1_valid = decode_0_io_rs2Read_valid; // @[SCore.scala 229:36]
+  assign regfile_io_readAddr_1_addr = decode_0_io_rs2Read_addr; // @[SCore.scala 229:36]
+  assign regfile_io_readAddr_2_valid = decode_1_io_rs1Read_valid; // @[SCore.scala 228:36]
+  assign regfile_io_readAddr_2_addr = decode_1_io_rs1Read_addr; // @[SCore.scala 228:36]
+  assign regfile_io_readAddr_3_valid = decode_1_io_rs2Read_valid; // @[SCore.scala 229:36]
+  assign regfile_io_readAddr_3_addr = decode_1_io_rs2Read_addr; // @[SCore.scala 229:36]
+  assign regfile_io_readAddr_4_valid = decode_2_io_rs1Read_valid; // @[SCore.scala 228:36]
+  assign regfile_io_readAddr_4_addr = decode_2_io_rs1Read_addr; // @[SCore.scala 228:36]
+  assign regfile_io_readAddr_5_valid = decode_2_io_rs2Read_valid; // @[SCore.scala 229:36]
+  assign regfile_io_readAddr_5_addr = decode_2_io_rs2Read_addr; // @[SCore.scala 229:36]
+  assign regfile_io_readAddr_6_valid = decode_3_io_rs1Read_valid; // @[SCore.scala 228:36]
+  assign regfile_io_readAddr_6_addr = decode_3_io_rs1Read_addr; // @[SCore.scala 228:36]
+  assign regfile_io_readAddr_7_valid = decode_3_io_rs2Read_valid; // @[SCore.scala 229:36]
+  assign regfile_io_readAddr_7_addr = decode_3_io_rs2Read_addr; // @[SCore.scala 229:36]
+  assign regfile_io_readSet_0_valid = decode_0_io_rs1Set_valid; // @[SCore.scala 230:35]
+  assign regfile_io_readSet_0_value = decode_0_io_rs1Set_value; // @[SCore.scala 230:35]
+  assign regfile_io_readSet_1_valid = decode_0_io_rs2Set_valid; // @[SCore.scala 231:35]
+  assign regfile_io_readSet_1_value = decode_0_io_rs2Set_value; // @[SCore.scala 231:35]
+  assign regfile_io_readSet_2_valid = decode_1_io_rs1Set_valid; // @[SCore.scala 230:35]
+  assign regfile_io_readSet_2_value = decode_1_io_rs1Set_value; // @[SCore.scala 230:35]
+  assign regfile_io_readSet_3_valid = decode_1_io_rs2Set_valid; // @[SCore.scala 231:35]
+  assign regfile_io_readSet_3_value = decode_1_io_rs2Set_value; // @[SCore.scala 231:35]
+  assign regfile_io_readSet_4_valid = decode_2_io_rs1Set_valid; // @[SCore.scala 230:35]
+  assign regfile_io_readSet_4_value = decode_2_io_rs1Set_value; // @[SCore.scala 230:35]
+  assign regfile_io_readSet_5_valid = decode_2_io_rs2Set_valid; // @[SCore.scala 231:35]
+  assign regfile_io_readSet_5_value = decode_2_io_rs2Set_value; // @[SCore.scala 231:35]
+  assign regfile_io_readSet_6_valid = decode_3_io_rs1Set_valid; // @[SCore.scala 230:35]
+  assign regfile_io_readSet_6_value = decode_3_io_rs1Set_value; // @[SCore.scala 230:35]
+  assign regfile_io_readSet_7_valid = decode_3_io_rs2Set_valid; // @[SCore.scala 231:35]
+  assign regfile_io_readSet_7_value = decode_3_io_rs2Set_value; // @[SCore.scala 231:35]
+  assign regfile_io_writeAddr_0_valid = decode_0_io_rdMark_valid; // @[SCore.scala 232:29]
+  assign regfile_io_writeAddr_0_addr = decode_0_io_rdMark_addr; // @[SCore.scala 232:29]
+  assign regfile_io_writeAddr_1_valid = decode_1_io_rdMark_valid; // @[SCore.scala 232:29]
+  assign regfile_io_writeAddr_1_addr = decode_1_io_rdMark_addr; // @[SCore.scala 232:29]
+  assign regfile_io_writeAddr_2_valid = decode_2_io_rdMark_valid; // @[SCore.scala 232:29]
+  assign regfile_io_writeAddr_2_addr = decode_2_io_rdMark_addr; // @[SCore.scala 232:29]
+  assign regfile_io_writeAddr_3_valid = decode_3_io_rdMark_valid; // @[SCore.scala 232:29]
+  assign regfile_io_writeAddr_3_addr = decode_3_io_rdMark_addr; // @[SCore.scala 232:29]
+  assign regfile_io_busAddr_0_bypass = decode_0_io_busRead_bypass; // @[SCore.scala 233:27]
+  assign regfile_io_busAddr_0_immen = decode_0_io_busRead_immen; // @[SCore.scala 233:27]
+  assign regfile_io_busAddr_0_immed = decode_0_io_busRead_immed; // @[SCore.scala 233:27]
+  assign regfile_io_busAddr_1_bypass = decode_1_io_busRead_bypass; // @[SCore.scala 233:27]
+  assign regfile_io_busAddr_1_immed = decode_1_io_busRead_immed; // @[SCore.scala 233:27]
+  assign regfile_io_busAddr_2_bypass = decode_2_io_busRead_bypass; // @[SCore.scala 233:27]
+  assign regfile_io_busAddr_2_immed = decode_2_io_busRead_immed; // @[SCore.scala 233:27]
+  assign regfile_io_busAddr_3_bypass = decode_3_io_busRead_bypass; // @[SCore.scala 233:27]
+  assign regfile_io_busAddr_3_immed = decode_3_io_busRead_immed; // @[SCore.scala 233:27]
+  assign regfile_io_writeData_0_valid = _regfile_io_writeData_0_valid_T | bru_0_io_rd_valid | io_vcore_rd_0_valid; // @[SCore.scala 241:79]
+  assign regfile_io_writeData_0_addr = _regfile_io_writeData_0_addr_T_4 | _regfile_io_writeData_0_addr_T_5; // @[SCore.scala 247:54]
+  assign regfile_io_writeData_0_data = _regfile_io_writeData_0_data_T_4 | _regfile_io_writeData_0_data_T_5; // @[SCore.scala 253:54]
+  assign regfile_io_writeData_1_valid = _regfile_io_writeData_1_valid_T | bru_1_io_rd_valid | io_vcore_rd_1_valid; // @[SCore.scala 241:79]
+  assign regfile_io_writeData_1_addr = _regfile_io_writeData_1_addr_T_4 | _regfile_io_writeData_1_addr_T_5; // @[SCore.scala 247:54]
+  assign regfile_io_writeData_1_data = _regfile_io_writeData_1_data_T_4 | _regfile_io_writeData_1_data_T_5; // @[SCore.scala 253:54]
+  assign regfile_io_writeData_2_valid = _regfile_io_writeData_2_valid_T | bru_2_io_rd_valid | io_vcore_rd_2_valid; // @[SCore.scala 241:79]
+  assign regfile_io_writeData_2_addr = _regfile_io_writeData_2_addr_T_4 | _regfile_io_writeData_2_addr_T_5; // @[SCore.scala 247:54]
+  assign regfile_io_writeData_2_data = _regfile_io_writeData_2_data_T_4 | _regfile_io_writeData_2_data_T_5; // @[SCore.scala 253:54]
+  assign regfile_io_writeData_3_valid = _regfile_io_writeData_3_valid_T | bru_3_io_rd_valid | io_vcore_rd_3_valid; // @[SCore.scala 241:79]
+  assign regfile_io_writeData_3_addr = _regfile_io_writeData_3_addr_T_4 | _regfile_io_writeData_3_addr_T_5; // @[SCore.scala 247:54]
+  assign regfile_io_writeData_3_data = _regfile_io_writeData_3_data_T_4 | _regfile_io_writeData_3_data_T_5; // @[SCore.scala 253:54]
+  assign regfile_io_writeData_4_valid = mlu_io_rd_valid | dvu_io_rd_valid; // @[SCore.scala 261:52]
+  assign regfile_io_writeData_4_addr = mlu_io_rd_valid ? mlu_io_rd_addr : dvu_io_rd_addr; // @[SCore.scala 262:38]
+  assign regfile_io_writeData_4_data = mlu_io_rd_valid ? mlu_io_rd_data : dvu_io_rd_data; // @[SCore.scala 263:38]
+  assign regfile_io_writeData_5_valid = lsu_io_rd_valid; // @[SCore.scala 266:33]
+  assign regfile_io_writeData_5_addr = lsu_io_rd_addr; // @[SCore.scala 267:33]
+  assign regfile_io_writeData_5_data = lsu_io_rd_data; // @[SCore.scala 268:33]
+  assign regfile_io_writeMask_0_valid = 1'h0; // @[SCore.scala 270:33]
+  assign regfile_io_writeMask_1_valid = regfile_io_writeMask_0_valid | bru_0_io_taken_valid; // @[SCore.scala 271:66]
+  assign regfile_io_writeMask_2_valid = regfile_io_writeMask_1_valid | bru_1_io_taken_valid; // @[SCore.scala 273:66]
+  assign regfile_io_writeMask_3_valid = regfile_io_writeMask_2_valid | bru_2_io_taken_valid; // @[SCore.scala 275:66]
+  assign regfile_io_writeMask_4_valid = mluInvalidate; // @[SCore.scala 277:33]
   assign fetch_clock = clock;
   assign fetch_reset = reset;
-  assign fetch_io_csr_value_0 = io_csr_in_value_0; // @[SCore.scala 71:16]
-  assign fetch_io_ibus_ready = io_ibus_ready; // @[SCore.scala 333:11]
-  assign fetch_io_ibus_rdata = io_ibus_rdata; // @[SCore.scala 333:11]
-  assign fetch_io_inst_lanes_0_ready = decode_0_io_inst_ready; // @[SCore.scala 91:61]
-  assign fetch_io_inst_lanes_1_ready = decode_1_io_inst_ready & decode_0_io_inst_ready; // @[SCore.scala 91:61]
-  assign fetch_io_inst_lanes_2_ready = decode_2_io_inst_ready & mask_2; // @[SCore.scala 91:61]
-  assign fetch_io_inst_lanes_3_ready = decode_3_io_inst_ready & mask_3; // @[SCore.scala 91:61]
-  assign fetch_io_branch_0_valid = bru_0_io_taken_valid; // @[SCore.scala 74:24]
-  assign fetch_io_branch_0_value = bru_0_io_taken_value; // @[SCore.scala 74:24]
-  assign fetch_io_branch_1_valid = bru_1_io_taken_valid; // @[SCore.scala 74:24]
-  assign fetch_io_branch_1_value = bru_1_io_taken_value; // @[SCore.scala 74:24]
-  assign fetch_io_branch_2_valid = bru_2_io_taken_valid; // @[SCore.scala 74:24]
-  assign fetch_io_branch_2_value = bru_2_io_taken_value; // @[SCore.scala 74:24]
-  assign fetch_io_branch_3_valid = bru_3_io_taken_valid; // @[SCore.scala 74:24]
-  assign fetch_io_branch_3_value = bru_3_io_taken_value; // @[SCore.scala 74:24]
-  assign fetch_io_linkPort_valid = regfile_io_linkPort_valid; // @[SCore.scala 77:21]
-  assign fetch_io_linkPort_value = regfile_io_linkPort_value; // @[SCore.scala 77:21]
-  assign fetch_io_iflush_valid = iflush; // @[SCore.scala 79:25]
+  assign fetch_io_csr_value_0 = io_csr_in_value_0; // @[SCore.scala 70:16]
+  assign fetch_io_ibus_ready = io_ibus_ready; // @[SCore.scala 291:11]
+  assign fetch_io_ibus_rdata = io_ibus_rdata; // @[SCore.scala 291:11]
+  assign fetch_io_inst_lanes_0_ready = decode_0_io_inst_ready; // @[SCore.scala 90:61]
+  assign fetch_io_inst_lanes_1_ready = decode_1_io_inst_ready & decode_0_io_inst_ready; // @[SCore.scala 90:61]
+  assign fetch_io_inst_lanes_2_ready = decode_2_io_inst_ready & mask_2; // @[SCore.scala 90:61]
+  assign fetch_io_inst_lanes_3_ready = decode_3_io_inst_ready & mask_3; // @[SCore.scala 90:61]
+  assign fetch_io_branch_0_valid = bru_0_io_taken_valid; // @[SCore.scala 73:24]
+  assign fetch_io_branch_0_value = bru_0_io_taken_value; // @[SCore.scala 73:24]
+  assign fetch_io_branch_1_valid = bru_1_io_taken_valid; // @[SCore.scala 73:24]
+  assign fetch_io_branch_1_value = bru_1_io_taken_value; // @[SCore.scala 73:24]
+  assign fetch_io_branch_2_valid = bru_2_io_taken_valid; // @[SCore.scala 73:24]
+  assign fetch_io_branch_2_value = bru_2_io_taken_value; // @[SCore.scala 73:24]
+  assign fetch_io_branch_3_valid = bru_3_io_taken_valid; // @[SCore.scala 73:24]
+  assign fetch_io_branch_3_value = bru_3_io_taken_value; // @[SCore.scala 73:24]
+  assign fetch_io_linkPort_valid = regfile_io_linkPort_valid; // @[SCore.scala 76:21]
+  assign fetch_io_linkPort_value = regfile_io_linkPort_value; // @[SCore.scala 76:21]
+  assign fetch_io_iflush_valid = iflush; // @[SCore.scala 78:25]
   assign decode_0_clock = clock;
   assign decode_0_reset = reset;
-  assign decode_0_io_halted = csr_io_halted; // @[SCore.scala 97:25]
-  assign decode_0_io_inst_valid = fetch_io_inst_lanes_0_valid; // @[SCore.scala 90:61]
-  assign decode_0_io_inst_addr = fetch_io_inst_lanes_0_addr; // @[SCore.scala 92:28]
-  assign decode_0_io_inst_inst = fetch_io_inst_lanes_0_inst; // @[SCore.scala 93:28]
-  assign decode_0_io_inst_brchFwd = fetch_io_inst_lanes_0_brchFwd; // @[SCore.scala 94:31]
-  assign decode_0_io_scoreboard_regd = regfile_io_scoreboard_regd; // @[SCore.scala 139:32]
-  assign decode_0_io_scoreboard_comb = regfile_io_scoreboard_comb; // @[SCore.scala 138:32]
-  assign decode_0_io_fscoreboard = fpu_io_fscoreboard; // @[SCore.scala 149:28]
-  assign decode_0_io_mactive = io_vcore_mactive; // @[SCore.scala 154:24]
-  assign decode_0_io_lsu_ready = lsu_io_req_0_ready; // @[SCore.scala 207:28]
-  assign decode_0_io_dvu_ready = dvu_io_req_ready; // @[SCore.scala 227:14]
-  assign decode_0_io_fpu_busyFDiv = fpu_io_req_0_busyFDiv; // @[SCore.scala 303:17]
-  assign decode_0_io_fpu_busyFSqrt = fpu_io_req_0_busyFSqrt; // @[SCore.scala 303:17]
-  assign decode_0_io_vinst_ready = io_vcore_vinst_0_ready; // @[SCore.scala 320:23]
-  assign decode_0_io_branchTaken = _branchTaken_T_1 | bru_3_io_taken_valid; // @[SCore.scala 47:43]
-  assign decode_0_io_interlock = bru_0_io_interlock; // @[SCore.scala 119:26]
+  assign decode_0_io_halted = csr_io_halted; // @[SCore.scala 96:25]
+  assign decode_0_io_inst_valid = fetch_io_inst_lanes_0_valid; // @[SCore.scala 89:61]
+  assign decode_0_io_inst_addr = fetch_io_inst_lanes_0_addr; // @[SCore.scala 91:28]
+  assign decode_0_io_inst_inst = fetch_io_inst_lanes_0_inst; // @[SCore.scala 92:28]
+  assign decode_0_io_inst_brchFwd = fetch_io_inst_lanes_0_brchFwd; // @[SCore.scala 93:31]
+  assign decode_0_io_scoreboard_regd = regfile_io_scoreboard_regd; // @[SCore.scala 130:32]
+  assign decode_0_io_scoreboard_comb = regfile_io_scoreboard_comb; // @[SCore.scala 129:32]
+  assign decode_0_io_mactive = io_vcore_mactive; // @[SCore.scala 139:24]
+  assign decode_0_io_lsu_ready = lsu_io_req_0_ready; // @[SCore.scala 191:28]
+  assign decode_0_io_dvu_ready = dvu_io_req_ready; // @[SCore.scala 215:14]
+  assign decode_0_io_vinst_ready = io_vcore_vinst_0_ready; // @[SCore.scala 282:23]
+  assign decode_0_io_branchTaken = _branchTaken_T_1 | bru_3_io_taken_valid; // @[SCore.scala 46:43]
+  assign decode_0_io_interlock = bru_0_io_interlock; // @[SCore.scala 110:26]
   assign decode_1_clock = clock;
   assign decode_1_reset = reset;
-  assign decode_1_io_halted = csr_io_halted; // @[SCore.scala 97:25]
-  assign decode_1_io_inst_valid = fetch_io_inst_lanes_1_valid & _fetch_io_inst_lanes_0_ready_T; // @[SCore.scala 90:61]
-  assign decode_1_io_inst_addr = fetch_io_inst_lanes_1_addr; // @[SCore.scala 92:28]
-  assign decode_1_io_inst_inst = fetch_io_inst_lanes_1_inst; // @[SCore.scala 93:28]
-  assign decode_1_io_inst_brchFwd = fetch_io_inst_lanes_1_brchFwd; // @[SCore.scala 94:31]
-  assign decode_1_io_scoreboard_regd = regfile_io_scoreboard_regd | decode_0_io_scoreboard_spec; // @[SCore.scala 141:62]
-  assign decode_1_io_scoreboard_comb = regfile_io_scoreboard_comb | decode_0_io_scoreboard_spec; // @[SCore.scala 140:62]
-  assign decode_1_io_fscoreboard = fpu_io_fscoreboard | fwriteMask; // @[SCore.scala 150:50]
-  assign decode_1_io_lsu_ready = lsu_io_req_1_ready; // @[SCore.scala 207:28]
-  assign decode_1_io_vinst_ready = io_vcore_vinst_1_ready; // @[SCore.scala 320:23]
-  assign decode_1_io_branchTaken = _branchTaken_T_1 | bru_3_io_taken_valid; // @[SCore.scala 47:43]
-  assign decode_1_io_interlock = decode_0_io_interlock; // @[SCore.scala 120:44]
-  assign decode_1_io_serializeIn_mul = decode_0_io_serializeOut_mul; // @[SCore.scala 126:28]
-  assign decode_1_io_serializeIn_jump = decode_0_io_serializeOut_jump; // @[SCore.scala 126:28]
-  assign decode_1_io_serializeIn_brcond = decode_0_io_serializeOut_brcond; // @[SCore.scala 126:28]
+  assign decode_1_io_halted = csr_io_halted; // @[SCore.scala 96:25]
+  assign decode_1_io_inst_valid = fetch_io_inst_lanes_1_valid & _fetch_io_inst_lanes_0_ready_T; // @[SCore.scala 89:61]
+  assign decode_1_io_inst_addr = fetch_io_inst_lanes_1_addr; // @[SCore.scala 91:28]
+  assign decode_1_io_inst_inst = fetch_io_inst_lanes_1_inst; // @[SCore.scala 92:28]
+  assign decode_1_io_inst_brchFwd = fetch_io_inst_lanes_1_brchFwd; // @[SCore.scala 93:31]
+  assign decode_1_io_scoreboard_regd = regfile_io_scoreboard_regd | decode_0_io_scoreboard_spec; // @[SCore.scala 132:62]
+  assign decode_1_io_scoreboard_comb = regfile_io_scoreboard_comb | decode_0_io_scoreboard_spec; // @[SCore.scala 131:62]
+  assign decode_1_io_lsu_ready = lsu_io_req_1_ready; // @[SCore.scala 191:28]
+  assign decode_1_io_vinst_ready = io_vcore_vinst_1_ready; // @[SCore.scala 282:23]
+  assign decode_1_io_branchTaken = _branchTaken_T_1 | bru_3_io_taken_valid; // @[SCore.scala 46:43]
+  assign decode_1_io_interlock = decode_0_io_interlock; // @[SCore.scala 111:44]
+  assign decode_1_io_serializeIn_mul = decode_0_io_serializeOut_mul; // @[SCore.scala 117:28]
+  assign decode_1_io_serializeIn_jump = decode_0_io_serializeOut_jump; // @[SCore.scala 117:28]
+  assign decode_1_io_serializeIn_brcond = decode_0_io_serializeOut_brcond; // @[SCore.scala 117:28]
   assign decode_2_clock = clock;
   assign decode_2_reset = reset;
-  assign decode_2_io_halted = csr_io_halted; // @[SCore.scala 97:25]
-  assign decode_2_io_inst_valid = fetch_io_inst_lanes_2_valid & mask_2; // @[SCore.scala 90:61]
-  assign decode_2_io_inst_addr = fetch_io_inst_lanes_2_addr; // @[SCore.scala 92:28]
-  assign decode_2_io_inst_inst = fetch_io_inst_lanes_2_inst; // @[SCore.scala 93:28]
-  assign decode_2_io_inst_brchFwd = fetch_io_inst_lanes_2_brchFwd; // @[SCore.scala 94:31]
-  assign decode_2_io_scoreboard_regd = regfile_io_scoreboard_regd | scoreboard_spec2; // @[SCore.scala 143:62]
-  assign decode_2_io_scoreboard_comb = regfile_io_scoreboard_comb | scoreboard_spec2; // @[SCore.scala 142:62]
-  assign decode_2_io_fscoreboard = fpu_io_fscoreboard | fwriteMask; // @[SCore.scala 151:50]
-  assign decode_2_io_lsu_ready = lsu_io_req_2_ready; // @[SCore.scala 207:28]
-  assign decode_2_io_vinst_ready = io_vcore_vinst_2_ready; // @[SCore.scala 320:23]
-  assign decode_2_io_branchTaken = _branchTaken_T_1 | bru_3_io_taken_valid; // @[SCore.scala 47:43]
-  assign decode_2_io_interlock = interlockPipe2 | decode_1_io_interlock; // @[SCore.scala 121:44]
-  assign decode_2_io_serializeIn_mul = decode_1_io_serializeOut_mul; // @[SCore.scala 127:28]
-  assign decode_2_io_serializeIn_jump = decode_1_io_serializeOut_jump; // @[SCore.scala 127:28]
-  assign decode_2_io_serializeIn_brcond = decode_1_io_serializeOut_brcond; // @[SCore.scala 127:28]
+  assign decode_2_io_halted = csr_io_halted; // @[SCore.scala 96:25]
+  assign decode_2_io_inst_valid = fetch_io_inst_lanes_2_valid & mask_2; // @[SCore.scala 89:61]
+  assign decode_2_io_inst_addr = fetch_io_inst_lanes_2_addr; // @[SCore.scala 91:28]
+  assign decode_2_io_inst_inst = fetch_io_inst_lanes_2_inst; // @[SCore.scala 92:28]
+  assign decode_2_io_inst_brchFwd = fetch_io_inst_lanes_2_brchFwd; // @[SCore.scala 93:31]
+  assign decode_2_io_scoreboard_regd = regfile_io_scoreboard_regd | scoreboard_spec2; // @[SCore.scala 134:62]
+  assign decode_2_io_scoreboard_comb = regfile_io_scoreboard_comb | scoreboard_spec2; // @[SCore.scala 133:62]
+  assign decode_2_io_lsu_ready = lsu_io_req_2_ready; // @[SCore.scala 191:28]
+  assign decode_2_io_vinst_ready = io_vcore_vinst_2_ready; // @[SCore.scala 282:23]
+  assign decode_2_io_branchTaken = _branchTaken_T_1 | bru_3_io_taken_valid; // @[SCore.scala 46:43]
+  assign decode_2_io_interlock = decode_1_io_interlock; // @[SCore.scala 112:44]
+  assign decode_2_io_serializeIn_mul = decode_1_io_serializeOut_mul; // @[SCore.scala 118:28]
+  assign decode_2_io_serializeIn_jump = decode_1_io_serializeOut_jump; // @[SCore.scala 118:28]
+  assign decode_2_io_serializeIn_brcond = decode_1_io_serializeOut_brcond; // @[SCore.scala 118:28]
   assign decode_3_clock = clock;
   assign decode_3_reset = reset;
-  assign decode_3_io_halted = csr_io_halted; // @[SCore.scala 97:25]
-  assign decode_3_io_inst_valid = fetch_io_inst_lanes_3_valid & mask_3; // @[SCore.scala 90:61]
-  assign decode_3_io_inst_addr = fetch_io_inst_lanes_3_addr; // @[SCore.scala 92:28]
-  assign decode_3_io_inst_inst = fetch_io_inst_lanes_3_inst; // @[SCore.scala 93:28]
-  assign decode_3_io_inst_brchFwd = fetch_io_inst_lanes_3_brchFwd; // @[SCore.scala 94:31]
-  assign decode_3_io_scoreboard_regd = regfile_io_scoreboard_regd | scoreboard_spec3; // @[SCore.scala 145:62]
-  assign decode_3_io_scoreboard_comb = regfile_io_scoreboard_comb | scoreboard_spec3; // @[SCore.scala 144:62]
-  assign decode_3_io_fscoreboard = fpu_io_fscoreboard | fwriteMask; // @[SCore.scala 152:50]
-  assign decode_3_io_lsu_ready = lsu_io_req_3_ready; // @[SCore.scala 207:28]
-  assign decode_3_io_vinst_ready = io_vcore_vinst_3_ready; // @[SCore.scala 320:23]
-  assign decode_3_io_branchTaken = _branchTaken_T_1 | bru_3_io_taken_valid; // @[SCore.scala 47:43]
-  assign decode_3_io_interlock = interlockPipe3 | decode_2_io_interlock; // @[SCore.scala 122:44]
-  assign decode_3_io_serializeIn_mul = decode_2_io_serializeOut_mul; // @[SCore.scala 128:28]
-  assign decode_3_io_serializeIn_jump = decode_2_io_serializeOut_jump; // @[SCore.scala 128:28]
-  assign decode_3_io_serializeIn_brcond = decode_2_io_serializeOut_brcond; // @[SCore.scala 128:28]
+  assign decode_3_io_halted = csr_io_halted; // @[SCore.scala 96:25]
+  assign decode_3_io_inst_valid = fetch_io_inst_lanes_3_valid & mask_3; // @[SCore.scala 89:61]
+  assign decode_3_io_inst_addr = fetch_io_inst_lanes_3_addr; // @[SCore.scala 91:28]
+  assign decode_3_io_inst_inst = fetch_io_inst_lanes_3_inst; // @[SCore.scala 92:28]
+  assign decode_3_io_inst_brchFwd = fetch_io_inst_lanes_3_brchFwd; // @[SCore.scala 93:31]
+  assign decode_3_io_scoreboard_regd = regfile_io_scoreboard_regd | scoreboard_spec3; // @[SCore.scala 136:62]
+  assign decode_3_io_scoreboard_comb = regfile_io_scoreboard_comb | scoreboard_spec3; // @[SCore.scala 135:62]
+  assign decode_3_io_lsu_ready = lsu_io_req_3_ready; // @[SCore.scala 191:28]
+  assign decode_3_io_vinst_ready = io_vcore_vinst_3_ready; // @[SCore.scala 282:23]
+  assign decode_3_io_branchTaken = _branchTaken_T_1 | bru_3_io_taken_valid; // @[SCore.scala 46:43]
+  assign decode_3_io_interlock = decode_2_io_interlock; // @[SCore.scala 113:44]
+  assign decode_3_io_serializeIn_mul = decode_2_io_serializeOut_mul; // @[SCore.scala 119:28]
+  assign decode_3_io_serializeIn_jump = decode_2_io_serializeOut_jump; // @[SCore.scala 119:28]
+  assign decode_3_io_serializeIn_brcond = decode_2_io_serializeOut_brcond; // @[SCore.scala 119:28]
   assign alu_0_clock = clock;
   assign alu_0_reset = reset;
-  assign alu_0_io_req_valid = decode_0_io_alu_valid; // @[SCore.scala 162:19]
-  assign alu_0_io_req_addr = decode_0_io_alu_addr; // @[SCore.scala 162:19]
-  assign alu_0_io_req_op = decode_0_io_alu_op; // @[SCore.scala 162:19]
-  assign alu_0_io_rs1_valid = regfile_io_readData_0_valid; // @[SCore.scala 163:19]
-  assign alu_0_io_rs1_data = regfile_io_readData_0_data; // @[SCore.scala 163:19]
-  assign alu_0_io_rs2_valid = regfile_io_readData_1_valid; // @[SCore.scala 164:19]
-  assign alu_0_io_rs2_data = regfile_io_readData_1_data; // @[SCore.scala 164:19]
+  assign alu_0_io_req_valid = decode_0_io_alu_valid; // @[SCore.scala 147:19]
+  assign alu_0_io_req_addr = decode_0_io_alu_addr; // @[SCore.scala 147:19]
+  assign alu_0_io_req_op = decode_0_io_alu_op; // @[SCore.scala 147:19]
+  assign alu_0_io_rs1_valid = regfile_io_readData_0_valid; // @[SCore.scala 148:19]
+  assign alu_0_io_rs1_data = regfile_io_readData_0_data; // @[SCore.scala 148:19]
+  assign alu_0_io_rs2_valid = regfile_io_readData_1_valid; // @[SCore.scala 149:19]
+  assign alu_0_io_rs2_data = regfile_io_readData_1_data; // @[SCore.scala 149:19]
   assign alu_1_clock = clock;
   assign alu_1_reset = reset;
-  assign alu_1_io_req_valid = decode_1_io_alu_valid; // @[SCore.scala 162:19]
-  assign alu_1_io_req_addr = decode_1_io_alu_addr; // @[SCore.scala 162:19]
-  assign alu_1_io_req_op = decode_1_io_alu_op; // @[SCore.scala 162:19]
-  assign alu_1_io_rs1_valid = regfile_io_readData_2_valid; // @[SCore.scala 163:19]
-  assign alu_1_io_rs1_data = regfile_io_readData_2_data; // @[SCore.scala 163:19]
-  assign alu_1_io_rs2_valid = regfile_io_readData_3_valid; // @[SCore.scala 164:19]
-  assign alu_1_io_rs2_data = regfile_io_readData_3_data; // @[SCore.scala 164:19]
+  assign alu_1_io_req_valid = decode_1_io_alu_valid; // @[SCore.scala 147:19]
+  assign alu_1_io_req_addr = decode_1_io_alu_addr; // @[SCore.scala 147:19]
+  assign alu_1_io_req_op = decode_1_io_alu_op; // @[SCore.scala 147:19]
+  assign alu_1_io_rs1_valid = regfile_io_readData_2_valid; // @[SCore.scala 148:19]
+  assign alu_1_io_rs1_data = regfile_io_readData_2_data; // @[SCore.scala 148:19]
+  assign alu_1_io_rs2_valid = regfile_io_readData_3_valid; // @[SCore.scala 149:19]
+  assign alu_1_io_rs2_data = regfile_io_readData_3_data; // @[SCore.scala 149:19]
   assign alu_2_clock = clock;
   assign alu_2_reset = reset;
-  assign alu_2_io_req_valid = decode_2_io_alu_valid; // @[SCore.scala 162:19]
-  assign alu_2_io_req_addr = decode_2_io_alu_addr; // @[SCore.scala 162:19]
-  assign alu_2_io_req_op = decode_2_io_alu_op; // @[SCore.scala 162:19]
-  assign alu_2_io_rs1_valid = regfile_io_readData_4_valid; // @[SCore.scala 163:19]
-  assign alu_2_io_rs1_data = regfile_io_readData_4_data; // @[SCore.scala 163:19]
-  assign alu_2_io_rs2_valid = regfile_io_readData_5_valid; // @[SCore.scala 164:19]
-  assign alu_2_io_rs2_data = regfile_io_readData_5_data; // @[SCore.scala 164:19]
+  assign alu_2_io_req_valid = decode_2_io_alu_valid; // @[SCore.scala 147:19]
+  assign alu_2_io_req_addr = decode_2_io_alu_addr; // @[SCore.scala 147:19]
+  assign alu_2_io_req_op = decode_2_io_alu_op; // @[SCore.scala 147:19]
+  assign alu_2_io_rs1_valid = regfile_io_readData_4_valid; // @[SCore.scala 148:19]
+  assign alu_2_io_rs1_data = regfile_io_readData_4_data; // @[SCore.scala 148:19]
+  assign alu_2_io_rs2_valid = regfile_io_readData_5_valid; // @[SCore.scala 149:19]
+  assign alu_2_io_rs2_data = regfile_io_readData_5_data; // @[SCore.scala 149:19]
   assign alu_3_clock = clock;
   assign alu_3_reset = reset;
-  assign alu_3_io_req_valid = decode_3_io_alu_valid; // @[SCore.scala 162:19]
-  assign alu_3_io_req_addr = decode_3_io_alu_addr; // @[SCore.scala 162:19]
-  assign alu_3_io_req_op = decode_3_io_alu_op; // @[SCore.scala 162:19]
-  assign alu_3_io_rs1_valid = regfile_io_readData_6_valid; // @[SCore.scala 163:19]
-  assign alu_3_io_rs1_data = regfile_io_readData_6_data; // @[SCore.scala 163:19]
-  assign alu_3_io_rs2_valid = regfile_io_readData_7_valid; // @[SCore.scala 164:19]
-  assign alu_3_io_rs2_data = regfile_io_readData_7_data; // @[SCore.scala 164:19]
+  assign alu_3_io_req_valid = decode_3_io_alu_valid; // @[SCore.scala 147:19]
+  assign alu_3_io_req_addr = decode_3_io_alu_addr; // @[SCore.scala 147:19]
+  assign alu_3_io_req_op = decode_3_io_alu_op; // @[SCore.scala 147:19]
+  assign alu_3_io_rs1_valid = regfile_io_readData_6_valid; // @[SCore.scala 148:19]
+  assign alu_3_io_rs1_data = regfile_io_readData_6_data; // @[SCore.scala 148:19]
+  assign alu_3_io_rs2_valid = regfile_io_readData_7_valid; // @[SCore.scala 149:19]
+  assign alu_3_io_rs2_data = regfile_io_readData_7_data; // @[SCore.scala 149:19]
   assign bru_0_clock = clock;
   assign bru_0_reset = reset;
-  assign bru_0_io_req_valid = decode_0_io_bru_valid; // @[SCore.scala 170:19]
-  assign bru_0_io_req_fwd = decode_0_io_bru_fwd; // @[SCore.scala 170:19]
-  assign bru_0_io_req_op = decode_0_io_bru_op; // @[SCore.scala 170:19]
-  assign bru_0_io_req_pc = decode_0_io_bru_pc; // @[SCore.scala 170:19]
-  assign bru_0_io_req_target = decode_0_io_bru_target; // @[SCore.scala 170:19]
-  assign bru_0_io_req_link = decode_0_io_bru_link; // @[SCore.scala 170:19]
-  assign bru_0_io_csr_out_mode = csr_io_bru_out_mode; // @[SCore.scala 176:17]
-  assign bru_0_io_csr_out_mepc = csr_io_bru_out_mepc; // @[SCore.scala 176:17]
-  assign bru_0_io_csr_out_mtvec = csr_io_bru_out_mtvec; // @[SCore.scala 176:17]
-  assign bru_0_io_rs1_valid = regfile_io_readData_0_valid; // @[SCore.scala 171:19]
-  assign bru_0_io_rs1_data = regfile_io_readData_0_data; // @[SCore.scala 171:19]
-  assign bru_0_io_rs2_valid = regfile_io_readData_1_valid; // @[SCore.scala 172:19]
-  assign bru_0_io_rs2_data = regfile_io_readData_1_data; // @[SCore.scala 172:19]
-  assign bru_0_io_target_data = regfile_io_target_0_data; // @[SCore.scala 173:22]
+  assign bru_0_io_req_valid = decode_0_io_bru_valid; // @[SCore.scala 155:19]
+  assign bru_0_io_req_fwd = decode_0_io_bru_fwd; // @[SCore.scala 155:19]
+  assign bru_0_io_req_op = decode_0_io_bru_op; // @[SCore.scala 155:19]
+  assign bru_0_io_req_pc = decode_0_io_bru_pc; // @[SCore.scala 155:19]
+  assign bru_0_io_req_target = decode_0_io_bru_target; // @[SCore.scala 155:19]
+  assign bru_0_io_req_link = decode_0_io_bru_link; // @[SCore.scala 155:19]
+  assign bru_0_io_csr_out_mode = csr_io_bru_out_mode; // @[SCore.scala 161:17]
+  assign bru_0_io_csr_out_mepc = csr_io_bru_out_mepc; // @[SCore.scala 161:17]
+  assign bru_0_io_csr_out_mtvec = csr_io_bru_out_mtvec; // @[SCore.scala 161:17]
+  assign bru_0_io_rs1_valid = regfile_io_readData_0_valid; // @[SCore.scala 156:19]
+  assign bru_0_io_rs1_data = regfile_io_readData_0_data; // @[SCore.scala 156:19]
+  assign bru_0_io_rs2_valid = regfile_io_readData_1_valid; // @[SCore.scala 157:19]
+  assign bru_0_io_rs2_data = regfile_io_readData_1_data; // @[SCore.scala 157:19]
+  assign bru_0_io_target_data = regfile_io_target_0_data; // @[SCore.scala 158:22]
   assign bru_1_clock = clock;
   assign bru_1_reset = reset;
-  assign bru_1_io_req_valid = decode_1_io_bru_valid; // @[SCore.scala 170:19]
-  assign bru_1_io_req_fwd = decode_1_io_bru_fwd; // @[SCore.scala 170:19]
-  assign bru_1_io_req_op = decode_1_io_bru_op; // @[SCore.scala 170:19]
-  assign bru_1_io_req_pc = decode_1_io_bru_pc; // @[SCore.scala 170:19]
-  assign bru_1_io_req_target = decode_1_io_bru_target; // @[SCore.scala 170:19]
-  assign bru_1_io_req_link = decode_1_io_bru_link; // @[SCore.scala 170:19]
+  assign bru_1_io_req_valid = decode_1_io_bru_valid; // @[SCore.scala 155:19]
+  assign bru_1_io_req_fwd = decode_1_io_bru_fwd; // @[SCore.scala 155:19]
+  assign bru_1_io_req_op = decode_1_io_bru_op; // @[SCore.scala 155:19]
+  assign bru_1_io_req_pc = decode_1_io_bru_pc; // @[SCore.scala 155:19]
+  assign bru_1_io_req_target = decode_1_io_bru_target; // @[SCore.scala 155:19]
+  assign bru_1_io_req_link = decode_1_io_bru_link; // @[SCore.scala 155:19]
   assign bru_1_io_csr_out_mode = 1'h0; // @[Csr.scala 48:14]
   assign bru_1_io_csr_out_mepc = 32'h0; // @[Csr.scala 49:14]
   assign bru_1_io_csr_out_mtvec = 32'h0; // @[Csr.scala 50:15]
-  assign bru_1_io_rs1_valid = regfile_io_readData_2_valid; // @[SCore.scala 171:19]
-  assign bru_1_io_rs1_data = regfile_io_readData_2_data; // @[SCore.scala 171:19]
-  assign bru_1_io_rs2_valid = regfile_io_readData_3_valid; // @[SCore.scala 172:19]
-  assign bru_1_io_rs2_data = regfile_io_readData_3_data; // @[SCore.scala 172:19]
-  assign bru_1_io_target_data = regfile_io_target_1_data; // @[SCore.scala 173:22]
+  assign bru_1_io_rs1_valid = regfile_io_readData_2_valid; // @[SCore.scala 156:19]
+  assign bru_1_io_rs1_data = regfile_io_readData_2_data; // @[SCore.scala 156:19]
+  assign bru_1_io_rs2_valid = regfile_io_readData_3_valid; // @[SCore.scala 157:19]
+  assign bru_1_io_rs2_data = regfile_io_readData_3_data; // @[SCore.scala 157:19]
+  assign bru_1_io_target_data = regfile_io_target_1_data; // @[SCore.scala 158:22]
   assign bru_2_clock = clock;
   assign bru_2_reset = reset;
-  assign bru_2_io_req_valid = decode_2_io_bru_valid; // @[SCore.scala 170:19]
-  assign bru_2_io_req_fwd = decode_2_io_bru_fwd; // @[SCore.scala 170:19]
-  assign bru_2_io_req_op = decode_2_io_bru_op; // @[SCore.scala 170:19]
-  assign bru_2_io_req_pc = decode_2_io_bru_pc; // @[SCore.scala 170:19]
-  assign bru_2_io_req_target = decode_2_io_bru_target; // @[SCore.scala 170:19]
-  assign bru_2_io_req_link = decode_2_io_bru_link; // @[SCore.scala 170:19]
+  assign bru_2_io_req_valid = decode_2_io_bru_valid; // @[SCore.scala 155:19]
+  assign bru_2_io_req_fwd = decode_2_io_bru_fwd; // @[SCore.scala 155:19]
+  assign bru_2_io_req_op = decode_2_io_bru_op; // @[SCore.scala 155:19]
+  assign bru_2_io_req_pc = decode_2_io_bru_pc; // @[SCore.scala 155:19]
+  assign bru_2_io_req_target = decode_2_io_bru_target; // @[SCore.scala 155:19]
+  assign bru_2_io_req_link = decode_2_io_bru_link; // @[SCore.scala 155:19]
   assign bru_2_io_csr_out_mode = 1'h0; // @[Csr.scala 48:14]
   assign bru_2_io_csr_out_mepc = 32'h0; // @[Csr.scala 49:14]
   assign bru_2_io_csr_out_mtvec = 32'h0; // @[Csr.scala 50:15]
-  assign bru_2_io_rs1_valid = regfile_io_readData_4_valid; // @[SCore.scala 171:19]
-  assign bru_2_io_rs1_data = regfile_io_readData_4_data; // @[SCore.scala 171:19]
-  assign bru_2_io_rs2_valid = regfile_io_readData_5_valid; // @[SCore.scala 172:19]
-  assign bru_2_io_rs2_data = regfile_io_readData_5_data; // @[SCore.scala 172:19]
-  assign bru_2_io_target_data = regfile_io_target_2_data; // @[SCore.scala 173:22]
+  assign bru_2_io_rs1_valid = regfile_io_readData_4_valid; // @[SCore.scala 156:19]
+  assign bru_2_io_rs1_data = regfile_io_readData_4_data; // @[SCore.scala 156:19]
+  assign bru_2_io_rs2_valid = regfile_io_readData_5_valid; // @[SCore.scala 157:19]
+  assign bru_2_io_rs2_data = regfile_io_readData_5_data; // @[SCore.scala 157:19]
+  assign bru_2_io_target_data = regfile_io_target_2_data; // @[SCore.scala 158:22]
   assign bru_3_clock = clock;
   assign bru_3_reset = reset;
-  assign bru_3_io_req_valid = decode_3_io_bru_valid; // @[SCore.scala 170:19]
-  assign bru_3_io_req_fwd = decode_3_io_bru_fwd; // @[SCore.scala 170:19]
-  assign bru_3_io_req_op = decode_3_io_bru_op; // @[SCore.scala 170:19]
-  assign bru_3_io_req_pc = decode_3_io_bru_pc; // @[SCore.scala 170:19]
-  assign bru_3_io_req_target = decode_3_io_bru_target; // @[SCore.scala 170:19]
-  assign bru_3_io_req_link = decode_3_io_bru_link; // @[SCore.scala 170:19]
+  assign bru_3_io_req_valid = decode_3_io_bru_valid; // @[SCore.scala 155:19]
+  assign bru_3_io_req_fwd = decode_3_io_bru_fwd; // @[SCore.scala 155:19]
+  assign bru_3_io_req_op = decode_3_io_bru_op; // @[SCore.scala 155:19]
+  assign bru_3_io_req_pc = decode_3_io_bru_pc; // @[SCore.scala 155:19]
+  assign bru_3_io_req_target = decode_3_io_bru_target; // @[SCore.scala 155:19]
+  assign bru_3_io_req_link = decode_3_io_bru_link; // @[SCore.scala 155:19]
   assign bru_3_io_csr_out_mode = 1'h0; // @[Csr.scala 48:14]
   assign bru_3_io_csr_out_mepc = 32'h0; // @[Csr.scala 49:14]
   assign bru_3_io_csr_out_mtvec = 32'h0; // @[Csr.scala 50:15]
-  assign bru_3_io_rs1_valid = regfile_io_readData_6_valid; // @[SCore.scala 171:19]
-  assign bru_3_io_rs1_data = regfile_io_readData_6_data; // @[SCore.scala 171:19]
-  assign bru_3_io_rs2_valid = regfile_io_readData_7_valid; // @[SCore.scala 172:19]
-  assign bru_3_io_rs2_data = regfile_io_readData_7_data; // @[SCore.scala 172:19]
-  assign bru_3_io_target_data = regfile_io_target_3_data; // @[SCore.scala 173:22]
+  assign bru_3_io_rs1_valid = regfile_io_readData_6_valid; // @[SCore.scala 156:19]
+  assign bru_3_io_rs1_data = regfile_io_readData_6_data; // @[SCore.scala 156:19]
+  assign bru_3_io_rs2_valid = regfile_io_readData_7_valid; // @[SCore.scala 157:19]
+  assign bru_3_io_rs2_data = regfile_io_readData_7_data; // @[SCore.scala 157:19]
+  assign bru_3_io_target_data = regfile_io_target_3_data; // @[SCore.scala 158:22]
   assign csr_clock = clock;
   assign csr_reset = reset;
-  assign csr_io_csr_in_value_0 = io_csr_in_value_0; // @[SCore.scala 185:14]
-  assign csr_io_req_valid = decode_0_io_csr_valid; // @[SCore.scala 187:14]
-  assign csr_io_req_addr = decode_0_io_csr_addr; // @[SCore.scala 187:14]
-  assign csr_io_req_index = decode_0_io_csr_index; // @[SCore.scala 187:14]
-  assign csr_io_req_op = decode_0_io_csr_op; // @[SCore.scala 187:14]
-  assign csr_io_rs1_valid = regfile_io_readData_0_valid; // @[SCore.scala 188:14]
-  assign csr_io_rs1_data = regfile_io_readData_0_data; // @[SCore.scala 188:14]
-  assign csr_io_bru_in_mode_valid = bru_0_io_csr_in_mode_valid; // @[SCore.scala 176:17]
-  assign csr_io_bru_in_mode_bits = bru_0_io_csr_in_mode_bits; // @[SCore.scala 176:17]
-  assign csr_io_bru_in_mcause_valid = bru_0_io_csr_in_mcause_valid; // @[SCore.scala 176:17]
-  assign csr_io_bru_in_mcause_bits = bru_0_io_csr_in_mcause_bits; // @[SCore.scala 176:17]
-  assign csr_io_bru_in_mepc_valid = bru_0_io_csr_in_mepc_valid; // @[SCore.scala 176:17]
-  assign csr_io_bru_in_mepc_bits = bru_0_io_csr_in_mepc_bits; // @[SCore.scala 176:17]
-  assign csr_io_bru_in_mtval_valid = bru_0_io_csr_in_mtval_valid; // @[SCore.scala 176:17]
-  assign csr_io_bru_in_mtval_bits = bru_0_io_csr_in_mtval_bits; // @[SCore.scala 176:17]
-  assign csr_io_bru_in_halt = bru_0_io_csr_in_halt; // @[SCore.scala 176:17]
-  assign csr_io_bru_in_fault = bru_0_io_csr_in_fault; // @[SCore.scala 176:17]
-  assign csr_io_vcore_undef = io_vcore_undef; // @[SCore.scala 190:22]
+  assign csr_io_csr_in_value_0 = io_csr_in_value_0; // @[SCore.scala 170:14]
+  assign csr_io_req_valid = decode_0_io_csr_valid; // @[SCore.scala 172:14]
+  assign csr_io_req_addr = decode_0_io_csr_addr; // @[SCore.scala 172:14]
+  assign csr_io_req_index = decode_0_io_csr_index; // @[SCore.scala 172:14]
+  assign csr_io_req_op = decode_0_io_csr_op; // @[SCore.scala 172:14]
+  assign csr_io_rs1_valid = regfile_io_readData_0_valid; // @[SCore.scala 173:14]
+  assign csr_io_rs1_data = regfile_io_readData_0_data; // @[SCore.scala 173:14]
+  assign csr_io_bru_in_mode_valid = bru_0_io_csr_in_mode_valid; // @[SCore.scala 161:17]
+  assign csr_io_bru_in_mode_bits = bru_0_io_csr_in_mode_bits; // @[SCore.scala 161:17]
+  assign csr_io_bru_in_mcause_valid = bru_0_io_csr_in_mcause_valid; // @[SCore.scala 161:17]
+  assign csr_io_bru_in_mcause_bits = bru_0_io_csr_in_mcause_bits; // @[SCore.scala 161:17]
+  assign csr_io_bru_in_mepc_valid = bru_0_io_csr_in_mepc_valid; // @[SCore.scala 161:17]
+  assign csr_io_bru_in_mepc_bits = bru_0_io_csr_in_mepc_bits; // @[SCore.scala 161:17]
+  assign csr_io_bru_in_mtval_valid = bru_0_io_csr_in_mtval_valid; // @[SCore.scala 161:17]
+  assign csr_io_bru_in_mtval_bits = bru_0_io_csr_in_mtval_bits; // @[SCore.scala 161:17]
+  assign csr_io_bru_in_halt = bru_0_io_csr_in_halt; // @[SCore.scala 161:17]
+  assign csr_io_bru_in_fault = bru_0_io_csr_in_fault; // @[SCore.scala 161:17]
+  assign csr_io_vcore_undef = io_vcore_undef; // @[SCore.scala 175:22]
   assign lsu_clock = clock;
   assign lsu_reset = reset;
-  assign lsu_io_req_0_valid = decode_0_io_lsu_valid; // @[SCore.scala 203:25]
-  assign lsu_io_req_0_addr = decode_0_io_lsu_addr; // @[SCore.scala 205:25]
-  assign lsu_io_req_0_op = decode_0_io_lsu_op; // @[SCore.scala 206:25]
-  assign lsu_io_req_1_valid = decode_1_io_lsu_valid; // @[SCore.scala 203:25]
-  assign lsu_io_req_1_addr = decode_1_io_lsu_addr; // @[SCore.scala 205:25]
-  assign lsu_io_req_1_op = decode_1_io_lsu_op; // @[SCore.scala 206:25]
-  assign lsu_io_req_2_valid = decode_2_io_lsu_valid; // @[SCore.scala 203:25]
-  assign lsu_io_req_2_addr = decode_2_io_lsu_addr; // @[SCore.scala 205:25]
-  assign lsu_io_req_2_op = decode_2_io_lsu_op; // @[SCore.scala 206:25]
-  assign lsu_io_req_3_valid = decode_3_io_lsu_valid; // @[SCore.scala 203:25]
-  assign lsu_io_req_3_addr = decode_3_io_lsu_addr; // @[SCore.scala 205:25]
-  assign lsu_io_req_3_op = decode_3_io_lsu_op; // @[SCore.scala 206:25]
-  assign lsu_io_busPort_addr_0 = regfile_io_busPort_addr_0; // @[SCore.scala 199:18]
-  assign lsu_io_busPort_addr_1 = regfile_io_busPort_addr_1; // @[SCore.scala 199:18]
-  assign lsu_io_busPort_addr_2 = regfile_io_busPort_addr_2; // @[SCore.scala 199:18]
-  assign lsu_io_busPort_addr_3 = regfile_io_busPort_addr_3; // @[SCore.scala 199:18]
-  assign lsu_io_busPort_data_0 = regfile_io_busPort_data_0; // @[SCore.scala 199:18]
-  assign lsu_io_busPort_data_1 = regfile_io_busPort_data_1; // @[SCore.scala 199:18]
-  assign lsu_io_busPort_data_2 = regfile_io_busPort_data_2; // @[SCore.scala 199:18]
-  assign lsu_io_busPort_data_3 = regfile_io_busPort_data_3; // @[SCore.scala 199:18]
-  assign lsu_io_fbusPort_data = fpu_io_fbusPort_data; // @[SCore.scala 200:19]
-  assign lsu_io_dbus_ready = io_dbus_ready; // @[SCore.scala 337:11]
-  assign lsu_io_dbus_rdata = io_dbus_rdata; // @[SCore.scala 337:11]
-  assign lsu_io_flush_ready = io_dflush_ready; // @[SCore.scala 63:22]
-  assign lsu_io_ubus_ready = io_ubus_ready; // @[SCore.scala 338:11]
-  assign lsu_io_ubus_rdata = io_ubus_rdata; // @[SCore.scala 338:11]
+  assign lsu_io_req_0_valid = decode_0_io_lsu_valid; // @[SCore.scala 187:25]
+  assign lsu_io_req_0_addr = decode_0_io_lsu_addr; // @[SCore.scala 189:25]
+  assign lsu_io_req_0_op = decode_0_io_lsu_op; // @[SCore.scala 190:25]
+  assign lsu_io_req_1_valid = decode_1_io_lsu_valid; // @[SCore.scala 187:25]
+  assign lsu_io_req_1_addr = decode_1_io_lsu_addr; // @[SCore.scala 189:25]
+  assign lsu_io_req_1_op = decode_1_io_lsu_op; // @[SCore.scala 190:25]
+  assign lsu_io_req_2_valid = decode_2_io_lsu_valid; // @[SCore.scala 187:25]
+  assign lsu_io_req_2_addr = decode_2_io_lsu_addr; // @[SCore.scala 189:25]
+  assign lsu_io_req_2_op = decode_2_io_lsu_op; // @[SCore.scala 190:25]
+  assign lsu_io_req_3_valid = decode_3_io_lsu_valid; // @[SCore.scala 187:25]
+  assign lsu_io_req_3_addr = decode_3_io_lsu_addr; // @[SCore.scala 189:25]
+  assign lsu_io_req_3_op = decode_3_io_lsu_op; // @[SCore.scala 190:25]
+  assign lsu_io_busPort_addr_0 = regfile_io_busPort_addr_0; // @[SCore.scala 184:18]
+  assign lsu_io_busPort_addr_1 = regfile_io_busPort_addr_1; // @[SCore.scala 184:18]
+  assign lsu_io_busPort_addr_2 = regfile_io_busPort_addr_2; // @[SCore.scala 184:18]
+  assign lsu_io_busPort_addr_3 = regfile_io_busPort_addr_3; // @[SCore.scala 184:18]
+  assign lsu_io_busPort_data_0 = regfile_io_busPort_data_0; // @[SCore.scala 184:18]
+  assign lsu_io_busPort_data_1 = regfile_io_busPort_data_1; // @[SCore.scala 184:18]
+  assign lsu_io_busPort_data_2 = regfile_io_busPort_data_2; // @[SCore.scala 184:18]
+  assign lsu_io_busPort_data_3 = regfile_io_busPort_data_3; // @[SCore.scala 184:18]
+  assign lsu_io_dbus_ready = io_dbus_ready; // @[SCore.scala 295:11]
+  assign lsu_io_dbus_rdata = io_dbus_rdata; // @[SCore.scala 295:11]
+  assign lsu_io_flush_ready = io_dflush_ready; // @[SCore.scala 62:22]
+  assign lsu_io_ubus_ready = io_ubus_ready; // @[SCore.scala 296:11]
+  assign lsu_io_ubus_rdata = io_ubus_rdata; // @[SCore.scala 296:11]
   assign mlu_clock = clock;
   assign mlu_reset = reset;
-  assign mlu_io_req_0_valid = decode_0_io_mlu_valid; // @[SCore.scala 212:17]
-  assign mlu_io_req_0_addr = decode_0_io_mlu_addr; // @[SCore.scala 212:17]
-  assign mlu_io_req_0_op = decode_0_io_mlu_op; // @[SCore.scala 212:17]
-  assign mlu_io_req_1_valid = decode_1_io_mlu_valid; // @[SCore.scala 213:17]
-  assign mlu_io_req_1_addr = decode_1_io_mlu_addr; // @[SCore.scala 213:17]
-  assign mlu_io_req_1_op = decode_1_io_mlu_op; // @[SCore.scala 213:17]
-  assign mlu_io_req_2_valid = decode_2_io_mlu_valid; // @[SCore.scala 214:17]
-  assign mlu_io_req_2_addr = decode_2_io_mlu_addr; // @[SCore.scala 214:17]
-  assign mlu_io_req_2_op = decode_2_io_mlu_op; // @[SCore.scala 214:17]
-  assign mlu_io_req_3_valid = decode_3_io_mlu_valid; // @[SCore.scala 215:17]
-  assign mlu_io_req_3_addr = decode_3_io_mlu_addr; // @[SCore.scala 215:17]
-  assign mlu_io_req_3_op = decode_3_io_mlu_op; // @[SCore.scala 215:17]
-  assign mlu_io_rs1_0_valid = regfile_io_readData_0_valid; // @[SCore.scala 216:17]
-  assign mlu_io_rs1_0_data = regfile_io_readData_0_data; // @[SCore.scala 216:17]
-  assign mlu_io_rs1_1_valid = regfile_io_readData_2_valid; // @[SCore.scala 217:17]
-  assign mlu_io_rs1_1_data = regfile_io_readData_2_data; // @[SCore.scala 217:17]
-  assign mlu_io_rs1_2_valid = regfile_io_readData_4_valid; // @[SCore.scala 218:17]
-  assign mlu_io_rs1_2_data = regfile_io_readData_4_data; // @[SCore.scala 218:17]
-  assign mlu_io_rs1_3_valid = regfile_io_readData_6_valid; // @[SCore.scala 219:17]
-  assign mlu_io_rs1_3_data = regfile_io_readData_6_data; // @[SCore.scala 219:17]
-  assign mlu_io_rs2_0_valid = regfile_io_readData_1_valid; // @[SCore.scala 220:17]
-  assign mlu_io_rs2_0_data = regfile_io_readData_1_data; // @[SCore.scala 220:17]
-  assign mlu_io_rs2_1_valid = regfile_io_readData_3_valid; // @[SCore.scala 221:17]
-  assign mlu_io_rs2_1_data = regfile_io_readData_3_data; // @[SCore.scala 221:17]
-  assign mlu_io_rs2_2_valid = regfile_io_readData_5_valid; // @[SCore.scala 222:17]
-  assign mlu_io_rs2_2_data = regfile_io_readData_5_data; // @[SCore.scala 222:17]
-  assign mlu_io_rs2_3_valid = regfile_io_readData_7_valid; // @[SCore.scala 223:17]
-  assign mlu_io_rs2_3_data = regfile_io_readData_7_data; // @[SCore.scala 223:17]
+  assign mlu_io_req_0_valid = decode_0_io_mlu_valid; // @[SCore.scala 196:17]
+  assign mlu_io_req_0_addr = decode_0_io_mlu_addr; // @[SCore.scala 196:17]
+  assign mlu_io_req_0_op = decode_0_io_mlu_op; // @[SCore.scala 196:17]
+  assign mlu_io_req_1_valid = decode_1_io_mlu_valid; // @[SCore.scala 197:17]
+  assign mlu_io_req_1_addr = decode_1_io_mlu_addr; // @[SCore.scala 197:17]
+  assign mlu_io_req_1_op = decode_1_io_mlu_op; // @[SCore.scala 197:17]
+  assign mlu_io_req_2_valid = decode_2_io_mlu_valid; // @[SCore.scala 198:17]
+  assign mlu_io_req_2_addr = decode_2_io_mlu_addr; // @[SCore.scala 198:17]
+  assign mlu_io_req_2_op = decode_2_io_mlu_op; // @[SCore.scala 198:17]
+  assign mlu_io_req_3_valid = decode_3_io_mlu_valid; // @[SCore.scala 199:17]
+  assign mlu_io_req_3_addr = decode_3_io_mlu_addr; // @[SCore.scala 199:17]
+  assign mlu_io_req_3_op = decode_3_io_mlu_op; // @[SCore.scala 199:17]
+  assign mlu_io_rs1_0_valid = regfile_io_readData_0_valid; // @[SCore.scala 200:17]
+  assign mlu_io_rs1_0_data = regfile_io_readData_0_data; // @[SCore.scala 200:17]
+  assign mlu_io_rs1_1_valid = regfile_io_readData_2_valid; // @[SCore.scala 201:17]
+  assign mlu_io_rs1_1_data = regfile_io_readData_2_data; // @[SCore.scala 201:17]
+  assign mlu_io_rs1_2_valid = regfile_io_readData_4_valid; // @[SCore.scala 202:17]
+  assign mlu_io_rs1_2_data = regfile_io_readData_4_data; // @[SCore.scala 202:17]
+  assign mlu_io_rs1_3_valid = regfile_io_readData_6_valid; // @[SCore.scala 203:17]
+  assign mlu_io_rs1_3_data = regfile_io_readData_6_data; // @[SCore.scala 203:17]
+  assign mlu_io_rs2_0_valid = regfile_io_readData_1_valid; // @[SCore.scala 204:17]
+  assign mlu_io_rs2_0_data = regfile_io_readData_1_data; // @[SCore.scala 204:17]
+  assign mlu_io_rs2_1_valid = regfile_io_readData_3_valid; // @[SCore.scala 205:17]
+  assign mlu_io_rs2_1_data = regfile_io_readData_3_data; // @[SCore.scala 205:17]
+  assign mlu_io_rs2_2_valid = regfile_io_readData_5_valid; // @[SCore.scala 206:17]
+  assign mlu_io_rs2_2_data = regfile_io_readData_5_data; // @[SCore.scala 206:17]
+  assign mlu_io_rs2_3_valid = regfile_io_readData_7_valid; // @[SCore.scala 207:17]
+  assign mlu_io_rs2_3_data = regfile_io_readData_7_data; // @[SCore.scala 207:17]
   assign dvu_clock = clock;
   assign dvu_reset = reset;
-  assign dvu_io_req_valid = decode_0_io_dvu_valid; // @[SCore.scala 227:14]
-  assign dvu_io_req_addr = decode_0_io_dvu_addr; // @[SCore.scala 227:14]
-  assign dvu_io_req_op = decode_0_io_dvu_op; // @[SCore.scala 227:14]
-  assign dvu_io_rs1_data = regfile_io_readData_0_data; // @[SCore.scala 228:14]
-  assign dvu_io_rs2_data = regfile_io_readData_1_data; // @[SCore.scala 229:14]
-  assign dvu_io_rd_ready = ~mlu_io_rd_valid; // @[SCore.scala 230:22]
-  assign fpu_clock = clock;
-  assign fpu_reset = reset;
-  assign fpu_io_req_0_valid = decode_0_io_fpu_valid; // @[SCore.scala 303:17]
-  assign fpu_io_req_0_raddr_0 = decode_0_io_fpu_raddr_0; // @[SCore.scala 303:17]
-  assign fpu_io_req_0_raddr_1 = decode_0_io_fpu_raddr_1; // @[SCore.scala 303:17]
-  assign fpu_io_req_0_raddr_2 = decode_0_io_fpu_raddr_2; // @[SCore.scala 303:17]
-  assign fpu_io_req_0_waddr = decode_0_io_fpu_waddr; // @[SCore.scala 303:17]
-  assign fpu_io_req_0_op = decode_0_io_fpu_op; // @[SCore.scala 303:17]
-  assign fpu_io_req_1_raddr_1 = decode_1_io_fpu_raddr_1; // @[SCore.scala 304:17]
-  assign fpu_io_req_1_op = decode_1_io_fpu_op; // @[SCore.scala 304:17]
-  assign fpu_io_req_2_raddr_1 = decode_2_io_fpu_raddr_1; // @[SCore.scala 305:17]
-  assign fpu_io_req_2_op = decode_2_io_fpu_op; // @[SCore.scala 305:17]
-  assign fpu_io_req_3_raddr_1 = decode_3_io_fpu_raddr_1; // @[SCore.scala 306:17]
-  assign fpu_io_req_3_op = decode_3_io_fpu_op; // @[SCore.scala 306:17]
-  assign fpu_io_fwriteData_valid = lsu_io_fd_valid; // @[SCore.scala 308:21]
-  assign fpu_io_fwriteData_addr = lsu_io_fd_addr; // @[SCore.scala 308:21]
-  assign fpu_io_fwriteData_data = lsu_io_fd_data; // @[SCore.scala 308:21]
-  assign fpu_io_readData_data = regfile_io_readData_0_data; // @[SCore.scala 310:19]
+  assign dvu_io_req_valid = decode_0_io_dvu_valid; // @[SCore.scala 215:14]
+  assign dvu_io_req_addr = decode_0_io_dvu_addr; // @[SCore.scala 215:14]
+  assign dvu_io_req_op = decode_0_io_dvu_op; // @[SCore.scala 215:14]
+  assign dvu_io_rs1_data = regfile_io_readData_0_data; // @[SCore.scala 216:14]
+  assign dvu_io_rs2_data = regfile_io_readData_1_data; // @[SCore.scala 217:14]
+  assign dvu_io_rd_ready = ~mlu_io_rd_valid; // @[SCore.scala 218:22]
   always @(posedge clock) begin
     slogAddr <= _GEN_2[1:0];
     `ifndef SYNTHESIS
@@ -32289,6 +23014,28 @@
       if (`STOP_COND) begin
     `endif
         if (~reset & ~(~bru_1_io_iflush)) begin
+          $fatal; // @[SCore.scala 64:9]
+        end
+    `ifdef STOP_COND
+      end
+    `endif
+    `endif // SYNTHESIS
+    `ifndef SYNTHESIS
+    `ifdef PRINTF_COND
+      if (`PRINTF_COND) begin
+    `endif
+        if (~reset & ~(~bru_1_io_iflush)) begin
+          $fwrite(32'h80000002,"Assertion failed\n    at SCore.scala:64 assert(!bru(1).io.iflush)\n"); // @[SCore.scala 64:9]
+        end
+    `ifdef PRINTF_COND
+      end
+    `endif
+    `endif // SYNTHESIS
+    `ifndef SYNTHESIS
+    `ifdef STOP_COND
+      if (`STOP_COND) begin
+    `endif
+        if (_T_5 & ~(~bru_2_io_iflush)) begin
           $fatal; // @[SCore.scala 65:9]
         end
     `ifdef STOP_COND
@@ -32299,8 +23046,8 @@
     `ifdef PRINTF_COND
       if (`PRINTF_COND) begin
     `endif
-        if (~reset & ~(~bru_1_io_iflush)) begin
-          $fwrite(32'h80000002,"Assertion failed\n    at SCore.scala:65 assert(!bru(1).io.iflush)\n"); // @[SCore.scala 65:9]
+        if (_T_5 & ~(~bru_2_io_iflush)) begin
+          $fwrite(32'h80000002,"Assertion failed\n    at SCore.scala:65 assert(!bru(2).io.iflush)\n"); // @[SCore.scala 65:9]
         end
     `ifdef PRINTF_COND
       end
@@ -32310,7 +23057,7 @@
     `ifdef STOP_COND
       if (`STOP_COND) begin
     `endif
-        if (_T_5 & ~(~bru_2_io_iflush)) begin
+        if (_T_5 & ~(~bru_3_io_iflush)) begin
           $fatal; // @[SCore.scala 66:9]
         end
     `ifdef STOP_COND
@@ -32321,30 +23068,8 @@
     `ifdef PRINTF_COND
       if (`PRINTF_COND) begin
     `endif
-        if (_T_5 & ~(~bru_2_io_iflush)) begin
-          $fwrite(32'h80000002,"Assertion failed\n    at SCore.scala:66 assert(!bru(2).io.iflush)\n"); // @[SCore.scala 66:9]
-        end
-    `ifdef PRINTF_COND
-      end
-    `endif
-    `endif // SYNTHESIS
-    `ifndef SYNTHESIS
-    `ifdef STOP_COND
-      if (`STOP_COND) begin
-    `endif
         if (_T_5 & ~(~bru_3_io_iflush)) begin
-          $fatal; // @[SCore.scala 67:9]
-        end
-    `ifdef STOP_COND
-      end
-    `endif
-    `endif // SYNTHESIS
-    `ifndef SYNTHESIS
-    `ifdef PRINTF_COND
-      if (`PRINTF_COND) begin
-    `endif
-        if (_T_5 & ~(~bru_3_io_iflush)) begin
-          $fwrite(32'h80000002,"Assertion failed\n    at SCore.scala:67 assert(!bru(3).io.iflush)\n"); // @[SCore.scala 67:9]
+          $fwrite(32'h80000002,"Assertion failed\n    at SCore.scala:66 assert(!bru(3).io.iflush)\n"); // @[SCore.scala 66:9]
         end
     `ifdef PRINTF_COND
       end
@@ -32354,8 +23079,8 @@
     `ifdef STOP_COND
       if (`STOP_COND) begin
     `endif
-        if (_T_5 & ~_T_20) begin
-          $fatal; // @[SCore.scala 279:11]
+        if (_T_5 & ~_T_18) begin
+          $fatal; // @[SCore.scala 256:11]
         end
     `ifdef STOP_COND
       end
@@ -32365,9 +23090,8 @@
     `ifdef PRINTF_COND
       if (`PRINTF_COND) begin
     `endif
-        if (_T_5 & ~_T_20) begin
-          $fwrite(32'h80000002,
-            "Assertion failed\n    at SCore.scala:279 assert((csr0Valid +& fpu0Valid +& fpu1Valid +&\n"); // @[SCore.scala 279:11]
+        if (_T_5 & ~_T_18) begin
+          $fwrite(32'h80000002,"Assertion failed\n    at SCore.scala:256 assert((csr0Valid +&\n"); // @[SCore.scala 256:11]
         end
     `ifdef PRINTF_COND
       end
@@ -32377,8 +23101,8 @@
     `ifdef STOP_COND
       if (`STOP_COND) begin
     `endif
-        if (_T_5 & ~_T_29) begin
-          $fatal; // @[SCore.scala 279:11]
+        if (_T_5 & ~_T_25) begin
+          $fatal; // @[SCore.scala 256:11]
         end
     `ifdef STOP_COND
       end
@@ -32388,9 +23112,8 @@
     `ifdef PRINTF_COND
       if (`PRINTF_COND) begin
     `endif
-        if (_T_5 & ~_T_29) begin
-          $fwrite(32'h80000002,
-            "Assertion failed\n    at SCore.scala:279 assert((csr0Valid +& fpu0Valid +& fpu1Valid +&\n"); // @[SCore.scala 279:11]
+        if (_T_5 & ~_T_25) begin
+          $fwrite(32'h80000002,"Assertion failed\n    at SCore.scala:256 assert((csr0Valid +&\n"); // @[SCore.scala 256:11]
         end
     `ifdef PRINTF_COND
       end
@@ -32400,8 +23123,8 @@
     `ifdef STOP_COND
       if (`STOP_COND) begin
     `endif
-        if (_T_5 & ~_T_38) begin
-          $fatal; // @[SCore.scala 279:11]
+        if (_T_5 & ~_T_32) begin
+          $fatal; // @[SCore.scala 256:11]
         end
     `ifdef STOP_COND
       end
@@ -32411,9 +23134,8 @@
     `ifdef PRINTF_COND
       if (`PRINTF_COND) begin
     `endif
-        if (_T_5 & ~_T_38) begin
-          $fwrite(32'h80000002,
-            "Assertion failed\n    at SCore.scala:279 assert((csr0Valid +& fpu0Valid +& fpu1Valid +&\n"); // @[SCore.scala 279:11]
+        if (_T_5 & ~_T_32) begin
+          $fwrite(32'h80000002,"Assertion failed\n    at SCore.scala:256 assert((csr0Valid +&\n"); // @[SCore.scala 256:11]
         end
     `ifdef PRINTF_COND
       end
@@ -32423,8 +23145,8 @@
     `ifdef STOP_COND
       if (`STOP_COND) begin
     `endif
-        if (_T_5 & ~_T_47) begin
-          $fatal; // @[SCore.scala 279:11]
+        if (_T_5 & ~_T_39) begin
+          $fatal; // @[SCore.scala 256:11]
         end
     `ifdef STOP_COND
       end
@@ -32434,9 +23156,8 @@
     `ifdef PRINTF_COND
       if (`PRINTF_COND) begin
     `endif
-        if (_T_5 & ~_T_47) begin
-          $fwrite(32'h80000002,
-            "Assertion failed\n    at SCore.scala:279 assert((csr0Valid +& fpu0Valid +& fpu1Valid +&\n"); // @[SCore.scala 279:11]
+        if (_T_5 & ~_T_39) begin
+          $fwrite(32'h80000002,"Assertion failed\n    at SCore.scala:256 assert((csr0Valid +&\n"); // @[SCore.scala 256:11]
         end
     `ifdef PRINTF_COND
       end
@@ -32447,7 +23168,7 @@
       if (`STOP_COND) begin
     `endif
         if (_T_5 & ~(~(mlu_io_rd_valid & (dvu_io_rd_valid & dvu_io_rd_ready)))) begin
-          $fatal; // @[SCore.scala 287:9]
+          $fatal; // @[SCore.scala 264:9]
         end
     `ifdef STOP_COND
       end
@@ -32459,8 +23180,8 @@
     `endif
         if (_T_5 & ~(~(mlu_io_rd_valid & (dvu_io_rd_valid & dvu_io_rd_ready)))) begin
           $fwrite(32'h80000002,
-            "Assertion failed\n    at SCore.scala:287 assert(!(mlu.io.rd.valid && (dvu.io.rd.valid && dvu.io.rd.ready)))  // TODO: stall dvu on mlu write\n"
-            ); // @[SCore.scala 287:9]
+            "Assertion failed\n    at SCore.scala:264 assert(!(mlu.io.rd.valid && (dvu.io.rd.valid && dvu.io.rd.ready)))  // TODO: stall dvu on mlu write\n"
+            ); // @[SCore.scala 264:9]
         end
     `ifdef PRINTF_COND
       end
@@ -32468,31 +23189,24 @@
     `endif // SYNTHESIS
   end
   always @(posedge clock or posedge reset) begin
-    if (reset) begin // @[SCore.scala 53:27]
-      iflush <= 1'h0; // @[SCore.scala 54:12]
+    if (reset) begin // @[SCore.scala 52:27]
+      iflush <= 1'h0; // @[SCore.scala 53:12]
     end else begin
       iflush <= bru_0_io_iflush | _GEN_0;
     end
   end
   always @(posedge clock or posedge reset) begin
-    if (reset) begin // @[Cat.scala 31:58]
-      interlockPipe2Reg <= 2'h0;
+    if (reset) begin // @[SCore.scala 46:43]
+      mluInvalidate <= 1'h0;
     end else begin
-      interlockPipe2Reg <= {_interlockPipe2Reg_T_3,interlockPipe2Reg[1]};
+      mluInvalidate <= _branchTaken_T_1 | bru_3_io_taken_valid;
     end
   end
   always @(posedge clock or posedge reset) begin
-    if (reset) begin // @[SCore.scala 112:43]
-      interlockPipe3 <= 1'h0;
+    if (reset) begin // @[SCore.scala 302:26]
+      slogValid <= 1'h0; // @[SCore.scala 302:26]
     end else begin
-      interlockPipe3 <= decode_0_io_fpu_op[18];
-    end
-  end
-  always @(posedge clock or posedge reset) begin
-    if (reset) begin // @[SCore.scala 344:26]
-      slogValid <= 1'h0; // @[SCore.scala 344:26]
-    end else begin
-      slogValid <= decode_0_io_slog; // @[SCore.scala 348:13]
+      slogValid <= decode_0_io_slog; // @[SCore.scala 306:13]
     end
   end
 // Register and memory initialization
@@ -32534,22 +23248,17 @@
   _RAND_0 = {1{`RANDOM}};
   iflush = _RAND_0[0:0];
   _RAND_1 = {1{`RANDOM}};
-  interlockPipe2Reg = _RAND_1[1:0];
+  mluInvalidate = _RAND_1[0:0];
   _RAND_2 = {1{`RANDOM}};
-  interlockPipe3 = _RAND_2[0:0];
+  slogValid = _RAND_2[0:0];
   _RAND_3 = {1{`RANDOM}};
-  slogValid = _RAND_3[0:0];
-  _RAND_4 = {1{`RANDOM}};
-  slogAddr = _RAND_4[1:0];
+  slogAddr = _RAND_3[1:0];
 `endif // RANDOMIZE_REG_INIT
   if (reset) begin
     iflush = 1'h0;
   end
   if (reset) begin
-    interlockPipe2Reg = 2'h0;
-  end
-  if (reset) begin
-    interlockPipe3 = 1'h0;
+    mluInvalidate = 1'h0;
   end
   if (reset) begin
     slogValid = 1'h0;
@@ -32561,7 +23270,7 @@
 `endif
 `endif // SYNTHESIS
 endmodule
-module Slice_4(
+module Slice_3(
   input         clock,
   input         reset,
   output        io_in_ready,
@@ -32971,22 +23680,22 @@
   output        io_in_0_ready,
   input  [4:0]  io_in_0_addr,
   input  [31:0] io_in_0_inst,
-  input  [5:0]  io_in_0_op,
+  input  [4:0]  io_in_0_op,
   input         io_in_1_valid,
   output        io_in_1_ready,
   input  [4:0]  io_in_1_addr,
   input  [31:0] io_in_1_inst,
-  input  [5:0]  io_in_1_op,
+  input  [4:0]  io_in_1_op,
   input         io_in_2_valid,
   output        io_in_2_ready,
   input  [4:0]  io_in_2_addr,
   input  [31:0] io_in_2_inst,
-  input  [5:0]  io_in_2_op,
+  input  [4:0]  io_in_2_op,
   input         io_in_3_valid,
   output        io_in_3_ready,
   input  [4:0]  io_in_3_addr,
   input  [31:0] io_in_3_inst,
-  input  [5:0]  io_in_3_op,
+  input  [4:0]  io_in_3_op,
   input  [31:0] io_rs_0_data,
   input  [31:0] io_rs_1_data,
   input  [31:0] io_rs_2_data,
@@ -33007,10 +23716,6 @@
   output        io_rd_3_valid,
   output [4:0]  io_rd_3_addr,
   output [31:0] io_rd_3_data,
-  input  [31:0] io_fs_0_data,
-  input  [31:0] io_fs_1_data,
-  input  [31:0] io_fs_2_data,
-  input  [31:0] io_fs_3_data,
   output        io_out_valid,
   input         io_out_ready,
   input         io_out_stall,
@@ -33067,10 +23772,6 @@
   reg [31:0] _RAND_31;
   reg [31:0] _RAND_32;
   reg [31:0] _RAND_33;
-  reg [31:0] _RAND_34;
-  reg [31:0] _RAND_35;
-  reg [31:0] _RAND_36;
-  reg [31:0] _RAND_37;
 `endif // RANDOMIZE_REG_INIT
   wire  slice_clock; // @[Slice.scala 9:11]
   wire  slice_reset; // @[Slice.scala 9:11]
@@ -33110,157 +23811,149 @@
   wire [31:0] slice_io_out_bits_3_lane_bits_inst; // @[Slice.scala 9:11]
   wire [31:0] slice_io_out_bits_3_lane_bits_addr; // @[Slice.scala 9:11]
   wire [31:0] slice_io_out_bits_3_lane_bits_data; // @[Slice.scala 9:11]
-  wire  _T_2 = ~reset; // @[VInst.scala 78:9]
-  wire  reqvalid_0 = io_in_0_valid & io_in_0_ready; // @[VInst.scala 86:41]
-  wire  reqvalid_1 = io_in_1_valid & io_in_1_ready; // @[VInst.scala 87:41]
-  wire  reqvalid_2 = io_in_2_valid & io_in_2_ready; // @[VInst.scala 88:41]
-  wire  reqvalid_3 = io_in_3_valid & io_in_3_ready; // @[VInst.scala 89:41]
-  reg  vld_u_0; // @[VInst.scala 105:22]
-  reg  vld_u_1; // @[VInst.scala 105:22]
-  reg  vld_u_2; // @[VInst.scala 105:22]
-  reg  vld_u_3; // @[VInst.scala 105:22]
-  reg  vst_u_0; // @[VInst.scala 107:22]
-  reg  vst_u_1; // @[VInst.scala 107:22]
-  reg  vst_u_2; // @[VInst.scala 107:22]
-  reg  vst_u_3; // @[VInst.scala 107:22]
-  reg  vst_q_0; // @[VInst.scala 108:22]
-  reg  vst_q_1; // @[VInst.scala 108:22]
-  reg  vst_q_2; // @[VInst.scala 108:22]
-  reg  vst_q_3; // @[VInst.scala 108:22]
-  reg  vfop_0; // @[VInst.scala 109:22]
-  reg  vfop_1; // @[VInst.scala 109:22]
-  reg  vfop_2; // @[VInst.scala 109:22]
-  reg  vfop_3; // @[VInst.scala 109:22]
-  reg  getvl_0; // @[VInst.scala 110:22]
-  reg  getvl_1; // @[VInst.scala 110:22]
-  reg  getvl_2; // @[VInst.scala 110:22]
-  reg  getvl_3; // @[VInst.scala 110:22]
-  reg  getmaxvl_0; // @[VInst.scala 111:25]
-  reg  getmaxvl_1; // @[VInst.scala 111:25]
-  reg  getmaxvl_2; // @[VInst.scala 111:25]
-  reg  getmaxvl_3; // @[VInst.scala 111:25]
-  reg [4:0] rdAddr_0; // @[VInst.scala 113:19]
-  reg [4:0] rdAddr_1; // @[VInst.scala 113:19]
-  reg [4:0] rdAddr_2; // @[VInst.scala 113:19]
-  reg [4:0] rdAddr_3; // @[VInst.scala 113:19]
-  reg  vvalid; // @[VInst.scala 123:23]
-  reg  vinstValid_0; // @[VInst.scala 124:23]
-  reg  vinstValid_1; // @[VInst.scala 124:23]
-  reg  vinstValid_2; // @[VInst.scala 124:23]
-  reg  vinstValid_3; // @[VInst.scala 124:23]
-  reg [31:0] vinstInst_0; // @[VInst.scala 125:22]
-  reg [31:0] vinstInst_1; // @[VInst.scala 125:22]
-  reg [31:0] vinstInst_2; // @[VInst.scala 125:22]
-  reg [31:0] vinstInst_3; // @[VInst.scala 125:22]
-  wire  _nxtVinstValid_1_T_2 = io_in_1_op[2] | io_in_1_op[3]; // @[VInst.scala 131:64]
-  wire  _nxtVinstValid_1_T_4 = _nxtVinstValid_1_T_2 | io_in_1_op[4]; // @[VInst.scala 132:64]
-  wire  _nxtVinstValid_1_T_6 = _nxtVinstValid_1_T_4 | io_in_1_op[5]; // @[VInst.scala 133:65]
-  wire  nxtVinstValid_1 = reqvalid_1 & _nxtVinstValid_1_T_6; // @[VInst.scala 131:37]
-  wire  _nxtVinstValid_0_T_2 = io_in_0_op[2] | io_in_0_op[3]; // @[VInst.scala 131:64]
-  wire  _nxtVinstValid_0_T_4 = _nxtVinstValid_0_T_2 | io_in_0_op[4]; // @[VInst.scala 132:64]
-  wire  _nxtVinstValid_0_T_6 = _nxtVinstValid_0_T_4 | io_in_0_op[5]; // @[VInst.scala 133:65]
-  wire  nxtVinstValid_0 = reqvalid_0 & _nxtVinstValid_0_T_6; // @[VInst.scala 131:37]
-  wire  _nxtVinstValid_3_T_2 = io_in_3_op[2] | io_in_3_op[3]; // @[VInst.scala 131:64]
-  wire  _nxtVinstValid_3_T_4 = _nxtVinstValid_3_T_2 | io_in_3_op[4]; // @[VInst.scala 132:64]
-  wire  _nxtVinstValid_3_T_6 = _nxtVinstValid_3_T_4 | io_in_3_op[5]; // @[VInst.scala 133:65]
-  wire  nxtVinstValid_3 = reqvalid_3 & _nxtVinstValid_3_T_6; // @[VInst.scala 131:37]
-  wire  _nxtVinstValid_2_T_2 = io_in_2_op[2] | io_in_2_op[3]; // @[VInst.scala 131:64]
-  wire  _nxtVinstValid_2_T_4 = _nxtVinstValid_2_T_2 | io_in_2_op[4]; // @[VInst.scala 132:64]
-  wire  _nxtVinstValid_2_T_6 = _nxtVinstValid_2_T_4 | io_in_2_op[5]; // @[VInst.scala 133:65]
-  wire  nxtVinstValid_2 = reqvalid_2 & _nxtVinstValid_2_T_6; // @[VInst.scala 131:37]
-  wire [3:0] _vvalid_T = {nxtVinstValid_3,nxtVinstValid_2,nxtVinstValid_1,nxtVinstValid_0}; // @[VInst.scala 128:27]
-  wire  p = io_in_0_inst[28]; // @[VInst.scala 140:26]
-  wire  q = io_in_0_inst[30]; // @[VInst.scala 141:26]
-  wire  _vld_o_0_T_1 = reqvalid_0 & io_in_0_op[2]; // @[VInst.scala 142:29]
-  wire  _vst_o_0_T_1 = reqvalid_0 & io_in_0_op[3]; // @[VInst.scala 144:29]
-  wire  _vst_u_0_T_2 = _vst_o_0_T_1 & p; // @[VInst.scala 145:55]
-  wire  p_1 = io_in_1_inst[28]; // @[VInst.scala 140:26]
-  wire  q_1 = io_in_1_inst[30]; // @[VInst.scala 141:26]
-  wire  _vld_o_1_T_1 = reqvalid_1 & io_in_1_op[2]; // @[VInst.scala 142:29]
-  wire  _vst_o_1_T_1 = reqvalid_1 & io_in_1_op[3]; // @[VInst.scala 144:29]
-  wire  _vst_u_1_T_2 = _vst_o_1_T_1 & p_1; // @[VInst.scala 145:55]
-  wire  p_2 = io_in_2_inst[28]; // @[VInst.scala 140:26]
-  wire  q_2 = io_in_2_inst[30]; // @[VInst.scala 141:26]
-  wire  _vld_o_2_T_1 = reqvalid_2 & io_in_2_op[2]; // @[VInst.scala 142:29]
-  wire  _vst_o_2_T_1 = reqvalid_2 & io_in_2_op[3]; // @[VInst.scala 144:29]
-  wire  _vst_u_2_T_2 = _vst_o_2_T_1 & p_2; // @[VInst.scala 145:55]
-  wire  p_3 = io_in_3_inst[28]; // @[VInst.scala 140:26]
-  wire  q_3 = io_in_3_inst[30]; // @[VInst.scala 141:26]
-  wire  _vld_o_3_T_1 = reqvalid_3 & io_in_3_op[2]; // @[VInst.scala 142:29]
-  wire  _vst_o_3_T_1 = reqvalid_3 & io_in_3_op[3]; // @[VInst.scala 144:29]
-  wire  _vst_u_3_T_2 = _vst_o_3_T_1 & p_3; // @[VInst.scala 145:55]
-  wire  m = vinstInst_0[5]; // @[VInst.scala 161:26]
-  wire [1:0] sz = vinstInst_0[13:12]; // @[VInst.scala 162:26]
-  wire [1:0] sl = vinstInst_0[27:26]; // @[VInst.scala 163:26]
-  wire  q_4 = vinstInst_0[30]; // @[VInst.scala 164:26]
-  wire  xs2zero = vinstInst_0[24:20] == 5'h0; // @[VInst.scala 166:39]
-  wire  _max_T = sz == 2'h0; // @[VInst.scala 168:24]
-  wire  _max_T_1 = ~m; // @[VInst.scala 168:35]
-  wire  _max_T_2 = sz == 2'h0 & ~m; // @[VInst.scala 168:32]
+  wire  _T_2 = ~reset; // @[VInst.scala 76:9]
+  wire  reqvalid_0 = io_in_0_valid & io_in_0_ready; // @[VInst.scala 84:41]
+  wire  reqvalid_1 = io_in_1_valid & io_in_1_ready; // @[VInst.scala 85:41]
+  wire  reqvalid_2 = io_in_2_valid & io_in_2_ready; // @[VInst.scala 86:41]
+  wire  reqvalid_3 = io_in_3_valid & io_in_3_ready; // @[VInst.scala 87:41]
+  reg  vld_u_0; // @[VInst.scala 103:22]
+  reg  vld_u_1; // @[VInst.scala 103:22]
+  reg  vld_u_2; // @[VInst.scala 103:22]
+  reg  vld_u_3; // @[VInst.scala 103:22]
+  reg  vst_u_0; // @[VInst.scala 105:22]
+  reg  vst_u_1; // @[VInst.scala 105:22]
+  reg  vst_u_2; // @[VInst.scala 105:22]
+  reg  vst_u_3; // @[VInst.scala 105:22]
+  reg  vst_q_0; // @[VInst.scala 106:22]
+  reg  vst_q_1; // @[VInst.scala 106:22]
+  reg  vst_q_2; // @[VInst.scala 106:22]
+  reg  vst_q_3; // @[VInst.scala 106:22]
+  reg  getvl_0; // @[VInst.scala 107:22]
+  reg  getvl_1; // @[VInst.scala 107:22]
+  reg  getvl_2; // @[VInst.scala 107:22]
+  reg  getvl_3; // @[VInst.scala 107:22]
+  reg  getmaxvl_0; // @[VInst.scala 108:25]
+  reg  getmaxvl_1; // @[VInst.scala 108:25]
+  reg  getmaxvl_2; // @[VInst.scala 108:25]
+  reg  getmaxvl_3; // @[VInst.scala 108:25]
+  reg [4:0] rdAddr_0; // @[VInst.scala 110:19]
+  reg [4:0] rdAddr_1; // @[VInst.scala 110:19]
+  reg [4:0] rdAddr_2; // @[VInst.scala 110:19]
+  reg [4:0] rdAddr_3; // @[VInst.scala 110:19]
+  reg  vvalid; // @[VInst.scala 120:23]
+  reg  vinstValid_0; // @[VInst.scala 121:23]
+  reg  vinstValid_1; // @[VInst.scala 121:23]
+  reg  vinstValid_2; // @[VInst.scala 121:23]
+  reg  vinstValid_3; // @[VInst.scala 121:23]
+  reg [31:0] vinstInst_0; // @[VInst.scala 122:22]
+  reg [31:0] vinstInst_1; // @[VInst.scala 122:22]
+  reg [31:0] vinstInst_2; // @[VInst.scala 122:22]
+  reg [31:0] vinstInst_3; // @[VInst.scala 122:22]
+  wire  _nxtVinstValid_1_T_2 = io_in_1_op[2] | io_in_1_op[3]; // @[VInst.scala 128:64]
+  wire  _nxtVinstValid_1_T_4 = _nxtVinstValid_1_T_2 | io_in_1_op[4]; // @[VInst.scala 129:64]
+  wire  nxtVinstValid_1 = reqvalid_1 & _nxtVinstValid_1_T_4; // @[VInst.scala 128:37]
+  wire  _nxtVinstValid_0_T_2 = io_in_0_op[2] | io_in_0_op[3]; // @[VInst.scala 128:64]
+  wire  _nxtVinstValid_0_T_4 = _nxtVinstValid_0_T_2 | io_in_0_op[4]; // @[VInst.scala 129:64]
+  wire  nxtVinstValid_0 = reqvalid_0 & _nxtVinstValid_0_T_4; // @[VInst.scala 128:37]
+  wire  _nxtVinstValid_3_T_2 = io_in_3_op[2] | io_in_3_op[3]; // @[VInst.scala 128:64]
+  wire  _nxtVinstValid_3_T_4 = _nxtVinstValid_3_T_2 | io_in_3_op[4]; // @[VInst.scala 129:64]
+  wire  nxtVinstValid_3 = reqvalid_3 & _nxtVinstValid_3_T_4; // @[VInst.scala 128:37]
+  wire  _nxtVinstValid_2_T_2 = io_in_2_op[2] | io_in_2_op[3]; // @[VInst.scala 128:64]
+  wire  _nxtVinstValid_2_T_4 = _nxtVinstValid_2_T_2 | io_in_2_op[4]; // @[VInst.scala 129:64]
+  wire  nxtVinstValid_2 = reqvalid_2 & _nxtVinstValid_2_T_4; // @[VInst.scala 128:37]
+  wire [3:0] _vvalid_T = {nxtVinstValid_3,nxtVinstValid_2,nxtVinstValid_1,nxtVinstValid_0}; // @[VInst.scala 125:27]
+  wire  p = io_in_0_inst[28]; // @[VInst.scala 136:26]
+  wire  q = io_in_0_inst[30]; // @[VInst.scala 137:26]
+  wire  _vld_o_0_T_1 = reqvalid_0 & io_in_0_op[2]; // @[VInst.scala 138:29]
+  wire  _vst_o_0_T_1 = reqvalid_0 & io_in_0_op[3]; // @[VInst.scala 140:29]
+  wire  _vst_u_0_T_2 = _vst_o_0_T_1 & p; // @[VInst.scala 141:55]
+  wire  p_1 = io_in_1_inst[28]; // @[VInst.scala 136:26]
+  wire  q_1 = io_in_1_inst[30]; // @[VInst.scala 137:26]
+  wire  _vld_o_1_T_1 = reqvalid_1 & io_in_1_op[2]; // @[VInst.scala 138:29]
+  wire  _vst_o_1_T_1 = reqvalid_1 & io_in_1_op[3]; // @[VInst.scala 140:29]
+  wire  _vst_u_1_T_2 = _vst_o_1_T_1 & p_1; // @[VInst.scala 141:55]
+  wire  p_2 = io_in_2_inst[28]; // @[VInst.scala 136:26]
+  wire  q_2 = io_in_2_inst[30]; // @[VInst.scala 137:26]
+  wire  _vld_o_2_T_1 = reqvalid_2 & io_in_2_op[2]; // @[VInst.scala 138:29]
+  wire  _vst_o_2_T_1 = reqvalid_2 & io_in_2_op[3]; // @[VInst.scala 140:29]
+  wire  _vst_u_2_T_2 = _vst_o_2_T_1 & p_2; // @[VInst.scala 141:55]
+  wire  p_3 = io_in_3_inst[28]; // @[VInst.scala 136:26]
+  wire  q_3 = io_in_3_inst[30]; // @[VInst.scala 137:26]
+  wire  _vld_o_3_T_1 = reqvalid_3 & io_in_3_op[2]; // @[VInst.scala 138:29]
+  wire  _vst_o_3_T_1 = reqvalid_3 & io_in_3_op[3]; // @[VInst.scala 140:29]
+  wire  _vst_u_3_T_2 = _vst_o_3_T_1 & p_3; // @[VInst.scala 141:55]
+  wire  m = vinstInst_0[5]; // @[VInst.scala 156:26]
+  wire [1:0] sz = vinstInst_0[13:12]; // @[VInst.scala 157:26]
+  wire [1:0] sl = vinstInst_0[27:26]; // @[VInst.scala 158:26]
+  wire  q_4 = vinstInst_0[30]; // @[VInst.scala 159:26]
+  wire  xs2zero = vinstInst_0[24:20] == 5'h0; // @[VInst.scala 161:39]
+  wire  _max_T = sz == 2'h0; // @[VInst.scala 163:24]
+  wire  _max_T_1 = ~m; // @[VInst.scala 163:35]
+  wire  _max_T_2 = sz == 2'h0 & ~m; // @[VInst.scala 163:32]
   wire [7:0] _max_T_3 = _max_T_2 ? 8'h20 : 8'h0; // @[Library.scala 8:8]
-  wire  _max_T_4 = sz == 2'h1; // @[VInst.scala 169:24]
-  wire  _max_T_6 = sz == 2'h1 & _max_T_1; // @[VInst.scala 169:32]
+  wire  _max_T_4 = sz == 2'h1; // @[VInst.scala 164:24]
+  wire  _max_T_6 = sz == 2'h1 & _max_T_1; // @[VInst.scala 164:32]
   wire [7:0] _max_T_7 = _max_T_6 ? 8'h10 : 8'h0; // @[Library.scala 8:8]
-  wire [7:0] _max_T_8 = _max_T_3 | _max_T_7; // @[VInst.scala 168:47]
-  wire  _max_T_9 = sz == 2'h2; // @[VInst.scala 170:24]
-  wire  _max_T_11 = sz == 2'h2 & _max_T_1; // @[VInst.scala 170:32]
+  wire [7:0] _max_T_8 = _max_T_3 | _max_T_7; // @[VInst.scala 163:47]
+  wire  _max_T_9 = sz == 2'h2; // @[VInst.scala 165:24]
+  wire  _max_T_11 = sz == 2'h2 & _max_T_1; // @[VInst.scala 165:32]
   wire [7:0] _max_T_12 = _max_T_11 ? 8'h8 : 8'h0; // @[Library.scala 8:8]
-  wire [7:0] _max_T_13 = _max_T_8 | _max_T_12; // @[VInst.scala 169:47]
-  wire  _max_T_15 = _max_T & m; // @[VInst.scala 171:32]
+  wire [7:0] _max_T_13 = _max_T_8 | _max_T_12; // @[VInst.scala 164:47]
+  wire  _max_T_15 = _max_T & m; // @[VInst.scala 166:32]
   wire [7:0] _max_T_16 = _max_T_15 ? 8'h80 : 8'h0; // @[Library.scala 8:8]
-  wire [7:0] _max_T_17 = _max_T_13 | _max_T_16; // @[VInst.scala 170:47]
-  wire  _max_T_19 = _max_T_4 & m; // @[VInst.scala 172:32]
+  wire [7:0] _max_T_17 = _max_T_13 | _max_T_16; // @[VInst.scala 165:47]
+  wire  _max_T_19 = _max_T_4 & m; // @[VInst.scala 167:32]
   wire [7:0] _max_T_20 = _max_T_19 ? 8'h40 : 8'h0; // @[Library.scala 8:8]
-  wire [7:0] _max_T_21 = _max_T_17 | _max_T_20; // @[VInst.scala 171:47]
-  wire  _max_T_23 = _max_T_9 & m; // @[VInst.scala 173:32]
+  wire [7:0] _max_T_21 = _max_T_17 | _max_T_20; // @[VInst.scala 166:47]
+  wire  _max_T_23 = _max_T_9 & m; // @[VInst.scala 168:32]
   wire [7:0] _max_T_24 = _max_T_23 ? 8'h20 : 8'h0; // @[Library.scala 8:8]
-  wire [7:0] max = _max_T_21 | _max_T_24; // @[VInst.scala 172:47]
-  wire [31:0] _GEN_12 = {{24'd0}, max}; // @[VInst.scala 175:25]
-  wire [31:0] cmp = io_rs_1_data < _GEN_12 ? io_rs_1_data : {{24'd0}, max}; // @[VInst.scala 175:18]
-  wire  _bytes_T_2 = _max_T & sl[0]; // @[VInst.scala 177:35]
+  wire [7:0] max = _max_T_21 | _max_T_24; // @[VInst.scala 167:47]
+  wire [31:0] _GEN_12 = {{24'd0}, max}; // @[VInst.scala 170:25]
+  wire [31:0] cmp = io_rs_1_data < _GEN_12 ? io_rs_1_data : {{24'd0}, max}; // @[VInst.scala 170:18]
+  wire  _bytes_T_2 = _max_T & sl[0]; // @[VInst.scala 172:35]
   wire [31:0] _bytes_T_3 = _bytes_T_2 ? cmp : 32'h0; // @[Library.scala 8:8]
-  wire  _bytes_T_6 = _max_T_4 & sl[0]; // @[VInst.scala 178:35]
+  wire  _bytes_T_6 = _max_T_4 & sl[0]; // @[VInst.scala 173:35]
   wire [32:0] _bytes_T_7 = {cmp,1'h0}; // @[Cat.scala 31:58]
   wire [32:0] _bytes_T_8 = _bytes_T_6 ? _bytes_T_7 : 33'h0; // @[Library.scala 8:8]
-  wire [32:0] _GEN_13 = {{1'd0}, _bytes_T_3}; // @[VInst.scala 177:50]
-  wire [32:0] _bytes_T_9 = _GEN_13 | _bytes_T_8; // @[VInst.scala 177:50]
-  wire  _bytes_T_12 = _max_T_9 & sl[0]; // @[VInst.scala 179:35]
+  wire [32:0] _GEN_13 = {{1'd0}, _bytes_T_3}; // @[VInst.scala 172:50]
+  wire [32:0] _bytes_T_9 = _GEN_13 | _bytes_T_8; // @[VInst.scala 172:50]
+  wire  _bytes_T_12 = _max_T_9 & sl[0]; // @[VInst.scala 174:35]
   wire [33:0] _bytes_T_13 = {cmp,2'h0}; // @[Cat.scala 31:58]
   wire [33:0] _bytes_T_14 = _bytes_T_12 ? _bytes_T_13 : 34'h0; // @[Library.scala 8:8]
-  wire [33:0] _GEN_14 = {{1'd0}, _bytes_T_9}; // @[VInst.scala 178:65]
-  wire [33:0] _bytes_T_15 = _GEN_14 | _bytes_T_14; // @[VInst.scala 178:65]
-  wire  _bytes_T_17 = ~sl[0]; // @[VInst.scala 180:24]
-  wire  _bytes_T_19 = ~sl[0] & _max_T_1; // @[VInst.scala 180:31]
+  wire [33:0] _GEN_14 = {{1'd0}, _bytes_T_9}; // @[VInst.scala 173:65]
+  wire [33:0] _bytes_T_15 = _GEN_14 | _bytes_T_14; // @[VInst.scala 173:65]
+  wire  _bytes_T_17 = ~sl[0]; // @[VInst.scala 175:24]
+  wire  _bytes_T_19 = ~sl[0] & _max_T_1; // @[VInst.scala 175:31]
   wire [7:0] _bytes_T_20 = _bytes_T_19 ? 8'h20 : 8'h0; // @[Library.scala 8:8]
-  wire [33:0] _GEN_15 = {{26'd0}, _bytes_T_20}; // @[VInst.scala 179:65]
-  wire [33:0] _bytes_T_21 = _bytes_T_15 | _GEN_15; // @[VInst.scala 179:65]
-  wire  _bytes_T_24 = _bytes_T_17 & m; // @[VInst.scala 181:31]
+  wire [33:0] _GEN_15 = {{26'd0}, _bytes_T_20}; // @[VInst.scala 174:65]
+  wire [33:0] _bytes_T_21 = _bytes_T_15 | _GEN_15; // @[VInst.scala 174:65]
+  wire  _bytes_T_24 = _bytes_T_17 & m; // @[VInst.scala 176:31]
   wire [7:0] _bytes_T_25 = _bytes_T_24 ? 8'h80 : 8'h0; // @[Library.scala 8:8]
-  wire [33:0] _GEN_16 = {{26'd0}, _bytes_T_25}; // @[VInst.scala 180:46]
-  wire [33:0] _bytes_T_26 = _bytes_T_21 | _GEN_16; // @[VInst.scala 180:46]
-  wire [31:0] bytes = _bytes_T_26[31:0]; // @[VInst.scala 182:18]
+  wire [33:0] _GEN_16 = {{26'd0}, _bytes_T_25}; // @[VInst.scala 175:46]
+  wire [33:0] _bytes_T_26 = _bytes_T_21 | _GEN_16; // @[VInst.scala 175:46]
+  wire [31:0] bytes = _bytes_T_26[31:0]; // @[VInst.scala 177:18]
   wire [31:0] _rt_T_1 = _max_T ? io_rs_1_data : 32'h0; // @[Library.scala 8:8]
   wire [32:0] _rt_T_3 = {io_rs_1_data,1'h0}; // @[Cat.scala 31:58]
   wire [32:0] _rt_T_4 = _max_T_4 ? _rt_T_3 : 33'h0; // @[Library.scala 8:8]
-  wire [32:0] _GEN_17 = {{1'd0}, _rt_T_1}; // @[VInst.scala 185:38]
-  wire [32:0] _rt_T_5 = _GEN_17 | _rt_T_4; // @[VInst.scala 185:38]
+  wire [32:0] _GEN_17 = {{1'd0}, _rt_T_1}; // @[VInst.scala 180:38]
+  wire [32:0] _rt_T_5 = _GEN_17 | _rt_T_4; // @[VInst.scala 180:38]
   wire [33:0] _rt_T_7 = {io_rs_1_data,2'h0}; // @[Cat.scala 31:58]
   wire [33:0] _rt_T_8 = _max_T_9 ? _rt_T_7 : 34'h0; // @[Library.scala 8:8]
-  wire [33:0] _GEN_18 = {{1'd0}, _rt_T_5}; // @[VInst.scala 186:53]
-  wire [33:0] _rt_T_9 = _GEN_18 | _rt_T_8; // @[VInst.scala 186:53]
-  wire [31:0] rt = _rt_T_9[31:0]; // @[VInst.scala 188:15]
+  wire [33:0] _GEN_18 = {{1'd0}, _rt_T_5}; // @[VInst.scala 181:53]
+  wire [33:0] _rt_T_9 = _GEN_18 | _rt_T_8; // @[VInst.scala 181:53]
+  wire [31:0] rt = _rt_T_9[31:0]; // @[VInst.scala 183:15]
   wire [33:0] _rtm_T = {rt,2'h0}; // @[Cat.scala 31:58]
-  wire [31:0] rtm = _rtm_T[31:0]; // @[VInst.scala 190:34]
+  wire [31:0] rtm = _rtm_T[31:0]; // @[VInst.scala 185:34]
   wire [35:0] _rtq_T = {rt,4'h0}; // @[Cat.scala 31:58]
-  wire [31:0] rtq = _rtq_T[31:0]; // @[VInst.scala 191:34]
-  wire  _p_x_T = sl == 2'h0; // @[VInst.scala 193:20]
-  wire  p_x = sl == 2'h0 & xs2zero; // @[VInst.scala 193:28]
-  wire  p_xx = _p_x_T & ~xs2zero; // @[VInst.scala 194:28]
-  wire  lp_xx = sl == 2'h1; // @[VInst.scala 195:20]
-  wire  _sp_xx_T = sl == 2'h2; // @[VInst.scala 196:20]
-  wire  sp_xx = sl == 2'h2 & ~q_4; // @[VInst.scala 196:28]
-  wire  qp_xx = _sp_xx_T & q_4; // @[VInst.scala 197:28]
-  wire  tp_xx = sl == 2'h3; // @[VInst.scala 198:20]
+  wire [31:0] rtq = _rtq_T[31:0]; // @[VInst.scala 186:34]
+  wire  _p_x_T = sl == 2'h0; // @[VInst.scala 188:20]
+  wire  p_x = sl == 2'h0 & xs2zero; // @[VInst.scala 188:28]
+  wire  p_xx = _p_x_T & ~xs2zero; // @[VInst.scala 189:28]
+  wire  lp_xx = sl == 2'h1; // @[VInst.scala 190:20]
+  wire  _sp_xx_T = sl == 2'h2; // @[VInst.scala 191:20]
+  wire  sp_xx = sl == 2'h2 & ~q_4; // @[VInst.scala 191:28]
+  wire  qp_xx = _sp_xx_T & q_4; // @[VInst.scala 192:28]
+  wire  tp_xx = sl == 2'h3; // @[VInst.scala 193:20]
   wire [5:0] _T_4 = {p_x,p_xx,lp_xx,sp_xx,qp_xx,tp_xx}; // @[Cat.scala 31:58]
   wire [1:0] _T_11 = _T_4[1] + _T_4[2]; // @[Bitwise.scala 48:55]
   wire [1:0] _GEN_19 = {{1'd0}, _T_4[0]}; // @[Bitwise.scala 48:55]
@@ -33269,95 +23962,95 @@
   wire [1:0] _GEN_20 = {{1'd0}, _T_4[3]}; // @[Bitwise.scala 48:55]
   wire [2:0] _T_17 = _GEN_20 + _T_15; // @[Bitwise.scala 48:55]
   wire [2:0] _T_19 = _T_13[1:0] + _T_17[1:0]; // @[Bitwise.scala 48:55]
-  wire [7:0] _offset_T = m ? 8'h80 : 8'h20; // @[VInst.scala 201:34]
+  wire [7:0] _offset_T = m ? 8'h80 : 8'h20; // @[VInst.scala 196:34]
   wire [7:0] _offset_T_1 = p_x ? _offset_T : 8'h0; // @[Library.scala 8:8]
   wire [31:0] _offset_T_2 = p_xx ? rt : 32'h0; // @[Library.scala 8:8]
-  wire [31:0] _GEN_21 = {{24'd0}, _offset_T_1}; // @[VInst.scala 201:56]
-  wire [31:0] _offset_T_3 = _GEN_21 | _offset_T_2; // @[VInst.scala 201:56]
+  wire [31:0] _GEN_21 = {{24'd0}, _offset_T_1}; // @[VInst.scala 196:56]
+  wire [31:0] _offset_T_3 = _GEN_21 | _offset_T_2; // @[VInst.scala 196:56]
   wire [31:0] _offset_T_4 = lp_xx ? bytes : 32'h0; // @[Library.scala 8:8]
-  wire [31:0] _offset_T_5 = _offset_T_3 | _offset_T_4; // @[VInst.scala 202:35]
-  wire [31:0] _offset_T_6 = m ? rtm : rt; // @[VInst.scala 204:34]
+  wire [31:0] _offset_T_5 = _offset_T_3 | _offset_T_4; // @[VInst.scala 197:35]
+  wire [31:0] _offset_T_6 = m ? rtm : rt; // @[VInst.scala 199:34]
   wire [31:0] _offset_T_7 = sp_xx ? _offset_T_6 : 32'h0; // @[Library.scala 8:8]
-  wire [31:0] _offset_T_8 = _offset_T_5 | _offset_T_7; // @[VInst.scala 203:38]
+  wire [31:0] _offset_T_8 = _offset_T_5 | _offset_T_7; // @[VInst.scala 198:38]
   wire [7:0] _offset_T_9 = tp_xx ? 8'h20 : 8'h0; // @[Library.scala 8:8]
-  wire [31:0] _GEN_22 = {{24'd0}, _offset_T_9}; // @[VInst.scala 204:48]
-  wire [31:0] _offset_T_10 = _offset_T_8 | _GEN_22; // @[VInst.scala 204:48]
-  wire [31:0] _offset_T_11 = m ? rtq : rtm; // @[VInst.scala 206:34]
+  wire [31:0] _GEN_22 = {{24'd0}, _offset_T_9}; // @[VInst.scala 199:48]
+  wire [31:0] _offset_T_10 = _offset_T_8 | _GEN_22; // @[VInst.scala 199:48]
+  wire [31:0] _offset_T_11 = m ? rtq : rtm; // @[VInst.scala 201:34]
   wire [31:0] _offset_T_12 = qp_xx ? _offset_T_11 : 32'h0; // @[Library.scala 8:8]
-  wire [31:0] offset = _offset_T_10 | _offset_T_12; // @[VInst.scala 205:39]
-  wire [31:0] lsuAdder_0 = io_rs_0_data + offset; // @[VInst.scala 209:24]
-  wire  m_1 = vinstInst_1[5]; // @[VInst.scala 161:26]
-  wire [1:0] sz_1 = vinstInst_1[13:12]; // @[VInst.scala 162:26]
-  wire [1:0] sl_1 = vinstInst_1[27:26]; // @[VInst.scala 163:26]
-  wire  q_5 = vinstInst_1[30]; // @[VInst.scala 164:26]
-  wire  xs2zero_1 = vinstInst_1[24:20] == 5'h0; // @[VInst.scala 166:39]
-  wire  _max_T_25 = sz_1 == 2'h0; // @[VInst.scala 168:24]
-  wire  _max_T_26 = ~m_1; // @[VInst.scala 168:35]
-  wire  _max_T_27 = sz_1 == 2'h0 & ~m_1; // @[VInst.scala 168:32]
+  wire [31:0] offset = _offset_T_10 | _offset_T_12; // @[VInst.scala 200:39]
+  wire [31:0] lsuAdder_0 = io_rs_0_data + offset; // @[VInst.scala 204:24]
+  wire  m_1 = vinstInst_1[5]; // @[VInst.scala 156:26]
+  wire [1:0] sz_1 = vinstInst_1[13:12]; // @[VInst.scala 157:26]
+  wire [1:0] sl_1 = vinstInst_1[27:26]; // @[VInst.scala 158:26]
+  wire  q_5 = vinstInst_1[30]; // @[VInst.scala 159:26]
+  wire  xs2zero_1 = vinstInst_1[24:20] == 5'h0; // @[VInst.scala 161:39]
+  wire  _max_T_25 = sz_1 == 2'h0; // @[VInst.scala 163:24]
+  wire  _max_T_26 = ~m_1; // @[VInst.scala 163:35]
+  wire  _max_T_27 = sz_1 == 2'h0 & ~m_1; // @[VInst.scala 163:32]
   wire [7:0] _max_T_28 = _max_T_27 ? 8'h20 : 8'h0; // @[Library.scala 8:8]
-  wire  _max_T_29 = sz_1 == 2'h1; // @[VInst.scala 169:24]
-  wire  _max_T_31 = sz_1 == 2'h1 & _max_T_26; // @[VInst.scala 169:32]
+  wire  _max_T_29 = sz_1 == 2'h1; // @[VInst.scala 164:24]
+  wire  _max_T_31 = sz_1 == 2'h1 & _max_T_26; // @[VInst.scala 164:32]
   wire [7:0] _max_T_32 = _max_T_31 ? 8'h10 : 8'h0; // @[Library.scala 8:8]
-  wire [7:0] _max_T_33 = _max_T_28 | _max_T_32; // @[VInst.scala 168:47]
-  wire  _max_T_34 = sz_1 == 2'h2; // @[VInst.scala 170:24]
-  wire  _max_T_36 = sz_1 == 2'h2 & _max_T_26; // @[VInst.scala 170:32]
+  wire [7:0] _max_T_33 = _max_T_28 | _max_T_32; // @[VInst.scala 163:47]
+  wire  _max_T_34 = sz_1 == 2'h2; // @[VInst.scala 165:24]
+  wire  _max_T_36 = sz_1 == 2'h2 & _max_T_26; // @[VInst.scala 165:32]
   wire [7:0] _max_T_37 = _max_T_36 ? 8'h8 : 8'h0; // @[Library.scala 8:8]
-  wire [7:0] _max_T_38 = _max_T_33 | _max_T_37; // @[VInst.scala 169:47]
-  wire  _max_T_40 = _max_T_25 & m_1; // @[VInst.scala 171:32]
+  wire [7:0] _max_T_38 = _max_T_33 | _max_T_37; // @[VInst.scala 164:47]
+  wire  _max_T_40 = _max_T_25 & m_1; // @[VInst.scala 166:32]
   wire [7:0] _max_T_41 = _max_T_40 ? 8'h80 : 8'h0; // @[Library.scala 8:8]
-  wire [7:0] _max_T_42 = _max_T_38 | _max_T_41; // @[VInst.scala 170:47]
-  wire  _max_T_44 = _max_T_29 & m_1; // @[VInst.scala 172:32]
+  wire [7:0] _max_T_42 = _max_T_38 | _max_T_41; // @[VInst.scala 165:47]
+  wire  _max_T_44 = _max_T_29 & m_1; // @[VInst.scala 167:32]
   wire [7:0] _max_T_45 = _max_T_44 ? 8'h40 : 8'h0; // @[Library.scala 8:8]
-  wire [7:0] _max_T_46 = _max_T_42 | _max_T_45; // @[VInst.scala 171:47]
-  wire  _max_T_48 = _max_T_34 & m_1; // @[VInst.scala 173:32]
+  wire [7:0] _max_T_46 = _max_T_42 | _max_T_45; // @[VInst.scala 166:47]
+  wire  _max_T_48 = _max_T_34 & m_1; // @[VInst.scala 168:32]
   wire [7:0] _max_T_49 = _max_T_48 ? 8'h20 : 8'h0; // @[Library.scala 8:8]
-  wire [7:0] max_1 = _max_T_46 | _max_T_49; // @[VInst.scala 172:47]
-  wire [31:0] _GEN_23 = {{24'd0}, max_1}; // @[VInst.scala 175:25]
-  wire [31:0] cmp_1 = io_rs_3_data < _GEN_23 ? io_rs_3_data : {{24'd0}, max_1}; // @[VInst.scala 175:18]
-  wire  _bytes_T_29 = _max_T_25 & sl_1[0]; // @[VInst.scala 177:35]
+  wire [7:0] max_1 = _max_T_46 | _max_T_49; // @[VInst.scala 167:47]
+  wire [31:0] _GEN_23 = {{24'd0}, max_1}; // @[VInst.scala 170:25]
+  wire [31:0] cmp_1 = io_rs_3_data < _GEN_23 ? io_rs_3_data : {{24'd0}, max_1}; // @[VInst.scala 170:18]
+  wire  _bytes_T_29 = _max_T_25 & sl_1[0]; // @[VInst.scala 172:35]
   wire [31:0] _bytes_T_30 = _bytes_T_29 ? cmp_1 : 32'h0; // @[Library.scala 8:8]
-  wire  _bytes_T_33 = _max_T_29 & sl_1[0]; // @[VInst.scala 178:35]
+  wire  _bytes_T_33 = _max_T_29 & sl_1[0]; // @[VInst.scala 173:35]
   wire [32:0] _bytes_T_34 = {cmp_1,1'h0}; // @[Cat.scala 31:58]
   wire [32:0] _bytes_T_35 = _bytes_T_33 ? _bytes_T_34 : 33'h0; // @[Library.scala 8:8]
-  wire [32:0] _GEN_24 = {{1'd0}, _bytes_T_30}; // @[VInst.scala 177:50]
-  wire [32:0] _bytes_T_36 = _GEN_24 | _bytes_T_35; // @[VInst.scala 177:50]
-  wire  _bytes_T_39 = _max_T_34 & sl_1[0]; // @[VInst.scala 179:35]
+  wire [32:0] _GEN_24 = {{1'd0}, _bytes_T_30}; // @[VInst.scala 172:50]
+  wire [32:0] _bytes_T_36 = _GEN_24 | _bytes_T_35; // @[VInst.scala 172:50]
+  wire  _bytes_T_39 = _max_T_34 & sl_1[0]; // @[VInst.scala 174:35]
   wire [33:0] _bytes_T_40 = {cmp_1,2'h0}; // @[Cat.scala 31:58]
   wire [33:0] _bytes_T_41 = _bytes_T_39 ? _bytes_T_40 : 34'h0; // @[Library.scala 8:8]
-  wire [33:0] _GEN_25 = {{1'd0}, _bytes_T_36}; // @[VInst.scala 178:65]
-  wire [33:0] _bytes_T_42 = _GEN_25 | _bytes_T_41; // @[VInst.scala 178:65]
-  wire  _bytes_T_44 = ~sl_1[0]; // @[VInst.scala 180:24]
-  wire  _bytes_T_46 = ~sl_1[0] & _max_T_26; // @[VInst.scala 180:31]
+  wire [33:0] _GEN_25 = {{1'd0}, _bytes_T_36}; // @[VInst.scala 173:65]
+  wire [33:0] _bytes_T_42 = _GEN_25 | _bytes_T_41; // @[VInst.scala 173:65]
+  wire  _bytes_T_44 = ~sl_1[0]; // @[VInst.scala 175:24]
+  wire  _bytes_T_46 = ~sl_1[0] & _max_T_26; // @[VInst.scala 175:31]
   wire [7:0] _bytes_T_47 = _bytes_T_46 ? 8'h20 : 8'h0; // @[Library.scala 8:8]
-  wire [33:0] _GEN_26 = {{26'd0}, _bytes_T_47}; // @[VInst.scala 179:65]
-  wire [33:0] _bytes_T_48 = _bytes_T_42 | _GEN_26; // @[VInst.scala 179:65]
-  wire  _bytes_T_51 = _bytes_T_44 & m_1; // @[VInst.scala 181:31]
+  wire [33:0] _GEN_26 = {{26'd0}, _bytes_T_47}; // @[VInst.scala 174:65]
+  wire [33:0] _bytes_T_48 = _bytes_T_42 | _GEN_26; // @[VInst.scala 174:65]
+  wire  _bytes_T_51 = _bytes_T_44 & m_1; // @[VInst.scala 176:31]
   wire [7:0] _bytes_T_52 = _bytes_T_51 ? 8'h80 : 8'h0; // @[Library.scala 8:8]
-  wire [33:0] _GEN_27 = {{26'd0}, _bytes_T_52}; // @[VInst.scala 180:46]
-  wire [33:0] _bytes_T_53 = _bytes_T_48 | _GEN_27; // @[VInst.scala 180:46]
-  wire [31:0] bytes_1 = _bytes_T_53[31:0]; // @[VInst.scala 182:18]
+  wire [33:0] _GEN_27 = {{26'd0}, _bytes_T_52}; // @[VInst.scala 175:46]
+  wire [33:0] _bytes_T_53 = _bytes_T_48 | _GEN_27; // @[VInst.scala 175:46]
+  wire [31:0] bytes_1 = _bytes_T_53[31:0]; // @[VInst.scala 177:18]
   wire [31:0] _rt_T_11 = _max_T_25 ? io_rs_3_data : 32'h0; // @[Library.scala 8:8]
   wire [32:0] _rt_T_13 = {io_rs_3_data,1'h0}; // @[Cat.scala 31:58]
   wire [32:0] _rt_T_14 = _max_T_29 ? _rt_T_13 : 33'h0; // @[Library.scala 8:8]
-  wire [32:0] _GEN_28 = {{1'd0}, _rt_T_11}; // @[VInst.scala 185:38]
-  wire [32:0] _rt_T_15 = _GEN_28 | _rt_T_14; // @[VInst.scala 185:38]
+  wire [32:0] _GEN_28 = {{1'd0}, _rt_T_11}; // @[VInst.scala 180:38]
+  wire [32:0] _rt_T_15 = _GEN_28 | _rt_T_14; // @[VInst.scala 180:38]
   wire [33:0] _rt_T_17 = {io_rs_3_data,2'h0}; // @[Cat.scala 31:58]
   wire [33:0] _rt_T_18 = _max_T_34 ? _rt_T_17 : 34'h0; // @[Library.scala 8:8]
-  wire [33:0] _GEN_29 = {{1'd0}, _rt_T_15}; // @[VInst.scala 186:53]
-  wire [33:0] _rt_T_19 = _GEN_29 | _rt_T_18; // @[VInst.scala 186:53]
-  wire [31:0] rt_1 = _rt_T_19[31:0]; // @[VInst.scala 188:15]
+  wire [33:0] _GEN_29 = {{1'd0}, _rt_T_15}; // @[VInst.scala 181:53]
+  wire [33:0] _rt_T_19 = _GEN_29 | _rt_T_18; // @[VInst.scala 181:53]
+  wire [31:0] rt_1 = _rt_T_19[31:0]; // @[VInst.scala 183:15]
   wire [33:0] _rtm_T_1 = {rt_1,2'h0}; // @[Cat.scala 31:58]
-  wire [31:0] rtm_1 = _rtm_T_1[31:0]; // @[VInst.scala 190:34]
+  wire [31:0] rtm_1 = _rtm_T_1[31:0]; // @[VInst.scala 185:34]
   wire [35:0] _rtq_T_1 = {rt_1,4'h0}; // @[Cat.scala 31:58]
-  wire [31:0] rtq_1 = _rtq_T_1[31:0]; // @[VInst.scala 191:34]
-  wire  _p_x_T_1 = sl_1 == 2'h0; // @[VInst.scala 193:20]
-  wire  p_x_1 = sl_1 == 2'h0 & xs2zero_1; // @[VInst.scala 193:28]
-  wire  p_xx_1 = _p_x_T_1 & ~xs2zero_1; // @[VInst.scala 194:28]
-  wire  lp_xx_1 = sl_1 == 2'h1; // @[VInst.scala 195:20]
-  wire  _sp_xx_T_2 = sl_1 == 2'h2; // @[VInst.scala 196:20]
-  wire  sp_xx_1 = sl_1 == 2'h2 & ~q_5; // @[VInst.scala 196:28]
-  wire  qp_xx_1 = _sp_xx_T_2 & q_5; // @[VInst.scala 197:28]
-  wire  tp_xx_1 = sl_1 == 2'h3; // @[VInst.scala 198:20]
+  wire [31:0] rtq_1 = _rtq_T_1[31:0]; // @[VInst.scala 186:34]
+  wire  _p_x_T_1 = sl_1 == 2'h0; // @[VInst.scala 188:20]
+  wire  p_x_1 = sl_1 == 2'h0 & xs2zero_1; // @[VInst.scala 188:28]
+  wire  p_xx_1 = _p_x_T_1 & ~xs2zero_1; // @[VInst.scala 189:28]
+  wire  lp_xx_1 = sl_1 == 2'h1; // @[VInst.scala 190:20]
+  wire  _sp_xx_T_2 = sl_1 == 2'h2; // @[VInst.scala 191:20]
+  wire  sp_xx_1 = sl_1 == 2'h2 & ~q_5; // @[VInst.scala 191:28]
+  wire  qp_xx_1 = _sp_xx_T_2 & q_5; // @[VInst.scala 192:28]
+  wire  tp_xx_1 = sl_1 == 2'h3; // @[VInst.scala 193:20]
   wire [5:0] _T_25 = {p_x_1,p_xx_1,lp_xx_1,sp_xx_1,qp_xx_1,tp_xx_1}; // @[Cat.scala 31:58]
   wire [1:0] _T_32 = _T_25[1] + _T_25[2]; // @[Bitwise.scala 48:55]
   wire [1:0] _GEN_30 = {{1'd0}, _T_25[0]}; // @[Bitwise.scala 48:55]
@@ -33366,95 +24059,95 @@
   wire [1:0] _GEN_31 = {{1'd0}, _T_25[3]}; // @[Bitwise.scala 48:55]
   wire [2:0] _T_38 = _GEN_31 + _T_36; // @[Bitwise.scala 48:55]
   wire [2:0] _T_40 = _T_34[1:0] + _T_38[1:0]; // @[Bitwise.scala 48:55]
-  wire [7:0] _offset_T_13 = m_1 ? 8'h80 : 8'h20; // @[VInst.scala 201:34]
+  wire [7:0] _offset_T_13 = m_1 ? 8'h80 : 8'h20; // @[VInst.scala 196:34]
   wire [7:0] _offset_T_14 = p_x_1 ? _offset_T_13 : 8'h0; // @[Library.scala 8:8]
   wire [31:0] _offset_T_15 = p_xx_1 ? rt_1 : 32'h0; // @[Library.scala 8:8]
-  wire [31:0] _GEN_32 = {{24'd0}, _offset_T_14}; // @[VInst.scala 201:56]
-  wire [31:0] _offset_T_16 = _GEN_32 | _offset_T_15; // @[VInst.scala 201:56]
+  wire [31:0] _GEN_32 = {{24'd0}, _offset_T_14}; // @[VInst.scala 196:56]
+  wire [31:0] _offset_T_16 = _GEN_32 | _offset_T_15; // @[VInst.scala 196:56]
   wire [31:0] _offset_T_17 = lp_xx_1 ? bytes_1 : 32'h0; // @[Library.scala 8:8]
-  wire [31:0] _offset_T_18 = _offset_T_16 | _offset_T_17; // @[VInst.scala 202:35]
-  wire [31:0] _offset_T_19 = m_1 ? rtm_1 : rt_1; // @[VInst.scala 204:34]
+  wire [31:0] _offset_T_18 = _offset_T_16 | _offset_T_17; // @[VInst.scala 197:35]
+  wire [31:0] _offset_T_19 = m_1 ? rtm_1 : rt_1; // @[VInst.scala 199:34]
   wire [31:0] _offset_T_20 = sp_xx_1 ? _offset_T_19 : 32'h0; // @[Library.scala 8:8]
-  wire [31:0] _offset_T_21 = _offset_T_18 | _offset_T_20; // @[VInst.scala 203:38]
+  wire [31:0] _offset_T_21 = _offset_T_18 | _offset_T_20; // @[VInst.scala 198:38]
   wire [7:0] _offset_T_22 = tp_xx_1 ? 8'h20 : 8'h0; // @[Library.scala 8:8]
-  wire [31:0] _GEN_33 = {{24'd0}, _offset_T_22}; // @[VInst.scala 204:48]
-  wire [31:0] _offset_T_23 = _offset_T_21 | _GEN_33; // @[VInst.scala 204:48]
-  wire [31:0] _offset_T_24 = m_1 ? rtq_1 : rtm_1; // @[VInst.scala 206:34]
+  wire [31:0] _GEN_33 = {{24'd0}, _offset_T_22}; // @[VInst.scala 199:48]
+  wire [31:0] _offset_T_23 = _offset_T_21 | _GEN_33; // @[VInst.scala 199:48]
+  wire [31:0] _offset_T_24 = m_1 ? rtq_1 : rtm_1; // @[VInst.scala 201:34]
   wire [31:0] _offset_T_25 = qp_xx_1 ? _offset_T_24 : 32'h0; // @[Library.scala 8:8]
-  wire [31:0] offset_1 = _offset_T_23 | _offset_T_25; // @[VInst.scala 205:39]
-  wire [31:0] lsuAdder_1 = io_rs_2_data + offset_1; // @[VInst.scala 209:24]
-  wire  m_2 = vinstInst_2[5]; // @[VInst.scala 161:26]
-  wire [1:0] sz_2 = vinstInst_2[13:12]; // @[VInst.scala 162:26]
-  wire [1:0] sl_2 = vinstInst_2[27:26]; // @[VInst.scala 163:26]
-  wire  q_6 = vinstInst_2[30]; // @[VInst.scala 164:26]
-  wire  xs2zero_2 = vinstInst_2[24:20] == 5'h0; // @[VInst.scala 166:39]
-  wire  _max_T_50 = sz_2 == 2'h0; // @[VInst.scala 168:24]
-  wire  _max_T_51 = ~m_2; // @[VInst.scala 168:35]
-  wire  _max_T_52 = sz_2 == 2'h0 & ~m_2; // @[VInst.scala 168:32]
+  wire [31:0] offset_1 = _offset_T_23 | _offset_T_25; // @[VInst.scala 200:39]
+  wire [31:0] lsuAdder_1 = io_rs_2_data + offset_1; // @[VInst.scala 204:24]
+  wire  m_2 = vinstInst_2[5]; // @[VInst.scala 156:26]
+  wire [1:0] sz_2 = vinstInst_2[13:12]; // @[VInst.scala 157:26]
+  wire [1:0] sl_2 = vinstInst_2[27:26]; // @[VInst.scala 158:26]
+  wire  q_6 = vinstInst_2[30]; // @[VInst.scala 159:26]
+  wire  xs2zero_2 = vinstInst_2[24:20] == 5'h0; // @[VInst.scala 161:39]
+  wire  _max_T_50 = sz_2 == 2'h0; // @[VInst.scala 163:24]
+  wire  _max_T_51 = ~m_2; // @[VInst.scala 163:35]
+  wire  _max_T_52 = sz_2 == 2'h0 & ~m_2; // @[VInst.scala 163:32]
   wire [7:0] _max_T_53 = _max_T_52 ? 8'h20 : 8'h0; // @[Library.scala 8:8]
-  wire  _max_T_54 = sz_2 == 2'h1; // @[VInst.scala 169:24]
-  wire  _max_T_56 = sz_2 == 2'h1 & _max_T_51; // @[VInst.scala 169:32]
+  wire  _max_T_54 = sz_2 == 2'h1; // @[VInst.scala 164:24]
+  wire  _max_T_56 = sz_2 == 2'h1 & _max_T_51; // @[VInst.scala 164:32]
   wire [7:0] _max_T_57 = _max_T_56 ? 8'h10 : 8'h0; // @[Library.scala 8:8]
-  wire [7:0] _max_T_58 = _max_T_53 | _max_T_57; // @[VInst.scala 168:47]
-  wire  _max_T_59 = sz_2 == 2'h2; // @[VInst.scala 170:24]
-  wire  _max_T_61 = sz_2 == 2'h2 & _max_T_51; // @[VInst.scala 170:32]
+  wire [7:0] _max_T_58 = _max_T_53 | _max_T_57; // @[VInst.scala 163:47]
+  wire  _max_T_59 = sz_2 == 2'h2; // @[VInst.scala 165:24]
+  wire  _max_T_61 = sz_2 == 2'h2 & _max_T_51; // @[VInst.scala 165:32]
   wire [7:0] _max_T_62 = _max_T_61 ? 8'h8 : 8'h0; // @[Library.scala 8:8]
-  wire [7:0] _max_T_63 = _max_T_58 | _max_T_62; // @[VInst.scala 169:47]
-  wire  _max_T_65 = _max_T_50 & m_2; // @[VInst.scala 171:32]
+  wire [7:0] _max_T_63 = _max_T_58 | _max_T_62; // @[VInst.scala 164:47]
+  wire  _max_T_65 = _max_T_50 & m_2; // @[VInst.scala 166:32]
   wire [7:0] _max_T_66 = _max_T_65 ? 8'h80 : 8'h0; // @[Library.scala 8:8]
-  wire [7:0] _max_T_67 = _max_T_63 | _max_T_66; // @[VInst.scala 170:47]
-  wire  _max_T_69 = _max_T_54 & m_2; // @[VInst.scala 172:32]
+  wire [7:0] _max_T_67 = _max_T_63 | _max_T_66; // @[VInst.scala 165:47]
+  wire  _max_T_69 = _max_T_54 & m_2; // @[VInst.scala 167:32]
   wire [7:0] _max_T_70 = _max_T_69 ? 8'h40 : 8'h0; // @[Library.scala 8:8]
-  wire [7:0] _max_T_71 = _max_T_67 | _max_T_70; // @[VInst.scala 171:47]
-  wire  _max_T_73 = _max_T_59 & m_2; // @[VInst.scala 173:32]
+  wire [7:0] _max_T_71 = _max_T_67 | _max_T_70; // @[VInst.scala 166:47]
+  wire  _max_T_73 = _max_T_59 & m_2; // @[VInst.scala 168:32]
   wire [7:0] _max_T_74 = _max_T_73 ? 8'h20 : 8'h0; // @[Library.scala 8:8]
-  wire [7:0] max_2 = _max_T_71 | _max_T_74; // @[VInst.scala 172:47]
-  wire [31:0] _GEN_34 = {{24'd0}, max_2}; // @[VInst.scala 175:25]
-  wire [31:0] cmp_2 = io_rs_5_data < _GEN_34 ? io_rs_5_data : {{24'd0}, max_2}; // @[VInst.scala 175:18]
-  wire  _bytes_T_56 = _max_T_50 & sl_2[0]; // @[VInst.scala 177:35]
+  wire [7:0] max_2 = _max_T_71 | _max_T_74; // @[VInst.scala 167:47]
+  wire [31:0] _GEN_34 = {{24'd0}, max_2}; // @[VInst.scala 170:25]
+  wire [31:0] cmp_2 = io_rs_5_data < _GEN_34 ? io_rs_5_data : {{24'd0}, max_2}; // @[VInst.scala 170:18]
+  wire  _bytes_T_56 = _max_T_50 & sl_2[0]; // @[VInst.scala 172:35]
   wire [31:0] _bytes_T_57 = _bytes_T_56 ? cmp_2 : 32'h0; // @[Library.scala 8:8]
-  wire  _bytes_T_60 = _max_T_54 & sl_2[0]; // @[VInst.scala 178:35]
+  wire  _bytes_T_60 = _max_T_54 & sl_2[0]; // @[VInst.scala 173:35]
   wire [32:0] _bytes_T_61 = {cmp_2,1'h0}; // @[Cat.scala 31:58]
   wire [32:0] _bytes_T_62 = _bytes_T_60 ? _bytes_T_61 : 33'h0; // @[Library.scala 8:8]
-  wire [32:0] _GEN_35 = {{1'd0}, _bytes_T_57}; // @[VInst.scala 177:50]
-  wire [32:0] _bytes_T_63 = _GEN_35 | _bytes_T_62; // @[VInst.scala 177:50]
-  wire  _bytes_T_66 = _max_T_59 & sl_2[0]; // @[VInst.scala 179:35]
+  wire [32:0] _GEN_35 = {{1'd0}, _bytes_T_57}; // @[VInst.scala 172:50]
+  wire [32:0] _bytes_T_63 = _GEN_35 | _bytes_T_62; // @[VInst.scala 172:50]
+  wire  _bytes_T_66 = _max_T_59 & sl_2[0]; // @[VInst.scala 174:35]
   wire [33:0] _bytes_T_67 = {cmp_2,2'h0}; // @[Cat.scala 31:58]
   wire [33:0] _bytes_T_68 = _bytes_T_66 ? _bytes_T_67 : 34'h0; // @[Library.scala 8:8]
-  wire [33:0] _GEN_36 = {{1'd0}, _bytes_T_63}; // @[VInst.scala 178:65]
-  wire [33:0] _bytes_T_69 = _GEN_36 | _bytes_T_68; // @[VInst.scala 178:65]
-  wire  _bytes_T_71 = ~sl_2[0]; // @[VInst.scala 180:24]
-  wire  _bytes_T_73 = ~sl_2[0] & _max_T_51; // @[VInst.scala 180:31]
+  wire [33:0] _GEN_36 = {{1'd0}, _bytes_T_63}; // @[VInst.scala 173:65]
+  wire [33:0] _bytes_T_69 = _GEN_36 | _bytes_T_68; // @[VInst.scala 173:65]
+  wire  _bytes_T_71 = ~sl_2[0]; // @[VInst.scala 175:24]
+  wire  _bytes_T_73 = ~sl_2[0] & _max_T_51; // @[VInst.scala 175:31]
   wire [7:0] _bytes_T_74 = _bytes_T_73 ? 8'h20 : 8'h0; // @[Library.scala 8:8]
-  wire [33:0] _GEN_37 = {{26'd0}, _bytes_T_74}; // @[VInst.scala 179:65]
-  wire [33:0] _bytes_T_75 = _bytes_T_69 | _GEN_37; // @[VInst.scala 179:65]
-  wire  _bytes_T_78 = _bytes_T_71 & m_2; // @[VInst.scala 181:31]
+  wire [33:0] _GEN_37 = {{26'd0}, _bytes_T_74}; // @[VInst.scala 174:65]
+  wire [33:0] _bytes_T_75 = _bytes_T_69 | _GEN_37; // @[VInst.scala 174:65]
+  wire  _bytes_T_78 = _bytes_T_71 & m_2; // @[VInst.scala 176:31]
   wire [7:0] _bytes_T_79 = _bytes_T_78 ? 8'h80 : 8'h0; // @[Library.scala 8:8]
-  wire [33:0] _GEN_38 = {{26'd0}, _bytes_T_79}; // @[VInst.scala 180:46]
-  wire [33:0] _bytes_T_80 = _bytes_T_75 | _GEN_38; // @[VInst.scala 180:46]
-  wire [31:0] bytes_2 = _bytes_T_80[31:0]; // @[VInst.scala 182:18]
+  wire [33:0] _GEN_38 = {{26'd0}, _bytes_T_79}; // @[VInst.scala 175:46]
+  wire [33:0] _bytes_T_80 = _bytes_T_75 | _GEN_38; // @[VInst.scala 175:46]
+  wire [31:0] bytes_2 = _bytes_T_80[31:0]; // @[VInst.scala 177:18]
   wire [31:0] _rt_T_21 = _max_T_50 ? io_rs_5_data : 32'h0; // @[Library.scala 8:8]
   wire [32:0] _rt_T_23 = {io_rs_5_data,1'h0}; // @[Cat.scala 31:58]
   wire [32:0] _rt_T_24 = _max_T_54 ? _rt_T_23 : 33'h0; // @[Library.scala 8:8]
-  wire [32:0] _GEN_39 = {{1'd0}, _rt_T_21}; // @[VInst.scala 185:38]
-  wire [32:0] _rt_T_25 = _GEN_39 | _rt_T_24; // @[VInst.scala 185:38]
+  wire [32:0] _GEN_39 = {{1'd0}, _rt_T_21}; // @[VInst.scala 180:38]
+  wire [32:0] _rt_T_25 = _GEN_39 | _rt_T_24; // @[VInst.scala 180:38]
   wire [33:0] _rt_T_27 = {io_rs_5_data,2'h0}; // @[Cat.scala 31:58]
   wire [33:0] _rt_T_28 = _max_T_59 ? _rt_T_27 : 34'h0; // @[Library.scala 8:8]
-  wire [33:0] _GEN_40 = {{1'd0}, _rt_T_25}; // @[VInst.scala 186:53]
-  wire [33:0] _rt_T_29 = _GEN_40 | _rt_T_28; // @[VInst.scala 186:53]
-  wire [31:0] rt_2 = _rt_T_29[31:0]; // @[VInst.scala 188:15]
+  wire [33:0] _GEN_40 = {{1'd0}, _rt_T_25}; // @[VInst.scala 181:53]
+  wire [33:0] _rt_T_29 = _GEN_40 | _rt_T_28; // @[VInst.scala 181:53]
+  wire [31:0] rt_2 = _rt_T_29[31:0]; // @[VInst.scala 183:15]
   wire [33:0] _rtm_T_2 = {rt_2,2'h0}; // @[Cat.scala 31:58]
-  wire [31:0] rtm_2 = _rtm_T_2[31:0]; // @[VInst.scala 190:34]
+  wire [31:0] rtm_2 = _rtm_T_2[31:0]; // @[VInst.scala 185:34]
   wire [35:0] _rtq_T_2 = {rt_2,4'h0}; // @[Cat.scala 31:58]
-  wire [31:0] rtq_2 = _rtq_T_2[31:0]; // @[VInst.scala 191:34]
-  wire  _p_x_T_2 = sl_2 == 2'h0; // @[VInst.scala 193:20]
-  wire  p_x_2 = sl_2 == 2'h0 & xs2zero_2; // @[VInst.scala 193:28]
-  wire  p_xx_2 = _p_x_T_2 & ~xs2zero_2; // @[VInst.scala 194:28]
-  wire  lp_xx_2 = sl_2 == 2'h1; // @[VInst.scala 195:20]
-  wire  _sp_xx_T_4 = sl_2 == 2'h2; // @[VInst.scala 196:20]
-  wire  sp_xx_2 = sl_2 == 2'h2 & ~q_6; // @[VInst.scala 196:28]
-  wire  qp_xx_2 = _sp_xx_T_4 & q_6; // @[VInst.scala 197:28]
-  wire  tp_xx_2 = sl_2 == 2'h3; // @[VInst.scala 198:20]
+  wire [31:0] rtq_2 = _rtq_T_2[31:0]; // @[VInst.scala 186:34]
+  wire  _p_x_T_2 = sl_2 == 2'h0; // @[VInst.scala 188:20]
+  wire  p_x_2 = sl_2 == 2'h0 & xs2zero_2; // @[VInst.scala 188:28]
+  wire  p_xx_2 = _p_x_T_2 & ~xs2zero_2; // @[VInst.scala 189:28]
+  wire  lp_xx_2 = sl_2 == 2'h1; // @[VInst.scala 190:20]
+  wire  _sp_xx_T_4 = sl_2 == 2'h2; // @[VInst.scala 191:20]
+  wire  sp_xx_2 = sl_2 == 2'h2 & ~q_6; // @[VInst.scala 191:28]
+  wire  qp_xx_2 = _sp_xx_T_4 & q_6; // @[VInst.scala 192:28]
+  wire  tp_xx_2 = sl_2 == 2'h3; // @[VInst.scala 193:20]
   wire [5:0] _T_46 = {p_x_2,p_xx_2,lp_xx_2,sp_xx_2,qp_xx_2,tp_xx_2}; // @[Cat.scala 31:58]
   wire [1:0] _T_53 = _T_46[1] + _T_46[2]; // @[Bitwise.scala 48:55]
   wire [1:0] _GEN_41 = {{1'd0}, _T_46[0]}; // @[Bitwise.scala 48:55]
@@ -33463,95 +24156,95 @@
   wire [1:0] _GEN_42 = {{1'd0}, _T_46[3]}; // @[Bitwise.scala 48:55]
   wire [2:0] _T_59 = _GEN_42 + _T_57; // @[Bitwise.scala 48:55]
   wire [2:0] _T_61 = _T_55[1:0] + _T_59[1:0]; // @[Bitwise.scala 48:55]
-  wire [7:0] _offset_T_26 = m_2 ? 8'h80 : 8'h20; // @[VInst.scala 201:34]
+  wire [7:0] _offset_T_26 = m_2 ? 8'h80 : 8'h20; // @[VInst.scala 196:34]
   wire [7:0] _offset_T_27 = p_x_2 ? _offset_T_26 : 8'h0; // @[Library.scala 8:8]
   wire [31:0] _offset_T_28 = p_xx_2 ? rt_2 : 32'h0; // @[Library.scala 8:8]
-  wire [31:0] _GEN_43 = {{24'd0}, _offset_T_27}; // @[VInst.scala 201:56]
-  wire [31:0] _offset_T_29 = _GEN_43 | _offset_T_28; // @[VInst.scala 201:56]
+  wire [31:0] _GEN_43 = {{24'd0}, _offset_T_27}; // @[VInst.scala 196:56]
+  wire [31:0] _offset_T_29 = _GEN_43 | _offset_T_28; // @[VInst.scala 196:56]
   wire [31:0] _offset_T_30 = lp_xx_2 ? bytes_2 : 32'h0; // @[Library.scala 8:8]
-  wire [31:0] _offset_T_31 = _offset_T_29 | _offset_T_30; // @[VInst.scala 202:35]
-  wire [31:0] _offset_T_32 = m_2 ? rtm_2 : rt_2; // @[VInst.scala 204:34]
+  wire [31:0] _offset_T_31 = _offset_T_29 | _offset_T_30; // @[VInst.scala 197:35]
+  wire [31:0] _offset_T_32 = m_2 ? rtm_2 : rt_2; // @[VInst.scala 199:34]
   wire [31:0] _offset_T_33 = sp_xx_2 ? _offset_T_32 : 32'h0; // @[Library.scala 8:8]
-  wire [31:0] _offset_T_34 = _offset_T_31 | _offset_T_33; // @[VInst.scala 203:38]
+  wire [31:0] _offset_T_34 = _offset_T_31 | _offset_T_33; // @[VInst.scala 198:38]
   wire [7:0] _offset_T_35 = tp_xx_2 ? 8'h20 : 8'h0; // @[Library.scala 8:8]
-  wire [31:0] _GEN_44 = {{24'd0}, _offset_T_35}; // @[VInst.scala 204:48]
-  wire [31:0] _offset_T_36 = _offset_T_34 | _GEN_44; // @[VInst.scala 204:48]
-  wire [31:0] _offset_T_37 = m_2 ? rtq_2 : rtm_2; // @[VInst.scala 206:34]
+  wire [31:0] _GEN_44 = {{24'd0}, _offset_T_35}; // @[VInst.scala 199:48]
+  wire [31:0] _offset_T_36 = _offset_T_34 | _GEN_44; // @[VInst.scala 199:48]
+  wire [31:0] _offset_T_37 = m_2 ? rtq_2 : rtm_2; // @[VInst.scala 201:34]
   wire [31:0] _offset_T_38 = qp_xx_2 ? _offset_T_37 : 32'h0; // @[Library.scala 8:8]
-  wire [31:0] offset_2 = _offset_T_36 | _offset_T_38; // @[VInst.scala 205:39]
-  wire [31:0] lsuAdder_2 = io_rs_4_data + offset_2; // @[VInst.scala 209:24]
-  wire  m_3 = vinstInst_3[5]; // @[VInst.scala 161:26]
-  wire [1:0] sz_3 = vinstInst_3[13:12]; // @[VInst.scala 162:26]
-  wire [1:0] sl_3 = vinstInst_3[27:26]; // @[VInst.scala 163:26]
-  wire  q_7 = vinstInst_3[30]; // @[VInst.scala 164:26]
-  wire  xs2zero_3 = vinstInst_3[24:20] == 5'h0; // @[VInst.scala 166:39]
-  wire  _max_T_75 = sz_3 == 2'h0; // @[VInst.scala 168:24]
-  wire  _max_T_76 = ~m_3; // @[VInst.scala 168:35]
-  wire  _max_T_77 = sz_3 == 2'h0 & ~m_3; // @[VInst.scala 168:32]
+  wire [31:0] offset_2 = _offset_T_36 | _offset_T_38; // @[VInst.scala 200:39]
+  wire [31:0] lsuAdder_2 = io_rs_4_data + offset_2; // @[VInst.scala 204:24]
+  wire  m_3 = vinstInst_3[5]; // @[VInst.scala 156:26]
+  wire [1:0] sz_3 = vinstInst_3[13:12]; // @[VInst.scala 157:26]
+  wire [1:0] sl_3 = vinstInst_3[27:26]; // @[VInst.scala 158:26]
+  wire  q_7 = vinstInst_3[30]; // @[VInst.scala 159:26]
+  wire  xs2zero_3 = vinstInst_3[24:20] == 5'h0; // @[VInst.scala 161:39]
+  wire  _max_T_75 = sz_3 == 2'h0; // @[VInst.scala 163:24]
+  wire  _max_T_76 = ~m_3; // @[VInst.scala 163:35]
+  wire  _max_T_77 = sz_3 == 2'h0 & ~m_3; // @[VInst.scala 163:32]
   wire [7:0] _max_T_78 = _max_T_77 ? 8'h20 : 8'h0; // @[Library.scala 8:8]
-  wire  _max_T_79 = sz_3 == 2'h1; // @[VInst.scala 169:24]
-  wire  _max_T_81 = sz_3 == 2'h1 & _max_T_76; // @[VInst.scala 169:32]
+  wire  _max_T_79 = sz_3 == 2'h1; // @[VInst.scala 164:24]
+  wire  _max_T_81 = sz_3 == 2'h1 & _max_T_76; // @[VInst.scala 164:32]
   wire [7:0] _max_T_82 = _max_T_81 ? 8'h10 : 8'h0; // @[Library.scala 8:8]
-  wire [7:0] _max_T_83 = _max_T_78 | _max_T_82; // @[VInst.scala 168:47]
-  wire  _max_T_84 = sz_3 == 2'h2; // @[VInst.scala 170:24]
-  wire  _max_T_86 = sz_3 == 2'h2 & _max_T_76; // @[VInst.scala 170:32]
+  wire [7:0] _max_T_83 = _max_T_78 | _max_T_82; // @[VInst.scala 163:47]
+  wire  _max_T_84 = sz_3 == 2'h2; // @[VInst.scala 165:24]
+  wire  _max_T_86 = sz_3 == 2'h2 & _max_T_76; // @[VInst.scala 165:32]
   wire [7:0] _max_T_87 = _max_T_86 ? 8'h8 : 8'h0; // @[Library.scala 8:8]
-  wire [7:0] _max_T_88 = _max_T_83 | _max_T_87; // @[VInst.scala 169:47]
-  wire  _max_T_90 = _max_T_75 & m_3; // @[VInst.scala 171:32]
+  wire [7:0] _max_T_88 = _max_T_83 | _max_T_87; // @[VInst.scala 164:47]
+  wire  _max_T_90 = _max_T_75 & m_3; // @[VInst.scala 166:32]
   wire [7:0] _max_T_91 = _max_T_90 ? 8'h80 : 8'h0; // @[Library.scala 8:8]
-  wire [7:0] _max_T_92 = _max_T_88 | _max_T_91; // @[VInst.scala 170:47]
-  wire  _max_T_94 = _max_T_79 & m_3; // @[VInst.scala 172:32]
+  wire [7:0] _max_T_92 = _max_T_88 | _max_T_91; // @[VInst.scala 165:47]
+  wire  _max_T_94 = _max_T_79 & m_3; // @[VInst.scala 167:32]
   wire [7:0] _max_T_95 = _max_T_94 ? 8'h40 : 8'h0; // @[Library.scala 8:8]
-  wire [7:0] _max_T_96 = _max_T_92 | _max_T_95; // @[VInst.scala 171:47]
-  wire  _max_T_98 = _max_T_84 & m_3; // @[VInst.scala 173:32]
+  wire [7:0] _max_T_96 = _max_T_92 | _max_T_95; // @[VInst.scala 166:47]
+  wire  _max_T_98 = _max_T_84 & m_3; // @[VInst.scala 168:32]
   wire [7:0] _max_T_99 = _max_T_98 ? 8'h20 : 8'h0; // @[Library.scala 8:8]
-  wire [7:0] max_3 = _max_T_96 | _max_T_99; // @[VInst.scala 172:47]
-  wire [31:0] _GEN_45 = {{24'd0}, max_3}; // @[VInst.scala 175:25]
-  wire [31:0] cmp_3 = io_rs_7_data < _GEN_45 ? io_rs_7_data : {{24'd0}, max_3}; // @[VInst.scala 175:18]
-  wire  _bytes_T_83 = _max_T_75 & sl_3[0]; // @[VInst.scala 177:35]
+  wire [7:0] max_3 = _max_T_96 | _max_T_99; // @[VInst.scala 167:47]
+  wire [31:0] _GEN_45 = {{24'd0}, max_3}; // @[VInst.scala 170:25]
+  wire [31:0] cmp_3 = io_rs_7_data < _GEN_45 ? io_rs_7_data : {{24'd0}, max_3}; // @[VInst.scala 170:18]
+  wire  _bytes_T_83 = _max_T_75 & sl_3[0]; // @[VInst.scala 172:35]
   wire [31:0] _bytes_T_84 = _bytes_T_83 ? cmp_3 : 32'h0; // @[Library.scala 8:8]
-  wire  _bytes_T_87 = _max_T_79 & sl_3[0]; // @[VInst.scala 178:35]
+  wire  _bytes_T_87 = _max_T_79 & sl_3[0]; // @[VInst.scala 173:35]
   wire [32:0] _bytes_T_88 = {cmp_3,1'h0}; // @[Cat.scala 31:58]
   wire [32:0] _bytes_T_89 = _bytes_T_87 ? _bytes_T_88 : 33'h0; // @[Library.scala 8:8]
-  wire [32:0] _GEN_46 = {{1'd0}, _bytes_T_84}; // @[VInst.scala 177:50]
-  wire [32:0] _bytes_T_90 = _GEN_46 | _bytes_T_89; // @[VInst.scala 177:50]
-  wire  _bytes_T_93 = _max_T_84 & sl_3[0]; // @[VInst.scala 179:35]
+  wire [32:0] _GEN_46 = {{1'd0}, _bytes_T_84}; // @[VInst.scala 172:50]
+  wire [32:0] _bytes_T_90 = _GEN_46 | _bytes_T_89; // @[VInst.scala 172:50]
+  wire  _bytes_T_93 = _max_T_84 & sl_3[0]; // @[VInst.scala 174:35]
   wire [33:0] _bytes_T_94 = {cmp_3,2'h0}; // @[Cat.scala 31:58]
   wire [33:0] _bytes_T_95 = _bytes_T_93 ? _bytes_T_94 : 34'h0; // @[Library.scala 8:8]
-  wire [33:0] _GEN_47 = {{1'd0}, _bytes_T_90}; // @[VInst.scala 178:65]
-  wire [33:0] _bytes_T_96 = _GEN_47 | _bytes_T_95; // @[VInst.scala 178:65]
-  wire  _bytes_T_98 = ~sl_3[0]; // @[VInst.scala 180:24]
-  wire  _bytes_T_100 = ~sl_3[0] & _max_T_76; // @[VInst.scala 180:31]
+  wire [33:0] _GEN_47 = {{1'd0}, _bytes_T_90}; // @[VInst.scala 173:65]
+  wire [33:0] _bytes_T_96 = _GEN_47 | _bytes_T_95; // @[VInst.scala 173:65]
+  wire  _bytes_T_98 = ~sl_3[0]; // @[VInst.scala 175:24]
+  wire  _bytes_T_100 = ~sl_3[0] & _max_T_76; // @[VInst.scala 175:31]
   wire [7:0] _bytes_T_101 = _bytes_T_100 ? 8'h20 : 8'h0; // @[Library.scala 8:8]
-  wire [33:0] _GEN_48 = {{26'd0}, _bytes_T_101}; // @[VInst.scala 179:65]
-  wire [33:0] _bytes_T_102 = _bytes_T_96 | _GEN_48; // @[VInst.scala 179:65]
-  wire  _bytes_T_105 = _bytes_T_98 & m_3; // @[VInst.scala 181:31]
+  wire [33:0] _GEN_48 = {{26'd0}, _bytes_T_101}; // @[VInst.scala 174:65]
+  wire [33:0] _bytes_T_102 = _bytes_T_96 | _GEN_48; // @[VInst.scala 174:65]
+  wire  _bytes_T_105 = _bytes_T_98 & m_3; // @[VInst.scala 176:31]
   wire [7:0] _bytes_T_106 = _bytes_T_105 ? 8'h80 : 8'h0; // @[Library.scala 8:8]
-  wire [33:0] _GEN_49 = {{26'd0}, _bytes_T_106}; // @[VInst.scala 180:46]
-  wire [33:0] _bytes_T_107 = _bytes_T_102 | _GEN_49; // @[VInst.scala 180:46]
-  wire [31:0] bytes_3 = _bytes_T_107[31:0]; // @[VInst.scala 182:18]
+  wire [33:0] _GEN_49 = {{26'd0}, _bytes_T_106}; // @[VInst.scala 175:46]
+  wire [33:0] _bytes_T_107 = _bytes_T_102 | _GEN_49; // @[VInst.scala 175:46]
+  wire [31:0] bytes_3 = _bytes_T_107[31:0]; // @[VInst.scala 177:18]
   wire [31:0] _rt_T_31 = _max_T_75 ? io_rs_7_data : 32'h0; // @[Library.scala 8:8]
   wire [32:0] _rt_T_33 = {io_rs_7_data,1'h0}; // @[Cat.scala 31:58]
   wire [32:0] _rt_T_34 = _max_T_79 ? _rt_T_33 : 33'h0; // @[Library.scala 8:8]
-  wire [32:0] _GEN_50 = {{1'd0}, _rt_T_31}; // @[VInst.scala 185:38]
-  wire [32:0] _rt_T_35 = _GEN_50 | _rt_T_34; // @[VInst.scala 185:38]
+  wire [32:0] _GEN_50 = {{1'd0}, _rt_T_31}; // @[VInst.scala 180:38]
+  wire [32:0] _rt_T_35 = _GEN_50 | _rt_T_34; // @[VInst.scala 180:38]
   wire [33:0] _rt_T_37 = {io_rs_7_data,2'h0}; // @[Cat.scala 31:58]
   wire [33:0] _rt_T_38 = _max_T_84 ? _rt_T_37 : 34'h0; // @[Library.scala 8:8]
-  wire [33:0] _GEN_51 = {{1'd0}, _rt_T_35}; // @[VInst.scala 186:53]
-  wire [33:0] _rt_T_39 = _GEN_51 | _rt_T_38; // @[VInst.scala 186:53]
-  wire [31:0] rt_3 = _rt_T_39[31:0]; // @[VInst.scala 188:15]
+  wire [33:0] _GEN_51 = {{1'd0}, _rt_T_35}; // @[VInst.scala 181:53]
+  wire [33:0] _rt_T_39 = _GEN_51 | _rt_T_38; // @[VInst.scala 181:53]
+  wire [31:0] rt_3 = _rt_T_39[31:0]; // @[VInst.scala 183:15]
   wire [33:0] _rtm_T_3 = {rt_3,2'h0}; // @[Cat.scala 31:58]
-  wire [31:0] rtm_3 = _rtm_T_3[31:0]; // @[VInst.scala 190:34]
+  wire [31:0] rtm_3 = _rtm_T_3[31:0]; // @[VInst.scala 185:34]
   wire [35:0] _rtq_T_3 = {rt_3,4'h0}; // @[Cat.scala 31:58]
-  wire [31:0] rtq_3 = _rtq_T_3[31:0]; // @[VInst.scala 191:34]
-  wire  _p_x_T_3 = sl_3 == 2'h0; // @[VInst.scala 193:20]
-  wire  p_x_3 = sl_3 == 2'h0 & xs2zero_3; // @[VInst.scala 193:28]
-  wire  p_xx_3 = _p_x_T_3 & ~xs2zero_3; // @[VInst.scala 194:28]
-  wire  lp_xx_3 = sl_3 == 2'h1; // @[VInst.scala 195:20]
-  wire  _sp_xx_T_6 = sl_3 == 2'h2; // @[VInst.scala 196:20]
-  wire  sp_xx_3 = sl_3 == 2'h2 & ~q_7; // @[VInst.scala 196:28]
-  wire  qp_xx_3 = _sp_xx_T_6 & q_7; // @[VInst.scala 197:28]
-  wire  tp_xx_3 = sl_3 == 2'h3; // @[VInst.scala 198:20]
+  wire [31:0] rtq_3 = _rtq_T_3[31:0]; // @[VInst.scala 186:34]
+  wire  _p_x_T_3 = sl_3 == 2'h0; // @[VInst.scala 188:20]
+  wire  p_x_3 = sl_3 == 2'h0 & xs2zero_3; // @[VInst.scala 188:28]
+  wire  p_xx_3 = _p_x_T_3 & ~xs2zero_3; // @[VInst.scala 189:28]
+  wire  lp_xx_3 = sl_3 == 2'h1; // @[VInst.scala 190:20]
+  wire  _sp_xx_T_6 = sl_3 == 2'h2; // @[VInst.scala 191:20]
+  wire  sp_xx_3 = sl_3 == 2'h2 & ~q_7; // @[VInst.scala 191:28]
+  wire  qp_xx_3 = _sp_xx_T_6 & q_7; // @[VInst.scala 192:28]
+  wire  tp_xx_3 = sl_3 == 2'h3; // @[VInst.scala 193:20]
   wire [5:0] _T_67 = {p_x_3,p_xx_3,lp_xx_3,sp_xx_3,qp_xx_3,tp_xx_3}; // @[Cat.scala 31:58]
   wire [1:0] _T_74 = _T_67[1] + _T_67[2]; // @[Bitwise.scala 48:55]
   wire [1:0] _GEN_52 = {{1'd0}, _T_67[0]}; // @[Bitwise.scala 48:55]
@@ -33560,163 +24253,163 @@
   wire [1:0] _GEN_53 = {{1'd0}, _T_67[3]}; // @[Bitwise.scala 48:55]
   wire [2:0] _T_80 = _GEN_53 + _T_78; // @[Bitwise.scala 48:55]
   wire [2:0] _T_82 = _T_76[1:0] + _T_80[1:0]; // @[Bitwise.scala 48:55]
-  wire [7:0] _offset_T_39 = m_3 ? 8'h80 : 8'h20; // @[VInst.scala 201:34]
+  wire [7:0] _offset_T_39 = m_3 ? 8'h80 : 8'h20; // @[VInst.scala 196:34]
   wire [7:0] _offset_T_40 = p_x_3 ? _offset_T_39 : 8'h0; // @[Library.scala 8:8]
   wire [31:0] _offset_T_41 = p_xx_3 ? rt_3 : 32'h0; // @[Library.scala 8:8]
-  wire [31:0] _GEN_54 = {{24'd0}, _offset_T_40}; // @[VInst.scala 201:56]
-  wire [31:0] _offset_T_42 = _GEN_54 | _offset_T_41; // @[VInst.scala 201:56]
+  wire [31:0] _GEN_54 = {{24'd0}, _offset_T_40}; // @[VInst.scala 196:56]
+  wire [31:0] _offset_T_42 = _GEN_54 | _offset_T_41; // @[VInst.scala 196:56]
   wire [31:0] _offset_T_43 = lp_xx_3 ? bytes_3 : 32'h0; // @[Library.scala 8:8]
-  wire [31:0] _offset_T_44 = _offset_T_42 | _offset_T_43; // @[VInst.scala 202:35]
-  wire [31:0] _offset_T_45 = m_3 ? rtm_3 : rt_3; // @[VInst.scala 204:34]
+  wire [31:0] _offset_T_44 = _offset_T_42 | _offset_T_43; // @[VInst.scala 197:35]
+  wire [31:0] _offset_T_45 = m_3 ? rtm_3 : rt_3; // @[VInst.scala 199:34]
   wire [31:0] _offset_T_46 = sp_xx_3 ? _offset_T_45 : 32'h0; // @[Library.scala 8:8]
-  wire [31:0] _offset_T_47 = _offset_T_44 | _offset_T_46; // @[VInst.scala 203:38]
+  wire [31:0] _offset_T_47 = _offset_T_44 | _offset_T_46; // @[VInst.scala 198:38]
   wire [7:0] _offset_T_48 = tp_xx_3 ? 8'h20 : 8'h0; // @[Library.scala 8:8]
-  wire [31:0] _GEN_55 = {{24'd0}, _offset_T_48}; // @[VInst.scala 204:48]
-  wire [31:0] _offset_T_49 = _offset_T_47 | _GEN_55; // @[VInst.scala 204:48]
-  wire [31:0] _offset_T_50 = m_3 ? rtq_3 : rtm_3; // @[VInst.scala 206:34]
+  wire [31:0] _GEN_55 = {{24'd0}, _offset_T_48}; // @[VInst.scala 199:48]
+  wire [31:0] _offset_T_49 = _offset_T_47 | _GEN_55; // @[VInst.scala 199:48]
+  wire [31:0] _offset_T_50 = m_3 ? rtq_3 : rtm_3; // @[VInst.scala 201:34]
   wire [31:0] _offset_T_51 = qp_xx_3 ? _offset_T_50 : 32'h0; // @[Library.scala 8:8]
-  wire [31:0] offset_3 = _offset_T_49 | _offset_T_51; // @[VInst.scala 205:39]
-  wire [31:0] lsuAdder_3 = io_rs_6_data + offset_3; // @[VInst.scala 209:24]
-  wire [1:0] getvlsz = vinstInst_0[26:25]; // @[VInst.scala 216:31]
-  wire  getvlm = vinstInst_0[27]; // @[VInst.scala 217:31]
-  wire  _maxvl_T = getvlsz == 2'h0; // @[VInst.scala 218:31]
-  wire  _maxvl_T_1 = ~getvlm; // @[VInst.scala 218:42]
-  wire  _maxvl_T_2 = getvlsz == 2'h0 & ~getvlm; // @[VInst.scala 218:39]
+  wire [31:0] offset_3 = _offset_T_49 | _offset_T_51; // @[VInst.scala 200:39]
+  wire [31:0] lsuAdder_3 = io_rs_6_data + offset_3; // @[VInst.scala 204:24]
+  wire [1:0] getvlsz = vinstInst_0[26:25]; // @[VInst.scala 211:31]
+  wire  getvlm = vinstInst_0[27]; // @[VInst.scala 212:31]
+  wire  _maxvl_T = getvlsz == 2'h0; // @[VInst.scala 213:31]
+  wire  _maxvl_T_1 = ~getvlm; // @[VInst.scala 213:42]
+  wire  _maxvl_T_2 = getvlsz == 2'h0 & ~getvlm; // @[VInst.scala 213:39]
   wire [7:0] _maxvl_T_3 = _maxvl_T_2 ? 8'h20 : 8'h0; // @[Library.scala 8:8]
-  wire  _maxvl_T_4 = getvlsz == 2'h1; // @[VInst.scala 219:31]
-  wire  _maxvl_T_6 = getvlsz == 2'h1 & _maxvl_T_1; // @[VInst.scala 219:39]
+  wire  _maxvl_T_4 = getvlsz == 2'h1; // @[VInst.scala 214:31]
+  wire  _maxvl_T_6 = getvlsz == 2'h1 & _maxvl_T_1; // @[VInst.scala 214:39]
   wire [7:0] _maxvl_T_7 = _maxvl_T_6 ? 8'h10 : 8'h0; // @[Library.scala 8:8]
-  wire [7:0] _maxvl_T_8 = _maxvl_T_3 | _maxvl_T_7; // @[VInst.scala 218:59]
-  wire  _maxvl_T_9 = getvlsz == 2'h2; // @[VInst.scala 220:31]
-  wire  _maxvl_T_11 = getvlsz == 2'h2 & _maxvl_T_1; // @[VInst.scala 220:39]
+  wire [7:0] _maxvl_T_8 = _maxvl_T_3 | _maxvl_T_7; // @[VInst.scala 213:59]
+  wire  _maxvl_T_9 = getvlsz == 2'h2; // @[VInst.scala 215:31]
+  wire  _maxvl_T_11 = getvlsz == 2'h2 & _maxvl_T_1; // @[VInst.scala 215:39]
   wire [7:0] _maxvl_T_12 = _maxvl_T_11 ? 8'h8 : 8'h0; // @[Library.scala 8:8]
-  wire [7:0] _maxvl_T_13 = _maxvl_T_8 | _maxvl_T_12; // @[VInst.scala 219:59]
-  wire  _maxvl_T_15 = _maxvl_T & getvlm; // @[VInst.scala 221:39]
+  wire [7:0] _maxvl_T_13 = _maxvl_T_8 | _maxvl_T_12; // @[VInst.scala 214:59]
+  wire  _maxvl_T_15 = _maxvl_T & getvlm; // @[VInst.scala 216:39]
   wire [7:0] _maxvl_T_16 = _maxvl_T_15 ? 8'h80 : 8'h0; // @[Library.scala 8:8]
-  wire [7:0] _maxvl_T_17 = _maxvl_T_13 | _maxvl_T_16; // @[VInst.scala 220:59]
-  wire  _maxvl_T_19 = _maxvl_T_4 & getvlm; // @[VInst.scala 222:39]
+  wire [7:0] _maxvl_T_17 = _maxvl_T_13 | _maxvl_T_16; // @[VInst.scala 215:59]
+  wire  _maxvl_T_19 = _maxvl_T_4 & getvlm; // @[VInst.scala 217:39]
   wire [7:0] _maxvl_T_20 = _maxvl_T_19 ? 8'h40 : 8'h0; // @[Library.scala 8:8]
-  wire [7:0] _maxvl_T_21 = _maxvl_T_17 | _maxvl_T_20; // @[VInst.scala 221:60]
-  wire  _maxvl_T_23 = _maxvl_T_9 & getvlm; // @[VInst.scala 223:39]
+  wire [7:0] _maxvl_T_21 = _maxvl_T_17 | _maxvl_T_20; // @[VInst.scala 216:60]
+  wire  _maxvl_T_23 = _maxvl_T_9 & getvlm; // @[VInst.scala 218:39]
   wire [7:0] _maxvl_T_24 = _maxvl_T_23 ? 8'h20 : 8'h0; // @[Library.scala 8:8]
-  wire [7:0] maxvl = _maxvl_T_21 | _maxvl_T_24; // @[VInst.scala 222:60]
-  wire  rs2nonzero = vinstInst_0[24:20] != 5'h0; // @[VInst.scala 225:42]
-  wire [31:0] _GEN_56 = {{24'd0}, maxvl}; // @[VInst.scala 227:15]
-  wire [31:0] _GEN_4 = io_rs_0_data < _GEN_56 ? io_rs_0_data : {{24'd0}, maxvl}; // @[VInst.scala 229:31 230:11 232:11]
-  wire [31:0] _GEN_5 = io_rs_1_data < _GEN_56 & io_rs_1_data < io_rs_0_data & rs2nonzero ? io_rs_1_data : _GEN_4; // @[VInst.scala 227:51 228:11]
-  wire [1:0] getvlsz_1 = vinstInst_1[26:25]; // @[VInst.scala 216:31]
-  wire  getvlm_1 = vinstInst_1[27]; // @[VInst.scala 217:31]
-  wire  _maxvl_T_25 = getvlsz_1 == 2'h0; // @[VInst.scala 218:31]
-  wire  _maxvl_T_26 = ~getvlm_1; // @[VInst.scala 218:42]
-  wire  _maxvl_T_27 = getvlsz_1 == 2'h0 & ~getvlm_1; // @[VInst.scala 218:39]
+  wire [7:0] maxvl = _maxvl_T_21 | _maxvl_T_24; // @[VInst.scala 217:60]
+  wire  rs2nonzero = vinstInst_0[24:20] != 5'h0; // @[VInst.scala 220:42]
+  wire [31:0] _GEN_56 = {{24'd0}, maxvl}; // @[VInst.scala 222:15]
+  wire [31:0] _GEN_4 = io_rs_0_data < _GEN_56 ? io_rs_0_data : {{24'd0}, maxvl}; // @[VInst.scala 224:31 225:11 227:11]
+  wire [31:0] _GEN_5 = io_rs_1_data < _GEN_56 & io_rs_1_data < io_rs_0_data & rs2nonzero ? io_rs_1_data : _GEN_4; // @[VInst.scala 222:51 223:11]
+  wire [1:0] getvlsz_1 = vinstInst_1[26:25]; // @[VInst.scala 211:31]
+  wire  getvlm_1 = vinstInst_1[27]; // @[VInst.scala 212:31]
+  wire  _maxvl_T_25 = getvlsz_1 == 2'h0; // @[VInst.scala 213:31]
+  wire  _maxvl_T_26 = ~getvlm_1; // @[VInst.scala 213:42]
+  wire  _maxvl_T_27 = getvlsz_1 == 2'h0 & ~getvlm_1; // @[VInst.scala 213:39]
   wire [7:0] _maxvl_T_28 = _maxvl_T_27 ? 8'h20 : 8'h0; // @[Library.scala 8:8]
-  wire  _maxvl_T_29 = getvlsz_1 == 2'h1; // @[VInst.scala 219:31]
-  wire  _maxvl_T_31 = getvlsz_1 == 2'h1 & _maxvl_T_26; // @[VInst.scala 219:39]
+  wire  _maxvl_T_29 = getvlsz_1 == 2'h1; // @[VInst.scala 214:31]
+  wire  _maxvl_T_31 = getvlsz_1 == 2'h1 & _maxvl_T_26; // @[VInst.scala 214:39]
   wire [7:0] _maxvl_T_32 = _maxvl_T_31 ? 8'h10 : 8'h0; // @[Library.scala 8:8]
-  wire [7:0] _maxvl_T_33 = _maxvl_T_28 | _maxvl_T_32; // @[VInst.scala 218:59]
-  wire  _maxvl_T_34 = getvlsz_1 == 2'h2; // @[VInst.scala 220:31]
-  wire  _maxvl_T_36 = getvlsz_1 == 2'h2 & _maxvl_T_26; // @[VInst.scala 220:39]
+  wire [7:0] _maxvl_T_33 = _maxvl_T_28 | _maxvl_T_32; // @[VInst.scala 213:59]
+  wire  _maxvl_T_34 = getvlsz_1 == 2'h2; // @[VInst.scala 215:31]
+  wire  _maxvl_T_36 = getvlsz_1 == 2'h2 & _maxvl_T_26; // @[VInst.scala 215:39]
   wire [7:0] _maxvl_T_37 = _maxvl_T_36 ? 8'h8 : 8'h0; // @[Library.scala 8:8]
-  wire [7:0] _maxvl_T_38 = _maxvl_T_33 | _maxvl_T_37; // @[VInst.scala 219:59]
-  wire  _maxvl_T_40 = _maxvl_T_25 & getvlm_1; // @[VInst.scala 221:39]
+  wire [7:0] _maxvl_T_38 = _maxvl_T_33 | _maxvl_T_37; // @[VInst.scala 214:59]
+  wire  _maxvl_T_40 = _maxvl_T_25 & getvlm_1; // @[VInst.scala 216:39]
   wire [7:0] _maxvl_T_41 = _maxvl_T_40 ? 8'h80 : 8'h0; // @[Library.scala 8:8]
-  wire [7:0] _maxvl_T_42 = _maxvl_T_38 | _maxvl_T_41; // @[VInst.scala 220:59]
-  wire  _maxvl_T_44 = _maxvl_T_29 & getvlm_1; // @[VInst.scala 222:39]
+  wire [7:0] _maxvl_T_42 = _maxvl_T_38 | _maxvl_T_41; // @[VInst.scala 215:59]
+  wire  _maxvl_T_44 = _maxvl_T_29 & getvlm_1; // @[VInst.scala 217:39]
   wire [7:0] _maxvl_T_45 = _maxvl_T_44 ? 8'h40 : 8'h0; // @[Library.scala 8:8]
-  wire [7:0] _maxvl_T_46 = _maxvl_T_42 | _maxvl_T_45; // @[VInst.scala 221:60]
-  wire  _maxvl_T_48 = _maxvl_T_34 & getvlm_1; // @[VInst.scala 223:39]
+  wire [7:0] _maxvl_T_46 = _maxvl_T_42 | _maxvl_T_45; // @[VInst.scala 216:60]
+  wire  _maxvl_T_48 = _maxvl_T_34 & getvlm_1; // @[VInst.scala 218:39]
   wire [7:0] _maxvl_T_49 = _maxvl_T_48 ? 8'h20 : 8'h0; // @[Library.scala 8:8]
-  wire [7:0] maxvl_1 = _maxvl_T_46 | _maxvl_T_49; // @[VInst.scala 222:60]
-  wire  rs2nonzero_1 = vinstInst_1[24:20] != 5'h0; // @[VInst.scala 225:42]
-  wire [31:0] _GEN_58 = {{24'd0}, maxvl_1}; // @[VInst.scala 227:15]
-  wire [31:0] _GEN_6 = io_rs_2_data < _GEN_58 ? io_rs_2_data : {{24'd0}, maxvl_1}; // @[VInst.scala 229:31 230:11 232:11]
-  wire [31:0] _GEN_7 = io_rs_3_data < _GEN_58 & io_rs_3_data < io_rs_2_data & rs2nonzero_1 ? io_rs_3_data : _GEN_6; // @[VInst.scala 227:51 228:11]
-  wire [1:0] getvlsz_2 = vinstInst_2[26:25]; // @[VInst.scala 216:31]
-  wire  getvlm_2 = vinstInst_2[27]; // @[VInst.scala 217:31]
-  wire  _maxvl_T_50 = getvlsz_2 == 2'h0; // @[VInst.scala 218:31]
-  wire  _maxvl_T_51 = ~getvlm_2; // @[VInst.scala 218:42]
-  wire  _maxvl_T_52 = getvlsz_2 == 2'h0 & ~getvlm_2; // @[VInst.scala 218:39]
+  wire [7:0] maxvl_1 = _maxvl_T_46 | _maxvl_T_49; // @[VInst.scala 217:60]
+  wire  rs2nonzero_1 = vinstInst_1[24:20] != 5'h0; // @[VInst.scala 220:42]
+  wire [31:0] _GEN_58 = {{24'd0}, maxvl_1}; // @[VInst.scala 222:15]
+  wire [31:0] _GEN_6 = io_rs_2_data < _GEN_58 ? io_rs_2_data : {{24'd0}, maxvl_1}; // @[VInst.scala 224:31 225:11 227:11]
+  wire [31:0] _GEN_7 = io_rs_3_data < _GEN_58 & io_rs_3_data < io_rs_2_data & rs2nonzero_1 ? io_rs_3_data : _GEN_6; // @[VInst.scala 222:51 223:11]
+  wire [1:0] getvlsz_2 = vinstInst_2[26:25]; // @[VInst.scala 211:31]
+  wire  getvlm_2 = vinstInst_2[27]; // @[VInst.scala 212:31]
+  wire  _maxvl_T_50 = getvlsz_2 == 2'h0; // @[VInst.scala 213:31]
+  wire  _maxvl_T_51 = ~getvlm_2; // @[VInst.scala 213:42]
+  wire  _maxvl_T_52 = getvlsz_2 == 2'h0 & ~getvlm_2; // @[VInst.scala 213:39]
   wire [7:0] _maxvl_T_53 = _maxvl_T_52 ? 8'h20 : 8'h0; // @[Library.scala 8:8]
-  wire  _maxvl_T_54 = getvlsz_2 == 2'h1; // @[VInst.scala 219:31]
-  wire  _maxvl_T_56 = getvlsz_2 == 2'h1 & _maxvl_T_51; // @[VInst.scala 219:39]
+  wire  _maxvl_T_54 = getvlsz_2 == 2'h1; // @[VInst.scala 214:31]
+  wire  _maxvl_T_56 = getvlsz_2 == 2'h1 & _maxvl_T_51; // @[VInst.scala 214:39]
   wire [7:0] _maxvl_T_57 = _maxvl_T_56 ? 8'h10 : 8'h0; // @[Library.scala 8:8]
-  wire [7:0] _maxvl_T_58 = _maxvl_T_53 | _maxvl_T_57; // @[VInst.scala 218:59]
-  wire  _maxvl_T_59 = getvlsz_2 == 2'h2; // @[VInst.scala 220:31]
-  wire  _maxvl_T_61 = getvlsz_2 == 2'h2 & _maxvl_T_51; // @[VInst.scala 220:39]
+  wire [7:0] _maxvl_T_58 = _maxvl_T_53 | _maxvl_T_57; // @[VInst.scala 213:59]
+  wire  _maxvl_T_59 = getvlsz_2 == 2'h2; // @[VInst.scala 215:31]
+  wire  _maxvl_T_61 = getvlsz_2 == 2'h2 & _maxvl_T_51; // @[VInst.scala 215:39]
   wire [7:0] _maxvl_T_62 = _maxvl_T_61 ? 8'h8 : 8'h0; // @[Library.scala 8:8]
-  wire [7:0] _maxvl_T_63 = _maxvl_T_58 | _maxvl_T_62; // @[VInst.scala 219:59]
-  wire  _maxvl_T_65 = _maxvl_T_50 & getvlm_2; // @[VInst.scala 221:39]
+  wire [7:0] _maxvl_T_63 = _maxvl_T_58 | _maxvl_T_62; // @[VInst.scala 214:59]
+  wire  _maxvl_T_65 = _maxvl_T_50 & getvlm_2; // @[VInst.scala 216:39]
   wire [7:0] _maxvl_T_66 = _maxvl_T_65 ? 8'h80 : 8'h0; // @[Library.scala 8:8]
-  wire [7:0] _maxvl_T_67 = _maxvl_T_63 | _maxvl_T_66; // @[VInst.scala 220:59]
-  wire  _maxvl_T_69 = _maxvl_T_54 & getvlm_2; // @[VInst.scala 222:39]
+  wire [7:0] _maxvl_T_67 = _maxvl_T_63 | _maxvl_T_66; // @[VInst.scala 215:59]
+  wire  _maxvl_T_69 = _maxvl_T_54 & getvlm_2; // @[VInst.scala 217:39]
   wire [7:0] _maxvl_T_70 = _maxvl_T_69 ? 8'h40 : 8'h0; // @[Library.scala 8:8]
-  wire [7:0] _maxvl_T_71 = _maxvl_T_67 | _maxvl_T_70; // @[VInst.scala 221:60]
-  wire  _maxvl_T_73 = _maxvl_T_59 & getvlm_2; // @[VInst.scala 223:39]
+  wire [7:0] _maxvl_T_71 = _maxvl_T_67 | _maxvl_T_70; // @[VInst.scala 216:60]
+  wire  _maxvl_T_73 = _maxvl_T_59 & getvlm_2; // @[VInst.scala 218:39]
   wire [7:0] _maxvl_T_74 = _maxvl_T_73 ? 8'h20 : 8'h0; // @[Library.scala 8:8]
-  wire [7:0] maxvl_2 = _maxvl_T_71 | _maxvl_T_74; // @[VInst.scala 222:60]
-  wire  rs2nonzero_2 = vinstInst_2[24:20] != 5'h0; // @[VInst.scala 225:42]
-  wire [31:0] _GEN_60 = {{24'd0}, maxvl_2}; // @[VInst.scala 227:15]
-  wire [31:0] _GEN_8 = io_rs_4_data < _GEN_60 ? io_rs_4_data : {{24'd0}, maxvl_2}; // @[VInst.scala 229:31 230:11 232:11]
-  wire [31:0] _GEN_9 = io_rs_5_data < _GEN_60 & io_rs_5_data < io_rs_4_data & rs2nonzero_2 ? io_rs_5_data : _GEN_8; // @[VInst.scala 227:51 228:11]
-  wire [1:0] getvlsz_3 = vinstInst_3[26:25]; // @[VInst.scala 216:31]
-  wire  getvlm_3 = vinstInst_3[27]; // @[VInst.scala 217:31]
-  wire  _maxvl_T_75 = getvlsz_3 == 2'h0; // @[VInst.scala 218:31]
-  wire  _maxvl_T_76 = ~getvlm_3; // @[VInst.scala 218:42]
-  wire  _maxvl_T_77 = getvlsz_3 == 2'h0 & ~getvlm_3; // @[VInst.scala 218:39]
+  wire [7:0] maxvl_2 = _maxvl_T_71 | _maxvl_T_74; // @[VInst.scala 217:60]
+  wire  rs2nonzero_2 = vinstInst_2[24:20] != 5'h0; // @[VInst.scala 220:42]
+  wire [31:0] _GEN_60 = {{24'd0}, maxvl_2}; // @[VInst.scala 222:15]
+  wire [31:0] _GEN_8 = io_rs_4_data < _GEN_60 ? io_rs_4_data : {{24'd0}, maxvl_2}; // @[VInst.scala 224:31 225:11 227:11]
+  wire [31:0] _GEN_9 = io_rs_5_data < _GEN_60 & io_rs_5_data < io_rs_4_data & rs2nonzero_2 ? io_rs_5_data : _GEN_8; // @[VInst.scala 222:51 223:11]
+  wire [1:0] getvlsz_3 = vinstInst_3[26:25]; // @[VInst.scala 211:31]
+  wire  getvlm_3 = vinstInst_3[27]; // @[VInst.scala 212:31]
+  wire  _maxvl_T_75 = getvlsz_3 == 2'h0; // @[VInst.scala 213:31]
+  wire  _maxvl_T_76 = ~getvlm_3; // @[VInst.scala 213:42]
+  wire  _maxvl_T_77 = getvlsz_3 == 2'h0 & ~getvlm_3; // @[VInst.scala 213:39]
   wire [7:0] _maxvl_T_78 = _maxvl_T_77 ? 8'h20 : 8'h0; // @[Library.scala 8:8]
-  wire  _maxvl_T_79 = getvlsz_3 == 2'h1; // @[VInst.scala 219:31]
-  wire  _maxvl_T_81 = getvlsz_3 == 2'h1 & _maxvl_T_76; // @[VInst.scala 219:39]
+  wire  _maxvl_T_79 = getvlsz_3 == 2'h1; // @[VInst.scala 214:31]
+  wire  _maxvl_T_81 = getvlsz_3 == 2'h1 & _maxvl_T_76; // @[VInst.scala 214:39]
   wire [7:0] _maxvl_T_82 = _maxvl_T_81 ? 8'h10 : 8'h0; // @[Library.scala 8:8]
-  wire [7:0] _maxvl_T_83 = _maxvl_T_78 | _maxvl_T_82; // @[VInst.scala 218:59]
-  wire  _maxvl_T_84 = getvlsz_3 == 2'h2; // @[VInst.scala 220:31]
-  wire  _maxvl_T_86 = getvlsz_3 == 2'h2 & _maxvl_T_76; // @[VInst.scala 220:39]
+  wire [7:0] _maxvl_T_83 = _maxvl_T_78 | _maxvl_T_82; // @[VInst.scala 213:59]
+  wire  _maxvl_T_84 = getvlsz_3 == 2'h2; // @[VInst.scala 215:31]
+  wire  _maxvl_T_86 = getvlsz_3 == 2'h2 & _maxvl_T_76; // @[VInst.scala 215:39]
   wire [7:0] _maxvl_T_87 = _maxvl_T_86 ? 8'h8 : 8'h0; // @[Library.scala 8:8]
-  wire [7:0] _maxvl_T_88 = _maxvl_T_83 | _maxvl_T_87; // @[VInst.scala 219:59]
-  wire  _maxvl_T_90 = _maxvl_T_75 & getvlm_3; // @[VInst.scala 221:39]
+  wire [7:0] _maxvl_T_88 = _maxvl_T_83 | _maxvl_T_87; // @[VInst.scala 214:59]
+  wire  _maxvl_T_90 = _maxvl_T_75 & getvlm_3; // @[VInst.scala 216:39]
   wire [7:0] _maxvl_T_91 = _maxvl_T_90 ? 8'h80 : 8'h0; // @[Library.scala 8:8]
-  wire [7:0] _maxvl_T_92 = _maxvl_T_88 | _maxvl_T_91; // @[VInst.scala 220:59]
-  wire  _maxvl_T_94 = _maxvl_T_79 & getvlm_3; // @[VInst.scala 222:39]
+  wire [7:0] _maxvl_T_92 = _maxvl_T_88 | _maxvl_T_91; // @[VInst.scala 215:59]
+  wire  _maxvl_T_94 = _maxvl_T_79 & getvlm_3; // @[VInst.scala 217:39]
   wire [7:0] _maxvl_T_95 = _maxvl_T_94 ? 8'h40 : 8'h0; // @[Library.scala 8:8]
-  wire [7:0] _maxvl_T_96 = _maxvl_T_92 | _maxvl_T_95; // @[VInst.scala 221:60]
-  wire  _maxvl_T_98 = _maxvl_T_84 & getvlm_3; // @[VInst.scala 223:39]
+  wire [7:0] _maxvl_T_96 = _maxvl_T_92 | _maxvl_T_95; // @[VInst.scala 216:60]
+  wire  _maxvl_T_98 = _maxvl_T_84 & getvlm_3; // @[VInst.scala 218:39]
   wire [7:0] _maxvl_T_99 = _maxvl_T_98 ? 8'h20 : 8'h0; // @[Library.scala 8:8]
-  wire [7:0] maxvl_3 = _maxvl_T_96 | _maxvl_T_99; // @[VInst.scala 222:60]
-  wire  rs2nonzero_3 = vinstInst_3[24:20] != 5'h0; // @[VInst.scala 225:42]
-  wire [31:0] _GEN_62 = {{24'd0}, maxvl_3}; // @[VInst.scala 227:15]
-  wire [31:0] _GEN_10 = io_rs_6_data < _GEN_62 ? io_rs_6_data : {{24'd0}, maxvl_3}; // @[VInst.scala 229:31 230:11 232:11]
-  wire [31:0] _GEN_11 = io_rs_7_data < _GEN_62 & io_rs_7_data < io_rs_6_data & rs2nonzero_3 ? io_rs_7_data : _GEN_10; // @[VInst.scala 227:51 228:11]
-  wire [7:0] len = _GEN_5[7:0]; // @[VInst.scala 213:19]
+  wire [7:0] maxvl_3 = _maxvl_T_96 | _maxvl_T_99; // @[VInst.scala 217:60]
+  wire  rs2nonzero_3 = vinstInst_3[24:20] != 5'h0; // @[VInst.scala 220:42]
+  wire [31:0] _GEN_62 = {{24'd0}, maxvl_3}; // @[VInst.scala 222:15]
+  wire [31:0] _GEN_10 = io_rs_6_data < _GEN_62 ? io_rs_6_data : {{24'd0}, maxvl_3}; // @[VInst.scala 224:31 225:11 227:11]
+  wire [31:0] _GEN_11 = io_rs_7_data < _GEN_62 & io_rs_7_data < io_rs_6_data & rs2nonzero_3 ? io_rs_7_data : _GEN_10; // @[VInst.scala 222:51 223:11]
+  wire [7:0] len = _GEN_5[7:0]; // @[VInst.scala 208:19]
   wire [7:0] _io_rd_0_data_T = getvl_0 ? len : 8'h0; // @[Library.scala 8:8]
   wire [7:0] _io_rd_0_data_T_1 = getmaxvl_0 ? maxvl : 8'h0; // @[Library.scala 8:8]
-  wire [7:0] _io_rd_0_data_T_2 = _io_rd_0_data_T | _io_rd_0_data_T_1; // @[VInst.scala 244:40]
-  wire  _io_rd_0_data_T_4 = vld_u_0 | vst_u_0 | vst_q_0; // @[VInst.scala 246:36]
+  wire [7:0] _io_rd_0_data_T_2 = _io_rd_0_data_T | _io_rd_0_data_T_1; // @[VInst.scala 239:40]
+  wire  _io_rd_0_data_T_4 = vld_u_0 | vst_u_0 | vst_q_0; // @[VInst.scala 241:36]
   wire [31:0] _io_rd_0_data_T_5 = _io_rd_0_data_T_4 ? lsuAdder_0 : 32'h0; // @[Library.scala 8:8]
-  wire [31:0] _GEN_64 = {{24'd0}, _io_rd_0_data_T_2}; // @[VInst.scala 245:46]
-  wire [7:0] len_1 = _GEN_7[7:0]; // @[VInst.scala 213:19]
+  wire [31:0] _GEN_64 = {{24'd0}, _io_rd_0_data_T_2}; // @[VInst.scala 240:46]
+  wire [7:0] len_1 = _GEN_7[7:0]; // @[VInst.scala 208:19]
   wire [7:0] _io_rd_1_data_T = getvl_1 ? len_1 : 8'h0; // @[Library.scala 8:8]
   wire [7:0] _io_rd_1_data_T_1 = getmaxvl_1 ? maxvl_1 : 8'h0; // @[Library.scala 8:8]
-  wire [7:0] _io_rd_1_data_T_2 = _io_rd_1_data_T | _io_rd_1_data_T_1; // @[VInst.scala 244:40]
-  wire  _io_rd_1_data_T_4 = vld_u_1 | vst_u_1 | vst_q_1; // @[VInst.scala 246:36]
+  wire [7:0] _io_rd_1_data_T_2 = _io_rd_1_data_T | _io_rd_1_data_T_1; // @[VInst.scala 239:40]
+  wire  _io_rd_1_data_T_4 = vld_u_1 | vst_u_1 | vst_q_1; // @[VInst.scala 241:36]
   wire [31:0] _io_rd_1_data_T_5 = _io_rd_1_data_T_4 ? lsuAdder_1 : 32'h0; // @[Library.scala 8:8]
-  wire [31:0] _GEN_65 = {{24'd0}, _io_rd_1_data_T_2}; // @[VInst.scala 245:46]
-  wire [7:0] len_2 = _GEN_9[7:0]; // @[VInst.scala 213:19]
+  wire [31:0] _GEN_65 = {{24'd0}, _io_rd_1_data_T_2}; // @[VInst.scala 240:46]
+  wire [7:0] len_2 = _GEN_9[7:0]; // @[VInst.scala 208:19]
   wire [7:0] _io_rd_2_data_T = getvl_2 ? len_2 : 8'h0; // @[Library.scala 8:8]
   wire [7:0] _io_rd_2_data_T_1 = getmaxvl_2 ? maxvl_2 : 8'h0; // @[Library.scala 8:8]
-  wire [7:0] _io_rd_2_data_T_2 = _io_rd_2_data_T | _io_rd_2_data_T_1; // @[VInst.scala 244:40]
-  wire  _io_rd_2_data_T_4 = vld_u_2 | vst_u_2 | vst_q_2; // @[VInst.scala 246:36]
+  wire [7:0] _io_rd_2_data_T_2 = _io_rd_2_data_T | _io_rd_2_data_T_1; // @[VInst.scala 239:40]
+  wire  _io_rd_2_data_T_4 = vld_u_2 | vst_u_2 | vst_q_2; // @[VInst.scala 241:36]
   wire [31:0] _io_rd_2_data_T_5 = _io_rd_2_data_T_4 ? lsuAdder_2 : 32'h0; // @[Library.scala 8:8]
-  wire [31:0] _GEN_66 = {{24'd0}, _io_rd_2_data_T_2}; // @[VInst.scala 245:46]
-  wire [7:0] len_3 = _GEN_11[7:0]; // @[VInst.scala 213:19]
+  wire [31:0] _GEN_66 = {{24'd0}, _io_rd_2_data_T_2}; // @[VInst.scala 240:46]
+  wire [7:0] len_3 = _GEN_11[7:0]; // @[VInst.scala 208:19]
   wire [7:0] _io_rd_3_data_T = getvl_3 ? len_3 : 8'h0; // @[Library.scala 8:8]
   wire [7:0] _io_rd_3_data_T_1 = getmaxvl_3 ? maxvl_3 : 8'h0; // @[Library.scala 8:8]
-  wire [7:0] _io_rd_3_data_T_2 = _io_rd_3_data_T | _io_rd_3_data_T_1; // @[VInst.scala 244:40]
-  wire  _io_rd_3_data_T_4 = vld_u_3 | vst_u_3 | vst_q_3; // @[VInst.scala 246:36]
+  wire [7:0] _io_rd_3_data_T_2 = _io_rd_3_data_T | _io_rd_3_data_T_1; // @[VInst.scala 239:40]
+  wire  _io_rd_3_data_T_4 = vld_u_3 | vst_u_3 | vst_q_3; // @[VInst.scala 241:36]
   wire [31:0] _io_rd_3_data_T_5 = _io_rd_3_data_T_4 ? lsuAdder_3 : 32'h0; // @[Library.scala 8:8]
-  wire [31:0] _GEN_67 = {{24'd0}, _io_rd_3_data_T_2}; // @[VInst.scala 245:46]
-  wire  _T_108 = ~slice_io_in_ready; // @[VInst.scala 257:33]
-  reg  nempty; // @[VInst.scala 279:23]
-  wire  _nempty_T_2 = io_in_0_valid | io_in_1_valid | io_in_2_valid | io_in_3_valid; // @[VInst.scala 282:64]
-  Slice_4 slice ( // @[Slice.scala 9:11]
+  wire [31:0] _GEN_67 = {{24'd0}, _io_rd_3_data_T_2}; // @[VInst.scala 240:46]
+  wire  _T_108 = ~slice_io_in_ready; // @[VInst.scala 252:33]
+  reg  nempty; // @[VInst.scala 274:23]
+  wire  _nempty_T_2 = io_in_0_valid | io_in_1_valid | io_in_2_valid | io_in_3_valid; // @[VInst.scala 277:64]
+  Slice_3 slice ( // @[Slice.scala 9:11]
     .clock(slice_clock),
     .reset(slice_reset),
     .io_in_ready(slice_io_in_ready),
@@ -33756,87 +24449,87 @@
     .io_out_bits_3_lane_bits_addr(slice_io_out_bits_3_lane_bits_addr),
     .io_out_bits_3_lane_bits_data(slice_io_out_bits_3_lane_bits_data)
   );
-  assign io_in_0_ready = ~io_out_stall; // @[VInst.scala 99:23]
-  assign io_in_1_ready = ~io_out_stall; // @[VInst.scala 99:23]
-  assign io_in_2_ready = ~io_out_stall; // @[VInst.scala 99:23]
-  assign io_in_3_ready = ~io_out_stall; // @[VInst.scala 99:23]
-  assign io_rd_0_valid = getvl_0 | getmaxvl_0 | vld_u_0 | vst_u_0 | vst_q_0; // @[VInst.scala 240:71]
-  assign io_rd_0_addr = rdAddr_0; // @[VInst.scala 241:19]
-  assign io_rd_0_data = _GEN_64 | _io_rd_0_data_T_5; // @[VInst.scala 245:46]
-  assign io_rd_1_valid = getvl_1 | getmaxvl_1 | vld_u_1 | vst_u_1 | vst_q_1; // @[VInst.scala 240:71]
-  assign io_rd_1_addr = rdAddr_1; // @[VInst.scala 241:19]
-  assign io_rd_1_data = _GEN_65 | _io_rd_1_data_T_5; // @[VInst.scala 245:46]
-  assign io_rd_2_valid = getvl_2 | getmaxvl_2 | vld_u_2 | vst_u_2 | vst_q_2; // @[VInst.scala 240:71]
-  assign io_rd_2_addr = rdAddr_2; // @[VInst.scala 241:19]
-  assign io_rd_2_data = _GEN_66 | _io_rd_2_data_T_5; // @[VInst.scala 245:46]
-  assign io_rd_3_valid = getvl_3 | getmaxvl_3 | vld_u_3 | vst_u_3 | vst_q_3; // @[VInst.scala 240:71]
-  assign io_rd_3_addr = rdAddr_3; // @[VInst.scala 241:19]
-  assign io_rd_3_data = _GEN_67 | _io_rd_3_data_T_5; // @[VInst.scala 245:46]
-  assign io_out_valid = slice_io_out_valid; // @[VInst.scala 253:16]
-  assign io_out_lane_0_valid = slice_io_out_bits_0_lane_valid; // @[VInst.scala 269:20]
-  assign io_out_lane_0_bits_inst = slice_io_out_bits_0_lane_bits_inst; // @[VInst.scala 269:20]
-  assign io_out_lane_0_bits_addr = slice_io_out_bits_0_lane_bits_addr; // @[VInst.scala 269:20]
-  assign io_out_lane_0_bits_data = slice_io_out_bits_0_lane_bits_data; // @[VInst.scala 269:20]
-  assign io_out_lane_1_valid = slice_io_out_bits_1_lane_valid; // @[VInst.scala 269:20]
-  assign io_out_lane_1_bits_inst = slice_io_out_bits_1_lane_bits_inst; // @[VInst.scala 269:20]
-  assign io_out_lane_1_bits_addr = slice_io_out_bits_1_lane_bits_addr; // @[VInst.scala 269:20]
-  assign io_out_lane_1_bits_data = slice_io_out_bits_1_lane_bits_data; // @[VInst.scala 269:20]
-  assign io_out_lane_2_valid = slice_io_out_bits_2_lane_valid; // @[VInst.scala 269:20]
-  assign io_out_lane_2_bits_inst = slice_io_out_bits_2_lane_bits_inst; // @[VInst.scala 269:20]
-  assign io_out_lane_2_bits_addr = slice_io_out_bits_2_lane_bits_addr; // @[VInst.scala 269:20]
-  assign io_out_lane_2_bits_data = slice_io_out_bits_2_lane_bits_data; // @[VInst.scala 269:20]
-  assign io_out_lane_3_valid = slice_io_out_bits_3_lane_valid; // @[VInst.scala 269:20]
-  assign io_out_lane_3_bits_inst = slice_io_out_bits_3_lane_bits_inst; // @[VInst.scala 269:20]
-  assign io_out_lane_3_bits_addr = slice_io_out_bits_3_lane_bits_addr; // @[VInst.scala 269:20]
-  assign io_out_lane_3_bits_data = slice_io_out_bits_3_lane_bits_data; // @[VInst.scala 269:20]
-  assign io_nempty = nempty; // @[VInst.scala 285:13]
+  assign io_in_0_ready = ~io_out_stall; // @[VInst.scala 97:23]
+  assign io_in_1_ready = ~io_out_stall; // @[VInst.scala 97:23]
+  assign io_in_2_ready = ~io_out_stall; // @[VInst.scala 97:23]
+  assign io_in_3_ready = ~io_out_stall; // @[VInst.scala 97:23]
+  assign io_rd_0_valid = getvl_0 | getmaxvl_0 | vld_u_0 | vst_u_0 | vst_q_0; // @[VInst.scala 235:71]
+  assign io_rd_0_addr = rdAddr_0; // @[VInst.scala 236:19]
+  assign io_rd_0_data = _GEN_64 | _io_rd_0_data_T_5; // @[VInst.scala 240:46]
+  assign io_rd_1_valid = getvl_1 | getmaxvl_1 | vld_u_1 | vst_u_1 | vst_q_1; // @[VInst.scala 235:71]
+  assign io_rd_1_addr = rdAddr_1; // @[VInst.scala 236:19]
+  assign io_rd_1_data = _GEN_65 | _io_rd_1_data_T_5; // @[VInst.scala 240:46]
+  assign io_rd_2_valid = getvl_2 | getmaxvl_2 | vld_u_2 | vst_u_2 | vst_q_2; // @[VInst.scala 235:71]
+  assign io_rd_2_addr = rdAddr_2; // @[VInst.scala 236:19]
+  assign io_rd_2_data = _GEN_66 | _io_rd_2_data_T_5; // @[VInst.scala 240:46]
+  assign io_rd_3_valid = getvl_3 | getmaxvl_3 | vld_u_3 | vst_u_3 | vst_q_3; // @[VInst.scala 235:71]
+  assign io_rd_3_addr = rdAddr_3; // @[VInst.scala 236:19]
+  assign io_rd_3_data = _GEN_67 | _io_rd_3_data_T_5; // @[VInst.scala 240:46]
+  assign io_out_valid = slice_io_out_valid; // @[VInst.scala 248:16]
+  assign io_out_lane_0_valid = slice_io_out_bits_0_lane_valid; // @[VInst.scala 264:20]
+  assign io_out_lane_0_bits_inst = slice_io_out_bits_0_lane_bits_inst; // @[VInst.scala 264:20]
+  assign io_out_lane_0_bits_addr = slice_io_out_bits_0_lane_bits_addr; // @[VInst.scala 264:20]
+  assign io_out_lane_0_bits_data = slice_io_out_bits_0_lane_bits_data; // @[VInst.scala 264:20]
+  assign io_out_lane_1_valid = slice_io_out_bits_1_lane_valid; // @[VInst.scala 264:20]
+  assign io_out_lane_1_bits_inst = slice_io_out_bits_1_lane_bits_inst; // @[VInst.scala 264:20]
+  assign io_out_lane_1_bits_addr = slice_io_out_bits_1_lane_bits_addr; // @[VInst.scala 264:20]
+  assign io_out_lane_1_bits_data = slice_io_out_bits_1_lane_bits_data; // @[VInst.scala 264:20]
+  assign io_out_lane_2_valid = slice_io_out_bits_2_lane_valid; // @[VInst.scala 264:20]
+  assign io_out_lane_2_bits_inst = slice_io_out_bits_2_lane_bits_inst; // @[VInst.scala 264:20]
+  assign io_out_lane_2_bits_addr = slice_io_out_bits_2_lane_bits_addr; // @[VInst.scala 264:20]
+  assign io_out_lane_2_bits_data = slice_io_out_bits_2_lane_bits_data; // @[VInst.scala 264:20]
+  assign io_out_lane_3_valid = slice_io_out_bits_3_lane_valid; // @[VInst.scala 264:20]
+  assign io_out_lane_3_bits_inst = slice_io_out_bits_3_lane_bits_inst; // @[VInst.scala 264:20]
+  assign io_out_lane_3_bits_addr = slice_io_out_bits_3_lane_bits_addr; // @[VInst.scala 264:20]
+  assign io_out_lane_3_bits_data = slice_io_out_bits_3_lane_bits_data; // @[VInst.scala 264:20]
+  assign io_nempty = nempty; // @[VInst.scala 280:13]
   assign slice_clock = clock;
   assign slice_reset = reset;
-  assign slice_io_in_valid = vvalid; // @[VInst.scala 251:21]
-  assign slice_io_in_bits_0_lane_valid = vinstValid_0; // @[VInst.scala 262:36]
-  assign slice_io_in_bits_0_lane_bits_inst = vinstInst_0; // @[VInst.scala 263:40]
-  assign slice_io_in_bits_0_lane_bits_addr = io_rs_0_data; // @[VInst.scala 264:40]
-  assign slice_io_in_bits_0_lane_bits_data = vfop_0 ? io_fs_0_data : io_rs_1_data; // @[VInst.scala 265:46]
-  assign slice_io_in_bits_1_lane_valid = vinstValid_1; // @[VInst.scala 262:36]
-  assign slice_io_in_bits_1_lane_bits_inst = vinstInst_1; // @[VInst.scala 263:40]
-  assign slice_io_in_bits_1_lane_bits_addr = io_rs_2_data; // @[VInst.scala 264:40]
-  assign slice_io_in_bits_1_lane_bits_data = vfop_1 ? io_fs_1_data : io_rs_3_data; // @[VInst.scala 265:46]
-  assign slice_io_in_bits_2_lane_valid = vinstValid_2; // @[VInst.scala 262:36]
-  assign slice_io_in_bits_2_lane_bits_inst = vinstInst_2; // @[VInst.scala 263:40]
-  assign slice_io_in_bits_2_lane_bits_addr = io_rs_4_data; // @[VInst.scala 264:40]
-  assign slice_io_in_bits_2_lane_bits_data = vfop_2 ? io_fs_2_data : io_rs_5_data; // @[VInst.scala 265:46]
-  assign slice_io_in_bits_3_lane_valid = vinstValid_3; // @[VInst.scala 262:36]
-  assign slice_io_in_bits_3_lane_bits_inst = vinstInst_3; // @[VInst.scala 263:40]
-  assign slice_io_in_bits_3_lane_bits_addr = io_rs_6_data; // @[VInst.scala 264:40]
-  assign slice_io_in_bits_3_lane_bits_data = vfop_3 ? io_fs_3_data : io_rs_7_data; // @[VInst.scala 265:46]
-  assign slice_io_out_ready = io_out_ready; // @[VInst.scala 252:22]
+  assign slice_io_in_valid = vvalid; // @[VInst.scala 246:21]
+  assign slice_io_in_bits_0_lane_valid = vinstValid_0; // @[VInst.scala 257:36]
+  assign slice_io_in_bits_0_lane_bits_inst = vinstInst_0; // @[VInst.scala 258:40]
+  assign slice_io_in_bits_0_lane_bits_addr = io_rs_0_data; // @[VInst.scala 259:40]
+  assign slice_io_in_bits_0_lane_bits_data = io_rs_1_data; // @[VInst.scala 260:40]
+  assign slice_io_in_bits_1_lane_valid = vinstValid_1; // @[VInst.scala 257:36]
+  assign slice_io_in_bits_1_lane_bits_inst = vinstInst_1; // @[VInst.scala 258:40]
+  assign slice_io_in_bits_1_lane_bits_addr = io_rs_2_data; // @[VInst.scala 259:40]
+  assign slice_io_in_bits_1_lane_bits_data = io_rs_3_data; // @[VInst.scala 260:40]
+  assign slice_io_in_bits_2_lane_valid = vinstValid_2; // @[VInst.scala 257:36]
+  assign slice_io_in_bits_2_lane_bits_inst = vinstInst_2; // @[VInst.scala 258:40]
+  assign slice_io_in_bits_2_lane_bits_addr = io_rs_4_data; // @[VInst.scala 259:40]
+  assign slice_io_in_bits_2_lane_bits_data = io_rs_5_data; // @[VInst.scala 260:40]
+  assign slice_io_in_bits_3_lane_valid = vinstValid_3; // @[VInst.scala 257:36]
+  assign slice_io_in_bits_3_lane_bits_inst = vinstInst_3; // @[VInst.scala 258:40]
+  assign slice_io_in_bits_3_lane_bits_addr = io_rs_6_data; // @[VInst.scala 259:40]
+  assign slice_io_in_bits_3_lane_bits_data = io_rs_7_data; // @[VInst.scala 260:40]
+  assign slice_io_out_ready = io_out_ready; // @[VInst.scala 247:22]
   always @(posedge clock) begin
-    if (reqvalid_0) begin // @[VInst.scala 116:24]
-      rdAddr_0 <= io_in_0_addr; // @[VInst.scala 117:17]
+    if (reqvalid_0) begin // @[VInst.scala 113:24]
+      rdAddr_0 <= io_in_0_addr; // @[VInst.scala 114:17]
     end
-    if (reqvalid_1) begin // @[VInst.scala 116:24]
-      rdAddr_1 <= io_in_1_addr; // @[VInst.scala 117:17]
+    if (reqvalid_1) begin // @[VInst.scala 113:24]
+      rdAddr_1 <= io_in_1_addr; // @[VInst.scala 114:17]
     end
-    if (reqvalid_2) begin // @[VInst.scala 116:24]
-      rdAddr_2 <= io_in_2_addr; // @[VInst.scala 117:17]
+    if (reqvalid_2) begin // @[VInst.scala 113:24]
+      rdAddr_2 <= io_in_2_addr; // @[VInst.scala 114:17]
     end
-    if (reqvalid_3) begin // @[VInst.scala 116:24]
-      rdAddr_3 <= io_in_3_addr; // @[VInst.scala 117:17]
+    if (reqvalid_3) begin // @[VInst.scala 113:24]
+      rdAddr_3 <= io_in_3_addr; // @[VInst.scala 114:17]
     end
-    vinstValid_0 <= reqvalid_0 & _nxtVinstValid_0_T_6; // @[VInst.scala 131:37]
-    vinstValid_1 <= reqvalid_1 & _nxtVinstValid_1_T_6; // @[VInst.scala 131:37]
-    vinstValid_2 <= reqvalid_2 & _nxtVinstValid_2_T_6; // @[VInst.scala 131:37]
-    vinstValid_3 <= reqvalid_3 & _nxtVinstValid_3_T_6; // @[VInst.scala 131:37]
-    vinstInst_0 <= io_in_0_inst; // @[VInst.scala 136:18]
-    vinstInst_1 <= io_in_1_inst; // @[VInst.scala 136:18]
-    vinstInst_2 <= io_in_2_inst; // @[VInst.scala 136:18]
-    vinstInst_3 <= io_in_3_inst; // @[VInst.scala 136:18]
+    vinstValid_0 <= reqvalid_0 & _nxtVinstValid_0_T_4; // @[VInst.scala 128:37]
+    vinstValid_1 <= reqvalid_1 & _nxtVinstValid_1_T_4; // @[VInst.scala 128:37]
+    vinstValid_2 <= reqvalid_2 & _nxtVinstValid_2_T_4; // @[VInst.scala 128:37]
+    vinstValid_3 <= reqvalid_3 & _nxtVinstValid_3_T_4; // @[VInst.scala 128:37]
+    vinstInst_0 <= io_in_0_inst; // @[VInst.scala 132:18]
+    vinstInst_1 <= io_in_1_inst; // @[VInst.scala 132:18]
+    vinstInst_2 <= io_in_2_inst; // @[VInst.scala 132:18]
+    vinstInst_3 <= io_in_3_inst; // @[VInst.scala 132:18]
     `ifndef SYNTHESIS
     `ifdef STOP_COND
       if (`STOP_COND) begin
     `endif
         if (_T_2 & ~(_T_19 <= 3'h1)) begin
-          $fatal; // @[VInst.scala 199:11]
+          $fatal; // @[VInst.scala 194:11]
         end
     `ifdef STOP_COND
       end
@@ -33848,8 +24541,8 @@
     `endif
         if (_T_2 & ~(_T_19 <= 3'h1)) begin
           $fwrite(32'h80000002,
-            "Assertion failed\n    at VInst.scala:199 assert(PopCount(Cat(p_x, p_xx, lp_xx, sp_xx, qp_xx, tp_xx)) <= 1.U)\n"
-            ); // @[VInst.scala 199:11]
+            "Assertion failed\n    at VInst.scala:194 assert(PopCount(Cat(p_x, p_xx, lp_xx, sp_xx, qp_xx, tp_xx)) <= 1.U)\n"
+            ); // @[VInst.scala 194:11]
         end
     `ifdef PRINTF_COND
       end
@@ -33860,7 +24553,7 @@
       if (`STOP_COND) begin
     `endif
         if (_T_2 & ~(_T_40 <= 3'h1)) begin
-          $fatal; // @[VInst.scala 199:11]
+          $fatal; // @[VInst.scala 194:11]
         end
     `ifdef STOP_COND
       end
@@ -33872,8 +24565,8 @@
     `endif
         if (_T_2 & ~(_T_40 <= 3'h1)) begin
           $fwrite(32'h80000002,
-            "Assertion failed\n    at VInst.scala:199 assert(PopCount(Cat(p_x, p_xx, lp_xx, sp_xx, qp_xx, tp_xx)) <= 1.U)\n"
-            ); // @[VInst.scala 199:11]
+            "Assertion failed\n    at VInst.scala:194 assert(PopCount(Cat(p_x, p_xx, lp_xx, sp_xx, qp_xx, tp_xx)) <= 1.U)\n"
+            ); // @[VInst.scala 194:11]
         end
     `ifdef PRINTF_COND
       end
@@ -33884,7 +24577,7 @@
       if (`STOP_COND) begin
     `endif
         if (_T_2 & ~(_T_61 <= 3'h1)) begin
-          $fatal; // @[VInst.scala 199:11]
+          $fatal; // @[VInst.scala 194:11]
         end
     `ifdef STOP_COND
       end
@@ -33896,8 +24589,8 @@
     `endif
         if (_T_2 & ~(_T_61 <= 3'h1)) begin
           $fwrite(32'h80000002,
-            "Assertion failed\n    at VInst.scala:199 assert(PopCount(Cat(p_x, p_xx, lp_xx, sp_xx, qp_xx, tp_xx)) <= 1.U)\n"
-            ); // @[VInst.scala 199:11]
+            "Assertion failed\n    at VInst.scala:194 assert(PopCount(Cat(p_x, p_xx, lp_xx, sp_xx, qp_xx, tp_xx)) <= 1.U)\n"
+            ); // @[VInst.scala 194:11]
         end
     `ifdef PRINTF_COND
       end
@@ -33908,7 +24601,7 @@
       if (`STOP_COND) begin
     `endif
         if (_T_2 & ~(_T_82 <= 3'h1)) begin
-          $fatal; // @[VInst.scala 199:11]
+          $fatal; // @[VInst.scala 194:11]
         end
     `ifdef STOP_COND
       end
@@ -33920,8 +24613,8 @@
     `endif
         if (_T_2 & ~(_T_82 <= 3'h1)) begin
           $fwrite(32'h80000002,
-            "Assertion failed\n    at VInst.scala:199 assert(PopCount(Cat(p_x, p_xx, lp_xx, sp_xx, qp_xx, tp_xx)) <= 1.U)\n"
-            ); // @[VInst.scala 199:11]
+            "Assertion failed\n    at VInst.scala:194 assert(PopCount(Cat(p_x, p_xx, lp_xx, sp_xx, qp_xx, tp_xx)) <= 1.U)\n"
+            ); // @[VInst.scala 194:11]
         end
     `ifdef PRINTF_COND
       end
@@ -33932,7 +24625,7 @@
       if (`STOP_COND) begin
     `endif
         if (_T_2 & ~(~(slice_io_in_valid & ~slice_io_in_ready))) begin
-          $fatal; // @[VInst.scala 257:9]
+          $fatal; // @[VInst.scala 252:9]
         end
     `ifdef STOP_COND
       end
@@ -33944,7 +24637,7 @@
     `endif
         if (_T_2 & ~(~(slice_io_in_valid & ~slice_io_in_ready))) begin
           $fwrite(32'h80000002,
-            "Assertion failed\n    at VInst.scala:257 assert(!(slice.io.in.valid && !slice.io.in.ready))\n"); // @[VInst.scala 257:9]
+            "Assertion failed\n    at VInst.scala:252 assert(!(slice.io.in.valid && !slice.io.in.ready))\n"); // @[VInst.scala 252:9]
         end
     `ifdef PRINTF_COND
       end
@@ -33955,7 +24648,7 @@
       if (`STOP_COND) begin
     `endif
         if (_T_2 & ~(~(vvalid & _T_108))) begin
-          $fatal; // @[VInst.scala 275:9]
+          $fatal; // @[VInst.scala 270:9]
         end
     `ifdef STOP_COND
       end
@@ -33966,7 +24659,7 @@
       if (`PRINTF_COND) begin
     `endif
         if (_T_2 & ~(~(vvalid & _T_108))) begin
-          $fwrite(32'h80000002,"Assertion failed\n    at VInst.scala:275 assert(!(vvalid && !slice.io.in.ready))\n"); // @[VInst.scala 275:9]
+          $fwrite(32'h80000002,"Assertion failed\n    at VInst.scala:270 assert(!(vvalid && !slice.io.in.ready))\n"); // @[VInst.scala 270:9]
         end
     `ifdef PRINTF_COND
       end
@@ -33974,182 +24667,154 @@
     `endif // SYNTHESIS
   end
   always @(posedge clock or posedge reset) begin
-    if (reset) begin // @[VInst.scala 143:55]
+    if (reset) begin // @[VInst.scala 139:55]
       vld_u_0 <= 1'h0;
     end else begin
       vld_u_0 <= _vld_o_0_T_1 & p;
     end
   end
   always @(posedge clock or posedge reset) begin
-    if (reset) begin // @[VInst.scala 143:55]
+    if (reset) begin // @[VInst.scala 139:55]
       vld_u_1 <= 1'h0;
     end else begin
       vld_u_1 <= _vld_o_1_T_1 & p_1;
     end
   end
   always @(posedge clock or posedge reset) begin
-    if (reset) begin // @[VInst.scala 143:55]
+    if (reset) begin // @[VInst.scala 139:55]
       vld_u_2 <= 1'h0;
     end else begin
       vld_u_2 <= _vld_o_2_T_1 & p_2;
     end
   end
   always @(posedge clock or posedge reset) begin
-    if (reset) begin // @[VInst.scala 143:55]
+    if (reset) begin // @[VInst.scala 139:55]
       vld_u_3 <= 1'h0;
     end else begin
       vld_u_3 <= _vld_o_3_T_1 & p_3;
     end
   end
   always @(posedge clock or posedge reset) begin
-    if (reset) begin // @[VInst.scala 145:61]
+    if (reset) begin // @[VInst.scala 141:61]
       vst_u_0 <= 1'h0;
     end else begin
       vst_u_0 <= _vst_o_0_T_1 & p & ~q;
     end
   end
   always @(posedge clock or posedge reset) begin
-    if (reset) begin // @[VInst.scala 145:61]
+    if (reset) begin // @[VInst.scala 141:61]
       vst_u_1 <= 1'h0;
     end else begin
       vst_u_1 <= _vst_o_1_T_1 & p_1 & ~q_1;
     end
   end
   always @(posedge clock or posedge reset) begin
-    if (reset) begin // @[VInst.scala 145:61]
+    if (reset) begin // @[VInst.scala 141:61]
       vst_u_2 <= 1'h0;
     end else begin
       vst_u_2 <= _vst_o_2_T_1 & p_2 & ~q_2;
     end
   end
   always @(posedge clock or posedge reset) begin
-    if (reset) begin // @[VInst.scala 145:61]
+    if (reset) begin // @[VInst.scala 141:61]
       vst_u_3 <= 1'h0;
     end else begin
       vst_u_3 <= _vst_o_3_T_1 & p_3 & ~q_3;
     end
   end
   always @(posedge clock or posedge reset) begin
-    if (reset) begin // @[VInst.scala 146:61]
+    if (reset) begin // @[VInst.scala 142:61]
       vst_q_0 <= 1'h0;
     end else begin
       vst_q_0 <= _vst_u_0_T_2 & q;
     end
   end
   always @(posedge clock or posedge reset) begin
-    if (reset) begin // @[VInst.scala 146:61]
+    if (reset) begin // @[VInst.scala 142:61]
       vst_q_1 <= 1'h0;
     end else begin
       vst_q_1 <= _vst_u_1_T_2 & q_1;
     end
   end
   always @(posedge clock or posedge reset) begin
-    if (reset) begin // @[VInst.scala 146:61]
+    if (reset) begin // @[VInst.scala 142:61]
       vst_q_2 <= 1'h0;
     end else begin
       vst_q_2 <= _vst_u_2_T_2 & q_2;
     end
   end
   always @(posedge clock or posedge reset) begin
-    if (reset) begin // @[VInst.scala 146:61]
+    if (reset) begin // @[VInst.scala 142:61]
       vst_q_3 <= 1'h0;
     end else begin
       vst_q_3 <= _vst_u_3_T_2 & q_3;
     end
   end
   always @(posedge clock or posedge reset) begin
-    if (reset) begin // @[VInst.scala 147:29]
-      vfop_0 <= 1'h0;
-    end else begin
-      vfop_0 <= reqvalid_0 & io_in_0_op[5];
-    end
-  end
-  always @(posedge clock or posedge reset) begin
-    if (reset) begin // @[VInst.scala 147:29]
-      vfop_1 <= 1'h0;
-    end else begin
-      vfop_1 <= reqvalid_1 & io_in_1_op[5];
-    end
-  end
-  always @(posedge clock or posedge reset) begin
-    if (reset) begin // @[VInst.scala 147:29]
-      vfop_2 <= 1'h0;
-    end else begin
-      vfop_2 <= reqvalid_2 & io_in_2_op[5];
-    end
-  end
-  always @(posedge clock or posedge reset) begin
-    if (reset) begin // @[VInst.scala 147:29]
-      vfop_3 <= 1'h0;
-    end else begin
-      vfop_3 <= reqvalid_3 & io_in_3_op[5];
-    end
-  end
-  always @(posedge clock or posedge reset) begin
-    if (reset) begin // @[VInst.scala 148:29]
+    if (reset) begin // @[VInst.scala 143:29]
       getvl_0 <= 1'h0;
     end else begin
       getvl_0 <= reqvalid_0 & io_in_0_op[0];
     end
   end
   always @(posedge clock or posedge reset) begin
-    if (reset) begin // @[VInst.scala 148:29]
+    if (reset) begin // @[VInst.scala 143:29]
       getvl_1 <= 1'h0;
     end else begin
       getvl_1 <= reqvalid_1 & io_in_1_op[0];
     end
   end
   always @(posedge clock or posedge reset) begin
-    if (reset) begin // @[VInst.scala 148:29]
+    if (reset) begin // @[VInst.scala 143:29]
       getvl_2 <= 1'h0;
     end else begin
       getvl_2 <= reqvalid_2 & io_in_2_op[0];
     end
   end
   always @(posedge clock or posedge reset) begin
-    if (reset) begin // @[VInst.scala 148:29]
+    if (reset) begin // @[VInst.scala 143:29]
       getvl_3 <= 1'h0;
     end else begin
       getvl_3 <= reqvalid_3 & io_in_3_op[0];
     end
   end
   always @(posedge clock or posedge reset) begin
-    if (reset) begin // @[VInst.scala 149:32]
+    if (reset) begin // @[VInst.scala 144:32]
       getmaxvl_0 <= 1'h0;
     end else begin
       getmaxvl_0 <= reqvalid_0 & io_in_0_op[1];
     end
   end
   always @(posedge clock or posedge reset) begin
-    if (reset) begin // @[VInst.scala 149:32]
+    if (reset) begin // @[VInst.scala 144:32]
       getmaxvl_1 <= 1'h0;
     end else begin
       getmaxvl_1 <= reqvalid_1 & io_in_1_op[1];
     end
   end
   always @(posedge clock or posedge reset) begin
-    if (reset) begin // @[VInst.scala 149:32]
+    if (reset) begin // @[VInst.scala 144:32]
       getmaxvl_2 <= 1'h0;
     end else begin
       getmaxvl_2 <= reqvalid_2 & io_in_2_op[1];
     end
   end
   always @(posedge clock or posedge reset) begin
-    if (reset) begin // @[VInst.scala 149:32]
+    if (reset) begin // @[VInst.scala 144:32]
       getmaxvl_3 <= 1'h0;
     end else begin
       getmaxvl_3 <= reqvalid_3 & io_in_3_op[1];
     end
   end
   always @(posedge clock or posedge reset) begin
-    if (reset) begin // @[VInst.scala 128:34]
+    if (reset) begin // @[VInst.scala 125:34]
       vvalid <= 1'h0;
     end else begin
       vvalid <= _vvalid_T != 4'h0;
     end
   end
   always @(posedge clock or posedge reset) begin
-    if (reset) begin // @[VInst.scala 283:38]
+    if (reset) begin // @[VInst.scala 278:38]
       nempty <= 1'h0;
     end else begin
       nempty <= _nempty_T_2 | vvalid | io_out_valid;
@@ -34216,57 +24881,49 @@
   _RAND_11 = {1{`RANDOM}};
   vst_q_3 = _RAND_11[0:0];
   _RAND_12 = {1{`RANDOM}};
-  vfop_0 = _RAND_12[0:0];
+  getvl_0 = _RAND_12[0:0];
   _RAND_13 = {1{`RANDOM}};
-  vfop_1 = _RAND_13[0:0];
+  getvl_1 = _RAND_13[0:0];
   _RAND_14 = {1{`RANDOM}};
-  vfop_2 = _RAND_14[0:0];
+  getvl_2 = _RAND_14[0:0];
   _RAND_15 = {1{`RANDOM}};
-  vfop_3 = _RAND_15[0:0];
+  getvl_3 = _RAND_15[0:0];
   _RAND_16 = {1{`RANDOM}};
-  getvl_0 = _RAND_16[0:0];
+  getmaxvl_0 = _RAND_16[0:0];
   _RAND_17 = {1{`RANDOM}};
-  getvl_1 = _RAND_17[0:0];
+  getmaxvl_1 = _RAND_17[0:0];
   _RAND_18 = {1{`RANDOM}};
-  getvl_2 = _RAND_18[0:0];
+  getmaxvl_2 = _RAND_18[0:0];
   _RAND_19 = {1{`RANDOM}};
-  getvl_3 = _RAND_19[0:0];
+  getmaxvl_3 = _RAND_19[0:0];
   _RAND_20 = {1{`RANDOM}};
-  getmaxvl_0 = _RAND_20[0:0];
+  rdAddr_0 = _RAND_20[4:0];
   _RAND_21 = {1{`RANDOM}};
-  getmaxvl_1 = _RAND_21[0:0];
+  rdAddr_1 = _RAND_21[4:0];
   _RAND_22 = {1{`RANDOM}};
-  getmaxvl_2 = _RAND_22[0:0];
+  rdAddr_2 = _RAND_22[4:0];
   _RAND_23 = {1{`RANDOM}};
-  getmaxvl_3 = _RAND_23[0:0];
+  rdAddr_3 = _RAND_23[4:0];
   _RAND_24 = {1{`RANDOM}};
-  rdAddr_0 = _RAND_24[4:0];
+  vvalid = _RAND_24[0:0];
   _RAND_25 = {1{`RANDOM}};
-  rdAddr_1 = _RAND_25[4:0];
+  vinstValid_0 = _RAND_25[0:0];
   _RAND_26 = {1{`RANDOM}};
-  rdAddr_2 = _RAND_26[4:0];
+  vinstValid_1 = _RAND_26[0:0];
   _RAND_27 = {1{`RANDOM}};
-  rdAddr_3 = _RAND_27[4:0];
+  vinstValid_2 = _RAND_27[0:0];
   _RAND_28 = {1{`RANDOM}};
-  vvalid = _RAND_28[0:0];
+  vinstValid_3 = _RAND_28[0:0];
   _RAND_29 = {1{`RANDOM}};
-  vinstValid_0 = _RAND_29[0:0];
+  vinstInst_0 = _RAND_29[31:0];
   _RAND_30 = {1{`RANDOM}};
-  vinstValid_1 = _RAND_30[0:0];
+  vinstInst_1 = _RAND_30[31:0];
   _RAND_31 = {1{`RANDOM}};
-  vinstValid_2 = _RAND_31[0:0];
+  vinstInst_2 = _RAND_31[31:0];
   _RAND_32 = {1{`RANDOM}};
-  vinstValid_3 = _RAND_32[0:0];
+  vinstInst_3 = _RAND_32[31:0];
   _RAND_33 = {1{`RANDOM}};
-  vinstInst_0 = _RAND_33[31:0];
-  _RAND_34 = {1{`RANDOM}};
-  vinstInst_1 = _RAND_34[31:0];
-  _RAND_35 = {1{`RANDOM}};
-  vinstInst_2 = _RAND_35[31:0];
-  _RAND_36 = {1{`RANDOM}};
-  vinstInst_3 = _RAND_36[31:0];
-  _RAND_37 = {1{`RANDOM}};
-  nempty = _RAND_37[0:0];
+  nempty = _RAND_33[0:0];
 `endif // RANDOMIZE_REG_INIT
   if (reset) begin
     vld_u_0 = 1'h0;
@@ -34305,18 +24962,6 @@
     vst_q_3 = 1'h0;
   end
   if (reset) begin
-    vfop_0 = 1'h0;
-  end
-  if (reset) begin
-    vfop_1 = 1'h0;
-  end
-  if (reset) begin
-    vfop_2 = 1'h0;
-  end
-  if (reset) begin
-    vfop_3 = 1'h0;
-  end
-  if (reset) begin
     getvl_0 = 1'h0;
   end
   if (reset) begin
@@ -36324,64 +26969,62 @@
   wire [5:0] vtbits = io_in_inst[25:20]; // @[VDecodeInstruction.scala 36:20]
   wire  quad = m & x; // @[VDecodeInstruction.scala 39:16]
   wire  uncached = io_in_addr[31]; // @[VDecodeInstruction.scala 41:22]
-  wire  vdup_bit = ~io_in_inst[31]; // @[Library.scala 310:19]
-  wire  vdup_bit_1 = io_in_inst[30]; // @[Library.scala 313:23]
-  wire  _vdup_T_1 = vdup_bit & vdup_bit_1; // @[Library.scala 314:48]
-  wire  vdup_bit_2 = ~io_in_inst[29]; // @[Library.scala 310:19]
-  wire  _vdup_T_2 = _vdup_T_1 & vdup_bit_2; // @[Library.scala 311:48]
-  wire  vdup_bit_3 = ~io_in_inst[28]; // @[Library.scala 310:19]
-  wire  vdup_bit_4 = ~io_in_inst[27]; // @[Library.scala 310:19]
-  wire  vdup_bit_5 = io_in_inst[26]; // @[Library.scala 316:23]
-  wire  vdup_bit_6 = ~io_in_inst[25]; // @[Library.scala 310:19]
-  wire  vdup_bit_7 = io_in_inst[24]; // @[Library.scala 316:23]
-  wire  vdup_bit_8 = io_in_inst[23]; // @[Library.scala 316:23]
-  wire  vdup_bit_9 = io_in_inst[22]; // @[Library.scala 316:23]
-  wire  vdup_bit_10 = io_in_inst[21]; // @[Library.scala 316:23]
-  wire  vdup_bit_11 = io_in_inst[20]; // @[Library.scala 316:23]
-  wire  vdup_bit_12 = ~io_in_inst[19]; // @[Library.scala 310:19]
-  wire  vdup_bit_13 = ~io_in_inst[18]; // @[Library.scala 310:19]
-  wire  vdup_bit_14 = ~io_in_inst[17]; // @[Library.scala 310:19]
-  wire  vdup_bit_15 = ~io_in_inst[16]; // @[Library.scala 310:19]
-  wire  vdup_bit_16 = ~io_in_inst[15]; // @[Library.scala 310:19]
-  wire  vdup_bit_17 = ~io_in_inst[14]; // @[Library.scala 310:19]
+  wire  vdup_bit = ~io_in_inst[31]; // @[Library.scala 312:19]
+  wire  vdup_bit_1 = io_in_inst[30]; // @[Library.scala 315:23]
+  wire  _vdup_T_1 = vdup_bit & vdup_bit_1; // @[Library.scala 316:48]
+  wire  vdup_bit_2 = ~io_in_inst[29]; // @[Library.scala 312:19]
+  wire  _vdup_T_2 = _vdup_T_1 & vdup_bit_2; // @[Library.scala 313:48]
+  wire  vdup_bit_3 = ~io_in_inst[28]; // @[Library.scala 312:19]
+  wire  vdup_bit_4 = ~io_in_inst[27]; // @[Library.scala 312:19]
+  wire  vdup_bit_5 = io_in_inst[26]; // @[Library.scala 318:23]
+  wire  vdup_bit_6 = ~io_in_inst[25]; // @[Library.scala 312:19]
+  wire  vdup_bit_7 = io_in_inst[24]; // @[Library.scala 318:23]
+  wire  vdup_bit_8 = io_in_inst[23]; // @[Library.scala 318:23]
+  wire  vdup_bit_9 = io_in_inst[22]; // @[Library.scala 318:23]
+  wire  vdup_bit_10 = io_in_inst[21]; // @[Library.scala 318:23]
+  wire  vdup_bit_11 = io_in_inst[20]; // @[Library.scala 318:23]
+  wire  vdup_bit_12 = ~io_in_inst[19]; // @[Library.scala 312:19]
+  wire  vdup_bit_13 = ~io_in_inst[18]; // @[Library.scala 312:19]
+  wire  vdup_bit_14 = ~io_in_inst[17]; // @[Library.scala 312:19]
+  wire  vdup_bit_15 = ~io_in_inst[16]; // @[Library.scala 312:19]
+  wire  vdup_bit_16 = ~io_in_inst[15]; // @[Library.scala 312:19]
+  wire  vdup_bit_17 = ~io_in_inst[14]; // @[Library.scala 312:19]
   wire  _vdup_T_11 = _vdup_T_1 & vdup_bit_2 & vdup_bit_3 & vdup_bit_4 & vdup_bit_6 & vdup_bit_12 & vdup_bit_13 &
-    vdup_bit_14 & vdup_bit_15 & vdup_bit_16 & vdup_bit_17; // @[Library.scala 311:48]
-  wire  vdup_bit_18 = io_in_inst[13]; // @[Library.scala 316:23]
-  wire  vdup_bit_19 = io_in_inst[12]; // @[Library.scala 316:23]
-  wire  vdup_bit_27 = io_in_inst[4]; // @[Library.scala 313:23]
-  wire  vdup_bit_28 = io_in_inst[3]; // @[Library.scala 313:23]
-  wire  _vdup_T_16 = _vdup_T_11 & vdup_bit_27 & vdup_bit_28 & x3 & x & v; // @[Library.scala 314:48]
-  wire  _vdup_T_17 = sz < 2'h3; // @[VDecodeInstruction.scala 233:80]
-  wire  vdup = _vdup_T_16 & sz < 2'h3; // @[VDecodeInstruction.scala 233:74]
-  wire  vdupf2 = io_in_inst[31:27] == 5'h8; // @[VDecodeInstruction.scala 234:28]
-  wire  _vldstdec_T_1 = vdup_bit_6 & vdup_bit_17; // @[Library.scala 311:48]
-  wire  _vldstdec_T_6 = _vldstdec_T_1 & vdup_bit_27 & vdup_bit_28 & x3 & x & v; // @[Library.scala 314:48]
-  wire  vldstdec = _vldstdec_T_6 & _vdup_T_17 & ~vdupf2; // @[VDecodeInstruction.scala 237:90]
-  wire  _T_3 = ~reset; // @[VDecodeInstruction.scala 238:9]
-  wire  _vld_T = func2 == 6'h0; // @[VDecodeInstruction.scala 240:33]
-  wire  _vld_T_1 = func2 == 6'h1; // @[VDecodeInstruction.scala 240:50]
-  wire  _vld_T_3 = func2 == 6'h2; // @[VDecodeInstruction.scala 240:67]
-  wire  _vld_T_5 = func2 == 6'h4; // @[VDecodeInstruction.scala 241:33]
-  wire  _vld_T_6 = func2 == 6'h0 | func2 == 6'h1 | func2 == 6'h2 | _vld_T_5; // @[VDecodeInstruction.scala 240:75]
-  wire  _vld_T_7 = func2 == 6'h5; // @[VDecodeInstruction.scala 241:50]
-  wire  _vld_T_9 = func2 == 6'h6; // @[VDecodeInstruction.scala 241:67]
-  wire  _vld_T_11 = func2 == 6'h7; // @[VDecodeInstruction.scala 242:33]
-  wire  _vld_T_12 = _vld_T_6 | func2 == 6'h5 | func2 == 6'h6 | _vld_T_11; // @[VDecodeInstruction.scala 241:75]
-  wire  vld = vldstdec & _vld_T_12; // @[VDecodeInstruction.scala 240:23]
-  wire  _vst_T = func2 == 6'h8; // @[VDecodeInstruction.scala 244:33]
-  wire  _vst_T_1 = func2 == 6'h9; // @[VDecodeInstruction.scala 244:50]
-  wire  _vst_T_3 = func2 == 6'ha; // @[VDecodeInstruction.scala 244:67]
-  wire  _vst_T_5 = func2 == 6'hc; // @[VDecodeInstruction.scala 245:33]
-  wire  _vst_T_6 = func2 == 6'h8 | func2 == 6'h9 | func2 == 6'ha | _vst_T_5; // @[VDecodeInstruction.scala 244:76]
-  wire  _vst_T_7 = func2 == 6'hd; // @[VDecodeInstruction.scala 245:51]
-  wire  _vst_T_9 = func2 == 6'he; // @[VDecodeInstruction.scala 245:69]
-  wire  _vst_T_11 = func2 == 6'hf; // @[VDecodeInstruction.scala 246:33]
-  wire  _vst_T_12 = _vst_T_6 | func2 == 6'hd | func2 == 6'he | _vst_T_11; // @[VDecodeInstruction.scala 245:78]
-  wire  vst = vldstdec & _vst_T_12; // @[VDecodeInstruction.scala 244:23]
-  wire  _vstq_T = func2 == 6'h1a; // @[VDecodeInstruction.scala 248:33]
-  wire  vstq = vldstdec & (func2 == 6'h1a | func2 == 6'h1e); // @[VDecodeInstruction.scala 248:23]
-  wire  vldst = vld | vst | vstq; // @[VDecodeInstruction.scala 250:26]
-  wire  _vadd_T = ~v; // @[VDecodeInstruction.scala 46:7]
+    vdup_bit_14 & vdup_bit_15 & vdup_bit_16 & vdup_bit_17; // @[Library.scala 313:48]
+  wire  vdup_bit_18 = io_in_inst[13]; // @[Library.scala 318:23]
+  wire  vdup_bit_19 = io_in_inst[12]; // @[Library.scala 318:23]
+  wire  vdup_bit_27 = io_in_inst[4]; // @[Library.scala 315:23]
+  wire  vdup_bit_28 = io_in_inst[3]; // @[Library.scala 315:23]
+  wire  _vdup_T_16 = _vdup_T_11 & vdup_bit_27 & vdup_bit_28 & x3 & x & v; // @[Library.scala 316:48]
+  wire  _vdup_T_17 = sz < 2'h3; // @[VDecodeInstruction.scala 228:80]
+  wire  vdup = _vdup_T_16 & sz < 2'h3; // @[VDecodeInstruction.scala 228:74]
+  wire  vdupf2 = io_in_inst[31:27] == 5'h8; // @[VDecodeInstruction.scala 229:28]
+  wire  _vldstdec_T_1 = vdup_bit_6 & vdup_bit_17; // @[Library.scala 313:48]
+  wire  _vldstdec_T_6 = _vldstdec_T_1 & vdup_bit_27 & vdup_bit_28 & x3 & x & v; // @[Library.scala 316:48]
+  wire  vldstdec = _vldstdec_T_6 & _vdup_T_17 & ~vdupf2; // @[VDecodeInstruction.scala 232:90]
+  wire  _T_3 = ~reset; // @[VDecodeInstruction.scala 233:9]
+  wire  _vld_T = func2 == 6'h0; // @[VDecodeInstruction.scala 235:33]
+  wire  _vld_T_1 = func2 == 6'h1; // @[VDecodeInstruction.scala 235:50]
+  wire  _vld_T_3 = func2 == 6'h2; // @[VDecodeInstruction.scala 235:67]
+  wire  _vld_T_5 = func2 == 6'h4; // @[VDecodeInstruction.scala 236:33]
+  wire  _vld_T_6 = func2 == 6'h0 | func2 == 6'h1 | func2 == 6'h2 | _vld_T_5; // @[VDecodeInstruction.scala 235:75]
+  wire  _vld_T_7 = func2 == 6'h5; // @[VDecodeInstruction.scala 236:50]
+  wire  _vld_T_9 = func2 == 6'h6; // @[VDecodeInstruction.scala 236:67]
+  wire  _vld_T_11 = func2 == 6'h7; // @[VDecodeInstruction.scala 237:33]
+  wire  _vld_T_12 = _vld_T_6 | func2 == 6'h5 | func2 == 6'h6 | _vld_T_11; // @[VDecodeInstruction.scala 236:75]
+  wire  vld = vldstdec & _vld_T_12; // @[VDecodeInstruction.scala 235:23]
+  wire  _vst_T = func2 == 6'h8; // @[VDecodeInstruction.scala 239:33]
+  wire  _vst_T_1 = func2 == 6'h9; // @[VDecodeInstruction.scala 239:50]
+  wire  _vst_T_3 = func2 == 6'ha; // @[VDecodeInstruction.scala 239:67]
+  wire  _vst_T_5 = func2 == 6'hc; // @[VDecodeInstruction.scala 240:33]
+  wire  _vst_T_6 = func2 == 6'h8 | func2 == 6'h9 | func2 == 6'ha | _vst_T_5; // @[VDecodeInstruction.scala 239:76]
+  wire  _vst_T_7 = func2 == 6'hd; // @[VDecodeInstruction.scala 240:51]
+  wire  _vst_T_11 = func2 == 6'hf; // @[VDecodeInstruction.scala 241:33]
+  wire  _vst_T_12 = _vst_T_6 | func2 == 6'hd | func2 == 6'he | _vst_T_11; // @[VDecodeInstruction.scala 240:78]
+  wire  vst = vldstdec & _vst_T_12; // @[VDecodeInstruction.scala 239:23]
+  wire  _vstq_T = func2 == 6'h1a; // @[VDecodeInstruction.scala 243:33]
+  wire  vstq = vldstdec & (func2 == 6'h1a | func2 == 6'h1e); // @[VDecodeInstruction.scala 243:23]
+  wire  vldst = vld | vst | vstq; // @[VDecodeInstruction.scala 245:26]
   wire  vadd = ~v & func1 == 3'h0 & _vld_T & _vdup_T_17; // @[VDecodeInstruction.scala 46:65]
   wire  vsub = ~v & func1 == 3'h0 & _vld_T_1 & _vdup_T_17; // @[VDecodeInstruction.scala 46:65]
   wire  vrsub = ~v & func1 == 3'h0 & _vld_T_3 & _vdup_T_17; // @[VDecodeInstruction.scala 46:65]
@@ -36395,13 +27038,11 @@
   wire  vabsd = ~v & func1 == 3'h0 & _vlt_T_3 == 6'h10 & _vdup_T_17; // @[VDecodeInstruction.scala 46:65]
   wire  vmax = ~v & func1 == 3'h0 & _vlt_T_3 == 6'h12 & _vdup_T_17; // @[VDecodeInstruction.scala 46:65]
   wire  vmin = ~v & func1 == 3'h0 & _vlt_T_3 == 6'h14 & _vdup_T_17; // @[VDecodeInstruction.scala 46:65]
-  wire  _vadd3_T_5 = func2 == 6'h18; // @[VDecodeInstruction.scala 46:49]
   wire  vadd3 = ~v & func1 == 3'h0 & func2 == 6'h18 & _vdup_T_17; // @[VDecodeInstruction.scala 46:65]
-  wire  vfmt0 = vadd | vsub | vrsub | veq | vne | vlt | vle | vgt | vge | vabsd | vmax | vmin | vadd3; // @[VDecodeInstruction.scala 267:104]
+  wire  vfmt0 = vadd | vsub | vrsub | veq | vne | vlt | vle | vgt | vge | vabsd | vmax | vmin | vadd3; // @[VDecodeInstruction.scala 262:104]
   wire  vand = ~v & func1 == 3'h1 & _vld_T & _vdup_T_17; // @[VDecodeInstruction.scala 46:65]
   wire  vor = ~v & func1 == 3'h1 & _vld_T_1 & _vdup_T_17; // @[VDecodeInstruction.scala 46:65]
   wire  vxor = ~v & func1 == 3'h1 & _vld_T_3 & _vdup_T_17; // @[VDecodeInstruction.scala 46:65]
-  wire  _vnot_T_5 = func2 == 6'h3; // @[VDecodeInstruction.scala 46:49]
   wire  vnot = ~v & func1 == 3'h1 & func2 == 6'h3 & _vdup_T_17; // @[VDecodeInstruction.scala 46:65]
   wire  vrev = ~v & func1 == 3'h1 & _vld_T_5 & _vdup_T_17; // @[VDecodeInstruction.scala 46:65]
   wire  vror = ~v & func1 == 3'h1 & _vld_T_7 & _vdup_T_17; // @[VDecodeInstruction.scala 46:65]
@@ -36409,20 +27050,17 @@
   wire  vclz = ~v & func1 == 3'h1 & _vst_T_1 & _vdup_T_17; // @[VDecodeInstruction.scala 46:65]
   wire  vcpop = ~v & func1 == 3'h1 & _vst_T_3 & _vdup_T_17; // @[VDecodeInstruction.scala 46:65]
   wire  _vmv_T_8 = ~v & func1 == 3'h1 & _vst_T_5 & _vdup_T_17; // @[VDecodeInstruction.scala 46:65]
-  wire  _vmv_T_9 = ~quad; // @[VDecodeInstruction.scala 279:40]
-  wire  vmv = _vmv_T_8 & ~quad; // @[VDecodeInstruction.scala 279:37]
-  wire  vmv2 = _vmv_T_8 & quad; // @[VDecodeInstruction.scala 280:37]
+  wire  _vmv_T_9 = ~quad; // @[VDecodeInstruction.scala 274:40]
+  wire  vmv = _vmv_T_8 & ~quad; // @[VDecodeInstruction.scala 274:37]
+  wire  vmv2 = _vmv_T_8 & quad; // @[VDecodeInstruction.scala 275:37]
   wire  vmvp = ~v & func1 == 3'h1 & _vst_T_7 & _vdup_T_17; // @[VDecodeInstruction.scala 46:65]
-  wire  vfmt1 = vand | vor | vxor | vnot | vrev | vror | vclb | vclz | vcpop | vmv | vmv2 | vmvp; // @[VDecodeInstruction.scala 283:99]
-  wire  _acset_T_5 = func2 == 6'h10; // @[VDecodeInstruction.scala 46:49]
+  wire  vfmt1 = vand | vor | vxor | vnot | vrev | vror | vclb | vclz | vcpop | vmv | vmv2 | vmvp; // @[VDecodeInstruction.scala 278:99]
   wire  _acset_T_8 = ~v & func1 == 3'h1 & func2 == 6'h10 & _vdup_T_17; // @[VDecodeInstruction.scala 46:65]
-  wire  _acset_T_10 = ~m; // @[VDecodeInstruction.scala 286:49]
-  wire  _acset_T_12 = vtbits == 6'h0; // @[VDecodeInstruction.scala 286:62]
-  wire  acset = _acset_T_8 & x & ~m & vtbits == 6'h0; // @[VDecodeInstruction.scala 286:52]
-  wire  _actr_T_5 = func2 == 6'h11; // @[VDecodeInstruction.scala 46:49]
+  wire  _acset_T_10 = ~m; // @[VDecodeInstruction.scala 281:49]
+  wire  _acset_T_12 = vtbits == 6'h0; // @[VDecodeInstruction.scala 281:62]
+  wire  acset = _acset_T_8 & x & ~m & vtbits == 6'h0; // @[VDecodeInstruction.scala 281:52]
   wire  _actr_T_8 = ~v & func1 == 3'h1 & func2 == 6'h11 & _vdup_T_17; // @[VDecodeInstruction.scala 46:65]
-  wire  actr = _actr_T_8 & x & _acset_T_10 & _acset_T_12; // @[VDecodeInstruction.scala 287:52]
-  wire  _adwinit_T_5 = func2 == 6'h12; // @[VDecodeInstruction.scala 46:49]
+  wire  actr = _actr_T_8 & x & _acset_T_10 & _acset_T_12; // @[VDecodeInstruction.scala 282:52]
   wire  adwinit = ~v & func1 == 3'h1 & func2 == 6'h12 & _vdup_T_17; // @[VDecodeInstruction.scala 46:65]
   wire  vsll = ~v & func1 == 3'h2 & _vld_T_1 & _vdup_T_17; // @[VDecodeInstruction.scala 46:65]
   wire  vsra = ~v & func1 == 3'h2 & _vld_T_3 & _vdup_T_17; // @[VDecodeInstruction.scala 46:65]
@@ -36433,29 +27071,27 @@
   wire [5:0] _vsrans_T_3 = func2 & 6'h3c; // @[VDecodeInstruction.scala 46:43]
   wire  vsrans = ~v & func1 == 3'h2 & _vsrans_T_3 == 6'h10 & _vdup_T_17; // @[VDecodeInstruction.scala 46:65]
   wire  vsraqs = ~v & func1 == 3'h2 & _vsrans_T_3 == 6'h18 & _vdup_T_17; // @[VDecodeInstruction.scala 46:65]
-  wire  vfmt2 = vsll | vsra | vsrl | vsha | vshl | vsrans | vsraqs; // @[VDecodeInstruction.scala 299:62]
+  wire  vfmt2 = vsll | vsra | vsrl | vsha | vshl | vsrans | vsraqs; // @[VDecodeInstruction.scala 294:62]
   wire  _vmul_T_8 = ~v & func1 == 3'h3 & _vld_T & _vdup_T_17; // @[VDecodeInstruction.scala 46:65]
-  wire  vmul = _vmul_T_8 & _vmv_T_9; // @[VDecodeInstruction.scala 302:40]
-  wire  vmul2 = _vmul_T_8 & quad; // @[VDecodeInstruction.scala 303:40]
+  wire  vmul = _vmul_T_8 & _vmv_T_9; // @[VDecodeInstruction.scala 297:40]
+  wire  vmul2 = _vmul_T_8 & quad; // @[VDecodeInstruction.scala 298:40]
   wire  _vmuls_T_8 = ~v & func1 == 3'h3 & _vlt_T_3 == 6'h2 & _vdup_T_17; // @[VDecodeInstruction.scala 46:65]
-  wire  vmuls = _vmuls_T_8 & _vmv_T_9; // @[VDecodeInstruction.scala 304:44]
-  wire  vmuls2 = _vmuls_T_8 & quad; // @[VDecodeInstruction.scala 305:44]
+  wire  vmuls = _vmuls_T_8 & _vmv_T_9; // @[VDecodeInstruction.scala 299:44]
+  wire  vmuls2 = _vmuls_T_8 & quad; // @[VDecodeInstruction.scala 300:44]
   wire  _vmulh_T_8 = ~v & func1 == 3'h3 & _vsha_T_3 == 6'h8 & _vdup_T_17; // @[VDecodeInstruction.scala 46:65]
-  wire  vmulh = _vmulh_T_8 & _vmv_T_9; // @[VDecodeInstruction.scala 306:44]
-  wire  vmulh2 = _vmulh_T_8 & quad; // @[VDecodeInstruction.scala 307:44]
+  wire  vmulh = _vmulh_T_8 & _vmv_T_9; // @[VDecodeInstruction.scala 301:44]
+  wire  vmulh2 = _vmulh_T_8 & quad; // @[VDecodeInstruction.scala 302:44]
   wire  _vmulhu_T_8 = ~v & func1 == 3'h3 & _vsha_T_3 == 6'h9 & _vdup_T_17; // @[VDecodeInstruction.scala 46:65]
-  wire  vmulhu = _vmulhu_T_8 & _vmv_T_9; // @[VDecodeInstruction.scala 308:45]
-  wire  vmulhu2 = _vmulhu_T_8 & quad; // @[VDecodeInstruction.scala 309:45]
+  wire  vmulhu = _vmulhu_T_8 & _vmv_T_9; // @[VDecodeInstruction.scala 303:45]
+  wire  vmulhu2 = _vmulhu_T_8 & quad; // @[VDecodeInstruction.scala 304:45]
   wire  _vdmulh_T_8 = ~v & func1 == 3'h3 & _vsrans_T_3 == 6'h10 & _vdup_T_17; // @[VDecodeInstruction.scala 46:65]
-  wire  vdmulh = _vdmulh_T_8 & _vmv_T_9; // @[VDecodeInstruction.scala 310:45]
-  wire  vdmulh2 = _vdmulh_T_8 & quad; // @[VDecodeInstruction.scala 311:45]
+  wire  vdmulh = _vdmulh_T_8 & _vmv_T_9; // @[VDecodeInstruction.scala 305:45]
+  wire  vdmulh2 = _vdmulh_T_8 & quad; // @[VDecodeInstruction.scala 306:45]
   wire  vmulw = ~v & func1 == 3'h3 & _vlt_T_3 == 6'h4 & _vdup_T_17; // @[VDecodeInstruction.scala 46:65]
   wire  vmacc = ~v & func1 == 3'h3 & func2 == 6'h14 & _vdup_T_17; // @[VDecodeInstruction.scala 46:65]
   wire  vmadd = ~v & func1 == 3'h3 & func2 == 6'h15 & _vdup_T_17; // @[VDecodeInstruction.scala 46:65]
-  wire  vdiv = ~v & func1 == 3'h3 & _vlt_T_3 == 6'h18 & _vdup_T_17; // @[VDecodeInstruction.scala 46:65]
-  wire  vrem = ~v & func1 == 3'h3 & _vlt_T_3 == 6'h1a & _vdup_T_17; // @[VDecodeInstruction.scala 46:65]
   wire  vfmt3 = vmul | vmul2 | vmuls | vmuls2 | vmulh | vmulh2 | vmulhu | vmulhu2 | vdmulh | vdmulh2 | vmulw | vmacc |
-    vmadd | vdiv | vrem; // @[VDecodeInstruction.scala 318:144]
+    vmadd; // @[VDecodeInstruction.scala 311:127]
   wire  vadds = ~v & func1 == 3'h4 & _vlt_T_3 == 6'h0 & _vdup_T_17; // @[VDecodeInstruction.scala 46:65]
   wire  vsubs = ~v & func1 == 3'h4 & _vlt_T_3 == 6'h2 & _vdup_T_17; // @[VDecodeInstruction.scala 46:65]
   wire  vaddw = ~v & func1 == 3'h4 & _vlt_T_3 == 6'h4 & _vdup_T_17; // @[VDecodeInstruction.scala 46:65]
@@ -36465,111 +27101,65 @@
   wire  vpsub = ~v & func1 == 3'h4 & _vlt_T_3 == 6'he & _vdup_T_17; // @[VDecodeInstruction.scala 46:65]
   wire  vhadd = ~v & func1 == 3'h4 & _vsrans_T_3 == 6'h10 & _vdup_T_17; // @[VDecodeInstruction.scala 46:65]
   wire  vhsub = ~v & func1 == 3'h4 & _vsrans_T_3 == 6'h14 & _vdup_T_17; // @[VDecodeInstruction.scala 46:65]
-  wire  vfmt4 = vadds | vsubs | vaddw | vsubw | vacc | vpadd | vpsub | vhadd | vhsub; // @[VDecodeInstruction.scala 331:83]
-  wire  _vfadd_T_5 = sz == 2'h2; // @[VDecodeInstruction.scala 51:56]
-  wire  vfadd = _vadd_T & func1 == 3'h5 & _vld_T & sz == 2'h2; // @[VDecodeInstruction.scala 51:50]
-  wire  vfsub = _vadd_T & func1 == 3'h5 & _vld_T_1 & sz == 2'h2; // @[VDecodeInstruction.scala 51:50]
-  wire  vfmul = _vadd_T & func1 == 3'h5 & _vld_T_3 & sz == 2'h2; // @[VDecodeInstruction.scala 51:50]
-  wire  vfabsd = _vadd_T & func1 == 3'h5 & _vnot_T_5 & sz == 2'h2; // @[VDecodeInstruction.scala 51:50]
-  wire  vfmadd = _vadd_T & func1 == 3'h5 & _vld_T_5 & sz == 2'h2; // @[VDecodeInstruction.scala 51:50]
-  wire  vfmsub = _vadd_T & func1 == 3'h5 & _vld_T_7 & sz == 2'h2; // @[VDecodeInstruction.scala 51:50]
-  wire  vfnmsub = _vadd_T & func1 == 3'h5 & _vld_T_9 & sz == 2'h2; // @[VDecodeInstruction.scala 51:50]
-  wire  vfnmadd = _vadd_T & func1 == 3'h5 & _vld_T_11 & sz == 2'h2; // @[VDecodeInstruction.scala 51:50]
-  wire  vfdiv = _vadd_T & func1 == 3'h5 & _vst_T & sz == 2'h2; // @[VDecodeInstruction.scala 51:50]
-  wire  vfrdiv = _vadd_T & func1 == 3'h5 & _vst_T_1 & sz == 2'h2; // @[VDecodeInstruction.scala 51:50]
-  wire  vfsqrt = _vadd_T & func1 == 3'h5 & _vst_T_3 & sz == 2'h2; // @[VDecodeInstruction.scala 51:50]
-  wire  vfsgnj = _vadd_T & func1 == 3'h5 & func2 == 6'hb & sz == 2'h2; // @[VDecodeInstruction.scala 51:50]
-  wire  vfsgnjn = _vadd_T & func1 == 3'h5 & _vst_T_5 & sz == 2'h2; // @[VDecodeInstruction.scala 51:50]
-  wire  vfsgnjx = _vadd_T & func1 == 3'h5 & _vst_T_7 & sz == 2'h2; // @[VDecodeInstruction.scala 51:50]
-  wire  vfmin = _vadd_T & func1 == 3'h5 & _vst_T_9 & sz == 2'h2; // @[VDecodeInstruction.scala 51:50]
-  wire  vfmax = _vadd_T & func1 == 3'h5 & _vst_T_11 & sz == 2'h2; // @[VDecodeInstruction.scala 51:50]
-  wire  vfcvt_s_w = _vadd_T & func1 == 3'h5 & _acset_T_5 & sz == 2'h2; // @[VDecodeInstruction.scala 51:50]
-  wire  vfcvt_s_wu = _vadd_T & func1 == 3'h5 & _actr_T_5 & sz == 2'h2; // @[VDecodeInstruction.scala 51:50]
-  wire  vfcvt_w_s = _vadd_T & func1 == 3'h5 & _adwinit_T_5 & sz == 2'h2; // @[VDecodeInstruction.scala 51:50]
-  wire  vfcvt_wu_s = _vadd_T & func1 == 3'h5 & func2 == 6'h13 & sz == 2'h2; // @[VDecodeInstruction.scala 51:50]
-  wire  vflt = _vadd_T & func1 == 3'h5 & _vadd3_T_5 & sz == 2'h2; // @[VDecodeInstruction.scala 51:50]
-  wire  _vfle_T_3 = func2 == 6'h19; // @[VDecodeInstruction.scala 51:41]
-  wire  vfle = _vadd_T & func1 == 3'h5 & func2 == 6'h19 & sz == 2'h2; // @[VDecodeInstruction.scala 51:50]
-  wire  vfgt = _vadd_T & func1 == 3'h5 & _vstq_T & sz == 2'h2; // @[VDecodeInstruction.scala 51:50]
-  wire  vfge = _vadd_T & func1 == 3'h5 & func2 == 6'h1b & sz == 2'h2; // @[VDecodeInstruction.scala 51:50]
-  wire  _vfeq_T_3 = func2 == 6'h1c; // @[VDecodeInstruction.scala 51:41]
-  wire  vfeq = _vadd_T & func1 == 3'h5 & func2 == 6'h1c & sz == 2'h2; // @[VDecodeInstruction.scala 51:50]
-  wire  vfne = _vadd_T & func1 == 3'h5 & func2 == 6'h1d & sz == 2'h2; // @[VDecodeInstruction.scala 51:50]
-  wire  vfmt5 = vfadd | vfsub | vfmul | vfabsd | vfmadd | vfmsub | vfnmsub | vfnmadd | vfdiv | vfrdiv | vfsqrt | vfsgnj
-     | vfsgnjn | vfsgnjx | vfmin | vfmax | vfcvt_s_w | vfcvt_s_wu | vfcvt_w_s | vfcvt_wu_s | vflt | vfle | vfgt | vfge
-     | vfeq | vfne; // @[VDecodeInstruction.scala 361:240]
+  wire  vfmt4 = vadds | vsubs | vaddw | vsubw | vacc | vpadd | vpsub | vhadd | vhsub; // @[VDecodeInstruction.scala 324:83]
   wire  vslidevn = ~v & func1 == 3'h6 & _vsrans_T_3 == 6'h0 & _vdup_T_17; // @[VDecodeInstruction.scala 46:65]
   wire  _vslidehn_T_8 = ~v & func1 == 3'h6 & _vsrans_T_3 == 6'h4 & _vdup_T_17; // @[VDecodeInstruction.scala 46:65]
-  wire  vslidehn = _vslidehn_T_8 & _acset_T_10; // @[VDecodeInstruction.scala 365:49]
-  wire  vslidehn2 = _vslidehn_T_8 & m; // @[VDecodeInstruction.scala 366:49]
+  wire  vslidehn = _vslidehn_T_8 & _acset_T_10; // @[VDecodeInstruction.scala 328:49]
+  wire  vslidehn2 = _vslidehn_T_8 & m; // @[VDecodeInstruction.scala 329:49]
   wire  vslidevp = ~v & func1 == 3'h6 & _vsrans_T_3 == 6'h8 & _vdup_T_17; // @[VDecodeInstruction.scala 46:65]
   wire  _vslidehp_T_8 = ~v & func1 == 3'h6 & _vsrans_T_3 == 6'hc & _vdup_T_17; // @[VDecodeInstruction.scala 46:65]
-  wire  vslidehp = _vslidehp_T_8 & _acset_T_10; // @[VDecodeInstruction.scala 368:49]
-  wire  vslidehp2 = _vslidehp_T_8 & m; // @[VDecodeInstruction.scala 369:49]
+  wire  vslidehp = _vslidehp_T_8 & _acset_T_10; // @[VDecodeInstruction.scala 331:49]
+  wire  vslidehp2 = _vslidehp_T_8 & m; // @[VDecodeInstruction.scala 332:49]
   wire  vsel = ~v & func1 == 3'h6 & func2 == 6'h10 & _vdup_T_17; // @[VDecodeInstruction.scala 46:65]
   wire  vevn = ~v & func1 == 3'h6 & func2 == 6'h18 & _vdup_T_17; // @[VDecodeInstruction.scala 46:65]
-  wire  vodd = ~v & func1 == 3'h6 & _vfle_T_3 & _vdup_T_17; // @[VDecodeInstruction.scala 46:65]
+  wire  vodd = ~v & func1 == 3'h6 & func2 == 6'h19 & _vdup_T_17; // @[VDecodeInstruction.scala 46:65]
   wire  vevnodd = ~v & func1 == 3'h6 & _vstq_T & _vdup_T_17; // @[VDecodeInstruction.scala 46:65]
-  wire  vzip = ~v & func1 == 3'h6 & _vfeq_T_3 & _vdup_T_17; // @[VDecodeInstruction.scala 46:65]
-  wire  vslideh2 = vslidehn2 | vslidehp2; // @[VDecodeInstruction.scala 376:28]
-  wire  vevn3 = vevn | vevnodd | vodd; // @[VDecodeInstruction.scala 377:31]
-  wire  vfmt6 = vslidevn | vslidehn | vslidehn2 | vslidevp | vslidehp | vslidehp2 | vsel | vevn | vodd | vevnodd | vzip; // @[VDecodeInstruction.scala 379:112]
-  wire  vfmadd4_bit_18 = ~vdup_bit_18; // @[Library.scala 310:19]
-  wire  vfmadd4_bit_19 = ~vdup_bit_19; // @[Library.scala 310:19]
-  wire  vfmadd4_bit_27 = ~vdup_bit_27; // @[Library.scala 310:19]
-  wire  vfmadd4_bit_28 = ~vdup_bit_28; // @[Library.scala 310:19]
-  wire  vfmadd4_bit_30 = ~x; // @[Library.scala 310:19]
-  wire  _vfmadd4_T_4 = vfmadd4_bit_18 & vfmadd4_bit_19 & vfmadd4_bit_27 & vfmadd4_bit_28 & vfmadd4_bit_30; // @[Library.scala 311:48]
-  wire  _vfmadd4_T_5 = _vfmadd4_T_4 & v; // @[Library.scala 314:48]
-  wire  vfmadd4 = _vfmadd4_T_5 & ~(x3 & io_in_inst[25]); // @[VDecodeInstruction.scala 382:77]
-  wire  _aconv_T_1 = io_in_inst[25] & vdup_bit_18; // @[Library.scala 314:48]
-  wire  _aconv_T_2 = _aconv_T_1 & vfmadd4_bit_19; // @[Library.scala 311:48]
-  wire  _aconv_T_5 = _aconv_T_1 & vfmadd4_bit_19 & _acset_T_10 & vfmadd4_bit_27 & vfmadd4_bit_28; // @[Library.scala 311:48]
-  wire  _aconv_T_6 = _aconv_T_5 & x3; // @[Library.scala 314:48]
-  wire  _aconv_T_7 = _aconv_T_6 & vfmadd4_bit_30; // @[Library.scala 311:48]
-  wire  aconv = _aconv_T_7 & v; // @[Library.scala 314:48]
-  wire  _vcget_T_3 = _vdup_T_2 & io_in_inst[28]; // @[Library.scala 314:48]
-  wire  vcget_bit_5 = ~vdup_bit_5; // @[Library.scala 310:19]
-  wire  vcget_bit_7 = ~vdup_bit_7; // @[Library.scala 310:19]
-  wire  vcget_bit_8 = ~vdup_bit_8; // @[Library.scala 310:19]
-  wire  vcget_bit_9 = ~vdup_bit_9; // @[Library.scala 310:19]
-  wire  vcget_bit_10 = ~vdup_bit_10; // @[Library.scala 310:19]
-  wire  vcget_bit_11 = ~vdup_bit_11; // @[Library.scala 310:19]
+  wire  vzip = ~v & func1 == 3'h6 & func2 == 6'h1c & _vdup_T_17; // @[VDecodeInstruction.scala 46:65]
+  wire  vslideh2 = vslidehn2 | vslidehp2; // @[VDecodeInstruction.scala 339:28]
+  wire  vevn3 = vevn | vevnodd | vodd; // @[VDecodeInstruction.scala 340:31]
+  wire  vfmt6 = vslidevn | vslidehn | vslidehn2 | vslidevp | vslidehp | vslidehp2 | vsel | vevn | vodd | vevnodd | vzip; // @[VDecodeInstruction.scala 342:112]
+  wire  _aconv_T_1 = io_in_inst[25] & vdup_bit_18; // @[Library.scala 316:48]
+  wire  aconv_bit_19 = ~vdup_bit_19; // @[Library.scala 312:19]
+  wire  _aconv_T_2 = _aconv_T_1 & aconv_bit_19; // @[Library.scala 313:48]
+  wire  aconv_bit_27 = ~vdup_bit_27; // @[Library.scala 312:19]
+  wire  aconv_bit_28 = ~vdup_bit_28; // @[Library.scala 312:19]
+  wire  _aconv_T_5 = _aconv_T_1 & aconv_bit_19 & _acset_T_10 & aconv_bit_27 & aconv_bit_28; // @[Library.scala 313:48]
+  wire  _aconv_T_6 = _aconv_T_5 & x3; // @[Library.scala 316:48]
+  wire  aconv_bit_30 = ~x; // @[Library.scala 312:19]
+  wire  _aconv_T_7 = _aconv_T_6 & aconv_bit_30; // @[Library.scala 313:48]
+  wire  aconv = _aconv_T_7 & v; // @[Library.scala 316:48]
+  wire  _vcget_T_3 = _vdup_T_2 & io_in_inst[28]; // @[Library.scala 316:48]
+  wire  vcget_bit_5 = ~vdup_bit_5; // @[Library.scala 312:19]
+  wire  vcget_bit_7 = ~vdup_bit_7; // @[Library.scala 312:19]
+  wire  vcget_bit_8 = ~vdup_bit_8; // @[Library.scala 312:19]
+  wire  vcget_bit_9 = ~vdup_bit_9; // @[Library.scala 312:19]
+  wire  vcget_bit_10 = ~vdup_bit_10; // @[Library.scala 312:19]
+  wire  vcget_bit_11 = ~vdup_bit_11; // @[Library.scala 312:19]
   wire  _vcget_T_17 = _vcget_T_3 & vdup_bit_4 & vcget_bit_5 & vdup_bit_6 & vcget_bit_7 & vcget_bit_8 & vcget_bit_9 &
-    vcget_bit_10 & vcget_bit_11 & vdup_bit_12 & vdup_bit_13 & vdup_bit_14 & vdup_bit_15 & vdup_bit_16 & vdup_bit_17; // @[Library.scala 311:48]
-  wire  vcget = _vcget_T_17 & vdup_bit_27 & vdup_bit_28 & x3 & x & v; // @[Library.scala 314:48]
-  wire  _vdwconv_T_1 = vdup_bit_6 & vdup_bit_18; // @[Library.scala 314:48]
-  wire  _vdwconv_T_2 = _vdwconv_T_1 & vfmadd4_bit_19; // @[Library.scala 311:48]
-  wire  _vdwconv_T_3 = _vdwconv_T_2 & vdup_bit_27; // @[Library.scala 314:48]
-  wire  _vdwconv_T_4 = _vdwconv_T_3 & vfmadd4_bit_28; // @[Library.scala 311:48]
-  wire  _vdwconv_T_5 = _vdwconv_T_4 & x3; // @[Library.scala 314:48]
-  wire  _vdwconv_T_6 = _vdwconv_T_5 & vfmadd4_bit_30; // @[Library.scala 311:48]
-  wire  vdwconv = _vdwconv_T_6 & v; // @[Library.scala 314:48]
-  wire  _adwconv_T_3 = _aconv_T_2 & vdup_bit_27; // @[Library.scala 314:48]
-  wire  _adwconv_T_4 = _adwconv_T_3 & vfmadd4_bit_28; // @[Library.scala 311:48]
-  wire  _adwconv_T_5 = _adwconv_T_4 & x3; // @[Library.scala 314:48]
-  wire  _adwconv_T_6 = _adwconv_T_5 & vfmadd4_bit_30; // @[Library.scala 311:48]
-  wire  adwconv = _adwconv_T_6 & v; // @[Library.scala 314:48]
-  wire  vadwconv = vdwconv | adwconv; // @[VDecodeInstruction.scala 389:26]
-  wire [5:0] vopbits_lo_lo_lo_lo = {vevnodd,vzip,vfmadd4,aconv,vdwconv,adwconv}; // @[Cat.scala 31:58]
-  wire [12:0] vopbits_lo_lo_lo = {vslidehn2,vslidevp,vslidehp,vslidehp2,vsel,vevn,vodd,vopbits_lo_lo_lo_lo}; // @[Cat.scala 31:58]
-  wire [5:0] vopbits_lo_lo_hi_lo = {vfgt,vfge,vfeq,vfne,vslidevn,vslidehn}; // @[Cat.scala 31:58]
-  wire [25:0] vopbits_lo_lo = {vfmax,vfcvt_s_w,vfcvt_s_wu,vfcvt_w_s,vfcvt_wu_s,vflt,vfle,vopbits_lo_lo_hi_lo,
-    vopbits_lo_lo_lo}; // @[Cat.scala 31:58]
-  wire [5:0] vopbits_lo_hi_lo_lo = {vfrdiv,vfsqrt,vfsgnj,vfsgnjn,vfsgnjx,vfmin}; // @[Cat.scala 31:58]
-  wire [12:0] vopbits_lo_hi_lo = {vfmul,vfabsd,vfmadd,vfmsub,vfnmsub,vfnmadd,vfdiv,vopbits_lo_hi_lo_lo}; // @[Cat.scala 31:58]
-  wire [5:0] vopbits_lo_hi_hi_lo = {vpadd,vpsub,vhadd,vhsub,vfadd,vfsub}; // @[Cat.scala 31:58]
-  wire [51:0] vopbits_lo = {vdiv,vrem,vadds,vsubs,vaddw,vsubw,vacc,vopbits_lo_hi_hi_lo,vopbits_lo_hi_lo,vopbits_lo_lo}; // @[Cat.scala 31:58]
-  wire [5:0] vopbits_hi_lo_lo_lo = {vmulhu2,vdmulh,vdmulh2,vmulw,vmacc,vmadd}; // @[Cat.scala 31:58]
-  wire [12:0] vopbits_hi_lo_lo = {vmul,vmul2,vmuls,vmuls2,vmulh,vmulh2,vmulhu,vopbits_hi_lo_lo_lo}; // @[Cat.scala 31:58]
-  wire [5:0] vopbits_hi_lo_hi_lo = {vsra,vsrl,vsha,vshl,vsrans,vsraqs}; // @[Cat.scala 31:58]
-  wire [25:0] vopbits_hi_lo = {vmv,vmv2,vmvp,acset,actr,adwinit,vsll,vopbits_hi_lo_hi_lo,vopbits_hi_lo_lo}; // @[Cat.scala 31:58]
-  wire [5:0] vopbits_hi_hi_lo_lo = {vnot,vrev,vror,vclb,vclz,vcpop}; // @[Cat.scala 31:58]
-  wire [12:0] vopbits_hi_hi_lo = {vabsd,vmax,vmin,vadd3,vand,vor,vxor,vopbits_hi_hi_lo_lo}; // @[Cat.scala 31:58]
-  wire [6:0] vopbits_hi_hi_hi_lo = {vrsub,veq,vne,vlt,vle,vgt,vge}; // @[Cat.scala 31:58]
-  wire [52:0] vopbits_hi = {vdup,vld,vst,vstq,vcget,vadd,vsub,vopbits_hi_hi_hi_lo,vopbits_hi_hi_lo,vopbits_hi_lo}; // @[Cat.scala 31:58]
-  wire [104:0] vopbits = {vopbits_hi,vopbits_lo}; // @[Cat.scala 31:58]
-  wire  undef_value__52 = vopbits[104]; // @[Library.scala 182:26]
+    vcget_bit_10 & vcget_bit_11 & vdup_bit_12 & vdup_bit_13 & vdup_bit_14 & vdup_bit_15 & vdup_bit_16 & vdup_bit_17; // @[Library.scala 313:48]
+  wire  vcget = _vcget_T_17 & vdup_bit_27 & vdup_bit_28 & x3 & x & v; // @[Library.scala 316:48]
+  wire  _vdwconv_T_1 = vdup_bit_6 & vdup_bit_18; // @[Library.scala 316:48]
+  wire  _vdwconv_T_2 = _vdwconv_T_1 & aconv_bit_19; // @[Library.scala 313:48]
+  wire  _vdwconv_T_3 = _vdwconv_T_2 & vdup_bit_27; // @[Library.scala 316:48]
+  wire  _vdwconv_T_4 = _vdwconv_T_3 & aconv_bit_28; // @[Library.scala 313:48]
+  wire  _vdwconv_T_5 = _vdwconv_T_4 & x3; // @[Library.scala 316:48]
+  wire  _vdwconv_T_6 = _vdwconv_T_5 & aconv_bit_30; // @[Library.scala 313:48]
+  wire  vdwconv = _vdwconv_T_6 & v; // @[Library.scala 316:48]
+  wire  _adwconv_T_3 = _aconv_T_2 & vdup_bit_27; // @[Library.scala 316:48]
+  wire  _adwconv_T_4 = _adwconv_T_3 & aconv_bit_28; // @[Library.scala 313:48]
+  wire  _adwconv_T_5 = _adwconv_T_4 & x3; // @[Library.scala 316:48]
+  wire  _adwconv_T_6 = _adwconv_T_5 & aconv_bit_30; // @[Library.scala 313:48]
+  wire  adwconv = _adwconv_T_6 & v; // @[Library.scala 316:48]
+  wire  vadwconv = vdwconv | adwconv; // @[VDecodeInstruction.scala 350:26]
+  wire [9:0] vopbits_lo_lo_hi = {vacc,vpadd,vpsub,vhadd,vhsub,vslidevn,vslidehn,vslidehn2,vslidevp,vslidehp}; // @[Cat.scala 31:58]
+  wire [18:0] vopbits_lo_lo = {vopbits_lo_lo_hi,vslidehp2,vsel,vevn,vodd,vevnodd,vzip,aconv,vdwconv,adwconv}; // @[Cat.scala 31:58]
+  wire [9:0] vopbits_lo_hi_hi = {vsrans,vsraqs,vmul,vmul2,vmuls,vmuls2,vmulh,vmulh2,vmulhu,vmulhu2}; // @[Cat.scala 31:58]
+  wire [18:0] vopbits_lo_hi = {vopbits_lo_hi_hi,vdmulh,vdmulh2,vmulw,vmacc,vmadd,vadds,vsubs,vaddw,vsubw}; // @[Cat.scala 31:58]
+  wire [9:0] vopbits_hi_lo_hi = {vor,vxor,vnot,vrev,vror,vclb,vclz,vcpop,vmv,vmv2}; // @[Cat.scala 31:58]
+  wire [18:0] vopbits_hi_lo = {vopbits_hi_lo_hi,vmvp,acset,actr,adwinit,vsll,vsra,vsrl,vsha,vshl}; // @[Cat.scala 31:58]
+  wire [9:0] vopbits_hi_hi_hi = {vdup,vld,vst,vstq,vcget,vadd,vsub,vrsub,veq,vne}; // @[Cat.scala 31:58]
+  wire [18:0] vopbits_hi_hi = {vopbits_hi_hi_hi,vlt,vle,vgt,vge,vabsd,vmax,vmin,vadd3,vand}; // @[Cat.scala 31:58]
+  wire [75:0] vopbits = {vopbits_hi_hi,vopbits_hi_lo,vopbits_lo_hi,vopbits_lo_lo}; // @[Cat.scala 31:58]
   wire  undef_value__0 = vopbits[0] | vopbits[1]; // @[Library.scala 194:39]
   wire  undef_value__1 = vopbits[2] | vopbits[3]; // @[Library.scala 194:39]
   wire  undef_value__2 = vopbits[4] | vopbits[5]; // @[Library.scala 194:39]
@@ -36608,20 +27198,6 @@
   wire  undef_value__35 = vopbits[70] | vopbits[71]; // @[Library.scala 194:39]
   wire  undef_value__36 = vopbits[72] | vopbits[73]; // @[Library.scala 194:39]
   wire  undef_value__37 = vopbits[74] | vopbits[75]; // @[Library.scala 194:39]
-  wire  undef_value__38 = vopbits[76] | vopbits[77]; // @[Library.scala 194:39]
-  wire  undef_value__39 = vopbits[78] | vopbits[79]; // @[Library.scala 194:39]
-  wire  undef_value__40 = vopbits[80] | vopbits[81]; // @[Library.scala 194:39]
-  wire  undef_value__41 = vopbits[82] | vopbits[83]; // @[Library.scala 194:39]
-  wire  undef_value__42 = vopbits[84] | vopbits[85]; // @[Library.scala 194:39]
-  wire  undef_value__43 = vopbits[86] | vopbits[87]; // @[Library.scala 194:39]
-  wire  undef_value__44 = vopbits[88] | vopbits[89]; // @[Library.scala 194:39]
-  wire  undef_value__45 = vopbits[90] | vopbits[91]; // @[Library.scala 194:39]
-  wire  undef_value__46 = vopbits[92] | vopbits[93]; // @[Library.scala 194:39]
-  wire  undef_value__47 = vopbits[94] | vopbits[95]; // @[Library.scala 194:39]
-  wire  undef_value__48 = vopbits[96] | vopbits[97]; // @[Library.scala 194:39]
-  wire  undef_value__49 = vopbits[98] | vopbits[99]; // @[Library.scala 194:39]
-  wire  undef_value__50 = vopbits[100] | vopbits[101]; // @[Library.scala 194:39]
-  wire  undef_value__51 = vopbits[102] | vopbits[103]; // @[Library.scala 194:39]
   wire  undef_value_1_0 = undef_value__0 | undef_value__1; // @[Library.scala 194:39]
   wire  undef_value_1_1 = undef_value__2 | undef_value__3; // @[Library.scala 194:39]
   wire  undef_value_1_2 = undef_value__4 | undef_value__5; // @[Library.scala 194:39]
@@ -36641,13 +27217,6 @@
   wire  undef_value_1_16 = undef_value__32 | undef_value__33; // @[Library.scala 194:39]
   wire  undef_value_1_17 = undef_value__34 | undef_value__35; // @[Library.scala 194:39]
   wire  undef_value_1_18 = undef_value__36 | undef_value__37; // @[Library.scala 194:39]
-  wire  undef_value_1_19 = undef_value__38 | undef_value__39; // @[Library.scala 194:39]
-  wire  undef_value_1_20 = undef_value__40 | undef_value__41; // @[Library.scala 194:39]
-  wire  undef_value_1_21 = undef_value__42 | undef_value__43; // @[Library.scala 194:39]
-  wire  undef_value_1_22 = undef_value__44 | undef_value__45; // @[Library.scala 194:39]
-  wire  undef_value_1_23 = undef_value__46 | undef_value__47; // @[Library.scala 194:39]
-  wire  undef_value_1_24 = undef_value__48 | undef_value__49; // @[Library.scala 194:39]
-  wire  undef_value_1_25 = undef_value__50 | undef_value__51; // @[Library.scala 194:39]
   wire  undef_value_2_0 = undef_value_1_0 | undef_value_1_1; // @[Library.scala 194:39]
   wire  undef_value_2_1 = undef_value_1_2 | undef_value_1_3; // @[Library.scala 194:39]
   wire  undef_value_2_2 = undef_value_1_4 | undef_value_1_5; // @[Library.scala 194:39]
@@ -36657,638 +27226,524 @@
   wire  undef_value_2_6 = undef_value_1_12 | undef_value_1_13; // @[Library.scala 194:39]
   wire  undef_value_2_7 = undef_value_1_14 | undef_value_1_15; // @[Library.scala 194:39]
   wire  undef_value_2_8 = undef_value_1_16 | undef_value_1_17; // @[Library.scala 194:39]
-  wire  undef_value_2_9 = undef_value_1_18 | undef_value_1_19; // @[Library.scala 194:39]
-  wire  undef_value_2_10 = undef_value_1_20 | undef_value_1_21; // @[Library.scala 194:39]
-  wire  undef_value_2_11 = undef_value_1_22 | undef_value_1_23; // @[Library.scala 194:39]
-  wire  undef_value_2_12 = undef_value_1_24 | undef_value_1_25; // @[Library.scala 194:39]
   wire  undef_value_3_0 = undef_value_2_0 | undef_value_2_1; // @[Library.scala 194:39]
   wire  undef_value_3_1 = undef_value_2_2 | undef_value_2_3; // @[Library.scala 194:39]
   wire  undef_value_3_2 = undef_value_2_4 | undef_value_2_5; // @[Library.scala 194:39]
   wire  undef_value_3_3 = undef_value_2_6 | undef_value_2_7; // @[Library.scala 194:39]
-  wire  undef_value_3_4 = undef_value_2_8 | undef_value_2_9; // @[Library.scala 194:39]
-  wire  undef_value_3_5 = undef_value_2_10 | undef_value_2_11; // @[Library.scala 194:39]
-  wire  undef_value_3_6 = undef_value_2_12 | undef_value__52; // @[Library.scala 194:39]
+  wire  undef_value_3_4 = undef_value_2_8 | undef_value_1_18; // @[Library.scala 194:39]
   wire  undef_value_4_0 = undef_value_3_0 | undef_value_3_1; // @[Library.scala 194:39]
   wire  undef_value_4_1 = undef_value_3_2 | undef_value_3_3; // @[Library.scala 194:39]
-  wire  undef_value_4_2 = undef_value_3_4 | undef_value_3_5; // @[Library.scala 194:39]
   wire  undef_value_5_0 = undef_value_4_0 | undef_value_4_1; // @[Library.scala 194:39]
-  wire  undef_value_5_1 = undef_value_4_2 | undef_value_3_6; // @[Library.scala 194:39]
-  wire  undef_value_6_0 = undef_value_5_0 | undef_value_5_1; // @[Library.scala 194:39]
-  wire  undef = ~undef_value_6_0; // @[VDecodeInstruction.scala 416:15]
-  wire [105:0] _T_5 = {vopbits_hi,vopbits_lo,undef}; // @[Cat.scala 31:58]
-  wire [1:0] _T_112 = _T_5[1] + _T_5[2]; // @[Bitwise.scala 48:55]
-  wire [1:0] _GEN_48 = {{1'd0}, _T_5[0]}; // @[Bitwise.scala 48:55]
-  wire [2:0] _T_114 = _GEN_48 + _T_112; // @[Bitwise.scala 48:55]
-  wire [1:0] _T_116 = _T_5[4] + _T_5[5]; // @[Bitwise.scala 48:55]
-  wire [1:0] _GEN_49 = {{1'd0}, _T_5[3]}; // @[Bitwise.scala 48:55]
-  wire [2:0] _T_118 = _GEN_49 + _T_116; // @[Bitwise.scala 48:55]
-  wire [2:0] _T_120 = _T_114[1:0] + _T_118[1:0]; // @[Bitwise.scala 48:55]
-  wire [1:0] _T_122 = _T_5[7] + _T_5[8]; // @[Bitwise.scala 48:55]
-  wire [1:0] _GEN_50 = {{1'd0}, _T_5[6]}; // @[Bitwise.scala 48:55]
-  wire [2:0] _T_124 = _GEN_50 + _T_122; // @[Bitwise.scala 48:55]
-  wire [1:0] _T_126 = _T_5[9] + _T_5[10]; // @[Bitwise.scala 48:55]
-  wire [1:0] _T_128 = _T_5[11] + _T_5[12]; // @[Bitwise.scala 48:55]
-  wire [2:0] _T_130 = _T_126 + _T_128; // @[Bitwise.scala 48:55]
-  wire [2:0] _GEN_51 = {{1'd0}, _T_124[1:0]}; // @[Bitwise.scala 48:55]
-  wire [3:0] _T_132 = _GEN_51 + _T_130; // @[Bitwise.scala 48:55]
-  wire [3:0] _T_134 = _T_120 + _T_132[2:0]; // @[Bitwise.scala 48:55]
-  wire [1:0] _T_136 = _T_5[14] + _T_5[15]; // @[Bitwise.scala 48:55]
-  wire [1:0] _GEN_52 = {{1'd0}, _T_5[13]}; // @[Bitwise.scala 48:55]
-  wire [2:0] _T_138 = _GEN_52 + _T_136; // @[Bitwise.scala 48:55]
-  wire [1:0] _T_140 = _T_5[17] + _T_5[18]; // @[Bitwise.scala 48:55]
-  wire [1:0] _GEN_53 = {{1'd0}, _T_5[16]}; // @[Bitwise.scala 48:55]
-  wire [2:0] _T_142 = _GEN_53 + _T_140; // @[Bitwise.scala 48:55]
-  wire [2:0] _T_144 = _T_138[1:0] + _T_142[1:0]; // @[Bitwise.scala 48:55]
-  wire [1:0] _T_146 = _T_5[20] + _T_5[21]; // @[Bitwise.scala 48:55]
-  wire [1:0] _GEN_54 = {{1'd0}, _T_5[19]}; // @[Bitwise.scala 48:55]
-  wire [2:0] _T_148 = _GEN_54 + _T_146; // @[Bitwise.scala 48:55]
-  wire [1:0] _T_150 = _T_5[22] + _T_5[23]; // @[Bitwise.scala 48:55]
-  wire [1:0] _T_152 = _T_5[24] + _T_5[25]; // @[Bitwise.scala 48:55]
-  wire [2:0] _T_154 = _T_150 + _T_152; // @[Bitwise.scala 48:55]
-  wire [2:0] _GEN_55 = {{1'd0}, _T_148[1:0]}; // @[Bitwise.scala 48:55]
-  wire [3:0] _T_156 = _GEN_55 + _T_154; // @[Bitwise.scala 48:55]
-  wire [3:0] _T_158 = _T_144 + _T_156[2:0]; // @[Bitwise.scala 48:55]
-  wire [4:0] _T_160 = _T_134 + _T_158; // @[Bitwise.scala 48:55]
-  wire [1:0] _T_162 = _T_5[27] + _T_5[28]; // @[Bitwise.scala 48:55]
-  wire [1:0] _GEN_56 = {{1'd0}, _T_5[26]}; // @[Bitwise.scala 48:55]
-  wire [2:0] _T_164 = _GEN_56 + _T_162; // @[Bitwise.scala 48:55]
-  wire [1:0] _T_166 = _T_5[30] + _T_5[31]; // @[Bitwise.scala 48:55]
-  wire [1:0] _GEN_57 = {{1'd0}, _T_5[29]}; // @[Bitwise.scala 48:55]
-  wire [2:0] _T_168 = _GEN_57 + _T_166; // @[Bitwise.scala 48:55]
-  wire [2:0] _T_170 = _T_164[1:0] + _T_168[1:0]; // @[Bitwise.scala 48:55]
-  wire [1:0] _T_172 = _T_5[33] + _T_5[34]; // @[Bitwise.scala 48:55]
-  wire [1:0] _GEN_58 = {{1'd0}, _T_5[32]}; // @[Bitwise.scala 48:55]
-  wire [2:0] _T_174 = _GEN_58 + _T_172; // @[Bitwise.scala 48:55]
-  wire [1:0] _T_176 = _T_5[35] + _T_5[36]; // @[Bitwise.scala 48:55]
-  wire [1:0] _T_178 = _T_5[37] + _T_5[38]; // @[Bitwise.scala 48:55]
-  wire [2:0] _T_180 = _T_176 + _T_178; // @[Bitwise.scala 48:55]
-  wire [2:0] _GEN_59 = {{1'd0}, _T_174[1:0]}; // @[Bitwise.scala 48:55]
-  wire [3:0] _T_182 = _GEN_59 + _T_180; // @[Bitwise.scala 48:55]
-  wire [3:0] _T_184 = _T_170 + _T_182[2:0]; // @[Bitwise.scala 48:55]
-  wire [1:0] _T_186 = _T_5[40] + _T_5[41]; // @[Bitwise.scala 48:55]
-  wire [1:0] _GEN_60 = {{1'd0}, _T_5[39]}; // @[Bitwise.scala 48:55]
-  wire [2:0] _T_188 = _GEN_60 + _T_186; // @[Bitwise.scala 48:55]
-  wire [1:0] _T_190 = _T_5[42] + _T_5[43]; // @[Bitwise.scala 48:55]
-  wire [1:0] _T_192 = _T_5[44] + _T_5[45]; // @[Bitwise.scala 48:55]
-  wire [2:0] _T_194 = _T_190 + _T_192; // @[Bitwise.scala 48:55]
-  wire [2:0] _GEN_61 = {{1'd0}, _T_188[1:0]}; // @[Bitwise.scala 48:55]
-  wire [3:0] _T_196 = _GEN_61 + _T_194; // @[Bitwise.scala 48:55]
-  wire [1:0] _T_198 = _T_5[47] + _T_5[48]; // @[Bitwise.scala 48:55]
-  wire [1:0] _GEN_62 = {{1'd0}, _T_5[46]}; // @[Bitwise.scala 48:55]
-  wire [2:0] _T_200 = _GEN_62 + _T_198; // @[Bitwise.scala 48:55]
-  wire [1:0] _T_202 = _T_5[49] + _T_5[50]; // @[Bitwise.scala 48:55]
-  wire [1:0] _T_204 = _T_5[51] + _T_5[52]; // @[Bitwise.scala 48:55]
-  wire [2:0] _T_206 = _T_202 + _T_204; // @[Bitwise.scala 48:55]
-  wire [2:0] _GEN_63 = {{1'd0}, _T_200[1:0]}; // @[Bitwise.scala 48:55]
-  wire [3:0] _T_208 = _GEN_63 + _T_206; // @[Bitwise.scala 48:55]
-  wire [3:0] _T_210 = _T_196[2:0] + _T_208[2:0]; // @[Bitwise.scala 48:55]
-  wire [4:0] _T_212 = _T_184 + _T_210; // @[Bitwise.scala 48:55]
-  wire [5:0] _T_214 = _T_160 + _T_212; // @[Bitwise.scala 48:55]
-  wire [1:0] _T_216 = _T_5[54] + _T_5[55]; // @[Bitwise.scala 48:55]
-  wire [1:0] _GEN_64 = {{1'd0}, _T_5[53]}; // @[Bitwise.scala 48:55]
-  wire [2:0] _T_218 = _GEN_64 + _T_216; // @[Bitwise.scala 48:55]
-  wire [1:0] _T_220 = _T_5[57] + _T_5[58]; // @[Bitwise.scala 48:55]
-  wire [1:0] _GEN_65 = {{1'd0}, _T_5[56]}; // @[Bitwise.scala 48:55]
-  wire [2:0] _T_222 = _GEN_65 + _T_220; // @[Bitwise.scala 48:55]
-  wire [2:0] _T_224 = _T_218[1:0] + _T_222[1:0]; // @[Bitwise.scala 48:55]
-  wire [1:0] _T_226 = _T_5[60] + _T_5[61]; // @[Bitwise.scala 48:55]
-  wire [1:0] _GEN_66 = {{1'd0}, _T_5[59]}; // @[Bitwise.scala 48:55]
-  wire [2:0] _T_228 = _GEN_66 + _T_226; // @[Bitwise.scala 48:55]
-  wire [1:0] _T_230 = _T_5[62] + _T_5[63]; // @[Bitwise.scala 48:55]
-  wire [1:0] _T_232 = _T_5[64] + _T_5[65]; // @[Bitwise.scala 48:55]
-  wire [2:0] _T_234 = _T_230 + _T_232; // @[Bitwise.scala 48:55]
-  wire [2:0] _GEN_67 = {{1'd0}, _T_228[1:0]}; // @[Bitwise.scala 48:55]
-  wire [3:0] _T_236 = _GEN_67 + _T_234; // @[Bitwise.scala 48:55]
-  wire [3:0] _T_238 = _T_224 + _T_236[2:0]; // @[Bitwise.scala 48:55]
-  wire [1:0] _T_240 = _T_5[67] + _T_5[68]; // @[Bitwise.scala 48:55]
-  wire [1:0] _GEN_68 = {{1'd0}, _T_5[66]}; // @[Bitwise.scala 48:55]
-  wire [2:0] _T_242 = _GEN_68 + _T_240; // @[Bitwise.scala 48:55]
-  wire [1:0] _T_244 = _T_5[70] + _T_5[71]; // @[Bitwise.scala 48:55]
-  wire [1:0] _GEN_69 = {{1'd0}, _T_5[69]}; // @[Bitwise.scala 48:55]
-  wire [2:0] _T_246 = _GEN_69 + _T_244; // @[Bitwise.scala 48:55]
-  wire [2:0] _T_248 = _T_242[1:0] + _T_246[1:0]; // @[Bitwise.scala 48:55]
-  wire [1:0] _T_250 = _T_5[73] + _T_5[74]; // @[Bitwise.scala 48:55]
-  wire [1:0] _GEN_70 = {{1'd0}, _T_5[72]}; // @[Bitwise.scala 48:55]
-  wire [2:0] _T_252 = _GEN_70 + _T_250; // @[Bitwise.scala 48:55]
-  wire [1:0] _T_254 = _T_5[75] + _T_5[76]; // @[Bitwise.scala 48:55]
-  wire [1:0] _T_256 = _T_5[77] + _T_5[78]; // @[Bitwise.scala 48:55]
-  wire [2:0] _T_258 = _T_254 + _T_256; // @[Bitwise.scala 48:55]
-  wire [2:0] _GEN_71 = {{1'd0}, _T_252[1:0]}; // @[Bitwise.scala 48:55]
-  wire [3:0] _T_260 = _GEN_71 + _T_258; // @[Bitwise.scala 48:55]
-  wire [3:0] _T_262 = _T_248 + _T_260[2:0]; // @[Bitwise.scala 48:55]
-  wire [4:0] _T_264 = _T_238 + _T_262; // @[Bitwise.scala 48:55]
-  wire [1:0] _T_266 = _T_5[80] + _T_5[81]; // @[Bitwise.scala 48:55]
-  wire [1:0] _GEN_72 = {{1'd0}, _T_5[79]}; // @[Bitwise.scala 48:55]
-  wire [2:0] _T_268 = _GEN_72 + _T_266; // @[Bitwise.scala 48:55]
-  wire [1:0] _T_270 = _T_5[83] + _T_5[84]; // @[Bitwise.scala 48:55]
-  wire [1:0] _GEN_73 = {{1'd0}, _T_5[82]}; // @[Bitwise.scala 48:55]
-  wire [2:0] _T_272 = _GEN_73 + _T_270; // @[Bitwise.scala 48:55]
-  wire [2:0] _T_274 = _T_268[1:0] + _T_272[1:0]; // @[Bitwise.scala 48:55]
-  wire [1:0] _T_276 = _T_5[86] + _T_5[87]; // @[Bitwise.scala 48:55]
-  wire [1:0] _GEN_74 = {{1'd0}, _T_5[85]}; // @[Bitwise.scala 48:55]
-  wire [2:0] _T_278 = _GEN_74 + _T_276; // @[Bitwise.scala 48:55]
-  wire [1:0] _T_280 = _T_5[88] + _T_5[89]; // @[Bitwise.scala 48:55]
-  wire [1:0] _T_282 = _T_5[90] + _T_5[91]; // @[Bitwise.scala 48:55]
-  wire [2:0] _T_284 = _T_280 + _T_282; // @[Bitwise.scala 48:55]
-  wire [2:0] _GEN_75 = {{1'd0}, _T_278[1:0]}; // @[Bitwise.scala 48:55]
-  wire [3:0] _T_286 = _GEN_75 + _T_284; // @[Bitwise.scala 48:55]
-  wire [3:0] _T_288 = _T_274 + _T_286[2:0]; // @[Bitwise.scala 48:55]
-  wire [1:0] _T_290 = _T_5[93] + _T_5[94]; // @[Bitwise.scala 48:55]
-  wire [1:0] _GEN_76 = {{1'd0}, _T_5[92]}; // @[Bitwise.scala 48:55]
-  wire [2:0] _T_292 = _GEN_76 + _T_290; // @[Bitwise.scala 48:55]
-  wire [1:0] _T_294 = _T_5[95] + _T_5[96]; // @[Bitwise.scala 48:55]
-  wire [1:0] _T_296 = _T_5[97] + _T_5[98]; // @[Bitwise.scala 48:55]
-  wire [2:0] _T_298 = _T_294 + _T_296; // @[Bitwise.scala 48:55]
-  wire [2:0] _GEN_77 = {{1'd0}, _T_292[1:0]}; // @[Bitwise.scala 48:55]
-  wire [3:0] _T_300 = _GEN_77 + _T_298; // @[Bitwise.scala 48:55]
-  wire [1:0] _T_302 = _T_5[100] + _T_5[101]; // @[Bitwise.scala 48:55]
-  wire [1:0] _GEN_78 = {{1'd0}, _T_5[99]}; // @[Bitwise.scala 48:55]
-  wire [2:0] _T_304 = _GEN_78 + _T_302; // @[Bitwise.scala 48:55]
-  wire [1:0] _T_306 = _T_5[102] + _T_5[103]; // @[Bitwise.scala 48:55]
-  wire [1:0] _T_308 = _T_5[104] + _T_5[105]; // @[Bitwise.scala 48:55]
-  wire [2:0] _T_310 = _T_306 + _T_308; // @[Bitwise.scala 48:55]
-  wire [2:0] _GEN_79 = {{1'd0}, _T_304[1:0]}; // @[Bitwise.scala 48:55]
-  wire [3:0] _T_312 = _GEN_79 + _T_310; // @[Bitwise.scala 48:55]
-  wire [3:0] _T_314 = _T_300[2:0] + _T_312[2:0]; // @[Bitwise.scala 48:55]
-  wire [4:0] _T_316 = _T_288 + _T_314; // @[Bitwise.scala 48:55]
-  wire [5:0] _T_318 = _T_264 + _T_316; // @[Bitwise.scala 48:55]
-  wire [6:0] _T_320 = _T_214 + _T_318; // @[Bitwise.scala 48:55]
+  wire  undef_value_6_0 = undef_value_5_0 | undef_value_3_4; // @[Library.scala 194:39]
+  wire  undef = ~undef_value_6_0; // @[VDecodeInstruction.scala 375:15]
+  wire [76:0] _T_5 = {vopbits_hi_hi,vopbits_hi_lo,vopbits_lo_hi,vopbits_lo_lo,undef}; // @[Cat.scala 31:58]
+  wire [1:0] _T_83 = _T_5[0] + _T_5[1]; // @[Bitwise.scala 48:55]
+  wire [1:0] _T_85 = _T_5[2] + _T_5[3]; // @[Bitwise.scala 48:55]
+  wire [2:0] _T_87 = _T_83 + _T_85; // @[Bitwise.scala 48:55]
+  wire [1:0] _T_89 = _T_5[4] + _T_5[5]; // @[Bitwise.scala 48:55]
+  wire [1:0] _T_91 = _T_5[7] + _T_5[8]; // @[Bitwise.scala 48:55]
+  wire [1:0] _GEN_48 = {{1'd0}, _T_5[6]}; // @[Bitwise.scala 48:55]
+  wire [2:0] _T_93 = _GEN_48 + _T_91; // @[Bitwise.scala 48:55]
+  wire [2:0] _T_95 = _T_89 + _T_93[1:0]; // @[Bitwise.scala 48:55]
+  wire [3:0] _T_97 = _T_87 + _T_95; // @[Bitwise.scala 48:55]
+  wire [1:0] _T_99 = _T_5[9] + _T_5[10]; // @[Bitwise.scala 48:55]
+  wire [1:0] _T_101 = _T_5[12] + _T_5[13]; // @[Bitwise.scala 48:55]
+  wire [1:0] _GEN_49 = {{1'd0}, _T_5[11]}; // @[Bitwise.scala 48:55]
+  wire [2:0] _T_103 = _GEN_49 + _T_101; // @[Bitwise.scala 48:55]
+  wire [2:0] _T_105 = _T_99 + _T_103[1:0]; // @[Bitwise.scala 48:55]
+  wire [1:0] _T_107 = _T_5[14] + _T_5[15]; // @[Bitwise.scala 48:55]
+  wire [1:0] _T_109 = _T_5[17] + _T_5[18]; // @[Bitwise.scala 48:55]
+  wire [1:0] _GEN_50 = {{1'd0}, _T_5[16]}; // @[Bitwise.scala 48:55]
+  wire [2:0] _T_111 = _GEN_50 + _T_109; // @[Bitwise.scala 48:55]
+  wire [2:0] _T_113 = _T_107 + _T_111[1:0]; // @[Bitwise.scala 48:55]
+  wire [3:0] _T_115 = _T_105 + _T_113; // @[Bitwise.scala 48:55]
+  wire [4:0] _T_117 = _T_97 + _T_115; // @[Bitwise.scala 48:55]
+  wire [1:0] _T_119 = _T_5[19] + _T_5[20]; // @[Bitwise.scala 48:55]
+  wire [1:0] _T_121 = _T_5[21] + _T_5[22]; // @[Bitwise.scala 48:55]
+  wire [2:0] _T_123 = _T_119 + _T_121; // @[Bitwise.scala 48:55]
+  wire [1:0] _T_125 = _T_5[23] + _T_5[24]; // @[Bitwise.scala 48:55]
+  wire [1:0] _T_127 = _T_5[26] + _T_5[27]; // @[Bitwise.scala 48:55]
+  wire [1:0] _GEN_51 = {{1'd0}, _T_5[25]}; // @[Bitwise.scala 48:55]
+  wire [2:0] _T_129 = _GEN_51 + _T_127; // @[Bitwise.scala 48:55]
+  wire [2:0] _T_131 = _T_125 + _T_129[1:0]; // @[Bitwise.scala 48:55]
+  wire [3:0] _T_133 = _T_123 + _T_131; // @[Bitwise.scala 48:55]
+  wire [1:0] _T_135 = _T_5[28] + _T_5[29]; // @[Bitwise.scala 48:55]
+  wire [1:0] _T_137 = _T_5[31] + _T_5[32]; // @[Bitwise.scala 48:55]
+  wire [1:0] _GEN_52 = {{1'd0}, _T_5[30]}; // @[Bitwise.scala 48:55]
+  wire [2:0] _T_139 = _GEN_52 + _T_137; // @[Bitwise.scala 48:55]
+  wire [2:0] _T_141 = _T_135 + _T_139[1:0]; // @[Bitwise.scala 48:55]
+  wire [1:0] _T_143 = _T_5[33] + _T_5[34]; // @[Bitwise.scala 48:55]
+  wire [1:0] _T_145 = _T_5[36] + _T_5[37]; // @[Bitwise.scala 48:55]
+  wire [1:0] _GEN_53 = {{1'd0}, _T_5[35]}; // @[Bitwise.scala 48:55]
+  wire [2:0] _T_147 = _GEN_53 + _T_145; // @[Bitwise.scala 48:55]
+  wire [2:0] _T_149 = _T_143 + _T_147[1:0]; // @[Bitwise.scala 48:55]
+  wire [3:0] _T_151 = _T_141 + _T_149; // @[Bitwise.scala 48:55]
+  wire [4:0] _T_153 = _T_133 + _T_151; // @[Bitwise.scala 48:55]
+  wire [5:0] _T_155 = _T_117 + _T_153; // @[Bitwise.scala 48:55]
+  wire [1:0] _T_157 = _T_5[38] + _T_5[39]; // @[Bitwise.scala 48:55]
+  wire [1:0] _T_159 = _T_5[40] + _T_5[41]; // @[Bitwise.scala 48:55]
+  wire [2:0] _T_161 = _T_157 + _T_159; // @[Bitwise.scala 48:55]
+  wire [1:0] _T_163 = _T_5[42] + _T_5[43]; // @[Bitwise.scala 48:55]
+  wire [1:0] _T_165 = _T_5[45] + _T_5[46]; // @[Bitwise.scala 48:55]
+  wire [1:0] _GEN_54 = {{1'd0}, _T_5[44]}; // @[Bitwise.scala 48:55]
+  wire [2:0] _T_167 = _GEN_54 + _T_165; // @[Bitwise.scala 48:55]
+  wire [2:0] _T_169 = _T_163 + _T_167[1:0]; // @[Bitwise.scala 48:55]
+  wire [3:0] _T_171 = _T_161 + _T_169; // @[Bitwise.scala 48:55]
+  wire [1:0] _T_173 = _T_5[47] + _T_5[48]; // @[Bitwise.scala 48:55]
+  wire [1:0] _T_175 = _T_5[50] + _T_5[51]; // @[Bitwise.scala 48:55]
+  wire [1:0] _GEN_55 = {{1'd0}, _T_5[49]}; // @[Bitwise.scala 48:55]
+  wire [2:0] _T_177 = _GEN_55 + _T_175; // @[Bitwise.scala 48:55]
+  wire [2:0] _T_179 = _T_173 + _T_177[1:0]; // @[Bitwise.scala 48:55]
+  wire [1:0] _T_181 = _T_5[52] + _T_5[53]; // @[Bitwise.scala 48:55]
+  wire [1:0] _T_183 = _T_5[55] + _T_5[56]; // @[Bitwise.scala 48:55]
+  wire [1:0] _GEN_56 = {{1'd0}, _T_5[54]}; // @[Bitwise.scala 48:55]
+  wire [2:0] _T_185 = _GEN_56 + _T_183; // @[Bitwise.scala 48:55]
+  wire [2:0] _T_187 = _T_181 + _T_185[1:0]; // @[Bitwise.scala 48:55]
+  wire [3:0] _T_189 = _T_179 + _T_187; // @[Bitwise.scala 48:55]
+  wire [4:0] _T_191 = _T_171 + _T_189; // @[Bitwise.scala 48:55]
+  wire [1:0] _T_193 = _T_5[57] + _T_5[58]; // @[Bitwise.scala 48:55]
+  wire [1:0] _T_195 = _T_5[60] + _T_5[61]; // @[Bitwise.scala 48:55]
+  wire [1:0] _GEN_57 = {{1'd0}, _T_5[59]}; // @[Bitwise.scala 48:55]
+  wire [2:0] _T_197 = _GEN_57 + _T_195; // @[Bitwise.scala 48:55]
+  wire [2:0] _T_199 = _T_193 + _T_197[1:0]; // @[Bitwise.scala 48:55]
+  wire [1:0] _T_201 = _T_5[62] + _T_5[63]; // @[Bitwise.scala 48:55]
+  wire [1:0] _T_203 = _T_5[65] + _T_5[66]; // @[Bitwise.scala 48:55]
+  wire [1:0] _GEN_58 = {{1'd0}, _T_5[64]}; // @[Bitwise.scala 48:55]
+  wire [2:0] _T_205 = _GEN_58 + _T_203; // @[Bitwise.scala 48:55]
+  wire [2:0] _T_207 = _T_201 + _T_205[1:0]; // @[Bitwise.scala 48:55]
+  wire [3:0] _T_209 = _T_199 + _T_207; // @[Bitwise.scala 48:55]
+  wire [1:0] _T_211 = _T_5[67] + _T_5[68]; // @[Bitwise.scala 48:55]
+  wire [1:0] _T_213 = _T_5[70] + _T_5[71]; // @[Bitwise.scala 48:55]
+  wire [1:0] _GEN_59 = {{1'd0}, _T_5[69]}; // @[Bitwise.scala 48:55]
+  wire [2:0] _T_215 = _GEN_59 + _T_213; // @[Bitwise.scala 48:55]
+  wire [2:0] _T_217 = _T_211 + _T_215[1:0]; // @[Bitwise.scala 48:55]
+  wire [1:0] _T_219 = _T_5[72] + _T_5[73]; // @[Bitwise.scala 48:55]
+  wire [1:0] _T_221 = _T_5[75] + _T_5[76]; // @[Bitwise.scala 48:55]
+  wire [1:0] _GEN_60 = {{1'd0}, _T_5[74]}; // @[Bitwise.scala 48:55]
+  wire [2:0] _T_223 = _GEN_60 + _T_221; // @[Bitwise.scala 48:55]
+  wire [2:0] _T_225 = _T_219 + _T_223[1:0]; // @[Bitwise.scala 48:55]
+  wire [3:0] _T_227 = _T_217 + _T_225; // @[Bitwise.scala 48:55]
+  wire [4:0] _T_229 = _T_209 + _T_227; // @[Bitwise.scala 48:55]
+  wire [5:0] _T_231 = _T_191 + _T_229; // @[Bitwise.scala 48:55]
+  wire [6:0] _T_233 = _T_155 + _T_231; // @[Bitwise.scala 48:55]
   wire [1:0] _op_T_1 = vld ? 2'h2 : 2'h0; // @[Library.scala 18:8]
-  wire [1:0] _GEN_80 = {{1'd0}, vdup}; // @[VDecodeInstruction.scala 422:31]
-  wire [1:0] _op_T_2 = _GEN_80 | _op_T_1; // @[VDecodeInstruction.scala 422:31]
+  wire [1:0] _GEN_61 = {{1'd0}, vdup}; // @[VDecodeInstruction.scala 381:31]
+  wire [1:0] _op_T_2 = _GEN_61 | _op_T_1; // @[VDecodeInstruction.scala 381:31]
   wire [1:0] _op_T_3 = vst ? 2'h3 : 2'h0; // @[Library.scala 18:8]
-  wire [1:0] _op_T_4 = _op_T_2 | _op_T_3; // @[VDecodeInstruction.scala 424:30]
+  wire [1:0] _op_T_4 = _op_T_2 | _op_T_3; // @[VDecodeInstruction.scala 383:30]
   wire [2:0] _op_T_5 = vstq ? 3'h4 : 3'h0; // @[Library.scala 18:8]
-  wire [2:0] _GEN_81 = {{1'd0}, _op_T_4}; // @[VDecodeInstruction.scala 425:30]
-  wire [2:0] _op_T_6 = _GEN_81 | _op_T_5; // @[VDecodeInstruction.scala 425:30]
+  wire [2:0] _GEN_62 = {{1'd0}, _op_T_4}; // @[VDecodeInstruction.scala 384:30]
+  wire [2:0] _op_T_6 = _GEN_62 | _op_T_5; // @[VDecodeInstruction.scala 384:30]
   wire [2:0] _op_T_7 = vcget ? 3'h5 : 3'h0; // @[Library.scala 18:8]
-  wire [2:0] _op_T_8 = _op_T_6 | _op_T_7; // @[VDecodeInstruction.scala 426:31]
+  wire [2:0] _op_T_8 = _op_T_6 | _op_T_7; // @[VDecodeInstruction.scala 385:31]
   wire [2:0] _op_T_9 = vadd ? 3'h6 : 3'h0; // @[Library.scala 18:8]
-  wire [2:0] _op_T_10 = _op_T_8 | _op_T_9; // @[VDecodeInstruction.scala 428:33]
+  wire [2:0] _op_T_10 = _op_T_8 | _op_T_9; // @[VDecodeInstruction.scala 387:33]
   wire [2:0] _op_T_11 = vsub ? 3'h7 : 3'h0; // @[Library.scala 18:8]
-  wire [2:0] _op_T_12 = _op_T_10 | _op_T_11; // @[VDecodeInstruction.scala 430:32]
+  wire [2:0] _op_T_12 = _op_T_10 | _op_T_11; // @[VDecodeInstruction.scala 389:32]
   wire [3:0] _op_T_13 = vrsub ? 4'h8 : 4'h0; // @[Library.scala 18:8]
-  wire [3:0] _GEN_82 = {{1'd0}, _op_T_12}; // @[VDecodeInstruction.scala 431:32]
-  wire [3:0] _op_T_14 = _GEN_82 | _op_T_13; // @[VDecodeInstruction.scala 431:32]
+  wire [3:0] _GEN_63 = {{1'd0}, _op_T_12}; // @[VDecodeInstruction.scala 390:32]
+  wire [3:0] _op_T_14 = _GEN_63 | _op_T_13; // @[VDecodeInstruction.scala 390:32]
   wire [3:0] _op_T_15 = veq ? 4'h9 : 4'h0; // @[Library.scala 18:8]
-  wire [3:0] _op_T_16 = _op_T_14 | _op_T_15; // @[VDecodeInstruction.scala 432:33]
+  wire [3:0] _op_T_16 = _op_T_14 | _op_T_15; // @[VDecodeInstruction.scala 391:33]
   wire [3:0] _op_T_17 = vne ? 4'ha : 4'h0; // @[Library.scala 18:8]
-  wire [3:0] _op_T_18 = _op_T_16 | _op_T_17; // @[VDecodeInstruction.scala 433:31]
+  wire [3:0] _op_T_18 = _op_T_16 | _op_T_17; // @[VDecodeInstruction.scala 392:31]
   wire [3:0] _op_T_19 = vlt ? 4'hb : 4'h0; // @[Library.scala 18:8]
-  wire [3:0] _op_T_20 = _op_T_18 | _op_T_19; // @[VDecodeInstruction.scala 434:31]
+  wire [3:0] _op_T_20 = _op_T_18 | _op_T_19; // @[VDecodeInstruction.scala 393:31]
   wire [3:0] _op_T_21 = vle ? 4'hc : 4'h0; // @[Library.scala 18:8]
-  wire [3:0] _op_T_22 = _op_T_20 | _op_T_21; // @[VDecodeInstruction.scala 435:31]
+  wire [3:0] _op_T_22 = _op_T_20 | _op_T_21; // @[VDecodeInstruction.scala 394:31]
   wire [3:0] _op_T_23 = vgt ? 4'hd : 4'h0; // @[Library.scala 18:8]
-  wire [3:0] _op_T_24 = _op_T_22 | _op_T_23; // @[VDecodeInstruction.scala 436:31]
+  wire [3:0] _op_T_24 = _op_T_22 | _op_T_23; // @[VDecodeInstruction.scala 395:31]
   wire [3:0] _op_T_25 = vge ? 4'he : 4'h0; // @[Library.scala 18:8]
-  wire [3:0] _op_T_26 = _op_T_24 | _op_T_25; // @[VDecodeInstruction.scala 437:31]
+  wire [3:0] _op_T_26 = _op_T_24 | _op_T_25; // @[VDecodeInstruction.scala 396:31]
   wire [3:0] _op_T_27 = vabsd ? 4'hf : 4'h0; // @[Library.scala 18:8]
-  wire [3:0] _op_T_28 = _op_T_26 | _op_T_27; // @[VDecodeInstruction.scala 438:31]
+  wire [3:0] _op_T_28 = _op_T_26 | _op_T_27; // @[VDecodeInstruction.scala 397:31]
   wire [4:0] _op_T_29 = vmax ? 5'h10 : 5'h0; // @[Library.scala 18:8]
-  wire [4:0] _GEN_83 = {{1'd0}, _op_T_28}; // @[VDecodeInstruction.scala 439:33]
-  wire [4:0] _op_T_30 = _GEN_83 | _op_T_29; // @[VDecodeInstruction.scala 439:33]
+  wire [4:0] _GEN_64 = {{1'd0}, _op_T_28}; // @[VDecodeInstruction.scala 398:33]
+  wire [4:0] _op_T_30 = _GEN_64 | _op_T_29; // @[VDecodeInstruction.scala 398:33]
   wire [4:0] _op_T_31 = vmin ? 5'h11 : 5'h0; // @[Library.scala 18:8]
-  wire [4:0] _op_T_32 = _op_T_30 | _op_T_31; // @[VDecodeInstruction.scala 440:32]
+  wire [4:0] _op_T_32 = _op_T_30 | _op_T_31; // @[VDecodeInstruction.scala 399:32]
   wire [4:0] _op_T_33 = vadd3 ? 5'h12 : 5'h0; // @[Library.scala 18:8]
-  wire [4:0] _op_T_34 = _op_T_32 | _op_T_33; // @[VDecodeInstruction.scala 441:32]
+  wire [4:0] _op_T_34 = _op_T_32 | _op_T_33; // @[VDecodeInstruction.scala 400:32]
   wire [4:0] _op_T_35 = vand ? 5'h13 : 5'h0; // @[Library.scala 18:8]
-  wire [4:0] _op_T_36 = _op_T_34 | _op_T_35; // @[VDecodeInstruction.scala 442:33]
+  wire [4:0] _op_T_36 = _op_T_34 | _op_T_35; // @[VDecodeInstruction.scala 401:33]
   wire [4:0] _op_T_37 = vor ? 5'h14 : 5'h0; // @[Library.scala 18:8]
-  wire [4:0] _op_T_38 = _op_T_36 | _op_T_37; // @[VDecodeInstruction.scala 444:32]
+  wire [4:0] _op_T_38 = _op_T_36 | _op_T_37; // @[VDecodeInstruction.scala 403:32]
   wire [4:0] _op_T_39 = vxor ? 5'h15 : 5'h0; // @[Library.scala 18:8]
-  wire [4:0] _op_T_40 = _op_T_38 | _op_T_39; // @[VDecodeInstruction.scala 445:31]
+  wire [4:0] _op_T_40 = _op_T_38 | _op_T_39; // @[VDecodeInstruction.scala 404:31]
   wire [4:0] _op_T_41 = vnot ? 5'h16 : 5'h0; // @[Library.scala 18:8]
-  wire [4:0] _op_T_42 = _op_T_40 | _op_T_41; // @[VDecodeInstruction.scala 446:32]
+  wire [4:0] _op_T_42 = _op_T_40 | _op_T_41; // @[VDecodeInstruction.scala 405:32]
   wire [4:0] _op_T_43 = vrev ? 5'h17 : 5'h0; // @[Library.scala 18:8]
-  wire [4:0] _op_T_44 = _op_T_42 | _op_T_43; // @[VDecodeInstruction.scala 447:32]
+  wire [4:0] _op_T_44 = _op_T_42 | _op_T_43; // @[VDecodeInstruction.scala 406:32]
   wire [4:0] _op_T_45 = vror ? 5'h18 : 5'h0; // @[Library.scala 18:8]
-  wire [4:0] _op_T_46 = _op_T_44 | _op_T_45; // @[VDecodeInstruction.scala 448:32]
+  wire [4:0] _op_T_46 = _op_T_44 | _op_T_45; // @[VDecodeInstruction.scala 407:32]
   wire [4:0] _op_T_47 = vclb ? 5'h19 : 5'h0; // @[Library.scala 18:8]
-  wire [4:0] _op_T_48 = _op_T_46 | _op_T_47; // @[VDecodeInstruction.scala 449:32]
+  wire [4:0] _op_T_48 = _op_T_46 | _op_T_47; // @[VDecodeInstruction.scala 408:32]
   wire [4:0] _op_T_49 = vclz ? 5'h1a : 5'h0; // @[Library.scala 18:8]
-  wire [4:0] _op_T_50 = _op_T_48 | _op_T_49; // @[VDecodeInstruction.scala 450:32]
+  wire [4:0] _op_T_50 = _op_T_48 | _op_T_49; // @[VDecodeInstruction.scala 409:32]
   wire [4:0] _op_T_51 = vcpop ? 5'h1b : 5'h0; // @[Library.scala 18:8]
-  wire [4:0] _op_T_52 = _op_T_50 | _op_T_51; // @[VDecodeInstruction.scala 451:32]
+  wire [4:0] _op_T_52 = _op_T_50 | _op_T_51; // @[VDecodeInstruction.scala 410:32]
   wire [4:0] _op_T_53 = vmv ? 5'h1c : 5'h0; // @[Library.scala 18:8]
-  wire [4:0] _op_T_54 = _op_T_52 | _op_T_53; // @[VDecodeInstruction.scala 452:33]
+  wire [4:0] _op_T_54 = _op_T_52 | _op_T_53; // @[VDecodeInstruction.scala 411:33]
   wire [4:0] _op_T_55 = vmv2 ? 5'h1d : 5'h0; // @[Library.scala 18:8]
-  wire [4:0] _op_T_56 = _op_T_54 | _op_T_55; // @[VDecodeInstruction.scala 453:31]
+  wire [4:0] _op_T_56 = _op_T_54 | _op_T_55; // @[VDecodeInstruction.scala 412:31]
   wire [4:0] _op_T_57 = vmvp ? 5'h1e : 5'h0; // @[Library.scala 18:8]
-  wire [4:0] _op_T_58 = _op_T_56 | _op_T_57; // @[VDecodeInstruction.scala 454:32]
+  wire [4:0] _op_T_58 = _op_T_56 | _op_T_57; // @[VDecodeInstruction.scala 413:32]
   wire [4:0] _op_T_59 = acset ? 5'h1f : 5'h0; // @[Library.scala 18:8]
-  wire [4:0] _op_T_60 = _op_T_58 | _op_T_59; // @[VDecodeInstruction.scala 455:32]
+  wire [4:0] _op_T_60 = _op_T_58 | _op_T_59; // @[VDecodeInstruction.scala 414:32]
   wire [5:0] _op_T_61 = actr ? 6'h20 : 6'h0; // @[Library.scala 18:8]
-  wire [5:0] _GEN_84 = {{1'd0}, _op_T_60}; // @[VDecodeInstruction.scala 456:33]
-  wire [5:0] _op_T_62 = _GEN_84 | _op_T_61; // @[VDecodeInstruction.scala 456:33]
+  wire [5:0] _GEN_65 = {{1'd0}, _op_T_60}; // @[VDecodeInstruction.scala 415:33]
+  wire [5:0] _op_T_62 = _GEN_65 | _op_T_61; // @[VDecodeInstruction.scala 415:33]
   wire [5:0] _op_T_63 = adwinit ? 6'h21 : 6'h0; // @[Library.scala 18:8]
-  wire [5:0] _op_T_64 = _op_T_62 | _op_T_63; // @[VDecodeInstruction.scala 457:32]
+  wire [5:0] _op_T_64 = _op_T_62 | _op_T_63; // @[VDecodeInstruction.scala 416:32]
   wire [5:0] _op_T_65 = vsll ? 6'h22 : 6'h0; // @[Library.scala 18:8]
-  wire [5:0] _op_T_66 = _op_T_64 | _op_T_65; // @[VDecodeInstruction.scala 458:37]
+  wire [5:0] _op_T_66 = _op_T_64 | _op_T_65; // @[VDecodeInstruction.scala 417:37]
   wire [5:0] _op_T_67 = vsra ? 6'h23 : 6'h0; // @[Library.scala 18:8]
-  wire [5:0] _op_T_68 = _op_T_66 | _op_T_67; // @[VDecodeInstruction.scala 460:33]
+  wire [5:0] _op_T_68 = _op_T_66 | _op_T_67; // @[VDecodeInstruction.scala 419:33]
   wire [5:0] _op_T_69 = vsrl ? 6'h23 : 6'h0; // @[Library.scala 18:8]
-  wire [5:0] _op_T_70 = _op_T_68 | _op_T_69; // @[VDecodeInstruction.scala 461:33]
+  wire [5:0] _op_T_70 = _op_T_68 | _op_T_69; // @[VDecodeInstruction.scala 420:33]
   wire [5:0] _op_T_71 = vsha ? 6'h24 : 6'h0; // @[Library.scala 18:8]
-  wire [5:0] _op_T_72 = _op_T_70 | _op_T_71; // @[VDecodeInstruction.scala 462:33]
+  wire [5:0] _op_T_72 = _op_T_70 | _op_T_71; // @[VDecodeInstruction.scala 421:33]
   wire [5:0] _op_T_73 = vshl ? 6'h24 : 6'h0; // @[Library.scala 18:8]
-  wire [5:0] _op_T_74 = _op_T_72 | _op_T_73; // @[VDecodeInstruction.scala 463:33]
+  wire [5:0] _op_T_74 = _op_T_72 | _op_T_73; // @[VDecodeInstruction.scala 422:33]
   wire [5:0] _op_T_75 = vsrans ? 6'h25 : 6'h0; // @[Library.scala 18:8]
-  wire [5:0] _op_T_76 = _op_T_74 | _op_T_75; // @[VDecodeInstruction.scala 464:33]
+  wire [5:0] _op_T_76 = _op_T_74 | _op_T_75; // @[VDecodeInstruction.scala 423:33]
   wire [5:0] _op_T_77 = vsraqs ? 6'h26 : 6'h0; // @[Library.scala 18:8]
-  wire [5:0] _op_T_78 = _op_T_76 | _op_T_77; // @[VDecodeInstruction.scala 465:35]
+  wire [5:0] _op_T_78 = _op_T_76 | _op_T_77; // @[VDecodeInstruction.scala 424:35]
   wire [5:0] _op_T_79 = vmul ? 6'h27 : 6'h0; // @[Library.scala 18:8]
-  wire [5:0] _op_T_80 = _op_T_78 | _op_T_79; // @[VDecodeInstruction.scala 466:35]
+  wire [5:0] _op_T_80 = _op_T_78 | _op_T_79; // @[VDecodeInstruction.scala 425:35]
   wire [5:0] _op_T_81 = vmul2 ? 6'h28 : 6'h0; // @[Library.scala 18:8]
-  wire [5:0] _op_T_82 = _op_T_80 | _op_T_81; // @[VDecodeInstruction.scala 468:34]
+  wire [5:0] _op_T_82 = _op_T_80 | _op_T_81; // @[VDecodeInstruction.scala 427:34]
   wire [5:0] _op_T_83 = vmuls ? 6'h29 : 6'h0; // @[Library.scala 18:8]
-  wire [5:0] _op_T_84 = _op_T_82 | _op_T_83; // @[VDecodeInstruction.scala 469:35]
+  wire [5:0] _op_T_84 = _op_T_82 | _op_T_83; // @[VDecodeInstruction.scala 428:35]
   wire [5:0] _op_T_85 = vmuls2 ? 6'h2a : 6'h0; // @[Library.scala 18:8]
-  wire [5:0] _op_T_86 = _op_T_84 | _op_T_85; // @[VDecodeInstruction.scala 470:35]
+  wire [5:0] _op_T_86 = _op_T_84 | _op_T_85; // @[VDecodeInstruction.scala 429:35]
   wire [5:0] _op_T_87 = vmulh ? 6'h2b : 6'h0; // @[Library.scala 18:8]
-  wire [5:0] _op_T_88 = _op_T_86 | _op_T_87; // @[VDecodeInstruction.scala 471:36]
+  wire [5:0] _op_T_88 = _op_T_86 | _op_T_87; // @[VDecodeInstruction.scala 430:36]
   wire [5:0] _op_T_89 = vmulh2 ? 6'h2c : 6'h0; // @[Library.scala 18:8]
-  wire [5:0] _op_T_90 = _op_T_88 | _op_T_89; // @[VDecodeInstruction.scala 472:35]
+  wire [5:0] _op_T_90 = _op_T_88 | _op_T_89; // @[VDecodeInstruction.scala 431:35]
   wire [5:0] _op_T_91 = vmulhu ? 6'h2b : 6'h0; // @[Library.scala 18:8]
-  wire [5:0] _op_T_92 = _op_T_90 | _op_T_91; // @[VDecodeInstruction.scala 473:36]
+  wire [5:0] _op_T_92 = _op_T_90 | _op_T_91; // @[VDecodeInstruction.scala 432:36]
   wire [5:0] _op_T_93 = vmulhu2 ? 6'h2c : 6'h0; // @[Library.scala 18:8]
-  wire [5:0] _op_T_94 = _op_T_92 | _op_T_93; // @[VDecodeInstruction.scala 474:35]
+  wire [5:0] _op_T_94 = _op_T_92 | _op_T_93; // @[VDecodeInstruction.scala 433:35]
   wire [5:0] _op_T_95 = vdmulh ? 6'h2d : 6'h0; // @[Library.scala 18:8]
-  wire [5:0] _op_T_96 = _op_T_94 | _op_T_95; // @[VDecodeInstruction.scala 475:36]
+  wire [5:0] _op_T_96 = _op_T_94 | _op_T_95; // @[VDecodeInstruction.scala 434:36]
   wire [5:0] _op_T_97 = vdmulh2 ? 6'h2e : 6'h0; // @[Library.scala 18:8]
-  wire [5:0] _op_T_98 = _op_T_96 | _op_T_97; // @[VDecodeInstruction.scala 476:36]
+  wire [5:0] _op_T_98 = _op_T_96 | _op_T_97; // @[VDecodeInstruction.scala 435:36]
   wire [5:0] _op_T_99 = vmulw ? 6'h2f : 6'h0; // @[Library.scala 18:8]
-  wire [5:0] _op_T_100 = _op_T_98 | _op_T_99; // @[VDecodeInstruction.scala 477:37]
+  wire [5:0] _op_T_100 = _op_T_98 | _op_T_99; // @[VDecodeInstruction.scala 436:37]
   wire [5:0] _op_T_101 = vmacc ? 6'h30 : 6'h0; // @[Library.scala 18:8]
-  wire [5:0] _op_T_102 = _op_T_100 | _op_T_101; // @[VDecodeInstruction.scala 478:35]
+  wire [5:0] _op_T_102 = _op_T_100 | _op_T_101; // @[VDecodeInstruction.scala 437:35]
   wire [5:0] _op_T_103 = vmadd ? 6'h30 : 6'h0; // @[Library.scala 18:8]
-  wire [5:0] _op_T_104 = _op_T_102 | _op_T_103; // @[VDecodeInstruction.scala 479:35]
-  wire [5:0] _op_T_105 = vdiv ? 6'h31 : 6'h0; // @[Library.scala 18:8]
-  wire [5:0] _op_T_106 = _op_T_104 | _op_T_105; // @[VDecodeInstruction.scala 480:35]
-  wire [5:0] _op_T_107 = vrem ? 6'h32 : 6'h0; // @[Library.scala 18:8]
-  wire [5:0] _op_T_108 = _op_T_106 | _op_T_107; // @[VDecodeInstruction.scala 481:34]
-  wire [5:0] _op_T_109 = vadds ? 6'h33 : 6'h0; // @[Library.scala 18:8]
-  wire [5:0] _op_T_110 = _op_T_108 | _op_T_109; // @[VDecodeInstruction.scala 482:34]
-  wire [5:0] _op_T_111 = vsubs ? 6'h34 : 6'h0; // @[Library.scala 18:8]
-  wire [5:0] _op_T_112 = _op_T_110 | _op_T_111; // @[VDecodeInstruction.scala 484:34]
-  wire [5:0] _op_T_113 = vaddw ? 6'h35 : 6'h0; // @[Library.scala 18:8]
-  wire [5:0] _op_T_114 = _op_T_112 | _op_T_113; // @[VDecodeInstruction.scala 485:34]
-  wire [5:0] _op_T_115 = vsubw ? 6'h36 : 6'h0; // @[Library.scala 18:8]
-  wire [5:0] _op_T_116 = _op_T_114 | _op_T_115; // @[VDecodeInstruction.scala 486:34]
-  wire [5:0] _op_T_117 = vacc ? 6'h37 : 6'h0; // @[Library.scala 18:8]
-  wire [5:0] _op_T_118 = _op_T_116 | _op_T_117; // @[VDecodeInstruction.scala 487:34]
-  wire [5:0] _op_T_119 = vpadd ? 6'h38 : 6'h0; // @[Library.scala 18:8]
-  wire [5:0] _op_T_120 = _op_T_118 | _op_T_119; // @[VDecodeInstruction.scala 488:33]
-  wire [5:0] _op_T_121 = vpsub ? 6'h39 : 6'h0; // @[Library.scala 18:8]
-  wire [5:0] _op_T_122 = _op_T_120 | _op_T_121; // @[VDecodeInstruction.scala 489:34]
-  wire [5:0] _op_T_123 = vhadd ? 6'h3a : 6'h0; // @[Library.scala 18:8]
-  wire [5:0] _op_T_124 = _op_T_122 | _op_T_123; // @[VDecodeInstruction.scala 490:34]
-  wire [5:0] _op_T_125 = vhsub ? 6'h3b : 6'h0; // @[Library.scala 18:8]
-  wire [5:0] _op_T_126 = _op_T_124 | _op_T_125; // @[VDecodeInstruction.scala 491:34]
-  wire [5:0] _op_T_127 = vfadd ? 6'h3c : 6'h0; // @[Library.scala 18:8]
-  wire [5:0] _op_T_128 = _op_T_126 | _op_T_127; // @[VDecodeInstruction.scala 492:34]
-  wire [5:0] _op_T_129 = vfsub ? 6'h3d : 6'h0; // @[Library.scala 18:8]
-  wire [5:0] _op_T_130 = _op_T_128 | _op_T_129; // @[VDecodeInstruction.scala 494:35]
-  wire [5:0] _op_T_131 = vfmul ? 6'h3e : 6'h0; // @[Library.scala 18:8]
-  wire [5:0] _op_T_132 = _op_T_130 | _op_T_131; // @[VDecodeInstruction.scala 495:35]
-  wire [5:0] _op_T_133 = vfabsd ? 6'h3f : 6'h0; // @[Library.scala 18:8]
-  wire [5:0] _op_T_134 = _op_T_132 | _op_T_133; // @[VDecodeInstruction.scala 496:35]
-  wire [6:0] _op_T_135 = vfmadd ? 7'h40 : 7'h0; // @[Library.scala 18:8]
-  wire [6:0] _GEN_85 = {{1'd0}, _op_T_134}; // @[VDecodeInstruction.scala 497:36]
-  wire [6:0] _op_T_136 = _GEN_85 | _op_T_135; // @[VDecodeInstruction.scala 497:36]
-  wire [6:0] _op_T_137 = vfmsub ? 7'h41 : 7'h0; // @[Library.scala 18:8]
-  wire [6:0] _op_T_138 = _op_T_136 | _op_T_137; // @[VDecodeInstruction.scala 498:36]
-  wire [6:0] _op_T_139 = vfnmsub ? 7'h42 : 7'h0; // @[Library.scala 18:8]
-  wire [6:0] _op_T_140 = _op_T_138 | _op_T_139; // @[VDecodeInstruction.scala 499:36]
-  wire [6:0] _op_T_141 = vfnmadd ? 7'h43 : 7'h0; // @[Library.scala 18:8]
-  wire [6:0] _op_T_142 = _op_T_140 | _op_T_141; // @[VDecodeInstruction.scala 500:37]
-  wire [6:0] _op_T_143 = vfdiv ? 7'h44 : 7'h0; // @[Library.scala 18:8]
-  wire [6:0] _op_T_144 = _op_T_142 | _op_T_143; // @[VDecodeInstruction.scala 501:37]
-  wire [6:0] _op_T_145 = vfrdiv ? 7'h45 : 7'h0; // @[Library.scala 18:8]
-  wire [6:0] _op_T_146 = _op_T_144 | _op_T_145; // @[VDecodeInstruction.scala 502:35]
-  wire [6:0] _op_T_147 = vfsqrt ? 7'h46 : 7'h0; // @[Library.scala 18:8]
-  wire [6:0] _op_T_148 = _op_T_146 | _op_T_147; // @[VDecodeInstruction.scala 503:36]
-  wire [6:0] _op_T_149 = vfsgnj ? 7'h47 : 7'h0; // @[Library.scala 18:8]
-  wire [6:0] _op_T_150 = _op_T_148 | _op_T_149; // @[VDecodeInstruction.scala 504:36]
-  wire [6:0] _op_T_151 = vfsgnjn ? 7'h48 : 7'h0; // @[Library.scala 18:8]
-  wire [6:0] _op_T_152 = _op_T_150 | _op_T_151; // @[VDecodeInstruction.scala 505:36]
-  wire [6:0] _op_T_153 = vfsgnjx ? 7'h49 : 7'h0; // @[Library.scala 18:8]
-  wire [6:0] _op_T_154 = _op_T_152 | _op_T_153; // @[VDecodeInstruction.scala 506:37]
-  wire [6:0] _op_T_155 = vfmin ? 7'h4a : 7'h0; // @[Library.scala 18:8]
-  wire [6:0] _op_T_156 = _op_T_154 | _op_T_155; // @[VDecodeInstruction.scala 507:37]
-  wire [6:0] _op_T_157 = vfmax ? 7'h4b : 7'h0; // @[Library.scala 18:8]
-  wire [6:0] _op_T_158 = _op_T_156 | _op_T_157; // @[VDecodeInstruction.scala 508:35]
-  wire [6:0] _op_T_159 = vfcvt_s_w ? 7'h4c : 7'h0; // @[Library.scala 18:8]
-  wire [6:0] _op_T_160 = _op_T_158 | _op_T_159; // @[VDecodeInstruction.scala 509:35]
-  wire [6:0] _op_T_161 = vfcvt_s_wu ? 7'h4d : 7'h0; // @[Library.scala 18:8]
-  wire [6:0] _op_T_162 = _op_T_160 | _op_T_161; // @[VDecodeInstruction.scala 510:42]
-  wire [6:0] _op_T_163 = vfcvt_w_s ? 7'h4e : 7'h0; // @[Library.scala 18:8]
-  wire [6:0] _op_T_164 = _op_T_162 | _op_T_163; // @[VDecodeInstruction.scala 511:43]
-  wire [6:0] _op_T_165 = vfcvt_wu_s ? 7'h4f : 7'h0; // @[Library.scala 18:8]
-  wire [6:0] _op_T_166 = _op_T_164 | _op_T_165; // @[VDecodeInstruction.scala 512:42]
-  wire [6:0] _op_T_167 = vflt ? 7'h50 : 7'h0; // @[Library.scala 18:8]
-  wire [6:0] _op_T_168 = _op_T_166 | _op_T_167; // @[VDecodeInstruction.scala 513:43]
-  wire [6:0] _op_T_169 = vfle ? 7'h51 : 7'h0; // @[Library.scala 18:8]
-  wire [6:0] _op_T_170 = _op_T_168 | _op_T_169; // @[VDecodeInstruction.scala 514:31]
-  wire [6:0] _op_T_171 = vfgt ? 7'h52 : 7'h0; // @[Library.scala 18:8]
-  wire [6:0] _op_T_172 = _op_T_170 | _op_T_171; // @[VDecodeInstruction.scala 515:31]
-  wire [6:0] _op_T_173 = vfge ? 7'h53 : 7'h0; // @[Library.scala 18:8]
-  wire [6:0] _op_T_174 = _op_T_172 | _op_T_173; // @[VDecodeInstruction.scala 516:31]
-  wire [6:0] _op_T_175 = vfeq ? 7'h54 : 7'h0; // @[Library.scala 18:8]
-  wire [6:0] _op_T_176 = _op_T_174 | _op_T_175; // @[VDecodeInstruction.scala 517:31]
-  wire [6:0] _op_T_177 = vfne ? 7'h55 : 7'h0; // @[Library.scala 18:8]
-  wire [6:0] _op_T_178 = _op_T_176 | _op_T_177; // @[VDecodeInstruction.scala 518:31]
-  wire [6:0] _op_T_179 = vslidevn ? 7'h56 : 7'h0; // @[Library.scala 18:8]
-  wire [6:0] _op_T_180 = _op_T_178 | _op_T_179; // @[VDecodeInstruction.scala 519:31]
-  wire [6:0] _op_T_181 = vslidehn ? 7'h57 : 7'h0; // @[Library.scala 18:8]
-  wire [6:0] _op_T_182 = _op_T_180 | _op_T_181; // @[VDecodeInstruction.scala 521:40]
-  wire [6:0] _op_T_183 = vslidehn2 ? 7'h58 : 7'h0; // @[Library.scala 18:8]
-  wire [6:0] _op_T_184 = _op_T_182 | _op_T_183; // @[VDecodeInstruction.scala 522:40]
-  wire [6:0] _op_T_185 = vslidevp ? 7'h59 : 7'h0; // @[Library.scala 18:8]
-  wire [6:0] _op_T_186 = _op_T_184 | _op_T_185; // @[VDecodeInstruction.scala 523:41]
-  wire [6:0] _op_T_187 = vslidehp ? 7'h5a : 7'h0; // @[Library.scala 18:8]
-  wire [6:0] _op_T_188 = _op_T_186 | _op_T_187; // @[VDecodeInstruction.scala 524:40]
-  wire [6:0] _op_T_189 = vslidehp2 ? 7'h5b : 7'h0; // @[Library.scala 18:8]
-  wire [6:0] _op_T_190 = _op_T_188 | _op_T_189; // @[VDecodeInstruction.scala 525:40]
-  wire [6:0] _op_T_191 = vsel ? 7'h5c : 7'h0; // @[Library.scala 18:8]
-  wire [6:0] _op_T_192 = _op_T_190 | _op_T_191; // @[VDecodeInstruction.scala 526:41]
-  wire [6:0] _op_T_193 = vevn ? 7'h5d : 7'h0; // @[Library.scala 18:8]
-  wire [6:0] _op_T_194 = _op_T_192 | _op_T_193; // @[VDecodeInstruction.scala 527:35]
-  wire [6:0] _op_T_195 = vodd ? 7'h5e : 7'h0; // @[Library.scala 18:8]
-  wire [6:0] _op_T_196 = _op_T_194 | _op_T_195; // @[VDecodeInstruction.scala 528:35]
-  wire [6:0] _op_T_197 = vevnodd ? 7'h5f : 7'h0; // @[Library.scala 18:8]
-  wire [6:0] _op_T_198 = _op_T_196 | _op_T_197; // @[VDecodeInstruction.scala 529:35]
-  wire [6:0] _op_T_199 = vzip ? 7'h60 : 7'h0; // @[Library.scala 18:8]
-  wire [6:0] _op_T_200 = _op_T_198 | _op_T_199; // @[VDecodeInstruction.scala 530:38]
-  wire [6:0] _op_T_201 = vfmadd4 ? 7'h61 : 7'h0; // @[Library.scala 18:8]
-  wire [6:0] _op_T_202 = _op_T_200 | _op_T_201; // @[VDecodeInstruction.scala 531:35]
-  wire [6:0] _op_T_203 = aconv ? 7'h62 : 7'h0; // @[Library.scala 18:8]
-  wire [6:0] _op_T_204 = _op_T_202 | _op_T_203; // @[VDecodeInstruction.scala 533:38]
-  wire [6:0] _op_T_205 = vdwconv ? 7'h63 : 7'h0; // @[Library.scala 18:8]
-  wire [6:0] _op_T_206 = _op_T_204 | _op_T_205; // @[VDecodeInstruction.scala 534:36]
-  wire [6:0] _op_T_207 = adwconv ? 7'h64 : 7'h0; // @[Library.scala 18:8]
-  wire [3:0] regbase = io_in_data[7:4]; // @[VDecodeInstruction.scala 154:23]
-  wire [3:0] _GEN_1 = 4'h1 == regbase ? 4'h1 : 4'h0; // @[VDecodeInstruction.scala 156:{21,21}]
-  wire [3:0] _GEN_2 = 4'h2 == regbase ? 4'h2 : _GEN_1; // @[VDecodeInstruction.scala 156:{21,21}]
-  wire [3:0] _GEN_3 = 4'h3 == regbase ? 4'h3 : _GEN_2; // @[VDecodeInstruction.scala 156:{21,21}]
-  wire [3:0] _GEN_4 = 4'h4 == regbase ? 4'h4 : _GEN_3; // @[VDecodeInstruction.scala 156:{21,21}]
-  wire [3:0] _GEN_5 = 4'h5 == regbase ? 4'h5 : _GEN_4; // @[VDecodeInstruction.scala 156:{21,21}]
-  wire [3:0] _GEN_6 = 4'h6 == regbase ? 4'h6 : _GEN_5; // @[VDecodeInstruction.scala 156:{21,21}]
-  wire [3:0] _GEN_7 = 4'h7 == regbase ? 4'h1 : _GEN_6; // @[VDecodeInstruction.scala 156:{21,21}]
-  wire [3:0] _GEN_8 = 4'h8 == regbase ? 4'h1 : _GEN_7; // @[VDecodeInstruction.scala 156:{21,21}]
-  wire [3:0] _GEN_9 = 4'h9 == regbase ? 4'h3 : _GEN_8; // @[VDecodeInstruction.scala 156:{21,21}]
-  wire [3:0] _GEN_10 = 4'ha == regbase ? 4'h5 : _GEN_9; // @[VDecodeInstruction.scala 156:{21,21}]
-  wire [3:0] _GEN_11 = 4'hb == regbase ? 4'h7 : _GEN_10; // @[VDecodeInstruction.scala 156:{21,21}]
-  wire [3:0] _GEN_12 = 4'hc == regbase ? 4'h2 : _GEN_11; // @[VDecodeInstruction.scala 156:{21,21}]
-  wire [3:0] _GEN_13 = 4'hd == regbase ? 4'h4 : _GEN_12; // @[VDecodeInstruction.scala 156:{21,21}]
-  wire [3:0] _GEN_14 = 4'he == regbase ? 4'h6 : _GEN_13; // @[VDecodeInstruction.scala 156:{21,21}]
-  wire [3:0] _GEN_15 = 4'hf == regbase ? 4'h8 : _GEN_14; // @[VDecodeInstruction.scala 156:{21,21}]
-  wire [5:0] _GEN_86 = {{2'd0}, _GEN_15}; // @[VDecodeInstruction.scala 156:21]
-  wire [5:0] vsdw = vsbits + _GEN_86; // @[VDecodeInstruction.scala 156:21]
-  wire [3:0] _GEN_17 = 4'h1 == regbase ? 4'h2 : 4'h1; // @[VDecodeInstruction.scala 157:{21,21}]
-  wire [3:0] _GEN_18 = 4'h2 == regbase ? 4'h3 : _GEN_17; // @[VDecodeInstruction.scala 157:{21,21}]
-  wire [3:0] _GEN_19 = 4'h3 == regbase ? 4'h4 : _GEN_18; // @[VDecodeInstruction.scala 157:{21,21}]
-  wire [3:0] _GEN_20 = 4'h4 == regbase ? 4'h5 : _GEN_19; // @[VDecodeInstruction.scala 157:{21,21}]
-  wire [3:0] _GEN_21 = 4'h5 == regbase ? 4'h6 : _GEN_20; // @[VDecodeInstruction.scala 157:{21,21}]
-  wire [3:0] _GEN_22 = 4'h6 == regbase ? 4'h7 : _GEN_21; // @[VDecodeInstruction.scala 157:{21,21}]
-  wire [3:0] _GEN_23 = 4'h7 == regbase ? 4'h0 : _GEN_22; // @[VDecodeInstruction.scala 157:{21,21}]
-  wire [3:0] _GEN_24 = 4'h8 == regbase ? 4'h2 : _GEN_23; // @[VDecodeInstruction.scala 157:{21,21}]
-  wire [3:0] _GEN_25 = 4'h9 == regbase ? 4'h4 : _GEN_24; // @[VDecodeInstruction.scala 157:{21,21}]
-  wire [3:0] _GEN_26 = 4'ha == regbase ? 4'h6 : _GEN_25; // @[VDecodeInstruction.scala 157:{21,21}]
-  wire [3:0] _GEN_27 = 4'hb == regbase ? 4'h8 : _GEN_26; // @[VDecodeInstruction.scala 157:{21,21}]
-  wire [3:0] _GEN_28 = 4'hc == regbase ? 4'h0 : _GEN_27; // @[VDecodeInstruction.scala 157:{21,21}]
-  wire [3:0] _GEN_29 = 4'hd == regbase ? 4'h0 : _GEN_28; // @[VDecodeInstruction.scala 157:{21,21}]
-  wire [3:0] _GEN_30 = 4'he == regbase ? 4'h0 : _GEN_29; // @[VDecodeInstruction.scala 157:{21,21}]
-  wire [3:0] _GEN_31 = 4'hf == regbase ? 4'h0 : _GEN_30; // @[VDecodeInstruction.scala 157:{21,21}]
-  wire [5:0] _GEN_87 = {{2'd0}, _GEN_31}; // @[VDecodeInstruction.scala 157:21]
-  wire [5:0] vtdw = vsbits + _GEN_87; // @[VDecodeInstruction.scala 157:21]
-  wire [3:0] _GEN_33 = 4'h1 == regbase ? 4'h3 : 4'h2; // @[VDecodeInstruction.scala 158:{21,21}]
-  wire [3:0] _GEN_34 = 4'h2 == regbase ? 4'h4 : _GEN_33; // @[VDecodeInstruction.scala 158:{21,21}]
-  wire [3:0] _GEN_35 = 4'h3 == regbase ? 4'h5 : _GEN_34; // @[VDecodeInstruction.scala 158:{21,21}]
-  wire [3:0] _GEN_36 = 4'h4 == regbase ? 4'h6 : _GEN_35; // @[VDecodeInstruction.scala 158:{21,21}]
-  wire [3:0] _GEN_37 = 4'h5 == regbase ? 4'h7 : _GEN_36; // @[VDecodeInstruction.scala 158:{21,21}]
-  wire [3:0] _GEN_38 = 4'h6 == regbase ? 4'h8 : _GEN_37; // @[VDecodeInstruction.scala 158:{21,21}]
-  wire [3:0] _GEN_39 = 4'h7 == regbase ? 4'h2 : _GEN_38; // @[VDecodeInstruction.scala 158:{21,21}]
-  wire [3:0] _GEN_40 = 4'h8 == regbase ? 4'h0 : _GEN_39; // @[VDecodeInstruction.scala 158:{21,21}]
-  wire [3:0] _GEN_41 = 4'h9 == regbase ? 4'h0 : _GEN_40; // @[VDecodeInstruction.scala 158:{21,21}]
-  wire [3:0] _GEN_42 = 4'ha == regbase ? 4'h0 : _GEN_41; // @[VDecodeInstruction.scala 158:{21,21}]
-  wire [3:0] _GEN_43 = 4'hb == regbase ? 4'h0 : _GEN_42; // @[VDecodeInstruction.scala 158:{21,21}]
-  wire [3:0] _GEN_44 = 4'hc == regbase ? 4'h1 : _GEN_43; // @[VDecodeInstruction.scala 158:{21,21}]
-  wire [3:0] _GEN_45 = 4'hd == regbase ? 4'h1 : _GEN_44; // @[VDecodeInstruction.scala 158:{21,21}]
-  wire [3:0] _GEN_46 = 4'he == regbase ? 4'h1 : _GEN_45; // @[VDecodeInstruction.scala 158:{21,21}]
-  wire [3:0] _GEN_47 = 4'hf == regbase ? 4'h1 : _GEN_46; // @[VDecodeInstruction.scala 158:{21,21}]
-  wire [5:0] _GEN_88 = {{2'd0}, _GEN_47}; // @[VDecodeInstruction.scala 158:21]
-  wire [5:0] vudw = vsbits + _GEN_88; // @[VDecodeInstruction.scala 158:21]
-  wire [2:0] _vy_T = m ? 3'h4 : 3'h1; // @[VDecodeInstruction.scala 164:26]
-  wire [5:0] _GEN_89 = {{3'd0}, _vy_T}; // @[VDecodeInstruction.scala 164:21]
-  wire [5:0] vydw = func2 + _GEN_89; // @[VDecodeInstruction.scala 164:21]
-  wire [3:0] _vz_T = m ? 4'h8 : 4'h2; // @[VDecodeInstruction.scala 165:26]
-  wire [5:0] _GEN_90 = {{2'd0}, _vz_T}; // @[VDecodeInstruction.scala 165:21]
-  wire [5:0] vzdw = func2 + _GEN_90; // @[VDecodeInstruction.scala 165:21]
+  wire [5:0] _op_T_104 = _op_T_102 | _op_T_103; // @[VDecodeInstruction.scala 438:35]
+  wire [5:0] _op_T_105 = vadds ? 6'h31 : 6'h0; // @[Library.scala 18:8]
+  wire [5:0] _op_T_106 = _op_T_104 | _op_T_105; // @[VDecodeInstruction.scala 439:35]
+  wire [5:0] _op_T_107 = vsubs ? 6'h32 : 6'h0; // @[Library.scala 18:8]
+  wire [5:0] _op_T_108 = _op_T_106 | _op_T_107; // @[VDecodeInstruction.scala 441:34]
+  wire [5:0] _op_T_109 = vaddw ? 6'h33 : 6'h0; // @[Library.scala 18:8]
+  wire [5:0] _op_T_110 = _op_T_108 | _op_T_109; // @[VDecodeInstruction.scala 442:34]
+  wire [5:0] _op_T_111 = vsubw ? 6'h34 : 6'h0; // @[Library.scala 18:8]
+  wire [5:0] _op_T_112 = _op_T_110 | _op_T_111; // @[VDecodeInstruction.scala 443:34]
+  wire [5:0] _op_T_113 = vacc ? 6'h35 : 6'h0; // @[Library.scala 18:8]
+  wire [5:0] _op_T_114 = _op_T_112 | _op_T_113; // @[VDecodeInstruction.scala 444:34]
+  wire [5:0] _op_T_115 = vpadd ? 6'h36 : 6'h0; // @[Library.scala 18:8]
+  wire [5:0] _op_T_116 = _op_T_114 | _op_T_115; // @[VDecodeInstruction.scala 445:33]
+  wire [5:0] _op_T_117 = vpsub ? 6'h37 : 6'h0; // @[Library.scala 18:8]
+  wire [5:0] _op_T_118 = _op_T_116 | _op_T_117; // @[VDecodeInstruction.scala 446:34]
+  wire [5:0] _op_T_119 = vhadd ? 6'h38 : 6'h0; // @[Library.scala 18:8]
+  wire [5:0] _op_T_120 = _op_T_118 | _op_T_119; // @[VDecodeInstruction.scala 447:34]
+  wire [5:0] _op_T_121 = vhsub ? 6'h39 : 6'h0; // @[Library.scala 18:8]
+  wire [5:0] _op_T_122 = _op_T_120 | _op_T_121; // @[VDecodeInstruction.scala 448:34]
+  wire [5:0] _op_T_123 = vslidevn ? 6'h3a : 6'h0; // @[Library.scala 18:8]
+  wire [5:0] _op_T_124 = _op_T_122 | _op_T_123; // @[VDecodeInstruction.scala 449:34]
+  wire [5:0] _op_T_125 = vslidehn ? 6'h3b : 6'h0; // @[Library.scala 18:8]
+  wire [5:0] _op_T_126 = _op_T_124 | _op_T_125; // @[VDecodeInstruction.scala 451:40]
+  wire [5:0] _op_T_127 = vslidehn2 ? 6'h3c : 6'h0; // @[Library.scala 18:8]
+  wire [5:0] _op_T_128 = _op_T_126 | _op_T_127; // @[VDecodeInstruction.scala 452:40]
+  wire [5:0] _op_T_129 = vslidevp ? 6'h3d : 6'h0; // @[Library.scala 18:8]
+  wire [5:0] _op_T_130 = _op_T_128 | _op_T_129; // @[VDecodeInstruction.scala 453:41]
+  wire [5:0] _op_T_131 = vslidehp ? 6'h3e : 6'h0; // @[Library.scala 18:8]
+  wire [5:0] _op_T_132 = _op_T_130 | _op_T_131; // @[VDecodeInstruction.scala 454:40]
+  wire [5:0] _op_T_133 = vslidehp2 ? 6'h3f : 6'h0; // @[Library.scala 18:8]
+  wire [5:0] _op_T_134 = _op_T_132 | _op_T_133; // @[VDecodeInstruction.scala 455:40]
+  wire [6:0] _op_T_135 = vsel ? 7'h40 : 7'h0; // @[Library.scala 18:8]
+  wire [6:0] _GEN_66 = {{1'd0}, _op_T_134}; // @[VDecodeInstruction.scala 456:41]
+  wire [6:0] _op_T_136 = _GEN_66 | _op_T_135; // @[VDecodeInstruction.scala 456:41]
+  wire [6:0] _op_T_137 = vevn ? 7'h41 : 7'h0; // @[Library.scala 18:8]
+  wire [6:0] _op_T_138 = _op_T_136 | _op_T_137; // @[VDecodeInstruction.scala 457:35]
+  wire [6:0] _op_T_139 = vodd ? 7'h42 : 7'h0; // @[Library.scala 18:8]
+  wire [6:0] _op_T_140 = _op_T_138 | _op_T_139; // @[VDecodeInstruction.scala 458:35]
+  wire [6:0] _op_T_141 = vevnodd ? 7'h43 : 7'h0; // @[Library.scala 18:8]
+  wire [6:0] _op_T_142 = _op_T_140 | _op_T_141; // @[VDecodeInstruction.scala 459:35]
+  wire [6:0] _op_T_143 = vzip ? 7'h44 : 7'h0; // @[Library.scala 18:8]
+  wire [6:0] _op_T_144 = _op_T_142 | _op_T_143; // @[VDecodeInstruction.scala 460:38]
+  wire [6:0] _op_T_145 = aconv ? 7'h45 : 7'h0; // @[Library.scala 18:8]
+  wire [6:0] _op_T_146 = _op_T_144 | _op_T_145; // @[VDecodeInstruction.scala 461:35]
+  wire [6:0] _op_T_147 = vdwconv ? 7'h46 : 7'h0; // @[Library.scala 18:8]
+  wire [6:0] _op_T_148 = _op_T_146 | _op_T_147; // @[VDecodeInstruction.scala 463:36]
+  wire [6:0] _op_T_149 = adwconv ? 7'h47 : 7'h0; // @[Library.scala 18:8]
+  wire [3:0] regbase = io_in_data[7:4]; // @[VDecodeInstruction.scala 149:23]
+  wire [3:0] _GEN_1 = 4'h1 == regbase ? 4'h1 : 4'h0; // @[VDecodeInstruction.scala 151:{21,21}]
+  wire [3:0] _GEN_2 = 4'h2 == regbase ? 4'h2 : _GEN_1; // @[VDecodeInstruction.scala 151:{21,21}]
+  wire [3:0] _GEN_3 = 4'h3 == regbase ? 4'h3 : _GEN_2; // @[VDecodeInstruction.scala 151:{21,21}]
+  wire [3:0] _GEN_4 = 4'h4 == regbase ? 4'h4 : _GEN_3; // @[VDecodeInstruction.scala 151:{21,21}]
+  wire [3:0] _GEN_5 = 4'h5 == regbase ? 4'h5 : _GEN_4; // @[VDecodeInstruction.scala 151:{21,21}]
+  wire [3:0] _GEN_6 = 4'h6 == regbase ? 4'h6 : _GEN_5; // @[VDecodeInstruction.scala 151:{21,21}]
+  wire [3:0] _GEN_7 = 4'h7 == regbase ? 4'h1 : _GEN_6; // @[VDecodeInstruction.scala 151:{21,21}]
+  wire [3:0] _GEN_8 = 4'h8 == regbase ? 4'h1 : _GEN_7; // @[VDecodeInstruction.scala 151:{21,21}]
+  wire [3:0] _GEN_9 = 4'h9 == regbase ? 4'h3 : _GEN_8; // @[VDecodeInstruction.scala 151:{21,21}]
+  wire [3:0] _GEN_10 = 4'ha == regbase ? 4'h5 : _GEN_9; // @[VDecodeInstruction.scala 151:{21,21}]
+  wire [3:0] _GEN_11 = 4'hb == regbase ? 4'h7 : _GEN_10; // @[VDecodeInstruction.scala 151:{21,21}]
+  wire [3:0] _GEN_12 = 4'hc == regbase ? 4'h2 : _GEN_11; // @[VDecodeInstruction.scala 151:{21,21}]
+  wire [3:0] _GEN_13 = 4'hd == regbase ? 4'h4 : _GEN_12; // @[VDecodeInstruction.scala 151:{21,21}]
+  wire [3:0] _GEN_14 = 4'he == regbase ? 4'h6 : _GEN_13; // @[VDecodeInstruction.scala 151:{21,21}]
+  wire [3:0] _GEN_15 = 4'hf == regbase ? 4'h8 : _GEN_14; // @[VDecodeInstruction.scala 151:{21,21}]
+  wire [5:0] _GEN_67 = {{2'd0}, _GEN_15}; // @[VDecodeInstruction.scala 151:21]
+  wire [5:0] vsdw = vsbits + _GEN_67; // @[VDecodeInstruction.scala 151:21]
+  wire [3:0] _GEN_17 = 4'h1 == regbase ? 4'h2 : 4'h1; // @[VDecodeInstruction.scala 152:{21,21}]
+  wire [3:0] _GEN_18 = 4'h2 == regbase ? 4'h3 : _GEN_17; // @[VDecodeInstruction.scala 152:{21,21}]
+  wire [3:0] _GEN_19 = 4'h3 == regbase ? 4'h4 : _GEN_18; // @[VDecodeInstruction.scala 152:{21,21}]
+  wire [3:0] _GEN_20 = 4'h4 == regbase ? 4'h5 : _GEN_19; // @[VDecodeInstruction.scala 152:{21,21}]
+  wire [3:0] _GEN_21 = 4'h5 == regbase ? 4'h6 : _GEN_20; // @[VDecodeInstruction.scala 152:{21,21}]
+  wire [3:0] _GEN_22 = 4'h6 == regbase ? 4'h7 : _GEN_21; // @[VDecodeInstruction.scala 152:{21,21}]
+  wire [3:0] _GEN_23 = 4'h7 == regbase ? 4'h0 : _GEN_22; // @[VDecodeInstruction.scala 152:{21,21}]
+  wire [3:0] _GEN_24 = 4'h8 == regbase ? 4'h2 : _GEN_23; // @[VDecodeInstruction.scala 152:{21,21}]
+  wire [3:0] _GEN_25 = 4'h9 == regbase ? 4'h4 : _GEN_24; // @[VDecodeInstruction.scala 152:{21,21}]
+  wire [3:0] _GEN_26 = 4'ha == regbase ? 4'h6 : _GEN_25; // @[VDecodeInstruction.scala 152:{21,21}]
+  wire [3:0] _GEN_27 = 4'hb == regbase ? 4'h8 : _GEN_26; // @[VDecodeInstruction.scala 152:{21,21}]
+  wire [3:0] _GEN_28 = 4'hc == regbase ? 4'h0 : _GEN_27; // @[VDecodeInstruction.scala 152:{21,21}]
+  wire [3:0] _GEN_29 = 4'hd == regbase ? 4'h0 : _GEN_28; // @[VDecodeInstruction.scala 152:{21,21}]
+  wire [3:0] _GEN_30 = 4'he == regbase ? 4'h0 : _GEN_29; // @[VDecodeInstruction.scala 152:{21,21}]
+  wire [3:0] _GEN_31 = 4'hf == regbase ? 4'h0 : _GEN_30; // @[VDecodeInstruction.scala 152:{21,21}]
+  wire [5:0] _GEN_68 = {{2'd0}, _GEN_31}; // @[VDecodeInstruction.scala 152:21]
+  wire [5:0] vtdw = vsbits + _GEN_68; // @[VDecodeInstruction.scala 152:21]
+  wire [3:0] _GEN_33 = 4'h1 == regbase ? 4'h3 : 4'h2; // @[VDecodeInstruction.scala 153:{21,21}]
+  wire [3:0] _GEN_34 = 4'h2 == regbase ? 4'h4 : _GEN_33; // @[VDecodeInstruction.scala 153:{21,21}]
+  wire [3:0] _GEN_35 = 4'h3 == regbase ? 4'h5 : _GEN_34; // @[VDecodeInstruction.scala 153:{21,21}]
+  wire [3:0] _GEN_36 = 4'h4 == regbase ? 4'h6 : _GEN_35; // @[VDecodeInstruction.scala 153:{21,21}]
+  wire [3:0] _GEN_37 = 4'h5 == regbase ? 4'h7 : _GEN_36; // @[VDecodeInstruction.scala 153:{21,21}]
+  wire [3:0] _GEN_38 = 4'h6 == regbase ? 4'h8 : _GEN_37; // @[VDecodeInstruction.scala 153:{21,21}]
+  wire [3:0] _GEN_39 = 4'h7 == regbase ? 4'h2 : _GEN_38; // @[VDecodeInstruction.scala 153:{21,21}]
+  wire [3:0] _GEN_40 = 4'h8 == regbase ? 4'h0 : _GEN_39; // @[VDecodeInstruction.scala 153:{21,21}]
+  wire [3:0] _GEN_41 = 4'h9 == regbase ? 4'h0 : _GEN_40; // @[VDecodeInstruction.scala 153:{21,21}]
+  wire [3:0] _GEN_42 = 4'ha == regbase ? 4'h0 : _GEN_41; // @[VDecodeInstruction.scala 153:{21,21}]
+  wire [3:0] _GEN_43 = 4'hb == regbase ? 4'h0 : _GEN_42; // @[VDecodeInstruction.scala 153:{21,21}]
+  wire [3:0] _GEN_44 = 4'hc == regbase ? 4'h1 : _GEN_43; // @[VDecodeInstruction.scala 153:{21,21}]
+  wire [3:0] _GEN_45 = 4'hd == regbase ? 4'h1 : _GEN_44; // @[VDecodeInstruction.scala 153:{21,21}]
+  wire [3:0] _GEN_46 = 4'he == regbase ? 4'h1 : _GEN_45; // @[VDecodeInstruction.scala 153:{21,21}]
+  wire [3:0] _GEN_47 = 4'hf == regbase ? 4'h1 : _GEN_46; // @[VDecodeInstruction.scala 153:{21,21}]
+  wire [5:0] _GEN_69 = {{2'd0}, _GEN_47}; // @[VDecodeInstruction.scala 153:21]
+  wire [5:0] vudw = vsbits + _GEN_69; // @[VDecodeInstruction.scala 153:21]
+  wire [2:0] _vy_T = m ? 3'h4 : 3'h1; // @[VDecodeInstruction.scala 159:26]
+  wire [5:0] _GEN_70 = {{3'd0}, _vy_T}; // @[VDecodeInstruction.scala 159:21]
+  wire [5:0] vydw = func2 + _GEN_70; // @[VDecodeInstruction.scala 159:21]
+  wire [3:0] _vz_T = m ? 4'h8 : 4'h2; // @[VDecodeInstruction.scala 160:26]
+  wire [5:0] _GEN_71 = {{2'd0}, _vz_T}; // @[VDecodeInstruction.scala 160:21]
+  wire [5:0] vzdw = func2 + _GEN_71; // @[VDecodeInstruction.scala 160:21]
   wire [63:0] ra_vs = 64'h1 << vsdw; // @[OneHot.scala 64:12]
   wire [63:0] ra_vt = 64'h1 << vtdw; // @[OneHot.scala 64:12]
   wire [63:0] ra_vu = 64'h1 << vudw; // @[OneHot.scala 64:12]
   wire [63:0] ra_vx = 64'h1 << func2; // @[OneHot.scala 64:12]
   wire [63:0] ra_vy = 64'h1 << vydw; // @[OneHot.scala 64:12]
   wire [63:0] ra_vz = 64'h1 << vzdw; // @[OneHot.scala 64:12]
-  wire [3:0] ra_vxm_shiftAmount = func2[5:2]; // @[VDecodeInstruction.scala 176:40]
+  wire [3:0] ra_vxm_shiftAmount = func2[5:2]; // @[VDecodeInstruction.scala 171:40]
   wire [15:0] _ra_vxm_T_1 = 16'h1 << ra_vxm_shiftAmount; // @[OneHot.scala 64:12]
-  wire  ra_vxm_v = _ra_vxm_T_1[0]; // @[VDecodeInstruction.scala 57:16]
-  wire  ra_vxm_v_1 = _ra_vxm_T_1[1]; // @[VDecodeInstruction.scala 57:16]
-  wire  ra_vxm_v_2 = _ra_vxm_T_1[2]; // @[VDecodeInstruction.scala 57:16]
-  wire  ra_vxm_v_3 = _ra_vxm_T_1[3]; // @[VDecodeInstruction.scala 57:16]
-  wire  ra_vxm_v_4 = _ra_vxm_T_1[4]; // @[VDecodeInstruction.scala 57:16]
-  wire  ra_vxm_v_5 = _ra_vxm_T_1[5]; // @[VDecodeInstruction.scala 57:16]
-  wire  ra_vxm_v_6 = _ra_vxm_T_1[6]; // @[VDecodeInstruction.scala 57:16]
-  wire  ra_vxm_v_7 = _ra_vxm_T_1[7]; // @[VDecodeInstruction.scala 57:16]
-  wire  ra_vxm_v_8 = _ra_vxm_T_1[8]; // @[VDecodeInstruction.scala 57:16]
-  wire  ra_vxm_v_9 = _ra_vxm_T_1[9]; // @[VDecodeInstruction.scala 57:16]
-  wire  ra_vxm_v_10 = _ra_vxm_T_1[10]; // @[VDecodeInstruction.scala 57:16]
-  wire  ra_vxm_v_11 = _ra_vxm_T_1[11]; // @[VDecodeInstruction.scala 57:16]
-  wire  ra_vxm_v_12 = _ra_vxm_T_1[12]; // @[VDecodeInstruction.scala 57:16]
-  wire  ra_vxm_v_13 = _ra_vxm_T_1[13]; // @[VDecodeInstruction.scala 57:16]
-  wire  ra_vxm_v_14 = _ra_vxm_T_1[14]; // @[VDecodeInstruction.scala 57:16]
-  wire  ra_vxm_v_15 = _ra_vxm_T_1[15]; // @[VDecodeInstruction.scala 57:16]
-  wire [7:0] ra_vxm_b_lo_lo_lo = {ra_vxm_v_1,ra_vxm_v_1,ra_vxm_v_1,ra_vxm_v_1,ra_vxm_v,ra_vxm_v,ra_vxm_v,ra_vxm_v}; // @[VDecodeInstruction.scala 60:19]
+  wire  ra_vxm_v = _ra_vxm_T_1[0]; // @[VDecodeInstruction.scala 52:16]
+  wire  ra_vxm_v_1 = _ra_vxm_T_1[1]; // @[VDecodeInstruction.scala 52:16]
+  wire  ra_vxm_v_2 = _ra_vxm_T_1[2]; // @[VDecodeInstruction.scala 52:16]
+  wire  ra_vxm_v_3 = _ra_vxm_T_1[3]; // @[VDecodeInstruction.scala 52:16]
+  wire  ra_vxm_v_4 = _ra_vxm_T_1[4]; // @[VDecodeInstruction.scala 52:16]
+  wire  ra_vxm_v_5 = _ra_vxm_T_1[5]; // @[VDecodeInstruction.scala 52:16]
+  wire  ra_vxm_v_6 = _ra_vxm_T_1[6]; // @[VDecodeInstruction.scala 52:16]
+  wire  ra_vxm_v_7 = _ra_vxm_T_1[7]; // @[VDecodeInstruction.scala 52:16]
+  wire  ra_vxm_v_8 = _ra_vxm_T_1[8]; // @[VDecodeInstruction.scala 52:16]
+  wire  ra_vxm_v_9 = _ra_vxm_T_1[9]; // @[VDecodeInstruction.scala 52:16]
+  wire  ra_vxm_v_10 = _ra_vxm_T_1[10]; // @[VDecodeInstruction.scala 52:16]
+  wire  ra_vxm_v_11 = _ra_vxm_T_1[11]; // @[VDecodeInstruction.scala 52:16]
+  wire  ra_vxm_v_12 = _ra_vxm_T_1[12]; // @[VDecodeInstruction.scala 52:16]
+  wire  ra_vxm_v_13 = _ra_vxm_T_1[13]; // @[VDecodeInstruction.scala 52:16]
+  wire  ra_vxm_v_14 = _ra_vxm_T_1[14]; // @[VDecodeInstruction.scala 52:16]
+  wire  ra_vxm_v_15 = _ra_vxm_T_1[15]; // @[VDecodeInstruction.scala 52:16]
+  wire [7:0] ra_vxm_b_lo_lo_lo = {ra_vxm_v_1,ra_vxm_v_1,ra_vxm_v_1,ra_vxm_v_1,ra_vxm_v,ra_vxm_v,ra_vxm_v,ra_vxm_v}; // @[VDecodeInstruction.scala 55:19]
   wire [15:0] ra_vxm_b_lo_lo = {ra_vxm_v_3,ra_vxm_v_3,ra_vxm_v_3,ra_vxm_v_3,ra_vxm_v_2,ra_vxm_v_2,ra_vxm_v_2,ra_vxm_v_2,
-    ra_vxm_b_lo_lo_lo}; // @[VDecodeInstruction.scala 60:19]
+    ra_vxm_b_lo_lo_lo}; // @[VDecodeInstruction.scala 55:19]
   wire [7:0] ra_vxm_b_lo_hi_lo = {ra_vxm_v_5,ra_vxm_v_5,ra_vxm_v_5,ra_vxm_v_5,ra_vxm_v_4,ra_vxm_v_4,ra_vxm_v_4,
-    ra_vxm_v_4}; // @[VDecodeInstruction.scala 60:19]
+    ra_vxm_v_4}; // @[VDecodeInstruction.scala 55:19]
   wire [31:0] ra_vxm_b_lo = {ra_vxm_v_7,ra_vxm_v_7,ra_vxm_v_7,ra_vxm_v_7,ra_vxm_v_6,ra_vxm_v_6,ra_vxm_v_6,ra_vxm_v_6,
-    ra_vxm_b_lo_hi_lo,ra_vxm_b_lo_lo}; // @[VDecodeInstruction.scala 60:19]
+    ra_vxm_b_lo_hi_lo,ra_vxm_b_lo_lo}; // @[VDecodeInstruction.scala 55:19]
   wire [7:0] ra_vxm_b_hi_lo_lo = {ra_vxm_v_9,ra_vxm_v_9,ra_vxm_v_9,ra_vxm_v_9,ra_vxm_v_8,ra_vxm_v_8,ra_vxm_v_8,
-    ra_vxm_v_8}; // @[VDecodeInstruction.scala 60:19]
+    ra_vxm_v_8}; // @[VDecodeInstruction.scala 55:19]
   wire [15:0] ra_vxm_b_hi_lo = {ra_vxm_v_11,ra_vxm_v_11,ra_vxm_v_11,ra_vxm_v_11,ra_vxm_v_10,ra_vxm_v_10,ra_vxm_v_10,
-    ra_vxm_v_10,ra_vxm_b_hi_lo_lo}; // @[VDecodeInstruction.scala 60:19]
+    ra_vxm_v_10,ra_vxm_b_hi_lo_lo}; // @[VDecodeInstruction.scala 55:19]
   wire [7:0] ra_vxm_b_hi_hi_lo = {ra_vxm_v_13,ra_vxm_v_13,ra_vxm_v_13,ra_vxm_v_13,ra_vxm_v_12,ra_vxm_v_12,ra_vxm_v_12,
-    ra_vxm_v_12}; // @[VDecodeInstruction.scala 60:19]
+    ra_vxm_v_12}; // @[VDecodeInstruction.scala 55:19]
   wire [31:0] ra_vxm_b_hi = {ra_vxm_v_15,ra_vxm_v_15,ra_vxm_v_15,ra_vxm_v_15,ra_vxm_v_14,ra_vxm_v_14,ra_vxm_v_14,
-    ra_vxm_v_14,ra_vxm_b_hi_hi_lo,ra_vxm_b_hi_lo}; // @[VDecodeInstruction.scala 60:19]
-  wire [63:0] ra_vxm_b = {ra_vxm_b_hi,ra_vxm_b_lo}; // @[VDecodeInstruction.scala 60:19]
+    ra_vxm_v_14,ra_vxm_b_hi_hi_lo,ra_vxm_b_hi_lo}; // @[VDecodeInstruction.scala 55:19]
+  wire [63:0] ra_vxm_b = {ra_vxm_b_hi,ra_vxm_b_lo}; // @[VDecodeInstruction.scala 55:19]
   wire [63:0] ra_vxm = m ? ra_vxm_b : 64'h0; // @[Library.scala 18:8]
-  wire [3:0] ra_vym_shiftAmount = vydw[5:2]; // @[VDecodeInstruction.scala 177:40]
+  wire [3:0] ra_vym_shiftAmount = vydw[5:2]; // @[VDecodeInstruction.scala 172:40]
   wire [15:0] _ra_vym_T_1 = 16'h1 << ra_vym_shiftAmount; // @[OneHot.scala 64:12]
-  wire  ra_vym_v = _ra_vym_T_1[0]; // @[VDecodeInstruction.scala 57:16]
-  wire  ra_vym_v_1 = _ra_vym_T_1[1]; // @[VDecodeInstruction.scala 57:16]
-  wire  ra_vym_v_2 = _ra_vym_T_1[2]; // @[VDecodeInstruction.scala 57:16]
-  wire  ra_vym_v_3 = _ra_vym_T_1[3]; // @[VDecodeInstruction.scala 57:16]
-  wire  ra_vym_v_4 = _ra_vym_T_1[4]; // @[VDecodeInstruction.scala 57:16]
-  wire  ra_vym_v_5 = _ra_vym_T_1[5]; // @[VDecodeInstruction.scala 57:16]
-  wire  ra_vym_v_6 = _ra_vym_T_1[6]; // @[VDecodeInstruction.scala 57:16]
-  wire  ra_vym_v_7 = _ra_vym_T_1[7]; // @[VDecodeInstruction.scala 57:16]
-  wire  ra_vym_v_8 = _ra_vym_T_1[8]; // @[VDecodeInstruction.scala 57:16]
-  wire  ra_vym_v_9 = _ra_vym_T_1[9]; // @[VDecodeInstruction.scala 57:16]
-  wire  ra_vym_v_10 = _ra_vym_T_1[10]; // @[VDecodeInstruction.scala 57:16]
-  wire  ra_vym_v_11 = _ra_vym_T_1[11]; // @[VDecodeInstruction.scala 57:16]
-  wire  ra_vym_v_12 = _ra_vym_T_1[12]; // @[VDecodeInstruction.scala 57:16]
-  wire  ra_vym_v_13 = _ra_vym_T_1[13]; // @[VDecodeInstruction.scala 57:16]
-  wire  ra_vym_v_14 = _ra_vym_T_1[14]; // @[VDecodeInstruction.scala 57:16]
-  wire  ra_vym_v_15 = _ra_vym_T_1[15]; // @[VDecodeInstruction.scala 57:16]
-  wire [7:0] ra_vym_b_lo_lo_lo = {ra_vym_v_1,ra_vym_v_1,ra_vym_v_1,ra_vym_v_1,ra_vym_v,ra_vym_v,ra_vym_v,ra_vym_v}; // @[VDecodeInstruction.scala 60:19]
+  wire  ra_vym_v = _ra_vym_T_1[0]; // @[VDecodeInstruction.scala 52:16]
+  wire  ra_vym_v_1 = _ra_vym_T_1[1]; // @[VDecodeInstruction.scala 52:16]
+  wire  ra_vym_v_2 = _ra_vym_T_1[2]; // @[VDecodeInstruction.scala 52:16]
+  wire  ra_vym_v_3 = _ra_vym_T_1[3]; // @[VDecodeInstruction.scala 52:16]
+  wire  ra_vym_v_4 = _ra_vym_T_1[4]; // @[VDecodeInstruction.scala 52:16]
+  wire  ra_vym_v_5 = _ra_vym_T_1[5]; // @[VDecodeInstruction.scala 52:16]
+  wire  ra_vym_v_6 = _ra_vym_T_1[6]; // @[VDecodeInstruction.scala 52:16]
+  wire  ra_vym_v_7 = _ra_vym_T_1[7]; // @[VDecodeInstruction.scala 52:16]
+  wire  ra_vym_v_8 = _ra_vym_T_1[8]; // @[VDecodeInstruction.scala 52:16]
+  wire  ra_vym_v_9 = _ra_vym_T_1[9]; // @[VDecodeInstruction.scala 52:16]
+  wire  ra_vym_v_10 = _ra_vym_T_1[10]; // @[VDecodeInstruction.scala 52:16]
+  wire  ra_vym_v_11 = _ra_vym_T_1[11]; // @[VDecodeInstruction.scala 52:16]
+  wire  ra_vym_v_12 = _ra_vym_T_1[12]; // @[VDecodeInstruction.scala 52:16]
+  wire  ra_vym_v_13 = _ra_vym_T_1[13]; // @[VDecodeInstruction.scala 52:16]
+  wire  ra_vym_v_14 = _ra_vym_T_1[14]; // @[VDecodeInstruction.scala 52:16]
+  wire  ra_vym_v_15 = _ra_vym_T_1[15]; // @[VDecodeInstruction.scala 52:16]
+  wire [7:0] ra_vym_b_lo_lo_lo = {ra_vym_v_1,ra_vym_v_1,ra_vym_v_1,ra_vym_v_1,ra_vym_v,ra_vym_v,ra_vym_v,ra_vym_v}; // @[VDecodeInstruction.scala 55:19]
   wire [15:0] ra_vym_b_lo_lo = {ra_vym_v_3,ra_vym_v_3,ra_vym_v_3,ra_vym_v_3,ra_vym_v_2,ra_vym_v_2,ra_vym_v_2,ra_vym_v_2,
-    ra_vym_b_lo_lo_lo}; // @[VDecodeInstruction.scala 60:19]
+    ra_vym_b_lo_lo_lo}; // @[VDecodeInstruction.scala 55:19]
   wire [7:0] ra_vym_b_lo_hi_lo = {ra_vym_v_5,ra_vym_v_5,ra_vym_v_5,ra_vym_v_5,ra_vym_v_4,ra_vym_v_4,ra_vym_v_4,
-    ra_vym_v_4}; // @[VDecodeInstruction.scala 60:19]
+    ra_vym_v_4}; // @[VDecodeInstruction.scala 55:19]
   wire [31:0] ra_vym_b_lo = {ra_vym_v_7,ra_vym_v_7,ra_vym_v_7,ra_vym_v_7,ra_vym_v_6,ra_vym_v_6,ra_vym_v_6,ra_vym_v_6,
-    ra_vym_b_lo_hi_lo,ra_vym_b_lo_lo}; // @[VDecodeInstruction.scala 60:19]
+    ra_vym_b_lo_hi_lo,ra_vym_b_lo_lo}; // @[VDecodeInstruction.scala 55:19]
   wire [7:0] ra_vym_b_hi_lo_lo = {ra_vym_v_9,ra_vym_v_9,ra_vym_v_9,ra_vym_v_9,ra_vym_v_8,ra_vym_v_8,ra_vym_v_8,
-    ra_vym_v_8}; // @[VDecodeInstruction.scala 60:19]
+    ra_vym_v_8}; // @[VDecodeInstruction.scala 55:19]
   wire [15:0] ra_vym_b_hi_lo = {ra_vym_v_11,ra_vym_v_11,ra_vym_v_11,ra_vym_v_11,ra_vym_v_10,ra_vym_v_10,ra_vym_v_10,
-    ra_vym_v_10,ra_vym_b_hi_lo_lo}; // @[VDecodeInstruction.scala 60:19]
+    ra_vym_v_10,ra_vym_b_hi_lo_lo}; // @[VDecodeInstruction.scala 55:19]
   wire [7:0] ra_vym_b_hi_hi_lo = {ra_vym_v_13,ra_vym_v_13,ra_vym_v_13,ra_vym_v_13,ra_vym_v_12,ra_vym_v_12,ra_vym_v_12,
-    ra_vym_v_12}; // @[VDecodeInstruction.scala 60:19]
+    ra_vym_v_12}; // @[VDecodeInstruction.scala 55:19]
   wire [31:0] ra_vym_b_hi = {ra_vym_v_15,ra_vym_v_15,ra_vym_v_15,ra_vym_v_15,ra_vym_v_14,ra_vym_v_14,ra_vym_v_14,
-    ra_vym_v_14,ra_vym_b_hi_hi_lo,ra_vym_b_hi_lo}; // @[VDecodeInstruction.scala 60:19]
-  wire [63:0] ra_vym_b = {ra_vym_b_hi,ra_vym_b_lo}; // @[VDecodeInstruction.scala 60:19]
+    ra_vym_v_14,ra_vym_b_hi_hi_lo,ra_vym_b_hi_lo}; // @[VDecodeInstruction.scala 55:19]
+  wire [63:0] ra_vym_b = {ra_vym_b_hi,ra_vym_b_lo}; // @[VDecodeInstruction.scala 55:19]
   wire [63:0] ra_vym = m ? ra_vym_b : 64'h0; // @[Library.scala 18:8]
-  wire [3:0] ra_vzm_shiftAmount = vzdw[5:2]; // @[VDecodeInstruction.scala 178:40]
+  wire [3:0] ra_vzm_shiftAmount = vzdw[5:2]; // @[VDecodeInstruction.scala 173:40]
   wire [15:0] _ra_vzm_T_1 = 16'h1 << ra_vzm_shiftAmount; // @[OneHot.scala 64:12]
-  wire  ra_vzm_v = _ra_vzm_T_1[0]; // @[VDecodeInstruction.scala 57:16]
-  wire  ra_vzm_v_1 = _ra_vzm_T_1[1]; // @[VDecodeInstruction.scala 57:16]
-  wire  ra_vzm_v_2 = _ra_vzm_T_1[2]; // @[VDecodeInstruction.scala 57:16]
-  wire  ra_vzm_v_3 = _ra_vzm_T_1[3]; // @[VDecodeInstruction.scala 57:16]
-  wire  ra_vzm_v_4 = _ra_vzm_T_1[4]; // @[VDecodeInstruction.scala 57:16]
-  wire  ra_vzm_v_5 = _ra_vzm_T_1[5]; // @[VDecodeInstruction.scala 57:16]
-  wire  ra_vzm_v_6 = _ra_vzm_T_1[6]; // @[VDecodeInstruction.scala 57:16]
-  wire  ra_vzm_v_7 = _ra_vzm_T_1[7]; // @[VDecodeInstruction.scala 57:16]
-  wire  ra_vzm_v_8 = _ra_vzm_T_1[8]; // @[VDecodeInstruction.scala 57:16]
-  wire  ra_vzm_v_9 = _ra_vzm_T_1[9]; // @[VDecodeInstruction.scala 57:16]
-  wire  ra_vzm_v_10 = _ra_vzm_T_1[10]; // @[VDecodeInstruction.scala 57:16]
-  wire  ra_vzm_v_11 = _ra_vzm_T_1[11]; // @[VDecodeInstruction.scala 57:16]
-  wire  ra_vzm_v_12 = _ra_vzm_T_1[12]; // @[VDecodeInstruction.scala 57:16]
-  wire  ra_vzm_v_13 = _ra_vzm_T_1[13]; // @[VDecodeInstruction.scala 57:16]
-  wire  ra_vzm_v_14 = _ra_vzm_T_1[14]; // @[VDecodeInstruction.scala 57:16]
-  wire  ra_vzm_v_15 = _ra_vzm_T_1[15]; // @[VDecodeInstruction.scala 57:16]
-  wire [7:0] ra_vzm_b_lo_lo_lo = {ra_vzm_v_1,ra_vzm_v_1,ra_vzm_v_1,ra_vzm_v_1,ra_vzm_v,ra_vzm_v,ra_vzm_v,ra_vzm_v}; // @[VDecodeInstruction.scala 60:19]
+  wire  ra_vzm_v = _ra_vzm_T_1[0]; // @[VDecodeInstruction.scala 52:16]
+  wire  ra_vzm_v_1 = _ra_vzm_T_1[1]; // @[VDecodeInstruction.scala 52:16]
+  wire  ra_vzm_v_2 = _ra_vzm_T_1[2]; // @[VDecodeInstruction.scala 52:16]
+  wire  ra_vzm_v_3 = _ra_vzm_T_1[3]; // @[VDecodeInstruction.scala 52:16]
+  wire  ra_vzm_v_4 = _ra_vzm_T_1[4]; // @[VDecodeInstruction.scala 52:16]
+  wire  ra_vzm_v_5 = _ra_vzm_T_1[5]; // @[VDecodeInstruction.scala 52:16]
+  wire  ra_vzm_v_6 = _ra_vzm_T_1[6]; // @[VDecodeInstruction.scala 52:16]
+  wire  ra_vzm_v_7 = _ra_vzm_T_1[7]; // @[VDecodeInstruction.scala 52:16]
+  wire  ra_vzm_v_8 = _ra_vzm_T_1[8]; // @[VDecodeInstruction.scala 52:16]
+  wire  ra_vzm_v_9 = _ra_vzm_T_1[9]; // @[VDecodeInstruction.scala 52:16]
+  wire  ra_vzm_v_10 = _ra_vzm_T_1[10]; // @[VDecodeInstruction.scala 52:16]
+  wire  ra_vzm_v_11 = _ra_vzm_T_1[11]; // @[VDecodeInstruction.scala 52:16]
+  wire  ra_vzm_v_12 = _ra_vzm_T_1[12]; // @[VDecodeInstruction.scala 52:16]
+  wire  ra_vzm_v_13 = _ra_vzm_T_1[13]; // @[VDecodeInstruction.scala 52:16]
+  wire  ra_vzm_v_14 = _ra_vzm_T_1[14]; // @[VDecodeInstruction.scala 52:16]
+  wire  ra_vzm_v_15 = _ra_vzm_T_1[15]; // @[VDecodeInstruction.scala 52:16]
+  wire [7:0] ra_vzm_b_lo_lo_lo = {ra_vzm_v_1,ra_vzm_v_1,ra_vzm_v_1,ra_vzm_v_1,ra_vzm_v,ra_vzm_v,ra_vzm_v,ra_vzm_v}; // @[VDecodeInstruction.scala 55:19]
   wire [15:0] ra_vzm_b_lo_lo = {ra_vzm_v_3,ra_vzm_v_3,ra_vzm_v_3,ra_vzm_v_3,ra_vzm_v_2,ra_vzm_v_2,ra_vzm_v_2,ra_vzm_v_2,
-    ra_vzm_b_lo_lo_lo}; // @[VDecodeInstruction.scala 60:19]
+    ra_vzm_b_lo_lo_lo}; // @[VDecodeInstruction.scala 55:19]
   wire [7:0] ra_vzm_b_lo_hi_lo = {ra_vzm_v_5,ra_vzm_v_5,ra_vzm_v_5,ra_vzm_v_5,ra_vzm_v_4,ra_vzm_v_4,ra_vzm_v_4,
-    ra_vzm_v_4}; // @[VDecodeInstruction.scala 60:19]
+    ra_vzm_v_4}; // @[VDecodeInstruction.scala 55:19]
   wire [31:0] ra_vzm_b_lo = {ra_vzm_v_7,ra_vzm_v_7,ra_vzm_v_7,ra_vzm_v_7,ra_vzm_v_6,ra_vzm_v_6,ra_vzm_v_6,ra_vzm_v_6,
-    ra_vzm_b_lo_hi_lo,ra_vzm_b_lo_lo}; // @[VDecodeInstruction.scala 60:19]
+    ra_vzm_b_lo_hi_lo,ra_vzm_b_lo_lo}; // @[VDecodeInstruction.scala 55:19]
   wire [7:0] ra_vzm_b_hi_lo_lo = {ra_vzm_v_9,ra_vzm_v_9,ra_vzm_v_9,ra_vzm_v_9,ra_vzm_v_8,ra_vzm_v_8,ra_vzm_v_8,
-    ra_vzm_v_8}; // @[VDecodeInstruction.scala 60:19]
+    ra_vzm_v_8}; // @[VDecodeInstruction.scala 55:19]
   wire [15:0] ra_vzm_b_hi_lo = {ra_vzm_v_11,ra_vzm_v_11,ra_vzm_v_11,ra_vzm_v_11,ra_vzm_v_10,ra_vzm_v_10,ra_vzm_v_10,
-    ra_vzm_v_10,ra_vzm_b_hi_lo_lo}; // @[VDecodeInstruction.scala 60:19]
+    ra_vzm_v_10,ra_vzm_b_hi_lo_lo}; // @[VDecodeInstruction.scala 55:19]
   wire [7:0] ra_vzm_b_hi_hi_lo = {ra_vzm_v_13,ra_vzm_v_13,ra_vzm_v_13,ra_vzm_v_13,ra_vzm_v_12,ra_vzm_v_12,ra_vzm_v_12,
-    ra_vzm_v_12}; // @[VDecodeInstruction.scala 60:19]
+    ra_vzm_v_12}; // @[VDecodeInstruction.scala 55:19]
   wire [31:0] ra_vzm_b_hi = {ra_vzm_v_15,ra_vzm_v_15,ra_vzm_v_15,ra_vzm_v_15,ra_vzm_v_14,ra_vzm_v_14,ra_vzm_v_14,
-    ra_vzm_v_14,ra_vzm_b_hi_hi_lo,ra_vzm_b_hi_lo}; // @[VDecodeInstruction.scala 60:19]
-  wire [63:0] ra_vzm_b = {ra_vzm_b_hi,ra_vzm_b_lo}; // @[VDecodeInstruction.scala 60:19]
+    ra_vzm_v_14,ra_vzm_b_hi_hi_lo,ra_vzm_b_hi_lo}; // @[VDecodeInstruction.scala 55:19]
+  wire [63:0] ra_vzm_b = {ra_vzm_b_hi,ra_vzm_b_lo}; // @[VDecodeInstruction.scala 55:19]
   wire [63:0] ra_vzm = m ? ra_vzm_b : 64'h0; // @[Library.scala 18:8]
-  wire [63:0] _ractive_T = ra_vs | ra_vt; // @[VDecodeInstruction.scala 189:25]
-  wire [63:0] _ractive_T_1 = _ractive_T | ra_vu; // @[VDecodeInstruction.scala 189:33]
-  wire [63:0] _ractive_T_2 = _ractive_T_1 | ra_vx; // @[VDecodeInstruction.scala 189:41]
-  wire [63:0] _ractive_T_3 = _ractive_T_2 | ra_vy; // @[VDecodeInstruction.scala 189:49]
-  wire [63:0] _ractive_T_4 = _ractive_T_3 | ra_vz; // @[VDecodeInstruction.scala 189:57]
-  wire [63:0] _ractive_T_5 = _ractive_T_4 | ra_vxm; // @[VDecodeInstruction.scala 189:65]
-  wire [63:0] _ractive_T_6 = _ractive_T_5 | ra_vym; // @[VDecodeInstruction.scala 189:74]
-  wire [63:0] ractivedw = _ractive_T_6 | ra_vzm; // @[VDecodeInstruction.scala 189:83]
-  wire [3:0] ractivedi_shiftAmount = vsbits[5:2]; // @[VDecodeInstruction.scala 550:36]
+  wire [63:0] _ractive_T = ra_vs | ra_vt; // @[VDecodeInstruction.scala 184:25]
+  wire [63:0] _ractive_T_1 = _ractive_T | ra_vu; // @[VDecodeInstruction.scala 184:33]
+  wire [63:0] _ractive_T_2 = _ractive_T_1 | ra_vx; // @[VDecodeInstruction.scala 184:41]
+  wire [63:0] _ractive_T_3 = _ractive_T_2 | ra_vy; // @[VDecodeInstruction.scala 184:49]
+  wire [63:0] _ractive_T_4 = _ractive_T_3 | ra_vz; // @[VDecodeInstruction.scala 184:57]
+  wire [63:0] _ractive_T_5 = _ractive_T_4 | ra_vxm; // @[VDecodeInstruction.scala 184:65]
+  wire [63:0] _ractive_T_6 = _ractive_T_5 | ra_vym; // @[VDecodeInstruction.scala 184:74]
+  wire [63:0] ractivedw = _ractive_T_6 | ra_vzm; // @[VDecodeInstruction.scala 184:83]
+  wire [3:0] ractivedi_shiftAmount = vsbits[5:2]; // @[VDecodeInstruction.scala 479:36]
   wire [15:0] _ractivedi_T_1 = 16'h1 << ractivedi_shiftAmount; // @[OneHot.scala 64:12]
-  wire  ractivedi_v = _ractivedi_T_1[0]; // @[VDecodeInstruction.scala 57:16]
-  wire  ractivedi_v_1 = _ractivedi_T_1[1]; // @[VDecodeInstruction.scala 57:16]
-  wire  ractivedi_v_2 = _ractivedi_T_1[2]; // @[VDecodeInstruction.scala 57:16]
-  wire  ractivedi_v_3 = _ractivedi_T_1[3]; // @[VDecodeInstruction.scala 57:16]
-  wire  ractivedi_v_4 = _ractivedi_T_1[4]; // @[VDecodeInstruction.scala 57:16]
-  wire  ractivedi_v_5 = _ractivedi_T_1[5]; // @[VDecodeInstruction.scala 57:16]
-  wire  ractivedi_v_6 = _ractivedi_T_1[6]; // @[VDecodeInstruction.scala 57:16]
-  wire  ractivedi_v_7 = _ractivedi_T_1[7]; // @[VDecodeInstruction.scala 57:16]
-  wire  ractivedi_v_8 = _ractivedi_T_1[8]; // @[VDecodeInstruction.scala 57:16]
-  wire  ractivedi_v_9 = _ractivedi_T_1[9]; // @[VDecodeInstruction.scala 57:16]
-  wire  ractivedi_v_10 = _ractivedi_T_1[10]; // @[VDecodeInstruction.scala 57:16]
-  wire  ractivedi_v_11 = _ractivedi_T_1[11]; // @[VDecodeInstruction.scala 57:16]
-  wire  ractivedi_v_12 = _ractivedi_T_1[12]; // @[VDecodeInstruction.scala 57:16]
-  wire  ractivedi_v_13 = _ractivedi_T_1[13]; // @[VDecodeInstruction.scala 57:16]
-  wire  ractivedi_v_14 = _ractivedi_T_1[14]; // @[VDecodeInstruction.scala 57:16]
-  wire  ractivedi_v_15 = _ractivedi_T_1[15]; // @[VDecodeInstruction.scala 57:16]
+  wire  ractivedi_v = _ractivedi_T_1[0]; // @[VDecodeInstruction.scala 52:16]
+  wire  ractivedi_v_1 = _ractivedi_T_1[1]; // @[VDecodeInstruction.scala 52:16]
+  wire  ractivedi_v_2 = _ractivedi_T_1[2]; // @[VDecodeInstruction.scala 52:16]
+  wire  ractivedi_v_3 = _ractivedi_T_1[3]; // @[VDecodeInstruction.scala 52:16]
+  wire  ractivedi_v_4 = _ractivedi_T_1[4]; // @[VDecodeInstruction.scala 52:16]
+  wire  ractivedi_v_5 = _ractivedi_T_1[5]; // @[VDecodeInstruction.scala 52:16]
+  wire  ractivedi_v_6 = _ractivedi_T_1[6]; // @[VDecodeInstruction.scala 52:16]
+  wire  ractivedi_v_7 = _ractivedi_T_1[7]; // @[VDecodeInstruction.scala 52:16]
+  wire  ractivedi_v_8 = _ractivedi_T_1[8]; // @[VDecodeInstruction.scala 52:16]
+  wire  ractivedi_v_9 = _ractivedi_T_1[9]; // @[VDecodeInstruction.scala 52:16]
+  wire  ractivedi_v_10 = _ractivedi_T_1[10]; // @[VDecodeInstruction.scala 52:16]
+  wire  ractivedi_v_11 = _ractivedi_T_1[11]; // @[VDecodeInstruction.scala 52:16]
+  wire  ractivedi_v_12 = _ractivedi_T_1[12]; // @[VDecodeInstruction.scala 52:16]
+  wire  ractivedi_v_13 = _ractivedi_T_1[13]; // @[VDecodeInstruction.scala 52:16]
+  wire  ractivedi_v_14 = _ractivedi_T_1[14]; // @[VDecodeInstruction.scala 52:16]
+  wire  ractivedi_v_15 = _ractivedi_T_1[15]; // @[VDecodeInstruction.scala 52:16]
   wire [7:0] ractivedi_b_lo_lo_lo = {ractivedi_v_1,ractivedi_v_1,ractivedi_v_1,ractivedi_v_1,ractivedi_v,ractivedi_v,
-    ractivedi_v,ractivedi_v}; // @[VDecodeInstruction.scala 60:19]
+    ractivedi_v,ractivedi_v}; // @[VDecodeInstruction.scala 55:19]
   wire [15:0] ractivedi_b_lo_lo = {ractivedi_v_3,ractivedi_v_3,ractivedi_v_3,ractivedi_v_3,ractivedi_v_2,ractivedi_v_2,
-    ractivedi_v_2,ractivedi_v_2,ractivedi_b_lo_lo_lo}; // @[VDecodeInstruction.scala 60:19]
+    ractivedi_v_2,ractivedi_v_2,ractivedi_b_lo_lo_lo}; // @[VDecodeInstruction.scala 55:19]
   wire [7:0] ractivedi_b_lo_hi_lo = {ractivedi_v_5,ractivedi_v_5,ractivedi_v_5,ractivedi_v_5,ractivedi_v_4,ractivedi_v_4
-    ,ractivedi_v_4,ractivedi_v_4}; // @[VDecodeInstruction.scala 60:19]
+    ,ractivedi_v_4,ractivedi_v_4}; // @[VDecodeInstruction.scala 55:19]
   wire [31:0] ractivedi_b_lo = {ractivedi_v_7,ractivedi_v_7,ractivedi_v_7,ractivedi_v_7,ractivedi_v_6,ractivedi_v_6,
-    ractivedi_v_6,ractivedi_v_6,ractivedi_b_lo_hi_lo,ractivedi_b_lo_lo}; // @[VDecodeInstruction.scala 60:19]
+    ractivedi_v_6,ractivedi_v_6,ractivedi_b_lo_hi_lo,ractivedi_b_lo_lo}; // @[VDecodeInstruction.scala 55:19]
   wire [7:0] ractivedi_b_hi_lo_lo = {ractivedi_v_9,ractivedi_v_9,ractivedi_v_9,ractivedi_v_9,ractivedi_v_8,ractivedi_v_8
-    ,ractivedi_v_8,ractivedi_v_8}; // @[VDecodeInstruction.scala 60:19]
+    ,ractivedi_v_8,ractivedi_v_8}; // @[VDecodeInstruction.scala 55:19]
   wire [15:0] ractivedi_b_hi_lo = {ractivedi_v_11,ractivedi_v_11,ractivedi_v_11,ractivedi_v_11,ractivedi_v_10,
-    ractivedi_v_10,ractivedi_v_10,ractivedi_v_10,ractivedi_b_hi_lo_lo}; // @[VDecodeInstruction.scala 60:19]
+    ractivedi_v_10,ractivedi_v_10,ractivedi_v_10,ractivedi_b_hi_lo_lo}; // @[VDecodeInstruction.scala 55:19]
   wire [7:0] ractivedi_b_hi_hi_lo = {ractivedi_v_13,ractivedi_v_13,ractivedi_v_13,ractivedi_v_13,ractivedi_v_12,
-    ractivedi_v_12,ractivedi_v_12,ractivedi_v_12}; // @[VDecodeInstruction.scala 60:19]
+    ractivedi_v_12,ractivedi_v_12,ractivedi_v_12}; // @[VDecodeInstruction.scala 55:19]
   wire [31:0] ractivedi_b_hi = {ractivedi_v_15,ractivedi_v_15,ractivedi_v_15,ractivedi_v_15,ractivedi_v_14,
-    ractivedi_v_14,ractivedi_v_14,ractivedi_v_14,ractivedi_b_hi_hi_lo,ractivedi_b_hi_lo}; // @[VDecodeInstruction.scala 60:19]
-  wire [63:0] ractivedi = {ractivedi_b_hi,ractivedi_b_lo}; // @[VDecodeInstruction.scala 60:19]
-  wire [3:0] wactivedw_shiftAmount = vdbits[5:2]; // @[VDecodeInstruction.scala 551:36]
+    ractivedi_v_14,ractivedi_v_14,ractivedi_v_14,ractivedi_b_hi_hi_lo,ractivedi_b_hi_lo}; // @[VDecodeInstruction.scala 55:19]
+  wire [63:0] ractivedi = {ractivedi_b_hi,ractivedi_b_lo}; // @[VDecodeInstruction.scala 55:19]
+  wire [3:0] wactivedw_shiftAmount = vdbits[5:2]; // @[VDecodeInstruction.scala 480:36]
   wire [15:0] _wactivedw_T_1 = 16'h1 << wactivedw_shiftAmount; // @[OneHot.scala 64:12]
-  wire  wactivedw_v = _wactivedw_T_1[0]; // @[VDecodeInstruction.scala 57:16]
-  wire  wactivedw_v_1 = _wactivedw_T_1[1]; // @[VDecodeInstruction.scala 57:16]
-  wire  wactivedw_v_2 = _wactivedw_T_1[2]; // @[VDecodeInstruction.scala 57:16]
-  wire  wactivedw_v_3 = _wactivedw_T_1[3]; // @[VDecodeInstruction.scala 57:16]
-  wire  wactivedw_v_4 = _wactivedw_T_1[4]; // @[VDecodeInstruction.scala 57:16]
-  wire  wactivedw_v_5 = _wactivedw_T_1[5]; // @[VDecodeInstruction.scala 57:16]
-  wire  wactivedw_v_6 = _wactivedw_T_1[6]; // @[VDecodeInstruction.scala 57:16]
-  wire  wactivedw_v_7 = _wactivedw_T_1[7]; // @[VDecodeInstruction.scala 57:16]
-  wire  wactivedw_v_8 = _wactivedw_T_1[8]; // @[VDecodeInstruction.scala 57:16]
-  wire  wactivedw_v_9 = _wactivedw_T_1[9]; // @[VDecodeInstruction.scala 57:16]
-  wire  wactivedw_v_10 = _wactivedw_T_1[10]; // @[VDecodeInstruction.scala 57:16]
-  wire  wactivedw_v_11 = _wactivedw_T_1[11]; // @[VDecodeInstruction.scala 57:16]
-  wire  wactivedw_v_12 = _wactivedw_T_1[12]; // @[VDecodeInstruction.scala 57:16]
-  wire  wactivedw_v_13 = _wactivedw_T_1[13]; // @[VDecodeInstruction.scala 57:16]
-  wire  wactivedw_v_14 = _wactivedw_T_1[14]; // @[VDecodeInstruction.scala 57:16]
-  wire  wactivedw_v_15 = _wactivedw_T_1[15]; // @[VDecodeInstruction.scala 57:16]
+  wire  wactivedw_v = _wactivedw_T_1[0]; // @[VDecodeInstruction.scala 52:16]
+  wire  wactivedw_v_1 = _wactivedw_T_1[1]; // @[VDecodeInstruction.scala 52:16]
+  wire  wactivedw_v_2 = _wactivedw_T_1[2]; // @[VDecodeInstruction.scala 52:16]
+  wire  wactivedw_v_3 = _wactivedw_T_1[3]; // @[VDecodeInstruction.scala 52:16]
+  wire  wactivedw_v_4 = _wactivedw_T_1[4]; // @[VDecodeInstruction.scala 52:16]
+  wire  wactivedw_v_5 = _wactivedw_T_1[5]; // @[VDecodeInstruction.scala 52:16]
+  wire  wactivedw_v_6 = _wactivedw_T_1[6]; // @[VDecodeInstruction.scala 52:16]
+  wire  wactivedw_v_7 = _wactivedw_T_1[7]; // @[VDecodeInstruction.scala 52:16]
+  wire  wactivedw_v_8 = _wactivedw_T_1[8]; // @[VDecodeInstruction.scala 52:16]
+  wire  wactivedw_v_9 = _wactivedw_T_1[9]; // @[VDecodeInstruction.scala 52:16]
+  wire  wactivedw_v_10 = _wactivedw_T_1[10]; // @[VDecodeInstruction.scala 52:16]
+  wire  wactivedw_v_11 = _wactivedw_T_1[11]; // @[VDecodeInstruction.scala 52:16]
+  wire  wactivedw_v_12 = _wactivedw_T_1[12]; // @[VDecodeInstruction.scala 52:16]
+  wire  wactivedw_v_13 = _wactivedw_T_1[13]; // @[VDecodeInstruction.scala 52:16]
+  wire  wactivedw_v_14 = _wactivedw_T_1[14]; // @[VDecodeInstruction.scala 52:16]
+  wire  wactivedw_v_15 = _wactivedw_T_1[15]; // @[VDecodeInstruction.scala 52:16]
   wire [7:0] wactivedw_b_lo_lo_lo = {wactivedw_v_1,wactivedw_v_1,wactivedw_v_1,wactivedw_v_1,wactivedw_v,wactivedw_v,
-    wactivedw_v,wactivedw_v}; // @[VDecodeInstruction.scala 60:19]
+    wactivedw_v,wactivedw_v}; // @[VDecodeInstruction.scala 55:19]
   wire [15:0] wactivedw_b_lo_lo = {wactivedw_v_3,wactivedw_v_3,wactivedw_v_3,wactivedw_v_3,wactivedw_v_2,wactivedw_v_2,
-    wactivedw_v_2,wactivedw_v_2,wactivedw_b_lo_lo_lo}; // @[VDecodeInstruction.scala 60:19]
+    wactivedw_v_2,wactivedw_v_2,wactivedw_b_lo_lo_lo}; // @[VDecodeInstruction.scala 55:19]
   wire [7:0] wactivedw_b_lo_hi_lo = {wactivedw_v_5,wactivedw_v_5,wactivedw_v_5,wactivedw_v_5,wactivedw_v_4,wactivedw_v_4
-    ,wactivedw_v_4,wactivedw_v_4}; // @[VDecodeInstruction.scala 60:19]
+    ,wactivedw_v_4,wactivedw_v_4}; // @[VDecodeInstruction.scala 55:19]
   wire [31:0] wactivedw_b_lo = {wactivedw_v_7,wactivedw_v_7,wactivedw_v_7,wactivedw_v_7,wactivedw_v_6,wactivedw_v_6,
-    wactivedw_v_6,wactivedw_v_6,wactivedw_b_lo_hi_lo,wactivedw_b_lo_lo}; // @[VDecodeInstruction.scala 60:19]
+    wactivedw_v_6,wactivedw_v_6,wactivedw_b_lo_hi_lo,wactivedw_b_lo_lo}; // @[VDecodeInstruction.scala 55:19]
   wire [7:0] wactivedw_b_hi_lo_lo = {wactivedw_v_9,wactivedw_v_9,wactivedw_v_9,wactivedw_v_9,wactivedw_v_8,wactivedw_v_8
-    ,wactivedw_v_8,wactivedw_v_8}; // @[VDecodeInstruction.scala 60:19]
+    ,wactivedw_v_8,wactivedw_v_8}; // @[VDecodeInstruction.scala 55:19]
   wire [15:0] wactivedw_b_hi_lo = {wactivedw_v_11,wactivedw_v_11,wactivedw_v_11,wactivedw_v_11,wactivedw_v_10,
-    wactivedw_v_10,wactivedw_v_10,wactivedw_v_10,wactivedw_b_hi_lo_lo}; // @[VDecodeInstruction.scala 60:19]
+    wactivedw_v_10,wactivedw_v_10,wactivedw_v_10,wactivedw_b_hi_lo_lo}; // @[VDecodeInstruction.scala 55:19]
   wire [7:0] wactivedw_b_hi_hi_lo = {wactivedw_v_13,wactivedw_v_13,wactivedw_v_13,wactivedw_v_13,wactivedw_v_12,
-    wactivedw_v_12,wactivedw_v_12,wactivedw_v_12}; // @[VDecodeInstruction.scala 60:19]
+    wactivedw_v_12,wactivedw_v_12,wactivedw_v_12}; // @[VDecodeInstruction.scala 55:19]
   wire [31:0] wactivedw_b_hi = {wactivedw_v_15,wactivedw_v_15,wactivedw_v_15,wactivedw_v_15,wactivedw_v_14,
-    wactivedw_v_14,wactivedw_v_14,wactivedw_v_14,wactivedw_b_hi_hi_lo,wactivedw_b_hi_lo}; // @[VDecodeInstruction.scala 60:19]
-  wire [63:0] wactivedw = {wactivedw_b_hi,wactivedw_b_lo}; // @[VDecodeInstruction.scala 60:19]
-  wire  s = func2[3]; // @[VDecodeInstruction.scala 196:18]
-  wire [5:0] _vs_T_2 = vsbits + 6'h3; // @[VDecodeInstruction.scala 197:28]
-  wire [6:0] _vs_T_3 = {{1'd0}, vsbits}; // @[VDecodeInstruction.scala 197:42]
-  wire [5:0] vssl = s ? _vs_T_2 : _vs_T_3[5:0]; // @[VDecodeInstruction.scala 197:17]
-  wire [6:0] _vt_T_1 = {{1'd0}, vtbits}; // @[VDecodeInstruction.scala 198:28]
-  wire [5:0] _vt_T_4 = vsbits + 6'h1; // @[VDecodeInstruction.scala 198:42]
-  wire [5:0] vtsl = s ? _vt_T_1[5:0] : _vt_T_4; // @[VDecodeInstruction.scala 198:17]
-  wire [5:0] _vu_T_2 = vtbits + 6'h1; // @[VDecodeInstruction.scala 199:28]
-  wire [5:0] _vu_T_4 = vsbits + 6'h2; // @[VDecodeInstruction.scala 199:42]
-  wire [5:0] vusl = s ? _vu_T_2 : _vu_T_4; // @[VDecodeInstruction.scala 199:17]
-  wire [5:0] _vy_T_3 = vtbits + 6'h2; // @[VDecodeInstruction.scala 201:28]
-  wire [5:0] vysl = s ? _vy_T_3 : _vs_T_2; // @[VDecodeInstruction.scala 201:17]
-  wire [5:0] _vz_T_3 = vtbits + 6'h3; // @[VDecodeInstruction.scala 202:28]
-  wire [5:0] vzsl = s ? _vz_T_3 : _vt_T_1[5:0]; // @[VDecodeInstruction.scala 202:17]
+    wactivedw_v_14,wactivedw_v_14,wactivedw_v_14,wactivedw_b_hi_hi_lo,wactivedw_b_hi_lo}; // @[VDecodeInstruction.scala 55:19]
+  wire [63:0] wactivedw = {wactivedw_b_hi,wactivedw_b_lo}; // @[VDecodeInstruction.scala 55:19]
+  wire  s = func2[3]; // @[VDecodeInstruction.scala 191:18]
+  wire [5:0] _vs_T_2 = vsbits + 6'h3; // @[VDecodeInstruction.scala 192:28]
+  wire [6:0] _vs_T_3 = {{1'd0}, vsbits}; // @[VDecodeInstruction.scala 192:42]
+  wire [5:0] vssl = s ? _vs_T_2 : _vs_T_3[5:0]; // @[VDecodeInstruction.scala 192:17]
+  wire [6:0] _vt_T_1 = {{1'd0}, vtbits}; // @[VDecodeInstruction.scala 193:28]
+  wire [5:0] _vt_T_4 = vsbits + 6'h1; // @[VDecodeInstruction.scala 193:42]
+  wire [5:0] vtsl = s ? _vt_T_1[5:0] : _vt_T_4; // @[VDecodeInstruction.scala 193:17]
+  wire [5:0] _vu_T_2 = vtbits + 6'h1; // @[VDecodeInstruction.scala 194:28]
+  wire [5:0] _vu_T_4 = vsbits + 6'h2; // @[VDecodeInstruction.scala 194:42]
+  wire [5:0] vusl = s ? _vu_T_2 : _vu_T_4; // @[VDecodeInstruction.scala 194:17]
+  wire [5:0] _vy_T_3 = vtbits + 6'h2; // @[VDecodeInstruction.scala 196:28]
+  wire [5:0] vysl = s ? _vy_T_3 : _vs_T_2; // @[VDecodeInstruction.scala 196:17]
+  wire [5:0] _vz_T_3 = vtbits + 6'h3; // @[VDecodeInstruction.scala 197:28]
+  wire [5:0] vzsl = s ? _vz_T_3 : _vt_T_1[5:0]; // @[VDecodeInstruction.scala 197:17]
   wire [63:0] ra_vs_1 = 64'h1 << vssl; // @[OneHot.scala 64:12]
-  wire  _ra_vt_T_3 = vfmadd4_bit_30 | ~s; // @[VDecodeInstruction.scala 211:27]
+  wire  _ra_vt_T_3 = aconv_bit_30 | ~s; // @[VDecodeInstruction.scala 206:27]
   wire [63:0] _ra_vt_T_4 = 64'h1 << vtsl; // @[OneHot.scala 64:12]
   wire [63:0] ra_vt_1 = _ra_vt_T_3 ? _ra_vt_T_4 : 64'h0; // @[Library.scala 18:8]
   wire [63:0] _ra_vu_T_4 = 64'h1 << vusl; // @[OneHot.scala 64:12]
@@ -37296,256 +27751,243 @@
   wire [63:0] _ra_vy_T_4 = 64'h1 << vysl; // @[OneHot.scala 64:12]
   wire [63:0] ra_vy_1 = _ra_vt_T_3 ? _ra_vy_T_4 : 64'h0; // @[Library.scala 18:8]
   wire [63:0] _ra_vz_T_2 = 64'h1 << vzsl; // @[OneHot.scala 64:12]
-  wire [63:0] ra_vz_1 = vfmadd4_bit_30 ? _ra_vz_T_2 : 64'h0; // @[Library.scala 18:8]
-  wire [63:0] _ractive_T_7 = ra_vs_1 | ra_vt_1; // @[VDecodeInstruction.scala 223:25]
-  wire [63:0] _ractive_T_8 = _ractive_T_7 | ra_vu_1; // @[VDecodeInstruction.scala 223:33]
-  wire [63:0] _ractive_T_9 = _ractive_T_8 | ra_vu_1; // @[VDecodeInstruction.scala 223:41]
-  wire [63:0] _ractive_T_10 = _ractive_T_9 | ra_vy_1; // @[VDecodeInstruction.scala 223:49]
-  wire [63:0] ractivesl = _ractive_T_10 | ra_vz_1; // @[VDecodeInstruction.scala 223:57]
+  wire [63:0] ra_vz_1 = aconv_bit_30 ? _ra_vz_T_2 : 64'h0; // @[Library.scala 18:8]
+  wire [63:0] _ractive_T_7 = ra_vs_1 | ra_vt_1; // @[VDecodeInstruction.scala 218:25]
+  wire [63:0] _ractive_T_8 = _ractive_T_7 | ra_vu_1; // @[VDecodeInstruction.scala 218:33]
+  wire [63:0] _ractive_T_9 = _ractive_T_8 | ra_vu_1; // @[VDecodeInstruction.scala 218:41]
+  wire [63:0] _ractive_T_10 = _ractive_T_9 | ra_vy_1; // @[VDecodeInstruction.scala 218:49]
+  wire [63:0] ractivesl = _ractive_T_10 | ra_vz_1; // @[VDecodeInstruction.scala 218:57]
   wire [5:0] _ractiveconv1_T_1 = {vsbits[5:4],4'h0}; // @[Cat.scala 31:58]
-  wire [70:0] _ractiveconv1_T_2 = 71'hff << _ractiveconv1_T_1; // @[VDecodeInstruction.scala 571:30]
+  wire [70:0] _ractiveconv1_T_2 = 71'hff << _ractiveconv1_T_1; // @[VDecodeInstruction.scala 500:30]
   wire [5:0] _ractiveconv2_T_1 = {func2[5:3],3'h0}; // @[Cat.scala 31:58]
-  wire [70:0] _ractiveconv2_T_2 = 71'hff << _ractiveconv2_T_1; // @[VDecodeInstruction.scala 572:30]
+  wire [70:0] _ractiveconv2_T_2 = 71'hff << _ractiveconv2_T_1; // @[VDecodeInstruction.scala 501:30]
   wire [5:0] _ractiveaset_T_1 = {vsbits[5:3],3'h0}; // @[Cat.scala 31:58]
-  wire [70:0] _ractiveaset_T_2 = 71'hff << _ractiveaset_T_1; // @[VDecodeInstruction.scala 573:30]
+  wire [70:0] _ractiveaset_T_2 = 71'hff << _ractiveaset_T_1; // @[VDecodeInstruction.scala 502:30]
   wire [5:0] _wactiveconv_T_1 = {vdbits[5:4],4'h0}; // @[Cat.scala 31:58]
-  wire [70:0] _wactiveconv_T_2 = 71'hff << _wactiveconv_T_1; // @[VDecodeInstruction.scala 574:30]
-  wire  _io_out_sz_T_1 = sz == 2'h1; // @[VDecodeInstruction.scala 589:35]
-  wire  _io_out_sz_T_2 = sz == 2'h0; // @[VDecodeInstruction.scala 589:47]
-  wire [1:0] io_out_sz_hi = {_vfadd_T_5,_io_out_sz_T_1}; // @[Cat.scala 31:58]
-  wire  _io_out_vs_valid_T = vadwconv | adwinit; // @[VDecodeInstruction.scala 597:31]
-  wire  _io_out_vt_valid_T_6 = vfmt0 | vfmt1 | vfmt2 | vfmt3 | vfmt4 | vfmt5; // @[VDecodeInstruction.scala 598:94]
-  wire  _io_out_vt_valid_T_7 = vfmt0 | vfmt1 | vfmt2 | vfmt3 | vfmt4 | vfmt5 | vfmt6; // @[VDecodeInstruction.scala 598:103]
-  wire  _io_out_vt_valid_T_10 = ~x3; // @[VDecodeInstruction.scala 598:116]
-  wire  _io_out_vu_valid_T_5 = vadwconv | vdmulh2 | vmul2 | vmulh2 | vmulhu2 | vmuls2 | vmv2; // @[VDecodeInstruction.scala 599:82]
-  wire  _io_out_vu_valid_T_16 = m & vevn3; // @[VDecodeInstruction.scala 599:190]
-  wire  _io_out_vz_valid_T_6 = _io_out_vu_valid_T_5 | vslideh2; // @[VDecodeInstruction.scala 602:90]
-  wire  _io_out_sv_valid_T_6 = vdup | vfmt0 | vfmt1 | vfmt2 | vfmt3 | vfmt4 | vfmt5 | vfmt6; // @[VDecodeInstruction.scala 603:87]
-  wire [5:0] _io_out_ve_addr_T_9 = vdbits + 6'h1; // @[VDecodeInstruction.scala 607:121]
-  wire [5:0] _io_out_ve_addr_T_11 = vdbits + 6'h4; // @[VDecodeInstruction.scala 608:35]
-  wire [5:0] _io_out_ve_addr_T_14 = m ? _io_out_ve_addr_T_11 : _io_out_ve_addr_T_9; // @[VDecodeInstruction.scala 608:24]
-  wire [5:0] _io_out_ve_addr_T_15 = _io_out_vz_valid_T_6 | vzip ? _io_out_ve_addr_T_9 : _io_out_ve_addr_T_14; // @[VDecodeInstruction.scala 607:24]
-  wire [5:0] _io_out_vs_addr_T_2 = vmadd | vst | vstq ? vdbits : vsbits; // @[VDecodeInstruction.scala 613:24]
-  wire [5:0] _io_out_vs_addr_T_3 = vslideh2 ? vssl : _io_out_vs_addr_T_2; // @[VDecodeInstruction.scala 612:24]
-  wire [5:0] _io_out_vt_addr_T_5 = _io_out_vu_valid_T_16 ? _vt_T_4 : vtbits; // @[VDecodeInstruction.scala 618:24]
-  wire [5:0] _io_out_vt_addr_T_6 = vslideh2 ? vtsl : _io_out_vt_addr_T_5; // @[VDecodeInstruction.scala 617:24]
-  wire [5:0] _io_out_vt_addr_T_7 = adwinit ? _vt_T_4 : _io_out_vt_addr_T_6; // @[VDecodeInstruction.scala 616:24]
-  wire  _io_out_vu_addr_T_4 = vdmulh2 | vmul2 | vmulh2 | vmulhu2 | vmuls2 | vmv2; // @[VDecodeInstruction.scala 621:73]
-  wire [5:0] _io_out_vu_addr_T_9 = vsbits + 6'h4; // @[VDecodeInstruction.scala 623:55]
-  wire [5:0] _io_out_vu_addr_T_12 = m ? _io_out_vu_addr_T_9 : _vt_T_4; // @[VDecodeInstruction.scala 623:44]
-  wire [5:0] _io_out_vu_addr_T_20 = vevn3 ? vtbits : func2; // @[VDecodeInstruction.scala 627:24]
-  wire [5:0] _io_out_vu_addr_T_21 = vmadd ? vsbits : _io_out_vu_addr_T_20; // @[VDecodeInstruction.scala 626:24]
-  wire [5:0] _io_out_vu_addr_T_22 = vmacc | vadd3 | vsel ? vdbits : _io_out_vu_addr_T_21; // @[VDecodeInstruction.scala 625:24]
-  wire [5:0] _io_out_vu_addr_T_23 = vsraqs ? _io_out_vu_addr_T_12 : _io_out_vu_addr_T_22; // @[VDecodeInstruction.scala 624:24]
-  wire [5:0] _io_out_vu_addr_T_24 = vacc | vsrans ? _io_out_vu_addr_T_12 : _io_out_vu_addr_T_23; // @[VDecodeInstruction.scala 623:24]
-  wire [5:0] _io_out_vu_addr_T_25 = vslideh2 ? vusl : _io_out_vu_addr_T_24; // @[VDecodeInstruction.scala 622:24]
-  wire [5:0] _io_out_vu_addr_T_26 = vdmulh2 | vmul2 | vmulh2 | vmulhu2 | vmuls2 | vmv2 ? _vt_T_4 : _io_out_vu_addr_T_25; // @[VDecodeInstruction.scala 621:24]
-  wire [5:0] _io_out_vx_addr_T_9 = vsbits + 6'h8; // @[VDecodeInstruction.scala 631:47]
-  wire [5:0] _io_out_vx_addr_T_12 = m ? _io_out_vx_addr_T_9 : _vu_T_4; // @[VDecodeInstruction.scala 631:36]
-  wire [5:0] _io_out_vx_addr_T_13 = vsraqs ? _io_out_vx_addr_T_12 : vusl; // @[VDecodeInstruction.scala 631:24]
+  wire [70:0] _wactiveconv_T_2 = 71'hff << _wactiveconv_T_1; // @[VDecodeInstruction.scala 503:30]
+  wire  _io_out_sz_T = sz == 2'h2; // @[VDecodeInstruction.scala 518:23]
+  wire  _io_out_sz_T_1 = sz == 2'h1; // @[VDecodeInstruction.scala 518:35]
+  wire  _io_out_sz_T_2 = sz == 2'h0; // @[VDecodeInstruction.scala 518:47]
+  wire [1:0] io_out_sz_hi = {_io_out_sz_T,_io_out_sz_T_1}; // @[Cat.scala 31:58]
+  wire  _io_out_vs_valid_T = vadwconv | adwinit; // @[VDecodeInstruction.scala 526:31]
+  wire  _io_out_vt_valid_T_5 = vfmt0 | vfmt1 | vfmt2 | vfmt3 | vfmt4; // @[VDecodeInstruction.scala 527:85]
+  wire  _io_out_vt_valid_T_6 = vfmt0 | vfmt1 | vfmt2 | vfmt3 | vfmt4 | vfmt6; // @[VDecodeInstruction.scala 527:94]
+  wire  _io_out_vu_valid_T_5 = vadwconv | vdmulh2 | vmul2 | vmulh2 | vmulhu2 | vmuls2 | vmv2; // @[VDecodeInstruction.scala 528:82]
+  wire  _io_out_vu_valid_T_15 = m & vevn3; // @[VDecodeInstruction.scala 528:179]
+  wire  _io_out_vz_valid_T_6 = _io_out_vu_valid_T_5 | vslideh2; // @[VDecodeInstruction.scala 531:90]
+  wire  _io_out_sv_valid_T_5 = vdup | vfmt0 | vfmt1 | vfmt2 | vfmt3 | vfmt4 | vfmt6; // @[VDecodeInstruction.scala 532:78]
+  wire [5:0] _io_out_ve_addr_T_9 = vdbits + 6'h1; // @[VDecodeInstruction.scala 536:121]
+  wire [5:0] _io_out_ve_addr_T_11 = vdbits + 6'h4; // @[VDecodeInstruction.scala 537:35]
+  wire [5:0] _io_out_ve_addr_T_14 = m ? _io_out_ve_addr_T_11 : _io_out_ve_addr_T_9; // @[VDecodeInstruction.scala 537:24]
+  wire [5:0] _io_out_ve_addr_T_15 = _io_out_vz_valid_T_6 | vzip ? _io_out_ve_addr_T_9 : _io_out_ve_addr_T_14; // @[VDecodeInstruction.scala 536:24]
+  wire [5:0] _io_out_vs_addr_T_2 = vmadd | vst | vstq ? vdbits : vsbits; // @[VDecodeInstruction.scala 542:24]
+  wire [5:0] _io_out_vs_addr_T_3 = vslideh2 ? vssl : _io_out_vs_addr_T_2; // @[VDecodeInstruction.scala 541:24]
+  wire [5:0] _io_out_vt_addr_T_5 = _io_out_vu_valid_T_15 ? _vt_T_4 : vtbits; // @[VDecodeInstruction.scala 547:24]
+  wire [5:0] _io_out_vt_addr_T_6 = vslideh2 ? vtsl : _io_out_vt_addr_T_5; // @[VDecodeInstruction.scala 546:24]
+  wire [5:0] _io_out_vt_addr_T_7 = adwinit ? _vt_T_4 : _io_out_vt_addr_T_6; // @[VDecodeInstruction.scala 545:24]
+  wire  _io_out_vu_addr_T_4 = vdmulh2 | vmul2 | vmulh2 | vmulhu2 | vmuls2 | vmv2; // @[VDecodeInstruction.scala 550:73]
+  wire [5:0] _io_out_vu_addr_T_9 = vsbits + 6'h4; // @[VDecodeInstruction.scala 552:55]
+  wire [5:0] _io_out_vu_addr_T_12 = m ? _io_out_vu_addr_T_9 : _vt_T_4; // @[VDecodeInstruction.scala 552:44]
+  wire [5:0] _io_out_vu_addr_T_20 = vevn3 ? vtbits : func2; // @[VDecodeInstruction.scala 556:24]
+  wire [5:0] _io_out_vu_addr_T_21 = vmadd ? vsbits : _io_out_vu_addr_T_20; // @[VDecodeInstruction.scala 555:24]
+  wire [5:0] _io_out_vu_addr_T_22 = vmacc | vadd3 | vsel ? vdbits : _io_out_vu_addr_T_21; // @[VDecodeInstruction.scala 554:24]
+  wire [5:0] _io_out_vu_addr_T_23 = vsraqs ? _io_out_vu_addr_T_12 : _io_out_vu_addr_T_22; // @[VDecodeInstruction.scala 553:24]
+  wire [5:0] _io_out_vu_addr_T_24 = vacc | vsrans ? _io_out_vu_addr_T_12 : _io_out_vu_addr_T_23; // @[VDecodeInstruction.scala 552:24]
+  wire [5:0] _io_out_vu_addr_T_25 = vslideh2 ? vusl : _io_out_vu_addr_T_24; // @[VDecodeInstruction.scala 551:24]
+  wire [5:0] _io_out_vu_addr_T_26 = vdmulh2 | vmul2 | vmulh2 | vmulhu2 | vmuls2 | vmv2 ? _vt_T_4 : _io_out_vu_addr_T_25; // @[VDecodeInstruction.scala 550:24]
+  wire [5:0] _io_out_vx_addr_T_9 = vsbits + 6'h8; // @[VDecodeInstruction.scala 560:47]
+  wire [5:0] _io_out_vx_addr_T_12 = m ? _io_out_vx_addr_T_9 : _vu_T_4; // @[VDecodeInstruction.scala 560:36]
+  wire [5:0] _io_out_vx_addr_T_13 = vsraqs ? _io_out_vx_addr_T_12 : vusl; // @[VDecodeInstruction.scala 560:24]
   wire [5:0] _io_out_vx_addr_T_14 = adwinit | vdmulh2 | vmul2 | vmulh2 | vmulhu2 | vmuls2 | vmv2 ? _vu_T_4 :
-    _io_out_vx_addr_T_13; // @[VDecodeInstruction.scala 630:24]
-  wire [5:0] _io_out_vy_addr_T_2 = vsraqs ? vtbits : vysl; // @[VDecodeInstruction.scala 635:24]
-  wire [5:0] _io_out_vy_addr_T_3 = adwinit ? _vs_T_2 : _io_out_vy_addr_T_2; // @[VDecodeInstruction.scala 634:24]
-  wire [5:0] _io_out_vz_addr_T_8 = vsbits + 6'hc; // @[VDecodeInstruction.scala 639:47]
-  wire [5:0] _io_out_vz_addr_T_11 = m ? _io_out_vz_addr_T_8 : _vs_T_2; // @[VDecodeInstruction.scala 639:36]
-  wire [5:0] _io_out_vz_addr_T_12 = vsraqs ? _io_out_vz_addr_T_11 : vzsl; // @[VDecodeInstruction.scala 639:24]
-  wire [5:0] _io_out_vz_addr_T_13 = _io_out_vu_addr_T_4 ? _vs_T_2 : _io_out_vz_addr_T_12; // @[VDecodeInstruction.scala 638:24]
-  wire [1:0] _io_out_sv_data_T_3 = sz - 2'h1; // @[VDecodeInstruction.scala 651:64]
-  wire  _io_out_sv_data_T_4 = _io_out_sv_data_T_3 == 2'h0; // @[VDecodeInstruction.scala 542:14]
+    _io_out_vx_addr_T_13; // @[VDecodeInstruction.scala 559:24]
+  wire [5:0] _io_out_vy_addr_T_2 = vsraqs ? vtbits : vysl; // @[VDecodeInstruction.scala 564:24]
+  wire [5:0] _io_out_vy_addr_T_3 = adwinit ? _vs_T_2 : _io_out_vy_addr_T_2; // @[VDecodeInstruction.scala 563:24]
+  wire [5:0] _io_out_vz_addr_T_8 = vsbits + 6'hc; // @[VDecodeInstruction.scala 568:47]
+  wire [5:0] _io_out_vz_addr_T_11 = m ? _io_out_vz_addr_T_8 : _vs_T_2; // @[VDecodeInstruction.scala 568:36]
+  wire [5:0] _io_out_vz_addr_T_12 = vsraqs ? _io_out_vz_addr_T_11 : vzsl; // @[VDecodeInstruction.scala 568:24]
+  wire [5:0] _io_out_vz_addr_T_13 = _io_out_vu_addr_T_4 ? _vs_T_2 : _io_out_vz_addr_T_12; // @[VDecodeInstruction.scala 567:24]
+  wire [1:0] _io_out_sv_data_T_3 = sz - 2'h1; // @[VDecodeInstruction.scala 580:64]
+  wire  _io_out_sv_data_T_4 = _io_out_sv_data_T_3 == 2'h0; // @[VDecodeInstruction.scala 471:14]
   wire [31:0] _io_out_sv_data_T_9 = {io_in_data[7:0],io_in_data[7:0],io_in_data[7:0],io_in_data[7:0]}; // @[Cat.scala 31:58]
   wire [31:0] _io_out_sv_data_T_10 = _io_out_sv_data_T_4 ? _io_out_sv_data_T_9 : 32'h0; // @[Library.scala 18:8]
-  wire  _io_out_sv_data_T_11 = _io_out_sv_data_T_3 == 2'h1; // @[VDecodeInstruction.scala 543:20]
+  wire  _io_out_sv_data_T_11 = _io_out_sv_data_T_3 == 2'h1; // @[VDecodeInstruction.scala 472:20]
   wire [31:0] _io_out_sv_data_T_14 = {io_in_data[15:0],io_in_data[15:0]}; // @[Cat.scala 31:58]
   wire [31:0] _io_out_sv_data_T_15 = _io_out_sv_data_T_11 ? _io_out_sv_data_T_14 : 32'h0; // @[Library.scala 18:8]
-  wire [31:0] _io_out_sv_data_T_16 = _io_out_sv_data_T_10 | _io_out_sv_data_T_15; // @[VDecodeInstruction.scala 542:72]
-  wire  _io_out_sv_data_T_17 = _io_out_sv_data_T_3 == 2'h2; // @[VDecodeInstruction.scala 544:20]
+  wire [31:0] _io_out_sv_data_T_16 = _io_out_sv_data_T_10 | _io_out_sv_data_T_15; // @[VDecodeInstruction.scala 471:72]
+  wire  _io_out_sv_data_T_17 = _io_out_sv_data_T_3 == 2'h2; // @[VDecodeInstruction.scala 473:20]
   wire [31:0] _io_out_sv_data_T_19 = _io_out_sv_data_T_17 ? io_in_data : 32'h0; // @[Library.scala 18:8]
-  wire [31:0] _io_out_sv_data_T_20 = _io_out_sv_data_T_16 | _io_out_sv_data_T_19; // @[VDecodeInstruction.scala 543:58]
+  wire [31:0] _io_out_sv_data_T_20 = _io_out_sv_data_T_16 | _io_out_sv_data_T_19; // @[VDecodeInstruction.scala 472:58]
   wire [31:0] _io_out_sv_data_T_27 = _io_out_sz_T_2 ? _io_out_sv_data_T_9 : 32'h0; // @[Library.scala 18:8]
   wire [31:0] _io_out_sv_data_T_32 = _io_out_sz_T_1 ? _io_out_sv_data_T_14 : 32'h0; // @[Library.scala 18:8]
-  wire [31:0] _io_out_sv_data_T_33 = _io_out_sv_data_T_27 | _io_out_sv_data_T_32; // @[VDecodeInstruction.scala 542:72]
-  wire [31:0] _io_out_sv_data_T_36 = _vfadd_T_5 ? io_in_data : 32'h0; // @[Library.scala 18:8]
-  wire [31:0] _io_out_sv_data_T_37 = _io_out_sv_data_T_33 | _io_out_sv_data_T_36; // @[VDecodeInstruction.scala 543:58]
-  wire [31:0] _io_out_sv_data_T_38 = vaddw | vmulw | vsubw ? _io_out_sv_data_T_20 : _io_out_sv_data_T_37; // @[VDecodeInstruction.scala 651:24]
-  wire [1:0] _T_329 = io_out_sz[1] + io_out_sz[2]; // @[Bitwise.scala 48:55]
-  wire [1:0] _GEN_91 = {{1'd0}, io_out_sz[0]}; // @[Bitwise.scala 48:55]
-  wire [2:0] _T_331 = _GEN_91 + _T_329; // @[Bitwise.scala 48:55]
-  wire  _T_337 = ~io_out_cmdsync; // @[VDecodeInstruction.scala 655:31]
+  wire [31:0] _io_out_sv_data_T_33 = _io_out_sv_data_T_27 | _io_out_sv_data_T_32; // @[VDecodeInstruction.scala 471:72]
+  wire [31:0] _io_out_sv_data_T_36 = _io_out_sz_T ? io_in_data : 32'h0; // @[Library.scala 18:8]
+  wire [31:0] _io_out_sv_data_T_37 = _io_out_sv_data_T_33 | _io_out_sv_data_T_36; // @[VDecodeInstruction.scala 472:58]
+  wire [31:0] _io_out_sv_data_T_38 = vaddw | vmulw | vsubw ? _io_out_sv_data_T_20 : _io_out_sv_data_T_37; // @[VDecodeInstruction.scala 580:24]
+  wire [1:0] _T_242 = io_out_sz[1] + io_out_sz[2]; // @[Bitwise.scala 48:55]
+  wire [1:0] _GEN_72 = {{1'd0}, io_out_sz[0]}; // @[Bitwise.scala 48:55]
+  wire [2:0] _T_244 = _GEN_72 + _T_242; // @[Bitwise.scala 48:55]
+  wire  _T_250 = ~io_out_cmdsync; // @[VDecodeInstruction.scala 584:31]
   wire [5:0] cmdqchk = {io_undef,io_cmdq_alu,io_cmdq_conv,io_cmdq_ldst,io_cmdq_ld,io_cmdq_st}; // @[Cat.scala 31:58]
-  wire [1:0] _T_361 = cmdqchk[1] + cmdqchk[2]; // @[Bitwise.scala 48:55]
-  wire [1:0] _GEN_92 = {{1'd0}, cmdqchk[0]}; // @[Bitwise.scala 48:55]
-  wire [2:0] _T_363 = _GEN_92 + _T_361; // @[Bitwise.scala 48:55]
-  wire [1:0] _T_365 = cmdqchk[4] + cmdqchk[5]; // @[Bitwise.scala 48:55]
-  wire [1:0] _GEN_93 = {{1'd0}, cmdqchk[3]}; // @[Bitwise.scala 48:55]
-  wire [2:0] _T_367 = _GEN_93 + _T_365; // @[Bitwise.scala 48:55]
-  wire [2:0] _T_369 = _T_363[1:0] + _T_367[1:0]; // @[Bitwise.scala 48:55]
-  wire  _io_actv_ractive_T_6 = vfmt6 & ~vslideh2; // @[VDecodeInstruction.scala 670:17]
-  wire  _io_actv_ractive_T_7 = _io_out_vt_valid_T_6 | _io_actv_ractive_T_6; // @[VDecodeInstruction.scala 669:62]
+  wire [1:0] _T_274 = cmdqchk[1] + cmdqchk[2]; // @[Bitwise.scala 48:55]
+  wire [1:0] _GEN_73 = {{1'd0}, cmdqchk[0]}; // @[Bitwise.scala 48:55]
+  wire [2:0] _T_276 = _GEN_73 + _T_274; // @[Bitwise.scala 48:55]
+  wire [1:0] _T_278 = cmdqchk[4] + cmdqchk[5]; // @[Bitwise.scala 48:55]
+  wire [1:0] _GEN_74 = {{1'd0}, cmdqchk[3]}; // @[Bitwise.scala 48:55]
+  wire [2:0] _T_280 = _GEN_74 + _T_278; // @[Bitwise.scala 48:55]
+  wire [2:0] _T_282 = _T_276[1:0] + _T_280[1:0]; // @[Bitwise.scala 48:55]
+  wire  _io_actv_ractive_T_5 = vfmt6 & ~vslideh2; // @[VDecodeInstruction.scala 599:17]
+  wire  _io_actv_ractive_T_6 = _io_out_vt_valid_T_5 | _io_actv_ractive_T_5; // @[VDecodeInstruction.scala 598:53]
   wire [63:0] io_actv_ractive_vs = 64'h1 << vsbits; // @[OneHot.scala 64:12]
   wire [63:0] io_actv_ractive_vsm = m ? ractivedi : 64'h0; // @[Library.scala 18:8]
   wire [63:0] _io_actv_ractive_vt_T_1 = 64'h1 << vtbits; // @[OneHot.scala 64:12]
-  wire [63:0] io_actv_ractive_vt = vfmadd4_bit_30 ? _io_actv_ractive_vt_T_1 : 64'h0; // @[Library.scala 18:8]
-  wire  _io_actv_ractive_vtm_T_1 = m & vfmadd4_bit_30; // @[VDecodeInstruction.scala 78:17]
-  wire [3:0] io_actv_ractive_vtm_shiftAmount = vtbits[5:2]; // @[VDecodeInstruction.scala 78:41]
+  wire [63:0] io_actv_ractive_vt = aconv_bit_30 ? _io_actv_ractive_vt_T_1 : 64'h0; // @[Library.scala 18:8]
+  wire  _io_actv_ractive_vtm_T_1 = m & aconv_bit_30; // @[VDecodeInstruction.scala 73:17]
+  wire [3:0] io_actv_ractive_vtm_shiftAmount = vtbits[5:2]; // @[VDecodeInstruction.scala 73:41]
   wire [15:0] _io_actv_ractive_vtm_T_3 = 16'h1 << io_actv_ractive_vtm_shiftAmount; // @[OneHot.scala 64:12]
-  wire  io_actv_ractive_vtm_v = _io_actv_ractive_vtm_T_3[0]; // @[VDecodeInstruction.scala 57:16]
-  wire  io_actv_ractive_vtm_v_1 = _io_actv_ractive_vtm_T_3[1]; // @[VDecodeInstruction.scala 57:16]
-  wire  io_actv_ractive_vtm_v_2 = _io_actv_ractive_vtm_T_3[2]; // @[VDecodeInstruction.scala 57:16]
-  wire  io_actv_ractive_vtm_v_3 = _io_actv_ractive_vtm_T_3[3]; // @[VDecodeInstruction.scala 57:16]
-  wire  io_actv_ractive_vtm_v_4 = _io_actv_ractive_vtm_T_3[4]; // @[VDecodeInstruction.scala 57:16]
-  wire  io_actv_ractive_vtm_v_5 = _io_actv_ractive_vtm_T_3[5]; // @[VDecodeInstruction.scala 57:16]
-  wire  io_actv_ractive_vtm_v_6 = _io_actv_ractive_vtm_T_3[6]; // @[VDecodeInstruction.scala 57:16]
-  wire  io_actv_ractive_vtm_v_7 = _io_actv_ractive_vtm_T_3[7]; // @[VDecodeInstruction.scala 57:16]
-  wire  io_actv_ractive_vtm_v_8 = _io_actv_ractive_vtm_T_3[8]; // @[VDecodeInstruction.scala 57:16]
-  wire  io_actv_ractive_vtm_v_9 = _io_actv_ractive_vtm_T_3[9]; // @[VDecodeInstruction.scala 57:16]
-  wire  io_actv_ractive_vtm_v_10 = _io_actv_ractive_vtm_T_3[10]; // @[VDecodeInstruction.scala 57:16]
-  wire  io_actv_ractive_vtm_v_11 = _io_actv_ractive_vtm_T_3[11]; // @[VDecodeInstruction.scala 57:16]
-  wire  io_actv_ractive_vtm_v_12 = _io_actv_ractive_vtm_T_3[12]; // @[VDecodeInstruction.scala 57:16]
-  wire  io_actv_ractive_vtm_v_13 = _io_actv_ractive_vtm_T_3[13]; // @[VDecodeInstruction.scala 57:16]
-  wire  io_actv_ractive_vtm_v_14 = _io_actv_ractive_vtm_T_3[14]; // @[VDecodeInstruction.scala 57:16]
-  wire  io_actv_ractive_vtm_v_15 = _io_actv_ractive_vtm_T_3[15]; // @[VDecodeInstruction.scala 57:16]
+  wire  io_actv_ractive_vtm_v = _io_actv_ractive_vtm_T_3[0]; // @[VDecodeInstruction.scala 52:16]
+  wire  io_actv_ractive_vtm_v_1 = _io_actv_ractive_vtm_T_3[1]; // @[VDecodeInstruction.scala 52:16]
+  wire  io_actv_ractive_vtm_v_2 = _io_actv_ractive_vtm_T_3[2]; // @[VDecodeInstruction.scala 52:16]
+  wire  io_actv_ractive_vtm_v_3 = _io_actv_ractive_vtm_T_3[3]; // @[VDecodeInstruction.scala 52:16]
+  wire  io_actv_ractive_vtm_v_4 = _io_actv_ractive_vtm_T_3[4]; // @[VDecodeInstruction.scala 52:16]
+  wire  io_actv_ractive_vtm_v_5 = _io_actv_ractive_vtm_T_3[5]; // @[VDecodeInstruction.scala 52:16]
+  wire  io_actv_ractive_vtm_v_6 = _io_actv_ractive_vtm_T_3[6]; // @[VDecodeInstruction.scala 52:16]
+  wire  io_actv_ractive_vtm_v_7 = _io_actv_ractive_vtm_T_3[7]; // @[VDecodeInstruction.scala 52:16]
+  wire  io_actv_ractive_vtm_v_8 = _io_actv_ractive_vtm_T_3[8]; // @[VDecodeInstruction.scala 52:16]
+  wire  io_actv_ractive_vtm_v_9 = _io_actv_ractive_vtm_T_3[9]; // @[VDecodeInstruction.scala 52:16]
+  wire  io_actv_ractive_vtm_v_10 = _io_actv_ractive_vtm_T_3[10]; // @[VDecodeInstruction.scala 52:16]
+  wire  io_actv_ractive_vtm_v_11 = _io_actv_ractive_vtm_T_3[11]; // @[VDecodeInstruction.scala 52:16]
+  wire  io_actv_ractive_vtm_v_12 = _io_actv_ractive_vtm_T_3[12]; // @[VDecodeInstruction.scala 52:16]
+  wire  io_actv_ractive_vtm_v_13 = _io_actv_ractive_vtm_T_3[13]; // @[VDecodeInstruction.scala 52:16]
+  wire  io_actv_ractive_vtm_v_14 = _io_actv_ractive_vtm_T_3[14]; // @[VDecodeInstruction.scala 52:16]
+  wire  io_actv_ractive_vtm_v_15 = _io_actv_ractive_vtm_T_3[15]; // @[VDecodeInstruction.scala 52:16]
   wire [7:0] io_actv_ractive_vtm_b_lo_lo_lo = {io_actv_ractive_vtm_v_1,io_actv_ractive_vtm_v_1,io_actv_ractive_vtm_v_1,
-    io_actv_ractive_vtm_v_1,io_actv_ractive_vtm_v,io_actv_ractive_vtm_v,io_actv_ractive_vtm_v,io_actv_ractive_vtm_v}; // @[VDecodeInstruction.scala 60:19]
+    io_actv_ractive_vtm_v_1,io_actv_ractive_vtm_v,io_actv_ractive_vtm_v,io_actv_ractive_vtm_v,io_actv_ractive_vtm_v}; // @[VDecodeInstruction.scala 55:19]
   wire [15:0] io_actv_ractive_vtm_b_lo_lo = {io_actv_ractive_vtm_v_3,io_actv_ractive_vtm_v_3,io_actv_ractive_vtm_v_3,
     io_actv_ractive_vtm_v_3,io_actv_ractive_vtm_v_2,io_actv_ractive_vtm_v_2,io_actv_ractive_vtm_v_2,
-    io_actv_ractive_vtm_v_2,io_actv_ractive_vtm_b_lo_lo_lo}; // @[VDecodeInstruction.scala 60:19]
+    io_actv_ractive_vtm_v_2,io_actv_ractive_vtm_b_lo_lo_lo}; // @[VDecodeInstruction.scala 55:19]
   wire [7:0] io_actv_ractive_vtm_b_lo_hi_lo = {io_actv_ractive_vtm_v_5,io_actv_ractive_vtm_v_5,io_actv_ractive_vtm_v_5,
     io_actv_ractive_vtm_v_5,io_actv_ractive_vtm_v_4,io_actv_ractive_vtm_v_4,io_actv_ractive_vtm_v_4,
-    io_actv_ractive_vtm_v_4}; // @[VDecodeInstruction.scala 60:19]
+    io_actv_ractive_vtm_v_4}; // @[VDecodeInstruction.scala 55:19]
   wire [31:0] io_actv_ractive_vtm_b_lo = {io_actv_ractive_vtm_v_7,io_actv_ractive_vtm_v_7,io_actv_ractive_vtm_v_7,
     io_actv_ractive_vtm_v_7,io_actv_ractive_vtm_v_6,io_actv_ractive_vtm_v_6,io_actv_ractive_vtm_v_6,
-    io_actv_ractive_vtm_v_6,io_actv_ractive_vtm_b_lo_hi_lo,io_actv_ractive_vtm_b_lo_lo}; // @[VDecodeInstruction.scala 60:19]
+    io_actv_ractive_vtm_v_6,io_actv_ractive_vtm_b_lo_hi_lo,io_actv_ractive_vtm_b_lo_lo}; // @[VDecodeInstruction.scala 55:19]
   wire [7:0] io_actv_ractive_vtm_b_hi_lo_lo = {io_actv_ractive_vtm_v_9,io_actv_ractive_vtm_v_9,io_actv_ractive_vtm_v_9,
     io_actv_ractive_vtm_v_9,io_actv_ractive_vtm_v_8,io_actv_ractive_vtm_v_8,io_actv_ractive_vtm_v_8,
-    io_actv_ractive_vtm_v_8}; // @[VDecodeInstruction.scala 60:19]
+    io_actv_ractive_vtm_v_8}; // @[VDecodeInstruction.scala 55:19]
   wire [15:0] io_actv_ractive_vtm_b_hi_lo = {io_actv_ractive_vtm_v_11,io_actv_ractive_vtm_v_11,io_actv_ractive_vtm_v_11,
     io_actv_ractive_vtm_v_11,io_actv_ractive_vtm_v_10,io_actv_ractive_vtm_v_10,io_actv_ractive_vtm_v_10,
-    io_actv_ractive_vtm_v_10,io_actv_ractive_vtm_b_hi_lo_lo}; // @[VDecodeInstruction.scala 60:19]
+    io_actv_ractive_vtm_v_10,io_actv_ractive_vtm_b_hi_lo_lo}; // @[VDecodeInstruction.scala 55:19]
   wire [7:0] io_actv_ractive_vtm_b_hi_hi_lo = {io_actv_ractive_vtm_v_13,io_actv_ractive_vtm_v_13,
     io_actv_ractive_vtm_v_13,io_actv_ractive_vtm_v_13,io_actv_ractive_vtm_v_12,io_actv_ractive_vtm_v_12,
-    io_actv_ractive_vtm_v_12,io_actv_ractive_vtm_v_12}; // @[VDecodeInstruction.scala 60:19]
+    io_actv_ractive_vtm_v_12,io_actv_ractive_vtm_v_12}; // @[VDecodeInstruction.scala 55:19]
   wire [31:0] io_actv_ractive_vtm_b_hi = {io_actv_ractive_vtm_v_15,io_actv_ractive_vtm_v_15,io_actv_ractive_vtm_v_15,
     io_actv_ractive_vtm_v_15,io_actv_ractive_vtm_v_14,io_actv_ractive_vtm_v_14,io_actv_ractive_vtm_v_14,
-    io_actv_ractive_vtm_v_14,io_actv_ractive_vtm_b_hi_hi_lo,io_actv_ractive_vtm_b_hi_lo}; // @[VDecodeInstruction.scala 60:19]
-  wire [63:0] io_actv_ractive_vtm_b = {io_actv_ractive_vtm_b_hi,io_actv_ractive_vtm_b_lo}; // @[VDecodeInstruction.scala 60:19]
+    io_actv_ractive_vtm_v_14,io_actv_ractive_vtm_b_hi_hi_lo,io_actv_ractive_vtm_b_hi_lo}; // @[VDecodeInstruction.scala 55:19]
+  wire [63:0] io_actv_ractive_vtm_b = {io_actv_ractive_vtm_b_hi,io_actv_ractive_vtm_b_lo}; // @[VDecodeInstruction.scala 55:19]
   wire [63:0] io_actv_ractive_vtm = _io_actv_ractive_vtm_T_1 ? io_actv_ractive_vtm_b : 64'h0; // @[Library.scala 18:8]
-  wire [63:0] _io_actv_ractive_T_8 = io_actv_ractive_vs | io_actv_ractive_vsm; // @[VDecodeInstruction.scala 86:8]
-  wire [63:0] _io_actv_ractive_T_9 = _io_actv_ractive_T_8 | io_actv_ractive_vt; // @[VDecodeInstruction.scala 86:14]
-  wire [63:0] _io_actv_ractive_T_10 = _io_actv_ractive_T_9 | io_actv_ractive_vtm; // @[VDecodeInstruction.scala 86:19]
-  wire [63:0] _io_actv_ractive_T_11 = _io_actv_ractive_T_7 ? _io_actv_ractive_T_10 : 64'h0; // @[Library.scala 18:8]
-  wire [63:0] io_actv_ractive_vt_1 = _io_out_vt_valid_T_10 ? _io_actv_ractive_vt_T_1 : 64'h0; // @[Library.scala 18:8]
-  wire  _io_actv_ractive_vtm_T_6 = m & _io_out_vt_valid_T_10; // @[VDecodeInstruction.scala 80:17]
-  wire [63:0] io_actv_ractive_vtm_1 = _io_actv_ractive_vtm_T_6 ? io_actv_ractive_vtm_b : 64'h0; // @[Library.scala 18:8]
-  wire [63:0] _io_actv_ractive_T_13 = _io_actv_ractive_T_8 | io_actv_ractive_vt_1; // @[VDecodeInstruction.scala 86:14]
-  wire [63:0] _io_actv_ractive_T_14 = _io_actv_ractive_T_13 | io_actv_ractive_vtm_1; // @[VDecodeInstruction.scala 86:19]
-  wire [63:0] _io_actv_ractive_T_15 = vfmadd4 ? _io_actv_ractive_T_14 : 64'h0; // @[Library.scala 18:8]
-  wire [63:0] _io_actv_ractive_T_16 = _io_actv_ractive_T_11 | _io_actv_ractive_T_15; // @[VDecodeInstruction.scala 670:80]
-  wire  _io_actv_ractive_T_17 = vsraqs | vsrans; // @[VDecodeInstruction.scala 672:18]
-  wire [64:0] _io_actv_ractive_vs_T_4 = {io_actv_ractive_vs,1'h0}; // @[Cat.scala 31:58]
-  wire [63:0] io_actv_ractive_vs_2 = _io_actv_ractive_vs_T_4[63:0]; // @[VDecodeInstruction.scala 91:48]
-  wire [67:0] _io_actv_ractive_vsm_T_9 = {ractivedi_b_hi,ractivedi_b_lo,4'h0}; // @[Cat.scala 31:58]
-  wire [63:0] io_actv_ractive_vsm_2 = m ? _io_actv_ractive_vsm_T_9[63:0] : 64'h0; // @[Library.scala 18:8]
-  wire [63:0] _io_actv_ractive_T_18 = io_actv_ractive_vs_2 | io_actv_ractive_vsm_2; // @[VDecodeInstruction.scala 95:8]
-  wire [63:0] _io_actv_ractive_T_19 = _io_actv_ractive_T_17 ? _io_actv_ractive_T_18 : 64'h0; // @[Library.scala 18:8]
-  wire [63:0] _io_actv_ractive_T_20 = _io_actv_ractive_T_16 | _io_actv_ractive_T_19; // @[VDecodeInstruction.scala 671:80]
-  wire [65:0] _io_actv_ractive_vs_T_7 = {io_actv_ractive_vs,2'h0}; // @[Cat.scala 31:58]
-  wire [63:0] io_actv_ractive_vs_3 = _io_actv_ractive_vs_T_7[63:0]; // @[VDecodeInstruction.scala 100:48]
-  wire [71:0] _io_actv_ractive_vsm_T_14 = {ractivedi_b_hi,ractivedi_b_lo,8'h0}; // @[Cat.scala 31:58]
-  wire [63:0] io_actv_ractive_vsm_3 = m ? _io_actv_ractive_vsm_T_14[63:0] : 64'h0; // @[Library.scala 18:8]
-  wire [63:0] _io_actv_ractive_T_21 = io_actv_ractive_vs_3 | io_actv_ractive_vsm_3; // @[VDecodeInstruction.scala 104:8]
-  wire [63:0] _io_actv_ractive_T_22 = vsraqs ? _io_actv_ractive_T_21 : 64'h0; // @[Library.scala 18:8]
-  wire [63:0] _io_actv_ractive_T_23 = _io_actv_ractive_T_20 | _io_actv_ractive_T_22; // @[VDecodeInstruction.scala 672:80]
-  wire [66:0] _io_actv_ractive_vs_T_10 = {io_actv_ractive_vs,3'h0}; // @[Cat.scala 31:58]
-  wire [63:0] io_actv_ractive_vs_4 = _io_actv_ractive_vs_T_10[63:0]; // @[VDecodeInstruction.scala 109:48]
-  wire [75:0] _io_actv_ractive_vsm_T_19 = {ractivedi_b_hi,ractivedi_b_lo,12'h0}; // @[Cat.scala 31:58]
-  wire [63:0] io_actv_ractive_vsm_4 = m ? _io_actv_ractive_vsm_T_19[63:0] : 64'h0; // @[Library.scala 18:8]
-  wire [63:0] _io_actv_ractive_T_24 = io_actv_ractive_vs_4 | io_actv_ractive_vsm_4; // @[VDecodeInstruction.scala 113:8]
-  wire [63:0] _io_actv_ractive_T_25 = vsraqs ? _io_actv_ractive_T_24 : 64'h0; // @[Library.scala 18:8]
-  wire [63:0] _io_actv_ractive_T_26 = _io_actv_ractive_T_23 | _io_actv_ractive_T_25; // @[VDecodeInstruction.scala 673:80]
-  wire  _io_actv_ractive_T_29 = vmacc | vmadd | vst | vstq; // @[VDecodeInstruction.scala 675:33]
+  wire [63:0] _io_actv_ractive_T_7 = io_actv_ractive_vs | io_actv_ractive_vsm; // @[VDecodeInstruction.scala 81:8]
+  wire [63:0] _io_actv_ractive_T_8 = _io_actv_ractive_T_7 | io_actv_ractive_vt; // @[VDecodeInstruction.scala 81:14]
+  wire [63:0] _io_actv_ractive_T_9 = _io_actv_ractive_T_8 | io_actv_ractive_vtm; // @[VDecodeInstruction.scala 81:19]
+  wire [63:0] _io_actv_ractive_T_10 = _io_actv_ractive_T_6 ? _io_actv_ractive_T_9 : 64'h0; // @[Library.scala 18:8]
+  wire  _io_actv_ractive_T_11 = vsraqs | vsrans; // @[VDecodeInstruction.scala 600:18]
+  wire [64:0] _io_actv_ractive_vs_T_3 = {io_actv_ractive_vs,1'h0}; // @[Cat.scala 31:58]
+  wire [63:0] io_actv_ractive_vs_1 = _io_actv_ractive_vs_T_3[63:0]; // @[VDecodeInstruction.scala 86:48]
+  wire [67:0] _io_actv_ractive_vsm_T_6 = {ractivedi_b_hi,ractivedi_b_lo,4'h0}; // @[Cat.scala 31:58]
+  wire [63:0] io_actv_ractive_vsm_1 = m ? _io_actv_ractive_vsm_T_6[63:0] : 64'h0; // @[Library.scala 18:8]
+  wire [63:0] _io_actv_ractive_T_12 = io_actv_ractive_vs_1 | io_actv_ractive_vsm_1; // @[VDecodeInstruction.scala 90:8]
+  wire [63:0] _io_actv_ractive_T_13 = _io_actv_ractive_T_11 ? _io_actv_ractive_T_12 : 64'h0; // @[Library.scala 18:8]
+  wire [63:0] _io_actv_ractive_T_14 = _io_actv_ractive_T_10 | _io_actv_ractive_T_13; // @[VDecodeInstruction.scala 599:80]
+  wire [65:0] _io_actv_ractive_vs_T_6 = {io_actv_ractive_vs,2'h0}; // @[Cat.scala 31:58]
+  wire [63:0] io_actv_ractive_vs_2 = _io_actv_ractive_vs_T_6[63:0]; // @[VDecodeInstruction.scala 95:48]
+  wire [71:0] _io_actv_ractive_vsm_T_11 = {ractivedi_b_hi,ractivedi_b_lo,8'h0}; // @[Cat.scala 31:58]
+  wire [63:0] io_actv_ractive_vsm_2 = m ? _io_actv_ractive_vsm_T_11[63:0] : 64'h0; // @[Library.scala 18:8]
+  wire [63:0] _io_actv_ractive_T_15 = io_actv_ractive_vs_2 | io_actv_ractive_vsm_2; // @[VDecodeInstruction.scala 99:8]
+  wire [63:0] _io_actv_ractive_T_16 = vsraqs ? _io_actv_ractive_T_15 : 64'h0; // @[Library.scala 18:8]
+  wire [63:0] _io_actv_ractive_T_17 = _io_actv_ractive_T_14 | _io_actv_ractive_T_16; // @[VDecodeInstruction.scala 600:80]
+  wire [66:0] _io_actv_ractive_vs_T_9 = {io_actv_ractive_vs,3'h0}; // @[Cat.scala 31:58]
+  wire [63:0] io_actv_ractive_vs_3 = _io_actv_ractive_vs_T_9[63:0]; // @[VDecodeInstruction.scala 104:48]
+  wire [75:0] _io_actv_ractive_vsm_T_16 = {ractivedi_b_hi,ractivedi_b_lo,12'h0}; // @[Cat.scala 31:58]
+  wire [63:0] io_actv_ractive_vsm_3 = m ? _io_actv_ractive_vsm_T_16[63:0] : 64'h0; // @[Library.scala 18:8]
+  wire [63:0] _io_actv_ractive_T_18 = io_actv_ractive_vs_3 | io_actv_ractive_vsm_3; // @[VDecodeInstruction.scala 108:8]
+  wire [63:0] _io_actv_ractive_T_19 = vsraqs ? _io_actv_ractive_T_18 : 64'h0; // @[Library.scala 18:8]
+  wire [63:0] _io_actv_ractive_T_20 = _io_actv_ractive_T_17 | _io_actv_ractive_T_19; // @[VDecodeInstruction.scala 601:80]
+  wire  _io_actv_ractive_T_23 = vmacc | vmadd | vst | vstq; // @[VDecodeInstruction.scala 603:33]
   wire [63:0] io_actv_ractive_vd = 64'h1 << vdbits; // @[OneHot.scala 64:12]
   wire [63:0] io_actv_ractive_vdm = m ? wactivedw : 64'h0; // @[Library.scala 18:8]
-  wire [63:0] _io_actv_ractive_T_30 = io_actv_ractive_vd | io_actv_ractive_vdm; // @[VDecodeInstruction.scala 121:8]
-  wire [63:0] _io_actv_ractive_T_31 = _io_actv_ractive_T_29 ? _io_actv_ractive_T_30 : 64'h0; // @[Library.scala 18:8]
-  wire [63:0] _io_actv_ractive_T_32 = _io_actv_ractive_T_26 | _io_actv_ractive_T_31; // @[VDecodeInstruction.scala 674:80]
-  wire [63:0] _io_actv_ractive_T_33 = ra_vx | ra_vxm; // @[VDecodeInstruction.scala 129:8]
-  wire [63:0] _io_actv_ractive_T_34 = vfmadd4 ? _io_actv_ractive_T_33 : 64'h0; // @[Library.scala 18:8]
-  wire [63:0] _io_actv_ractive_T_35 = _io_actv_ractive_T_32 | _io_actv_ractive_T_34; // @[VDecodeInstruction.scala 675:80]
-  wire [63:0] _io_actv_ractive_T_36 = vadwconv ? ractivedw : 64'h0; // @[Library.scala 18:8]
-  wire [63:0] _io_actv_ractive_T_37 = _io_actv_ractive_T_35 | _io_actv_ractive_T_36; // @[VDecodeInstruction.scala 676:80]
-  wire [63:0] _io_actv_ractive_T_38 = adwinit ? ractivedi : 64'h0; // @[Library.scala 18:8]
-  wire [63:0] _io_actv_ractive_T_39 = _io_actv_ractive_T_37 | _io_actv_ractive_T_38; // @[VDecodeInstruction.scala 677:80]
-  wire [63:0] _io_actv_ractive_T_40 = vslideh2 ? ractivesl : 64'h0; // @[Library.scala 18:8]
-  wire [63:0] _io_actv_ractive_T_41 = _io_actv_ractive_T_39 | _io_actv_ractive_T_40; // @[VDecodeInstruction.scala 678:80]
-  wire  _io_actv_ractive_T_42 = aconv | actr; // @[VDecodeInstruction.scala 680:17]
-  wire [63:0] ractiveconv1 = _ractiveconv1_T_2[63:0]; // @[VDecodeInstruction.scala 557:26 571:18]
-  wire [63:0] _io_actv_ractive_T_43 = _io_actv_ractive_T_42 ? ractiveconv1 : 64'h0; // @[Library.scala 18:8]
-  wire [63:0] _io_actv_ractive_T_44 = _io_actv_ractive_T_41 | _io_actv_ractive_T_43; // @[VDecodeInstruction.scala 679:80]
-  wire [63:0] ractiveconv2 = _ractiveconv2_T_2[63:0]; // @[VDecodeInstruction.scala 558:26 572:18]
-  wire [63:0] _io_actv_ractive_T_45 = aconv ? ractiveconv2 : 64'h0; // @[Library.scala 18:8]
-  wire [63:0] _io_actv_ractive_T_46 = _io_actv_ractive_T_44 | _io_actv_ractive_T_45; // @[VDecodeInstruction.scala 680:80]
-  wire [63:0] ractiveaset = _ractiveaset_T_2[63:0]; // @[VDecodeInstruction.scala 559:26 573:18]
-  wire [63:0] _io_actv_ractive_T_47 = acset ? ractiveaset : 64'h0; // @[Library.scala 18:8]
-  wire  _io_actv_wactive_T_6 = _io_out_vt_valid_T_7 | vdup; // @[VDecodeInstruction.scala 685:71]
-  wire  _io_actv_wactive_T_8 = _io_actv_wactive_T_6 | vld | vfmadd4; // @[VDecodeInstruction.scala 686:23]
-  wire [63:0] _io_actv_wactive_T_10 = _io_actv_wactive_T_8 ? _io_actv_ractive_T_30 : 64'h0; // @[Library.scala 18:8]
-  wire  _io_actv_wactive_T_16 = vmvp | vmulw | vacc | vaddw | vsubw | vevnodd | vzip; // @[VDecodeInstruction.scala 687:62]
+  wire [63:0] _io_actv_ractive_T_24 = io_actv_ractive_vd | io_actv_ractive_vdm; // @[VDecodeInstruction.scala 116:8]
+  wire [63:0] _io_actv_ractive_T_25 = _io_actv_ractive_T_23 ? _io_actv_ractive_T_24 : 64'h0; // @[Library.scala 18:8]
+  wire [63:0] _io_actv_ractive_T_26 = _io_actv_ractive_T_20 | _io_actv_ractive_T_25; // @[VDecodeInstruction.scala 602:80]
+  wire [63:0] _io_actv_ractive_T_27 = vadwconv ? ractivedw : 64'h0; // @[Library.scala 18:8]
+  wire [63:0] _io_actv_ractive_T_28 = _io_actv_ractive_T_26 | _io_actv_ractive_T_27; // @[VDecodeInstruction.scala 603:80]
+  wire [63:0] _io_actv_ractive_T_29 = adwinit ? ractivedi : 64'h0; // @[Library.scala 18:8]
+  wire [63:0] _io_actv_ractive_T_30 = _io_actv_ractive_T_28 | _io_actv_ractive_T_29; // @[VDecodeInstruction.scala 604:80]
+  wire [63:0] _io_actv_ractive_T_31 = vslideh2 ? ractivesl : 64'h0; // @[Library.scala 18:8]
+  wire [63:0] _io_actv_ractive_T_32 = _io_actv_ractive_T_30 | _io_actv_ractive_T_31; // @[VDecodeInstruction.scala 605:80]
+  wire  _io_actv_ractive_T_33 = aconv | actr; // @[VDecodeInstruction.scala 607:17]
+  wire [63:0] ractiveconv1 = _ractiveconv1_T_2[63:0]; // @[VDecodeInstruction.scala 486:26 500:18]
+  wire [63:0] _io_actv_ractive_T_34 = _io_actv_ractive_T_33 ? ractiveconv1 : 64'h0; // @[Library.scala 18:8]
+  wire [63:0] _io_actv_ractive_T_35 = _io_actv_ractive_T_32 | _io_actv_ractive_T_34; // @[VDecodeInstruction.scala 606:80]
+  wire [63:0] ractiveconv2 = _ractiveconv2_T_2[63:0]; // @[VDecodeInstruction.scala 487:26 501:18]
+  wire [63:0] _io_actv_ractive_T_36 = aconv ? ractiveconv2 : 64'h0; // @[Library.scala 18:8]
+  wire [63:0] _io_actv_ractive_T_37 = _io_actv_ractive_T_35 | _io_actv_ractive_T_36; // @[VDecodeInstruction.scala 607:80]
+  wire [63:0] ractiveaset = _ractiveaset_T_2[63:0]; // @[VDecodeInstruction.scala 488:26 502:18]
+  wire [63:0] _io_actv_ractive_T_38 = acset ? ractiveaset : 64'h0; // @[Library.scala 18:8]
+  wire  _io_actv_wactive_T_5 = _io_out_vt_valid_T_6 | vdup; // @[VDecodeInstruction.scala 612:62]
+  wire  _io_actv_wactive_T_6 = _io_actv_wactive_T_5 | vld; // @[VDecodeInstruction.scala 613:16]
+  wire [63:0] _io_actv_wactive_T_8 = _io_actv_wactive_T_6 ? _io_actv_ractive_T_24 : 64'h0; // @[Library.scala 18:8]
+  wire  _io_actv_wactive_T_14 = vmvp | vmulw | vacc | vaddw | vsubw | vevnodd | vzip; // @[VDecodeInstruction.scala 614:62]
   wire [64:0] _io_actv_wactive_vd_T_3 = {io_actv_ractive_vd,1'h0}; // @[Cat.scala 31:58]
-  wire [63:0] io_actv_wactive_vd_1 = _io_actv_wactive_vd_T_3[63:0]; // @[VDecodeInstruction.scala 142:48]
+  wire [63:0] io_actv_wactive_vd_1 = _io_actv_wactive_vd_T_3[63:0]; // @[VDecodeInstruction.scala 137:48]
   wire [67:0] _io_actv_wactive_vdm_T_6 = {wactivedw_b_hi,wactivedw_b_lo,4'h0}; // @[Cat.scala 31:58]
   wire [63:0] io_actv_wactive_vdm_1 = m ? _io_actv_wactive_vdm_T_6[63:0] : 64'h0; // @[Library.scala 18:8]
-  wire [63:0] _io_actv_wactive_T_17 = io_actv_wactive_vd_1 | io_actv_wactive_vdm_1; // @[VDecodeInstruction.scala 146:8]
-  wire [63:0] _io_actv_wactive_T_18 = _io_actv_wactive_T_16 ? _io_actv_wactive_T_17 : 64'h0; // @[Library.scala 18:8]
-  wire [63:0] _io_actv_wactive_T_19 = _io_actv_wactive_T_10 | _io_actv_wactive_T_18; // @[VDecodeInstruction.scala 686:80]
-  wire [63:0] _io_actv_wactive_T_20 = vdwconv ? wactivedw : 64'h0; // @[Library.scala 18:8]
-  wire [63:0] _io_actv_wactive_T_21 = _io_actv_wactive_T_19 | _io_actv_wactive_T_20; // @[VDecodeInstruction.scala 688:80]
-  wire [63:0] wactiveconv = _wactiveconv_T_2[63:0]; // @[VDecodeInstruction.scala 560:26 574:18]
-  wire [63:0] _io_actv_wactive_T_22 = vcget ? wactiveconv : 64'h0; // @[Library.scala 18:8]
-  assign io_out_op = _op_T_206 | _op_T_207; // @[VDecodeInstruction.scala 535:38]
-  assign io_out_f2 = func2[2:0]; // @[VDecodeInstruction.scala 588:21]
+  wire [63:0] _io_actv_wactive_T_15 = io_actv_wactive_vd_1 | io_actv_wactive_vdm_1; // @[VDecodeInstruction.scala 141:8]
+  wire [63:0] _io_actv_wactive_T_16 = _io_actv_wactive_T_14 ? _io_actv_wactive_T_15 : 64'h0; // @[Library.scala 18:8]
+  wire [63:0] _io_actv_wactive_T_17 = _io_actv_wactive_T_8 | _io_actv_wactive_T_16; // @[VDecodeInstruction.scala 613:80]
+  wire [63:0] _io_actv_wactive_T_18 = vdwconv ? wactivedw : 64'h0; // @[Library.scala 18:8]
+  wire [63:0] _io_actv_wactive_T_19 = _io_actv_wactive_T_17 | _io_actv_wactive_T_18; // @[VDecodeInstruction.scala 615:80]
+  wire [63:0] wactiveconv = _wactiveconv_T_2[63:0]; // @[VDecodeInstruction.scala 489:26 503:18]
+  wire [63:0] _io_actv_wactive_T_20 = vcget ? wactiveconv : 64'h0; // @[Library.scala 18:8]
+  assign io_out_op = _op_T_148 | _op_T_149; // @[VDecodeInstruction.scala 464:38]
+  assign io_out_f2 = func2[2:0]; // @[VDecodeInstruction.scala 517:21]
   assign io_out_sz = {io_out_sz_hi,_io_out_sz_T_2}; // @[Cat.scala 31:58]
-  assign io_out_m = m & ~vdmulh2 & ~vmul2 & ~vmulh2 & ~vmulhu2 & ~vmuls2 & ~vmv2 & ~vslidehn2 & ~vslidehp2; // @[VDecodeInstruction.scala 590:97]
-  assign io_out_vd_valid = vdwconv | vfmt0 | vfmt1 | vfmt2 | vfmt3 | vfmt4 | vfmt5 | vfmt6 | vld | vdup | vfmadd4 |
-    vcget; // @[VDecodeInstruction.scala 593:119]
+  assign io_out_m = m & ~vdmulh2 & ~vmul2 & ~vmulh2 & ~vmulhu2 & ~vmuls2 & ~vmv2 & ~vslidehn2 & ~vslidehp2; // @[VDecodeInstruction.scala 519:97]
+  assign io_out_vd_valid = vdwconv | vfmt0 | vfmt1 | vfmt2 | vfmt3 | vfmt4 | vfmt6 | vld | vdup | vcget; // @[VDecodeInstruction.scala 522:99]
   assign io_out_vd_addr = io_in_inst[11:6]; // @[VDecodeInstruction.scala 34:20]
-  assign io_out_ve_addr = vodd ? vdbits : _io_out_ve_addr_T_15; // @[VDecodeInstruction.scala 606:24]
-  assign io_out_vf_addr = vdbits + 6'h2; // @[VDecodeInstruction.scala 609:28]
-  assign io_out_vg_addr = vdbits + 6'h3; // @[VDecodeInstruction.scala 610:28]
-  assign io_out_vs_valid = vadwconv | adwinit | vfmt0 | vfmt1 | vfmt2 | vfmt3 | vfmt4 | vfmt5 | vfmt6 | vst | vstq |
-    vfmadd4 | aconv; // @[VDecodeInstruction.scala 597:131]
-  assign io_out_vs_addr = vadwconv ? vsdw : _io_out_vs_addr_T_3; // @[VDecodeInstruction.scala 611:24]
-  assign io_out_vt_valid = _io_out_vs_valid_T | vfmadd4_bit_30 & (vfmt0 | vfmt1 | vfmt2 | vfmt3 | vfmt4 | vfmt5 | vfmt6)
-     | ~x3 & vfmadd4; // @[VDecodeInstruction.scala 598:113]
-  assign io_out_vt_addr = vadwconv ? vtdw : _io_out_vt_addr_T_7; // @[VDecodeInstruction.scala 615:24]
+  assign io_out_ve_addr = vodd ? vdbits : _io_out_ve_addr_T_15; // @[VDecodeInstruction.scala 535:24]
+  assign io_out_vf_addr = vdbits + 6'h2; // @[VDecodeInstruction.scala 538:28]
+  assign io_out_vg_addr = vdbits + 6'h3; // @[VDecodeInstruction.scala 539:28]
+  assign io_out_vs_valid = vadwconv | adwinit | vfmt0 | vfmt1 | vfmt2 | vfmt3 | vfmt4 | vfmt6 | vst | vstq | aconv; // @[VDecodeInstruction.scala 526:111]
+  assign io_out_vs_addr = vadwconv ? vsdw : _io_out_vs_addr_T_3; // @[VDecodeInstruction.scala 540:24]
+  assign io_out_vt_valid = _io_out_vs_valid_T | aconv_bit_30 & (vfmt0 | vfmt1 | vfmt2 | vfmt3 | vfmt4 | vfmt6); // @[VDecodeInstruction.scala 527:42]
+  assign io_out_vt_addr = vadwconv ? vtdw : _io_out_vt_addr_T_7; // @[VDecodeInstruction.scala 544:24]
   assign io_out_vu_valid = vadwconv | vdmulh2 | vmul2 | vmulh2 | vmulhu2 | vmuls2 | vmv2 | vacc | vadd3 | vmacc | vmadd
-     | aconv | vsrans | vsraqs | vfmadd4 | vsel | vslideh2 | m & vevn3; // @[VDecodeInstruction.scala 599:185]
-  assign io_out_vu_addr = vadwconv ? vudw : _io_out_vu_addr_T_26; // @[VDecodeInstruction.scala 620:24]
-  assign io_out_vx_valid = _io_out_vs_valid_T | vdmulh2 | vmul2 | vmulh2 | vmulhu2 | vmuls2 | vmv2 | vslideh2 | vsraqs; // @[VDecodeInstruction.scala 600:113]
-  assign io_out_vx_addr = vadwconv ? func2 : _io_out_vx_addr_T_14; // @[VDecodeInstruction.scala 629:24]
-  assign io_out_vy_valid = _io_out_vs_valid_T | vslideh2 | vfmadd4_bit_30 & vsraqs; // @[VDecodeInstruction.scala 601:54]
-  assign io_out_vy_addr = vadwconv ? vydw : _io_out_vy_addr_T_3; // @[VDecodeInstruction.scala 633:24]
-  assign io_out_vz_valid = _io_out_vu_valid_T_5 | vslideh2 | vsraqs; // @[VDecodeInstruction.scala 602:102]
-  assign io_out_vz_addr = vadwconv ? vzdw : _io_out_vz_addr_T_13; // @[VDecodeInstruction.scala 637:24]
-  assign io_out_sv_valid = x & (vdup | vfmt0 | vfmt1 | vfmt2 | vfmt3 | vfmt4 | vfmt5 | vfmt6) | x3 & vfmadd4; // @[VDecodeInstruction.scala 603:97]
-  assign io_out_sv_addr = io_in_addr; // @[VDecodeInstruction.scala 649:18]
-  assign io_out_sv_data = vldstdec ? io_in_data : _io_out_sv_data_T_38; // @[VDecodeInstruction.scala 650:24]
-  assign io_out_cmdsync = adwinit | vadwconv | vdmulh2 | vmul2 | vmulh2 | vmulhu2 | vmuls2 | vmv2 | vslideh2 | vsraqs; // @[VDecodeInstruction.scala 591:112]
-  assign io_cmdq_alu = _io_out_sv_valid_T_6 | vfmadd4 | vadwconv | adwinit; // @[VDecodeInstruction.scala 659:110]
-  assign io_cmdq_conv = aconv | vcget | acset | actr; // @[VDecodeInstruction.scala 660:43]
-  assign io_cmdq_ldst = vldst & ~uncached; // @[VDecodeInstruction.scala 661:25]
-  assign io_cmdq_ld = vld & uncached; // @[VDecodeInstruction.scala 662:21]
-  assign io_cmdq_st = (vst | vstq) & uncached; // @[VDecodeInstruction.scala 663:31]
-  assign io_actv_ractive = _io_actv_ractive_T_46 | _io_actv_ractive_T_47; // @[VDecodeInstruction.scala 681:80]
-  assign io_actv_wactive = _io_actv_wactive_T_21 | _io_actv_wactive_T_22; // @[VDecodeInstruction.scala 689:80]
-  assign io_undef = ~undef_value_6_0; // @[VDecodeInstruction.scala 416:15]
+     | aconv | vsrans | vsraqs | vsel | vslideh2 | m & vevn3; // @[VDecodeInstruction.scala 528:174]
+  assign io_out_vu_addr = vadwconv ? vudw : _io_out_vu_addr_T_26; // @[VDecodeInstruction.scala 549:24]
+  assign io_out_vx_valid = _io_out_vs_valid_T | vdmulh2 | vmul2 | vmulh2 | vmulhu2 | vmuls2 | vmv2 | vslideh2 | vsraqs; // @[VDecodeInstruction.scala 529:113]
+  assign io_out_vx_addr = vadwconv ? func2 : _io_out_vx_addr_T_14; // @[VDecodeInstruction.scala 558:24]
+  assign io_out_vy_valid = _io_out_vs_valid_T | vslideh2 | aconv_bit_30 & vsraqs; // @[VDecodeInstruction.scala 530:54]
+  assign io_out_vy_addr = vadwconv ? vydw : _io_out_vy_addr_T_3; // @[VDecodeInstruction.scala 562:24]
+  assign io_out_vz_valid = _io_out_vu_valid_T_5 | vslideh2 | vsraqs; // @[VDecodeInstruction.scala 531:102]
+  assign io_out_vz_addr = vadwconv ? vzdw : _io_out_vz_addr_T_13; // @[VDecodeInstruction.scala 566:24]
+  assign io_out_sv_valid = x & (vdup | vfmt0 | vfmt1 | vfmt2 | vfmt3 | vfmt4 | vfmt6); // @[VDecodeInstruction.scala 532:24]
+  assign io_out_sv_addr = io_in_addr; // @[VDecodeInstruction.scala 578:18]
+  assign io_out_sv_data = vldstdec ? io_in_data : _io_out_sv_data_T_38; // @[VDecodeInstruction.scala 579:24]
+  assign io_out_cmdsync = adwinit | vadwconv | vdmulh2 | vmul2 | vmulh2 | vmulhu2 | vmuls2 | vmv2 | vslideh2 | vsraqs; // @[VDecodeInstruction.scala 520:112]
+  assign io_cmdq_alu = _io_out_sv_valid_T_5 | vadwconv | adwinit; // @[VDecodeInstruction.scala 588:90]
+  assign io_cmdq_conv = aconv | vcget | acset | actr; // @[VDecodeInstruction.scala 589:43]
+  assign io_cmdq_ldst = vldst & ~uncached; // @[VDecodeInstruction.scala 590:25]
+  assign io_cmdq_ld = vld & uncached; // @[VDecodeInstruction.scala 591:21]
+  assign io_cmdq_st = (vst | vstq) & uncached; // @[VDecodeInstruction.scala 592:31]
+  assign io_actv_ractive = _io_actv_ractive_T_37 | _io_actv_ractive_T_38; // @[VDecodeInstruction.scala 608:80]
+  assign io_actv_wactive = _io_actv_wactive_T_19 | _io_actv_wactive_T_20; // @[VDecodeInstruction.scala 616:80]
+  assign io_undef = ~undef_value_6_0; // @[VDecodeInstruction.scala 375:15]
   always @(posedge clock) begin
     `ifndef SYNTHESIS
     `ifdef STOP_COND
       if (`STOP_COND) begin
     `endif
         if (~reset & ~(~(vdup & vldstdec))) begin
-          $fatal; // @[VDecodeInstruction.scala 238:9]
+          $fatal; // @[VDecodeInstruction.scala 233:9]
         end
     `ifdef STOP_COND
       end
@@ -37556,7 +27998,7 @@
       if (`PRINTF_COND) begin
     `endif
         if (~reset & ~(~(vdup & vldstdec))) begin
-          $fwrite(32'h80000002,"Assertion failed\n    at VDecodeInstruction.scala:238 assert(!(vdup && vldstdec))\n"); // @[VDecodeInstruction.scala 238:9]
+          $fwrite(32'h80000002,"Assertion failed\n    at VDecodeInstruction.scala:233 assert(!(vdup && vldstdec))\n"); // @[VDecodeInstruction.scala 233:9]
         end
     `ifdef PRINTF_COND
       end
@@ -37566,8 +28008,8 @@
     `ifdef STOP_COND
       if (`STOP_COND) begin
     `endif
-        if (_T_3 & ~(_T_320 == 7'h1)) begin
-          $fatal; // @[VDecodeInstruction.scala 417:9]
+        if (_T_3 & ~(_T_233 == 7'h1)) begin
+          $fatal; // @[VDecodeInstruction.scala 376:9]
         end
     `ifdef STOP_COND
       end
@@ -37577,9 +28019,9 @@
     `ifdef PRINTF_COND
       if (`PRINTF_COND) begin
     `endif
-        if (_T_3 & ~(_T_320 == 7'h1)) begin
+        if (_T_3 & ~(_T_233 == 7'h1)) begin
           $fwrite(32'h80000002,
-            "Assertion failed\n    at VDecodeInstruction.scala:417 assert(PopCount(Cat(vopbits, undef)) === 1.U)\n"); // @[VDecodeInstruction.scala 417:9]
+            "Assertion failed\n    at VDecodeInstruction.scala:376 assert(PopCount(Cat(vopbits, undef)) === 1.U)\n"); // @[VDecodeInstruction.scala 376:9]
         end
     `ifdef PRINTF_COND
       end
@@ -37589,8 +28031,8 @@
     `ifdef STOP_COND
       if (`STOP_COND) begin
     `endif
-        if (_T_3 & ~(_T_331[1:0] <= 2'h1)) begin
-          $fatal; // @[VDecodeInstruction.scala 654:9]
+        if (_T_3 & ~(_T_244[1:0] <= 2'h1)) begin
+          $fatal; // @[VDecodeInstruction.scala 583:9]
         end
     `ifdef STOP_COND
       end
@@ -37600,9 +28042,9 @@
     `ifdef PRINTF_COND
       if (`PRINTF_COND) begin
     `endif
-        if (_T_3 & ~(_T_331[1:0] <= 2'h1)) begin
+        if (_T_3 & ~(_T_244[1:0] <= 2'h1)) begin
           $fwrite(32'h80000002,
-            "Assertion failed\n    at VDecodeInstruction.scala:654 assert(PopCount(io.out.sz) <= 1.U)\n"); // @[VDecodeInstruction.scala 654:9]
+            "Assertion failed\n    at VDecodeInstruction.scala:583 assert(PopCount(io.out.sz) <= 1.U)\n"); // @[VDecodeInstruction.scala 583:9]
         end
     `ifdef PRINTF_COND
       end
@@ -37613,7 +28055,7 @@
       if (`STOP_COND) begin
     `endif
         if (_T_3 & ~(~(io_out_vx_valid & ~io_out_cmdsync))) begin
-          $fatal; // @[VDecodeInstruction.scala 655:9]
+          $fatal; // @[VDecodeInstruction.scala 584:9]
         end
     `ifdef STOP_COND
       end
@@ -37625,7 +28067,7 @@
     `endif
         if (_T_3 & ~(~(io_out_vx_valid & ~io_out_cmdsync))) begin
           $fwrite(32'h80000002,
-            "Assertion failed\n    at VDecodeInstruction.scala:655 assert(!(io.out.vx.valid && !io.out.cmdsync))\n"); // @[VDecodeInstruction.scala 655:9]
+            "Assertion failed\n    at VDecodeInstruction.scala:584 assert(!(io.out.vx.valid && !io.out.cmdsync))\n"); // @[VDecodeInstruction.scala 584:9]
         end
     `ifdef PRINTF_COND
       end
@@ -37635,8 +28077,8 @@
     `ifdef STOP_COND
       if (`STOP_COND) begin
     `endif
-        if (_T_3 & ~(~(io_out_vy_valid & _T_337))) begin
-          $fatal; // @[VDecodeInstruction.scala 656:9]
+        if (_T_3 & ~(~(io_out_vy_valid & _T_250))) begin
+          $fatal; // @[VDecodeInstruction.scala 585:9]
         end
     `ifdef STOP_COND
       end
@@ -37646,9 +28088,9 @@
     `ifdef PRINTF_COND
       if (`PRINTF_COND) begin
     `endif
-        if (_T_3 & ~(~(io_out_vy_valid & _T_337))) begin
+        if (_T_3 & ~(~(io_out_vy_valid & _T_250))) begin
           $fwrite(32'h80000002,
-            "Assertion failed\n    at VDecodeInstruction.scala:656 assert(!(io.out.vy.valid && !io.out.cmdsync))\n"); // @[VDecodeInstruction.scala 656:9]
+            "Assertion failed\n    at VDecodeInstruction.scala:585 assert(!(io.out.vy.valid && !io.out.cmdsync))\n"); // @[VDecodeInstruction.scala 585:9]
         end
     `ifdef PRINTF_COND
       end
@@ -37658,8 +28100,8 @@
     `ifdef STOP_COND
       if (`STOP_COND) begin
     `endif
-        if (_T_3 & ~(~(io_out_vz_valid & _T_337))) begin
-          $fatal; // @[VDecodeInstruction.scala 657:9]
+        if (_T_3 & ~(~(io_out_vz_valid & _T_250))) begin
+          $fatal; // @[VDecodeInstruction.scala 586:9]
         end
     `ifdef STOP_COND
       end
@@ -37669,9 +28111,9 @@
     `ifdef PRINTF_COND
       if (`PRINTF_COND) begin
     `endif
-        if (_T_3 & ~(~(io_out_vz_valid & _T_337))) begin
+        if (_T_3 & ~(~(io_out_vz_valid & _T_250))) begin
           $fwrite(32'h80000002,
-            "Assertion failed\n    at VDecodeInstruction.scala:657 assert(!(io.out.vz.valid && !io.out.cmdsync))\n"); // @[VDecodeInstruction.scala 657:9]
+            "Assertion failed\n    at VDecodeInstruction.scala:586 assert(!(io.out.vz.valid && !io.out.cmdsync))\n"); // @[VDecodeInstruction.scala 586:9]
         end
     `ifdef PRINTF_COND
       end
@@ -37681,8 +28123,8 @@
     `ifdef STOP_COND
       if (`STOP_COND) begin
     `endif
-        if (_T_3 & ~(_T_369 == 3'h1)) begin
-          $fatal; // @[VDecodeInstruction.scala 666:9]
+        if (_T_3 & ~(_T_282 == 3'h1)) begin
+          $fatal; // @[VDecodeInstruction.scala 595:9]
         end
     `ifdef STOP_COND
       end
@@ -37692,9 +28134,9 @@
     `ifdef PRINTF_COND
       if (`PRINTF_COND) begin
     `endif
-        if (_T_3 & ~(_T_369 == 3'h1)) begin
+        if (_T_3 & ~(_T_282 == 3'h1)) begin
           $fwrite(32'h80000002,
-            "Assertion failed\n    at VDecodeInstruction.scala:666 assert(PopCount(cmdqchk) === 1.U)\n"); // @[VDecodeInstruction.scala 666:9]
+            "Assertion failed\n    at VDecodeInstruction.scala:595 assert(PopCount(cmdqchk) === 1.U)\n"); // @[VDecodeInstruction.scala 595:9]
         end
     `ifdef PRINTF_COND
       end
@@ -50704,28 +41146,28 @@
   reg  value_tin_cmdsync; // @[VCmdq.scala 37:18]
   reg  value_m; // @[VCmdq.scala 37:18]
   reg [4:0] step; // @[VCmdq.scala 42:21]
-  wire  vevnodd = value_tin_op == 7'h5d | value_tin_op == 7'h5e | value_tin_op == 7'h5f; // @[VAlu.scala 221:60]
-  wire  vzip = value_tin_op == 7'h60; // @[VAlu.scala 222:22]
-  wire  _last_T = ~value_m; // @[VAlu.scala 224:16]
-  wire  last = ~value_m | step == 5'h3; // @[VAlu.scala 224:19]
-  wire [5:0] _out_vd_addr_T_1 = value_tin_vd_addr + 6'h1; // @[VAlu.scala 226:31]
-  wire [5:0] _out_ve_addr_T_1 = value_tin_ve_addr + 6'h1; // @[VAlu.scala 227:31]
-  wire [5:0] _out_vs_addr_T_1 = value_tin_vs_addr + 6'h1; // @[VAlu.scala 228:31]
-  wire [5:0] _out_vt_addr_T_1 = value_tin_vt_addr + 6'h1; // @[VAlu.scala 229:31]
-  wire [5:0] _out_vu_addr_T_1 = value_tin_vu_addr + 6'h1; // @[VAlu.scala 230:31]
-  wire [6:0] _out_vs_addr_T_2 = {{1'd0}, value_tin_vu_addr}; // @[VAlu.scala 234:35]
-  wire [5:0] _out_vs_addr_T_5 = value_tin_vs_addr + 6'h2; // @[VAlu.scala 237:35]
-  wire [5:0] _out_vt_addr_T_5 = value_tin_vt_addr + 6'h2; // @[VAlu.scala 238:35]
-  wire [5:0] _GEN_0 = step == 5'h1 ? _out_vs_addr_T_2[5:0] : _out_vs_addr_T_5; // @[VAlu.scala 233:27 234:21 237:21]
-  wire [5:0] _GEN_1 = step == 5'h1 ? _out_vu_addr_T_1 : _out_vt_addr_T_5; // @[VAlu.scala 233:27 235:21 238:21]
-  wire [5:0] tin_vu_addr = value_m & vevnodd ? value_tin_vu_addr : _out_vu_addr_T_1; // @[VAlu.scala 230:17 231:25 232:19]
-  wire [5:0] tin_vs_addr = value_m & vevnodd ? _GEN_0 : _out_vs_addr_T_1; // @[VAlu.scala 228:17 231:25]
-  wire [5:0] tin_vt_addr = value_m & vevnodd ? _GEN_1 : _out_vt_addr_T_1; // @[VAlu.scala 229:17 231:25]
-  wire  _T_6 = ~reset; // @[VAlu.scala 242:13]
-  wire [5:0] _out_vd_addr_T_3 = value_tin_vd_addr + 6'h2; // @[VAlu.scala 243:33]
-  wire [5:0] _out_ve_addr_T_3 = value_tin_ve_addr + 6'h2; // @[VAlu.scala 244:33]
-  wire [5:0] tin_vd_addr = vzip ? _out_vd_addr_T_3 : _out_vd_addr_T_1; // @[VAlu.scala 226:17 241:17 243:19]
-  wire [5:0] tin_ve_addr = vzip ? _out_ve_addr_T_3 : _out_ve_addr_T_1; // @[VAlu.scala 227:17 241:17 244:19]
+  wire  vevnodd = value_tin_op == 7'h41 | value_tin_op == 7'h42 | value_tin_op == 7'h43; // @[VAlu.scala 201:60]
+  wire  vzip = value_tin_op == 7'h44; // @[VAlu.scala 202:22]
+  wire  _last_T = ~value_m; // @[VAlu.scala 204:16]
+  wire  last = ~value_m | step == 5'h3; // @[VAlu.scala 204:19]
+  wire [5:0] _out_vd_addr_T_1 = value_tin_vd_addr + 6'h1; // @[VAlu.scala 206:31]
+  wire [5:0] _out_ve_addr_T_1 = value_tin_ve_addr + 6'h1; // @[VAlu.scala 207:31]
+  wire [5:0] _out_vs_addr_T_1 = value_tin_vs_addr + 6'h1; // @[VAlu.scala 208:31]
+  wire [5:0] _out_vt_addr_T_1 = value_tin_vt_addr + 6'h1; // @[VAlu.scala 209:31]
+  wire [5:0] _out_vu_addr_T_1 = value_tin_vu_addr + 6'h1; // @[VAlu.scala 210:31]
+  wire [6:0] _out_vs_addr_T_2 = {{1'd0}, value_tin_vu_addr}; // @[VAlu.scala 214:35]
+  wire [5:0] _out_vs_addr_T_5 = value_tin_vs_addr + 6'h2; // @[VAlu.scala 217:35]
+  wire [5:0] _out_vt_addr_T_5 = value_tin_vt_addr + 6'h2; // @[VAlu.scala 218:35]
+  wire [5:0] _GEN_0 = step == 5'h1 ? _out_vs_addr_T_2[5:0] : _out_vs_addr_T_5; // @[VAlu.scala 213:27 214:21 217:21]
+  wire [5:0] _GEN_1 = step == 5'h1 ? _out_vu_addr_T_1 : _out_vt_addr_T_5; // @[VAlu.scala 213:27 215:21 218:21]
+  wire [5:0] tin_vu_addr = value_m & vevnodd ? value_tin_vu_addr : _out_vu_addr_T_1; // @[VAlu.scala 210:17 211:25 212:19]
+  wire [5:0] tin_vs_addr = value_m & vevnodd ? _GEN_0 : _out_vs_addr_T_1; // @[VAlu.scala 208:17 211:25]
+  wire [5:0] tin_vt_addr = value_m & vevnodd ? _GEN_1 : _out_vt_addr_T_1; // @[VAlu.scala 209:17 211:25]
+  wire  _T_6 = ~reset; // @[VAlu.scala 222:13]
+  wire [5:0] _out_vd_addr_T_3 = value_tin_vd_addr + 6'h2; // @[VAlu.scala 223:33]
+  wire [5:0] _out_ve_addr_T_3 = value_tin_ve_addr + 6'h2; // @[VAlu.scala 224:33]
+  wire [5:0] tin_vd_addr = vzip ? _out_vd_addr_T_3 : _out_vd_addr_T_1; // @[VAlu.scala 206:17 221:17 223:19]
+  wire [5:0] tin_ve_addr = vzip ? _out_ve_addr_T_3 : _out_ve_addr_T_1; // @[VAlu.scala 207:17 221:17 224:19]
   wire  _T_9 = io_out_valid & io_out_ready; // @[VCmdq.scala 65:29]
   wire  _T_10 = ~last; // @[VCmdq.scala 66:11]
   wire [4:0] _step_T_1 = step + 5'h1; // @[VCmdq.scala 70:20]
@@ -50852,7 +41294,7 @@
   wire [63:0] _active_active_active_T_59 = _active_active_active_T_58 ? active_active_oh3_1 : 64'h0; // @[Library.scala 18:8]
   wire [63:0] active_active_active_1 = _active_active_active_T_52 | _active_active_active_T_59; // @[VCommon.scala 93:68]
   wire [63:0] _active_active_T_9 = f_io_in_bits_0_bits_tin_vt_valid ? active_active_active_1 : 64'h0; // @[Library.scala 8:8]
-  wire [63:0] _active_active_T_10 = _active_active_T_4 | _active_active_T_9; // @[VAlu.scala 253:74]
+  wire [63:0] _active_active_T_10 = _active_active_T_4 | _active_active_T_9; // @[VAlu.scala 233:74]
   wire [3:0] active_active_oh_shiftAmount_2 = f_io_in_bits_0_bits_tin_vu_addr[5:2]; // @[VCommon.scala 13:27]
   wire [15:0] active_active_oh_2 = 16'h1 << active_active_oh_shiftAmount_2; // @[OneHot.scala 64:12]
   wire [15:0] active_active_oh0_lo_lo_2 = {3'h0,active_active_oh_2[3],3'h0,active_active_oh_2[2],3'h0,active_active_oh_2
@@ -50908,7 +41350,7 @@
   wire [63:0] _active_active_active_T_89 = _active_active_active_T_88 ? active_active_oh3_2 : 64'h0; // @[Library.scala 18:8]
   wire [63:0] active_active_active_2 = _active_active_active_T_82 | _active_active_active_T_89; // @[VCommon.scala 93:68]
   wire [63:0] _active_active_T_15 = f_io_in_bits_0_bits_tin_vu_valid ? active_active_active_2 : 64'h0; // @[Library.scala 8:8]
-  wire [63:0] active_active = _active_active_T_10 | _active_active_T_15; // @[VAlu.scala 254:74]
+  wire [63:0] active_active = _active_active_T_10 | _active_active_T_15; // @[VAlu.scala 234:74]
   wire [63:0] _active_T_5 = fvalid[0] ? active_active : 64'h0; // @[Library.scala 8:8]
   wire [3:0] active_active_oh_shiftAmount_3 = f_io_in_bits_1_bits_tin_vs_addr[5:2]; // @[VCommon.scala 13:27]
   wire [15:0] active_active_oh_3 = 16'h1 << active_active_oh_shiftAmount_3; // @[OneHot.scala 64:12]
@@ -51028,7 +41470,7 @@
   wire [63:0] _active_active_active_T_149 = _active_active_active_T_148 ? active_active_oh3_4 : 64'h0; // @[Library.scala 18:8]
   wire [63:0] active_active_active_4 = _active_active_active_T_142 | _active_active_active_T_149; // @[VCommon.scala 93:68]
   wire [63:0] _active_active_T_25 = f_io_in_bits_1_bits_tin_vt_valid ? active_active_active_4 : 64'h0; // @[Library.scala 8:8]
-  wire [63:0] _active_active_T_26 = _active_active_T_20 | _active_active_T_25; // @[VAlu.scala 253:74]
+  wire [63:0] _active_active_T_26 = _active_active_T_20 | _active_active_T_25; // @[VAlu.scala 233:74]
   wire [3:0] active_active_oh_shiftAmount_5 = f_io_in_bits_1_bits_tin_vu_addr[5:2]; // @[VCommon.scala 13:27]
   wire [15:0] active_active_oh_5 = 16'h1 << active_active_oh_shiftAmount_5; // @[OneHot.scala 64:12]
   wire [15:0] active_active_oh0_lo_lo_5 = {3'h0,active_active_oh_5[3],3'h0,active_active_oh_5[2],3'h0,active_active_oh_5
@@ -51087,7 +41529,7 @@
   wire [63:0] _active_active_active_T_179 = _active_active_active_T_178 ? active_active_oh3_5 : 64'h0; // @[Library.scala 18:8]
   wire [63:0] active_active_active_5 = _active_active_active_T_172 | _active_active_active_T_179; // @[VCommon.scala 93:68]
   wire [63:0] _active_active_T_31 = f_io_in_bits_1_bits_tin_vu_valid ? active_active_active_5 : 64'h0; // @[Library.scala 8:8]
-  wire [63:0] active_active_1 = _active_active_T_26 | _active_active_T_31; // @[VAlu.scala 254:74]
+  wire [63:0] active_active_1 = _active_active_T_26 | _active_active_T_31; // @[VAlu.scala 234:74]
   wire [63:0] _active_T_11 = fvalid[1] ? active_active_1 : 64'h0; // @[Library.scala 8:8]
   wire [63:0] _active_T_12 = _active_T_5 | _active_T_11; // @[VCmdq.scala 108:90]
   wire [3:0] active_active_oh_shiftAmount_6 = f_io_in_bits_2_bits_tin_vs_addr[5:2]; // @[VCommon.scala 13:27]
@@ -51208,7 +41650,7 @@
   wire [63:0] _active_active_active_T_239 = _active_active_active_T_238 ? active_active_oh3_7 : 64'h0; // @[Library.scala 18:8]
   wire [63:0] active_active_active_7 = _active_active_active_T_232 | _active_active_active_T_239; // @[VCommon.scala 93:68]
   wire [63:0] _active_active_T_41 = f_io_in_bits_2_bits_tin_vt_valid ? active_active_active_7 : 64'h0; // @[Library.scala 8:8]
-  wire [63:0] _active_active_T_42 = _active_active_T_36 | _active_active_T_41; // @[VAlu.scala 253:74]
+  wire [63:0] _active_active_T_42 = _active_active_T_36 | _active_active_T_41; // @[VAlu.scala 233:74]
   wire [3:0] active_active_oh_shiftAmount_8 = f_io_in_bits_2_bits_tin_vu_addr[5:2]; // @[VCommon.scala 13:27]
   wire [15:0] active_active_oh_8 = 16'h1 << active_active_oh_shiftAmount_8; // @[OneHot.scala 64:12]
   wire [15:0] active_active_oh0_lo_lo_8 = {3'h0,active_active_oh_8[3],3'h0,active_active_oh_8[2],3'h0,active_active_oh_8
@@ -51267,7 +41709,7 @@
   wire [63:0] _active_active_active_T_269 = _active_active_active_T_268 ? active_active_oh3_8 : 64'h0; // @[Library.scala 18:8]
   wire [63:0] active_active_active_8 = _active_active_active_T_262 | _active_active_active_T_269; // @[VCommon.scala 93:68]
   wire [63:0] _active_active_T_47 = f_io_in_bits_2_bits_tin_vu_valid ? active_active_active_8 : 64'h0; // @[Library.scala 8:8]
-  wire [63:0] active_active_2 = _active_active_T_42 | _active_active_T_47; // @[VAlu.scala 254:74]
+  wire [63:0] active_active_2 = _active_active_T_42 | _active_active_T_47; // @[VAlu.scala 234:74]
   wire [63:0] _active_T_18 = fvalid[2] ? active_active_2 : 64'h0; // @[Library.scala 8:8]
   wire [63:0] _active_T_19 = _active_T_12 | _active_T_18; // @[VCmdq.scala 109:90]
   wire [3:0] active_active_oh_shiftAmount_9 = f_io_in_bits_3_bits_tin_vs_addr[5:2]; // @[VCommon.scala 13:27]
@@ -51388,7 +41830,7 @@
   wire [63:0] _active_active_active_T_329 = _active_active_active_T_328 ? active_active_oh3_10 : 64'h0; // @[Library.scala 18:8]
   wire [63:0] active_active_active_10 = _active_active_active_T_322 | _active_active_active_T_329; // @[VCommon.scala 93:68]
   wire [63:0] _active_active_T_57 = f_io_in_bits_3_bits_tin_vt_valid ? active_active_active_10 : 64'h0; // @[Library.scala 8:8]
-  wire [63:0] _active_active_T_58 = _active_active_T_52 | _active_active_T_57; // @[VAlu.scala 253:74]
+  wire [63:0] _active_active_T_58 = _active_active_T_52 | _active_active_T_57; // @[VAlu.scala 233:74]
   wire [3:0] active_active_oh_shiftAmount_11 = f_io_in_bits_3_bits_tin_vu_addr[5:2]; // @[VCommon.scala 13:27]
   wire [15:0] active_active_oh_11 = 16'h1 << active_active_oh_shiftAmount_11; // @[OneHot.scala 64:12]
   wire [15:0] active_active_oh0_lo_lo_11 = {3'h0,active_active_oh_11[3],3'h0,active_active_oh_11[2],3'h0,
@@ -51447,7 +41889,7 @@
   wire [63:0] _active_active_active_T_359 = _active_active_active_T_358 ? active_active_oh3_11 : 64'h0; // @[Library.scala 18:8]
   wire [63:0] active_active_active_11 = _active_active_active_T_352 | _active_active_active_T_359; // @[VCommon.scala 93:68]
   wire [63:0] _active_active_T_63 = f_io_in_bits_3_bits_tin_vu_valid ? active_active_active_11 : 64'h0; // @[Library.scala 8:8]
-  wire [63:0] active_active_3 = _active_active_T_58 | _active_active_T_63; // @[VAlu.scala 254:74]
+  wire [63:0] active_active_3 = _active_active_T_58 | _active_active_T_63; // @[VAlu.scala 234:74]
   wire [63:0] _active_T_25 = fvalid[3] ? active_active_3 : 64'h0; // @[Library.scala 8:8]
   wire [63:0] _active_T_26 = _active_T_19 | _active_T_25; // @[VCmdq.scala 110:90]
   wire [3:0] active_active_active_oh_shiftAmount = f_io_entry_0_bits_tin_vs_addr[5:2]; // @[VCommon.scala 13:27]
@@ -51594,7 +42036,7 @@
     ; // @[Library.scala 18:8]
   wire [63:0] active_active_active_active_1 = _active_active_active_active_T_52 | _active_active_active_active_T_59; // @[VCommon.scala 93:68]
   wire [63:0] _active_active_active_T_369 = f_io_entry_0_bits_tin_vt_valid ? active_active_active_active_1 : 64'h0; // @[Library.scala 8:8]
-  wire [63:0] _active_active_active_T_370 = _active_active_active_T_364 | _active_active_active_T_369; // @[VAlu.scala 253:74]
+  wire [63:0] _active_active_active_T_370 = _active_active_active_T_364 | _active_active_active_T_369; // @[VAlu.scala 233:74]
   wire [3:0] active_active_active_oh_shiftAmount_2 = f_io_entry_0_bits_tin_vu_addr[5:2]; // @[VCommon.scala 13:27]
   wire [15:0] active_active_active_oh_2 = 16'h1 << active_active_active_oh_shiftAmount_2; // @[OneHot.scala 64:12]
   wire [15:0] active_active_active_oh0_lo_lo_2 = {3'h0,active_active_active_oh_2[3],3'h0,active_active_active_oh_2[2],3'h0
@@ -51668,7 +42110,7 @@
     ; // @[Library.scala 18:8]
   wire [63:0] active_active_active_active_2 = _active_active_active_active_T_82 | _active_active_active_active_T_89; // @[VCommon.scala 93:68]
   wire [63:0] _active_active_active_T_375 = f_io_entry_0_bits_tin_vu_valid ? active_active_active_active_2 : 64'h0; // @[Library.scala 8:8]
-  wire [63:0] active_active_active_12 = _active_active_active_T_370 | _active_active_active_T_375; // @[VAlu.scala 254:74]
+  wire [63:0] active_active_active_12 = _active_active_active_T_370 | _active_active_active_T_375; // @[VAlu.scala 234:74]
   wire [63:0] active_active_4 = f_io_entry_0_valid ? active_active_active_12 : 64'h0; // @[Library.scala 8:8]
   wire [3:0] active_active_active_oh_shiftAmount_3 = f_io_entry_1_bits_tin_vs_addr[5:2]; // @[VCommon.scala 13:27]
   wire [15:0] active_active_active_oh_3 = 16'h1 << active_active_active_oh_shiftAmount_3; // @[OneHot.scala 64:12]
@@ -51822,7 +42264,7 @@
     ; // @[Library.scala 18:8]
   wire [63:0] active_active_active_active_4 = _active_active_active_active_T_142 | _active_active_active_active_T_149; // @[VCommon.scala 93:68]
   wire [63:0] _active_active_active_T_385 = f_io_entry_1_bits_tin_vt_valid ? active_active_active_active_4 : 64'h0; // @[Library.scala 8:8]
-  wire [63:0] _active_active_active_T_386 = _active_active_active_T_380 | _active_active_active_T_385; // @[VAlu.scala 253:74]
+  wire [63:0] _active_active_active_T_386 = _active_active_active_T_380 | _active_active_active_T_385; // @[VAlu.scala 233:74]
   wire [3:0] active_active_active_oh_shiftAmount_5 = f_io_entry_1_bits_tin_vu_addr[5:2]; // @[VCommon.scala 13:27]
   wire [15:0] active_active_active_oh_5 = 16'h1 << active_active_active_oh_shiftAmount_5; // @[OneHot.scala 64:12]
   wire [15:0] active_active_active_oh0_lo_lo_5 = {3'h0,active_active_active_oh_5[3],3'h0,active_active_active_oh_5[2],3'h0
@@ -51898,7 +42340,7 @@
     ; // @[Library.scala 18:8]
   wire [63:0] active_active_active_active_5 = _active_active_active_active_T_172 | _active_active_active_active_T_179; // @[VCommon.scala 93:68]
   wire [63:0] _active_active_active_T_391 = f_io_entry_1_bits_tin_vu_valid ? active_active_active_active_5 : 64'h0; // @[Library.scala 8:8]
-  wire [63:0] active_active_active_13 = _active_active_active_T_386 | _active_active_active_T_391; // @[VAlu.scala 254:74]
+  wire [63:0] active_active_active_13 = _active_active_active_T_386 | _active_active_active_T_391; // @[VAlu.scala 234:74]
   wire [63:0] active_active_5 = f_io_entry_1_valid ? active_active_active_13 : 64'h0; // @[Library.scala 8:8]
   wire [63:0] _active_T_28 = active_active_4 | active_active_5; // @[VCmdq.scala 91:24]
   wire [3:0] active_active_active_oh_shiftAmount_6 = f_io_entry_2_bits_tin_vs_addr[5:2]; // @[VCommon.scala 13:27]
@@ -52053,7 +42495,7 @@
     ; // @[Library.scala 18:8]
   wire [63:0] active_active_active_active_7 = _active_active_active_active_T_232 | _active_active_active_active_T_239; // @[VCommon.scala 93:68]
   wire [63:0] _active_active_active_T_401 = f_io_entry_2_bits_tin_vt_valid ? active_active_active_active_7 : 64'h0; // @[Library.scala 8:8]
-  wire [63:0] _active_active_active_T_402 = _active_active_active_T_396 | _active_active_active_T_401; // @[VAlu.scala 253:74]
+  wire [63:0] _active_active_active_T_402 = _active_active_active_T_396 | _active_active_active_T_401; // @[VAlu.scala 233:74]
   wire [3:0] active_active_active_oh_shiftAmount_8 = f_io_entry_2_bits_tin_vu_addr[5:2]; // @[VCommon.scala 13:27]
   wire [15:0] active_active_active_oh_8 = 16'h1 << active_active_active_oh_shiftAmount_8; // @[OneHot.scala 64:12]
   wire [15:0] active_active_active_oh0_lo_lo_8 = {3'h0,active_active_active_oh_8[3],3'h0,active_active_active_oh_8[2],3'h0
@@ -52129,7 +42571,7 @@
     ; // @[Library.scala 18:8]
   wire [63:0] active_active_active_active_8 = _active_active_active_active_T_262 | _active_active_active_active_T_269; // @[VCommon.scala 93:68]
   wire [63:0] _active_active_active_T_407 = f_io_entry_2_bits_tin_vu_valid ? active_active_active_active_8 : 64'h0; // @[Library.scala 8:8]
-  wire [63:0] active_active_active_14 = _active_active_active_T_402 | _active_active_active_T_407; // @[VAlu.scala 254:74]
+  wire [63:0] active_active_active_14 = _active_active_active_T_402 | _active_active_active_T_407; // @[VAlu.scala 234:74]
   wire [63:0] active_active_6 = f_io_entry_2_valid ? active_active_active_14 : 64'h0; // @[Library.scala 8:8]
   wire [63:0] _active_T_29 = _active_T_28 | active_active_6; // @[VCmdq.scala 91:24]
   wire [3:0] active_active_active_oh_shiftAmount_9 = f_io_entry_3_bits_tin_vs_addr[5:2]; // @[VCommon.scala 13:27]
@@ -52284,7 +42726,7 @@
     ; // @[Library.scala 18:8]
   wire [63:0] active_active_active_active_10 = _active_active_active_active_T_322 | _active_active_active_active_T_329; // @[VCommon.scala 93:68]
   wire [63:0] _active_active_active_T_417 = f_io_entry_3_bits_tin_vt_valid ? active_active_active_active_10 : 64'h0; // @[Library.scala 8:8]
-  wire [63:0] _active_active_active_T_418 = _active_active_active_T_412 | _active_active_active_T_417; // @[VAlu.scala 253:74]
+  wire [63:0] _active_active_active_T_418 = _active_active_active_T_412 | _active_active_active_T_417; // @[VAlu.scala 233:74]
   wire [3:0] active_active_active_oh_shiftAmount_11 = f_io_entry_3_bits_tin_vu_addr[5:2]; // @[VCommon.scala 13:27]
   wire [15:0] active_active_active_oh_11 = 16'h1 << active_active_active_oh_shiftAmount_11; // @[OneHot.scala 64:12]
   wire [15:0] active_active_active_oh0_lo_lo_11 = {3'h0,active_active_active_oh_11[3],3'h0,active_active_active_oh_11[2]
@@ -52360,7 +42802,7 @@
     ; // @[Library.scala 18:8]
   wire [63:0] active_active_active_active_11 = _active_active_active_active_T_352 | _active_active_active_active_T_359; // @[VCommon.scala 93:68]
   wire [63:0] _active_active_active_T_423 = f_io_entry_3_bits_tin_vu_valid ? active_active_active_active_11 : 64'h0; // @[Library.scala 8:8]
-  wire [63:0] active_active_active_15 = _active_active_active_T_418 | _active_active_active_T_423; // @[VAlu.scala 254:74]
+  wire [63:0] active_active_active_15 = _active_active_active_T_418 | _active_active_active_T_423; // @[VAlu.scala 234:74]
   wire [63:0] active_active_7 = f_io_entry_3_valid ? active_active_active_15 : 64'h0; // @[Library.scala 8:8]
   wire [63:0] _active_T_30 = _active_T_29 | active_active_7; // @[VCmdq.scala 91:24]
   wire [3:0] active_active_active_oh_shiftAmount_12 = f_io_entry_4_bits_tin_vs_addr[5:2]; // @[VCommon.scala 13:27]
@@ -52515,7 +42957,7 @@
     ; // @[Library.scala 18:8]
   wire [63:0] active_active_active_active_13 = _active_active_active_active_T_412 | _active_active_active_active_T_419; // @[VCommon.scala 93:68]
   wire [63:0] _active_active_active_T_433 = f_io_entry_4_bits_tin_vt_valid ? active_active_active_active_13 : 64'h0; // @[Library.scala 8:8]
-  wire [63:0] _active_active_active_T_434 = _active_active_active_T_428 | _active_active_active_T_433; // @[VAlu.scala 253:74]
+  wire [63:0] _active_active_active_T_434 = _active_active_active_T_428 | _active_active_active_T_433; // @[VAlu.scala 233:74]
   wire [3:0] active_active_active_oh_shiftAmount_14 = f_io_entry_4_bits_tin_vu_addr[5:2]; // @[VCommon.scala 13:27]
   wire [15:0] active_active_active_oh_14 = 16'h1 << active_active_active_oh_shiftAmount_14; // @[OneHot.scala 64:12]
   wire [15:0] active_active_active_oh0_lo_lo_14 = {3'h0,active_active_active_oh_14[3],3'h0,active_active_active_oh_14[2]
@@ -52591,7 +43033,7 @@
     ; // @[Library.scala 18:8]
   wire [63:0] active_active_active_active_14 = _active_active_active_active_T_442 | _active_active_active_active_T_449; // @[VCommon.scala 93:68]
   wire [63:0] _active_active_active_T_439 = f_io_entry_4_bits_tin_vu_valid ? active_active_active_active_14 : 64'h0; // @[Library.scala 8:8]
-  wire [63:0] active_active_active_16 = _active_active_active_T_434 | _active_active_active_T_439; // @[VAlu.scala 254:74]
+  wire [63:0] active_active_active_16 = _active_active_active_T_434 | _active_active_active_T_439; // @[VAlu.scala 234:74]
   wire [63:0] active_active_8 = f_io_entry_4_valid ? active_active_active_16 : 64'h0; // @[Library.scala 8:8]
   wire [63:0] _active_T_31 = _active_T_30 | active_active_8; // @[VCmdq.scala 91:24]
   wire [3:0] active_active_active_oh_shiftAmount_15 = f_io_entry_5_bits_tin_vs_addr[5:2]; // @[VCommon.scala 13:27]
@@ -52746,7 +43188,7 @@
     ; // @[Library.scala 18:8]
   wire [63:0] active_active_active_active_16 = _active_active_active_active_T_502 | _active_active_active_active_T_509; // @[VCommon.scala 93:68]
   wire [63:0] _active_active_active_T_449 = f_io_entry_5_bits_tin_vt_valid ? active_active_active_active_16 : 64'h0; // @[Library.scala 8:8]
-  wire [63:0] _active_active_active_T_450 = _active_active_active_T_444 | _active_active_active_T_449; // @[VAlu.scala 253:74]
+  wire [63:0] _active_active_active_T_450 = _active_active_active_T_444 | _active_active_active_T_449; // @[VAlu.scala 233:74]
   wire [3:0] active_active_active_oh_shiftAmount_17 = f_io_entry_5_bits_tin_vu_addr[5:2]; // @[VCommon.scala 13:27]
   wire [15:0] active_active_active_oh_17 = 16'h1 << active_active_active_oh_shiftAmount_17; // @[OneHot.scala 64:12]
   wire [15:0] active_active_active_oh0_lo_lo_17 = {3'h0,active_active_active_oh_17[3],3'h0,active_active_active_oh_17[2]
@@ -52822,7 +43264,7 @@
     ; // @[Library.scala 18:8]
   wire [63:0] active_active_active_active_17 = _active_active_active_active_T_532 | _active_active_active_active_T_539; // @[VCommon.scala 93:68]
   wire [63:0] _active_active_active_T_455 = f_io_entry_5_bits_tin_vu_valid ? active_active_active_active_17 : 64'h0; // @[Library.scala 8:8]
-  wire [63:0] active_active_active_17 = _active_active_active_T_450 | _active_active_active_T_455; // @[VAlu.scala 254:74]
+  wire [63:0] active_active_active_17 = _active_active_active_T_450 | _active_active_active_T_455; // @[VAlu.scala 234:74]
   wire [63:0] active_active_9 = f_io_entry_5_valid ? active_active_active_17 : 64'h0; // @[Library.scala 8:8]
   wire [63:0] _active_T_32 = _active_T_31 | active_active_9; // @[VCmdq.scala 91:24]
   wire [3:0] active_active_active_oh_shiftAmount_18 = f_io_entry_6_bits_tin_vs_addr[5:2]; // @[VCommon.scala 13:27]
@@ -52977,7 +43419,7 @@
     ; // @[Library.scala 18:8]
   wire [63:0] active_active_active_active_19 = _active_active_active_active_T_592 | _active_active_active_active_T_599; // @[VCommon.scala 93:68]
   wire [63:0] _active_active_active_T_465 = f_io_entry_6_bits_tin_vt_valid ? active_active_active_active_19 : 64'h0; // @[Library.scala 8:8]
-  wire [63:0] _active_active_active_T_466 = _active_active_active_T_460 | _active_active_active_T_465; // @[VAlu.scala 253:74]
+  wire [63:0] _active_active_active_T_466 = _active_active_active_T_460 | _active_active_active_T_465; // @[VAlu.scala 233:74]
   wire [3:0] active_active_active_oh_shiftAmount_20 = f_io_entry_6_bits_tin_vu_addr[5:2]; // @[VCommon.scala 13:27]
   wire [15:0] active_active_active_oh_20 = 16'h1 << active_active_active_oh_shiftAmount_20; // @[OneHot.scala 64:12]
   wire [15:0] active_active_active_oh0_lo_lo_20 = {3'h0,active_active_active_oh_20[3],3'h0,active_active_active_oh_20[2]
@@ -53053,7 +43495,7 @@
     ; // @[Library.scala 18:8]
   wire [63:0] active_active_active_active_20 = _active_active_active_active_T_622 | _active_active_active_active_T_629; // @[VCommon.scala 93:68]
   wire [63:0] _active_active_active_T_471 = f_io_entry_6_bits_tin_vu_valid ? active_active_active_active_20 : 64'h0; // @[Library.scala 8:8]
-  wire [63:0] active_active_active_18 = _active_active_active_T_466 | _active_active_active_T_471; // @[VAlu.scala 254:74]
+  wire [63:0] active_active_active_18 = _active_active_active_T_466 | _active_active_active_T_471; // @[VAlu.scala 234:74]
   wire [63:0] active_active_10 = f_io_entry_6_valid ? active_active_active_18 : 64'h0; // @[Library.scala 8:8]
   wire [63:0] _active_T_33 = _active_T_32 | active_active_10; // @[VCmdq.scala 91:24]
   wire [3:0] active_active_active_oh_shiftAmount_21 = f_io_entry_7_bits_tin_vs_addr[5:2]; // @[VCommon.scala 13:27]
@@ -53208,7 +43650,7 @@
     ; // @[Library.scala 18:8]
   wire [63:0] active_active_active_active_22 = _active_active_active_active_T_682 | _active_active_active_active_T_689; // @[VCommon.scala 93:68]
   wire [63:0] _active_active_active_T_481 = f_io_entry_7_bits_tin_vt_valid ? active_active_active_active_22 : 64'h0; // @[Library.scala 8:8]
-  wire [63:0] _active_active_active_T_482 = _active_active_active_T_476 | _active_active_active_T_481; // @[VAlu.scala 253:74]
+  wire [63:0] _active_active_active_T_482 = _active_active_active_T_476 | _active_active_active_T_481; // @[VAlu.scala 233:74]
   wire [3:0] active_active_active_oh_shiftAmount_23 = f_io_entry_7_bits_tin_vu_addr[5:2]; // @[VCommon.scala 13:27]
   wire [15:0] active_active_active_oh_23 = 16'h1 << active_active_active_oh_shiftAmount_23; // @[OneHot.scala 64:12]
   wire [15:0] active_active_active_oh0_lo_lo_23 = {3'h0,active_active_active_oh_23[3],3'h0,active_active_active_oh_23[2]
@@ -53284,7 +43726,7 @@
     ; // @[Library.scala 18:8]
   wire [63:0] active_active_active_active_23 = _active_active_active_active_T_712 | _active_active_active_active_T_719; // @[VCommon.scala 93:68]
   wire [63:0] _active_active_active_T_487 = f_io_entry_7_bits_tin_vu_valid ? active_active_active_active_23 : 64'h0; // @[Library.scala 8:8]
-  wire [63:0] active_active_active_19 = _active_active_active_T_482 | _active_active_active_T_487; // @[VAlu.scala 254:74]
+  wire [63:0] active_active_active_19 = _active_active_active_T_482 | _active_active_active_T_487; // @[VAlu.scala 234:74]
   wire [63:0] active_active_11 = f_io_entry_7_valid ? active_active_active_19 : 64'h0; // @[Library.scala 8:8]
   wire [63:0] _active_T_34 = _active_T_33 | active_active_11; // @[VCmdq.scala 91:24]
   wire [5:0] _active_active0_T = {{1'd0}, step}; // @[VCmdq.scala 94:48]
@@ -53437,7 +43879,7 @@
     ; // @[Library.scala 18:8]
   wire [63:0] active_active0_active_active_1 = _active_active0_active_active_T_52 | _active_active0_active_active_T_59; // @[VCommon.scala 93:68]
   wire [63:0] _active_active0_active_T_11 = value_tin_vt_valid ? active_active0_active_active_1 : 64'h0; // @[Library.scala 8:8]
-  wire [63:0] _active_active0_active_T_12 = _active_active0_active_T_5 | _active_active0_active_T_11; // @[VAlu.scala 253:74]
+  wire [63:0] _active_active0_active_T_12 = _active_active0_active_T_5 | _active_active0_active_T_11; // @[VAlu.scala 233:74]
   wire [3:0] active_active0_active_oh_shiftAmount_2 = value_tin_vu_addr[5:2]; // @[VCommon.scala 13:27]
   wire [15:0] active_active0_active_oh_2 = 16'h1 << active_active0_active_oh_shiftAmount_2; // @[OneHot.scala 64:12]
   wire [15:0] active_active0_active_oh0_lo_lo_2 = {3'h0,active_active0_active_oh_2[3],3'h0,active_active0_active_oh_2[2]
@@ -53513,7 +43955,7 @@
     ; // @[Library.scala 18:8]
   wire [63:0] active_active0_active_active_2 = _active_active0_active_active_T_82 | _active_active0_active_active_T_89; // @[VCommon.scala 93:68]
   wire [63:0] _active_active0_active_T_18 = value_tin_vu_valid ? active_active0_active_active_2 : 64'h0; // @[Library.scala 8:8]
-  wire [63:0] active_active0 = _active_active0_active_T_12 | _active_active0_active_T_18; // @[VAlu.scala 254:74]
+  wire [63:0] active_active0 = _active_active0_active_T_12 | _active_active0_active_T_18; // @[VAlu.scala 234:74]
   wire  _active_active1_active_active_T_5 = _last_T & active_active0_active_idx == 2'h0 | value_m & _step_T_1[2:0] <= 3'h0
     ; // @[VCommon.scala 91:42]
   wire [63:0] _active_active1_active_active_T_6 = _active_active1_active_active_T_5 ? active_active0_active_oh0 : 64'h0; // @[Library.scala 18:8]
@@ -53557,7 +43999,7 @@
     ; // @[Library.scala 18:8]
   wire [63:0] active_active1_active_active_1 = _active_active1_active_active_T_52 | _active_active1_active_active_T_59; // @[VCommon.scala 93:68]
   wire [63:0] _active_active1_active_T_11 = value_tin_vt_valid ? active_active1_active_active_1 : 64'h0; // @[Library.scala 8:8]
-  wire [63:0] _active_active1_active_T_12 = _active_active1_active_T_5 | _active_active1_active_T_11; // @[VAlu.scala 253:74]
+  wire [63:0] _active_active1_active_T_12 = _active_active1_active_T_5 | _active_active1_active_T_11; // @[VAlu.scala 233:74]
   wire  _active_active1_active_active_T_65 = _last_T & active_active0_active_idx_2 == 2'h0 | value_m & _step_T_1[2:0]
      <= 3'h0; // @[VCommon.scala 91:42]
   wire [63:0] _active_active1_active_active_T_66 = _active_active1_active_active_T_65 ? active_active0_active_oh0_2 : 64'h0
@@ -53580,14 +44022,14 @@
     ; // @[Library.scala 18:8]
   wire [63:0] active_active1_active_active_2 = _active_active1_active_active_T_82 | _active_active1_active_active_T_89; // @[VCommon.scala 93:68]
   wire [63:0] _active_active1_active_T_18 = value_tin_vu_valid ? active_active1_active_active_2 : 64'h0; // @[Library.scala 8:8]
-  wire [63:0] active_active1 = _active_active1_active_T_12 | _active_active1_active_T_18; // @[VAlu.scala 254:74]
+  wire [63:0] active_active1 = _active_active1_active_T_12 | _active_active1_active_T_18; // @[VAlu.scala 234:74]
   wire  _active_active_T_96 = ~io_out_ready; // @[VCmdq.scala 96:36]
   wire  _active_active_T_99 = valid & (~io_out_ready | _T_10); // @[VCmdq.scala 96:32]
   wire [63:0] _active_active_T_101 = _active_active_T_96 ? active_active0 : active_active1; // @[VCmdq.scala 97:29]
   wire [63:0] active_active_12 = _active_active_T_99 ? _active_active_T_101 : 64'h0; // @[Library.scala 8:8]
   wire [63:0] _active_T_35 = _active_T_34 | active_active_12; // @[VCmdq.scala 98:12]
   wire [63:0] _active_T_36 = _active_T_26 | _active_T_35; // @[VCmdq.scala 111:90]
-  wire  _GEN_149 = _T_14 & _T_6; // @[VAlu.scala 251:11]
+  wire  _GEN_149 = _T_14 & _T_6; // @[VAlu.scala 231:11]
   Fifo4e f ( // @[Fifo4e.scala 10:11]
     .clock(f_clock),
     .reset(f_reset),
@@ -53778,80 +44220,80 @@
   assign f_reset = reset;
   assign f_io_in_valid = io_in_valid; // @[VCmdq.scala 48:17]
   assign f_io_in_bits_0_valid = io_in_bits_0_valid; // @[VCmdq.scala 52:27]
-  assign f_io_in_bits_0_bits_tin_op = io_in_bits_0_bits_op; // @[VAlu.scala 190:19 191:12]
-  assign f_io_in_bits_0_bits_tin_f2 = io_in_bits_0_bits_f2; // @[VAlu.scala 190:19 192:12]
-  assign f_io_in_bits_0_bits_tin_sz = io_in_bits_0_bits_sz; // @[VAlu.scala 190:19 193:12]
-  assign f_io_in_bits_0_bits_tin_vd_addr = io_in_bits_0_bits_vd_addr; // @[VAlu.scala 195:40 196:14 202:14]
-  assign f_io_in_bits_0_bits_tin_ve_addr = io_in_bits_0_bits_ve_addr; // @[VAlu.scala 195:40 197:14 203:14]
-  assign f_io_in_bits_0_bits_tin_vs_valid = io_in_bits_0_bits_vs_valid; // @[VAlu.scala 195:40 198:14 204:14]
-  assign f_io_in_bits_0_bits_tin_vs_addr = io_in_bits_0_bits_vs_addr; // @[VAlu.scala 195:40 198:14 204:14]
-  assign f_io_in_bits_0_bits_tin_vs_tag = io_in_bits_0_bits_vs_tag; // @[VAlu.scala 195:40 198:14 204:14]
-  assign f_io_in_bits_0_bits_tin_vt_valid = io_in_bits_0_bits_vt_valid; // @[VAlu.scala 195:40 199:14 205:14]
-  assign f_io_in_bits_0_bits_tin_vt_addr = io_in_bits_0_bits_vt_addr; // @[VAlu.scala 195:40 199:14 205:14]
-  assign f_io_in_bits_0_bits_tin_vt_tag = io_in_bits_0_bits_vt_tag; // @[VAlu.scala 195:40 199:14 205:14]
-  assign f_io_in_bits_0_bits_tin_vu_valid = io_in_bits_0_bits_vu_valid; // @[VAlu.scala 195:40 200:14 206:14]
-  assign f_io_in_bits_0_bits_tin_vu_addr = io_in_bits_0_bits_vu_addr; // @[VAlu.scala 195:40 200:14 206:14]
-  assign f_io_in_bits_0_bits_tin_vu_tag = io_in_bits_0_bits_vu_tag; // @[VAlu.scala 195:40 200:14 206:14]
-  assign f_io_in_bits_0_bits_tin_sv_valid = io_in_bits_0_bits_sv_valid; // @[VAlu.scala 190:19 208:12]
-  assign f_io_in_bits_0_bits_tin_sv_data = io_in_bits_0_bits_sv_data; // @[VAlu.scala 190:19 208:12]
-  assign f_io_in_bits_0_bits_tin_cmdsync = io_in_bits_0_bits_cmdsync; // @[VAlu.scala 190:19 194:17]
+  assign f_io_in_bits_0_bits_tin_op = io_in_bits_0_bits_op; // @[VAlu.scala 170:19 171:12]
+  assign f_io_in_bits_0_bits_tin_f2 = io_in_bits_0_bits_f2; // @[VAlu.scala 170:19 172:12]
+  assign f_io_in_bits_0_bits_tin_sz = io_in_bits_0_bits_sz; // @[VAlu.scala 170:19 173:12]
+  assign f_io_in_bits_0_bits_tin_vd_addr = io_in_bits_0_bits_vd_addr; // @[VAlu.scala 175:40 176:14 182:14]
+  assign f_io_in_bits_0_bits_tin_ve_addr = io_in_bits_0_bits_ve_addr; // @[VAlu.scala 175:40 177:14 183:14]
+  assign f_io_in_bits_0_bits_tin_vs_valid = io_in_bits_0_bits_vs_valid; // @[VAlu.scala 175:40 178:14 184:14]
+  assign f_io_in_bits_0_bits_tin_vs_addr = io_in_bits_0_bits_vs_addr; // @[VAlu.scala 175:40 178:14 184:14]
+  assign f_io_in_bits_0_bits_tin_vs_tag = io_in_bits_0_bits_vs_tag; // @[VAlu.scala 175:40 178:14 184:14]
+  assign f_io_in_bits_0_bits_tin_vt_valid = io_in_bits_0_bits_vt_valid; // @[VAlu.scala 175:40 179:14 185:14]
+  assign f_io_in_bits_0_bits_tin_vt_addr = io_in_bits_0_bits_vt_addr; // @[VAlu.scala 175:40 179:14 185:14]
+  assign f_io_in_bits_0_bits_tin_vt_tag = io_in_bits_0_bits_vt_tag; // @[VAlu.scala 175:40 179:14 185:14]
+  assign f_io_in_bits_0_bits_tin_vu_valid = io_in_bits_0_bits_vu_valid; // @[VAlu.scala 175:40 180:14 186:14]
+  assign f_io_in_bits_0_bits_tin_vu_addr = io_in_bits_0_bits_vu_addr; // @[VAlu.scala 175:40 180:14 186:14]
+  assign f_io_in_bits_0_bits_tin_vu_tag = io_in_bits_0_bits_vu_tag; // @[VAlu.scala 175:40 180:14 186:14]
+  assign f_io_in_bits_0_bits_tin_sv_valid = io_in_bits_0_bits_sv_valid; // @[VAlu.scala 170:19 188:12]
+  assign f_io_in_bits_0_bits_tin_sv_data = io_in_bits_0_bits_sv_data; // @[VAlu.scala 170:19 188:12]
+  assign f_io_in_bits_0_bits_tin_cmdsync = io_in_bits_0_bits_cmdsync; // @[VAlu.scala 170:19 174:17]
   assign f_io_in_bits_0_bits_m = io_in_bits_0_bits_m; // @[VCmdq.scala 54:28]
   assign f_io_in_bits_1_valid = io_in_bits_1_valid; // @[VCmdq.scala 52:27]
-  assign f_io_in_bits_1_bits_tin_op = io_in_bits_1_bits_op; // @[VAlu.scala 190:19 191:12]
-  assign f_io_in_bits_1_bits_tin_f2 = io_in_bits_1_bits_f2; // @[VAlu.scala 190:19 192:12]
-  assign f_io_in_bits_1_bits_tin_sz = io_in_bits_1_bits_sz; // @[VAlu.scala 190:19 193:12]
-  assign f_io_in_bits_1_bits_tin_vd_addr = io_in_bits_1_bits_vd_addr; // @[VAlu.scala 195:40 196:14 202:14]
-  assign f_io_in_bits_1_bits_tin_ve_addr = io_in_bits_1_bits_ve_addr; // @[VAlu.scala 195:40 197:14 203:14]
-  assign f_io_in_bits_1_bits_tin_vs_valid = io_in_bits_1_bits_vs_valid; // @[VAlu.scala 195:40 198:14 204:14]
-  assign f_io_in_bits_1_bits_tin_vs_addr = io_in_bits_1_bits_vs_addr; // @[VAlu.scala 195:40 198:14 204:14]
-  assign f_io_in_bits_1_bits_tin_vs_tag = io_in_bits_1_bits_vs_tag; // @[VAlu.scala 195:40 198:14 204:14]
-  assign f_io_in_bits_1_bits_tin_vt_valid = io_in_bits_1_bits_vt_valid; // @[VAlu.scala 195:40 199:14 205:14]
-  assign f_io_in_bits_1_bits_tin_vt_addr = io_in_bits_1_bits_vt_addr; // @[VAlu.scala 195:40 199:14 205:14]
-  assign f_io_in_bits_1_bits_tin_vt_tag = io_in_bits_1_bits_vt_tag; // @[VAlu.scala 195:40 199:14 205:14]
-  assign f_io_in_bits_1_bits_tin_vu_valid = io_in_bits_1_bits_vu_valid; // @[VAlu.scala 195:40 200:14 206:14]
-  assign f_io_in_bits_1_bits_tin_vu_addr = io_in_bits_1_bits_vu_addr; // @[VAlu.scala 195:40 200:14 206:14]
-  assign f_io_in_bits_1_bits_tin_vu_tag = io_in_bits_1_bits_vu_tag; // @[VAlu.scala 195:40 200:14 206:14]
-  assign f_io_in_bits_1_bits_tin_sv_valid = io_in_bits_1_bits_sv_valid; // @[VAlu.scala 190:19 208:12]
-  assign f_io_in_bits_1_bits_tin_sv_data = io_in_bits_1_bits_sv_data; // @[VAlu.scala 190:19 208:12]
-  assign f_io_in_bits_1_bits_tin_cmdsync = io_in_bits_1_bits_cmdsync; // @[VAlu.scala 190:19 194:17]
+  assign f_io_in_bits_1_bits_tin_op = io_in_bits_1_bits_op; // @[VAlu.scala 170:19 171:12]
+  assign f_io_in_bits_1_bits_tin_f2 = io_in_bits_1_bits_f2; // @[VAlu.scala 170:19 172:12]
+  assign f_io_in_bits_1_bits_tin_sz = io_in_bits_1_bits_sz; // @[VAlu.scala 170:19 173:12]
+  assign f_io_in_bits_1_bits_tin_vd_addr = io_in_bits_1_bits_vd_addr; // @[VAlu.scala 175:40 176:14 182:14]
+  assign f_io_in_bits_1_bits_tin_ve_addr = io_in_bits_1_bits_ve_addr; // @[VAlu.scala 175:40 177:14 183:14]
+  assign f_io_in_bits_1_bits_tin_vs_valid = io_in_bits_1_bits_vs_valid; // @[VAlu.scala 175:40 178:14 184:14]
+  assign f_io_in_bits_1_bits_tin_vs_addr = io_in_bits_1_bits_vs_addr; // @[VAlu.scala 175:40 178:14 184:14]
+  assign f_io_in_bits_1_bits_tin_vs_tag = io_in_bits_1_bits_vs_tag; // @[VAlu.scala 175:40 178:14 184:14]
+  assign f_io_in_bits_1_bits_tin_vt_valid = io_in_bits_1_bits_vt_valid; // @[VAlu.scala 175:40 179:14 185:14]
+  assign f_io_in_bits_1_bits_tin_vt_addr = io_in_bits_1_bits_vt_addr; // @[VAlu.scala 175:40 179:14 185:14]
+  assign f_io_in_bits_1_bits_tin_vt_tag = io_in_bits_1_bits_vt_tag; // @[VAlu.scala 175:40 179:14 185:14]
+  assign f_io_in_bits_1_bits_tin_vu_valid = io_in_bits_1_bits_vu_valid; // @[VAlu.scala 175:40 180:14 186:14]
+  assign f_io_in_bits_1_bits_tin_vu_addr = io_in_bits_1_bits_vu_addr; // @[VAlu.scala 175:40 180:14 186:14]
+  assign f_io_in_bits_1_bits_tin_vu_tag = io_in_bits_1_bits_vu_tag; // @[VAlu.scala 175:40 180:14 186:14]
+  assign f_io_in_bits_1_bits_tin_sv_valid = io_in_bits_1_bits_sv_valid; // @[VAlu.scala 170:19 188:12]
+  assign f_io_in_bits_1_bits_tin_sv_data = io_in_bits_1_bits_sv_data; // @[VAlu.scala 170:19 188:12]
+  assign f_io_in_bits_1_bits_tin_cmdsync = io_in_bits_1_bits_cmdsync; // @[VAlu.scala 170:19 174:17]
   assign f_io_in_bits_1_bits_m = io_in_bits_1_bits_m; // @[VCmdq.scala 54:28]
   assign f_io_in_bits_2_valid = io_in_bits_2_valid; // @[VCmdq.scala 52:27]
-  assign f_io_in_bits_2_bits_tin_op = io_in_bits_2_bits_op; // @[VAlu.scala 190:19 191:12]
-  assign f_io_in_bits_2_bits_tin_f2 = io_in_bits_2_bits_f2; // @[VAlu.scala 190:19 192:12]
-  assign f_io_in_bits_2_bits_tin_sz = io_in_bits_2_bits_sz; // @[VAlu.scala 190:19 193:12]
-  assign f_io_in_bits_2_bits_tin_vd_addr = io_in_bits_2_bits_vd_addr; // @[VAlu.scala 195:40 196:14 202:14]
-  assign f_io_in_bits_2_bits_tin_ve_addr = io_in_bits_2_bits_ve_addr; // @[VAlu.scala 195:40 197:14 203:14]
-  assign f_io_in_bits_2_bits_tin_vs_valid = io_in_bits_2_bits_vs_valid; // @[VAlu.scala 195:40 198:14 204:14]
-  assign f_io_in_bits_2_bits_tin_vs_addr = io_in_bits_2_bits_vs_addr; // @[VAlu.scala 195:40 198:14 204:14]
-  assign f_io_in_bits_2_bits_tin_vs_tag = io_in_bits_2_bits_vs_tag; // @[VAlu.scala 195:40 198:14 204:14]
-  assign f_io_in_bits_2_bits_tin_vt_valid = io_in_bits_2_bits_vt_valid; // @[VAlu.scala 195:40 199:14 205:14]
-  assign f_io_in_bits_2_bits_tin_vt_addr = io_in_bits_2_bits_vt_addr; // @[VAlu.scala 195:40 199:14 205:14]
-  assign f_io_in_bits_2_bits_tin_vt_tag = io_in_bits_2_bits_vt_tag; // @[VAlu.scala 195:40 199:14 205:14]
-  assign f_io_in_bits_2_bits_tin_vu_valid = io_in_bits_2_bits_vu_valid; // @[VAlu.scala 195:40 200:14 206:14]
-  assign f_io_in_bits_2_bits_tin_vu_addr = io_in_bits_2_bits_vu_addr; // @[VAlu.scala 195:40 200:14 206:14]
-  assign f_io_in_bits_2_bits_tin_vu_tag = io_in_bits_2_bits_vu_tag; // @[VAlu.scala 195:40 200:14 206:14]
-  assign f_io_in_bits_2_bits_tin_sv_valid = io_in_bits_2_bits_sv_valid; // @[VAlu.scala 190:19 208:12]
-  assign f_io_in_bits_2_bits_tin_sv_data = io_in_bits_2_bits_sv_data; // @[VAlu.scala 190:19 208:12]
-  assign f_io_in_bits_2_bits_tin_cmdsync = io_in_bits_2_bits_cmdsync; // @[VAlu.scala 190:19 194:17]
+  assign f_io_in_bits_2_bits_tin_op = io_in_bits_2_bits_op; // @[VAlu.scala 170:19 171:12]
+  assign f_io_in_bits_2_bits_tin_f2 = io_in_bits_2_bits_f2; // @[VAlu.scala 170:19 172:12]
+  assign f_io_in_bits_2_bits_tin_sz = io_in_bits_2_bits_sz; // @[VAlu.scala 170:19 173:12]
+  assign f_io_in_bits_2_bits_tin_vd_addr = io_in_bits_2_bits_vd_addr; // @[VAlu.scala 175:40 176:14 182:14]
+  assign f_io_in_bits_2_bits_tin_ve_addr = io_in_bits_2_bits_ve_addr; // @[VAlu.scala 175:40 177:14 183:14]
+  assign f_io_in_bits_2_bits_tin_vs_valid = io_in_bits_2_bits_vs_valid; // @[VAlu.scala 175:40 178:14 184:14]
+  assign f_io_in_bits_2_bits_tin_vs_addr = io_in_bits_2_bits_vs_addr; // @[VAlu.scala 175:40 178:14 184:14]
+  assign f_io_in_bits_2_bits_tin_vs_tag = io_in_bits_2_bits_vs_tag; // @[VAlu.scala 175:40 178:14 184:14]
+  assign f_io_in_bits_2_bits_tin_vt_valid = io_in_bits_2_bits_vt_valid; // @[VAlu.scala 175:40 179:14 185:14]
+  assign f_io_in_bits_2_bits_tin_vt_addr = io_in_bits_2_bits_vt_addr; // @[VAlu.scala 175:40 179:14 185:14]
+  assign f_io_in_bits_2_bits_tin_vt_tag = io_in_bits_2_bits_vt_tag; // @[VAlu.scala 175:40 179:14 185:14]
+  assign f_io_in_bits_2_bits_tin_vu_valid = io_in_bits_2_bits_vu_valid; // @[VAlu.scala 175:40 180:14 186:14]
+  assign f_io_in_bits_2_bits_tin_vu_addr = io_in_bits_2_bits_vu_addr; // @[VAlu.scala 175:40 180:14 186:14]
+  assign f_io_in_bits_2_bits_tin_vu_tag = io_in_bits_2_bits_vu_tag; // @[VAlu.scala 175:40 180:14 186:14]
+  assign f_io_in_bits_2_bits_tin_sv_valid = io_in_bits_2_bits_sv_valid; // @[VAlu.scala 170:19 188:12]
+  assign f_io_in_bits_2_bits_tin_sv_data = io_in_bits_2_bits_sv_data; // @[VAlu.scala 170:19 188:12]
+  assign f_io_in_bits_2_bits_tin_cmdsync = io_in_bits_2_bits_cmdsync; // @[VAlu.scala 170:19 174:17]
   assign f_io_in_bits_2_bits_m = io_in_bits_2_bits_m; // @[VCmdq.scala 54:28]
   assign f_io_in_bits_3_valid = io_in_bits_3_valid; // @[VCmdq.scala 52:27]
-  assign f_io_in_bits_3_bits_tin_op = io_in_bits_3_bits_op; // @[VAlu.scala 190:19 191:12]
-  assign f_io_in_bits_3_bits_tin_f2 = io_in_bits_3_bits_f2; // @[VAlu.scala 190:19 192:12]
-  assign f_io_in_bits_3_bits_tin_sz = io_in_bits_3_bits_sz; // @[VAlu.scala 190:19 193:12]
-  assign f_io_in_bits_3_bits_tin_vd_addr = io_in_bits_3_bits_vd_addr; // @[VAlu.scala 195:40 196:14 202:14]
-  assign f_io_in_bits_3_bits_tin_ve_addr = io_in_bits_3_bits_ve_addr; // @[VAlu.scala 195:40 197:14 203:14]
-  assign f_io_in_bits_3_bits_tin_vs_valid = io_in_bits_3_bits_vs_valid; // @[VAlu.scala 195:40 198:14 204:14]
-  assign f_io_in_bits_3_bits_tin_vs_addr = io_in_bits_3_bits_vs_addr; // @[VAlu.scala 195:40 198:14 204:14]
-  assign f_io_in_bits_3_bits_tin_vs_tag = io_in_bits_3_bits_vs_tag; // @[VAlu.scala 195:40 198:14 204:14]
-  assign f_io_in_bits_3_bits_tin_vt_valid = io_in_bits_3_bits_vt_valid; // @[VAlu.scala 195:40 199:14 205:14]
-  assign f_io_in_bits_3_bits_tin_vt_addr = io_in_bits_3_bits_vt_addr; // @[VAlu.scala 195:40 199:14 205:14]
-  assign f_io_in_bits_3_bits_tin_vt_tag = io_in_bits_3_bits_vt_tag; // @[VAlu.scala 195:40 199:14 205:14]
-  assign f_io_in_bits_3_bits_tin_vu_valid = io_in_bits_3_bits_vu_valid; // @[VAlu.scala 195:40 200:14 206:14]
-  assign f_io_in_bits_3_bits_tin_vu_addr = io_in_bits_3_bits_vu_addr; // @[VAlu.scala 195:40 200:14 206:14]
-  assign f_io_in_bits_3_bits_tin_vu_tag = io_in_bits_3_bits_vu_tag; // @[VAlu.scala 195:40 200:14 206:14]
-  assign f_io_in_bits_3_bits_tin_sv_valid = io_in_bits_3_bits_sv_valid; // @[VAlu.scala 190:19 208:12]
-  assign f_io_in_bits_3_bits_tin_sv_data = io_in_bits_3_bits_sv_data; // @[VAlu.scala 190:19 208:12]
-  assign f_io_in_bits_3_bits_tin_cmdsync = io_in_bits_3_bits_cmdsync; // @[VAlu.scala 190:19 194:17]
+  assign f_io_in_bits_3_bits_tin_op = io_in_bits_3_bits_op; // @[VAlu.scala 170:19 171:12]
+  assign f_io_in_bits_3_bits_tin_f2 = io_in_bits_3_bits_f2; // @[VAlu.scala 170:19 172:12]
+  assign f_io_in_bits_3_bits_tin_sz = io_in_bits_3_bits_sz; // @[VAlu.scala 170:19 173:12]
+  assign f_io_in_bits_3_bits_tin_vd_addr = io_in_bits_3_bits_vd_addr; // @[VAlu.scala 175:40 176:14 182:14]
+  assign f_io_in_bits_3_bits_tin_ve_addr = io_in_bits_3_bits_ve_addr; // @[VAlu.scala 175:40 177:14 183:14]
+  assign f_io_in_bits_3_bits_tin_vs_valid = io_in_bits_3_bits_vs_valid; // @[VAlu.scala 175:40 178:14 184:14]
+  assign f_io_in_bits_3_bits_tin_vs_addr = io_in_bits_3_bits_vs_addr; // @[VAlu.scala 175:40 178:14 184:14]
+  assign f_io_in_bits_3_bits_tin_vs_tag = io_in_bits_3_bits_vs_tag; // @[VAlu.scala 175:40 178:14 184:14]
+  assign f_io_in_bits_3_bits_tin_vt_valid = io_in_bits_3_bits_vt_valid; // @[VAlu.scala 175:40 179:14 185:14]
+  assign f_io_in_bits_3_bits_tin_vt_addr = io_in_bits_3_bits_vt_addr; // @[VAlu.scala 175:40 179:14 185:14]
+  assign f_io_in_bits_3_bits_tin_vt_tag = io_in_bits_3_bits_vt_tag; // @[VAlu.scala 175:40 179:14 185:14]
+  assign f_io_in_bits_3_bits_tin_vu_valid = io_in_bits_3_bits_vu_valid; // @[VAlu.scala 175:40 180:14 186:14]
+  assign f_io_in_bits_3_bits_tin_vu_addr = io_in_bits_3_bits_vu_addr; // @[VAlu.scala 175:40 180:14 186:14]
+  assign f_io_in_bits_3_bits_tin_vu_tag = io_in_bits_3_bits_vu_tag; // @[VAlu.scala 175:40 180:14 186:14]
+  assign f_io_in_bits_3_bits_tin_sv_valid = io_in_bits_3_bits_sv_valid; // @[VAlu.scala 170:19 188:12]
+  assign f_io_in_bits_3_bits_tin_sv_data = io_in_bits_3_bits_sv_data; // @[VAlu.scala 170:19 188:12]
+  assign f_io_in_bits_3_bits_tin_cmdsync = io_in_bits_3_bits_cmdsync; // @[VAlu.scala 170:19 174:17]
   assign f_io_in_bits_3_bits_m = io_in_bits_3_bits_m; // @[VCmdq.scala 54:28]
   assign f_io_out_ready = ~valid | io_out_ready & last; // @[VCmdq.scala 57:28]
   always @(posedge clock) begin
@@ -54020,7 +44462,7 @@
       if (`STOP_COND) begin
     `endif
         if (vzip & ~reset & ~(value_tin_ve_addr == _out_vd_addr_T_1)) begin
-          $fatal; // @[VAlu.scala 242:13]
+          $fatal; // @[VAlu.scala 222:13]
         end
     `ifdef STOP_COND
       end
@@ -54031,7 +44473,7 @@
       if (`PRINTF_COND) begin
     `endif
         if (vzip & ~reset & ~(value_tin_ve_addr == _out_vd_addr_T_1)) begin
-          $fwrite(32'h80000002,"Assertion failed\n    at VAlu.scala:242 assert(in.ve.addr === (in.vd.addr + 1.U))\n"); // @[VAlu.scala 242:13]
+          $fwrite(32'h80000002,"Assertion failed\n    at VAlu.scala:222 assert(in.ve.addr === (in.vd.addr + 1.U))\n"); // @[VAlu.scala 222:13]
         end
     `ifdef PRINTF_COND
       end
@@ -54042,7 +44484,7 @@
       if (`STOP_COND) begin
     `endif
         if (_T_14 & _T_6 & ~(_active_active0_T[4:0] <= 5'h4)) begin
-          $fatal; // @[VAlu.scala 251:11]
+          $fatal; // @[VAlu.scala 231:11]
         end
     `ifdef STOP_COND
       end
@@ -54053,7 +44495,7 @@
       if (`PRINTF_COND) begin
     `endif
         if (_T_14 & _T_6 & ~(_active_active0_T[4:0] <= 5'h4)) begin
-          $fwrite(32'h80000002,"Assertion failed\n    at VAlu.scala:251 assert(step <= 4.U)\n"); // @[VAlu.scala 251:11]
+          $fwrite(32'h80000002,"Assertion failed\n    at VAlu.scala:231 assert(step <= 4.U)\n"); // @[VAlu.scala 231:11]
         end
     `ifdef PRINTF_COND
       end
@@ -54130,7 +44572,7 @@
       if (`STOP_COND) begin
     `endif
         if (_T_14 & _T_6 & ~(_step_T_1 <= 5'h4)) begin
-          $fatal; // @[VAlu.scala 251:11]
+          $fatal; // @[VAlu.scala 231:11]
         end
     `ifdef STOP_COND
       end
@@ -54141,7 +44583,7 @@
       if (`PRINTF_COND) begin
     `endif
         if (_T_14 & _T_6 & ~(_step_T_1 <= 5'h4)) begin
-          $fwrite(32'h80000002,"Assertion failed\n    at VAlu.scala:251 assert(step <= 4.U)\n"); // @[VAlu.scala 251:11]
+          $fwrite(32'h80000002,"Assertion failed\n    at VAlu.scala:231 assert(step <= 4.U)\n"); // @[VAlu.scala 231:11]
         end
     `ifdef PRINTF_COND
       end
@@ -54690,28 +45132,28 @@
   reg  value_tin_cmdsync; // @[VCmdq.scala 37:18]
   reg  value_m; // @[VCmdq.scala 37:18]
   reg [4:0] step; // @[VCmdq.scala 42:21]
-  wire  vevnodd = value_tin_op == 7'h5d | value_tin_op == 7'h5e | value_tin_op == 7'h5f; // @[VAlu.scala 221:60]
-  wire  vzip = value_tin_op == 7'h60; // @[VAlu.scala 222:22]
-  wire  _last_T = ~value_m; // @[VAlu.scala 224:16]
-  wire  last = ~value_m | step == 5'h3; // @[VAlu.scala 224:19]
-  wire [5:0] _out_vd_addr_T_1 = value_tin_vd_addr + 6'h1; // @[VAlu.scala 226:31]
-  wire [5:0] _out_ve_addr_T_1 = value_tin_ve_addr + 6'h1; // @[VAlu.scala 227:31]
-  wire [5:0] _out_vs_addr_T_1 = value_tin_vs_addr + 6'h1; // @[VAlu.scala 228:31]
-  wire [5:0] _out_vt_addr_T_1 = value_tin_vt_addr + 6'h1; // @[VAlu.scala 229:31]
-  wire [5:0] _out_vu_addr_T_1 = value_tin_vu_addr + 6'h1; // @[VAlu.scala 230:31]
-  wire [6:0] _out_vs_addr_T_2 = {{1'd0}, value_tin_vu_addr}; // @[VAlu.scala 234:35]
-  wire [5:0] _out_vs_addr_T_5 = value_tin_vs_addr + 6'h2; // @[VAlu.scala 237:35]
-  wire [5:0] _out_vt_addr_T_5 = value_tin_vt_addr + 6'h2; // @[VAlu.scala 238:35]
-  wire [5:0] _GEN_0 = step == 5'h1 ? _out_vs_addr_T_2[5:0] : _out_vs_addr_T_5; // @[VAlu.scala 233:27 234:21 237:21]
-  wire [5:0] _GEN_1 = step == 5'h1 ? _out_vu_addr_T_1 : _out_vt_addr_T_5; // @[VAlu.scala 233:27 235:21 238:21]
-  wire [5:0] tin_vu_addr = value_m & vevnodd ? value_tin_vu_addr : _out_vu_addr_T_1; // @[VAlu.scala 230:17 231:25 232:19]
-  wire [5:0] tin_vs_addr = value_m & vevnodd ? _GEN_0 : _out_vs_addr_T_1; // @[VAlu.scala 228:17 231:25]
-  wire [5:0] tin_vt_addr = value_m & vevnodd ? _GEN_1 : _out_vt_addr_T_1; // @[VAlu.scala 229:17 231:25]
-  wire  _T_6 = ~reset; // @[VAlu.scala 242:13]
-  wire [5:0] _out_vd_addr_T_3 = value_tin_vd_addr + 6'h2; // @[VAlu.scala 243:33]
-  wire [5:0] _out_ve_addr_T_3 = value_tin_ve_addr + 6'h2; // @[VAlu.scala 244:33]
-  wire [5:0] tin_vd_addr = vzip ? _out_vd_addr_T_3 : _out_vd_addr_T_1; // @[VAlu.scala 226:17 241:17 243:19]
-  wire [5:0] tin_ve_addr = vzip ? _out_ve_addr_T_3 : _out_ve_addr_T_1; // @[VAlu.scala 227:17 241:17 244:19]
+  wire  vevnodd = value_tin_op == 7'h41 | value_tin_op == 7'h42 | value_tin_op == 7'h43; // @[VAlu.scala 201:60]
+  wire  vzip = value_tin_op == 7'h44; // @[VAlu.scala 202:22]
+  wire  _last_T = ~value_m; // @[VAlu.scala 204:16]
+  wire  last = ~value_m | step == 5'h3; // @[VAlu.scala 204:19]
+  wire [5:0] _out_vd_addr_T_1 = value_tin_vd_addr + 6'h1; // @[VAlu.scala 206:31]
+  wire [5:0] _out_ve_addr_T_1 = value_tin_ve_addr + 6'h1; // @[VAlu.scala 207:31]
+  wire [5:0] _out_vs_addr_T_1 = value_tin_vs_addr + 6'h1; // @[VAlu.scala 208:31]
+  wire [5:0] _out_vt_addr_T_1 = value_tin_vt_addr + 6'h1; // @[VAlu.scala 209:31]
+  wire [5:0] _out_vu_addr_T_1 = value_tin_vu_addr + 6'h1; // @[VAlu.scala 210:31]
+  wire [6:0] _out_vs_addr_T_2 = {{1'd0}, value_tin_vu_addr}; // @[VAlu.scala 214:35]
+  wire [5:0] _out_vs_addr_T_5 = value_tin_vs_addr + 6'h2; // @[VAlu.scala 217:35]
+  wire [5:0] _out_vt_addr_T_5 = value_tin_vt_addr + 6'h2; // @[VAlu.scala 218:35]
+  wire [5:0] _GEN_0 = step == 5'h1 ? _out_vs_addr_T_2[5:0] : _out_vs_addr_T_5; // @[VAlu.scala 213:27 214:21 217:21]
+  wire [5:0] _GEN_1 = step == 5'h1 ? _out_vu_addr_T_1 : _out_vt_addr_T_5; // @[VAlu.scala 213:27 215:21 218:21]
+  wire [5:0] tin_vu_addr = value_m & vevnodd ? value_tin_vu_addr : _out_vu_addr_T_1; // @[VAlu.scala 210:17 211:25 212:19]
+  wire [5:0] tin_vs_addr = value_m & vevnodd ? _GEN_0 : _out_vs_addr_T_1; // @[VAlu.scala 208:17 211:25]
+  wire [5:0] tin_vt_addr = value_m & vevnodd ? _GEN_1 : _out_vt_addr_T_1; // @[VAlu.scala 209:17 211:25]
+  wire  _T_6 = ~reset; // @[VAlu.scala 222:13]
+  wire [5:0] _out_vd_addr_T_3 = value_tin_vd_addr + 6'h2; // @[VAlu.scala 223:33]
+  wire [5:0] _out_ve_addr_T_3 = value_tin_ve_addr + 6'h2; // @[VAlu.scala 224:33]
+  wire [5:0] tin_vd_addr = vzip ? _out_vd_addr_T_3 : _out_vd_addr_T_1; // @[VAlu.scala 206:17 221:17 223:19]
+  wire [5:0] tin_ve_addr = vzip ? _out_ve_addr_T_3 : _out_ve_addr_T_1; // @[VAlu.scala 207:17 221:17 224:19]
   wire  _T_9 = io_out_valid & io_out_ready; // @[VCmdq.scala 65:29]
   wire  _T_10 = ~last; // @[VCmdq.scala 66:11]
   wire [4:0] _step_T_1 = step + 5'h1; // @[VCmdq.scala 70:20]
@@ -54838,7 +45280,7 @@
   wire [63:0] _active_active_active_T_59 = _active_active_active_T_58 ? active_active_oh3_1 : 64'h0; // @[Library.scala 18:8]
   wire [63:0] active_active_active_1 = _active_active_active_T_52 | _active_active_active_T_59; // @[VCommon.scala 93:68]
   wire [63:0] _active_active_T_9 = f_io_in_bits_0_bits_tin_vt_valid ? active_active_active_1 : 64'h0; // @[Library.scala 8:8]
-  wire [63:0] _active_active_T_10 = _active_active_T_4 | _active_active_T_9; // @[VAlu.scala 253:74]
+  wire [63:0] _active_active_T_10 = _active_active_T_4 | _active_active_T_9; // @[VAlu.scala 233:74]
   wire [3:0] active_active_oh_shiftAmount_2 = f_io_in_bits_0_bits_tin_vu_addr[5:2]; // @[VCommon.scala 13:27]
   wire [15:0] active_active_oh_2 = 16'h1 << active_active_oh_shiftAmount_2; // @[OneHot.scala 64:12]
   wire [15:0] active_active_oh0_lo_lo_2 = {3'h0,active_active_oh_2[3],3'h0,active_active_oh_2[2],3'h0,active_active_oh_2
@@ -54894,7 +45336,7 @@
   wire [63:0] _active_active_active_T_89 = _active_active_active_T_88 ? active_active_oh3_2 : 64'h0; // @[Library.scala 18:8]
   wire [63:0] active_active_active_2 = _active_active_active_T_82 | _active_active_active_T_89; // @[VCommon.scala 93:68]
   wire [63:0] _active_active_T_15 = f_io_in_bits_0_bits_tin_vu_valid ? active_active_active_2 : 64'h0; // @[Library.scala 8:8]
-  wire [63:0] active_active = _active_active_T_10 | _active_active_T_15; // @[VAlu.scala 254:74]
+  wire [63:0] active_active = _active_active_T_10 | _active_active_T_15; // @[VAlu.scala 234:74]
   wire [63:0] _active_T_5 = fvalid[0] ? active_active : 64'h0; // @[Library.scala 8:8]
   wire [3:0] active_active_oh_shiftAmount_3 = f_io_in_bits_1_bits_tin_vs_addr[5:2]; // @[VCommon.scala 13:27]
   wire [15:0] active_active_oh_3 = 16'h1 << active_active_oh_shiftAmount_3; // @[OneHot.scala 64:12]
@@ -55014,7 +45456,7 @@
   wire [63:0] _active_active_active_T_149 = _active_active_active_T_148 ? active_active_oh3_4 : 64'h0; // @[Library.scala 18:8]
   wire [63:0] active_active_active_4 = _active_active_active_T_142 | _active_active_active_T_149; // @[VCommon.scala 93:68]
   wire [63:0] _active_active_T_25 = f_io_in_bits_1_bits_tin_vt_valid ? active_active_active_4 : 64'h0; // @[Library.scala 8:8]
-  wire [63:0] _active_active_T_26 = _active_active_T_20 | _active_active_T_25; // @[VAlu.scala 253:74]
+  wire [63:0] _active_active_T_26 = _active_active_T_20 | _active_active_T_25; // @[VAlu.scala 233:74]
   wire [3:0] active_active_oh_shiftAmount_5 = f_io_in_bits_1_bits_tin_vu_addr[5:2]; // @[VCommon.scala 13:27]
   wire [15:0] active_active_oh_5 = 16'h1 << active_active_oh_shiftAmount_5; // @[OneHot.scala 64:12]
   wire [15:0] active_active_oh0_lo_lo_5 = {3'h0,active_active_oh_5[3],3'h0,active_active_oh_5[2],3'h0,active_active_oh_5
@@ -55073,7 +45515,7 @@
   wire [63:0] _active_active_active_T_179 = _active_active_active_T_178 ? active_active_oh3_5 : 64'h0; // @[Library.scala 18:8]
   wire [63:0] active_active_active_5 = _active_active_active_T_172 | _active_active_active_T_179; // @[VCommon.scala 93:68]
   wire [63:0] _active_active_T_31 = f_io_in_bits_1_bits_tin_vu_valid ? active_active_active_5 : 64'h0; // @[Library.scala 8:8]
-  wire [63:0] active_active_1 = _active_active_T_26 | _active_active_T_31; // @[VAlu.scala 254:74]
+  wire [63:0] active_active_1 = _active_active_T_26 | _active_active_T_31; // @[VAlu.scala 234:74]
   wire [63:0] _active_T_11 = fvalid[1] ? active_active_1 : 64'h0; // @[Library.scala 8:8]
   wire [63:0] _active_T_12 = _active_T_5 | _active_T_11; // @[VCmdq.scala 108:90]
   wire [3:0] active_active_oh_shiftAmount_6 = f_io_in_bits_2_bits_tin_vs_addr[5:2]; // @[VCommon.scala 13:27]
@@ -55194,7 +45636,7 @@
   wire [63:0] _active_active_active_T_239 = _active_active_active_T_238 ? active_active_oh3_7 : 64'h0; // @[Library.scala 18:8]
   wire [63:0] active_active_active_7 = _active_active_active_T_232 | _active_active_active_T_239; // @[VCommon.scala 93:68]
   wire [63:0] _active_active_T_41 = f_io_in_bits_2_bits_tin_vt_valid ? active_active_active_7 : 64'h0; // @[Library.scala 8:8]
-  wire [63:0] _active_active_T_42 = _active_active_T_36 | _active_active_T_41; // @[VAlu.scala 253:74]
+  wire [63:0] _active_active_T_42 = _active_active_T_36 | _active_active_T_41; // @[VAlu.scala 233:74]
   wire [3:0] active_active_oh_shiftAmount_8 = f_io_in_bits_2_bits_tin_vu_addr[5:2]; // @[VCommon.scala 13:27]
   wire [15:0] active_active_oh_8 = 16'h1 << active_active_oh_shiftAmount_8; // @[OneHot.scala 64:12]
   wire [15:0] active_active_oh0_lo_lo_8 = {3'h0,active_active_oh_8[3],3'h0,active_active_oh_8[2],3'h0,active_active_oh_8
@@ -55253,7 +45695,7 @@
   wire [63:0] _active_active_active_T_269 = _active_active_active_T_268 ? active_active_oh3_8 : 64'h0; // @[Library.scala 18:8]
   wire [63:0] active_active_active_8 = _active_active_active_T_262 | _active_active_active_T_269; // @[VCommon.scala 93:68]
   wire [63:0] _active_active_T_47 = f_io_in_bits_2_bits_tin_vu_valid ? active_active_active_8 : 64'h0; // @[Library.scala 8:8]
-  wire [63:0] active_active_2 = _active_active_T_42 | _active_active_T_47; // @[VAlu.scala 254:74]
+  wire [63:0] active_active_2 = _active_active_T_42 | _active_active_T_47; // @[VAlu.scala 234:74]
   wire [63:0] _active_T_18 = fvalid[2] ? active_active_2 : 64'h0; // @[Library.scala 8:8]
   wire [63:0] _active_T_19 = _active_T_12 | _active_T_18; // @[VCmdq.scala 109:90]
   wire [3:0] active_active_oh_shiftAmount_9 = f_io_in_bits_3_bits_tin_vs_addr[5:2]; // @[VCommon.scala 13:27]
@@ -55374,7 +45816,7 @@
   wire [63:0] _active_active_active_T_329 = _active_active_active_T_328 ? active_active_oh3_10 : 64'h0; // @[Library.scala 18:8]
   wire [63:0] active_active_active_10 = _active_active_active_T_322 | _active_active_active_T_329; // @[VCommon.scala 93:68]
   wire [63:0] _active_active_T_57 = f_io_in_bits_3_bits_tin_vt_valid ? active_active_active_10 : 64'h0; // @[Library.scala 8:8]
-  wire [63:0] _active_active_T_58 = _active_active_T_52 | _active_active_T_57; // @[VAlu.scala 253:74]
+  wire [63:0] _active_active_T_58 = _active_active_T_52 | _active_active_T_57; // @[VAlu.scala 233:74]
   wire [3:0] active_active_oh_shiftAmount_11 = f_io_in_bits_3_bits_tin_vu_addr[5:2]; // @[VCommon.scala 13:27]
   wire [15:0] active_active_oh_11 = 16'h1 << active_active_oh_shiftAmount_11; // @[OneHot.scala 64:12]
   wire [15:0] active_active_oh0_lo_lo_11 = {3'h0,active_active_oh_11[3],3'h0,active_active_oh_11[2],3'h0,
@@ -55433,7 +45875,7 @@
   wire [63:0] _active_active_active_T_359 = _active_active_active_T_358 ? active_active_oh3_11 : 64'h0; // @[Library.scala 18:8]
   wire [63:0] active_active_active_11 = _active_active_active_T_352 | _active_active_active_T_359; // @[VCommon.scala 93:68]
   wire [63:0] _active_active_T_63 = f_io_in_bits_3_bits_tin_vu_valid ? active_active_active_11 : 64'h0; // @[Library.scala 8:8]
-  wire [63:0] active_active_3 = _active_active_T_58 | _active_active_T_63; // @[VAlu.scala 254:74]
+  wire [63:0] active_active_3 = _active_active_T_58 | _active_active_T_63; // @[VAlu.scala 234:74]
   wire [63:0] _active_T_25 = fvalid[3] ? active_active_3 : 64'h0; // @[Library.scala 8:8]
   wire [63:0] _active_T_26 = _active_T_19 | _active_T_25; // @[VCmdq.scala 110:90]
   wire [3:0] active_active_active_oh_shiftAmount = f_io_entry_0_bits_tin_vs_addr[5:2]; // @[VCommon.scala 13:27]
@@ -55580,7 +46022,7 @@
     ; // @[Library.scala 18:8]
   wire [63:0] active_active_active_active_1 = _active_active_active_active_T_52 | _active_active_active_active_T_59; // @[VCommon.scala 93:68]
   wire [63:0] _active_active_active_T_369 = f_io_entry_0_bits_tin_vt_valid ? active_active_active_active_1 : 64'h0; // @[Library.scala 8:8]
-  wire [63:0] _active_active_active_T_370 = _active_active_active_T_364 | _active_active_active_T_369; // @[VAlu.scala 253:74]
+  wire [63:0] _active_active_active_T_370 = _active_active_active_T_364 | _active_active_active_T_369; // @[VAlu.scala 233:74]
   wire [3:0] active_active_active_oh_shiftAmount_2 = f_io_entry_0_bits_tin_vu_addr[5:2]; // @[VCommon.scala 13:27]
   wire [15:0] active_active_active_oh_2 = 16'h1 << active_active_active_oh_shiftAmount_2; // @[OneHot.scala 64:12]
   wire [15:0] active_active_active_oh0_lo_lo_2 = {3'h0,active_active_active_oh_2[3],3'h0,active_active_active_oh_2[2],3'h0
@@ -55654,7 +46096,7 @@
     ; // @[Library.scala 18:8]
   wire [63:0] active_active_active_active_2 = _active_active_active_active_T_82 | _active_active_active_active_T_89; // @[VCommon.scala 93:68]
   wire [63:0] _active_active_active_T_375 = f_io_entry_0_bits_tin_vu_valid ? active_active_active_active_2 : 64'h0; // @[Library.scala 8:8]
-  wire [63:0] active_active_active_12 = _active_active_active_T_370 | _active_active_active_T_375; // @[VAlu.scala 254:74]
+  wire [63:0] active_active_active_12 = _active_active_active_T_370 | _active_active_active_T_375; // @[VAlu.scala 234:74]
   wire [63:0] active_active_4 = f_io_entry_0_valid ? active_active_active_12 : 64'h0; // @[Library.scala 8:8]
   wire [3:0] active_active_active_oh_shiftAmount_3 = f_io_entry_1_bits_tin_vs_addr[5:2]; // @[VCommon.scala 13:27]
   wire [15:0] active_active_active_oh_3 = 16'h1 << active_active_active_oh_shiftAmount_3; // @[OneHot.scala 64:12]
@@ -55808,7 +46250,7 @@
     ; // @[Library.scala 18:8]
   wire [63:0] active_active_active_active_4 = _active_active_active_active_T_142 | _active_active_active_active_T_149; // @[VCommon.scala 93:68]
   wire [63:0] _active_active_active_T_385 = f_io_entry_1_bits_tin_vt_valid ? active_active_active_active_4 : 64'h0; // @[Library.scala 8:8]
-  wire [63:0] _active_active_active_T_386 = _active_active_active_T_380 | _active_active_active_T_385; // @[VAlu.scala 253:74]
+  wire [63:0] _active_active_active_T_386 = _active_active_active_T_380 | _active_active_active_T_385; // @[VAlu.scala 233:74]
   wire [3:0] active_active_active_oh_shiftAmount_5 = f_io_entry_1_bits_tin_vu_addr[5:2]; // @[VCommon.scala 13:27]
   wire [15:0] active_active_active_oh_5 = 16'h1 << active_active_active_oh_shiftAmount_5; // @[OneHot.scala 64:12]
   wire [15:0] active_active_active_oh0_lo_lo_5 = {3'h0,active_active_active_oh_5[3],3'h0,active_active_active_oh_5[2],3'h0
@@ -55884,7 +46326,7 @@
     ; // @[Library.scala 18:8]
   wire [63:0] active_active_active_active_5 = _active_active_active_active_T_172 | _active_active_active_active_T_179; // @[VCommon.scala 93:68]
   wire [63:0] _active_active_active_T_391 = f_io_entry_1_bits_tin_vu_valid ? active_active_active_active_5 : 64'h0; // @[Library.scala 8:8]
-  wire [63:0] active_active_active_13 = _active_active_active_T_386 | _active_active_active_T_391; // @[VAlu.scala 254:74]
+  wire [63:0] active_active_active_13 = _active_active_active_T_386 | _active_active_active_T_391; // @[VAlu.scala 234:74]
   wire [63:0] active_active_5 = f_io_entry_1_valid ? active_active_active_13 : 64'h0; // @[Library.scala 8:8]
   wire [63:0] _active_T_28 = active_active_4 | active_active_5; // @[VCmdq.scala 91:24]
   wire [3:0] active_active_active_oh_shiftAmount_6 = f_io_entry_2_bits_tin_vs_addr[5:2]; // @[VCommon.scala 13:27]
@@ -56039,7 +46481,7 @@
     ; // @[Library.scala 18:8]
   wire [63:0] active_active_active_active_7 = _active_active_active_active_T_232 | _active_active_active_active_T_239; // @[VCommon.scala 93:68]
   wire [63:0] _active_active_active_T_401 = f_io_entry_2_bits_tin_vt_valid ? active_active_active_active_7 : 64'h0; // @[Library.scala 8:8]
-  wire [63:0] _active_active_active_T_402 = _active_active_active_T_396 | _active_active_active_T_401; // @[VAlu.scala 253:74]
+  wire [63:0] _active_active_active_T_402 = _active_active_active_T_396 | _active_active_active_T_401; // @[VAlu.scala 233:74]
   wire [3:0] active_active_active_oh_shiftAmount_8 = f_io_entry_2_bits_tin_vu_addr[5:2]; // @[VCommon.scala 13:27]
   wire [15:0] active_active_active_oh_8 = 16'h1 << active_active_active_oh_shiftAmount_8; // @[OneHot.scala 64:12]
   wire [15:0] active_active_active_oh0_lo_lo_8 = {3'h0,active_active_active_oh_8[3],3'h0,active_active_active_oh_8[2],3'h0
@@ -56115,7 +46557,7 @@
     ; // @[Library.scala 18:8]
   wire [63:0] active_active_active_active_8 = _active_active_active_active_T_262 | _active_active_active_active_T_269; // @[VCommon.scala 93:68]
   wire [63:0] _active_active_active_T_407 = f_io_entry_2_bits_tin_vu_valid ? active_active_active_active_8 : 64'h0; // @[Library.scala 8:8]
-  wire [63:0] active_active_active_14 = _active_active_active_T_402 | _active_active_active_T_407; // @[VAlu.scala 254:74]
+  wire [63:0] active_active_active_14 = _active_active_active_T_402 | _active_active_active_T_407; // @[VAlu.scala 234:74]
   wire [63:0] active_active_6 = f_io_entry_2_valid ? active_active_active_14 : 64'h0; // @[Library.scala 8:8]
   wire [63:0] _active_T_29 = _active_T_28 | active_active_6; // @[VCmdq.scala 91:24]
   wire [3:0] active_active_active_oh_shiftAmount_9 = f_io_entry_3_bits_tin_vs_addr[5:2]; // @[VCommon.scala 13:27]
@@ -56270,7 +46712,7 @@
     ; // @[Library.scala 18:8]
   wire [63:0] active_active_active_active_10 = _active_active_active_active_T_322 | _active_active_active_active_T_329; // @[VCommon.scala 93:68]
   wire [63:0] _active_active_active_T_417 = f_io_entry_3_bits_tin_vt_valid ? active_active_active_active_10 : 64'h0; // @[Library.scala 8:8]
-  wire [63:0] _active_active_active_T_418 = _active_active_active_T_412 | _active_active_active_T_417; // @[VAlu.scala 253:74]
+  wire [63:0] _active_active_active_T_418 = _active_active_active_T_412 | _active_active_active_T_417; // @[VAlu.scala 233:74]
   wire [3:0] active_active_active_oh_shiftAmount_11 = f_io_entry_3_bits_tin_vu_addr[5:2]; // @[VCommon.scala 13:27]
   wire [15:0] active_active_active_oh_11 = 16'h1 << active_active_active_oh_shiftAmount_11; // @[OneHot.scala 64:12]
   wire [15:0] active_active_active_oh0_lo_lo_11 = {3'h0,active_active_active_oh_11[3],3'h0,active_active_active_oh_11[2]
@@ -56346,7 +46788,7 @@
     ; // @[Library.scala 18:8]
   wire [63:0] active_active_active_active_11 = _active_active_active_active_T_352 | _active_active_active_active_T_359; // @[VCommon.scala 93:68]
   wire [63:0] _active_active_active_T_423 = f_io_entry_3_bits_tin_vu_valid ? active_active_active_active_11 : 64'h0; // @[Library.scala 8:8]
-  wire [63:0] active_active_active_15 = _active_active_active_T_418 | _active_active_active_T_423; // @[VAlu.scala 254:74]
+  wire [63:0] active_active_active_15 = _active_active_active_T_418 | _active_active_active_T_423; // @[VAlu.scala 234:74]
   wire [63:0] active_active_7 = f_io_entry_3_valid ? active_active_active_15 : 64'h0; // @[Library.scala 8:8]
   wire [63:0] _active_T_30 = _active_T_29 | active_active_7; // @[VCmdq.scala 91:24]
   wire [3:0] active_active_active_oh_shiftAmount_12 = f_io_entry_4_bits_tin_vs_addr[5:2]; // @[VCommon.scala 13:27]
@@ -56501,7 +46943,7 @@
     ; // @[Library.scala 18:8]
   wire [63:0] active_active_active_active_13 = _active_active_active_active_T_412 | _active_active_active_active_T_419; // @[VCommon.scala 93:68]
   wire [63:0] _active_active_active_T_433 = f_io_entry_4_bits_tin_vt_valid ? active_active_active_active_13 : 64'h0; // @[Library.scala 8:8]
-  wire [63:0] _active_active_active_T_434 = _active_active_active_T_428 | _active_active_active_T_433; // @[VAlu.scala 253:74]
+  wire [63:0] _active_active_active_T_434 = _active_active_active_T_428 | _active_active_active_T_433; // @[VAlu.scala 233:74]
   wire [3:0] active_active_active_oh_shiftAmount_14 = f_io_entry_4_bits_tin_vu_addr[5:2]; // @[VCommon.scala 13:27]
   wire [15:0] active_active_active_oh_14 = 16'h1 << active_active_active_oh_shiftAmount_14; // @[OneHot.scala 64:12]
   wire [15:0] active_active_active_oh0_lo_lo_14 = {3'h0,active_active_active_oh_14[3],3'h0,active_active_active_oh_14[2]
@@ -56577,7 +47019,7 @@
     ; // @[Library.scala 18:8]
   wire [63:0] active_active_active_active_14 = _active_active_active_active_T_442 | _active_active_active_active_T_449; // @[VCommon.scala 93:68]
   wire [63:0] _active_active_active_T_439 = f_io_entry_4_bits_tin_vu_valid ? active_active_active_active_14 : 64'h0; // @[Library.scala 8:8]
-  wire [63:0] active_active_active_16 = _active_active_active_T_434 | _active_active_active_T_439; // @[VAlu.scala 254:74]
+  wire [63:0] active_active_active_16 = _active_active_active_T_434 | _active_active_active_T_439; // @[VAlu.scala 234:74]
   wire [63:0] active_active_8 = f_io_entry_4_valid ? active_active_active_16 : 64'h0; // @[Library.scala 8:8]
   wire [63:0] _active_T_31 = _active_T_30 | active_active_8; // @[VCmdq.scala 91:24]
   wire [3:0] active_active_active_oh_shiftAmount_15 = f_io_entry_5_bits_tin_vs_addr[5:2]; // @[VCommon.scala 13:27]
@@ -56732,7 +47174,7 @@
     ; // @[Library.scala 18:8]
   wire [63:0] active_active_active_active_16 = _active_active_active_active_T_502 | _active_active_active_active_T_509; // @[VCommon.scala 93:68]
   wire [63:0] _active_active_active_T_449 = f_io_entry_5_bits_tin_vt_valid ? active_active_active_active_16 : 64'h0; // @[Library.scala 8:8]
-  wire [63:0] _active_active_active_T_450 = _active_active_active_T_444 | _active_active_active_T_449; // @[VAlu.scala 253:74]
+  wire [63:0] _active_active_active_T_450 = _active_active_active_T_444 | _active_active_active_T_449; // @[VAlu.scala 233:74]
   wire [3:0] active_active_active_oh_shiftAmount_17 = f_io_entry_5_bits_tin_vu_addr[5:2]; // @[VCommon.scala 13:27]
   wire [15:0] active_active_active_oh_17 = 16'h1 << active_active_active_oh_shiftAmount_17; // @[OneHot.scala 64:12]
   wire [15:0] active_active_active_oh0_lo_lo_17 = {3'h0,active_active_active_oh_17[3],3'h0,active_active_active_oh_17[2]
@@ -56808,7 +47250,7 @@
     ; // @[Library.scala 18:8]
   wire [63:0] active_active_active_active_17 = _active_active_active_active_T_532 | _active_active_active_active_T_539; // @[VCommon.scala 93:68]
   wire [63:0] _active_active_active_T_455 = f_io_entry_5_bits_tin_vu_valid ? active_active_active_active_17 : 64'h0; // @[Library.scala 8:8]
-  wire [63:0] active_active_active_17 = _active_active_active_T_450 | _active_active_active_T_455; // @[VAlu.scala 254:74]
+  wire [63:0] active_active_active_17 = _active_active_active_T_450 | _active_active_active_T_455; // @[VAlu.scala 234:74]
   wire [63:0] active_active_9 = f_io_entry_5_valid ? active_active_active_17 : 64'h0; // @[Library.scala 8:8]
   wire [63:0] _active_T_32 = _active_T_31 | active_active_9; // @[VCmdq.scala 91:24]
   wire [3:0] active_active_active_oh_shiftAmount_18 = f_io_entry_6_bits_tin_vs_addr[5:2]; // @[VCommon.scala 13:27]
@@ -56963,7 +47405,7 @@
     ; // @[Library.scala 18:8]
   wire [63:0] active_active_active_active_19 = _active_active_active_active_T_592 | _active_active_active_active_T_599; // @[VCommon.scala 93:68]
   wire [63:0] _active_active_active_T_465 = f_io_entry_6_bits_tin_vt_valid ? active_active_active_active_19 : 64'h0; // @[Library.scala 8:8]
-  wire [63:0] _active_active_active_T_466 = _active_active_active_T_460 | _active_active_active_T_465; // @[VAlu.scala 253:74]
+  wire [63:0] _active_active_active_T_466 = _active_active_active_T_460 | _active_active_active_T_465; // @[VAlu.scala 233:74]
   wire [3:0] active_active_active_oh_shiftAmount_20 = f_io_entry_6_bits_tin_vu_addr[5:2]; // @[VCommon.scala 13:27]
   wire [15:0] active_active_active_oh_20 = 16'h1 << active_active_active_oh_shiftAmount_20; // @[OneHot.scala 64:12]
   wire [15:0] active_active_active_oh0_lo_lo_20 = {3'h0,active_active_active_oh_20[3],3'h0,active_active_active_oh_20[2]
@@ -57039,7 +47481,7 @@
     ; // @[Library.scala 18:8]
   wire [63:0] active_active_active_active_20 = _active_active_active_active_T_622 | _active_active_active_active_T_629; // @[VCommon.scala 93:68]
   wire [63:0] _active_active_active_T_471 = f_io_entry_6_bits_tin_vu_valid ? active_active_active_active_20 : 64'h0; // @[Library.scala 8:8]
-  wire [63:0] active_active_active_18 = _active_active_active_T_466 | _active_active_active_T_471; // @[VAlu.scala 254:74]
+  wire [63:0] active_active_active_18 = _active_active_active_T_466 | _active_active_active_T_471; // @[VAlu.scala 234:74]
   wire [63:0] active_active_10 = f_io_entry_6_valid ? active_active_active_18 : 64'h0; // @[Library.scala 8:8]
   wire [63:0] _active_T_33 = _active_T_32 | active_active_10; // @[VCmdq.scala 91:24]
   wire [3:0] active_active_active_oh_shiftAmount_21 = f_io_entry_7_bits_tin_vs_addr[5:2]; // @[VCommon.scala 13:27]
@@ -57194,7 +47636,7 @@
     ; // @[Library.scala 18:8]
   wire [63:0] active_active_active_active_22 = _active_active_active_active_T_682 | _active_active_active_active_T_689; // @[VCommon.scala 93:68]
   wire [63:0] _active_active_active_T_481 = f_io_entry_7_bits_tin_vt_valid ? active_active_active_active_22 : 64'h0; // @[Library.scala 8:8]
-  wire [63:0] _active_active_active_T_482 = _active_active_active_T_476 | _active_active_active_T_481; // @[VAlu.scala 253:74]
+  wire [63:0] _active_active_active_T_482 = _active_active_active_T_476 | _active_active_active_T_481; // @[VAlu.scala 233:74]
   wire [3:0] active_active_active_oh_shiftAmount_23 = f_io_entry_7_bits_tin_vu_addr[5:2]; // @[VCommon.scala 13:27]
   wire [15:0] active_active_active_oh_23 = 16'h1 << active_active_active_oh_shiftAmount_23; // @[OneHot.scala 64:12]
   wire [15:0] active_active_active_oh0_lo_lo_23 = {3'h0,active_active_active_oh_23[3],3'h0,active_active_active_oh_23[2]
@@ -57270,7 +47712,7 @@
     ; // @[Library.scala 18:8]
   wire [63:0] active_active_active_active_23 = _active_active_active_active_T_712 | _active_active_active_active_T_719; // @[VCommon.scala 93:68]
   wire [63:0] _active_active_active_T_487 = f_io_entry_7_bits_tin_vu_valid ? active_active_active_active_23 : 64'h0; // @[Library.scala 8:8]
-  wire [63:0] active_active_active_19 = _active_active_active_T_482 | _active_active_active_T_487; // @[VAlu.scala 254:74]
+  wire [63:0] active_active_active_19 = _active_active_active_T_482 | _active_active_active_T_487; // @[VAlu.scala 234:74]
   wire [63:0] active_active_11 = f_io_entry_7_valid ? active_active_active_19 : 64'h0; // @[Library.scala 8:8]
   wire [63:0] _active_T_34 = _active_T_33 | active_active_11; // @[VCmdq.scala 91:24]
   wire [5:0] _active_active0_T = {{1'd0}, step}; // @[VCmdq.scala 94:48]
@@ -57423,7 +47865,7 @@
     ; // @[Library.scala 18:8]
   wire [63:0] active_active0_active_active_1 = _active_active0_active_active_T_52 | _active_active0_active_active_T_59; // @[VCommon.scala 93:68]
   wire [63:0] _active_active0_active_T_11 = value_tin_vt_valid ? active_active0_active_active_1 : 64'h0; // @[Library.scala 8:8]
-  wire [63:0] _active_active0_active_T_12 = _active_active0_active_T_5 | _active_active0_active_T_11; // @[VAlu.scala 253:74]
+  wire [63:0] _active_active0_active_T_12 = _active_active0_active_T_5 | _active_active0_active_T_11; // @[VAlu.scala 233:74]
   wire [3:0] active_active0_active_oh_shiftAmount_2 = value_tin_vu_addr[5:2]; // @[VCommon.scala 13:27]
   wire [15:0] active_active0_active_oh_2 = 16'h1 << active_active0_active_oh_shiftAmount_2; // @[OneHot.scala 64:12]
   wire [15:0] active_active0_active_oh0_lo_lo_2 = {3'h0,active_active0_active_oh_2[3],3'h0,active_active0_active_oh_2[2]
@@ -57499,7 +47941,7 @@
     ; // @[Library.scala 18:8]
   wire [63:0] active_active0_active_active_2 = _active_active0_active_active_T_82 | _active_active0_active_active_T_89; // @[VCommon.scala 93:68]
   wire [63:0] _active_active0_active_T_18 = value_tin_vu_valid ? active_active0_active_active_2 : 64'h0; // @[Library.scala 8:8]
-  wire [63:0] active_active0 = _active_active0_active_T_12 | _active_active0_active_T_18; // @[VAlu.scala 254:74]
+  wire [63:0] active_active0 = _active_active0_active_T_12 | _active_active0_active_T_18; // @[VAlu.scala 234:74]
   wire  _active_active1_active_active_T_5 = _last_T & active_active0_active_idx == 2'h0 | value_m & _step_T_1[2:0] <= 3'h0
     ; // @[VCommon.scala 91:42]
   wire [63:0] _active_active1_active_active_T_6 = _active_active1_active_active_T_5 ? active_active0_active_oh0 : 64'h0; // @[Library.scala 18:8]
@@ -57543,7 +47985,7 @@
     ; // @[Library.scala 18:8]
   wire [63:0] active_active1_active_active_1 = _active_active1_active_active_T_52 | _active_active1_active_active_T_59; // @[VCommon.scala 93:68]
   wire [63:0] _active_active1_active_T_11 = value_tin_vt_valid ? active_active1_active_active_1 : 64'h0; // @[Library.scala 8:8]
-  wire [63:0] _active_active1_active_T_12 = _active_active1_active_T_5 | _active_active1_active_T_11; // @[VAlu.scala 253:74]
+  wire [63:0] _active_active1_active_T_12 = _active_active1_active_T_5 | _active_active1_active_T_11; // @[VAlu.scala 233:74]
   wire  _active_active1_active_active_T_65 = _last_T & active_active0_active_idx_2 == 2'h0 | value_m & _step_T_1[2:0]
      <= 3'h0; // @[VCommon.scala 91:42]
   wire [63:0] _active_active1_active_active_T_66 = _active_active1_active_active_T_65 ? active_active0_active_oh0_2 : 64'h0
@@ -57566,14 +48008,14 @@
     ; // @[Library.scala 18:8]
   wire [63:0] active_active1_active_active_2 = _active_active1_active_active_T_82 | _active_active1_active_active_T_89; // @[VCommon.scala 93:68]
   wire [63:0] _active_active1_active_T_18 = value_tin_vu_valid ? active_active1_active_active_2 : 64'h0; // @[Library.scala 8:8]
-  wire [63:0] active_active1 = _active_active1_active_T_12 | _active_active1_active_T_18; // @[VAlu.scala 254:74]
+  wire [63:0] active_active1 = _active_active1_active_T_12 | _active_active1_active_T_18; // @[VAlu.scala 234:74]
   wire  _active_active_T_96 = ~io_out_ready; // @[VCmdq.scala 96:36]
   wire  _active_active_T_99 = valid & (~io_out_ready | _T_10); // @[VCmdq.scala 96:32]
   wire [63:0] _active_active_T_101 = _active_active_T_96 ? active_active0 : active_active1; // @[VCmdq.scala 97:29]
   wire [63:0] active_active_12 = _active_active_T_99 ? _active_active_T_101 : 64'h0; // @[Library.scala 8:8]
   wire [63:0] _active_T_35 = _active_T_34 | active_active_12; // @[VCmdq.scala 98:12]
   wire [63:0] _active_T_36 = _active_T_26 | _active_T_35; // @[VCmdq.scala 111:90]
-  wire  _GEN_149 = _T_14 & _T_6; // @[VAlu.scala 251:11]
+  wire  _GEN_149 = _T_14 & _T_6; // @[VAlu.scala 231:11]
   Fifo4e f ( // @[Fifo4e.scala 10:11]
     .clock(f_clock),
     .reset(f_reset),
@@ -57764,124 +48206,124 @@
   assign f_reset = reset;
   assign f_io_in_valid = io_in_valid; // @[VCmdq.scala 48:17]
   assign f_io_in_bits_0_valid = io_in_bits_0_valid; // @[VCmdq.scala 52:27]
-  assign f_io_in_bits_0_bits_tin_op = io_in_bits_0_bits_op; // @[VAlu.scala 190:19 191:12]
-  assign f_io_in_bits_0_bits_tin_f2 = io_in_bits_0_bits_f2; // @[VAlu.scala 190:19 192:12]
-  assign f_io_in_bits_0_bits_tin_sz = io_in_bits_0_bits_sz; // @[VAlu.scala 190:19 193:12]
+  assign f_io_in_bits_0_bits_tin_op = io_in_bits_0_bits_op; // @[VAlu.scala 170:19 171:12]
+  assign f_io_in_bits_0_bits_tin_f2 = io_in_bits_0_bits_f2; // @[VAlu.scala 170:19 172:12]
+  assign f_io_in_bits_0_bits_tin_sz = io_in_bits_0_bits_sz; // @[VAlu.scala 170:19 173:12]
   assign f_io_in_bits_0_bits_tin_vd_addr = ~io_in_bits_0_bits_cmdsync ? io_in_bits_0_bits_vd_addr :
-    io_in_bits_0_bits_vf_addr; // @[VAlu.scala 195:40 196:14 202:14]
+    io_in_bits_0_bits_vf_addr; // @[VAlu.scala 175:40 176:14 182:14]
   assign f_io_in_bits_0_bits_tin_ve_addr = ~io_in_bits_0_bits_cmdsync ? io_in_bits_0_bits_ve_addr :
-    io_in_bits_0_bits_vg_addr; // @[VAlu.scala 195:40 197:14 203:14]
+    io_in_bits_0_bits_vg_addr; // @[VAlu.scala 175:40 177:14 183:14]
   assign f_io_in_bits_0_bits_tin_vs_valid = ~io_in_bits_0_bits_cmdsync ? io_in_bits_0_bits_vs_valid :
-    io_in_bits_0_bits_vx_valid; // @[VAlu.scala 195:40 198:14 204:14]
+    io_in_bits_0_bits_vx_valid; // @[VAlu.scala 175:40 178:14 184:14]
   assign f_io_in_bits_0_bits_tin_vs_addr = ~io_in_bits_0_bits_cmdsync ? io_in_bits_0_bits_vs_addr :
-    io_in_bits_0_bits_vx_addr; // @[VAlu.scala 195:40 198:14 204:14]
+    io_in_bits_0_bits_vx_addr; // @[VAlu.scala 175:40 178:14 184:14]
   assign f_io_in_bits_0_bits_tin_vs_tag = ~io_in_bits_0_bits_cmdsync ? io_in_bits_0_bits_vs_tag :
-    io_in_bits_0_bits_vx_tag; // @[VAlu.scala 195:40 198:14 204:14]
+    io_in_bits_0_bits_vx_tag; // @[VAlu.scala 175:40 178:14 184:14]
   assign f_io_in_bits_0_bits_tin_vt_valid = ~io_in_bits_0_bits_cmdsync ? io_in_bits_0_bits_vt_valid :
-    io_in_bits_0_bits_vy_valid; // @[VAlu.scala 195:40 199:14 205:14]
+    io_in_bits_0_bits_vy_valid; // @[VAlu.scala 175:40 179:14 185:14]
   assign f_io_in_bits_0_bits_tin_vt_addr = ~io_in_bits_0_bits_cmdsync ? io_in_bits_0_bits_vt_addr :
-    io_in_bits_0_bits_vy_addr; // @[VAlu.scala 195:40 199:14 205:14]
+    io_in_bits_0_bits_vy_addr; // @[VAlu.scala 175:40 179:14 185:14]
   assign f_io_in_bits_0_bits_tin_vt_tag = ~io_in_bits_0_bits_cmdsync ? io_in_bits_0_bits_vt_tag :
-    io_in_bits_0_bits_vy_tag; // @[VAlu.scala 195:40 199:14 205:14]
+    io_in_bits_0_bits_vy_tag; // @[VAlu.scala 175:40 179:14 185:14]
   assign f_io_in_bits_0_bits_tin_vu_valid = ~io_in_bits_0_bits_cmdsync ? io_in_bits_0_bits_vu_valid :
-    io_in_bits_0_bits_vz_valid; // @[VAlu.scala 195:40 200:14 206:14]
+    io_in_bits_0_bits_vz_valid; // @[VAlu.scala 175:40 180:14 186:14]
   assign f_io_in_bits_0_bits_tin_vu_addr = ~io_in_bits_0_bits_cmdsync ? io_in_bits_0_bits_vu_addr :
-    io_in_bits_0_bits_vz_addr; // @[VAlu.scala 195:40 200:14 206:14]
+    io_in_bits_0_bits_vz_addr; // @[VAlu.scala 175:40 180:14 186:14]
   assign f_io_in_bits_0_bits_tin_vu_tag = ~io_in_bits_0_bits_cmdsync ? io_in_bits_0_bits_vu_tag :
-    io_in_bits_0_bits_vz_tag; // @[VAlu.scala 195:40 200:14 206:14]
-  assign f_io_in_bits_0_bits_tin_sv_valid = io_in_bits_0_bits_sv_valid; // @[VAlu.scala 190:19 208:12]
-  assign f_io_in_bits_0_bits_tin_sv_data = io_in_bits_0_bits_sv_data; // @[VAlu.scala 190:19 208:12]
-  assign f_io_in_bits_0_bits_tin_cmdsync = io_in_bits_0_bits_cmdsync; // @[VAlu.scala 190:19 194:17]
+    io_in_bits_0_bits_vz_tag; // @[VAlu.scala 175:40 180:14 186:14]
+  assign f_io_in_bits_0_bits_tin_sv_valid = io_in_bits_0_bits_sv_valid; // @[VAlu.scala 170:19 188:12]
+  assign f_io_in_bits_0_bits_tin_sv_data = io_in_bits_0_bits_sv_data; // @[VAlu.scala 170:19 188:12]
+  assign f_io_in_bits_0_bits_tin_cmdsync = io_in_bits_0_bits_cmdsync; // @[VAlu.scala 170:19 174:17]
   assign f_io_in_bits_0_bits_m = io_in_bits_0_bits_m; // @[VCmdq.scala 54:28]
   assign f_io_in_bits_1_valid = io_in_bits_1_valid; // @[VCmdq.scala 52:27]
-  assign f_io_in_bits_1_bits_tin_op = io_in_bits_1_bits_op; // @[VAlu.scala 190:19 191:12]
-  assign f_io_in_bits_1_bits_tin_f2 = io_in_bits_1_bits_f2; // @[VAlu.scala 190:19 192:12]
-  assign f_io_in_bits_1_bits_tin_sz = io_in_bits_1_bits_sz; // @[VAlu.scala 190:19 193:12]
+  assign f_io_in_bits_1_bits_tin_op = io_in_bits_1_bits_op; // @[VAlu.scala 170:19 171:12]
+  assign f_io_in_bits_1_bits_tin_f2 = io_in_bits_1_bits_f2; // @[VAlu.scala 170:19 172:12]
+  assign f_io_in_bits_1_bits_tin_sz = io_in_bits_1_bits_sz; // @[VAlu.scala 170:19 173:12]
   assign f_io_in_bits_1_bits_tin_vd_addr = ~io_in_bits_1_bits_cmdsync ? io_in_bits_1_bits_vd_addr :
-    io_in_bits_1_bits_vf_addr; // @[VAlu.scala 195:40 196:14 202:14]
+    io_in_bits_1_bits_vf_addr; // @[VAlu.scala 175:40 176:14 182:14]
   assign f_io_in_bits_1_bits_tin_ve_addr = ~io_in_bits_1_bits_cmdsync ? io_in_bits_1_bits_ve_addr :
-    io_in_bits_1_bits_vg_addr; // @[VAlu.scala 195:40 197:14 203:14]
+    io_in_bits_1_bits_vg_addr; // @[VAlu.scala 175:40 177:14 183:14]
   assign f_io_in_bits_1_bits_tin_vs_valid = ~io_in_bits_1_bits_cmdsync ? io_in_bits_1_bits_vs_valid :
-    io_in_bits_1_bits_vx_valid; // @[VAlu.scala 195:40 198:14 204:14]
+    io_in_bits_1_bits_vx_valid; // @[VAlu.scala 175:40 178:14 184:14]
   assign f_io_in_bits_1_bits_tin_vs_addr = ~io_in_bits_1_bits_cmdsync ? io_in_bits_1_bits_vs_addr :
-    io_in_bits_1_bits_vx_addr; // @[VAlu.scala 195:40 198:14 204:14]
+    io_in_bits_1_bits_vx_addr; // @[VAlu.scala 175:40 178:14 184:14]
   assign f_io_in_bits_1_bits_tin_vs_tag = ~io_in_bits_1_bits_cmdsync ? io_in_bits_1_bits_vs_tag :
-    io_in_bits_1_bits_vx_tag; // @[VAlu.scala 195:40 198:14 204:14]
+    io_in_bits_1_bits_vx_tag; // @[VAlu.scala 175:40 178:14 184:14]
   assign f_io_in_bits_1_bits_tin_vt_valid = ~io_in_bits_1_bits_cmdsync ? io_in_bits_1_bits_vt_valid :
-    io_in_bits_1_bits_vy_valid; // @[VAlu.scala 195:40 199:14 205:14]
+    io_in_bits_1_bits_vy_valid; // @[VAlu.scala 175:40 179:14 185:14]
   assign f_io_in_bits_1_bits_tin_vt_addr = ~io_in_bits_1_bits_cmdsync ? io_in_bits_1_bits_vt_addr :
-    io_in_bits_1_bits_vy_addr; // @[VAlu.scala 195:40 199:14 205:14]
+    io_in_bits_1_bits_vy_addr; // @[VAlu.scala 175:40 179:14 185:14]
   assign f_io_in_bits_1_bits_tin_vt_tag = ~io_in_bits_1_bits_cmdsync ? io_in_bits_1_bits_vt_tag :
-    io_in_bits_1_bits_vy_tag; // @[VAlu.scala 195:40 199:14 205:14]
+    io_in_bits_1_bits_vy_tag; // @[VAlu.scala 175:40 179:14 185:14]
   assign f_io_in_bits_1_bits_tin_vu_valid = ~io_in_bits_1_bits_cmdsync ? io_in_bits_1_bits_vu_valid :
-    io_in_bits_1_bits_vz_valid; // @[VAlu.scala 195:40 200:14 206:14]
+    io_in_bits_1_bits_vz_valid; // @[VAlu.scala 175:40 180:14 186:14]
   assign f_io_in_bits_1_bits_tin_vu_addr = ~io_in_bits_1_bits_cmdsync ? io_in_bits_1_bits_vu_addr :
-    io_in_bits_1_bits_vz_addr; // @[VAlu.scala 195:40 200:14 206:14]
+    io_in_bits_1_bits_vz_addr; // @[VAlu.scala 175:40 180:14 186:14]
   assign f_io_in_bits_1_bits_tin_vu_tag = ~io_in_bits_1_bits_cmdsync ? io_in_bits_1_bits_vu_tag :
-    io_in_bits_1_bits_vz_tag; // @[VAlu.scala 195:40 200:14 206:14]
-  assign f_io_in_bits_1_bits_tin_sv_valid = io_in_bits_1_bits_sv_valid; // @[VAlu.scala 190:19 208:12]
-  assign f_io_in_bits_1_bits_tin_sv_data = io_in_bits_1_bits_sv_data; // @[VAlu.scala 190:19 208:12]
-  assign f_io_in_bits_1_bits_tin_cmdsync = io_in_bits_1_bits_cmdsync; // @[VAlu.scala 190:19 194:17]
+    io_in_bits_1_bits_vz_tag; // @[VAlu.scala 175:40 180:14 186:14]
+  assign f_io_in_bits_1_bits_tin_sv_valid = io_in_bits_1_bits_sv_valid; // @[VAlu.scala 170:19 188:12]
+  assign f_io_in_bits_1_bits_tin_sv_data = io_in_bits_1_bits_sv_data; // @[VAlu.scala 170:19 188:12]
+  assign f_io_in_bits_1_bits_tin_cmdsync = io_in_bits_1_bits_cmdsync; // @[VAlu.scala 170:19 174:17]
   assign f_io_in_bits_1_bits_m = io_in_bits_1_bits_m; // @[VCmdq.scala 54:28]
   assign f_io_in_bits_2_valid = io_in_bits_2_valid; // @[VCmdq.scala 52:27]
-  assign f_io_in_bits_2_bits_tin_op = io_in_bits_2_bits_op; // @[VAlu.scala 190:19 191:12]
-  assign f_io_in_bits_2_bits_tin_f2 = io_in_bits_2_bits_f2; // @[VAlu.scala 190:19 192:12]
-  assign f_io_in_bits_2_bits_tin_sz = io_in_bits_2_bits_sz; // @[VAlu.scala 190:19 193:12]
+  assign f_io_in_bits_2_bits_tin_op = io_in_bits_2_bits_op; // @[VAlu.scala 170:19 171:12]
+  assign f_io_in_bits_2_bits_tin_f2 = io_in_bits_2_bits_f2; // @[VAlu.scala 170:19 172:12]
+  assign f_io_in_bits_2_bits_tin_sz = io_in_bits_2_bits_sz; // @[VAlu.scala 170:19 173:12]
   assign f_io_in_bits_2_bits_tin_vd_addr = ~io_in_bits_2_bits_cmdsync ? io_in_bits_2_bits_vd_addr :
-    io_in_bits_2_bits_vf_addr; // @[VAlu.scala 195:40 196:14 202:14]
+    io_in_bits_2_bits_vf_addr; // @[VAlu.scala 175:40 176:14 182:14]
   assign f_io_in_bits_2_bits_tin_ve_addr = ~io_in_bits_2_bits_cmdsync ? io_in_bits_2_bits_ve_addr :
-    io_in_bits_2_bits_vg_addr; // @[VAlu.scala 195:40 197:14 203:14]
+    io_in_bits_2_bits_vg_addr; // @[VAlu.scala 175:40 177:14 183:14]
   assign f_io_in_bits_2_bits_tin_vs_valid = ~io_in_bits_2_bits_cmdsync ? io_in_bits_2_bits_vs_valid :
-    io_in_bits_2_bits_vx_valid; // @[VAlu.scala 195:40 198:14 204:14]
+    io_in_bits_2_bits_vx_valid; // @[VAlu.scala 175:40 178:14 184:14]
   assign f_io_in_bits_2_bits_tin_vs_addr = ~io_in_bits_2_bits_cmdsync ? io_in_bits_2_bits_vs_addr :
-    io_in_bits_2_bits_vx_addr; // @[VAlu.scala 195:40 198:14 204:14]
+    io_in_bits_2_bits_vx_addr; // @[VAlu.scala 175:40 178:14 184:14]
   assign f_io_in_bits_2_bits_tin_vs_tag = ~io_in_bits_2_bits_cmdsync ? io_in_bits_2_bits_vs_tag :
-    io_in_bits_2_bits_vx_tag; // @[VAlu.scala 195:40 198:14 204:14]
+    io_in_bits_2_bits_vx_tag; // @[VAlu.scala 175:40 178:14 184:14]
   assign f_io_in_bits_2_bits_tin_vt_valid = ~io_in_bits_2_bits_cmdsync ? io_in_bits_2_bits_vt_valid :
-    io_in_bits_2_bits_vy_valid; // @[VAlu.scala 195:40 199:14 205:14]
+    io_in_bits_2_bits_vy_valid; // @[VAlu.scala 175:40 179:14 185:14]
   assign f_io_in_bits_2_bits_tin_vt_addr = ~io_in_bits_2_bits_cmdsync ? io_in_bits_2_bits_vt_addr :
-    io_in_bits_2_bits_vy_addr; // @[VAlu.scala 195:40 199:14 205:14]
+    io_in_bits_2_bits_vy_addr; // @[VAlu.scala 175:40 179:14 185:14]
   assign f_io_in_bits_2_bits_tin_vt_tag = ~io_in_bits_2_bits_cmdsync ? io_in_bits_2_bits_vt_tag :
-    io_in_bits_2_bits_vy_tag; // @[VAlu.scala 195:40 199:14 205:14]
+    io_in_bits_2_bits_vy_tag; // @[VAlu.scala 175:40 179:14 185:14]
   assign f_io_in_bits_2_bits_tin_vu_valid = ~io_in_bits_2_bits_cmdsync ? io_in_bits_2_bits_vu_valid :
-    io_in_bits_2_bits_vz_valid; // @[VAlu.scala 195:40 200:14 206:14]
+    io_in_bits_2_bits_vz_valid; // @[VAlu.scala 175:40 180:14 186:14]
   assign f_io_in_bits_2_bits_tin_vu_addr = ~io_in_bits_2_bits_cmdsync ? io_in_bits_2_bits_vu_addr :
-    io_in_bits_2_bits_vz_addr; // @[VAlu.scala 195:40 200:14 206:14]
+    io_in_bits_2_bits_vz_addr; // @[VAlu.scala 175:40 180:14 186:14]
   assign f_io_in_bits_2_bits_tin_vu_tag = ~io_in_bits_2_bits_cmdsync ? io_in_bits_2_bits_vu_tag :
-    io_in_bits_2_bits_vz_tag; // @[VAlu.scala 195:40 200:14 206:14]
-  assign f_io_in_bits_2_bits_tin_sv_valid = io_in_bits_2_bits_sv_valid; // @[VAlu.scala 190:19 208:12]
-  assign f_io_in_bits_2_bits_tin_sv_data = io_in_bits_2_bits_sv_data; // @[VAlu.scala 190:19 208:12]
-  assign f_io_in_bits_2_bits_tin_cmdsync = io_in_bits_2_bits_cmdsync; // @[VAlu.scala 190:19 194:17]
+    io_in_bits_2_bits_vz_tag; // @[VAlu.scala 175:40 180:14 186:14]
+  assign f_io_in_bits_2_bits_tin_sv_valid = io_in_bits_2_bits_sv_valid; // @[VAlu.scala 170:19 188:12]
+  assign f_io_in_bits_2_bits_tin_sv_data = io_in_bits_2_bits_sv_data; // @[VAlu.scala 170:19 188:12]
+  assign f_io_in_bits_2_bits_tin_cmdsync = io_in_bits_2_bits_cmdsync; // @[VAlu.scala 170:19 174:17]
   assign f_io_in_bits_2_bits_m = io_in_bits_2_bits_m; // @[VCmdq.scala 54:28]
   assign f_io_in_bits_3_valid = io_in_bits_3_valid; // @[VCmdq.scala 52:27]
-  assign f_io_in_bits_3_bits_tin_op = io_in_bits_3_bits_op; // @[VAlu.scala 190:19 191:12]
-  assign f_io_in_bits_3_bits_tin_f2 = io_in_bits_3_bits_f2; // @[VAlu.scala 190:19 192:12]
-  assign f_io_in_bits_3_bits_tin_sz = io_in_bits_3_bits_sz; // @[VAlu.scala 190:19 193:12]
+  assign f_io_in_bits_3_bits_tin_op = io_in_bits_3_bits_op; // @[VAlu.scala 170:19 171:12]
+  assign f_io_in_bits_3_bits_tin_f2 = io_in_bits_3_bits_f2; // @[VAlu.scala 170:19 172:12]
+  assign f_io_in_bits_3_bits_tin_sz = io_in_bits_3_bits_sz; // @[VAlu.scala 170:19 173:12]
   assign f_io_in_bits_3_bits_tin_vd_addr = ~io_in_bits_3_bits_cmdsync ? io_in_bits_3_bits_vd_addr :
-    io_in_bits_3_bits_vf_addr; // @[VAlu.scala 195:40 196:14 202:14]
+    io_in_bits_3_bits_vf_addr; // @[VAlu.scala 175:40 176:14 182:14]
   assign f_io_in_bits_3_bits_tin_ve_addr = ~io_in_bits_3_bits_cmdsync ? io_in_bits_3_bits_ve_addr :
-    io_in_bits_3_bits_vg_addr; // @[VAlu.scala 195:40 197:14 203:14]
+    io_in_bits_3_bits_vg_addr; // @[VAlu.scala 175:40 177:14 183:14]
   assign f_io_in_bits_3_bits_tin_vs_valid = ~io_in_bits_3_bits_cmdsync ? io_in_bits_3_bits_vs_valid :
-    io_in_bits_3_bits_vx_valid; // @[VAlu.scala 195:40 198:14 204:14]
+    io_in_bits_3_bits_vx_valid; // @[VAlu.scala 175:40 178:14 184:14]
   assign f_io_in_bits_3_bits_tin_vs_addr = ~io_in_bits_3_bits_cmdsync ? io_in_bits_3_bits_vs_addr :
-    io_in_bits_3_bits_vx_addr; // @[VAlu.scala 195:40 198:14 204:14]
+    io_in_bits_3_bits_vx_addr; // @[VAlu.scala 175:40 178:14 184:14]
   assign f_io_in_bits_3_bits_tin_vs_tag = ~io_in_bits_3_bits_cmdsync ? io_in_bits_3_bits_vs_tag :
-    io_in_bits_3_bits_vx_tag; // @[VAlu.scala 195:40 198:14 204:14]
+    io_in_bits_3_bits_vx_tag; // @[VAlu.scala 175:40 178:14 184:14]
   assign f_io_in_bits_3_bits_tin_vt_valid = ~io_in_bits_3_bits_cmdsync ? io_in_bits_3_bits_vt_valid :
-    io_in_bits_3_bits_vy_valid; // @[VAlu.scala 195:40 199:14 205:14]
+    io_in_bits_3_bits_vy_valid; // @[VAlu.scala 175:40 179:14 185:14]
   assign f_io_in_bits_3_bits_tin_vt_addr = ~io_in_bits_3_bits_cmdsync ? io_in_bits_3_bits_vt_addr :
-    io_in_bits_3_bits_vy_addr; // @[VAlu.scala 195:40 199:14 205:14]
+    io_in_bits_3_bits_vy_addr; // @[VAlu.scala 175:40 179:14 185:14]
   assign f_io_in_bits_3_bits_tin_vt_tag = ~io_in_bits_3_bits_cmdsync ? io_in_bits_3_bits_vt_tag :
-    io_in_bits_3_bits_vy_tag; // @[VAlu.scala 195:40 199:14 205:14]
+    io_in_bits_3_bits_vy_tag; // @[VAlu.scala 175:40 179:14 185:14]
   assign f_io_in_bits_3_bits_tin_vu_valid = ~io_in_bits_3_bits_cmdsync ? io_in_bits_3_bits_vu_valid :
-    io_in_bits_3_bits_vz_valid; // @[VAlu.scala 195:40 200:14 206:14]
+    io_in_bits_3_bits_vz_valid; // @[VAlu.scala 175:40 180:14 186:14]
   assign f_io_in_bits_3_bits_tin_vu_addr = ~io_in_bits_3_bits_cmdsync ? io_in_bits_3_bits_vu_addr :
-    io_in_bits_3_bits_vz_addr; // @[VAlu.scala 195:40 200:14 206:14]
+    io_in_bits_3_bits_vz_addr; // @[VAlu.scala 175:40 180:14 186:14]
   assign f_io_in_bits_3_bits_tin_vu_tag = ~io_in_bits_3_bits_cmdsync ? io_in_bits_3_bits_vu_tag :
-    io_in_bits_3_bits_vz_tag; // @[VAlu.scala 195:40 200:14 206:14]
-  assign f_io_in_bits_3_bits_tin_sv_valid = io_in_bits_3_bits_sv_valid; // @[VAlu.scala 190:19 208:12]
-  assign f_io_in_bits_3_bits_tin_sv_data = io_in_bits_3_bits_sv_data; // @[VAlu.scala 190:19 208:12]
-  assign f_io_in_bits_3_bits_tin_cmdsync = io_in_bits_3_bits_cmdsync; // @[VAlu.scala 190:19 194:17]
+    io_in_bits_3_bits_vz_tag; // @[VAlu.scala 175:40 180:14 186:14]
+  assign f_io_in_bits_3_bits_tin_sv_valid = io_in_bits_3_bits_sv_valid; // @[VAlu.scala 170:19 188:12]
+  assign f_io_in_bits_3_bits_tin_sv_data = io_in_bits_3_bits_sv_data; // @[VAlu.scala 170:19 188:12]
+  assign f_io_in_bits_3_bits_tin_cmdsync = io_in_bits_3_bits_cmdsync; // @[VAlu.scala 170:19 174:17]
   assign f_io_in_bits_3_bits_m = io_in_bits_3_bits_m; // @[VCmdq.scala 54:28]
   assign f_io_out_ready = ~valid | io_out_ready & last; // @[VCmdq.scala 57:28]
   always @(posedge clock) begin
@@ -58050,7 +48492,7 @@
       if (`STOP_COND) begin
     `endif
         if (vzip & ~reset & ~(value_tin_ve_addr == _out_vd_addr_T_1)) begin
-          $fatal; // @[VAlu.scala 242:13]
+          $fatal; // @[VAlu.scala 222:13]
         end
     `ifdef STOP_COND
       end
@@ -58061,7 +48503,7 @@
       if (`PRINTF_COND) begin
     `endif
         if (vzip & ~reset & ~(value_tin_ve_addr == _out_vd_addr_T_1)) begin
-          $fwrite(32'h80000002,"Assertion failed\n    at VAlu.scala:242 assert(in.ve.addr === (in.vd.addr + 1.U))\n"); // @[VAlu.scala 242:13]
+          $fwrite(32'h80000002,"Assertion failed\n    at VAlu.scala:222 assert(in.ve.addr === (in.vd.addr + 1.U))\n"); // @[VAlu.scala 222:13]
         end
     `ifdef PRINTF_COND
       end
@@ -58072,7 +48514,7 @@
       if (`STOP_COND) begin
     `endif
         if (_T_14 & _T_6 & ~(_active_active0_T[4:0] <= 5'h4)) begin
-          $fatal; // @[VAlu.scala 251:11]
+          $fatal; // @[VAlu.scala 231:11]
         end
     `ifdef STOP_COND
       end
@@ -58083,7 +48525,7 @@
       if (`PRINTF_COND) begin
     `endif
         if (_T_14 & _T_6 & ~(_active_active0_T[4:0] <= 5'h4)) begin
-          $fwrite(32'h80000002,"Assertion failed\n    at VAlu.scala:251 assert(step <= 4.U)\n"); // @[VAlu.scala 251:11]
+          $fwrite(32'h80000002,"Assertion failed\n    at VAlu.scala:231 assert(step <= 4.U)\n"); // @[VAlu.scala 231:11]
         end
     `ifdef PRINTF_COND
       end
@@ -58160,7 +48602,7 @@
       if (`STOP_COND) begin
     `endif
         if (_T_14 & _T_6 & ~(_step_T_1 <= 5'h4)) begin
-          $fatal; // @[VAlu.scala 251:11]
+          $fatal; // @[VAlu.scala 231:11]
         end
     `ifdef STOP_COND
       end
@@ -58171,7 +48613,7 @@
       if (`PRINTF_COND) begin
     `endif
         if (_T_14 & _T_6 & ~(_step_T_1 <= 5'h4)) begin
-          $fwrite(32'h80000002,"Assertion failed\n    at VAlu.scala:251 assert(step <= 4.U)\n"); // @[VAlu.scala 251:11]
+          $fwrite(32'h80000002,"Assertion failed\n    at VAlu.scala:231 assert(step <= 4.U)\n"); // @[VAlu.scala 231:11]
         end
     `ifdef PRINTF_COND
       end
@@ -58919,7 +49361,7 @@
   wire [3:0] _log_clz_T_44 = _log_clz_T_29[2] ? 4'h2 : _log_clz_T_43; // @[Mux.scala 47:70]
   wire [3:0] _log_clz_T_45 = _log_clz_T_29[1] ? 4'h1 : _log_clz_T_44; // @[Mux.scala 47:70]
   wire [3:0] log_clz = _log_clz_T_29[0] ? 4'h0 : _log_clz_T_45; // @[Mux.scala 47:70]
-  wire [3:0] _log_T_33 = log_a[7] ? log_clo : log_clz; // @[Library.scala 274:8]
+  wire [3:0] _log_T_33 = log_a[7] ? log_clo : log_clz; // @[Library.scala 275:8]
   wire [3:0] _log_T_34 = io_in_sz[0] ? _log_T_33 : 4'h0; // @[Library.scala 18:8]
   wire [3:0] _log_T_35 = io_op_log_clb ? _log_T_34 : 4'h0; // @[Library.scala 18:8]
   wire [7:0] _GEN_24 = {{4'd0}, _log_T_35}; // @[VAluInt.scala 1359:81]
@@ -59404,7 +49846,7 @@
   wire [3:0] _log_clz_T_90 = _log_clz_T_75[2] ? 4'h2 : _log_clz_T_89; // @[Mux.scala 47:70]
   wire [3:0] _log_clz_T_91 = _log_clz_T_75[1] ? 4'h1 : _log_clz_T_90; // @[Mux.scala 47:70]
   wire [3:0] log_clz_1 = _log_clz_T_75[0] ? 4'h0 : _log_clz_T_91; // @[Mux.scala 47:70]
-  wire [3:0] _log_T_146 = log_a[15] ? log_clo_1 : log_clz_1; // @[Library.scala 274:8]
+  wire [3:0] _log_T_146 = log_a[15] ? log_clo_1 : log_clz_1; // @[Library.scala 275:8]
   wire [3:0] _log_T_147 = io_in_sz[0] ? _log_T_146 : 4'h0; // @[Library.scala 18:8]
   wire [3:0] _log_T_148 = io_op_log_clb ? _log_T_147 : 4'h0; // @[Library.scala 18:8]
   wire [7:0] _GEN_56 = {{4'd0}, _log_T_148}; // @[VAluInt.scala 1359:81]
@@ -59890,7 +50332,7 @@
   wire [3:0] _log_clz_T_136 = _log_clz_T_121[2] ? 4'h2 : _log_clz_T_135; // @[Mux.scala 47:70]
   wire [3:0] _log_clz_T_137 = _log_clz_T_121[1] ? 4'h1 : _log_clz_T_136; // @[Mux.scala 47:70]
   wire [3:0] log_clz_2 = _log_clz_T_121[0] ? 4'h0 : _log_clz_T_137; // @[Mux.scala 47:70]
-  wire [3:0] _log_T_259 = log_a[23] ? log_clo_2 : log_clz_2; // @[Library.scala 274:8]
+  wire [3:0] _log_T_259 = log_a[23] ? log_clo_2 : log_clz_2; // @[Library.scala 275:8]
   wire [3:0] _log_T_260 = io_in_sz[0] ? _log_T_259 : 4'h0; // @[Library.scala 18:8]
   wire [3:0] _log_T_261 = io_op_log_clb ? _log_T_260 : 4'h0; // @[Library.scala 18:8]
   wire [7:0] _GEN_88 = {{4'd0}, _log_T_261}; // @[VAluInt.scala 1359:81]
@@ -60376,7 +50818,7 @@
   wire [3:0] _log_clz_T_182 = _log_clz_T_167[2] ? 4'h2 : _log_clz_T_181; // @[Mux.scala 47:70]
   wire [3:0] _log_clz_T_183 = _log_clz_T_167[1] ? 4'h1 : _log_clz_T_182; // @[Mux.scala 47:70]
   wire [3:0] log_clz_3 = _log_clz_T_167[0] ? 4'h0 : _log_clz_T_183; // @[Mux.scala 47:70]
-  wire [3:0] _log_T_372 = log_a[31] ? log_clo_3 : log_clz_3; // @[Library.scala 274:8]
+  wire [3:0] _log_T_372 = log_a[31] ? log_clo_3 : log_clz_3; // @[Library.scala 275:8]
   wire [3:0] _log_T_373 = io_in_sz[0] ? _log_T_372 : 4'h0; // @[Library.scala 18:8]
   wire [3:0] _log_T_374 = io_op_log_clb ? _log_T_373 : 4'h0; // @[Library.scala 18:8]
   wire [7:0] _GEN_120 = {{4'd0}, _log_T_374}; // @[VAluInt.scala 1359:81]
@@ -60923,7 +51365,7 @@
   wire [4:0] _log_clz_T_254 = _log_clz_T_223[2] ? 5'h2 : _log_clz_T_253; // @[Mux.scala 47:70]
   wire [4:0] _log_clz_T_255 = _log_clz_T_223[1] ? 5'h1 : _log_clz_T_254; // @[Mux.scala 47:70]
   wire [4:0] log_clz_4 = _log_clz_T_223[0] ? 5'h0 : _log_clz_T_255; // @[Mux.scala 47:70]
-  wire [4:0] _log_T_485 = log_a_1[15] ? log_clo_4 : log_clz_4; // @[Library.scala 274:8]
+  wire [4:0] _log_T_485 = log_a_1[15] ? log_clo_4 : log_clz_4; // @[Library.scala 275:8]
   wire [4:0] _log_T_486 = io_in_sz[1] ? _log_T_485 : 5'h0; // @[Library.scala 18:8]
   wire [4:0] _log_T_487 = io_op_log_clb ? _log_T_486 : 5'h0; // @[Library.scala 18:8]
   wire [15:0] _GEN_153 = {{11'd0}, _log_T_487}; // @[VAluInt.scala 1359:81]
@@ -61442,7 +51884,7 @@
   wire [4:0] _log_clz_T_326 = _log_clz_T_295[2] ? 5'h2 : _log_clz_T_325; // @[Mux.scala 47:70]
   wire [4:0] _log_clz_T_327 = _log_clz_T_295[1] ? 5'h1 : _log_clz_T_326; // @[Mux.scala 47:70]
   wire [4:0] log_clz_5 = _log_clz_T_295[0] ? 5'h0 : _log_clz_T_327; // @[Mux.scala 47:70]
-  wire [4:0] _log_T_648 = log_a_1[31] ? log_clo_5 : log_clz_5; // @[Library.scala 274:8]
+  wire [4:0] _log_T_648 = log_a_1[31] ? log_clo_5 : log_clz_5; // @[Library.scala 275:8]
   wire [4:0] _log_T_649 = io_in_sz[1] ? _log_T_648 : 5'h0; // @[Library.scala 18:8]
   wire [4:0] _log_T_650 = io_op_log_clb ? _log_T_649 : 5'h0; // @[Library.scala 18:8]
   wire [15:0] _GEN_187 = {{11'd0}, _log_T_650}; // @[VAluInt.scala 1359:81]
@@ -61997,7 +52439,7 @@
   wire [5:0] _log_clz_T_440 = _log_clz_T_377[2] ? 6'h2 : _log_clz_T_439; // @[Mux.scala 47:70]
   wire [5:0] _log_clz_T_441 = _log_clz_T_377[1] ? 6'h1 : _log_clz_T_440; // @[Mux.scala 47:70]
   wire [5:0] log_clz_6 = _log_clz_T_377[0] ? 6'h0 : _log_clz_T_441; // @[Mux.scala 47:70]
-  wire [5:0] _log_T_811 = log_a_2[31] ? log_clo_6 : log_clz_6; // @[Library.scala 274:8]
+  wire [5:0] _log_T_811 = log_a_2[31] ? log_clo_6 : log_clz_6; // @[Library.scala 275:8]
   wire [5:0] _log_T_812 = io_in_sz[2] ? _log_T_811 : 6'h0; // @[Library.scala 18:8]
   wire [5:0] _log_T_813 = io_op_log_clb ? _log_T_812 : 6'h0; // @[Library.scala 18:8]
   wire [31:0] _GEN_222 = {{26'd0}, _log_T_813}; // @[VAluInt.scala 1359:81]
@@ -64244,30 +54686,30 @@
   wire [2:0] _T_6 = _GEN_89 + _T_4; // @[Bitwise.scala 48:55]
   wire  _T_11 = ~reset; // @[VAluInt.scala 47:9]
   wire  e_absd = io_in_op == 7'hf; // @[VAluInt.scala 63:26]
-  wire  e_acc = io_in_op == 7'h37; // @[VAluInt.scala 64:26]
+  wire  e_acc = io_in_op == 7'h35; // @[VAluInt.scala 64:26]
   wire  e_dup = io_in_op == 7'h1; // @[VAluInt.scala 65:26]
   wire  e_max = io_in_op == 7'h10; // @[VAluInt.scala 66:26]
   wire  e_min = io_in_op == 7'h11; // @[VAluInt.scala 67:26]
   wire  e_rsub = io_in_op == 7'h8; // @[VAluInt.scala 68:26]
   wire  e_srans = io_in_op == 7'h25; // @[VAluInt.scala 69:26]
-  wire  e_sraqs = io_in_op == 7'h26; // @[VAluInt.scala 70:40]
-  wire  _e_slidevn_T_3 = io_in_op == 7'h58; // @[VAluInt.scala 72:86]
-  wire  e_slidevn = io_in_op == 7'h56 | io_in_op == 7'h57 | io_in_op == 7'h58; // @[VAluInt.scala 72:74]
-  wire  _e_slidevp_T_3 = io_in_op == 7'h5b; // @[VAluInt.scala 73:86]
-  wire  e_slidevp = io_in_op == 7'h59 | io_in_op == 7'h5a | io_in_op == 7'h5b; // @[VAluInt.scala 73:74]
-  wire  e_sel = io_in_op == 7'h5c; // @[VAluInt.scala 76:24]
-  wire  _e_evn_T_1 = io_in_op == 7'h5f; // @[VAluInt.scala 77:49]
-  wire  e_evn = io_in_op == 7'h5d | io_in_op == 7'h5f; // @[VAluInt.scala 77:37]
-  wire  e_odd = io_in_op == 7'h5e | _e_evn_T_1; // @[VAluInt.scala 78:37]
-  wire  e_zip = io_in_op == 7'h60; // @[VAluInt.scala 79:24]
+  wire  e_sraqs = io_in_op == 7'h26; // @[VAluInt.scala 70:42]
+  wire  _e_slidevn_T_3 = io_in_op == 7'h3c; // @[VAluInt.scala 72:86]
+  wire  e_slidevn = io_in_op == 7'h3a | io_in_op == 7'h3b | io_in_op == 7'h3c; // @[VAluInt.scala 72:74]
+  wire  _e_slidevp_T_3 = io_in_op == 7'h3f; // @[VAluInt.scala 73:86]
+  wire  e_slidevp = io_in_op == 7'h3d | io_in_op == 7'h3e | io_in_op == 7'h3f; // @[VAluInt.scala 73:74]
+  wire  e_sel = io_in_op == 7'h40; // @[VAluInt.scala 76:24]
+  wire  _e_evn_T_1 = io_in_op == 7'h43; // @[VAluInt.scala 77:49]
+  wire  e_evn = io_in_op == 7'h41 | io_in_op == 7'h43; // @[VAluInt.scala 77:37]
+  wire  e_odd = io_in_op == 7'h42 | _e_evn_T_1; // @[VAluInt.scala 78:37]
+  wire  e_zip = io_in_op == 7'h44; // @[VAluInt.scala 79:24]
   wire  e_dwinit = io_in_op == 7'h21; // @[VAluInt.scala 81:27]
-  wire  _e_dwconv_T_1 = io_in_op == 7'h64; // @[VAluInt.scala 82:55]
-  wire  e_dwconv = io_in_op == 7'h63 | io_in_op == 7'h64; // @[VAluInt.scala 82:43]
+  wire  _e_dwconv_T_1 = io_in_op == 7'h47; // @[VAluInt.scala 82:55]
+  wire  e_dwconv = io_in_op == 7'h46 | io_in_op == 7'h47; // @[VAluInt.scala 82:43]
   wire  e_add_add = io_in_op == 7'h6; // @[VAluInt.scala 85:29]
-  wire  e_add_adds = io_in_op == 7'h33; // @[VAluInt.scala 86:29]
-  wire  e_add_addw = io_in_op == 7'h35; // @[VAluInt.scala 87:29]
+  wire  e_add_adds = io_in_op == 7'h31; // @[VAluInt.scala 86:29]
+  wire  e_add_addw = io_in_op == 7'h33; // @[VAluInt.scala 87:29]
   wire  e_add_add3 = io_in_op == 7'h12; // @[VAluInt.scala 88:29]
-  wire  e_add_hadd = io_in_op == 7'h3a; // @[VAluInt.scala 89:29]
+  wire  e_add_hadd = io_in_op == 7'h38; // @[VAluInt.scala 89:29]
   wire  e_add = e_add_add | e_add_adds | e_add_addw | e_add_add3 | e_add_hadd; // @[VAluInt.scala 90:67]
   wire  e_cmp_eq = io_in_op == 7'h9; // @[VAluInt.scala 92:27]
   wire  e_cmp_ne = io_in_op == 7'ha; // @[VAluInt.scala 93:27]
@@ -64320,8 +54762,8 @@
   wire  e_mv2 = io_in_op == 7'h1d; // @[VAluInt.scala 127:24]
   wire  e_mvp = io_in_op == 7'h1e; // @[VAluInt.scala 128:24]
   wire  e_mv = io_in_op == 7'h1c | e_mv2 | e_mvp; // @[VAluInt.scala 129:45]
-  wire  e_padd_add = io_in_op == 7'h38; // @[VAluInt.scala 131:29]
-  wire  e_padd_sub = io_in_op == 7'h39; // @[VAluInt.scala 132:29]
+  wire  e_padd_add = io_in_op == 7'h36; // @[VAluInt.scala 131:29]
+  wire  e_padd_sub = io_in_op == 7'h37; // @[VAluInt.scala 132:29]
   wire  e_padd = e_padd_add | e_padd_sub; // @[VAluInt.scala 133:27]
   wire  e_shf_shl = io_in_op == 7'h22; // @[VAluInt.scala 135:28]
   wire  e_shf_shr = io_in_op == 7'h23; // @[VAluInt.scala 136:28]
@@ -64329,9 +54771,9 @@
   wire  e_shf_l = e_shf_shl | e_shf_shf; // @[VAluInt.scala 138:27]
   wire  e_shf_r = e_shf_shr | e_shf_shf; // @[VAluInt.scala 139:27]
   wire  e_sub_sub = io_in_op == 7'h7; // @[VAluInt.scala 141:29]
-  wire  e_sub_subs = io_in_op == 7'h34; // @[VAluInt.scala 142:29]
-  wire  e_sub_subw = io_in_op == 7'h36; // @[VAluInt.scala 143:29]
-  wire  e_sub_hsub = io_in_op == 7'h3b; // @[VAluInt.scala 144:29]
+  wire  e_sub_subs = io_in_op == 7'h32; // @[VAluInt.scala 142:29]
+  wire  e_sub_subw = io_in_op == 7'h34; // @[VAluInt.scala 143:29]
+  wire  e_sub_hsub = io_in_op == 7'h39; // @[VAluInt.scala 144:29]
   wire  e_sub = e_sub_sub | e_sub_subs | e_sub_subw | e_sub_hsub; // @[VAluInt.scala 145:53]
   wire  e_negative = io_in_f2[0] & e_mul0_dmulh; // @[VAluInt.scala 147:32]
   wire  e_round = io_in_f2[1] & (e_add_hadd | e_sub_hsub | e_mul0_dmulh | e_mul0_mulh | e_shf_shf | e_srans | e_sraqs); // @[VAluInt.scala 148:32]
@@ -68783,29 +59225,29 @@
   wire [2:0] _T_6 = _GEN_89 + _T_4; // @[Bitwise.scala 48:55]
   wire  _T_11 = ~reset; // @[VAluInt.scala 47:9]
   wire  e_absd = io_in_op == 7'hf; // @[VAluInt.scala 63:26]
-  wire  e_acc = io_in_op == 7'h37; // @[VAluInt.scala 64:26]
+  wire  e_acc = io_in_op == 7'h35; // @[VAluInt.scala 64:26]
   wire  e_dup = io_in_op == 7'h1; // @[VAluInt.scala 65:26]
   wire  e_max = io_in_op == 7'h10; // @[VAluInt.scala 66:26]
   wire  e_min = io_in_op == 7'h11; // @[VAluInt.scala 67:26]
   wire  e_rsub = io_in_op == 7'h8; // @[VAluInt.scala 68:26]
   wire  e_srans = io_in_op == 7'h25; // @[VAluInt.scala 69:26]
-  wire  _e_slidevn_T_3 = io_in_op == 7'h58; // @[VAluInt.scala 72:86]
-  wire  e_slidevn = io_in_op == 7'h56 | io_in_op == 7'h57 | io_in_op == 7'h58; // @[VAluInt.scala 72:74]
-  wire  _e_slidevp_T_3 = io_in_op == 7'h5b; // @[VAluInt.scala 73:86]
-  wire  e_slidevp = io_in_op == 7'h59 | io_in_op == 7'h5a | io_in_op == 7'h5b; // @[VAluInt.scala 73:74]
-  wire  e_sel = io_in_op == 7'h5c; // @[VAluInt.scala 76:24]
-  wire  _e_evn_T_1 = io_in_op == 7'h5f; // @[VAluInt.scala 77:49]
-  wire  e_evn = io_in_op == 7'h5d | io_in_op == 7'h5f; // @[VAluInt.scala 77:37]
-  wire  e_odd = io_in_op == 7'h5e | _e_evn_T_1; // @[VAluInt.scala 78:37]
-  wire  e_zip = io_in_op == 7'h60; // @[VAluInt.scala 79:24]
+  wire  _e_slidevn_T_3 = io_in_op == 7'h3c; // @[VAluInt.scala 72:86]
+  wire  e_slidevn = io_in_op == 7'h3a | io_in_op == 7'h3b | io_in_op == 7'h3c; // @[VAluInt.scala 72:74]
+  wire  _e_slidevp_T_3 = io_in_op == 7'h3f; // @[VAluInt.scala 73:86]
+  wire  e_slidevp = io_in_op == 7'h3d | io_in_op == 7'h3e | io_in_op == 7'h3f; // @[VAluInt.scala 73:74]
+  wire  e_sel = io_in_op == 7'h40; // @[VAluInt.scala 76:24]
+  wire  _e_evn_T_1 = io_in_op == 7'h43; // @[VAluInt.scala 77:49]
+  wire  e_evn = io_in_op == 7'h41 | io_in_op == 7'h43; // @[VAluInt.scala 77:37]
+  wire  e_odd = io_in_op == 7'h42 | _e_evn_T_1; // @[VAluInt.scala 78:37]
+  wire  e_zip = io_in_op == 7'h44; // @[VAluInt.scala 79:24]
   wire  e_dwinit = io_in_op == 7'h21; // @[VAluInt.scala 81:27]
-  wire  _e_dwconv_T_1 = io_in_op == 7'h64; // @[VAluInt.scala 82:55]
-  wire  e_dwconv = io_in_op == 7'h63 | io_in_op == 7'h64; // @[VAluInt.scala 82:43]
+  wire  _e_dwconv_T_1 = io_in_op == 7'h47; // @[VAluInt.scala 82:55]
+  wire  e_dwconv = io_in_op == 7'h46 | io_in_op == 7'h47; // @[VAluInt.scala 82:43]
   wire  e_add_add = io_in_op == 7'h6; // @[VAluInt.scala 85:29]
-  wire  e_add_adds = io_in_op == 7'h33; // @[VAluInt.scala 86:29]
-  wire  e_add_addw = io_in_op == 7'h35; // @[VAluInt.scala 87:29]
+  wire  e_add_adds = io_in_op == 7'h31; // @[VAluInt.scala 86:29]
+  wire  e_add_addw = io_in_op == 7'h33; // @[VAluInt.scala 87:29]
   wire  e_add_add3 = io_in_op == 7'h12; // @[VAluInt.scala 88:29]
-  wire  e_add_hadd = io_in_op == 7'h3a; // @[VAluInt.scala 89:29]
+  wire  e_add_hadd = io_in_op == 7'h38; // @[VAluInt.scala 89:29]
   wire  e_add = e_add_add | e_add_adds | e_add_addw | e_add_add3 | e_add_hadd; // @[VAluInt.scala 90:67]
   wire  e_cmp_eq = io_in_op == 7'h9; // @[VAluInt.scala 92:27]
   wire  e_cmp_ne = io_in_op == 7'ha; // @[VAluInt.scala 93:27]
@@ -68858,8 +59300,8 @@
   wire  e_mv2 = io_in_op == 7'h1d; // @[VAluInt.scala 127:24]
   wire  e_mvp = io_in_op == 7'h1e; // @[VAluInt.scala 128:24]
   wire  e_mv = io_in_op == 7'h1c | e_mv2 | e_mvp; // @[VAluInt.scala 129:45]
-  wire  e_padd_add = io_in_op == 7'h38; // @[VAluInt.scala 131:29]
-  wire  e_padd_sub = io_in_op == 7'h39; // @[VAluInt.scala 132:29]
+  wire  e_padd_add = io_in_op == 7'h36; // @[VAluInt.scala 131:29]
+  wire  e_padd_sub = io_in_op == 7'h37; // @[VAluInt.scala 132:29]
   wire  e_padd = e_padd_add | e_padd_sub; // @[VAluInt.scala 133:27]
   wire  e_shf_shl = io_in_op == 7'h22; // @[VAluInt.scala 135:28]
   wire  e_shf_shr = io_in_op == 7'h23; // @[VAluInt.scala 136:28]
@@ -68867,9 +59309,9 @@
   wire  e_shf_l = e_shf_shl | e_shf_shf; // @[VAluInt.scala 138:27]
   wire  e_shf_r = e_shf_shr | e_shf_shf; // @[VAluInt.scala 139:27]
   wire  e_sub_sub = io_in_op == 7'h7; // @[VAluInt.scala 141:29]
-  wire  e_sub_subs = io_in_op == 7'h34; // @[VAluInt.scala 142:29]
-  wire  e_sub_subw = io_in_op == 7'h36; // @[VAluInt.scala 143:29]
-  wire  e_sub_hsub = io_in_op == 7'h3b; // @[VAluInt.scala 144:29]
+  wire  e_sub_subs = io_in_op == 7'h32; // @[VAluInt.scala 142:29]
+  wire  e_sub_subw = io_in_op == 7'h34; // @[VAluInt.scala 143:29]
+  wire  e_sub_hsub = io_in_op == 7'h39; // @[VAluInt.scala 144:29]
   wire  e_sub = e_sub_sub | e_sub_subs | e_sub_subw | e_sub_hsub; // @[VAluInt.scala 145:53]
   wire  e_negative = io_in_f2[0] & e_mul0_dmulh; // @[VAluInt.scala 147:32]
   wire  e_round = io_in_f2[1] & (e_add_hadd | e_sub_hsub | e_mul0_dmulh | e_mul0_mulh | e_shf_shf | e_srans); // @[VAluInt.scala 148:32]
@@ -72972,558 +63414,558 @@
   wire [31:0] q1_io_out_bits_sv_data; // @[VCmdq.scala 14:11]
   wire  q1_io_out_bits_cmdsync; // @[VCmdq.scala 14:11]
   wire [63:0] q1_io_active; // @[VCmdq.scala 14:11]
-  wire  alu0_clock; // @[VAlu.scala 341:20]
-  wire  alu0_reset; // @[VAlu.scala 341:20]
-  wire  alu0_io_in_valid; // @[VAlu.scala 341:20]
-  wire [6:0] alu0_io_in_op; // @[VAlu.scala 341:20]
-  wire [2:0] alu0_io_in_f2; // @[VAlu.scala 341:20]
-  wire [2:0] alu0_io_in_sz; // @[VAlu.scala 341:20]
-  wire [5:0] alu0_io_in_vd_addr; // @[VAlu.scala 341:20]
-  wire [5:0] alu0_io_in_ve_addr; // @[VAlu.scala 341:20]
-  wire [31:0] alu0_io_in_sv_data; // @[VAlu.scala 341:20]
-  wire [255:0] alu0_io_read_0_data; // @[VAlu.scala 341:20]
-  wire [255:0] alu0_io_read_1_data; // @[VAlu.scala 341:20]
-  wire [255:0] alu0_io_read_2_data; // @[VAlu.scala 341:20]
-  wire [255:0] alu0_io_read_3_data; // @[VAlu.scala 341:20]
-  wire [255:0] alu0_io_read_4_data; // @[VAlu.scala 341:20]
-  wire [255:0] alu0_io_read_5_data; // @[VAlu.scala 341:20]
-  wire  alu0_io_write_0_valid; // @[VAlu.scala 341:20]
-  wire [5:0] alu0_io_write_0_addr; // @[VAlu.scala 341:20]
-  wire [255:0] alu0_io_write_0_data; // @[VAlu.scala 341:20]
-  wire  alu0_io_write_1_valid; // @[VAlu.scala 341:20]
-  wire [5:0] alu0_io_write_1_addr; // @[VAlu.scala 341:20]
-  wire [255:0] alu0_io_write_1_data; // @[VAlu.scala 341:20]
-  wire  alu0_io_whint_0_valid; // @[VAlu.scala 341:20]
-  wire [5:0] alu0_io_whint_0_addr; // @[VAlu.scala 341:20]
-  wire  alu0_io_whint_1_valid; // @[VAlu.scala 341:20]
-  wire [5:0] alu0_io_whint_1_addr; // @[VAlu.scala 341:20]
-  wire  alu1_clock; // @[VAlu.scala 375:20]
-  wire  alu1_reset; // @[VAlu.scala 375:20]
-  wire  alu1_io_in_valid; // @[VAlu.scala 375:20]
-  wire [6:0] alu1_io_in_op; // @[VAlu.scala 375:20]
-  wire [2:0] alu1_io_in_f2; // @[VAlu.scala 375:20]
-  wire [2:0] alu1_io_in_sz; // @[VAlu.scala 375:20]
-  wire [5:0] alu1_io_in_vd_addr; // @[VAlu.scala 375:20]
-  wire [5:0] alu1_io_in_ve_addr; // @[VAlu.scala 375:20]
-  wire [31:0] alu1_io_in_sv_data; // @[VAlu.scala 375:20]
-  wire [255:0] alu1_io_read_0_data; // @[VAlu.scala 375:20]
-  wire [255:0] alu1_io_read_1_data; // @[VAlu.scala 375:20]
-  wire [255:0] alu1_io_read_2_data; // @[VAlu.scala 375:20]
-  wire [255:0] alu1_io_read_3_data; // @[VAlu.scala 375:20]
-  wire [255:0] alu1_io_read_4_data; // @[VAlu.scala 375:20]
-  wire [255:0] alu1_io_read_5_data; // @[VAlu.scala 375:20]
-  wire  alu1_io_write_0_valid; // @[VAlu.scala 375:20]
-  wire [5:0] alu1_io_write_0_addr; // @[VAlu.scala 375:20]
-  wire [255:0] alu1_io_write_0_data; // @[VAlu.scala 375:20]
-  wire  alu1_io_write_1_valid; // @[VAlu.scala 375:20]
-  wire [5:0] alu1_io_write_1_addr; // @[VAlu.scala 375:20]
-  wire [255:0] alu1_io_write_1_data; // @[VAlu.scala 375:20]
-  wire  alu1_io_whint_0_valid; // @[VAlu.scala 375:20]
-  wire [5:0] alu1_io_whint_0_addr; // @[VAlu.scala 375:20]
-  wire  alu1_io_whint_1_valid; // @[VAlu.scala 375:20]
-  wire [5:0] alu1_io_whint_1_addr; // @[VAlu.scala 375:20]
-  wire  _T = io_in_valid & io_in_ready; // @[VAlu.scala 82:23]
-  wire  _supported_T_1 = io_in_bits_0_bits_op == 7'h37; // @[VAlu.scala 88:16]
-  wire  _supported_T_2 = io_in_bits_0_bits_op == 7'hf | _supported_T_1; // @[VAlu.scala 87:30]
-  wire  _supported_T_3 = io_in_bits_0_bits_op == 7'h6; // @[VAlu.scala 89:16]
-  wire  _supported_T_4 = _supported_T_2 | _supported_T_3; // @[VAlu.scala 88:29]
-  wire  _supported_T_5 = io_in_bits_0_bits_op == 7'h33; // @[VAlu.scala 90:16]
-  wire  _supported_T_6 = _supported_T_4 | _supported_T_5; // @[VAlu.scala 89:29]
-  wire  _supported_T_7 = io_in_bits_0_bits_op == 7'h35; // @[VAlu.scala 91:16]
-  wire  _supported_T_8 = _supported_T_6 | _supported_T_7; // @[VAlu.scala 90:30]
-  wire  _supported_T_9 = io_in_bits_0_bits_op == 7'h12; // @[VAlu.scala 92:16]
-  wire  _supported_T_10 = _supported_T_8 | _supported_T_9; // @[VAlu.scala 91:30]
-  wire  _supported_T_11 = io_in_bits_0_bits_op == 7'h1; // @[VAlu.scala 93:16]
-  wire  _supported_T_12 = _supported_T_10 | _supported_T_11; // @[VAlu.scala 92:30]
-  wire  _supported_T_13 = io_in_bits_0_bits_op == 7'h3a; // @[VAlu.scala 94:16]
-  wire  _supported_T_14 = _supported_T_12 | _supported_T_13; // @[VAlu.scala 93:29]
-  wire  _supported_T_15 = io_in_bits_0_bits_op == 7'h3b; // @[VAlu.scala 95:16]
-  wire  _supported_T_16 = _supported_T_14 | _supported_T_15; // @[VAlu.scala 94:30]
-  wire  _supported_T_17 = io_in_bits_0_bits_op == 7'h10; // @[VAlu.scala 96:16]
-  wire  _supported_T_18 = _supported_T_16 | _supported_T_17; // @[VAlu.scala 95:30]
-  wire  _supported_T_19 = io_in_bits_0_bits_op == 7'h11; // @[VAlu.scala 97:16]
-  wire  _supported_T_20 = _supported_T_18 | _supported_T_19; // @[VAlu.scala 96:29]
-  wire  _supported_T_21 = io_in_bits_0_bits_op == 7'h38; // @[VAlu.scala 98:16]
-  wire  _supported_T_22 = _supported_T_20 | _supported_T_21; // @[VAlu.scala 97:29]
-  wire  _supported_T_23 = io_in_bits_0_bits_op == 7'h39; // @[VAlu.scala 99:16]
-  wire  _supported_T_24 = _supported_T_22 | _supported_T_23; // @[VAlu.scala 98:30]
-  wire  _supported_T_25 = io_in_bits_0_bits_op == 7'h8; // @[VAlu.scala 100:16]
-  wire  _supported_T_26 = _supported_T_24 | _supported_T_25; // @[VAlu.scala 99:30]
-  wire  _supported_T_27 = io_in_bits_0_bits_op == 7'h7; // @[VAlu.scala 101:16]
-  wire  _supported_T_28 = _supported_T_26 | _supported_T_27; // @[VAlu.scala 100:30]
-  wire  _supported_T_29 = io_in_bits_0_bits_op == 7'h34; // @[VAlu.scala 102:16]
-  wire  _supported_T_30 = _supported_T_28 | _supported_T_29; // @[VAlu.scala 101:29]
-  wire  _supported_T_31 = io_in_bits_0_bits_op == 7'h36; // @[VAlu.scala 103:16]
-  wire  _supported_T_32 = _supported_T_30 | _supported_T_31; // @[VAlu.scala 102:30]
-  wire  _supported_T_33 = io_in_bits_0_bits_op == 7'h9; // @[VAlu.scala 105:16]
-  wire  _supported_T_34 = _supported_T_32 | _supported_T_33; // @[VAlu.scala 103:30]
-  wire  _supported_T_35 = io_in_bits_0_bits_op == 7'ha; // @[VAlu.scala 106:16]
-  wire  _supported_T_36 = _supported_T_34 | _supported_T_35; // @[VAlu.scala 105:28]
-  wire  _supported_T_37 = io_in_bits_0_bits_op == 7'hb; // @[VAlu.scala 107:16]
-  wire  _supported_T_38 = _supported_T_36 | _supported_T_37; // @[VAlu.scala 106:28]
-  wire  _supported_T_39 = io_in_bits_0_bits_op == 7'hc; // @[VAlu.scala 108:16]
-  wire  _supported_T_40 = _supported_T_38 | _supported_T_39; // @[VAlu.scala 107:28]
-  wire  _supported_T_41 = io_in_bits_0_bits_op == 7'hd; // @[VAlu.scala 109:16]
-  wire  _supported_T_42 = _supported_T_40 | _supported_T_41; // @[VAlu.scala 108:28]
-  wire  _supported_T_43 = io_in_bits_0_bits_op == 7'he; // @[VAlu.scala 110:16]
-  wire  _supported_T_44 = _supported_T_42 | _supported_T_43; // @[VAlu.scala 109:28]
-  wire  _supported_T_45 = io_in_bits_0_bits_op == 7'h13; // @[VAlu.scala 112:16]
-  wire  _supported_T_46 = _supported_T_44 | _supported_T_45; // @[VAlu.scala 110:28]
-  wire  _supported_T_47 = io_in_bits_0_bits_op == 7'h19; // @[VAlu.scala 113:16]
-  wire  _supported_T_48 = _supported_T_46 | _supported_T_47; // @[VAlu.scala 112:29]
-  wire  _supported_T_49 = io_in_bits_0_bits_op == 7'h1a; // @[VAlu.scala 114:16]
-  wire  _supported_T_50 = _supported_T_48 | _supported_T_49; // @[VAlu.scala 113:29]
-  wire  _supported_T_51 = io_in_bits_0_bits_op == 7'h1b; // @[VAlu.scala 115:16]
-  wire  _supported_T_52 = _supported_T_50 | _supported_T_51; // @[VAlu.scala 114:29]
-  wire  _supported_T_53 = io_in_bits_0_bits_op == 7'h1c; // @[VAlu.scala 116:16]
-  wire  _supported_T_54 = _supported_T_52 | _supported_T_53; // @[VAlu.scala 115:30]
-  wire  _supported_T_55 = io_in_bits_0_bits_op == 7'h1d; // @[VAlu.scala 117:16]
-  wire  _supported_T_56 = _supported_T_54 | _supported_T_55; // @[VAlu.scala 116:28]
-  wire  _supported_T_57 = io_in_bits_0_bits_op == 7'h1e; // @[VAlu.scala 118:16]
-  wire  _supported_T_58 = _supported_T_56 | _supported_T_57; // @[VAlu.scala 117:29]
-  wire  _supported_T_59 = io_in_bits_0_bits_op == 7'h21; // @[VAlu.scala 119:16]
-  wire  _supported_T_60 = _supported_T_58 | _supported_T_59; // @[VAlu.scala 118:29]
-  wire  _supported_T_61 = io_in_bits_0_bits_op == 7'h16; // @[VAlu.scala 120:16]
-  wire  _supported_T_62 = _supported_T_60 | _supported_T_61; // @[VAlu.scala 119:32]
-  wire  _supported_T_63 = io_in_bits_0_bits_op == 7'h14; // @[VAlu.scala 121:16]
-  wire  _supported_T_64 = _supported_T_62 | _supported_T_63; // @[VAlu.scala 120:29]
-  wire  _supported_T_65 = io_in_bits_0_bits_op == 7'h17; // @[VAlu.scala 122:16]
-  wire  _supported_T_66 = _supported_T_64 | _supported_T_65; // @[VAlu.scala 121:28]
-  wire  _supported_T_67 = io_in_bits_0_bits_op == 7'h18; // @[VAlu.scala 123:16]
-  wire  _supported_T_68 = _supported_T_66 | _supported_T_67; // @[VAlu.scala 122:29]
-  wire  _supported_T_69 = io_in_bits_0_bits_op == 7'h15; // @[VAlu.scala 124:16]
-  wire  _supported_T_70 = _supported_T_68 | _supported_T_69; // @[VAlu.scala 123:29]
-  wire  _supported_T_71 = io_in_bits_0_bits_op == 7'h22; // @[VAlu.scala 126:16]
-  wire  _supported_T_72 = _supported_T_70 | _supported_T_71; // @[VAlu.scala 124:29]
-  wire  _supported_T_73 = io_in_bits_0_bits_op == 7'h23; // @[VAlu.scala 127:16]
-  wire  _supported_T_74 = _supported_T_72 | _supported_T_73; // @[VAlu.scala 126:29]
-  wire  _supported_T_75 = io_in_bits_0_bits_op == 7'h24; // @[VAlu.scala 128:16]
-  wire  _supported_T_76 = _supported_T_74 | _supported_T_75; // @[VAlu.scala 127:29]
-  wire  _supported_T_77 = io_in_bits_0_bits_op == 7'h25; // @[VAlu.scala 129:16]
-  wire  _supported_T_78 = _supported_T_76 | _supported_T_77; // @[VAlu.scala 128:29]
-  wire  _supported_T_79 = io_in_bits_0_bits_op == 7'h26; // @[VAlu.scala 130:16]
-  wire  _supported_T_80 = _supported_T_78 | _supported_T_79; // @[VAlu.scala 129:31]
-  wire  _supported_T_81 = io_in_bits_0_bits_op == 7'h2d; // @[VAlu.scala 132:16]
-  wire  _supported_T_82 = _supported_T_80 | _supported_T_81; // @[VAlu.scala 130:31]
-  wire  _supported_T_83 = io_in_bits_0_bits_op == 7'h2e; // @[VAlu.scala 133:16]
-  wire  _supported_T_84 = _supported_T_82 | _supported_T_83; // @[VAlu.scala 132:31]
-  wire  _supported_T_85 = io_in_bits_0_bits_op == 7'h30; // @[VAlu.scala 134:16]
-  wire  _supported_T_86 = _supported_T_84 | _supported_T_85; // @[VAlu.scala 133:32]
-  wire  _supported_T_87 = io_in_bits_0_bits_op == 7'h27; // @[VAlu.scala 135:16]
-  wire  _supported_T_88 = _supported_T_86 | _supported_T_87; // @[VAlu.scala 134:30]
-  wire  _supported_T_89 = io_in_bits_0_bits_op == 7'h28; // @[VAlu.scala 136:16]
-  wire  _supported_T_90 = _supported_T_88 | _supported_T_89; // @[VAlu.scala 135:29]
-  wire  _supported_T_91 = io_in_bits_0_bits_op == 7'h2b; // @[VAlu.scala 137:16]
-  wire  _supported_T_92 = _supported_T_90 | _supported_T_91; // @[VAlu.scala 136:30]
-  wire  _supported_T_93 = io_in_bits_0_bits_op == 7'h2c; // @[VAlu.scala 138:16]
-  wire  _supported_T_94 = _supported_T_92 | _supported_T_93; // @[VAlu.scala 137:30]
-  wire  _supported_T_95 = io_in_bits_0_bits_op == 7'h29; // @[VAlu.scala 139:16]
-  wire  _supported_T_96 = _supported_T_94 | _supported_T_95; // @[VAlu.scala 138:31]
-  wire  _supported_T_97 = io_in_bits_0_bits_op == 7'h2a; // @[VAlu.scala 140:16]
-  wire  _supported_T_98 = _supported_T_96 | _supported_T_97; // @[VAlu.scala 139:30]
-  wire  _supported_T_99 = io_in_bits_0_bits_op == 7'h2f; // @[VAlu.scala 141:16]
-  wire  _supported_T_100 = _supported_T_98 | _supported_T_99; // @[VAlu.scala 140:31]
-  wire  _supported_T_101 = io_in_bits_0_bits_op == 7'h56; // @[VAlu.scala 143:16]
-  wire  _supported_T_102 = _supported_T_100 | _supported_T_101; // @[VAlu.scala 141:30]
-  wire  _supported_T_103 = io_in_bits_0_bits_op == 7'h59; // @[VAlu.scala 144:16]
-  wire  _supported_T_104 = _supported_T_102 | _supported_T_103; // @[VAlu.scala 143:33]
-  wire  _supported_T_105 = io_in_bits_0_bits_op == 7'h58; // @[VAlu.scala 145:16]
-  wire  _supported_T_106 = _supported_T_104 | _supported_T_105; // @[VAlu.scala 144:33]
-  wire  _supported_T_107 = io_in_bits_0_bits_op == 7'h5b; // @[VAlu.scala 146:16]
-  wire  _supported_T_108 = _supported_T_106 | _supported_T_107; // @[VAlu.scala 145:34]
-  wire  _supported_T_109 = io_in_bits_0_bits_op == 7'h5c; // @[VAlu.scala 147:16]
-  wire  _supported_T_110 = _supported_T_108 | _supported_T_109; // @[VAlu.scala 146:34]
-  wire  _supported_T_111 = io_in_bits_0_bits_op == 7'h5d; // @[VAlu.scala 148:16]
-  wire  _supported_T_112 = _supported_T_110 | _supported_T_111; // @[VAlu.scala 147:29]
-  wire  _supported_T_113 = io_in_bits_0_bits_op == 7'h5e; // @[VAlu.scala 149:16]
-  wire  _supported_T_114 = _supported_T_112 | _supported_T_113; // @[VAlu.scala 148:29]
-  wire  _supported_T_115 = io_in_bits_0_bits_op == 7'h5f; // @[VAlu.scala 150:16]
-  wire  _supported_T_116 = _supported_T_114 | _supported_T_115; // @[VAlu.scala 149:29]
-  wire  _supported_T_117 = io_in_bits_0_bits_op == 7'h60; // @[VAlu.scala 151:16]
-  wire  _supported_T_118 = _supported_T_116 | _supported_T_117; // @[VAlu.scala 150:32]
-  wire  _supported_T_119 = io_in_bits_0_bits_op == 7'h63; // @[VAlu.scala 153:16]
-  wire  _supported_T_120 = _supported_T_118 | _supported_T_119; // @[VAlu.scala 151:29]
-  wire  _supported_T_121 = io_in_bits_0_bits_op == 7'h64; // @[VAlu.scala 154:16]
-  wire  supported = _supported_T_120 | _supported_T_121; // @[VAlu.scala 153:32]
-  wire  _T_1 = ~supported; // @[VAlu.scala 156:15]
-  wire  _T_3 = ~reset; // @[VAlu.scala 157:17]
-  wire  _T_14 = _supported_T_119 | _supported_T_121; // @[VAlu.scala 163:34]
-  wire [1:0] sparse = io_in_bits_0_bits_sv_data[3:2]; // @[VAlu.scala 164:50]
-  wire  _supported_T_123 = io_in_bits_1_bits_op == 7'h37; // @[VAlu.scala 88:16]
-  wire  _supported_T_124 = io_in_bits_1_bits_op == 7'hf | _supported_T_123; // @[VAlu.scala 87:30]
-  wire  _supported_T_125 = io_in_bits_1_bits_op == 7'h6; // @[VAlu.scala 89:16]
-  wire  _supported_T_126 = _supported_T_124 | _supported_T_125; // @[VAlu.scala 88:29]
-  wire  _supported_T_127 = io_in_bits_1_bits_op == 7'h33; // @[VAlu.scala 90:16]
-  wire  _supported_T_128 = _supported_T_126 | _supported_T_127; // @[VAlu.scala 89:29]
-  wire  _supported_T_129 = io_in_bits_1_bits_op == 7'h35; // @[VAlu.scala 91:16]
-  wire  _supported_T_130 = _supported_T_128 | _supported_T_129; // @[VAlu.scala 90:30]
-  wire  _supported_T_131 = io_in_bits_1_bits_op == 7'h12; // @[VAlu.scala 92:16]
-  wire  _supported_T_132 = _supported_T_130 | _supported_T_131; // @[VAlu.scala 91:30]
-  wire  _supported_T_133 = io_in_bits_1_bits_op == 7'h1; // @[VAlu.scala 93:16]
-  wire  _supported_T_134 = _supported_T_132 | _supported_T_133; // @[VAlu.scala 92:30]
-  wire  _supported_T_135 = io_in_bits_1_bits_op == 7'h3a; // @[VAlu.scala 94:16]
-  wire  _supported_T_136 = _supported_T_134 | _supported_T_135; // @[VAlu.scala 93:29]
-  wire  _supported_T_137 = io_in_bits_1_bits_op == 7'h3b; // @[VAlu.scala 95:16]
-  wire  _supported_T_138 = _supported_T_136 | _supported_T_137; // @[VAlu.scala 94:30]
-  wire  _supported_T_139 = io_in_bits_1_bits_op == 7'h10; // @[VAlu.scala 96:16]
-  wire  _supported_T_140 = _supported_T_138 | _supported_T_139; // @[VAlu.scala 95:30]
-  wire  _supported_T_141 = io_in_bits_1_bits_op == 7'h11; // @[VAlu.scala 97:16]
-  wire  _supported_T_142 = _supported_T_140 | _supported_T_141; // @[VAlu.scala 96:29]
-  wire  _supported_T_143 = io_in_bits_1_bits_op == 7'h38; // @[VAlu.scala 98:16]
-  wire  _supported_T_144 = _supported_T_142 | _supported_T_143; // @[VAlu.scala 97:29]
-  wire  _supported_T_145 = io_in_bits_1_bits_op == 7'h39; // @[VAlu.scala 99:16]
-  wire  _supported_T_146 = _supported_T_144 | _supported_T_145; // @[VAlu.scala 98:30]
-  wire  _supported_T_147 = io_in_bits_1_bits_op == 7'h8; // @[VAlu.scala 100:16]
-  wire  _supported_T_148 = _supported_T_146 | _supported_T_147; // @[VAlu.scala 99:30]
-  wire  _supported_T_149 = io_in_bits_1_bits_op == 7'h7; // @[VAlu.scala 101:16]
-  wire  _supported_T_150 = _supported_T_148 | _supported_T_149; // @[VAlu.scala 100:30]
-  wire  _supported_T_151 = io_in_bits_1_bits_op == 7'h34; // @[VAlu.scala 102:16]
-  wire  _supported_T_152 = _supported_T_150 | _supported_T_151; // @[VAlu.scala 101:29]
-  wire  _supported_T_153 = io_in_bits_1_bits_op == 7'h36; // @[VAlu.scala 103:16]
-  wire  _supported_T_154 = _supported_T_152 | _supported_T_153; // @[VAlu.scala 102:30]
-  wire  _supported_T_155 = io_in_bits_1_bits_op == 7'h9; // @[VAlu.scala 105:16]
-  wire  _supported_T_156 = _supported_T_154 | _supported_T_155; // @[VAlu.scala 103:30]
-  wire  _supported_T_157 = io_in_bits_1_bits_op == 7'ha; // @[VAlu.scala 106:16]
-  wire  _supported_T_158 = _supported_T_156 | _supported_T_157; // @[VAlu.scala 105:28]
-  wire  _supported_T_159 = io_in_bits_1_bits_op == 7'hb; // @[VAlu.scala 107:16]
-  wire  _supported_T_160 = _supported_T_158 | _supported_T_159; // @[VAlu.scala 106:28]
-  wire  _supported_T_161 = io_in_bits_1_bits_op == 7'hc; // @[VAlu.scala 108:16]
-  wire  _supported_T_162 = _supported_T_160 | _supported_T_161; // @[VAlu.scala 107:28]
-  wire  _supported_T_163 = io_in_bits_1_bits_op == 7'hd; // @[VAlu.scala 109:16]
-  wire  _supported_T_164 = _supported_T_162 | _supported_T_163; // @[VAlu.scala 108:28]
-  wire  _supported_T_165 = io_in_bits_1_bits_op == 7'he; // @[VAlu.scala 110:16]
-  wire  _supported_T_166 = _supported_T_164 | _supported_T_165; // @[VAlu.scala 109:28]
-  wire  _supported_T_167 = io_in_bits_1_bits_op == 7'h13; // @[VAlu.scala 112:16]
-  wire  _supported_T_168 = _supported_T_166 | _supported_T_167; // @[VAlu.scala 110:28]
-  wire  _supported_T_169 = io_in_bits_1_bits_op == 7'h19; // @[VAlu.scala 113:16]
-  wire  _supported_T_170 = _supported_T_168 | _supported_T_169; // @[VAlu.scala 112:29]
-  wire  _supported_T_171 = io_in_bits_1_bits_op == 7'h1a; // @[VAlu.scala 114:16]
-  wire  _supported_T_172 = _supported_T_170 | _supported_T_171; // @[VAlu.scala 113:29]
-  wire  _supported_T_173 = io_in_bits_1_bits_op == 7'h1b; // @[VAlu.scala 115:16]
-  wire  _supported_T_174 = _supported_T_172 | _supported_T_173; // @[VAlu.scala 114:29]
-  wire  _supported_T_175 = io_in_bits_1_bits_op == 7'h1c; // @[VAlu.scala 116:16]
-  wire  _supported_T_176 = _supported_T_174 | _supported_T_175; // @[VAlu.scala 115:30]
-  wire  _supported_T_177 = io_in_bits_1_bits_op == 7'h1d; // @[VAlu.scala 117:16]
-  wire  _supported_T_178 = _supported_T_176 | _supported_T_177; // @[VAlu.scala 116:28]
-  wire  _supported_T_179 = io_in_bits_1_bits_op == 7'h1e; // @[VAlu.scala 118:16]
-  wire  _supported_T_180 = _supported_T_178 | _supported_T_179; // @[VAlu.scala 117:29]
-  wire  _supported_T_181 = io_in_bits_1_bits_op == 7'h21; // @[VAlu.scala 119:16]
-  wire  _supported_T_182 = _supported_T_180 | _supported_T_181; // @[VAlu.scala 118:29]
-  wire  _supported_T_183 = io_in_bits_1_bits_op == 7'h16; // @[VAlu.scala 120:16]
-  wire  _supported_T_184 = _supported_T_182 | _supported_T_183; // @[VAlu.scala 119:32]
-  wire  _supported_T_185 = io_in_bits_1_bits_op == 7'h14; // @[VAlu.scala 121:16]
-  wire  _supported_T_186 = _supported_T_184 | _supported_T_185; // @[VAlu.scala 120:29]
-  wire  _supported_T_187 = io_in_bits_1_bits_op == 7'h17; // @[VAlu.scala 122:16]
-  wire  _supported_T_188 = _supported_T_186 | _supported_T_187; // @[VAlu.scala 121:28]
-  wire  _supported_T_189 = io_in_bits_1_bits_op == 7'h18; // @[VAlu.scala 123:16]
-  wire  _supported_T_190 = _supported_T_188 | _supported_T_189; // @[VAlu.scala 122:29]
-  wire  _supported_T_191 = io_in_bits_1_bits_op == 7'h15; // @[VAlu.scala 124:16]
-  wire  _supported_T_192 = _supported_T_190 | _supported_T_191; // @[VAlu.scala 123:29]
-  wire  _supported_T_193 = io_in_bits_1_bits_op == 7'h22; // @[VAlu.scala 126:16]
-  wire  _supported_T_194 = _supported_T_192 | _supported_T_193; // @[VAlu.scala 124:29]
-  wire  _supported_T_195 = io_in_bits_1_bits_op == 7'h23; // @[VAlu.scala 127:16]
-  wire  _supported_T_196 = _supported_T_194 | _supported_T_195; // @[VAlu.scala 126:29]
-  wire  _supported_T_197 = io_in_bits_1_bits_op == 7'h24; // @[VAlu.scala 128:16]
-  wire  _supported_T_198 = _supported_T_196 | _supported_T_197; // @[VAlu.scala 127:29]
-  wire  _supported_T_199 = io_in_bits_1_bits_op == 7'h25; // @[VAlu.scala 129:16]
-  wire  _supported_T_200 = _supported_T_198 | _supported_T_199; // @[VAlu.scala 128:29]
-  wire  _supported_T_201 = io_in_bits_1_bits_op == 7'h26; // @[VAlu.scala 130:16]
-  wire  _supported_T_202 = _supported_T_200 | _supported_T_201; // @[VAlu.scala 129:31]
-  wire  _supported_T_203 = io_in_bits_1_bits_op == 7'h2d; // @[VAlu.scala 132:16]
-  wire  _supported_T_204 = _supported_T_202 | _supported_T_203; // @[VAlu.scala 130:31]
-  wire  _supported_T_205 = io_in_bits_1_bits_op == 7'h2e; // @[VAlu.scala 133:16]
-  wire  _supported_T_206 = _supported_T_204 | _supported_T_205; // @[VAlu.scala 132:31]
-  wire  _supported_T_207 = io_in_bits_1_bits_op == 7'h30; // @[VAlu.scala 134:16]
-  wire  _supported_T_208 = _supported_T_206 | _supported_T_207; // @[VAlu.scala 133:32]
-  wire  _supported_T_209 = io_in_bits_1_bits_op == 7'h27; // @[VAlu.scala 135:16]
-  wire  _supported_T_210 = _supported_T_208 | _supported_T_209; // @[VAlu.scala 134:30]
-  wire  _supported_T_211 = io_in_bits_1_bits_op == 7'h28; // @[VAlu.scala 136:16]
-  wire  _supported_T_212 = _supported_T_210 | _supported_T_211; // @[VAlu.scala 135:29]
-  wire  _supported_T_213 = io_in_bits_1_bits_op == 7'h2b; // @[VAlu.scala 137:16]
-  wire  _supported_T_214 = _supported_T_212 | _supported_T_213; // @[VAlu.scala 136:30]
-  wire  _supported_T_215 = io_in_bits_1_bits_op == 7'h2c; // @[VAlu.scala 138:16]
-  wire  _supported_T_216 = _supported_T_214 | _supported_T_215; // @[VAlu.scala 137:30]
-  wire  _supported_T_217 = io_in_bits_1_bits_op == 7'h29; // @[VAlu.scala 139:16]
-  wire  _supported_T_218 = _supported_T_216 | _supported_T_217; // @[VAlu.scala 138:31]
-  wire  _supported_T_219 = io_in_bits_1_bits_op == 7'h2a; // @[VAlu.scala 140:16]
-  wire  _supported_T_220 = _supported_T_218 | _supported_T_219; // @[VAlu.scala 139:30]
-  wire  _supported_T_221 = io_in_bits_1_bits_op == 7'h2f; // @[VAlu.scala 141:16]
-  wire  _supported_T_222 = _supported_T_220 | _supported_T_221; // @[VAlu.scala 140:31]
-  wire  _supported_T_223 = io_in_bits_1_bits_op == 7'h56; // @[VAlu.scala 143:16]
-  wire  _supported_T_224 = _supported_T_222 | _supported_T_223; // @[VAlu.scala 141:30]
-  wire  _supported_T_225 = io_in_bits_1_bits_op == 7'h59; // @[VAlu.scala 144:16]
-  wire  _supported_T_226 = _supported_T_224 | _supported_T_225; // @[VAlu.scala 143:33]
-  wire  _supported_T_227 = io_in_bits_1_bits_op == 7'h58; // @[VAlu.scala 145:16]
-  wire  _supported_T_228 = _supported_T_226 | _supported_T_227; // @[VAlu.scala 144:33]
-  wire  _supported_T_229 = io_in_bits_1_bits_op == 7'h5b; // @[VAlu.scala 146:16]
-  wire  _supported_T_230 = _supported_T_228 | _supported_T_229; // @[VAlu.scala 145:34]
-  wire  _supported_T_231 = io_in_bits_1_bits_op == 7'h5c; // @[VAlu.scala 147:16]
-  wire  _supported_T_232 = _supported_T_230 | _supported_T_231; // @[VAlu.scala 146:34]
-  wire  _supported_T_233 = io_in_bits_1_bits_op == 7'h5d; // @[VAlu.scala 148:16]
-  wire  _supported_T_234 = _supported_T_232 | _supported_T_233; // @[VAlu.scala 147:29]
-  wire  _supported_T_235 = io_in_bits_1_bits_op == 7'h5e; // @[VAlu.scala 149:16]
-  wire  _supported_T_236 = _supported_T_234 | _supported_T_235; // @[VAlu.scala 148:29]
-  wire  _supported_T_237 = io_in_bits_1_bits_op == 7'h5f; // @[VAlu.scala 150:16]
-  wire  _supported_T_238 = _supported_T_236 | _supported_T_237; // @[VAlu.scala 149:29]
-  wire  _supported_T_239 = io_in_bits_1_bits_op == 7'h60; // @[VAlu.scala 151:16]
-  wire  _supported_T_240 = _supported_T_238 | _supported_T_239; // @[VAlu.scala 150:32]
-  wire  _supported_T_241 = io_in_bits_1_bits_op == 7'h63; // @[VAlu.scala 153:16]
-  wire  _supported_T_242 = _supported_T_240 | _supported_T_241; // @[VAlu.scala 151:29]
-  wire  _supported_T_243 = io_in_bits_1_bits_op == 7'h64; // @[VAlu.scala 154:16]
-  wire  supported_1 = _supported_T_242 | _supported_T_243; // @[VAlu.scala 153:32]
-  wire  _T_32 = ~supported_1; // @[VAlu.scala 156:15]
-  wire  _T_45 = _supported_T_241 | _supported_T_243; // @[VAlu.scala 163:34]
-  wire [1:0] sparse_1 = io_in_bits_1_bits_sv_data[3:2]; // @[VAlu.scala 164:50]
-  wire  _supported_T_245 = io_in_bits_2_bits_op == 7'h37; // @[VAlu.scala 88:16]
-  wire  _supported_T_246 = io_in_bits_2_bits_op == 7'hf | _supported_T_245; // @[VAlu.scala 87:30]
-  wire  _supported_T_247 = io_in_bits_2_bits_op == 7'h6; // @[VAlu.scala 89:16]
-  wire  _supported_T_248 = _supported_T_246 | _supported_T_247; // @[VAlu.scala 88:29]
-  wire  _supported_T_249 = io_in_bits_2_bits_op == 7'h33; // @[VAlu.scala 90:16]
-  wire  _supported_T_250 = _supported_T_248 | _supported_T_249; // @[VAlu.scala 89:29]
-  wire  _supported_T_251 = io_in_bits_2_bits_op == 7'h35; // @[VAlu.scala 91:16]
-  wire  _supported_T_252 = _supported_T_250 | _supported_T_251; // @[VAlu.scala 90:30]
-  wire  _supported_T_253 = io_in_bits_2_bits_op == 7'h12; // @[VAlu.scala 92:16]
-  wire  _supported_T_254 = _supported_T_252 | _supported_T_253; // @[VAlu.scala 91:30]
-  wire  _supported_T_255 = io_in_bits_2_bits_op == 7'h1; // @[VAlu.scala 93:16]
-  wire  _supported_T_256 = _supported_T_254 | _supported_T_255; // @[VAlu.scala 92:30]
-  wire  _supported_T_257 = io_in_bits_2_bits_op == 7'h3a; // @[VAlu.scala 94:16]
-  wire  _supported_T_258 = _supported_T_256 | _supported_T_257; // @[VAlu.scala 93:29]
-  wire  _supported_T_259 = io_in_bits_2_bits_op == 7'h3b; // @[VAlu.scala 95:16]
-  wire  _supported_T_260 = _supported_T_258 | _supported_T_259; // @[VAlu.scala 94:30]
-  wire  _supported_T_261 = io_in_bits_2_bits_op == 7'h10; // @[VAlu.scala 96:16]
-  wire  _supported_T_262 = _supported_T_260 | _supported_T_261; // @[VAlu.scala 95:30]
-  wire  _supported_T_263 = io_in_bits_2_bits_op == 7'h11; // @[VAlu.scala 97:16]
-  wire  _supported_T_264 = _supported_T_262 | _supported_T_263; // @[VAlu.scala 96:29]
-  wire  _supported_T_265 = io_in_bits_2_bits_op == 7'h38; // @[VAlu.scala 98:16]
-  wire  _supported_T_266 = _supported_T_264 | _supported_T_265; // @[VAlu.scala 97:29]
-  wire  _supported_T_267 = io_in_bits_2_bits_op == 7'h39; // @[VAlu.scala 99:16]
-  wire  _supported_T_268 = _supported_T_266 | _supported_T_267; // @[VAlu.scala 98:30]
-  wire  _supported_T_269 = io_in_bits_2_bits_op == 7'h8; // @[VAlu.scala 100:16]
-  wire  _supported_T_270 = _supported_T_268 | _supported_T_269; // @[VAlu.scala 99:30]
-  wire  _supported_T_271 = io_in_bits_2_bits_op == 7'h7; // @[VAlu.scala 101:16]
-  wire  _supported_T_272 = _supported_T_270 | _supported_T_271; // @[VAlu.scala 100:30]
-  wire  _supported_T_273 = io_in_bits_2_bits_op == 7'h34; // @[VAlu.scala 102:16]
-  wire  _supported_T_274 = _supported_T_272 | _supported_T_273; // @[VAlu.scala 101:29]
-  wire  _supported_T_275 = io_in_bits_2_bits_op == 7'h36; // @[VAlu.scala 103:16]
-  wire  _supported_T_276 = _supported_T_274 | _supported_T_275; // @[VAlu.scala 102:30]
-  wire  _supported_T_277 = io_in_bits_2_bits_op == 7'h9; // @[VAlu.scala 105:16]
-  wire  _supported_T_278 = _supported_T_276 | _supported_T_277; // @[VAlu.scala 103:30]
-  wire  _supported_T_279 = io_in_bits_2_bits_op == 7'ha; // @[VAlu.scala 106:16]
-  wire  _supported_T_280 = _supported_T_278 | _supported_T_279; // @[VAlu.scala 105:28]
-  wire  _supported_T_281 = io_in_bits_2_bits_op == 7'hb; // @[VAlu.scala 107:16]
-  wire  _supported_T_282 = _supported_T_280 | _supported_T_281; // @[VAlu.scala 106:28]
-  wire  _supported_T_283 = io_in_bits_2_bits_op == 7'hc; // @[VAlu.scala 108:16]
-  wire  _supported_T_284 = _supported_T_282 | _supported_T_283; // @[VAlu.scala 107:28]
-  wire  _supported_T_285 = io_in_bits_2_bits_op == 7'hd; // @[VAlu.scala 109:16]
-  wire  _supported_T_286 = _supported_T_284 | _supported_T_285; // @[VAlu.scala 108:28]
-  wire  _supported_T_287 = io_in_bits_2_bits_op == 7'he; // @[VAlu.scala 110:16]
-  wire  _supported_T_288 = _supported_T_286 | _supported_T_287; // @[VAlu.scala 109:28]
-  wire  _supported_T_289 = io_in_bits_2_bits_op == 7'h13; // @[VAlu.scala 112:16]
-  wire  _supported_T_290 = _supported_T_288 | _supported_T_289; // @[VAlu.scala 110:28]
-  wire  _supported_T_291 = io_in_bits_2_bits_op == 7'h19; // @[VAlu.scala 113:16]
-  wire  _supported_T_292 = _supported_T_290 | _supported_T_291; // @[VAlu.scala 112:29]
-  wire  _supported_T_293 = io_in_bits_2_bits_op == 7'h1a; // @[VAlu.scala 114:16]
-  wire  _supported_T_294 = _supported_T_292 | _supported_T_293; // @[VAlu.scala 113:29]
-  wire  _supported_T_295 = io_in_bits_2_bits_op == 7'h1b; // @[VAlu.scala 115:16]
-  wire  _supported_T_296 = _supported_T_294 | _supported_T_295; // @[VAlu.scala 114:29]
-  wire  _supported_T_297 = io_in_bits_2_bits_op == 7'h1c; // @[VAlu.scala 116:16]
-  wire  _supported_T_298 = _supported_T_296 | _supported_T_297; // @[VAlu.scala 115:30]
-  wire  _supported_T_299 = io_in_bits_2_bits_op == 7'h1d; // @[VAlu.scala 117:16]
-  wire  _supported_T_300 = _supported_T_298 | _supported_T_299; // @[VAlu.scala 116:28]
-  wire  _supported_T_301 = io_in_bits_2_bits_op == 7'h1e; // @[VAlu.scala 118:16]
-  wire  _supported_T_302 = _supported_T_300 | _supported_T_301; // @[VAlu.scala 117:29]
-  wire  _supported_T_303 = io_in_bits_2_bits_op == 7'h21; // @[VAlu.scala 119:16]
-  wire  _supported_T_304 = _supported_T_302 | _supported_T_303; // @[VAlu.scala 118:29]
-  wire  _supported_T_305 = io_in_bits_2_bits_op == 7'h16; // @[VAlu.scala 120:16]
-  wire  _supported_T_306 = _supported_T_304 | _supported_T_305; // @[VAlu.scala 119:32]
-  wire  _supported_T_307 = io_in_bits_2_bits_op == 7'h14; // @[VAlu.scala 121:16]
-  wire  _supported_T_308 = _supported_T_306 | _supported_T_307; // @[VAlu.scala 120:29]
-  wire  _supported_T_309 = io_in_bits_2_bits_op == 7'h17; // @[VAlu.scala 122:16]
-  wire  _supported_T_310 = _supported_T_308 | _supported_T_309; // @[VAlu.scala 121:28]
-  wire  _supported_T_311 = io_in_bits_2_bits_op == 7'h18; // @[VAlu.scala 123:16]
-  wire  _supported_T_312 = _supported_T_310 | _supported_T_311; // @[VAlu.scala 122:29]
-  wire  _supported_T_313 = io_in_bits_2_bits_op == 7'h15; // @[VAlu.scala 124:16]
-  wire  _supported_T_314 = _supported_T_312 | _supported_T_313; // @[VAlu.scala 123:29]
-  wire  _supported_T_315 = io_in_bits_2_bits_op == 7'h22; // @[VAlu.scala 126:16]
-  wire  _supported_T_316 = _supported_T_314 | _supported_T_315; // @[VAlu.scala 124:29]
-  wire  _supported_T_317 = io_in_bits_2_bits_op == 7'h23; // @[VAlu.scala 127:16]
-  wire  _supported_T_318 = _supported_T_316 | _supported_T_317; // @[VAlu.scala 126:29]
-  wire  _supported_T_319 = io_in_bits_2_bits_op == 7'h24; // @[VAlu.scala 128:16]
-  wire  _supported_T_320 = _supported_T_318 | _supported_T_319; // @[VAlu.scala 127:29]
-  wire  _supported_T_321 = io_in_bits_2_bits_op == 7'h25; // @[VAlu.scala 129:16]
-  wire  _supported_T_322 = _supported_T_320 | _supported_T_321; // @[VAlu.scala 128:29]
-  wire  _supported_T_323 = io_in_bits_2_bits_op == 7'h26; // @[VAlu.scala 130:16]
-  wire  _supported_T_324 = _supported_T_322 | _supported_T_323; // @[VAlu.scala 129:31]
-  wire  _supported_T_325 = io_in_bits_2_bits_op == 7'h2d; // @[VAlu.scala 132:16]
-  wire  _supported_T_326 = _supported_T_324 | _supported_T_325; // @[VAlu.scala 130:31]
-  wire  _supported_T_327 = io_in_bits_2_bits_op == 7'h2e; // @[VAlu.scala 133:16]
-  wire  _supported_T_328 = _supported_T_326 | _supported_T_327; // @[VAlu.scala 132:31]
-  wire  _supported_T_329 = io_in_bits_2_bits_op == 7'h30; // @[VAlu.scala 134:16]
-  wire  _supported_T_330 = _supported_T_328 | _supported_T_329; // @[VAlu.scala 133:32]
-  wire  _supported_T_331 = io_in_bits_2_bits_op == 7'h27; // @[VAlu.scala 135:16]
-  wire  _supported_T_332 = _supported_T_330 | _supported_T_331; // @[VAlu.scala 134:30]
-  wire  _supported_T_333 = io_in_bits_2_bits_op == 7'h28; // @[VAlu.scala 136:16]
-  wire  _supported_T_334 = _supported_T_332 | _supported_T_333; // @[VAlu.scala 135:29]
-  wire  _supported_T_335 = io_in_bits_2_bits_op == 7'h2b; // @[VAlu.scala 137:16]
-  wire  _supported_T_336 = _supported_T_334 | _supported_T_335; // @[VAlu.scala 136:30]
-  wire  _supported_T_337 = io_in_bits_2_bits_op == 7'h2c; // @[VAlu.scala 138:16]
-  wire  _supported_T_338 = _supported_T_336 | _supported_T_337; // @[VAlu.scala 137:30]
-  wire  _supported_T_339 = io_in_bits_2_bits_op == 7'h29; // @[VAlu.scala 139:16]
-  wire  _supported_T_340 = _supported_T_338 | _supported_T_339; // @[VAlu.scala 138:31]
-  wire  _supported_T_341 = io_in_bits_2_bits_op == 7'h2a; // @[VAlu.scala 140:16]
-  wire  _supported_T_342 = _supported_T_340 | _supported_T_341; // @[VAlu.scala 139:30]
-  wire  _supported_T_343 = io_in_bits_2_bits_op == 7'h2f; // @[VAlu.scala 141:16]
-  wire  _supported_T_344 = _supported_T_342 | _supported_T_343; // @[VAlu.scala 140:31]
-  wire  _supported_T_345 = io_in_bits_2_bits_op == 7'h56; // @[VAlu.scala 143:16]
-  wire  _supported_T_346 = _supported_T_344 | _supported_T_345; // @[VAlu.scala 141:30]
-  wire  _supported_T_347 = io_in_bits_2_bits_op == 7'h59; // @[VAlu.scala 144:16]
-  wire  _supported_T_348 = _supported_T_346 | _supported_T_347; // @[VAlu.scala 143:33]
-  wire  _supported_T_349 = io_in_bits_2_bits_op == 7'h58; // @[VAlu.scala 145:16]
-  wire  _supported_T_350 = _supported_T_348 | _supported_T_349; // @[VAlu.scala 144:33]
-  wire  _supported_T_351 = io_in_bits_2_bits_op == 7'h5b; // @[VAlu.scala 146:16]
-  wire  _supported_T_352 = _supported_T_350 | _supported_T_351; // @[VAlu.scala 145:34]
-  wire  _supported_T_353 = io_in_bits_2_bits_op == 7'h5c; // @[VAlu.scala 147:16]
-  wire  _supported_T_354 = _supported_T_352 | _supported_T_353; // @[VAlu.scala 146:34]
-  wire  _supported_T_355 = io_in_bits_2_bits_op == 7'h5d; // @[VAlu.scala 148:16]
-  wire  _supported_T_356 = _supported_T_354 | _supported_T_355; // @[VAlu.scala 147:29]
-  wire  _supported_T_357 = io_in_bits_2_bits_op == 7'h5e; // @[VAlu.scala 149:16]
-  wire  _supported_T_358 = _supported_T_356 | _supported_T_357; // @[VAlu.scala 148:29]
-  wire  _supported_T_359 = io_in_bits_2_bits_op == 7'h5f; // @[VAlu.scala 150:16]
-  wire  _supported_T_360 = _supported_T_358 | _supported_T_359; // @[VAlu.scala 149:29]
-  wire  _supported_T_361 = io_in_bits_2_bits_op == 7'h60; // @[VAlu.scala 151:16]
-  wire  _supported_T_362 = _supported_T_360 | _supported_T_361; // @[VAlu.scala 150:32]
-  wire  _supported_T_363 = io_in_bits_2_bits_op == 7'h63; // @[VAlu.scala 153:16]
-  wire  _supported_T_364 = _supported_T_362 | _supported_T_363; // @[VAlu.scala 151:29]
-  wire  _supported_T_365 = io_in_bits_2_bits_op == 7'h64; // @[VAlu.scala 154:16]
-  wire  supported_2 = _supported_T_364 | _supported_T_365; // @[VAlu.scala 153:32]
-  wire  _T_63 = ~supported_2; // @[VAlu.scala 156:15]
-  wire  _T_76 = _supported_T_363 | _supported_T_365; // @[VAlu.scala 163:34]
-  wire [1:0] sparse_2 = io_in_bits_2_bits_sv_data[3:2]; // @[VAlu.scala 164:50]
-  wire  _supported_T_367 = io_in_bits_3_bits_op == 7'h37; // @[VAlu.scala 88:16]
-  wire  _supported_T_368 = io_in_bits_3_bits_op == 7'hf | _supported_T_367; // @[VAlu.scala 87:30]
-  wire  _supported_T_369 = io_in_bits_3_bits_op == 7'h6; // @[VAlu.scala 89:16]
-  wire  _supported_T_370 = _supported_T_368 | _supported_T_369; // @[VAlu.scala 88:29]
-  wire  _supported_T_371 = io_in_bits_3_bits_op == 7'h33; // @[VAlu.scala 90:16]
-  wire  _supported_T_372 = _supported_T_370 | _supported_T_371; // @[VAlu.scala 89:29]
-  wire  _supported_T_373 = io_in_bits_3_bits_op == 7'h35; // @[VAlu.scala 91:16]
-  wire  _supported_T_374 = _supported_T_372 | _supported_T_373; // @[VAlu.scala 90:30]
-  wire  _supported_T_375 = io_in_bits_3_bits_op == 7'h12; // @[VAlu.scala 92:16]
-  wire  _supported_T_376 = _supported_T_374 | _supported_T_375; // @[VAlu.scala 91:30]
-  wire  _supported_T_377 = io_in_bits_3_bits_op == 7'h1; // @[VAlu.scala 93:16]
-  wire  _supported_T_378 = _supported_T_376 | _supported_T_377; // @[VAlu.scala 92:30]
-  wire  _supported_T_379 = io_in_bits_3_bits_op == 7'h3a; // @[VAlu.scala 94:16]
-  wire  _supported_T_380 = _supported_T_378 | _supported_T_379; // @[VAlu.scala 93:29]
-  wire  _supported_T_381 = io_in_bits_3_bits_op == 7'h3b; // @[VAlu.scala 95:16]
-  wire  _supported_T_382 = _supported_T_380 | _supported_T_381; // @[VAlu.scala 94:30]
-  wire  _supported_T_383 = io_in_bits_3_bits_op == 7'h10; // @[VAlu.scala 96:16]
-  wire  _supported_T_384 = _supported_T_382 | _supported_T_383; // @[VAlu.scala 95:30]
-  wire  _supported_T_385 = io_in_bits_3_bits_op == 7'h11; // @[VAlu.scala 97:16]
-  wire  _supported_T_386 = _supported_T_384 | _supported_T_385; // @[VAlu.scala 96:29]
-  wire  _supported_T_387 = io_in_bits_3_bits_op == 7'h38; // @[VAlu.scala 98:16]
-  wire  _supported_T_388 = _supported_T_386 | _supported_T_387; // @[VAlu.scala 97:29]
-  wire  _supported_T_389 = io_in_bits_3_bits_op == 7'h39; // @[VAlu.scala 99:16]
-  wire  _supported_T_390 = _supported_T_388 | _supported_T_389; // @[VAlu.scala 98:30]
-  wire  _supported_T_391 = io_in_bits_3_bits_op == 7'h8; // @[VAlu.scala 100:16]
-  wire  _supported_T_392 = _supported_T_390 | _supported_T_391; // @[VAlu.scala 99:30]
-  wire  _supported_T_393 = io_in_bits_3_bits_op == 7'h7; // @[VAlu.scala 101:16]
-  wire  _supported_T_394 = _supported_T_392 | _supported_T_393; // @[VAlu.scala 100:30]
-  wire  _supported_T_395 = io_in_bits_3_bits_op == 7'h34; // @[VAlu.scala 102:16]
-  wire  _supported_T_396 = _supported_T_394 | _supported_T_395; // @[VAlu.scala 101:29]
-  wire  _supported_T_397 = io_in_bits_3_bits_op == 7'h36; // @[VAlu.scala 103:16]
-  wire  _supported_T_398 = _supported_T_396 | _supported_T_397; // @[VAlu.scala 102:30]
-  wire  _supported_T_399 = io_in_bits_3_bits_op == 7'h9; // @[VAlu.scala 105:16]
-  wire  _supported_T_400 = _supported_T_398 | _supported_T_399; // @[VAlu.scala 103:30]
-  wire  _supported_T_401 = io_in_bits_3_bits_op == 7'ha; // @[VAlu.scala 106:16]
-  wire  _supported_T_402 = _supported_T_400 | _supported_T_401; // @[VAlu.scala 105:28]
-  wire  _supported_T_403 = io_in_bits_3_bits_op == 7'hb; // @[VAlu.scala 107:16]
-  wire  _supported_T_404 = _supported_T_402 | _supported_T_403; // @[VAlu.scala 106:28]
-  wire  _supported_T_405 = io_in_bits_3_bits_op == 7'hc; // @[VAlu.scala 108:16]
-  wire  _supported_T_406 = _supported_T_404 | _supported_T_405; // @[VAlu.scala 107:28]
-  wire  _supported_T_407 = io_in_bits_3_bits_op == 7'hd; // @[VAlu.scala 109:16]
-  wire  _supported_T_408 = _supported_T_406 | _supported_T_407; // @[VAlu.scala 108:28]
-  wire  _supported_T_409 = io_in_bits_3_bits_op == 7'he; // @[VAlu.scala 110:16]
-  wire  _supported_T_410 = _supported_T_408 | _supported_T_409; // @[VAlu.scala 109:28]
-  wire  _supported_T_411 = io_in_bits_3_bits_op == 7'h13; // @[VAlu.scala 112:16]
-  wire  _supported_T_412 = _supported_T_410 | _supported_T_411; // @[VAlu.scala 110:28]
-  wire  _supported_T_413 = io_in_bits_3_bits_op == 7'h19; // @[VAlu.scala 113:16]
-  wire  _supported_T_414 = _supported_T_412 | _supported_T_413; // @[VAlu.scala 112:29]
-  wire  _supported_T_415 = io_in_bits_3_bits_op == 7'h1a; // @[VAlu.scala 114:16]
-  wire  _supported_T_416 = _supported_T_414 | _supported_T_415; // @[VAlu.scala 113:29]
-  wire  _supported_T_417 = io_in_bits_3_bits_op == 7'h1b; // @[VAlu.scala 115:16]
-  wire  _supported_T_418 = _supported_T_416 | _supported_T_417; // @[VAlu.scala 114:29]
-  wire  _supported_T_419 = io_in_bits_3_bits_op == 7'h1c; // @[VAlu.scala 116:16]
-  wire  _supported_T_420 = _supported_T_418 | _supported_T_419; // @[VAlu.scala 115:30]
-  wire  _supported_T_421 = io_in_bits_3_bits_op == 7'h1d; // @[VAlu.scala 117:16]
-  wire  _supported_T_422 = _supported_T_420 | _supported_T_421; // @[VAlu.scala 116:28]
-  wire  _supported_T_423 = io_in_bits_3_bits_op == 7'h1e; // @[VAlu.scala 118:16]
-  wire  _supported_T_424 = _supported_T_422 | _supported_T_423; // @[VAlu.scala 117:29]
-  wire  _supported_T_425 = io_in_bits_3_bits_op == 7'h21; // @[VAlu.scala 119:16]
-  wire  _supported_T_426 = _supported_T_424 | _supported_T_425; // @[VAlu.scala 118:29]
-  wire  _supported_T_427 = io_in_bits_3_bits_op == 7'h16; // @[VAlu.scala 120:16]
-  wire  _supported_T_428 = _supported_T_426 | _supported_T_427; // @[VAlu.scala 119:32]
-  wire  _supported_T_429 = io_in_bits_3_bits_op == 7'h14; // @[VAlu.scala 121:16]
-  wire  _supported_T_430 = _supported_T_428 | _supported_T_429; // @[VAlu.scala 120:29]
-  wire  _supported_T_431 = io_in_bits_3_bits_op == 7'h17; // @[VAlu.scala 122:16]
-  wire  _supported_T_432 = _supported_T_430 | _supported_T_431; // @[VAlu.scala 121:28]
-  wire  _supported_T_433 = io_in_bits_3_bits_op == 7'h18; // @[VAlu.scala 123:16]
-  wire  _supported_T_434 = _supported_T_432 | _supported_T_433; // @[VAlu.scala 122:29]
-  wire  _supported_T_435 = io_in_bits_3_bits_op == 7'h15; // @[VAlu.scala 124:16]
-  wire  _supported_T_436 = _supported_T_434 | _supported_T_435; // @[VAlu.scala 123:29]
-  wire  _supported_T_437 = io_in_bits_3_bits_op == 7'h22; // @[VAlu.scala 126:16]
-  wire  _supported_T_438 = _supported_T_436 | _supported_T_437; // @[VAlu.scala 124:29]
-  wire  _supported_T_439 = io_in_bits_3_bits_op == 7'h23; // @[VAlu.scala 127:16]
-  wire  _supported_T_440 = _supported_T_438 | _supported_T_439; // @[VAlu.scala 126:29]
-  wire  _supported_T_441 = io_in_bits_3_bits_op == 7'h24; // @[VAlu.scala 128:16]
-  wire  _supported_T_442 = _supported_T_440 | _supported_T_441; // @[VAlu.scala 127:29]
-  wire  _supported_T_443 = io_in_bits_3_bits_op == 7'h25; // @[VAlu.scala 129:16]
-  wire  _supported_T_444 = _supported_T_442 | _supported_T_443; // @[VAlu.scala 128:29]
-  wire  _supported_T_445 = io_in_bits_3_bits_op == 7'h26; // @[VAlu.scala 130:16]
-  wire  _supported_T_446 = _supported_T_444 | _supported_T_445; // @[VAlu.scala 129:31]
-  wire  _supported_T_447 = io_in_bits_3_bits_op == 7'h2d; // @[VAlu.scala 132:16]
-  wire  _supported_T_448 = _supported_T_446 | _supported_T_447; // @[VAlu.scala 130:31]
-  wire  _supported_T_449 = io_in_bits_3_bits_op == 7'h2e; // @[VAlu.scala 133:16]
-  wire  _supported_T_450 = _supported_T_448 | _supported_T_449; // @[VAlu.scala 132:31]
-  wire  _supported_T_451 = io_in_bits_3_bits_op == 7'h30; // @[VAlu.scala 134:16]
-  wire  _supported_T_452 = _supported_T_450 | _supported_T_451; // @[VAlu.scala 133:32]
-  wire  _supported_T_453 = io_in_bits_3_bits_op == 7'h27; // @[VAlu.scala 135:16]
-  wire  _supported_T_454 = _supported_T_452 | _supported_T_453; // @[VAlu.scala 134:30]
-  wire  _supported_T_455 = io_in_bits_3_bits_op == 7'h28; // @[VAlu.scala 136:16]
-  wire  _supported_T_456 = _supported_T_454 | _supported_T_455; // @[VAlu.scala 135:29]
-  wire  _supported_T_457 = io_in_bits_3_bits_op == 7'h2b; // @[VAlu.scala 137:16]
-  wire  _supported_T_458 = _supported_T_456 | _supported_T_457; // @[VAlu.scala 136:30]
-  wire  _supported_T_459 = io_in_bits_3_bits_op == 7'h2c; // @[VAlu.scala 138:16]
-  wire  _supported_T_460 = _supported_T_458 | _supported_T_459; // @[VAlu.scala 137:30]
-  wire  _supported_T_461 = io_in_bits_3_bits_op == 7'h29; // @[VAlu.scala 139:16]
-  wire  _supported_T_462 = _supported_T_460 | _supported_T_461; // @[VAlu.scala 138:31]
-  wire  _supported_T_463 = io_in_bits_3_bits_op == 7'h2a; // @[VAlu.scala 140:16]
-  wire  _supported_T_464 = _supported_T_462 | _supported_T_463; // @[VAlu.scala 139:30]
-  wire  _supported_T_465 = io_in_bits_3_bits_op == 7'h2f; // @[VAlu.scala 141:16]
-  wire  _supported_T_466 = _supported_T_464 | _supported_T_465; // @[VAlu.scala 140:31]
-  wire  _supported_T_467 = io_in_bits_3_bits_op == 7'h56; // @[VAlu.scala 143:16]
-  wire  _supported_T_468 = _supported_T_466 | _supported_T_467; // @[VAlu.scala 141:30]
-  wire  _supported_T_469 = io_in_bits_3_bits_op == 7'h59; // @[VAlu.scala 144:16]
-  wire  _supported_T_470 = _supported_T_468 | _supported_T_469; // @[VAlu.scala 143:33]
-  wire  _supported_T_471 = io_in_bits_3_bits_op == 7'h58; // @[VAlu.scala 145:16]
-  wire  _supported_T_472 = _supported_T_470 | _supported_T_471; // @[VAlu.scala 144:33]
-  wire  _supported_T_473 = io_in_bits_3_bits_op == 7'h5b; // @[VAlu.scala 146:16]
-  wire  _supported_T_474 = _supported_T_472 | _supported_T_473; // @[VAlu.scala 145:34]
-  wire  _supported_T_475 = io_in_bits_3_bits_op == 7'h5c; // @[VAlu.scala 147:16]
-  wire  _supported_T_476 = _supported_T_474 | _supported_T_475; // @[VAlu.scala 146:34]
-  wire  _supported_T_477 = io_in_bits_3_bits_op == 7'h5d; // @[VAlu.scala 148:16]
-  wire  _supported_T_478 = _supported_T_476 | _supported_T_477; // @[VAlu.scala 147:29]
-  wire  _supported_T_479 = io_in_bits_3_bits_op == 7'h5e; // @[VAlu.scala 149:16]
-  wire  _supported_T_480 = _supported_T_478 | _supported_T_479; // @[VAlu.scala 148:29]
-  wire  _supported_T_481 = io_in_bits_3_bits_op == 7'h5f; // @[VAlu.scala 150:16]
-  wire  _supported_T_482 = _supported_T_480 | _supported_T_481; // @[VAlu.scala 149:29]
-  wire  _supported_T_483 = io_in_bits_3_bits_op == 7'h60; // @[VAlu.scala 151:16]
-  wire  _supported_T_484 = _supported_T_482 | _supported_T_483; // @[VAlu.scala 150:32]
-  wire  _supported_T_485 = io_in_bits_3_bits_op == 7'h63; // @[VAlu.scala 153:16]
-  wire  _supported_T_486 = _supported_T_484 | _supported_T_485; // @[VAlu.scala 151:29]
-  wire  _supported_T_487 = io_in_bits_3_bits_op == 7'h64; // @[VAlu.scala 154:16]
-  wire  supported_3 = _supported_T_486 | _supported_T_487; // @[VAlu.scala 153:32]
-  wire  _T_94 = ~supported_3; // @[VAlu.scala 156:15]
-  wire  _T_107 = _supported_T_485 | _supported_T_487; // @[VAlu.scala 163:34]
-  wire [1:0] sparse_3 = io_in_bits_3_bits_sv_data[3:2]; // @[VAlu.scala 164:50]
+  wire  alu0_clock; // @[VAlu.scala 321:20]
+  wire  alu0_reset; // @[VAlu.scala 321:20]
+  wire  alu0_io_in_valid; // @[VAlu.scala 321:20]
+  wire [6:0] alu0_io_in_op; // @[VAlu.scala 321:20]
+  wire [2:0] alu0_io_in_f2; // @[VAlu.scala 321:20]
+  wire [2:0] alu0_io_in_sz; // @[VAlu.scala 321:20]
+  wire [5:0] alu0_io_in_vd_addr; // @[VAlu.scala 321:20]
+  wire [5:0] alu0_io_in_ve_addr; // @[VAlu.scala 321:20]
+  wire [31:0] alu0_io_in_sv_data; // @[VAlu.scala 321:20]
+  wire [255:0] alu0_io_read_0_data; // @[VAlu.scala 321:20]
+  wire [255:0] alu0_io_read_1_data; // @[VAlu.scala 321:20]
+  wire [255:0] alu0_io_read_2_data; // @[VAlu.scala 321:20]
+  wire [255:0] alu0_io_read_3_data; // @[VAlu.scala 321:20]
+  wire [255:0] alu0_io_read_4_data; // @[VAlu.scala 321:20]
+  wire [255:0] alu0_io_read_5_data; // @[VAlu.scala 321:20]
+  wire  alu0_io_write_0_valid; // @[VAlu.scala 321:20]
+  wire [5:0] alu0_io_write_0_addr; // @[VAlu.scala 321:20]
+  wire [255:0] alu0_io_write_0_data; // @[VAlu.scala 321:20]
+  wire  alu0_io_write_1_valid; // @[VAlu.scala 321:20]
+  wire [5:0] alu0_io_write_1_addr; // @[VAlu.scala 321:20]
+  wire [255:0] alu0_io_write_1_data; // @[VAlu.scala 321:20]
+  wire  alu0_io_whint_0_valid; // @[VAlu.scala 321:20]
+  wire [5:0] alu0_io_whint_0_addr; // @[VAlu.scala 321:20]
+  wire  alu0_io_whint_1_valid; // @[VAlu.scala 321:20]
+  wire [5:0] alu0_io_whint_1_addr; // @[VAlu.scala 321:20]
+  wire  alu1_clock; // @[VAlu.scala 355:20]
+  wire  alu1_reset; // @[VAlu.scala 355:20]
+  wire  alu1_io_in_valid; // @[VAlu.scala 355:20]
+  wire [6:0] alu1_io_in_op; // @[VAlu.scala 355:20]
+  wire [2:0] alu1_io_in_f2; // @[VAlu.scala 355:20]
+  wire [2:0] alu1_io_in_sz; // @[VAlu.scala 355:20]
+  wire [5:0] alu1_io_in_vd_addr; // @[VAlu.scala 355:20]
+  wire [5:0] alu1_io_in_ve_addr; // @[VAlu.scala 355:20]
+  wire [31:0] alu1_io_in_sv_data; // @[VAlu.scala 355:20]
+  wire [255:0] alu1_io_read_0_data; // @[VAlu.scala 355:20]
+  wire [255:0] alu1_io_read_1_data; // @[VAlu.scala 355:20]
+  wire [255:0] alu1_io_read_2_data; // @[VAlu.scala 355:20]
+  wire [255:0] alu1_io_read_3_data; // @[VAlu.scala 355:20]
+  wire [255:0] alu1_io_read_4_data; // @[VAlu.scala 355:20]
+  wire [255:0] alu1_io_read_5_data; // @[VAlu.scala 355:20]
+  wire  alu1_io_write_0_valid; // @[VAlu.scala 355:20]
+  wire [5:0] alu1_io_write_0_addr; // @[VAlu.scala 355:20]
+  wire [255:0] alu1_io_write_0_data; // @[VAlu.scala 355:20]
+  wire  alu1_io_write_1_valid; // @[VAlu.scala 355:20]
+  wire [5:0] alu1_io_write_1_addr; // @[VAlu.scala 355:20]
+  wire [255:0] alu1_io_write_1_data; // @[VAlu.scala 355:20]
+  wire  alu1_io_whint_0_valid; // @[VAlu.scala 355:20]
+  wire [5:0] alu1_io_whint_0_addr; // @[VAlu.scala 355:20]
+  wire  alu1_io_whint_1_valid; // @[VAlu.scala 355:20]
+  wire [5:0] alu1_io_whint_1_addr; // @[VAlu.scala 355:20]
+  wire  _T = io_in_valid & io_in_ready; // @[VAlu.scala 62:23]
+  wire  _supported_T_1 = io_in_bits_0_bits_op == 7'h35; // @[VAlu.scala 68:16]
+  wire  _supported_T_2 = io_in_bits_0_bits_op == 7'hf | _supported_T_1; // @[VAlu.scala 67:30]
+  wire  _supported_T_3 = io_in_bits_0_bits_op == 7'h6; // @[VAlu.scala 69:16]
+  wire  _supported_T_4 = _supported_T_2 | _supported_T_3; // @[VAlu.scala 68:29]
+  wire  _supported_T_5 = io_in_bits_0_bits_op == 7'h31; // @[VAlu.scala 70:16]
+  wire  _supported_T_6 = _supported_T_4 | _supported_T_5; // @[VAlu.scala 69:29]
+  wire  _supported_T_7 = io_in_bits_0_bits_op == 7'h33; // @[VAlu.scala 71:16]
+  wire  _supported_T_8 = _supported_T_6 | _supported_T_7; // @[VAlu.scala 70:30]
+  wire  _supported_T_9 = io_in_bits_0_bits_op == 7'h12; // @[VAlu.scala 72:16]
+  wire  _supported_T_10 = _supported_T_8 | _supported_T_9; // @[VAlu.scala 71:30]
+  wire  _supported_T_11 = io_in_bits_0_bits_op == 7'h1; // @[VAlu.scala 73:16]
+  wire  _supported_T_12 = _supported_T_10 | _supported_T_11; // @[VAlu.scala 72:30]
+  wire  _supported_T_13 = io_in_bits_0_bits_op == 7'h38; // @[VAlu.scala 74:16]
+  wire  _supported_T_14 = _supported_T_12 | _supported_T_13; // @[VAlu.scala 73:29]
+  wire  _supported_T_15 = io_in_bits_0_bits_op == 7'h39; // @[VAlu.scala 75:16]
+  wire  _supported_T_16 = _supported_T_14 | _supported_T_15; // @[VAlu.scala 74:30]
+  wire  _supported_T_17 = io_in_bits_0_bits_op == 7'h10; // @[VAlu.scala 76:16]
+  wire  _supported_T_18 = _supported_T_16 | _supported_T_17; // @[VAlu.scala 75:30]
+  wire  _supported_T_19 = io_in_bits_0_bits_op == 7'h11; // @[VAlu.scala 77:16]
+  wire  _supported_T_20 = _supported_T_18 | _supported_T_19; // @[VAlu.scala 76:29]
+  wire  _supported_T_21 = io_in_bits_0_bits_op == 7'h36; // @[VAlu.scala 78:16]
+  wire  _supported_T_22 = _supported_T_20 | _supported_T_21; // @[VAlu.scala 77:29]
+  wire  _supported_T_23 = io_in_bits_0_bits_op == 7'h37; // @[VAlu.scala 79:16]
+  wire  _supported_T_24 = _supported_T_22 | _supported_T_23; // @[VAlu.scala 78:30]
+  wire  _supported_T_25 = io_in_bits_0_bits_op == 7'h8; // @[VAlu.scala 80:16]
+  wire  _supported_T_26 = _supported_T_24 | _supported_T_25; // @[VAlu.scala 79:30]
+  wire  _supported_T_27 = io_in_bits_0_bits_op == 7'h7; // @[VAlu.scala 81:16]
+  wire  _supported_T_28 = _supported_T_26 | _supported_T_27; // @[VAlu.scala 80:30]
+  wire  _supported_T_29 = io_in_bits_0_bits_op == 7'h32; // @[VAlu.scala 82:16]
+  wire  _supported_T_30 = _supported_T_28 | _supported_T_29; // @[VAlu.scala 81:29]
+  wire  _supported_T_31 = io_in_bits_0_bits_op == 7'h34; // @[VAlu.scala 83:16]
+  wire  _supported_T_32 = _supported_T_30 | _supported_T_31; // @[VAlu.scala 82:30]
+  wire  _supported_T_33 = io_in_bits_0_bits_op == 7'h9; // @[VAlu.scala 85:16]
+  wire  _supported_T_34 = _supported_T_32 | _supported_T_33; // @[VAlu.scala 83:30]
+  wire  _supported_T_35 = io_in_bits_0_bits_op == 7'ha; // @[VAlu.scala 86:16]
+  wire  _supported_T_36 = _supported_T_34 | _supported_T_35; // @[VAlu.scala 85:28]
+  wire  _supported_T_37 = io_in_bits_0_bits_op == 7'hb; // @[VAlu.scala 87:16]
+  wire  _supported_T_38 = _supported_T_36 | _supported_T_37; // @[VAlu.scala 86:28]
+  wire  _supported_T_39 = io_in_bits_0_bits_op == 7'hc; // @[VAlu.scala 88:16]
+  wire  _supported_T_40 = _supported_T_38 | _supported_T_39; // @[VAlu.scala 87:28]
+  wire  _supported_T_41 = io_in_bits_0_bits_op == 7'hd; // @[VAlu.scala 89:16]
+  wire  _supported_T_42 = _supported_T_40 | _supported_T_41; // @[VAlu.scala 88:28]
+  wire  _supported_T_43 = io_in_bits_0_bits_op == 7'he; // @[VAlu.scala 90:16]
+  wire  _supported_T_44 = _supported_T_42 | _supported_T_43; // @[VAlu.scala 89:28]
+  wire  _supported_T_45 = io_in_bits_0_bits_op == 7'h13; // @[VAlu.scala 92:16]
+  wire  _supported_T_46 = _supported_T_44 | _supported_T_45; // @[VAlu.scala 90:28]
+  wire  _supported_T_47 = io_in_bits_0_bits_op == 7'h19; // @[VAlu.scala 93:16]
+  wire  _supported_T_48 = _supported_T_46 | _supported_T_47; // @[VAlu.scala 92:29]
+  wire  _supported_T_49 = io_in_bits_0_bits_op == 7'h1a; // @[VAlu.scala 94:16]
+  wire  _supported_T_50 = _supported_T_48 | _supported_T_49; // @[VAlu.scala 93:29]
+  wire  _supported_T_51 = io_in_bits_0_bits_op == 7'h1b; // @[VAlu.scala 95:16]
+  wire  _supported_T_52 = _supported_T_50 | _supported_T_51; // @[VAlu.scala 94:29]
+  wire  _supported_T_53 = io_in_bits_0_bits_op == 7'h1c; // @[VAlu.scala 96:16]
+  wire  _supported_T_54 = _supported_T_52 | _supported_T_53; // @[VAlu.scala 95:30]
+  wire  _supported_T_55 = io_in_bits_0_bits_op == 7'h1d; // @[VAlu.scala 97:16]
+  wire  _supported_T_56 = _supported_T_54 | _supported_T_55; // @[VAlu.scala 96:28]
+  wire  _supported_T_57 = io_in_bits_0_bits_op == 7'h1e; // @[VAlu.scala 98:16]
+  wire  _supported_T_58 = _supported_T_56 | _supported_T_57; // @[VAlu.scala 97:29]
+  wire  _supported_T_59 = io_in_bits_0_bits_op == 7'h21; // @[VAlu.scala 99:16]
+  wire  _supported_T_60 = _supported_T_58 | _supported_T_59; // @[VAlu.scala 98:29]
+  wire  _supported_T_61 = io_in_bits_0_bits_op == 7'h16; // @[VAlu.scala 100:16]
+  wire  _supported_T_62 = _supported_T_60 | _supported_T_61; // @[VAlu.scala 99:32]
+  wire  _supported_T_63 = io_in_bits_0_bits_op == 7'h14; // @[VAlu.scala 101:16]
+  wire  _supported_T_64 = _supported_T_62 | _supported_T_63; // @[VAlu.scala 100:29]
+  wire  _supported_T_65 = io_in_bits_0_bits_op == 7'h17; // @[VAlu.scala 102:16]
+  wire  _supported_T_66 = _supported_T_64 | _supported_T_65; // @[VAlu.scala 101:28]
+  wire  _supported_T_67 = io_in_bits_0_bits_op == 7'h18; // @[VAlu.scala 103:16]
+  wire  _supported_T_68 = _supported_T_66 | _supported_T_67; // @[VAlu.scala 102:29]
+  wire  _supported_T_69 = io_in_bits_0_bits_op == 7'h15; // @[VAlu.scala 104:16]
+  wire  _supported_T_70 = _supported_T_68 | _supported_T_69; // @[VAlu.scala 103:29]
+  wire  _supported_T_71 = io_in_bits_0_bits_op == 7'h22; // @[VAlu.scala 106:16]
+  wire  _supported_T_72 = _supported_T_70 | _supported_T_71; // @[VAlu.scala 104:29]
+  wire  _supported_T_73 = io_in_bits_0_bits_op == 7'h23; // @[VAlu.scala 107:16]
+  wire  _supported_T_74 = _supported_T_72 | _supported_T_73; // @[VAlu.scala 106:29]
+  wire  _supported_T_75 = io_in_bits_0_bits_op == 7'h24; // @[VAlu.scala 108:16]
+  wire  _supported_T_76 = _supported_T_74 | _supported_T_75; // @[VAlu.scala 107:29]
+  wire  _supported_T_77 = io_in_bits_0_bits_op == 7'h25; // @[VAlu.scala 109:16]
+  wire  _supported_T_78 = _supported_T_76 | _supported_T_77; // @[VAlu.scala 108:29]
+  wire  _supported_T_79 = io_in_bits_0_bits_op == 7'h26; // @[VAlu.scala 110:16]
+  wire  _supported_T_80 = _supported_T_78 | _supported_T_79; // @[VAlu.scala 109:31]
+  wire  _supported_T_81 = io_in_bits_0_bits_op == 7'h2d; // @[VAlu.scala 112:16]
+  wire  _supported_T_82 = _supported_T_80 | _supported_T_81; // @[VAlu.scala 110:31]
+  wire  _supported_T_83 = io_in_bits_0_bits_op == 7'h2e; // @[VAlu.scala 113:16]
+  wire  _supported_T_84 = _supported_T_82 | _supported_T_83; // @[VAlu.scala 112:31]
+  wire  _supported_T_85 = io_in_bits_0_bits_op == 7'h30; // @[VAlu.scala 114:16]
+  wire  _supported_T_86 = _supported_T_84 | _supported_T_85; // @[VAlu.scala 113:32]
+  wire  _supported_T_87 = io_in_bits_0_bits_op == 7'h27; // @[VAlu.scala 115:16]
+  wire  _supported_T_88 = _supported_T_86 | _supported_T_87; // @[VAlu.scala 114:30]
+  wire  _supported_T_89 = io_in_bits_0_bits_op == 7'h28; // @[VAlu.scala 116:16]
+  wire  _supported_T_90 = _supported_T_88 | _supported_T_89; // @[VAlu.scala 115:29]
+  wire  _supported_T_91 = io_in_bits_0_bits_op == 7'h2b; // @[VAlu.scala 117:16]
+  wire  _supported_T_92 = _supported_T_90 | _supported_T_91; // @[VAlu.scala 116:30]
+  wire  _supported_T_93 = io_in_bits_0_bits_op == 7'h2c; // @[VAlu.scala 118:16]
+  wire  _supported_T_94 = _supported_T_92 | _supported_T_93; // @[VAlu.scala 117:30]
+  wire  _supported_T_95 = io_in_bits_0_bits_op == 7'h29; // @[VAlu.scala 119:16]
+  wire  _supported_T_96 = _supported_T_94 | _supported_T_95; // @[VAlu.scala 118:31]
+  wire  _supported_T_97 = io_in_bits_0_bits_op == 7'h2a; // @[VAlu.scala 120:16]
+  wire  _supported_T_98 = _supported_T_96 | _supported_T_97; // @[VAlu.scala 119:30]
+  wire  _supported_T_99 = io_in_bits_0_bits_op == 7'h2f; // @[VAlu.scala 121:16]
+  wire  _supported_T_100 = _supported_T_98 | _supported_T_99; // @[VAlu.scala 120:31]
+  wire  _supported_T_101 = io_in_bits_0_bits_op == 7'h3a; // @[VAlu.scala 123:16]
+  wire  _supported_T_102 = _supported_T_100 | _supported_T_101; // @[VAlu.scala 121:30]
+  wire  _supported_T_103 = io_in_bits_0_bits_op == 7'h3d; // @[VAlu.scala 124:16]
+  wire  _supported_T_104 = _supported_T_102 | _supported_T_103; // @[VAlu.scala 123:33]
+  wire  _supported_T_105 = io_in_bits_0_bits_op == 7'h3c; // @[VAlu.scala 125:16]
+  wire  _supported_T_106 = _supported_T_104 | _supported_T_105; // @[VAlu.scala 124:33]
+  wire  _supported_T_107 = io_in_bits_0_bits_op == 7'h3f; // @[VAlu.scala 126:16]
+  wire  _supported_T_108 = _supported_T_106 | _supported_T_107; // @[VAlu.scala 125:34]
+  wire  _supported_T_109 = io_in_bits_0_bits_op == 7'h40; // @[VAlu.scala 127:16]
+  wire  _supported_T_110 = _supported_T_108 | _supported_T_109; // @[VAlu.scala 126:34]
+  wire  _supported_T_111 = io_in_bits_0_bits_op == 7'h41; // @[VAlu.scala 128:16]
+  wire  _supported_T_112 = _supported_T_110 | _supported_T_111; // @[VAlu.scala 127:29]
+  wire  _supported_T_113 = io_in_bits_0_bits_op == 7'h42; // @[VAlu.scala 129:16]
+  wire  _supported_T_114 = _supported_T_112 | _supported_T_113; // @[VAlu.scala 128:29]
+  wire  _supported_T_115 = io_in_bits_0_bits_op == 7'h43; // @[VAlu.scala 130:16]
+  wire  _supported_T_116 = _supported_T_114 | _supported_T_115; // @[VAlu.scala 129:29]
+  wire  _supported_T_117 = io_in_bits_0_bits_op == 7'h44; // @[VAlu.scala 131:16]
+  wire  _supported_T_118 = _supported_T_116 | _supported_T_117; // @[VAlu.scala 130:32]
+  wire  _supported_T_119 = io_in_bits_0_bits_op == 7'h46; // @[VAlu.scala 133:16]
+  wire  _supported_T_120 = _supported_T_118 | _supported_T_119; // @[VAlu.scala 131:29]
+  wire  _supported_T_121 = io_in_bits_0_bits_op == 7'h47; // @[VAlu.scala 134:16]
+  wire  supported = _supported_T_120 | _supported_T_121; // @[VAlu.scala 133:32]
+  wire  _T_1 = ~supported; // @[VAlu.scala 136:15]
+  wire  _T_3 = ~reset; // @[VAlu.scala 137:17]
+  wire  _T_14 = _supported_T_119 | _supported_T_121; // @[VAlu.scala 143:34]
+  wire [1:0] sparse = io_in_bits_0_bits_sv_data[3:2]; // @[VAlu.scala 144:50]
+  wire  _supported_T_123 = io_in_bits_1_bits_op == 7'h35; // @[VAlu.scala 68:16]
+  wire  _supported_T_124 = io_in_bits_1_bits_op == 7'hf | _supported_T_123; // @[VAlu.scala 67:30]
+  wire  _supported_T_125 = io_in_bits_1_bits_op == 7'h6; // @[VAlu.scala 69:16]
+  wire  _supported_T_126 = _supported_T_124 | _supported_T_125; // @[VAlu.scala 68:29]
+  wire  _supported_T_127 = io_in_bits_1_bits_op == 7'h31; // @[VAlu.scala 70:16]
+  wire  _supported_T_128 = _supported_T_126 | _supported_T_127; // @[VAlu.scala 69:29]
+  wire  _supported_T_129 = io_in_bits_1_bits_op == 7'h33; // @[VAlu.scala 71:16]
+  wire  _supported_T_130 = _supported_T_128 | _supported_T_129; // @[VAlu.scala 70:30]
+  wire  _supported_T_131 = io_in_bits_1_bits_op == 7'h12; // @[VAlu.scala 72:16]
+  wire  _supported_T_132 = _supported_T_130 | _supported_T_131; // @[VAlu.scala 71:30]
+  wire  _supported_T_133 = io_in_bits_1_bits_op == 7'h1; // @[VAlu.scala 73:16]
+  wire  _supported_T_134 = _supported_T_132 | _supported_T_133; // @[VAlu.scala 72:30]
+  wire  _supported_T_135 = io_in_bits_1_bits_op == 7'h38; // @[VAlu.scala 74:16]
+  wire  _supported_T_136 = _supported_T_134 | _supported_T_135; // @[VAlu.scala 73:29]
+  wire  _supported_T_137 = io_in_bits_1_bits_op == 7'h39; // @[VAlu.scala 75:16]
+  wire  _supported_T_138 = _supported_T_136 | _supported_T_137; // @[VAlu.scala 74:30]
+  wire  _supported_T_139 = io_in_bits_1_bits_op == 7'h10; // @[VAlu.scala 76:16]
+  wire  _supported_T_140 = _supported_T_138 | _supported_T_139; // @[VAlu.scala 75:30]
+  wire  _supported_T_141 = io_in_bits_1_bits_op == 7'h11; // @[VAlu.scala 77:16]
+  wire  _supported_T_142 = _supported_T_140 | _supported_T_141; // @[VAlu.scala 76:29]
+  wire  _supported_T_143 = io_in_bits_1_bits_op == 7'h36; // @[VAlu.scala 78:16]
+  wire  _supported_T_144 = _supported_T_142 | _supported_T_143; // @[VAlu.scala 77:29]
+  wire  _supported_T_145 = io_in_bits_1_bits_op == 7'h37; // @[VAlu.scala 79:16]
+  wire  _supported_T_146 = _supported_T_144 | _supported_T_145; // @[VAlu.scala 78:30]
+  wire  _supported_T_147 = io_in_bits_1_bits_op == 7'h8; // @[VAlu.scala 80:16]
+  wire  _supported_T_148 = _supported_T_146 | _supported_T_147; // @[VAlu.scala 79:30]
+  wire  _supported_T_149 = io_in_bits_1_bits_op == 7'h7; // @[VAlu.scala 81:16]
+  wire  _supported_T_150 = _supported_T_148 | _supported_T_149; // @[VAlu.scala 80:30]
+  wire  _supported_T_151 = io_in_bits_1_bits_op == 7'h32; // @[VAlu.scala 82:16]
+  wire  _supported_T_152 = _supported_T_150 | _supported_T_151; // @[VAlu.scala 81:29]
+  wire  _supported_T_153 = io_in_bits_1_bits_op == 7'h34; // @[VAlu.scala 83:16]
+  wire  _supported_T_154 = _supported_T_152 | _supported_T_153; // @[VAlu.scala 82:30]
+  wire  _supported_T_155 = io_in_bits_1_bits_op == 7'h9; // @[VAlu.scala 85:16]
+  wire  _supported_T_156 = _supported_T_154 | _supported_T_155; // @[VAlu.scala 83:30]
+  wire  _supported_T_157 = io_in_bits_1_bits_op == 7'ha; // @[VAlu.scala 86:16]
+  wire  _supported_T_158 = _supported_T_156 | _supported_T_157; // @[VAlu.scala 85:28]
+  wire  _supported_T_159 = io_in_bits_1_bits_op == 7'hb; // @[VAlu.scala 87:16]
+  wire  _supported_T_160 = _supported_T_158 | _supported_T_159; // @[VAlu.scala 86:28]
+  wire  _supported_T_161 = io_in_bits_1_bits_op == 7'hc; // @[VAlu.scala 88:16]
+  wire  _supported_T_162 = _supported_T_160 | _supported_T_161; // @[VAlu.scala 87:28]
+  wire  _supported_T_163 = io_in_bits_1_bits_op == 7'hd; // @[VAlu.scala 89:16]
+  wire  _supported_T_164 = _supported_T_162 | _supported_T_163; // @[VAlu.scala 88:28]
+  wire  _supported_T_165 = io_in_bits_1_bits_op == 7'he; // @[VAlu.scala 90:16]
+  wire  _supported_T_166 = _supported_T_164 | _supported_T_165; // @[VAlu.scala 89:28]
+  wire  _supported_T_167 = io_in_bits_1_bits_op == 7'h13; // @[VAlu.scala 92:16]
+  wire  _supported_T_168 = _supported_T_166 | _supported_T_167; // @[VAlu.scala 90:28]
+  wire  _supported_T_169 = io_in_bits_1_bits_op == 7'h19; // @[VAlu.scala 93:16]
+  wire  _supported_T_170 = _supported_T_168 | _supported_T_169; // @[VAlu.scala 92:29]
+  wire  _supported_T_171 = io_in_bits_1_bits_op == 7'h1a; // @[VAlu.scala 94:16]
+  wire  _supported_T_172 = _supported_T_170 | _supported_T_171; // @[VAlu.scala 93:29]
+  wire  _supported_T_173 = io_in_bits_1_bits_op == 7'h1b; // @[VAlu.scala 95:16]
+  wire  _supported_T_174 = _supported_T_172 | _supported_T_173; // @[VAlu.scala 94:29]
+  wire  _supported_T_175 = io_in_bits_1_bits_op == 7'h1c; // @[VAlu.scala 96:16]
+  wire  _supported_T_176 = _supported_T_174 | _supported_T_175; // @[VAlu.scala 95:30]
+  wire  _supported_T_177 = io_in_bits_1_bits_op == 7'h1d; // @[VAlu.scala 97:16]
+  wire  _supported_T_178 = _supported_T_176 | _supported_T_177; // @[VAlu.scala 96:28]
+  wire  _supported_T_179 = io_in_bits_1_bits_op == 7'h1e; // @[VAlu.scala 98:16]
+  wire  _supported_T_180 = _supported_T_178 | _supported_T_179; // @[VAlu.scala 97:29]
+  wire  _supported_T_181 = io_in_bits_1_bits_op == 7'h21; // @[VAlu.scala 99:16]
+  wire  _supported_T_182 = _supported_T_180 | _supported_T_181; // @[VAlu.scala 98:29]
+  wire  _supported_T_183 = io_in_bits_1_bits_op == 7'h16; // @[VAlu.scala 100:16]
+  wire  _supported_T_184 = _supported_T_182 | _supported_T_183; // @[VAlu.scala 99:32]
+  wire  _supported_T_185 = io_in_bits_1_bits_op == 7'h14; // @[VAlu.scala 101:16]
+  wire  _supported_T_186 = _supported_T_184 | _supported_T_185; // @[VAlu.scala 100:29]
+  wire  _supported_T_187 = io_in_bits_1_bits_op == 7'h17; // @[VAlu.scala 102:16]
+  wire  _supported_T_188 = _supported_T_186 | _supported_T_187; // @[VAlu.scala 101:28]
+  wire  _supported_T_189 = io_in_bits_1_bits_op == 7'h18; // @[VAlu.scala 103:16]
+  wire  _supported_T_190 = _supported_T_188 | _supported_T_189; // @[VAlu.scala 102:29]
+  wire  _supported_T_191 = io_in_bits_1_bits_op == 7'h15; // @[VAlu.scala 104:16]
+  wire  _supported_T_192 = _supported_T_190 | _supported_T_191; // @[VAlu.scala 103:29]
+  wire  _supported_T_193 = io_in_bits_1_bits_op == 7'h22; // @[VAlu.scala 106:16]
+  wire  _supported_T_194 = _supported_T_192 | _supported_T_193; // @[VAlu.scala 104:29]
+  wire  _supported_T_195 = io_in_bits_1_bits_op == 7'h23; // @[VAlu.scala 107:16]
+  wire  _supported_T_196 = _supported_T_194 | _supported_T_195; // @[VAlu.scala 106:29]
+  wire  _supported_T_197 = io_in_bits_1_bits_op == 7'h24; // @[VAlu.scala 108:16]
+  wire  _supported_T_198 = _supported_T_196 | _supported_T_197; // @[VAlu.scala 107:29]
+  wire  _supported_T_199 = io_in_bits_1_bits_op == 7'h25; // @[VAlu.scala 109:16]
+  wire  _supported_T_200 = _supported_T_198 | _supported_T_199; // @[VAlu.scala 108:29]
+  wire  _supported_T_201 = io_in_bits_1_bits_op == 7'h26; // @[VAlu.scala 110:16]
+  wire  _supported_T_202 = _supported_T_200 | _supported_T_201; // @[VAlu.scala 109:31]
+  wire  _supported_T_203 = io_in_bits_1_bits_op == 7'h2d; // @[VAlu.scala 112:16]
+  wire  _supported_T_204 = _supported_T_202 | _supported_T_203; // @[VAlu.scala 110:31]
+  wire  _supported_T_205 = io_in_bits_1_bits_op == 7'h2e; // @[VAlu.scala 113:16]
+  wire  _supported_T_206 = _supported_T_204 | _supported_T_205; // @[VAlu.scala 112:31]
+  wire  _supported_T_207 = io_in_bits_1_bits_op == 7'h30; // @[VAlu.scala 114:16]
+  wire  _supported_T_208 = _supported_T_206 | _supported_T_207; // @[VAlu.scala 113:32]
+  wire  _supported_T_209 = io_in_bits_1_bits_op == 7'h27; // @[VAlu.scala 115:16]
+  wire  _supported_T_210 = _supported_T_208 | _supported_T_209; // @[VAlu.scala 114:30]
+  wire  _supported_T_211 = io_in_bits_1_bits_op == 7'h28; // @[VAlu.scala 116:16]
+  wire  _supported_T_212 = _supported_T_210 | _supported_T_211; // @[VAlu.scala 115:29]
+  wire  _supported_T_213 = io_in_bits_1_bits_op == 7'h2b; // @[VAlu.scala 117:16]
+  wire  _supported_T_214 = _supported_T_212 | _supported_T_213; // @[VAlu.scala 116:30]
+  wire  _supported_T_215 = io_in_bits_1_bits_op == 7'h2c; // @[VAlu.scala 118:16]
+  wire  _supported_T_216 = _supported_T_214 | _supported_T_215; // @[VAlu.scala 117:30]
+  wire  _supported_T_217 = io_in_bits_1_bits_op == 7'h29; // @[VAlu.scala 119:16]
+  wire  _supported_T_218 = _supported_T_216 | _supported_T_217; // @[VAlu.scala 118:31]
+  wire  _supported_T_219 = io_in_bits_1_bits_op == 7'h2a; // @[VAlu.scala 120:16]
+  wire  _supported_T_220 = _supported_T_218 | _supported_T_219; // @[VAlu.scala 119:30]
+  wire  _supported_T_221 = io_in_bits_1_bits_op == 7'h2f; // @[VAlu.scala 121:16]
+  wire  _supported_T_222 = _supported_T_220 | _supported_T_221; // @[VAlu.scala 120:31]
+  wire  _supported_T_223 = io_in_bits_1_bits_op == 7'h3a; // @[VAlu.scala 123:16]
+  wire  _supported_T_224 = _supported_T_222 | _supported_T_223; // @[VAlu.scala 121:30]
+  wire  _supported_T_225 = io_in_bits_1_bits_op == 7'h3d; // @[VAlu.scala 124:16]
+  wire  _supported_T_226 = _supported_T_224 | _supported_T_225; // @[VAlu.scala 123:33]
+  wire  _supported_T_227 = io_in_bits_1_bits_op == 7'h3c; // @[VAlu.scala 125:16]
+  wire  _supported_T_228 = _supported_T_226 | _supported_T_227; // @[VAlu.scala 124:33]
+  wire  _supported_T_229 = io_in_bits_1_bits_op == 7'h3f; // @[VAlu.scala 126:16]
+  wire  _supported_T_230 = _supported_T_228 | _supported_T_229; // @[VAlu.scala 125:34]
+  wire  _supported_T_231 = io_in_bits_1_bits_op == 7'h40; // @[VAlu.scala 127:16]
+  wire  _supported_T_232 = _supported_T_230 | _supported_T_231; // @[VAlu.scala 126:34]
+  wire  _supported_T_233 = io_in_bits_1_bits_op == 7'h41; // @[VAlu.scala 128:16]
+  wire  _supported_T_234 = _supported_T_232 | _supported_T_233; // @[VAlu.scala 127:29]
+  wire  _supported_T_235 = io_in_bits_1_bits_op == 7'h42; // @[VAlu.scala 129:16]
+  wire  _supported_T_236 = _supported_T_234 | _supported_T_235; // @[VAlu.scala 128:29]
+  wire  _supported_T_237 = io_in_bits_1_bits_op == 7'h43; // @[VAlu.scala 130:16]
+  wire  _supported_T_238 = _supported_T_236 | _supported_T_237; // @[VAlu.scala 129:29]
+  wire  _supported_T_239 = io_in_bits_1_bits_op == 7'h44; // @[VAlu.scala 131:16]
+  wire  _supported_T_240 = _supported_T_238 | _supported_T_239; // @[VAlu.scala 130:32]
+  wire  _supported_T_241 = io_in_bits_1_bits_op == 7'h46; // @[VAlu.scala 133:16]
+  wire  _supported_T_242 = _supported_T_240 | _supported_T_241; // @[VAlu.scala 131:29]
+  wire  _supported_T_243 = io_in_bits_1_bits_op == 7'h47; // @[VAlu.scala 134:16]
+  wire  supported_1 = _supported_T_242 | _supported_T_243; // @[VAlu.scala 133:32]
+  wire  _T_32 = ~supported_1; // @[VAlu.scala 136:15]
+  wire  _T_45 = _supported_T_241 | _supported_T_243; // @[VAlu.scala 143:34]
+  wire [1:0] sparse_1 = io_in_bits_1_bits_sv_data[3:2]; // @[VAlu.scala 144:50]
+  wire  _supported_T_245 = io_in_bits_2_bits_op == 7'h35; // @[VAlu.scala 68:16]
+  wire  _supported_T_246 = io_in_bits_2_bits_op == 7'hf | _supported_T_245; // @[VAlu.scala 67:30]
+  wire  _supported_T_247 = io_in_bits_2_bits_op == 7'h6; // @[VAlu.scala 69:16]
+  wire  _supported_T_248 = _supported_T_246 | _supported_T_247; // @[VAlu.scala 68:29]
+  wire  _supported_T_249 = io_in_bits_2_bits_op == 7'h31; // @[VAlu.scala 70:16]
+  wire  _supported_T_250 = _supported_T_248 | _supported_T_249; // @[VAlu.scala 69:29]
+  wire  _supported_T_251 = io_in_bits_2_bits_op == 7'h33; // @[VAlu.scala 71:16]
+  wire  _supported_T_252 = _supported_T_250 | _supported_T_251; // @[VAlu.scala 70:30]
+  wire  _supported_T_253 = io_in_bits_2_bits_op == 7'h12; // @[VAlu.scala 72:16]
+  wire  _supported_T_254 = _supported_T_252 | _supported_T_253; // @[VAlu.scala 71:30]
+  wire  _supported_T_255 = io_in_bits_2_bits_op == 7'h1; // @[VAlu.scala 73:16]
+  wire  _supported_T_256 = _supported_T_254 | _supported_T_255; // @[VAlu.scala 72:30]
+  wire  _supported_T_257 = io_in_bits_2_bits_op == 7'h38; // @[VAlu.scala 74:16]
+  wire  _supported_T_258 = _supported_T_256 | _supported_T_257; // @[VAlu.scala 73:29]
+  wire  _supported_T_259 = io_in_bits_2_bits_op == 7'h39; // @[VAlu.scala 75:16]
+  wire  _supported_T_260 = _supported_T_258 | _supported_T_259; // @[VAlu.scala 74:30]
+  wire  _supported_T_261 = io_in_bits_2_bits_op == 7'h10; // @[VAlu.scala 76:16]
+  wire  _supported_T_262 = _supported_T_260 | _supported_T_261; // @[VAlu.scala 75:30]
+  wire  _supported_T_263 = io_in_bits_2_bits_op == 7'h11; // @[VAlu.scala 77:16]
+  wire  _supported_T_264 = _supported_T_262 | _supported_T_263; // @[VAlu.scala 76:29]
+  wire  _supported_T_265 = io_in_bits_2_bits_op == 7'h36; // @[VAlu.scala 78:16]
+  wire  _supported_T_266 = _supported_T_264 | _supported_T_265; // @[VAlu.scala 77:29]
+  wire  _supported_T_267 = io_in_bits_2_bits_op == 7'h37; // @[VAlu.scala 79:16]
+  wire  _supported_T_268 = _supported_T_266 | _supported_T_267; // @[VAlu.scala 78:30]
+  wire  _supported_T_269 = io_in_bits_2_bits_op == 7'h8; // @[VAlu.scala 80:16]
+  wire  _supported_T_270 = _supported_T_268 | _supported_T_269; // @[VAlu.scala 79:30]
+  wire  _supported_T_271 = io_in_bits_2_bits_op == 7'h7; // @[VAlu.scala 81:16]
+  wire  _supported_T_272 = _supported_T_270 | _supported_T_271; // @[VAlu.scala 80:30]
+  wire  _supported_T_273 = io_in_bits_2_bits_op == 7'h32; // @[VAlu.scala 82:16]
+  wire  _supported_T_274 = _supported_T_272 | _supported_T_273; // @[VAlu.scala 81:29]
+  wire  _supported_T_275 = io_in_bits_2_bits_op == 7'h34; // @[VAlu.scala 83:16]
+  wire  _supported_T_276 = _supported_T_274 | _supported_T_275; // @[VAlu.scala 82:30]
+  wire  _supported_T_277 = io_in_bits_2_bits_op == 7'h9; // @[VAlu.scala 85:16]
+  wire  _supported_T_278 = _supported_T_276 | _supported_T_277; // @[VAlu.scala 83:30]
+  wire  _supported_T_279 = io_in_bits_2_bits_op == 7'ha; // @[VAlu.scala 86:16]
+  wire  _supported_T_280 = _supported_T_278 | _supported_T_279; // @[VAlu.scala 85:28]
+  wire  _supported_T_281 = io_in_bits_2_bits_op == 7'hb; // @[VAlu.scala 87:16]
+  wire  _supported_T_282 = _supported_T_280 | _supported_T_281; // @[VAlu.scala 86:28]
+  wire  _supported_T_283 = io_in_bits_2_bits_op == 7'hc; // @[VAlu.scala 88:16]
+  wire  _supported_T_284 = _supported_T_282 | _supported_T_283; // @[VAlu.scala 87:28]
+  wire  _supported_T_285 = io_in_bits_2_bits_op == 7'hd; // @[VAlu.scala 89:16]
+  wire  _supported_T_286 = _supported_T_284 | _supported_T_285; // @[VAlu.scala 88:28]
+  wire  _supported_T_287 = io_in_bits_2_bits_op == 7'he; // @[VAlu.scala 90:16]
+  wire  _supported_T_288 = _supported_T_286 | _supported_T_287; // @[VAlu.scala 89:28]
+  wire  _supported_T_289 = io_in_bits_2_bits_op == 7'h13; // @[VAlu.scala 92:16]
+  wire  _supported_T_290 = _supported_T_288 | _supported_T_289; // @[VAlu.scala 90:28]
+  wire  _supported_T_291 = io_in_bits_2_bits_op == 7'h19; // @[VAlu.scala 93:16]
+  wire  _supported_T_292 = _supported_T_290 | _supported_T_291; // @[VAlu.scala 92:29]
+  wire  _supported_T_293 = io_in_bits_2_bits_op == 7'h1a; // @[VAlu.scala 94:16]
+  wire  _supported_T_294 = _supported_T_292 | _supported_T_293; // @[VAlu.scala 93:29]
+  wire  _supported_T_295 = io_in_bits_2_bits_op == 7'h1b; // @[VAlu.scala 95:16]
+  wire  _supported_T_296 = _supported_T_294 | _supported_T_295; // @[VAlu.scala 94:29]
+  wire  _supported_T_297 = io_in_bits_2_bits_op == 7'h1c; // @[VAlu.scala 96:16]
+  wire  _supported_T_298 = _supported_T_296 | _supported_T_297; // @[VAlu.scala 95:30]
+  wire  _supported_T_299 = io_in_bits_2_bits_op == 7'h1d; // @[VAlu.scala 97:16]
+  wire  _supported_T_300 = _supported_T_298 | _supported_T_299; // @[VAlu.scala 96:28]
+  wire  _supported_T_301 = io_in_bits_2_bits_op == 7'h1e; // @[VAlu.scala 98:16]
+  wire  _supported_T_302 = _supported_T_300 | _supported_T_301; // @[VAlu.scala 97:29]
+  wire  _supported_T_303 = io_in_bits_2_bits_op == 7'h21; // @[VAlu.scala 99:16]
+  wire  _supported_T_304 = _supported_T_302 | _supported_T_303; // @[VAlu.scala 98:29]
+  wire  _supported_T_305 = io_in_bits_2_bits_op == 7'h16; // @[VAlu.scala 100:16]
+  wire  _supported_T_306 = _supported_T_304 | _supported_T_305; // @[VAlu.scala 99:32]
+  wire  _supported_T_307 = io_in_bits_2_bits_op == 7'h14; // @[VAlu.scala 101:16]
+  wire  _supported_T_308 = _supported_T_306 | _supported_T_307; // @[VAlu.scala 100:29]
+  wire  _supported_T_309 = io_in_bits_2_bits_op == 7'h17; // @[VAlu.scala 102:16]
+  wire  _supported_T_310 = _supported_T_308 | _supported_T_309; // @[VAlu.scala 101:28]
+  wire  _supported_T_311 = io_in_bits_2_bits_op == 7'h18; // @[VAlu.scala 103:16]
+  wire  _supported_T_312 = _supported_T_310 | _supported_T_311; // @[VAlu.scala 102:29]
+  wire  _supported_T_313 = io_in_bits_2_bits_op == 7'h15; // @[VAlu.scala 104:16]
+  wire  _supported_T_314 = _supported_T_312 | _supported_T_313; // @[VAlu.scala 103:29]
+  wire  _supported_T_315 = io_in_bits_2_bits_op == 7'h22; // @[VAlu.scala 106:16]
+  wire  _supported_T_316 = _supported_T_314 | _supported_T_315; // @[VAlu.scala 104:29]
+  wire  _supported_T_317 = io_in_bits_2_bits_op == 7'h23; // @[VAlu.scala 107:16]
+  wire  _supported_T_318 = _supported_T_316 | _supported_T_317; // @[VAlu.scala 106:29]
+  wire  _supported_T_319 = io_in_bits_2_bits_op == 7'h24; // @[VAlu.scala 108:16]
+  wire  _supported_T_320 = _supported_T_318 | _supported_T_319; // @[VAlu.scala 107:29]
+  wire  _supported_T_321 = io_in_bits_2_bits_op == 7'h25; // @[VAlu.scala 109:16]
+  wire  _supported_T_322 = _supported_T_320 | _supported_T_321; // @[VAlu.scala 108:29]
+  wire  _supported_T_323 = io_in_bits_2_bits_op == 7'h26; // @[VAlu.scala 110:16]
+  wire  _supported_T_324 = _supported_T_322 | _supported_T_323; // @[VAlu.scala 109:31]
+  wire  _supported_T_325 = io_in_bits_2_bits_op == 7'h2d; // @[VAlu.scala 112:16]
+  wire  _supported_T_326 = _supported_T_324 | _supported_T_325; // @[VAlu.scala 110:31]
+  wire  _supported_T_327 = io_in_bits_2_bits_op == 7'h2e; // @[VAlu.scala 113:16]
+  wire  _supported_T_328 = _supported_T_326 | _supported_T_327; // @[VAlu.scala 112:31]
+  wire  _supported_T_329 = io_in_bits_2_bits_op == 7'h30; // @[VAlu.scala 114:16]
+  wire  _supported_T_330 = _supported_T_328 | _supported_T_329; // @[VAlu.scala 113:32]
+  wire  _supported_T_331 = io_in_bits_2_bits_op == 7'h27; // @[VAlu.scala 115:16]
+  wire  _supported_T_332 = _supported_T_330 | _supported_T_331; // @[VAlu.scala 114:30]
+  wire  _supported_T_333 = io_in_bits_2_bits_op == 7'h28; // @[VAlu.scala 116:16]
+  wire  _supported_T_334 = _supported_T_332 | _supported_T_333; // @[VAlu.scala 115:29]
+  wire  _supported_T_335 = io_in_bits_2_bits_op == 7'h2b; // @[VAlu.scala 117:16]
+  wire  _supported_T_336 = _supported_T_334 | _supported_T_335; // @[VAlu.scala 116:30]
+  wire  _supported_T_337 = io_in_bits_2_bits_op == 7'h2c; // @[VAlu.scala 118:16]
+  wire  _supported_T_338 = _supported_T_336 | _supported_T_337; // @[VAlu.scala 117:30]
+  wire  _supported_T_339 = io_in_bits_2_bits_op == 7'h29; // @[VAlu.scala 119:16]
+  wire  _supported_T_340 = _supported_T_338 | _supported_T_339; // @[VAlu.scala 118:31]
+  wire  _supported_T_341 = io_in_bits_2_bits_op == 7'h2a; // @[VAlu.scala 120:16]
+  wire  _supported_T_342 = _supported_T_340 | _supported_T_341; // @[VAlu.scala 119:30]
+  wire  _supported_T_343 = io_in_bits_2_bits_op == 7'h2f; // @[VAlu.scala 121:16]
+  wire  _supported_T_344 = _supported_T_342 | _supported_T_343; // @[VAlu.scala 120:31]
+  wire  _supported_T_345 = io_in_bits_2_bits_op == 7'h3a; // @[VAlu.scala 123:16]
+  wire  _supported_T_346 = _supported_T_344 | _supported_T_345; // @[VAlu.scala 121:30]
+  wire  _supported_T_347 = io_in_bits_2_bits_op == 7'h3d; // @[VAlu.scala 124:16]
+  wire  _supported_T_348 = _supported_T_346 | _supported_T_347; // @[VAlu.scala 123:33]
+  wire  _supported_T_349 = io_in_bits_2_bits_op == 7'h3c; // @[VAlu.scala 125:16]
+  wire  _supported_T_350 = _supported_T_348 | _supported_T_349; // @[VAlu.scala 124:33]
+  wire  _supported_T_351 = io_in_bits_2_bits_op == 7'h3f; // @[VAlu.scala 126:16]
+  wire  _supported_T_352 = _supported_T_350 | _supported_T_351; // @[VAlu.scala 125:34]
+  wire  _supported_T_353 = io_in_bits_2_bits_op == 7'h40; // @[VAlu.scala 127:16]
+  wire  _supported_T_354 = _supported_T_352 | _supported_T_353; // @[VAlu.scala 126:34]
+  wire  _supported_T_355 = io_in_bits_2_bits_op == 7'h41; // @[VAlu.scala 128:16]
+  wire  _supported_T_356 = _supported_T_354 | _supported_T_355; // @[VAlu.scala 127:29]
+  wire  _supported_T_357 = io_in_bits_2_bits_op == 7'h42; // @[VAlu.scala 129:16]
+  wire  _supported_T_358 = _supported_T_356 | _supported_T_357; // @[VAlu.scala 128:29]
+  wire  _supported_T_359 = io_in_bits_2_bits_op == 7'h43; // @[VAlu.scala 130:16]
+  wire  _supported_T_360 = _supported_T_358 | _supported_T_359; // @[VAlu.scala 129:29]
+  wire  _supported_T_361 = io_in_bits_2_bits_op == 7'h44; // @[VAlu.scala 131:16]
+  wire  _supported_T_362 = _supported_T_360 | _supported_T_361; // @[VAlu.scala 130:32]
+  wire  _supported_T_363 = io_in_bits_2_bits_op == 7'h46; // @[VAlu.scala 133:16]
+  wire  _supported_T_364 = _supported_T_362 | _supported_T_363; // @[VAlu.scala 131:29]
+  wire  _supported_T_365 = io_in_bits_2_bits_op == 7'h47; // @[VAlu.scala 134:16]
+  wire  supported_2 = _supported_T_364 | _supported_T_365; // @[VAlu.scala 133:32]
+  wire  _T_63 = ~supported_2; // @[VAlu.scala 136:15]
+  wire  _T_76 = _supported_T_363 | _supported_T_365; // @[VAlu.scala 143:34]
+  wire [1:0] sparse_2 = io_in_bits_2_bits_sv_data[3:2]; // @[VAlu.scala 144:50]
+  wire  _supported_T_367 = io_in_bits_3_bits_op == 7'h35; // @[VAlu.scala 68:16]
+  wire  _supported_T_368 = io_in_bits_3_bits_op == 7'hf | _supported_T_367; // @[VAlu.scala 67:30]
+  wire  _supported_T_369 = io_in_bits_3_bits_op == 7'h6; // @[VAlu.scala 69:16]
+  wire  _supported_T_370 = _supported_T_368 | _supported_T_369; // @[VAlu.scala 68:29]
+  wire  _supported_T_371 = io_in_bits_3_bits_op == 7'h31; // @[VAlu.scala 70:16]
+  wire  _supported_T_372 = _supported_T_370 | _supported_T_371; // @[VAlu.scala 69:29]
+  wire  _supported_T_373 = io_in_bits_3_bits_op == 7'h33; // @[VAlu.scala 71:16]
+  wire  _supported_T_374 = _supported_T_372 | _supported_T_373; // @[VAlu.scala 70:30]
+  wire  _supported_T_375 = io_in_bits_3_bits_op == 7'h12; // @[VAlu.scala 72:16]
+  wire  _supported_T_376 = _supported_T_374 | _supported_T_375; // @[VAlu.scala 71:30]
+  wire  _supported_T_377 = io_in_bits_3_bits_op == 7'h1; // @[VAlu.scala 73:16]
+  wire  _supported_T_378 = _supported_T_376 | _supported_T_377; // @[VAlu.scala 72:30]
+  wire  _supported_T_379 = io_in_bits_3_bits_op == 7'h38; // @[VAlu.scala 74:16]
+  wire  _supported_T_380 = _supported_T_378 | _supported_T_379; // @[VAlu.scala 73:29]
+  wire  _supported_T_381 = io_in_bits_3_bits_op == 7'h39; // @[VAlu.scala 75:16]
+  wire  _supported_T_382 = _supported_T_380 | _supported_T_381; // @[VAlu.scala 74:30]
+  wire  _supported_T_383 = io_in_bits_3_bits_op == 7'h10; // @[VAlu.scala 76:16]
+  wire  _supported_T_384 = _supported_T_382 | _supported_T_383; // @[VAlu.scala 75:30]
+  wire  _supported_T_385 = io_in_bits_3_bits_op == 7'h11; // @[VAlu.scala 77:16]
+  wire  _supported_T_386 = _supported_T_384 | _supported_T_385; // @[VAlu.scala 76:29]
+  wire  _supported_T_387 = io_in_bits_3_bits_op == 7'h36; // @[VAlu.scala 78:16]
+  wire  _supported_T_388 = _supported_T_386 | _supported_T_387; // @[VAlu.scala 77:29]
+  wire  _supported_T_389 = io_in_bits_3_bits_op == 7'h37; // @[VAlu.scala 79:16]
+  wire  _supported_T_390 = _supported_T_388 | _supported_T_389; // @[VAlu.scala 78:30]
+  wire  _supported_T_391 = io_in_bits_3_bits_op == 7'h8; // @[VAlu.scala 80:16]
+  wire  _supported_T_392 = _supported_T_390 | _supported_T_391; // @[VAlu.scala 79:30]
+  wire  _supported_T_393 = io_in_bits_3_bits_op == 7'h7; // @[VAlu.scala 81:16]
+  wire  _supported_T_394 = _supported_T_392 | _supported_T_393; // @[VAlu.scala 80:30]
+  wire  _supported_T_395 = io_in_bits_3_bits_op == 7'h32; // @[VAlu.scala 82:16]
+  wire  _supported_T_396 = _supported_T_394 | _supported_T_395; // @[VAlu.scala 81:29]
+  wire  _supported_T_397 = io_in_bits_3_bits_op == 7'h34; // @[VAlu.scala 83:16]
+  wire  _supported_T_398 = _supported_T_396 | _supported_T_397; // @[VAlu.scala 82:30]
+  wire  _supported_T_399 = io_in_bits_3_bits_op == 7'h9; // @[VAlu.scala 85:16]
+  wire  _supported_T_400 = _supported_T_398 | _supported_T_399; // @[VAlu.scala 83:30]
+  wire  _supported_T_401 = io_in_bits_3_bits_op == 7'ha; // @[VAlu.scala 86:16]
+  wire  _supported_T_402 = _supported_T_400 | _supported_T_401; // @[VAlu.scala 85:28]
+  wire  _supported_T_403 = io_in_bits_3_bits_op == 7'hb; // @[VAlu.scala 87:16]
+  wire  _supported_T_404 = _supported_T_402 | _supported_T_403; // @[VAlu.scala 86:28]
+  wire  _supported_T_405 = io_in_bits_3_bits_op == 7'hc; // @[VAlu.scala 88:16]
+  wire  _supported_T_406 = _supported_T_404 | _supported_T_405; // @[VAlu.scala 87:28]
+  wire  _supported_T_407 = io_in_bits_3_bits_op == 7'hd; // @[VAlu.scala 89:16]
+  wire  _supported_T_408 = _supported_T_406 | _supported_T_407; // @[VAlu.scala 88:28]
+  wire  _supported_T_409 = io_in_bits_3_bits_op == 7'he; // @[VAlu.scala 90:16]
+  wire  _supported_T_410 = _supported_T_408 | _supported_T_409; // @[VAlu.scala 89:28]
+  wire  _supported_T_411 = io_in_bits_3_bits_op == 7'h13; // @[VAlu.scala 92:16]
+  wire  _supported_T_412 = _supported_T_410 | _supported_T_411; // @[VAlu.scala 90:28]
+  wire  _supported_T_413 = io_in_bits_3_bits_op == 7'h19; // @[VAlu.scala 93:16]
+  wire  _supported_T_414 = _supported_T_412 | _supported_T_413; // @[VAlu.scala 92:29]
+  wire  _supported_T_415 = io_in_bits_3_bits_op == 7'h1a; // @[VAlu.scala 94:16]
+  wire  _supported_T_416 = _supported_T_414 | _supported_T_415; // @[VAlu.scala 93:29]
+  wire  _supported_T_417 = io_in_bits_3_bits_op == 7'h1b; // @[VAlu.scala 95:16]
+  wire  _supported_T_418 = _supported_T_416 | _supported_T_417; // @[VAlu.scala 94:29]
+  wire  _supported_T_419 = io_in_bits_3_bits_op == 7'h1c; // @[VAlu.scala 96:16]
+  wire  _supported_T_420 = _supported_T_418 | _supported_T_419; // @[VAlu.scala 95:30]
+  wire  _supported_T_421 = io_in_bits_3_bits_op == 7'h1d; // @[VAlu.scala 97:16]
+  wire  _supported_T_422 = _supported_T_420 | _supported_T_421; // @[VAlu.scala 96:28]
+  wire  _supported_T_423 = io_in_bits_3_bits_op == 7'h1e; // @[VAlu.scala 98:16]
+  wire  _supported_T_424 = _supported_T_422 | _supported_T_423; // @[VAlu.scala 97:29]
+  wire  _supported_T_425 = io_in_bits_3_bits_op == 7'h21; // @[VAlu.scala 99:16]
+  wire  _supported_T_426 = _supported_T_424 | _supported_T_425; // @[VAlu.scala 98:29]
+  wire  _supported_T_427 = io_in_bits_3_bits_op == 7'h16; // @[VAlu.scala 100:16]
+  wire  _supported_T_428 = _supported_T_426 | _supported_T_427; // @[VAlu.scala 99:32]
+  wire  _supported_T_429 = io_in_bits_3_bits_op == 7'h14; // @[VAlu.scala 101:16]
+  wire  _supported_T_430 = _supported_T_428 | _supported_T_429; // @[VAlu.scala 100:29]
+  wire  _supported_T_431 = io_in_bits_3_bits_op == 7'h17; // @[VAlu.scala 102:16]
+  wire  _supported_T_432 = _supported_T_430 | _supported_T_431; // @[VAlu.scala 101:28]
+  wire  _supported_T_433 = io_in_bits_3_bits_op == 7'h18; // @[VAlu.scala 103:16]
+  wire  _supported_T_434 = _supported_T_432 | _supported_T_433; // @[VAlu.scala 102:29]
+  wire  _supported_T_435 = io_in_bits_3_bits_op == 7'h15; // @[VAlu.scala 104:16]
+  wire  _supported_T_436 = _supported_T_434 | _supported_T_435; // @[VAlu.scala 103:29]
+  wire  _supported_T_437 = io_in_bits_3_bits_op == 7'h22; // @[VAlu.scala 106:16]
+  wire  _supported_T_438 = _supported_T_436 | _supported_T_437; // @[VAlu.scala 104:29]
+  wire  _supported_T_439 = io_in_bits_3_bits_op == 7'h23; // @[VAlu.scala 107:16]
+  wire  _supported_T_440 = _supported_T_438 | _supported_T_439; // @[VAlu.scala 106:29]
+  wire  _supported_T_441 = io_in_bits_3_bits_op == 7'h24; // @[VAlu.scala 108:16]
+  wire  _supported_T_442 = _supported_T_440 | _supported_T_441; // @[VAlu.scala 107:29]
+  wire  _supported_T_443 = io_in_bits_3_bits_op == 7'h25; // @[VAlu.scala 109:16]
+  wire  _supported_T_444 = _supported_T_442 | _supported_T_443; // @[VAlu.scala 108:29]
+  wire  _supported_T_445 = io_in_bits_3_bits_op == 7'h26; // @[VAlu.scala 110:16]
+  wire  _supported_T_446 = _supported_T_444 | _supported_T_445; // @[VAlu.scala 109:31]
+  wire  _supported_T_447 = io_in_bits_3_bits_op == 7'h2d; // @[VAlu.scala 112:16]
+  wire  _supported_T_448 = _supported_T_446 | _supported_T_447; // @[VAlu.scala 110:31]
+  wire  _supported_T_449 = io_in_bits_3_bits_op == 7'h2e; // @[VAlu.scala 113:16]
+  wire  _supported_T_450 = _supported_T_448 | _supported_T_449; // @[VAlu.scala 112:31]
+  wire  _supported_T_451 = io_in_bits_3_bits_op == 7'h30; // @[VAlu.scala 114:16]
+  wire  _supported_T_452 = _supported_T_450 | _supported_T_451; // @[VAlu.scala 113:32]
+  wire  _supported_T_453 = io_in_bits_3_bits_op == 7'h27; // @[VAlu.scala 115:16]
+  wire  _supported_T_454 = _supported_T_452 | _supported_T_453; // @[VAlu.scala 114:30]
+  wire  _supported_T_455 = io_in_bits_3_bits_op == 7'h28; // @[VAlu.scala 116:16]
+  wire  _supported_T_456 = _supported_T_454 | _supported_T_455; // @[VAlu.scala 115:29]
+  wire  _supported_T_457 = io_in_bits_3_bits_op == 7'h2b; // @[VAlu.scala 117:16]
+  wire  _supported_T_458 = _supported_T_456 | _supported_T_457; // @[VAlu.scala 116:30]
+  wire  _supported_T_459 = io_in_bits_3_bits_op == 7'h2c; // @[VAlu.scala 118:16]
+  wire  _supported_T_460 = _supported_T_458 | _supported_T_459; // @[VAlu.scala 117:30]
+  wire  _supported_T_461 = io_in_bits_3_bits_op == 7'h29; // @[VAlu.scala 119:16]
+  wire  _supported_T_462 = _supported_T_460 | _supported_T_461; // @[VAlu.scala 118:31]
+  wire  _supported_T_463 = io_in_bits_3_bits_op == 7'h2a; // @[VAlu.scala 120:16]
+  wire  _supported_T_464 = _supported_T_462 | _supported_T_463; // @[VAlu.scala 119:30]
+  wire  _supported_T_465 = io_in_bits_3_bits_op == 7'h2f; // @[VAlu.scala 121:16]
+  wire  _supported_T_466 = _supported_T_464 | _supported_T_465; // @[VAlu.scala 120:31]
+  wire  _supported_T_467 = io_in_bits_3_bits_op == 7'h3a; // @[VAlu.scala 123:16]
+  wire  _supported_T_468 = _supported_T_466 | _supported_T_467; // @[VAlu.scala 121:30]
+  wire  _supported_T_469 = io_in_bits_3_bits_op == 7'h3d; // @[VAlu.scala 124:16]
+  wire  _supported_T_470 = _supported_T_468 | _supported_T_469; // @[VAlu.scala 123:33]
+  wire  _supported_T_471 = io_in_bits_3_bits_op == 7'h3c; // @[VAlu.scala 125:16]
+  wire  _supported_T_472 = _supported_T_470 | _supported_T_471; // @[VAlu.scala 124:33]
+  wire  _supported_T_473 = io_in_bits_3_bits_op == 7'h3f; // @[VAlu.scala 126:16]
+  wire  _supported_T_474 = _supported_T_472 | _supported_T_473; // @[VAlu.scala 125:34]
+  wire  _supported_T_475 = io_in_bits_3_bits_op == 7'h40; // @[VAlu.scala 127:16]
+  wire  _supported_T_476 = _supported_T_474 | _supported_T_475; // @[VAlu.scala 126:34]
+  wire  _supported_T_477 = io_in_bits_3_bits_op == 7'h41; // @[VAlu.scala 128:16]
+  wire  _supported_T_478 = _supported_T_476 | _supported_T_477; // @[VAlu.scala 127:29]
+  wire  _supported_T_479 = io_in_bits_3_bits_op == 7'h42; // @[VAlu.scala 129:16]
+  wire  _supported_T_480 = _supported_T_478 | _supported_T_479; // @[VAlu.scala 128:29]
+  wire  _supported_T_481 = io_in_bits_3_bits_op == 7'h43; // @[VAlu.scala 130:16]
+  wire  _supported_T_482 = _supported_T_480 | _supported_T_481; // @[VAlu.scala 129:29]
+  wire  _supported_T_483 = io_in_bits_3_bits_op == 7'h44; // @[VAlu.scala 131:16]
+  wire  _supported_T_484 = _supported_T_482 | _supported_T_483; // @[VAlu.scala 130:32]
+  wire  _supported_T_485 = io_in_bits_3_bits_op == 7'h46; // @[VAlu.scala 133:16]
+  wire  _supported_T_486 = _supported_T_484 | _supported_T_485; // @[VAlu.scala 131:29]
+  wire  _supported_T_487 = io_in_bits_3_bits_op == 7'h47; // @[VAlu.scala 134:16]
+  wire  supported_3 = _supported_T_486 | _supported_T_487; // @[VAlu.scala 133:32]
+  wire  _T_94 = ~supported_3; // @[VAlu.scala 136:15]
+  wire  _T_107 = _supported_T_485 | _supported_T_487; // @[VAlu.scala 143:34]
+  wire [1:0] sparse_3 = io_in_bits_3_bits_sv_data[3:2]; // @[VAlu.scala 144:50]
   wire [3:0] _q0ready_tag_T_1 = q0_io_out_bits_vs_tag >> q0_io_out_bits_vs_addr[1:0]; // @[VCommon.scala 119:20]
   wire  q0ready_tag = _q0ready_tag_T_1[0]; // @[VCommon.scala 119:20]
   wire [6:0] q0ready_idx = {q0ready_tag,q0_io_out_bits_vs_addr}; // @[Cat.scala 31:58]
@@ -73534,13 +63976,13 @@
   wire [6:0] q0ready_idx_1 = {q0ready_tag_1,q0_io_out_bits_vt_addr}; // @[Cat.scala 31:58]
   wire [127:0] _q0ready_T_6 = io_vrfsb >> q0ready_idx_1; // @[VCommon.scala 122:21]
   wire  _q0ready_T_9 = ~q0_io_out_bits_vt_valid | ~_q0ready_T_6[0]; // @[VCommon.scala 122:15]
-  wire  _q0ready_T_10 = _q0ready_T_4 & _q0ready_T_9; // @[VAlu.scala 270:62]
+  wire  _q0ready_T_10 = _q0ready_T_4 & _q0ready_T_9; // @[VAlu.scala 250:62]
   wire [3:0] _q0ready_tag_T_5 = q0_io_out_bits_vu_tag >> q0_io_out_bits_vu_addr[1:0]; // @[VCommon.scala 119:20]
   wire  q0ready_tag_2 = _q0ready_tag_T_5[0]; // @[VCommon.scala 119:20]
   wire [6:0] q0ready_idx_2 = {q0ready_tag_2,q0_io_out_bits_vu_addr}; // @[Cat.scala 31:58]
   wire [127:0] _q0ready_T_12 = io_vrfsb >> q0ready_idx_2; // @[VCommon.scala 122:21]
   wire  _q0ready_T_15 = ~q0_io_out_bits_vu_valid | ~_q0ready_T_12[0]; // @[VCommon.scala 122:15]
-  wire  q0ready = _q0ready_T_10 & _q0ready_T_15; // @[VAlu.scala 271:62]
+  wire  q0ready = _q0ready_T_10 & _q0ready_T_15; // @[VAlu.scala 251:62]
   wire [3:0] _q1ready_tag_T_1 = q1_io_out_bits_vs_tag >> q1_io_out_bits_vs_addr[1:0]; // @[VCommon.scala 119:20]
   wire  q1ready_tag = _q1ready_tag_T_1[0]; // @[VCommon.scala 119:20]
   wire [6:0] q1ready_idx = {q1ready_tag,q1_io_out_bits_vs_addr}; // @[Cat.scala 31:58]
@@ -73551,33 +63993,33 @@
   wire [6:0] q1ready_idx_1 = {q1ready_tag_1,q1_io_out_bits_vt_addr}; // @[Cat.scala 31:58]
   wire [127:0] _q1ready_T_6 = io_vrfsb >> q1ready_idx_1; // @[VCommon.scala 122:21]
   wire  _q1ready_T_9 = ~q1_io_out_bits_vt_valid | ~_q1ready_T_6[0]; // @[VCommon.scala 122:15]
-  wire  _q1ready_T_10 = _q1ready_T_4 & _q1ready_T_9; // @[VAlu.scala 274:62]
+  wire  _q1ready_T_10 = _q1ready_T_4 & _q1ready_T_9; // @[VAlu.scala 254:62]
   wire [3:0] _q1ready_tag_T_5 = q1_io_out_bits_vu_tag >> q1_io_out_bits_vu_addr[1:0]; // @[VCommon.scala 119:20]
   wire  q1ready_tag_2 = _q1ready_tag_T_5[0]; // @[VCommon.scala 119:20]
   wire [6:0] q1ready_idx_2 = {q1ready_tag_2,q1_io_out_bits_vu_addr}; // @[Cat.scala 31:58]
   wire [127:0] _q1ready_T_12 = io_vrfsb >> q1ready_idx_2; // @[VCommon.scala 122:21]
   wire  _q1ready_T_15 = ~q1_io_out_bits_vu_valid | ~_q1ready_T_12[0]; // @[VCommon.scala 122:15]
-  wire  q1ready = _q1ready_T_10 & _q1ready_T_15; // @[VAlu.scala 275:62]
-  reg  alureg; // @[VAlu.scala 283:23]
-  wire  _alusel_1_T_2 = ~alureg; // @[VAlu.scala 288:72]
-  wire  alusel_1 = io_in_bits_0_valid & ~io_in_bits_0_bits_cmdsync ? ~alureg : alureg; // @[VAlu.scala 288:19]
-  wire  _alusel_2_T_2 = ~alusel_1; // @[VAlu.scala 289:72]
-  wire  alusel_2 = io_in_bits_1_valid & ~io_in_bits_1_bits_cmdsync ? ~alusel_1 : alusel_1; // @[VAlu.scala 289:19]
-  wire  _alusel_3_T_2 = ~alusel_2; // @[VAlu.scala 290:72]
-  wire  alusel_3 = io_in_bits_2_valid & ~io_in_bits_2_bits_cmdsync ? ~alusel_2 : alusel_2; // @[VAlu.scala 290:19]
-  wire  _alusel_4_T_2 = ~alusel_3; // @[VAlu.scala 291:72]
-  wire  _GEN_1 = _T & io_in_bits_0_valid; // @[VAlu.scala 157:17]
-  wire  _GEN_4 = _GEN_1 & _T_3; // @[VAlu.scala 159:15]
-  wire  _GEN_15 = _GEN_1 & _T_14 & _T_3; // @[VAlu.scala 165:17]
-  wire  _GEN_41 = _T & io_in_bits_1_valid; // @[VAlu.scala 157:17]
-  wire  _GEN_44 = _GEN_41 & _T_3; // @[VAlu.scala 159:15]
-  wire  _GEN_55 = _GEN_41 & _T_45 & _T_3; // @[VAlu.scala 165:17]
-  wire  _GEN_81 = _T & io_in_bits_2_valid; // @[VAlu.scala 157:17]
-  wire  _GEN_84 = _GEN_81 & _T_3; // @[VAlu.scala 159:15]
-  wire  _GEN_95 = _GEN_81 & _T_76 & _T_3; // @[VAlu.scala 165:17]
-  wire  _GEN_121 = _T & io_in_bits_3_valid; // @[VAlu.scala 157:17]
-  wire  _GEN_124 = _GEN_121 & _T_3; // @[VAlu.scala 159:15]
-  wire  _GEN_135 = _GEN_121 & _T_107 & _T_3; // @[VAlu.scala 165:17]
+  wire  q1ready = _q1ready_T_10 & _q1ready_T_15; // @[VAlu.scala 255:62]
+  reg  alureg; // @[VAlu.scala 263:23]
+  wire  _alusel_1_T_2 = ~alureg; // @[VAlu.scala 268:72]
+  wire  alusel_1 = io_in_bits_0_valid & ~io_in_bits_0_bits_cmdsync ? ~alureg : alureg; // @[VAlu.scala 268:19]
+  wire  _alusel_2_T_2 = ~alusel_1; // @[VAlu.scala 269:72]
+  wire  alusel_2 = io_in_bits_1_valid & ~io_in_bits_1_bits_cmdsync ? ~alusel_1 : alusel_1; // @[VAlu.scala 269:19]
+  wire  _alusel_3_T_2 = ~alusel_2; // @[VAlu.scala 270:72]
+  wire  alusel_3 = io_in_bits_2_valid & ~io_in_bits_2_bits_cmdsync ? ~alusel_2 : alusel_2; // @[VAlu.scala 270:19]
+  wire  _alusel_4_T_2 = ~alusel_3; // @[VAlu.scala 271:72]
+  wire  _GEN_1 = _T & io_in_bits_0_valid; // @[VAlu.scala 137:17]
+  wire  _GEN_4 = _GEN_1 & _T_3; // @[VAlu.scala 139:15]
+  wire  _GEN_15 = _GEN_1 & _T_14 & _T_3; // @[VAlu.scala 145:17]
+  wire  _GEN_41 = _T & io_in_bits_1_valid; // @[VAlu.scala 137:17]
+  wire  _GEN_44 = _GEN_41 & _T_3; // @[VAlu.scala 139:15]
+  wire  _GEN_55 = _GEN_41 & _T_45 & _T_3; // @[VAlu.scala 145:17]
+  wire  _GEN_81 = _T & io_in_bits_2_valid; // @[VAlu.scala 137:17]
+  wire  _GEN_84 = _GEN_81 & _T_3; // @[VAlu.scala 139:15]
+  wire  _GEN_95 = _GEN_81 & _T_76 & _T_3; // @[VAlu.scala 145:17]
+  wire  _GEN_121 = _T & io_in_bits_3_valid; // @[VAlu.scala 137:17]
+  wire  _GEN_124 = _GEN_121 & _T_3; // @[VAlu.scala 139:15]
+  wire  _GEN_135 = _GEN_121 & _T_107 & _T_3; // @[VAlu.scala 145:17]
   VCmdq q0 ( // @[VCmdq.scala 14:11]
     .clock(q0_clock),
     .reset(q0_reset),
@@ -73826,7 +64268,7 @@
     .io_out_bits_cmdsync(q1_io_out_bits_cmdsync),
     .io_active(q1_io_active)
   );
-  VAluInt alu0 ( // @[VAlu.scala 341:20]
+  VAluInt alu0 ( // @[VAlu.scala 321:20]
     .clock(alu0_clock),
     .reset(alu0_reset),
     .io_in_valid(alu0_io_in_valid),
@@ -73853,7 +64295,7 @@
     .io_whint_1_valid(alu0_io_whint_1_valid),
     .io_whint_1_addr(alu0_io_whint_1_addr)
   );
-  VAluInt_1 alu1 ( // @[VAlu.scala 375:20]
+  VAluInt_1 alu1 ( // @[VAlu.scala 355:20]
     .clock(alu1_clock),
     .reset(alu1_reset),
     .io_in_valid(alu1_io_in_valid),
@@ -73880,285 +64322,285 @@
     .io_whint_1_valid(alu1_io_whint_1_valid),
     .io_whint_1_addr(alu1_io_whint_1_addr)
   );
-  assign io_in_ready = q0_io_in_ready & q1_io_in_ready; // @[VAlu.scala 265:33]
-  assign io_active = q0_io_active | q1_io_active; // @[VAlu.scala 409:29]
-  assign io_read_0_valid = q0_io_out_bits_vs_valid; // @[VAlu.scala 304:20]
-  assign io_read_0_addr = q0_io_out_bits_vs_addr; // @[VAlu.scala 311:19]
-  assign io_read_1_valid = q0_io_out_bits_vt_valid; // @[VAlu.scala 305:20]
-  assign io_read_1_addr = q0_io_out_bits_vt_addr; // @[VAlu.scala 312:19]
-  assign io_read_2_valid = q0_io_out_bits_vu_valid; // @[VAlu.scala 306:20]
-  assign io_read_2_addr = q0_io_out_bits_vu_addr; // @[VAlu.scala 313:19]
-  assign io_read_3_valid = q1_io_out_bits_vs_valid; // @[VAlu.scala 307:20]
-  assign io_read_3_addr = q1_io_out_bits_vs_addr; // @[VAlu.scala 314:19]
-  assign io_read_4_valid = q1_io_out_bits_vt_valid; // @[VAlu.scala 308:20]
-  assign io_read_4_addr = q1_io_out_bits_vt_addr; // @[VAlu.scala 315:19]
-  assign io_read_5_valid = q1_io_out_bits_vu_valid; // @[VAlu.scala 309:20]
-  assign io_read_5_addr = q1_io_out_bits_vu_addr; // @[VAlu.scala 316:19]
-  assign io_write_0_valid = alu0_io_write_0_valid; // @[VAlu.scala 359:21]
-  assign io_write_0_addr = alu0_io_write_0_addr; // @[VAlu.scala 360:20]
-  assign io_write_0_data = alu0_io_write_0_data; // @[VAlu.scala 361:20]
-  assign io_write_1_valid = alu0_io_write_1_valid; // @[VAlu.scala 363:21]
-  assign io_write_1_addr = alu0_io_write_1_addr; // @[VAlu.scala 364:20]
-  assign io_write_1_data = alu0_io_write_1_data; // @[VAlu.scala 365:20]
-  assign io_write_2_valid = alu1_io_write_0_valid; // @[VAlu.scala 393:21]
-  assign io_write_2_addr = alu1_io_write_0_addr; // @[VAlu.scala 394:20]
-  assign io_write_2_data = alu1_io_write_0_data; // @[VAlu.scala 395:20]
-  assign io_write_3_valid = alu1_io_write_1_valid; // @[VAlu.scala 397:21]
-  assign io_write_3_addr = alu1_io_write_1_addr; // @[VAlu.scala 398:20]
-  assign io_write_3_data = alu1_io_write_1_data; // @[VAlu.scala 399:20]
-  assign io_whint_0_valid = alu0_io_whint_0_valid; // @[VAlu.scala 367:21]
-  assign io_whint_0_addr = alu0_io_whint_0_addr; // @[VAlu.scala 368:20]
-  assign io_whint_1_valid = alu0_io_whint_1_valid; // @[VAlu.scala 370:21]
-  assign io_whint_1_addr = alu0_io_whint_1_addr; // @[VAlu.scala 371:20]
-  assign io_whint_2_valid = alu1_io_whint_0_valid; // @[VAlu.scala 401:21]
-  assign io_whint_2_addr = alu1_io_whint_0_addr; // @[VAlu.scala 402:20]
-  assign io_whint_3_valid = alu1_io_whint_1_valid; // @[VAlu.scala 404:21]
-  assign io_whint_3_addr = alu1_io_whint_1_addr; // @[VAlu.scala 405:20]
-  assign io_scalar_0_valid = q0_io_out_bits_sv_valid; // @[VAlu.scala 325:22]
-  assign io_scalar_0_data = q0_io_out_bits_sv_data; // @[VAlu.scala 328:21]
-  assign io_scalar_1_valid = q1_io_out_bits_sv_valid; // @[VAlu.scala 326:22]
-  assign io_scalar_1_data = q1_io_out_bits_sv_data; // @[VAlu.scala 329:21]
+  assign io_in_ready = q0_io_in_ready & q1_io_in_ready; // @[VAlu.scala 245:33]
+  assign io_active = q0_io_active | q1_io_active; // @[VAlu.scala 389:29]
+  assign io_read_0_valid = q0_io_out_bits_vs_valid; // @[VAlu.scala 284:20]
+  assign io_read_0_addr = q0_io_out_bits_vs_addr; // @[VAlu.scala 291:19]
+  assign io_read_1_valid = q0_io_out_bits_vt_valid; // @[VAlu.scala 285:20]
+  assign io_read_1_addr = q0_io_out_bits_vt_addr; // @[VAlu.scala 292:19]
+  assign io_read_2_valid = q0_io_out_bits_vu_valid; // @[VAlu.scala 286:20]
+  assign io_read_2_addr = q0_io_out_bits_vu_addr; // @[VAlu.scala 293:19]
+  assign io_read_3_valid = q1_io_out_bits_vs_valid; // @[VAlu.scala 287:20]
+  assign io_read_3_addr = q1_io_out_bits_vs_addr; // @[VAlu.scala 294:19]
+  assign io_read_4_valid = q1_io_out_bits_vt_valid; // @[VAlu.scala 288:20]
+  assign io_read_4_addr = q1_io_out_bits_vt_addr; // @[VAlu.scala 295:19]
+  assign io_read_5_valid = q1_io_out_bits_vu_valid; // @[VAlu.scala 289:20]
+  assign io_read_5_addr = q1_io_out_bits_vu_addr; // @[VAlu.scala 296:19]
+  assign io_write_0_valid = alu0_io_write_0_valid; // @[VAlu.scala 339:21]
+  assign io_write_0_addr = alu0_io_write_0_addr; // @[VAlu.scala 340:20]
+  assign io_write_0_data = alu0_io_write_0_data; // @[VAlu.scala 341:20]
+  assign io_write_1_valid = alu0_io_write_1_valid; // @[VAlu.scala 343:21]
+  assign io_write_1_addr = alu0_io_write_1_addr; // @[VAlu.scala 344:20]
+  assign io_write_1_data = alu0_io_write_1_data; // @[VAlu.scala 345:20]
+  assign io_write_2_valid = alu1_io_write_0_valid; // @[VAlu.scala 373:21]
+  assign io_write_2_addr = alu1_io_write_0_addr; // @[VAlu.scala 374:20]
+  assign io_write_2_data = alu1_io_write_0_data; // @[VAlu.scala 375:20]
+  assign io_write_3_valid = alu1_io_write_1_valid; // @[VAlu.scala 377:21]
+  assign io_write_3_addr = alu1_io_write_1_addr; // @[VAlu.scala 378:20]
+  assign io_write_3_data = alu1_io_write_1_data; // @[VAlu.scala 379:20]
+  assign io_whint_0_valid = alu0_io_whint_0_valid; // @[VAlu.scala 347:21]
+  assign io_whint_0_addr = alu0_io_whint_0_addr; // @[VAlu.scala 348:20]
+  assign io_whint_1_valid = alu0_io_whint_1_valid; // @[VAlu.scala 350:21]
+  assign io_whint_1_addr = alu0_io_whint_1_addr; // @[VAlu.scala 351:20]
+  assign io_whint_2_valid = alu1_io_whint_0_valid; // @[VAlu.scala 381:21]
+  assign io_whint_2_addr = alu1_io_whint_0_addr; // @[VAlu.scala 382:20]
+  assign io_whint_3_valid = alu1_io_whint_1_valid; // @[VAlu.scala 384:21]
+  assign io_whint_3_addr = alu1_io_whint_1_addr; // @[VAlu.scala 385:20]
+  assign io_scalar_0_valid = q0_io_out_bits_sv_valid; // @[VAlu.scala 305:22]
+  assign io_scalar_0_data = q0_io_out_bits_sv_data; // @[VAlu.scala 308:21]
+  assign io_scalar_1_valid = q1_io_out_bits_sv_valid; // @[VAlu.scala 306:22]
+  assign io_scalar_1_data = q1_io_out_bits_sv_data; // @[VAlu.scala 309:21]
   assign q0_clock = clock;
   assign q0_reset = reset;
-  assign q0_io_in_valid = io_in_valid & q1_io_in_ready; // @[VAlu.scala 263:33]
-  assign q0_io_in_bits_0_valid = io_in_bits_0_valid & (_alusel_1_T_2 | io_in_bits_0_bits_cmdsync); // @[VAlu.scala 298:51]
-  assign q0_io_in_bits_0_bits_op = io_in_bits_0_bits_op; // @[VAlu.scala 267:17]
-  assign q0_io_in_bits_0_bits_f2 = io_in_bits_0_bits_f2; // @[VAlu.scala 267:17]
-  assign q0_io_in_bits_0_bits_sz = io_in_bits_0_bits_sz; // @[VAlu.scala 267:17]
-  assign q0_io_in_bits_0_bits_m = io_in_bits_0_bits_m; // @[VAlu.scala 267:17]
-  assign q0_io_in_bits_0_bits_vd_addr = io_in_bits_0_bits_vd_addr; // @[VAlu.scala 267:17]
-  assign q0_io_in_bits_0_bits_ve_addr = io_in_bits_0_bits_ve_addr; // @[VAlu.scala 267:17]
-  assign q0_io_in_bits_0_bits_vs_valid = io_in_bits_0_bits_vs_valid; // @[VAlu.scala 267:17]
-  assign q0_io_in_bits_0_bits_vs_addr = io_in_bits_0_bits_vs_addr; // @[VAlu.scala 267:17]
-  assign q0_io_in_bits_0_bits_vs_tag = io_in_bits_0_bits_vs_tag; // @[VAlu.scala 267:17]
-  assign q0_io_in_bits_0_bits_vt_valid = io_in_bits_0_bits_vt_valid; // @[VAlu.scala 267:17]
-  assign q0_io_in_bits_0_bits_vt_addr = io_in_bits_0_bits_vt_addr; // @[VAlu.scala 267:17]
-  assign q0_io_in_bits_0_bits_vt_tag = io_in_bits_0_bits_vt_tag; // @[VAlu.scala 267:17]
-  assign q0_io_in_bits_0_bits_vu_valid = io_in_bits_0_bits_vu_valid; // @[VAlu.scala 267:17]
-  assign q0_io_in_bits_0_bits_vu_addr = io_in_bits_0_bits_vu_addr; // @[VAlu.scala 267:17]
-  assign q0_io_in_bits_0_bits_vu_tag = io_in_bits_0_bits_vu_tag; // @[VAlu.scala 267:17]
-  assign q0_io_in_bits_0_bits_sv_valid = io_in_bits_0_bits_sv_valid; // @[VAlu.scala 267:17]
-  assign q0_io_in_bits_0_bits_sv_data = io_in_bits_0_bits_sv_data; // @[VAlu.scala 267:17]
-  assign q0_io_in_bits_0_bits_cmdsync = io_in_bits_0_bits_cmdsync; // @[VAlu.scala 267:17]
-  assign q0_io_in_bits_1_valid = io_in_bits_1_valid & (_alusel_2_T_2 | io_in_bits_1_bits_cmdsync); // @[VAlu.scala 298:51]
-  assign q0_io_in_bits_1_bits_op = io_in_bits_1_bits_op; // @[VAlu.scala 267:17]
-  assign q0_io_in_bits_1_bits_f2 = io_in_bits_1_bits_f2; // @[VAlu.scala 267:17]
-  assign q0_io_in_bits_1_bits_sz = io_in_bits_1_bits_sz; // @[VAlu.scala 267:17]
-  assign q0_io_in_bits_1_bits_m = io_in_bits_1_bits_m; // @[VAlu.scala 267:17]
-  assign q0_io_in_bits_1_bits_vd_addr = io_in_bits_1_bits_vd_addr; // @[VAlu.scala 267:17]
-  assign q0_io_in_bits_1_bits_ve_addr = io_in_bits_1_bits_ve_addr; // @[VAlu.scala 267:17]
-  assign q0_io_in_bits_1_bits_vs_valid = io_in_bits_1_bits_vs_valid; // @[VAlu.scala 267:17]
-  assign q0_io_in_bits_1_bits_vs_addr = io_in_bits_1_bits_vs_addr; // @[VAlu.scala 267:17]
-  assign q0_io_in_bits_1_bits_vs_tag = io_in_bits_1_bits_vs_tag; // @[VAlu.scala 267:17]
-  assign q0_io_in_bits_1_bits_vt_valid = io_in_bits_1_bits_vt_valid; // @[VAlu.scala 267:17]
-  assign q0_io_in_bits_1_bits_vt_addr = io_in_bits_1_bits_vt_addr; // @[VAlu.scala 267:17]
-  assign q0_io_in_bits_1_bits_vt_tag = io_in_bits_1_bits_vt_tag; // @[VAlu.scala 267:17]
-  assign q0_io_in_bits_1_bits_vu_valid = io_in_bits_1_bits_vu_valid; // @[VAlu.scala 267:17]
-  assign q0_io_in_bits_1_bits_vu_addr = io_in_bits_1_bits_vu_addr; // @[VAlu.scala 267:17]
-  assign q0_io_in_bits_1_bits_vu_tag = io_in_bits_1_bits_vu_tag; // @[VAlu.scala 267:17]
-  assign q0_io_in_bits_1_bits_sv_valid = io_in_bits_1_bits_sv_valid; // @[VAlu.scala 267:17]
-  assign q0_io_in_bits_1_bits_sv_data = io_in_bits_1_bits_sv_data; // @[VAlu.scala 267:17]
-  assign q0_io_in_bits_1_bits_cmdsync = io_in_bits_1_bits_cmdsync; // @[VAlu.scala 267:17]
-  assign q0_io_in_bits_2_valid = io_in_bits_2_valid & (_alusel_3_T_2 | io_in_bits_2_bits_cmdsync); // @[VAlu.scala 298:51]
-  assign q0_io_in_bits_2_bits_op = io_in_bits_2_bits_op; // @[VAlu.scala 267:17]
-  assign q0_io_in_bits_2_bits_f2 = io_in_bits_2_bits_f2; // @[VAlu.scala 267:17]
-  assign q0_io_in_bits_2_bits_sz = io_in_bits_2_bits_sz; // @[VAlu.scala 267:17]
-  assign q0_io_in_bits_2_bits_m = io_in_bits_2_bits_m; // @[VAlu.scala 267:17]
-  assign q0_io_in_bits_2_bits_vd_addr = io_in_bits_2_bits_vd_addr; // @[VAlu.scala 267:17]
-  assign q0_io_in_bits_2_bits_ve_addr = io_in_bits_2_bits_ve_addr; // @[VAlu.scala 267:17]
-  assign q0_io_in_bits_2_bits_vs_valid = io_in_bits_2_bits_vs_valid; // @[VAlu.scala 267:17]
-  assign q0_io_in_bits_2_bits_vs_addr = io_in_bits_2_bits_vs_addr; // @[VAlu.scala 267:17]
-  assign q0_io_in_bits_2_bits_vs_tag = io_in_bits_2_bits_vs_tag; // @[VAlu.scala 267:17]
-  assign q0_io_in_bits_2_bits_vt_valid = io_in_bits_2_bits_vt_valid; // @[VAlu.scala 267:17]
-  assign q0_io_in_bits_2_bits_vt_addr = io_in_bits_2_bits_vt_addr; // @[VAlu.scala 267:17]
-  assign q0_io_in_bits_2_bits_vt_tag = io_in_bits_2_bits_vt_tag; // @[VAlu.scala 267:17]
-  assign q0_io_in_bits_2_bits_vu_valid = io_in_bits_2_bits_vu_valid; // @[VAlu.scala 267:17]
-  assign q0_io_in_bits_2_bits_vu_addr = io_in_bits_2_bits_vu_addr; // @[VAlu.scala 267:17]
-  assign q0_io_in_bits_2_bits_vu_tag = io_in_bits_2_bits_vu_tag; // @[VAlu.scala 267:17]
-  assign q0_io_in_bits_2_bits_sv_valid = io_in_bits_2_bits_sv_valid; // @[VAlu.scala 267:17]
-  assign q0_io_in_bits_2_bits_sv_data = io_in_bits_2_bits_sv_data; // @[VAlu.scala 267:17]
-  assign q0_io_in_bits_2_bits_cmdsync = io_in_bits_2_bits_cmdsync; // @[VAlu.scala 267:17]
-  assign q0_io_in_bits_3_valid = io_in_bits_3_valid & (_alusel_4_T_2 | io_in_bits_3_bits_cmdsync); // @[VAlu.scala 298:51]
-  assign q0_io_in_bits_3_bits_op = io_in_bits_3_bits_op; // @[VAlu.scala 267:17]
-  assign q0_io_in_bits_3_bits_f2 = io_in_bits_3_bits_f2; // @[VAlu.scala 267:17]
-  assign q0_io_in_bits_3_bits_sz = io_in_bits_3_bits_sz; // @[VAlu.scala 267:17]
-  assign q0_io_in_bits_3_bits_m = io_in_bits_3_bits_m; // @[VAlu.scala 267:17]
-  assign q0_io_in_bits_3_bits_vd_addr = io_in_bits_3_bits_vd_addr; // @[VAlu.scala 267:17]
-  assign q0_io_in_bits_3_bits_ve_addr = io_in_bits_3_bits_ve_addr; // @[VAlu.scala 267:17]
-  assign q0_io_in_bits_3_bits_vs_valid = io_in_bits_3_bits_vs_valid; // @[VAlu.scala 267:17]
-  assign q0_io_in_bits_3_bits_vs_addr = io_in_bits_3_bits_vs_addr; // @[VAlu.scala 267:17]
-  assign q0_io_in_bits_3_bits_vs_tag = io_in_bits_3_bits_vs_tag; // @[VAlu.scala 267:17]
-  assign q0_io_in_bits_3_bits_vt_valid = io_in_bits_3_bits_vt_valid; // @[VAlu.scala 267:17]
-  assign q0_io_in_bits_3_bits_vt_addr = io_in_bits_3_bits_vt_addr; // @[VAlu.scala 267:17]
-  assign q0_io_in_bits_3_bits_vt_tag = io_in_bits_3_bits_vt_tag; // @[VAlu.scala 267:17]
-  assign q0_io_in_bits_3_bits_vu_valid = io_in_bits_3_bits_vu_valid; // @[VAlu.scala 267:17]
-  assign q0_io_in_bits_3_bits_vu_addr = io_in_bits_3_bits_vu_addr; // @[VAlu.scala 267:17]
-  assign q0_io_in_bits_3_bits_vu_tag = io_in_bits_3_bits_vu_tag; // @[VAlu.scala 267:17]
-  assign q0_io_in_bits_3_bits_sv_valid = io_in_bits_3_bits_sv_valid; // @[VAlu.scala 267:17]
-  assign q0_io_in_bits_3_bits_sv_data = io_in_bits_3_bits_sv_data; // @[VAlu.scala 267:17]
-  assign q0_io_in_bits_3_bits_cmdsync = io_in_bits_3_bits_cmdsync; // @[VAlu.scala 267:17]
-  assign q0_io_out_ready = q0ready & (~q0_io_out_bits_cmdsync | q1_io_out_valid & q1ready & q1_io_out_bits_cmdsync); // @[VAlu.scala 278:30]
+  assign q0_io_in_valid = io_in_valid & q1_io_in_ready; // @[VAlu.scala 243:33]
+  assign q0_io_in_bits_0_valid = io_in_bits_0_valid & (_alusel_1_T_2 | io_in_bits_0_bits_cmdsync); // @[VAlu.scala 278:51]
+  assign q0_io_in_bits_0_bits_op = io_in_bits_0_bits_op; // @[VAlu.scala 247:17]
+  assign q0_io_in_bits_0_bits_f2 = io_in_bits_0_bits_f2; // @[VAlu.scala 247:17]
+  assign q0_io_in_bits_0_bits_sz = io_in_bits_0_bits_sz; // @[VAlu.scala 247:17]
+  assign q0_io_in_bits_0_bits_m = io_in_bits_0_bits_m; // @[VAlu.scala 247:17]
+  assign q0_io_in_bits_0_bits_vd_addr = io_in_bits_0_bits_vd_addr; // @[VAlu.scala 247:17]
+  assign q0_io_in_bits_0_bits_ve_addr = io_in_bits_0_bits_ve_addr; // @[VAlu.scala 247:17]
+  assign q0_io_in_bits_0_bits_vs_valid = io_in_bits_0_bits_vs_valid; // @[VAlu.scala 247:17]
+  assign q0_io_in_bits_0_bits_vs_addr = io_in_bits_0_bits_vs_addr; // @[VAlu.scala 247:17]
+  assign q0_io_in_bits_0_bits_vs_tag = io_in_bits_0_bits_vs_tag; // @[VAlu.scala 247:17]
+  assign q0_io_in_bits_0_bits_vt_valid = io_in_bits_0_bits_vt_valid; // @[VAlu.scala 247:17]
+  assign q0_io_in_bits_0_bits_vt_addr = io_in_bits_0_bits_vt_addr; // @[VAlu.scala 247:17]
+  assign q0_io_in_bits_0_bits_vt_tag = io_in_bits_0_bits_vt_tag; // @[VAlu.scala 247:17]
+  assign q0_io_in_bits_0_bits_vu_valid = io_in_bits_0_bits_vu_valid; // @[VAlu.scala 247:17]
+  assign q0_io_in_bits_0_bits_vu_addr = io_in_bits_0_bits_vu_addr; // @[VAlu.scala 247:17]
+  assign q0_io_in_bits_0_bits_vu_tag = io_in_bits_0_bits_vu_tag; // @[VAlu.scala 247:17]
+  assign q0_io_in_bits_0_bits_sv_valid = io_in_bits_0_bits_sv_valid; // @[VAlu.scala 247:17]
+  assign q0_io_in_bits_0_bits_sv_data = io_in_bits_0_bits_sv_data; // @[VAlu.scala 247:17]
+  assign q0_io_in_bits_0_bits_cmdsync = io_in_bits_0_bits_cmdsync; // @[VAlu.scala 247:17]
+  assign q0_io_in_bits_1_valid = io_in_bits_1_valid & (_alusel_2_T_2 | io_in_bits_1_bits_cmdsync); // @[VAlu.scala 278:51]
+  assign q0_io_in_bits_1_bits_op = io_in_bits_1_bits_op; // @[VAlu.scala 247:17]
+  assign q0_io_in_bits_1_bits_f2 = io_in_bits_1_bits_f2; // @[VAlu.scala 247:17]
+  assign q0_io_in_bits_1_bits_sz = io_in_bits_1_bits_sz; // @[VAlu.scala 247:17]
+  assign q0_io_in_bits_1_bits_m = io_in_bits_1_bits_m; // @[VAlu.scala 247:17]
+  assign q0_io_in_bits_1_bits_vd_addr = io_in_bits_1_bits_vd_addr; // @[VAlu.scala 247:17]
+  assign q0_io_in_bits_1_bits_ve_addr = io_in_bits_1_bits_ve_addr; // @[VAlu.scala 247:17]
+  assign q0_io_in_bits_1_bits_vs_valid = io_in_bits_1_bits_vs_valid; // @[VAlu.scala 247:17]
+  assign q0_io_in_bits_1_bits_vs_addr = io_in_bits_1_bits_vs_addr; // @[VAlu.scala 247:17]
+  assign q0_io_in_bits_1_bits_vs_tag = io_in_bits_1_bits_vs_tag; // @[VAlu.scala 247:17]
+  assign q0_io_in_bits_1_bits_vt_valid = io_in_bits_1_bits_vt_valid; // @[VAlu.scala 247:17]
+  assign q0_io_in_bits_1_bits_vt_addr = io_in_bits_1_bits_vt_addr; // @[VAlu.scala 247:17]
+  assign q0_io_in_bits_1_bits_vt_tag = io_in_bits_1_bits_vt_tag; // @[VAlu.scala 247:17]
+  assign q0_io_in_bits_1_bits_vu_valid = io_in_bits_1_bits_vu_valid; // @[VAlu.scala 247:17]
+  assign q0_io_in_bits_1_bits_vu_addr = io_in_bits_1_bits_vu_addr; // @[VAlu.scala 247:17]
+  assign q0_io_in_bits_1_bits_vu_tag = io_in_bits_1_bits_vu_tag; // @[VAlu.scala 247:17]
+  assign q0_io_in_bits_1_bits_sv_valid = io_in_bits_1_bits_sv_valid; // @[VAlu.scala 247:17]
+  assign q0_io_in_bits_1_bits_sv_data = io_in_bits_1_bits_sv_data; // @[VAlu.scala 247:17]
+  assign q0_io_in_bits_1_bits_cmdsync = io_in_bits_1_bits_cmdsync; // @[VAlu.scala 247:17]
+  assign q0_io_in_bits_2_valid = io_in_bits_2_valid & (_alusel_3_T_2 | io_in_bits_2_bits_cmdsync); // @[VAlu.scala 278:51]
+  assign q0_io_in_bits_2_bits_op = io_in_bits_2_bits_op; // @[VAlu.scala 247:17]
+  assign q0_io_in_bits_2_bits_f2 = io_in_bits_2_bits_f2; // @[VAlu.scala 247:17]
+  assign q0_io_in_bits_2_bits_sz = io_in_bits_2_bits_sz; // @[VAlu.scala 247:17]
+  assign q0_io_in_bits_2_bits_m = io_in_bits_2_bits_m; // @[VAlu.scala 247:17]
+  assign q0_io_in_bits_2_bits_vd_addr = io_in_bits_2_bits_vd_addr; // @[VAlu.scala 247:17]
+  assign q0_io_in_bits_2_bits_ve_addr = io_in_bits_2_bits_ve_addr; // @[VAlu.scala 247:17]
+  assign q0_io_in_bits_2_bits_vs_valid = io_in_bits_2_bits_vs_valid; // @[VAlu.scala 247:17]
+  assign q0_io_in_bits_2_bits_vs_addr = io_in_bits_2_bits_vs_addr; // @[VAlu.scala 247:17]
+  assign q0_io_in_bits_2_bits_vs_tag = io_in_bits_2_bits_vs_tag; // @[VAlu.scala 247:17]
+  assign q0_io_in_bits_2_bits_vt_valid = io_in_bits_2_bits_vt_valid; // @[VAlu.scala 247:17]
+  assign q0_io_in_bits_2_bits_vt_addr = io_in_bits_2_bits_vt_addr; // @[VAlu.scala 247:17]
+  assign q0_io_in_bits_2_bits_vt_tag = io_in_bits_2_bits_vt_tag; // @[VAlu.scala 247:17]
+  assign q0_io_in_bits_2_bits_vu_valid = io_in_bits_2_bits_vu_valid; // @[VAlu.scala 247:17]
+  assign q0_io_in_bits_2_bits_vu_addr = io_in_bits_2_bits_vu_addr; // @[VAlu.scala 247:17]
+  assign q0_io_in_bits_2_bits_vu_tag = io_in_bits_2_bits_vu_tag; // @[VAlu.scala 247:17]
+  assign q0_io_in_bits_2_bits_sv_valid = io_in_bits_2_bits_sv_valid; // @[VAlu.scala 247:17]
+  assign q0_io_in_bits_2_bits_sv_data = io_in_bits_2_bits_sv_data; // @[VAlu.scala 247:17]
+  assign q0_io_in_bits_2_bits_cmdsync = io_in_bits_2_bits_cmdsync; // @[VAlu.scala 247:17]
+  assign q0_io_in_bits_3_valid = io_in_bits_3_valid & (_alusel_4_T_2 | io_in_bits_3_bits_cmdsync); // @[VAlu.scala 278:51]
+  assign q0_io_in_bits_3_bits_op = io_in_bits_3_bits_op; // @[VAlu.scala 247:17]
+  assign q0_io_in_bits_3_bits_f2 = io_in_bits_3_bits_f2; // @[VAlu.scala 247:17]
+  assign q0_io_in_bits_3_bits_sz = io_in_bits_3_bits_sz; // @[VAlu.scala 247:17]
+  assign q0_io_in_bits_3_bits_m = io_in_bits_3_bits_m; // @[VAlu.scala 247:17]
+  assign q0_io_in_bits_3_bits_vd_addr = io_in_bits_3_bits_vd_addr; // @[VAlu.scala 247:17]
+  assign q0_io_in_bits_3_bits_ve_addr = io_in_bits_3_bits_ve_addr; // @[VAlu.scala 247:17]
+  assign q0_io_in_bits_3_bits_vs_valid = io_in_bits_3_bits_vs_valid; // @[VAlu.scala 247:17]
+  assign q0_io_in_bits_3_bits_vs_addr = io_in_bits_3_bits_vs_addr; // @[VAlu.scala 247:17]
+  assign q0_io_in_bits_3_bits_vs_tag = io_in_bits_3_bits_vs_tag; // @[VAlu.scala 247:17]
+  assign q0_io_in_bits_3_bits_vt_valid = io_in_bits_3_bits_vt_valid; // @[VAlu.scala 247:17]
+  assign q0_io_in_bits_3_bits_vt_addr = io_in_bits_3_bits_vt_addr; // @[VAlu.scala 247:17]
+  assign q0_io_in_bits_3_bits_vt_tag = io_in_bits_3_bits_vt_tag; // @[VAlu.scala 247:17]
+  assign q0_io_in_bits_3_bits_vu_valid = io_in_bits_3_bits_vu_valid; // @[VAlu.scala 247:17]
+  assign q0_io_in_bits_3_bits_vu_addr = io_in_bits_3_bits_vu_addr; // @[VAlu.scala 247:17]
+  assign q0_io_in_bits_3_bits_vu_tag = io_in_bits_3_bits_vu_tag; // @[VAlu.scala 247:17]
+  assign q0_io_in_bits_3_bits_sv_valid = io_in_bits_3_bits_sv_valid; // @[VAlu.scala 247:17]
+  assign q0_io_in_bits_3_bits_sv_data = io_in_bits_3_bits_sv_data; // @[VAlu.scala 247:17]
+  assign q0_io_in_bits_3_bits_cmdsync = io_in_bits_3_bits_cmdsync; // @[VAlu.scala 247:17]
+  assign q0_io_out_ready = q0ready & (~q0_io_out_bits_cmdsync | q1_io_out_valid & q1ready & q1_io_out_bits_cmdsync); // @[VAlu.scala 258:30]
   assign q1_clock = clock;
   assign q1_reset = reset;
-  assign q1_io_in_valid = io_in_valid & q0_io_in_ready; // @[VAlu.scala 264:33]
-  assign q1_io_in_bits_0_valid = io_in_bits_0_valid & (alureg | io_in_bits_0_bits_cmdsync); // @[VAlu.scala 299:51]
-  assign q1_io_in_bits_0_bits_op = io_in_bits_0_bits_op; // @[VAlu.scala 268:17]
-  assign q1_io_in_bits_0_bits_f2 = io_in_bits_0_bits_f2; // @[VAlu.scala 268:17]
-  assign q1_io_in_bits_0_bits_sz = io_in_bits_0_bits_sz; // @[VAlu.scala 268:17]
-  assign q1_io_in_bits_0_bits_m = io_in_bits_0_bits_m; // @[VAlu.scala 268:17]
-  assign q1_io_in_bits_0_bits_vd_addr = io_in_bits_0_bits_vd_addr; // @[VAlu.scala 268:17]
-  assign q1_io_in_bits_0_bits_ve_addr = io_in_bits_0_bits_ve_addr; // @[VAlu.scala 268:17]
-  assign q1_io_in_bits_0_bits_vf_addr = io_in_bits_0_bits_vf_addr; // @[VAlu.scala 268:17]
-  assign q1_io_in_bits_0_bits_vg_addr = io_in_bits_0_bits_vg_addr; // @[VAlu.scala 268:17]
-  assign q1_io_in_bits_0_bits_vs_valid = io_in_bits_0_bits_vs_valid; // @[VAlu.scala 268:17]
-  assign q1_io_in_bits_0_bits_vs_addr = io_in_bits_0_bits_vs_addr; // @[VAlu.scala 268:17]
-  assign q1_io_in_bits_0_bits_vs_tag = io_in_bits_0_bits_vs_tag; // @[VAlu.scala 268:17]
-  assign q1_io_in_bits_0_bits_vt_valid = io_in_bits_0_bits_vt_valid; // @[VAlu.scala 268:17]
-  assign q1_io_in_bits_0_bits_vt_addr = io_in_bits_0_bits_vt_addr; // @[VAlu.scala 268:17]
-  assign q1_io_in_bits_0_bits_vt_tag = io_in_bits_0_bits_vt_tag; // @[VAlu.scala 268:17]
-  assign q1_io_in_bits_0_bits_vu_valid = io_in_bits_0_bits_vu_valid; // @[VAlu.scala 268:17]
-  assign q1_io_in_bits_0_bits_vu_addr = io_in_bits_0_bits_vu_addr; // @[VAlu.scala 268:17]
-  assign q1_io_in_bits_0_bits_vu_tag = io_in_bits_0_bits_vu_tag; // @[VAlu.scala 268:17]
-  assign q1_io_in_bits_0_bits_vx_valid = io_in_bits_0_bits_vx_valid; // @[VAlu.scala 268:17]
-  assign q1_io_in_bits_0_bits_vx_addr = io_in_bits_0_bits_vx_addr; // @[VAlu.scala 268:17]
-  assign q1_io_in_bits_0_bits_vx_tag = io_in_bits_0_bits_vx_tag; // @[VAlu.scala 268:17]
-  assign q1_io_in_bits_0_bits_vy_valid = io_in_bits_0_bits_vy_valid; // @[VAlu.scala 268:17]
-  assign q1_io_in_bits_0_bits_vy_addr = io_in_bits_0_bits_vy_addr; // @[VAlu.scala 268:17]
-  assign q1_io_in_bits_0_bits_vy_tag = io_in_bits_0_bits_vy_tag; // @[VAlu.scala 268:17]
-  assign q1_io_in_bits_0_bits_vz_valid = io_in_bits_0_bits_vz_valid; // @[VAlu.scala 268:17]
-  assign q1_io_in_bits_0_bits_vz_addr = io_in_bits_0_bits_vz_addr; // @[VAlu.scala 268:17]
-  assign q1_io_in_bits_0_bits_vz_tag = io_in_bits_0_bits_vz_tag; // @[VAlu.scala 268:17]
-  assign q1_io_in_bits_0_bits_sv_valid = io_in_bits_0_bits_sv_valid; // @[VAlu.scala 268:17]
-  assign q1_io_in_bits_0_bits_sv_data = io_in_bits_0_bits_sv_data; // @[VAlu.scala 268:17]
-  assign q1_io_in_bits_0_bits_cmdsync = io_in_bits_0_bits_cmdsync; // @[VAlu.scala 268:17]
-  assign q1_io_in_bits_1_valid = io_in_bits_1_valid & (alusel_1 | io_in_bits_1_bits_cmdsync); // @[VAlu.scala 299:51]
-  assign q1_io_in_bits_1_bits_op = io_in_bits_1_bits_op; // @[VAlu.scala 268:17]
-  assign q1_io_in_bits_1_bits_f2 = io_in_bits_1_bits_f2; // @[VAlu.scala 268:17]
-  assign q1_io_in_bits_1_bits_sz = io_in_bits_1_bits_sz; // @[VAlu.scala 268:17]
-  assign q1_io_in_bits_1_bits_m = io_in_bits_1_bits_m; // @[VAlu.scala 268:17]
-  assign q1_io_in_bits_1_bits_vd_addr = io_in_bits_1_bits_vd_addr; // @[VAlu.scala 268:17]
-  assign q1_io_in_bits_1_bits_ve_addr = io_in_bits_1_bits_ve_addr; // @[VAlu.scala 268:17]
-  assign q1_io_in_bits_1_bits_vf_addr = io_in_bits_1_bits_vf_addr; // @[VAlu.scala 268:17]
-  assign q1_io_in_bits_1_bits_vg_addr = io_in_bits_1_bits_vg_addr; // @[VAlu.scala 268:17]
-  assign q1_io_in_bits_1_bits_vs_valid = io_in_bits_1_bits_vs_valid; // @[VAlu.scala 268:17]
-  assign q1_io_in_bits_1_bits_vs_addr = io_in_bits_1_bits_vs_addr; // @[VAlu.scala 268:17]
-  assign q1_io_in_bits_1_bits_vs_tag = io_in_bits_1_bits_vs_tag; // @[VAlu.scala 268:17]
-  assign q1_io_in_bits_1_bits_vt_valid = io_in_bits_1_bits_vt_valid; // @[VAlu.scala 268:17]
-  assign q1_io_in_bits_1_bits_vt_addr = io_in_bits_1_bits_vt_addr; // @[VAlu.scala 268:17]
-  assign q1_io_in_bits_1_bits_vt_tag = io_in_bits_1_bits_vt_tag; // @[VAlu.scala 268:17]
-  assign q1_io_in_bits_1_bits_vu_valid = io_in_bits_1_bits_vu_valid; // @[VAlu.scala 268:17]
-  assign q1_io_in_bits_1_bits_vu_addr = io_in_bits_1_bits_vu_addr; // @[VAlu.scala 268:17]
-  assign q1_io_in_bits_1_bits_vu_tag = io_in_bits_1_bits_vu_tag; // @[VAlu.scala 268:17]
-  assign q1_io_in_bits_1_bits_vx_valid = io_in_bits_1_bits_vx_valid; // @[VAlu.scala 268:17]
-  assign q1_io_in_bits_1_bits_vx_addr = io_in_bits_1_bits_vx_addr; // @[VAlu.scala 268:17]
-  assign q1_io_in_bits_1_bits_vx_tag = io_in_bits_1_bits_vx_tag; // @[VAlu.scala 268:17]
-  assign q1_io_in_bits_1_bits_vy_valid = io_in_bits_1_bits_vy_valid; // @[VAlu.scala 268:17]
-  assign q1_io_in_bits_1_bits_vy_addr = io_in_bits_1_bits_vy_addr; // @[VAlu.scala 268:17]
-  assign q1_io_in_bits_1_bits_vy_tag = io_in_bits_1_bits_vy_tag; // @[VAlu.scala 268:17]
-  assign q1_io_in_bits_1_bits_vz_valid = io_in_bits_1_bits_vz_valid; // @[VAlu.scala 268:17]
-  assign q1_io_in_bits_1_bits_vz_addr = io_in_bits_1_bits_vz_addr; // @[VAlu.scala 268:17]
-  assign q1_io_in_bits_1_bits_vz_tag = io_in_bits_1_bits_vz_tag; // @[VAlu.scala 268:17]
-  assign q1_io_in_bits_1_bits_sv_valid = io_in_bits_1_bits_sv_valid; // @[VAlu.scala 268:17]
-  assign q1_io_in_bits_1_bits_sv_data = io_in_bits_1_bits_sv_data; // @[VAlu.scala 268:17]
-  assign q1_io_in_bits_1_bits_cmdsync = io_in_bits_1_bits_cmdsync; // @[VAlu.scala 268:17]
-  assign q1_io_in_bits_2_valid = io_in_bits_2_valid & (alusel_2 | io_in_bits_2_bits_cmdsync); // @[VAlu.scala 299:51]
-  assign q1_io_in_bits_2_bits_op = io_in_bits_2_bits_op; // @[VAlu.scala 268:17]
-  assign q1_io_in_bits_2_bits_f2 = io_in_bits_2_bits_f2; // @[VAlu.scala 268:17]
-  assign q1_io_in_bits_2_bits_sz = io_in_bits_2_bits_sz; // @[VAlu.scala 268:17]
-  assign q1_io_in_bits_2_bits_m = io_in_bits_2_bits_m; // @[VAlu.scala 268:17]
-  assign q1_io_in_bits_2_bits_vd_addr = io_in_bits_2_bits_vd_addr; // @[VAlu.scala 268:17]
-  assign q1_io_in_bits_2_bits_ve_addr = io_in_bits_2_bits_ve_addr; // @[VAlu.scala 268:17]
-  assign q1_io_in_bits_2_bits_vf_addr = io_in_bits_2_bits_vf_addr; // @[VAlu.scala 268:17]
-  assign q1_io_in_bits_2_bits_vg_addr = io_in_bits_2_bits_vg_addr; // @[VAlu.scala 268:17]
-  assign q1_io_in_bits_2_bits_vs_valid = io_in_bits_2_bits_vs_valid; // @[VAlu.scala 268:17]
-  assign q1_io_in_bits_2_bits_vs_addr = io_in_bits_2_bits_vs_addr; // @[VAlu.scala 268:17]
-  assign q1_io_in_bits_2_bits_vs_tag = io_in_bits_2_bits_vs_tag; // @[VAlu.scala 268:17]
-  assign q1_io_in_bits_2_bits_vt_valid = io_in_bits_2_bits_vt_valid; // @[VAlu.scala 268:17]
-  assign q1_io_in_bits_2_bits_vt_addr = io_in_bits_2_bits_vt_addr; // @[VAlu.scala 268:17]
-  assign q1_io_in_bits_2_bits_vt_tag = io_in_bits_2_bits_vt_tag; // @[VAlu.scala 268:17]
-  assign q1_io_in_bits_2_bits_vu_valid = io_in_bits_2_bits_vu_valid; // @[VAlu.scala 268:17]
-  assign q1_io_in_bits_2_bits_vu_addr = io_in_bits_2_bits_vu_addr; // @[VAlu.scala 268:17]
-  assign q1_io_in_bits_2_bits_vu_tag = io_in_bits_2_bits_vu_tag; // @[VAlu.scala 268:17]
-  assign q1_io_in_bits_2_bits_vx_valid = io_in_bits_2_bits_vx_valid; // @[VAlu.scala 268:17]
-  assign q1_io_in_bits_2_bits_vx_addr = io_in_bits_2_bits_vx_addr; // @[VAlu.scala 268:17]
-  assign q1_io_in_bits_2_bits_vx_tag = io_in_bits_2_bits_vx_tag; // @[VAlu.scala 268:17]
-  assign q1_io_in_bits_2_bits_vy_valid = io_in_bits_2_bits_vy_valid; // @[VAlu.scala 268:17]
-  assign q1_io_in_bits_2_bits_vy_addr = io_in_bits_2_bits_vy_addr; // @[VAlu.scala 268:17]
-  assign q1_io_in_bits_2_bits_vy_tag = io_in_bits_2_bits_vy_tag; // @[VAlu.scala 268:17]
-  assign q1_io_in_bits_2_bits_vz_valid = io_in_bits_2_bits_vz_valid; // @[VAlu.scala 268:17]
-  assign q1_io_in_bits_2_bits_vz_addr = io_in_bits_2_bits_vz_addr; // @[VAlu.scala 268:17]
-  assign q1_io_in_bits_2_bits_vz_tag = io_in_bits_2_bits_vz_tag; // @[VAlu.scala 268:17]
-  assign q1_io_in_bits_2_bits_sv_valid = io_in_bits_2_bits_sv_valid; // @[VAlu.scala 268:17]
-  assign q1_io_in_bits_2_bits_sv_data = io_in_bits_2_bits_sv_data; // @[VAlu.scala 268:17]
-  assign q1_io_in_bits_2_bits_cmdsync = io_in_bits_2_bits_cmdsync; // @[VAlu.scala 268:17]
-  assign q1_io_in_bits_3_valid = io_in_bits_3_valid & (alusel_3 | io_in_bits_3_bits_cmdsync); // @[VAlu.scala 299:51]
-  assign q1_io_in_bits_3_bits_op = io_in_bits_3_bits_op; // @[VAlu.scala 268:17]
-  assign q1_io_in_bits_3_bits_f2 = io_in_bits_3_bits_f2; // @[VAlu.scala 268:17]
-  assign q1_io_in_bits_3_bits_sz = io_in_bits_3_bits_sz; // @[VAlu.scala 268:17]
-  assign q1_io_in_bits_3_bits_m = io_in_bits_3_bits_m; // @[VAlu.scala 268:17]
-  assign q1_io_in_bits_3_bits_vd_addr = io_in_bits_3_bits_vd_addr; // @[VAlu.scala 268:17]
-  assign q1_io_in_bits_3_bits_ve_addr = io_in_bits_3_bits_ve_addr; // @[VAlu.scala 268:17]
-  assign q1_io_in_bits_3_bits_vf_addr = io_in_bits_3_bits_vf_addr; // @[VAlu.scala 268:17]
-  assign q1_io_in_bits_3_bits_vg_addr = io_in_bits_3_bits_vg_addr; // @[VAlu.scala 268:17]
-  assign q1_io_in_bits_3_bits_vs_valid = io_in_bits_3_bits_vs_valid; // @[VAlu.scala 268:17]
-  assign q1_io_in_bits_3_bits_vs_addr = io_in_bits_3_bits_vs_addr; // @[VAlu.scala 268:17]
-  assign q1_io_in_bits_3_bits_vs_tag = io_in_bits_3_bits_vs_tag; // @[VAlu.scala 268:17]
-  assign q1_io_in_bits_3_bits_vt_valid = io_in_bits_3_bits_vt_valid; // @[VAlu.scala 268:17]
-  assign q1_io_in_bits_3_bits_vt_addr = io_in_bits_3_bits_vt_addr; // @[VAlu.scala 268:17]
-  assign q1_io_in_bits_3_bits_vt_tag = io_in_bits_3_bits_vt_tag; // @[VAlu.scala 268:17]
-  assign q1_io_in_bits_3_bits_vu_valid = io_in_bits_3_bits_vu_valid; // @[VAlu.scala 268:17]
-  assign q1_io_in_bits_3_bits_vu_addr = io_in_bits_3_bits_vu_addr; // @[VAlu.scala 268:17]
-  assign q1_io_in_bits_3_bits_vu_tag = io_in_bits_3_bits_vu_tag; // @[VAlu.scala 268:17]
-  assign q1_io_in_bits_3_bits_vx_valid = io_in_bits_3_bits_vx_valid; // @[VAlu.scala 268:17]
-  assign q1_io_in_bits_3_bits_vx_addr = io_in_bits_3_bits_vx_addr; // @[VAlu.scala 268:17]
-  assign q1_io_in_bits_3_bits_vx_tag = io_in_bits_3_bits_vx_tag; // @[VAlu.scala 268:17]
-  assign q1_io_in_bits_3_bits_vy_valid = io_in_bits_3_bits_vy_valid; // @[VAlu.scala 268:17]
-  assign q1_io_in_bits_3_bits_vy_addr = io_in_bits_3_bits_vy_addr; // @[VAlu.scala 268:17]
-  assign q1_io_in_bits_3_bits_vy_tag = io_in_bits_3_bits_vy_tag; // @[VAlu.scala 268:17]
-  assign q1_io_in_bits_3_bits_vz_valid = io_in_bits_3_bits_vz_valid; // @[VAlu.scala 268:17]
-  assign q1_io_in_bits_3_bits_vz_addr = io_in_bits_3_bits_vz_addr; // @[VAlu.scala 268:17]
-  assign q1_io_in_bits_3_bits_vz_tag = io_in_bits_3_bits_vz_tag; // @[VAlu.scala 268:17]
-  assign q1_io_in_bits_3_bits_sv_valid = io_in_bits_3_bits_sv_valid; // @[VAlu.scala 268:17]
-  assign q1_io_in_bits_3_bits_sv_data = io_in_bits_3_bits_sv_data; // @[VAlu.scala 268:17]
-  assign q1_io_in_bits_3_bits_cmdsync = io_in_bits_3_bits_cmdsync; // @[VAlu.scala 268:17]
-  assign q1_io_out_ready = q1ready & (~q1_io_out_bits_cmdsync | q0_io_out_valid & q0ready & q0_io_out_bits_cmdsync); // @[VAlu.scala 279:30]
+  assign q1_io_in_valid = io_in_valid & q0_io_in_ready; // @[VAlu.scala 244:33]
+  assign q1_io_in_bits_0_valid = io_in_bits_0_valid & (alureg | io_in_bits_0_bits_cmdsync); // @[VAlu.scala 279:51]
+  assign q1_io_in_bits_0_bits_op = io_in_bits_0_bits_op; // @[VAlu.scala 248:17]
+  assign q1_io_in_bits_0_bits_f2 = io_in_bits_0_bits_f2; // @[VAlu.scala 248:17]
+  assign q1_io_in_bits_0_bits_sz = io_in_bits_0_bits_sz; // @[VAlu.scala 248:17]
+  assign q1_io_in_bits_0_bits_m = io_in_bits_0_bits_m; // @[VAlu.scala 248:17]
+  assign q1_io_in_bits_0_bits_vd_addr = io_in_bits_0_bits_vd_addr; // @[VAlu.scala 248:17]
+  assign q1_io_in_bits_0_bits_ve_addr = io_in_bits_0_bits_ve_addr; // @[VAlu.scala 248:17]
+  assign q1_io_in_bits_0_bits_vf_addr = io_in_bits_0_bits_vf_addr; // @[VAlu.scala 248:17]
+  assign q1_io_in_bits_0_bits_vg_addr = io_in_bits_0_bits_vg_addr; // @[VAlu.scala 248:17]
+  assign q1_io_in_bits_0_bits_vs_valid = io_in_bits_0_bits_vs_valid; // @[VAlu.scala 248:17]
+  assign q1_io_in_bits_0_bits_vs_addr = io_in_bits_0_bits_vs_addr; // @[VAlu.scala 248:17]
+  assign q1_io_in_bits_0_bits_vs_tag = io_in_bits_0_bits_vs_tag; // @[VAlu.scala 248:17]
+  assign q1_io_in_bits_0_bits_vt_valid = io_in_bits_0_bits_vt_valid; // @[VAlu.scala 248:17]
+  assign q1_io_in_bits_0_bits_vt_addr = io_in_bits_0_bits_vt_addr; // @[VAlu.scala 248:17]
+  assign q1_io_in_bits_0_bits_vt_tag = io_in_bits_0_bits_vt_tag; // @[VAlu.scala 248:17]
+  assign q1_io_in_bits_0_bits_vu_valid = io_in_bits_0_bits_vu_valid; // @[VAlu.scala 248:17]
+  assign q1_io_in_bits_0_bits_vu_addr = io_in_bits_0_bits_vu_addr; // @[VAlu.scala 248:17]
+  assign q1_io_in_bits_0_bits_vu_tag = io_in_bits_0_bits_vu_tag; // @[VAlu.scala 248:17]
+  assign q1_io_in_bits_0_bits_vx_valid = io_in_bits_0_bits_vx_valid; // @[VAlu.scala 248:17]
+  assign q1_io_in_bits_0_bits_vx_addr = io_in_bits_0_bits_vx_addr; // @[VAlu.scala 248:17]
+  assign q1_io_in_bits_0_bits_vx_tag = io_in_bits_0_bits_vx_tag; // @[VAlu.scala 248:17]
+  assign q1_io_in_bits_0_bits_vy_valid = io_in_bits_0_bits_vy_valid; // @[VAlu.scala 248:17]
+  assign q1_io_in_bits_0_bits_vy_addr = io_in_bits_0_bits_vy_addr; // @[VAlu.scala 248:17]
+  assign q1_io_in_bits_0_bits_vy_tag = io_in_bits_0_bits_vy_tag; // @[VAlu.scala 248:17]
+  assign q1_io_in_bits_0_bits_vz_valid = io_in_bits_0_bits_vz_valid; // @[VAlu.scala 248:17]
+  assign q1_io_in_bits_0_bits_vz_addr = io_in_bits_0_bits_vz_addr; // @[VAlu.scala 248:17]
+  assign q1_io_in_bits_0_bits_vz_tag = io_in_bits_0_bits_vz_tag; // @[VAlu.scala 248:17]
+  assign q1_io_in_bits_0_bits_sv_valid = io_in_bits_0_bits_sv_valid; // @[VAlu.scala 248:17]
+  assign q1_io_in_bits_0_bits_sv_data = io_in_bits_0_bits_sv_data; // @[VAlu.scala 248:17]
+  assign q1_io_in_bits_0_bits_cmdsync = io_in_bits_0_bits_cmdsync; // @[VAlu.scala 248:17]
+  assign q1_io_in_bits_1_valid = io_in_bits_1_valid & (alusel_1 | io_in_bits_1_bits_cmdsync); // @[VAlu.scala 279:51]
+  assign q1_io_in_bits_1_bits_op = io_in_bits_1_bits_op; // @[VAlu.scala 248:17]
+  assign q1_io_in_bits_1_bits_f2 = io_in_bits_1_bits_f2; // @[VAlu.scala 248:17]
+  assign q1_io_in_bits_1_bits_sz = io_in_bits_1_bits_sz; // @[VAlu.scala 248:17]
+  assign q1_io_in_bits_1_bits_m = io_in_bits_1_bits_m; // @[VAlu.scala 248:17]
+  assign q1_io_in_bits_1_bits_vd_addr = io_in_bits_1_bits_vd_addr; // @[VAlu.scala 248:17]
+  assign q1_io_in_bits_1_bits_ve_addr = io_in_bits_1_bits_ve_addr; // @[VAlu.scala 248:17]
+  assign q1_io_in_bits_1_bits_vf_addr = io_in_bits_1_bits_vf_addr; // @[VAlu.scala 248:17]
+  assign q1_io_in_bits_1_bits_vg_addr = io_in_bits_1_bits_vg_addr; // @[VAlu.scala 248:17]
+  assign q1_io_in_bits_1_bits_vs_valid = io_in_bits_1_bits_vs_valid; // @[VAlu.scala 248:17]
+  assign q1_io_in_bits_1_bits_vs_addr = io_in_bits_1_bits_vs_addr; // @[VAlu.scala 248:17]
+  assign q1_io_in_bits_1_bits_vs_tag = io_in_bits_1_bits_vs_tag; // @[VAlu.scala 248:17]
+  assign q1_io_in_bits_1_bits_vt_valid = io_in_bits_1_bits_vt_valid; // @[VAlu.scala 248:17]
+  assign q1_io_in_bits_1_bits_vt_addr = io_in_bits_1_bits_vt_addr; // @[VAlu.scala 248:17]
+  assign q1_io_in_bits_1_bits_vt_tag = io_in_bits_1_bits_vt_tag; // @[VAlu.scala 248:17]
+  assign q1_io_in_bits_1_bits_vu_valid = io_in_bits_1_bits_vu_valid; // @[VAlu.scala 248:17]
+  assign q1_io_in_bits_1_bits_vu_addr = io_in_bits_1_bits_vu_addr; // @[VAlu.scala 248:17]
+  assign q1_io_in_bits_1_bits_vu_tag = io_in_bits_1_bits_vu_tag; // @[VAlu.scala 248:17]
+  assign q1_io_in_bits_1_bits_vx_valid = io_in_bits_1_bits_vx_valid; // @[VAlu.scala 248:17]
+  assign q1_io_in_bits_1_bits_vx_addr = io_in_bits_1_bits_vx_addr; // @[VAlu.scala 248:17]
+  assign q1_io_in_bits_1_bits_vx_tag = io_in_bits_1_bits_vx_tag; // @[VAlu.scala 248:17]
+  assign q1_io_in_bits_1_bits_vy_valid = io_in_bits_1_bits_vy_valid; // @[VAlu.scala 248:17]
+  assign q1_io_in_bits_1_bits_vy_addr = io_in_bits_1_bits_vy_addr; // @[VAlu.scala 248:17]
+  assign q1_io_in_bits_1_bits_vy_tag = io_in_bits_1_bits_vy_tag; // @[VAlu.scala 248:17]
+  assign q1_io_in_bits_1_bits_vz_valid = io_in_bits_1_bits_vz_valid; // @[VAlu.scala 248:17]
+  assign q1_io_in_bits_1_bits_vz_addr = io_in_bits_1_bits_vz_addr; // @[VAlu.scala 248:17]
+  assign q1_io_in_bits_1_bits_vz_tag = io_in_bits_1_bits_vz_tag; // @[VAlu.scala 248:17]
+  assign q1_io_in_bits_1_bits_sv_valid = io_in_bits_1_bits_sv_valid; // @[VAlu.scala 248:17]
+  assign q1_io_in_bits_1_bits_sv_data = io_in_bits_1_bits_sv_data; // @[VAlu.scala 248:17]
+  assign q1_io_in_bits_1_bits_cmdsync = io_in_bits_1_bits_cmdsync; // @[VAlu.scala 248:17]
+  assign q1_io_in_bits_2_valid = io_in_bits_2_valid & (alusel_2 | io_in_bits_2_bits_cmdsync); // @[VAlu.scala 279:51]
+  assign q1_io_in_bits_2_bits_op = io_in_bits_2_bits_op; // @[VAlu.scala 248:17]
+  assign q1_io_in_bits_2_bits_f2 = io_in_bits_2_bits_f2; // @[VAlu.scala 248:17]
+  assign q1_io_in_bits_2_bits_sz = io_in_bits_2_bits_sz; // @[VAlu.scala 248:17]
+  assign q1_io_in_bits_2_bits_m = io_in_bits_2_bits_m; // @[VAlu.scala 248:17]
+  assign q1_io_in_bits_2_bits_vd_addr = io_in_bits_2_bits_vd_addr; // @[VAlu.scala 248:17]
+  assign q1_io_in_bits_2_bits_ve_addr = io_in_bits_2_bits_ve_addr; // @[VAlu.scala 248:17]
+  assign q1_io_in_bits_2_bits_vf_addr = io_in_bits_2_bits_vf_addr; // @[VAlu.scala 248:17]
+  assign q1_io_in_bits_2_bits_vg_addr = io_in_bits_2_bits_vg_addr; // @[VAlu.scala 248:17]
+  assign q1_io_in_bits_2_bits_vs_valid = io_in_bits_2_bits_vs_valid; // @[VAlu.scala 248:17]
+  assign q1_io_in_bits_2_bits_vs_addr = io_in_bits_2_bits_vs_addr; // @[VAlu.scala 248:17]
+  assign q1_io_in_bits_2_bits_vs_tag = io_in_bits_2_bits_vs_tag; // @[VAlu.scala 248:17]
+  assign q1_io_in_bits_2_bits_vt_valid = io_in_bits_2_bits_vt_valid; // @[VAlu.scala 248:17]
+  assign q1_io_in_bits_2_bits_vt_addr = io_in_bits_2_bits_vt_addr; // @[VAlu.scala 248:17]
+  assign q1_io_in_bits_2_bits_vt_tag = io_in_bits_2_bits_vt_tag; // @[VAlu.scala 248:17]
+  assign q1_io_in_bits_2_bits_vu_valid = io_in_bits_2_bits_vu_valid; // @[VAlu.scala 248:17]
+  assign q1_io_in_bits_2_bits_vu_addr = io_in_bits_2_bits_vu_addr; // @[VAlu.scala 248:17]
+  assign q1_io_in_bits_2_bits_vu_tag = io_in_bits_2_bits_vu_tag; // @[VAlu.scala 248:17]
+  assign q1_io_in_bits_2_bits_vx_valid = io_in_bits_2_bits_vx_valid; // @[VAlu.scala 248:17]
+  assign q1_io_in_bits_2_bits_vx_addr = io_in_bits_2_bits_vx_addr; // @[VAlu.scala 248:17]
+  assign q1_io_in_bits_2_bits_vx_tag = io_in_bits_2_bits_vx_tag; // @[VAlu.scala 248:17]
+  assign q1_io_in_bits_2_bits_vy_valid = io_in_bits_2_bits_vy_valid; // @[VAlu.scala 248:17]
+  assign q1_io_in_bits_2_bits_vy_addr = io_in_bits_2_bits_vy_addr; // @[VAlu.scala 248:17]
+  assign q1_io_in_bits_2_bits_vy_tag = io_in_bits_2_bits_vy_tag; // @[VAlu.scala 248:17]
+  assign q1_io_in_bits_2_bits_vz_valid = io_in_bits_2_bits_vz_valid; // @[VAlu.scala 248:17]
+  assign q1_io_in_bits_2_bits_vz_addr = io_in_bits_2_bits_vz_addr; // @[VAlu.scala 248:17]
+  assign q1_io_in_bits_2_bits_vz_tag = io_in_bits_2_bits_vz_tag; // @[VAlu.scala 248:17]
+  assign q1_io_in_bits_2_bits_sv_valid = io_in_bits_2_bits_sv_valid; // @[VAlu.scala 248:17]
+  assign q1_io_in_bits_2_bits_sv_data = io_in_bits_2_bits_sv_data; // @[VAlu.scala 248:17]
+  assign q1_io_in_bits_2_bits_cmdsync = io_in_bits_2_bits_cmdsync; // @[VAlu.scala 248:17]
+  assign q1_io_in_bits_3_valid = io_in_bits_3_valid & (alusel_3 | io_in_bits_3_bits_cmdsync); // @[VAlu.scala 279:51]
+  assign q1_io_in_bits_3_bits_op = io_in_bits_3_bits_op; // @[VAlu.scala 248:17]
+  assign q1_io_in_bits_3_bits_f2 = io_in_bits_3_bits_f2; // @[VAlu.scala 248:17]
+  assign q1_io_in_bits_3_bits_sz = io_in_bits_3_bits_sz; // @[VAlu.scala 248:17]
+  assign q1_io_in_bits_3_bits_m = io_in_bits_3_bits_m; // @[VAlu.scala 248:17]
+  assign q1_io_in_bits_3_bits_vd_addr = io_in_bits_3_bits_vd_addr; // @[VAlu.scala 248:17]
+  assign q1_io_in_bits_3_bits_ve_addr = io_in_bits_3_bits_ve_addr; // @[VAlu.scala 248:17]
+  assign q1_io_in_bits_3_bits_vf_addr = io_in_bits_3_bits_vf_addr; // @[VAlu.scala 248:17]
+  assign q1_io_in_bits_3_bits_vg_addr = io_in_bits_3_bits_vg_addr; // @[VAlu.scala 248:17]
+  assign q1_io_in_bits_3_bits_vs_valid = io_in_bits_3_bits_vs_valid; // @[VAlu.scala 248:17]
+  assign q1_io_in_bits_3_bits_vs_addr = io_in_bits_3_bits_vs_addr; // @[VAlu.scala 248:17]
+  assign q1_io_in_bits_3_bits_vs_tag = io_in_bits_3_bits_vs_tag; // @[VAlu.scala 248:17]
+  assign q1_io_in_bits_3_bits_vt_valid = io_in_bits_3_bits_vt_valid; // @[VAlu.scala 248:17]
+  assign q1_io_in_bits_3_bits_vt_addr = io_in_bits_3_bits_vt_addr; // @[VAlu.scala 248:17]
+  assign q1_io_in_bits_3_bits_vt_tag = io_in_bits_3_bits_vt_tag; // @[VAlu.scala 248:17]
+  assign q1_io_in_bits_3_bits_vu_valid = io_in_bits_3_bits_vu_valid; // @[VAlu.scala 248:17]
+  assign q1_io_in_bits_3_bits_vu_addr = io_in_bits_3_bits_vu_addr; // @[VAlu.scala 248:17]
+  assign q1_io_in_bits_3_bits_vu_tag = io_in_bits_3_bits_vu_tag; // @[VAlu.scala 248:17]
+  assign q1_io_in_bits_3_bits_vx_valid = io_in_bits_3_bits_vx_valid; // @[VAlu.scala 248:17]
+  assign q1_io_in_bits_3_bits_vx_addr = io_in_bits_3_bits_vx_addr; // @[VAlu.scala 248:17]
+  assign q1_io_in_bits_3_bits_vx_tag = io_in_bits_3_bits_vx_tag; // @[VAlu.scala 248:17]
+  assign q1_io_in_bits_3_bits_vy_valid = io_in_bits_3_bits_vy_valid; // @[VAlu.scala 248:17]
+  assign q1_io_in_bits_3_bits_vy_addr = io_in_bits_3_bits_vy_addr; // @[VAlu.scala 248:17]
+  assign q1_io_in_bits_3_bits_vy_tag = io_in_bits_3_bits_vy_tag; // @[VAlu.scala 248:17]
+  assign q1_io_in_bits_3_bits_vz_valid = io_in_bits_3_bits_vz_valid; // @[VAlu.scala 248:17]
+  assign q1_io_in_bits_3_bits_vz_addr = io_in_bits_3_bits_vz_addr; // @[VAlu.scala 248:17]
+  assign q1_io_in_bits_3_bits_vz_tag = io_in_bits_3_bits_vz_tag; // @[VAlu.scala 248:17]
+  assign q1_io_in_bits_3_bits_sv_valid = io_in_bits_3_bits_sv_valid; // @[VAlu.scala 248:17]
+  assign q1_io_in_bits_3_bits_sv_data = io_in_bits_3_bits_sv_data; // @[VAlu.scala 248:17]
+  assign q1_io_in_bits_3_bits_cmdsync = io_in_bits_3_bits_cmdsync; // @[VAlu.scala 248:17]
+  assign q1_io_out_ready = q1ready & (~q1_io_out_bits_cmdsync | q0_io_out_valid & q0ready & q0_io_out_bits_cmdsync); // @[VAlu.scala 259:30]
   assign alu0_clock = clock;
   assign alu0_reset = reset;
-  assign alu0_io_in_valid = q0_io_out_valid & q0_io_out_ready; // @[VAlu.scala 343:39]
-  assign alu0_io_in_op = q0_io_out_bits_op; // @[VAlu.scala 344:17]
-  assign alu0_io_in_f2 = q0_io_out_bits_f2; // @[VAlu.scala 345:17]
-  assign alu0_io_in_sz = q0_io_out_bits_sz; // @[VAlu.scala 346:17]
-  assign alu0_io_in_vd_addr = q0_io_out_bits_vd_addr; // @[VAlu.scala 347:22]
-  assign alu0_io_in_ve_addr = q0_io_out_bits_ve_addr; // @[VAlu.scala 348:22]
-  assign alu0_io_in_sv_data = q0_io_out_bits_sv_data; // @[VAlu.scala 349:22]
-  assign alu0_io_read_0_data = io_read_0_data; // @[VAlu.scala 351:24]
-  assign alu0_io_read_1_data = io_read_1_data; // @[VAlu.scala 352:24]
-  assign alu0_io_read_2_data = io_read_2_data; // @[VAlu.scala 353:24]
-  assign alu0_io_read_3_data = io_read_3_data; // @[VAlu.scala 354:24]
-  assign alu0_io_read_4_data = io_read_4_data; // @[VAlu.scala 355:24]
-  assign alu0_io_read_5_data = io_read_5_data; // @[VAlu.scala 356:24]
+  assign alu0_io_in_valid = q0_io_out_valid & q0_io_out_ready; // @[VAlu.scala 323:39]
+  assign alu0_io_in_op = q0_io_out_bits_op; // @[VAlu.scala 324:17]
+  assign alu0_io_in_f2 = q0_io_out_bits_f2; // @[VAlu.scala 325:17]
+  assign alu0_io_in_sz = q0_io_out_bits_sz; // @[VAlu.scala 326:17]
+  assign alu0_io_in_vd_addr = q0_io_out_bits_vd_addr; // @[VAlu.scala 327:22]
+  assign alu0_io_in_ve_addr = q0_io_out_bits_ve_addr; // @[VAlu.scala 328:22]
+  assign alu0_io_in_sv_data = q0_io_out_bits_sv_data; // @[VAlu.scala 329:22]
+  assign alu0_io_read_0_data = io_read_0_data; // @[VAlu.scala 331:24]
+  assign alu0_io_read_1_data = io_read_1_data; // @[VAlu.scala 332:24]
+  assign alu0_io_read_2_data = io_read_2_data; // @[VAlu.scala 333:24]
+  assign alu0_io_read_3_data = io_read_3_data; // @[VAlu.scala 334:24]
+  assign alu0_io_read_4_data = io_read_4_data; // @[VAlu.scala 335:24]
+  assign alu0_io_read_5_data = io_read_5_data; // @[VAlu.scala 336:24]
   assign alu1_clock = clock;
   assign alu1_reset = reset;
-  assign alu1_io_in_valid = q1_io_out_valid & q1_io_out_ready; // @[VAlu.scala 377:39]
-  assign alu1_io_in_op = q1_io_out_bits_op; // @[VAlu.scala 378:17]
-  assign alu1_io_in_f2 = q1_io_out_bits_f2; // @[VAlu.scala 379:17]
-  assign alu1_io_in_sz = q1_io_out_bits_sz; // @[VAlu.scala 380:17]
-  assign alu1_io_in_vd_addr = q1_io_out_bits_vd_addr; // @[VAlu.scala 381:22]
-  assign alu1_io_in_ve_addr = q1_io_out_bits_ve_addr; // @[VAlu.scala 382:22]
-  assign alu1_io_in_sv_data = q1_io_out_bits_sv_data; // @[VAlu.scala 383:22]
-  assign alu1_io_read_0_data = io_read_3_data; // @[VAlu.scala 385:24]
-  assign alu1_io_read_1_data = io_read_4_data; // @[VAlu.scala 386:24]
-  assign alu1_io_read_2_data = io_read_5_data; // @[VAlu.scala 387:24]
-  assign alu1_io_read_3_data = io_read_0_data; // @[VAlu.scala 388:24]
-  assign alu1_io_read_4_data = io_read_1_data; // @[VAlu.scala 389:24]
-  assign alu1_io_read_5_data = io_read_2_data; // @[VAlu.scala 390:24]
+  assign alu1_io_in_valid = q1_io_out_valid & q1_io_out_ready; // @[VAlu.scala 357:39]
+  assign alu1_io_in_op = q1_io_out_bits_op; // @[VAlu.scala 358:17]
+  assign alu1_io_in_f2 = q1_io_out_bits_f2; // @[VAlu.scala 359:17]
+  assign alu1_io_in_sz = q1_io_out_bits_sz; // @[VAlu.scala 360:17]
+  assign alu1_io_in_vd_addr = q1_io_out_bits_vd_addr; // @[VAlu.scala 361:22]
+  assign alu1_io_in_ve_addr = q1_io_out_bits_ve_addr; // @[VAlu.scala 362:22]
+  assign alu1_io_in_sv_data = q1_io_out_bits_sv_data; // @[VAlu.scala 363:22]
+  assign alu1_io_read_0_data = io_read_3_data; // @[VAlu.scala 365:24]
+  assign alu1_io_read_1_data = io_read_4_data; // @[VAlu.scala 366:24]
+  assign alu1_io_read_2_data = io_read_5_data; // @[VAlu.scala 367:24]
+  assign alu1_io_read_3_data = io_read_0_data; // @[VAlu.scala 368:24]
+  assign alu1_io_read_4_data = io_read_1_data; // @[VAlu.scala 369:24]
+  assign alu1_io_read_5_data = io_read_2_data; // @[VAlu.scala 370:24]
   always @(posedge clock) begin
     `ifndef SYNTHESIS
     `ifdef PRINTF_COND
       if (`PRINTF_COND) begin
     `endif
         if (_T & io_in_bits_0_valid & _T_1 & ~reset) begin
-          $fwrite(32'h80000002,"**Op=%d unsupported\n",io_in_bits_0_bits_op); // @[VAlu.scala 157:17]
+          $fwrite(32'h80000002,"**Op=%d unsupported\n",io_in_bits_0_bits_op); // @[VAlu.scala 137:17]
         end
     `ifdef PRINTF_COND
       end
@@ -74169,7 +64611,7 @@
       if (`STOP_COND) begin
     `endif
         if (_GEN_1 & _T_3 & _T_1) begin
-          $fatal; // @[VAlu.scala 159:15]
+          $fatal; // @[VAlu.scala 139:15]
         end
     `ifdef STOP_COND
       end
@@ -74180,7 +64622,7 @@
       if (`PRINTF_COND) begin
     `endif
         if (_GEN_1 & _T_3 & _T_1) begin
-          $fwrite(32'h80000002,"Assertion failed\n    at VAlu.scala:159 assert(supported)\n"); // @[VAlu.scala 159:15]
+          $fwrite(32'h80000002,"Assertion failed\n    at VAlu.scala:139 assert(supported)\n"); // @[VAlu.scala 139:15]
         end
     `ifdef PRINTF_COND
       end
@@ -74191,7 +64633,7 @@
       if (`STOP_COND) begin
     `endif
         if (_GEN_4 & ~(~(io_in_bits_0_bits_vt_valid & io_in_bits_0_bits_sv_valid))) begin
-          $fatal; // @[VAlu.scala 161:15]
+          $fatal; // @[VAlu.scala 141:15]
         end
     `ifdef STOP_COND
       end
@@ -74203,8 +64645,8 @@
     `endif
         if (_GEN_4 & ~(~(io_in_bits_0_bits_vt_valid & io_in_bits_0_bits_sv_valid))) begin
           $fwrite(32'h80000002,
-            "Assertion failed\n    at VAlu.scala:161 assert(!(io.in.bits(i).bits.vt.valid && io.in.bits(i).bits.sv.valid))\n"
-            ); // @[VAlu.scala 161:15]
+            "Assertion failed\n    at VAlu.scala:141 assert(!(io.in.bits(i).bits.vt.valid && io.in.bits(i).bits.sv.valid))\n"
+            ); // @[VAlu.scala 141:15]
         end
     `ifdef PRINTF_COND
       end
@@ -74215,7 +64657,7 @@
       if (`STOP_COND) begin
     `endif
         if (_GEN_1 & _T_14 & _T_3 & ~(~io_in_bits_0_bits_m)) begin
-          $fatal; // @[VAlu.scala 165:17]
+          $fatal; // @[VAlu.scala 145:17]
         end
     `ifdef STOP_COND
       end
@@ -74226,7 +64668,7 @@
       if (`PRINTF_COND) begin
     `endif
         if (_GEN_1 & _T_14 & _T_3 & ~(~io_in_bits_0_bits_m)) begin
-          $fwrite(32'h80000002,"Assertion failed\n    at VAlu.scala:165 assert(io.in.bits(i).bits.m === false.B)\n"); // @[VAlu.scala 165:17]
+          $fwrite(32'h80000002,"Assertion failed\n    at VAlu.scala:145 assert(io.in.bits(i).bits.m === false.B)\n"); // @[VAlu.scala 145:17]
         end
     `ifdef PRINTF_COND
       end
@@ -74237,7 +64679,7 @@
       if (`STOP_COND) begin
     `endif
         if (_GEN_15 & ~(io_in_bits_0_bits_sz == 3'h4)) begin
-          $fatal; // @[VAlu.scala 166:17]
+          $fatal; // @[VAlu.scala 146:17]
         end
     `ifdef STOP_COND
       end
@@ -74248,7 +64690,7 @@
       if (`PRINTF_COND) begin
     `endif
         if (_GEN_15 & ~(io_in_bits_0_bits_sz == 3'h4)) begin
-          $fwrite(32'h80000002,"Assertion failed\n    at VAlu.scala:166 assert(io.in.bits(i).bits.sz === 4.U)\n"); // @[VAlu.scala 166:17]
+          $fwrite(32'h80000002,"Assertion failed\n    at VAlu.scala:146 assert(io.in.bits(i).bits.sz === 4.U)\n"); // @[VAlu.scala 146:17]
         end
     `ifdef PRINTF_COND
       end
@@ -74259,7 +64701,7 @@
       if (`STOP_COND) begin
     `endif
         if (_GEN_15 & ~(~io_in_bits_0_bits_sv_valid)) begin
-          $fatal; // @[VAlu.scala 167:17]
+          $fatal; // @[VAlu.scala 147:17]
         end
     `ifdef STOP_COND
       end
@@ -74271,7 +64713,7 @@
     `endif
         if (_GEN_15 & ~(~io_in_bits_0_bits_sv_valid)) begin
           $fwrite(32'h80000002,
-            "Assertion failed\n    at VAlu.scala:167 assert(io.in.bits(i).bits.sv.valid === false.B)\n"); // @[VAlu.scala 167:17]
+            "Assertion failed\n    at VAlu.scala:147 assert(io.in.bits(i).bits.sv.valid === false.B)\n"); // @[VAlu.scala 147:17]
         end
     `ifdef PRINTF_COND
       end
@@ -74282,7 +64724,7 @@
       if (`STOP_COND) begin
     `endif
         if (_GEN_15 & ~(sparse < 2'h3)) begin
-          $fatal; // @[VAlu.scala 168:17]
+          $fatal; // @[VAlu.scala 148:17]
         end
     `ifdef STOP_COND
       end
@@ -74293,7 +64735,7 @@
       if (`PRINTF_COND) begin
     `endif
         if (_GEN_15 & ~(sparse < 2'h3)) begin
-          $fwrite(32'h80000002,"Assertion failed\n    at VAlu.scala:168 assert(sparse < 3.U)\n"); // @[VAlu.scala 168:17]
+          $fwrite(32'h80000002,"Assertion failed\n    at VAlu.scala:148 assert(sparse < 3.U)\n"); // @[VAlu.scala 148:17]
         end
     `ifdef PRINTF_COND
       end
@@ -74304,7 +64746,7 @@
       if (`PRINTF_COND) begin
     `endif
         if (_T & io_in_bits_1_valid & _T_32 & ~reset) begin
-          $fwrite(32'h80000002,"**Op=%d unsupported\n",io_in_bits_1_bits_op); // @[VAlu.scala 157:17]
+          $fwrite(32'h80000002,"**Op=%d unsupported\n",io_in_bits_1_bits_op); // @[VAlu.scala 137:17]
         end
     `ifdef PRINTF_COND
       end
@@ -74315,7 +64757,7 @@
       if (`STOP_COND) begin
     `endif
         if (_GEN_41 & _T_3 & _T_32) begin
-          $fatal; // @[VAlu.scala 159:15]
+          $fatal; // @[VAlu.scala 139:15]
         end
     `ifdef STOP_COND
       end
@@ -74326,7 +64768,7 @@
       if (`PRINTF_COND) begin
     `endif
         if (_GEN_41 & _T_3 & _T_32) begin
-          $fwrite(32'h80000002,"Assertion failed\n    at VAlu.scala:159 assert(supported)\n"); // @[VAlu.scala 159:15]
+          $fwrite(32'h80000002,"Assertion failed\n    at VAlu.scala:139 assert(supported)\n"); // @[VAlu.scala 139:15]
         end
     `ifdef PRINTF_COND
       end
@@ -74337,7 +64779,7 @@
       if (`STOP_COND) begin
     `endif
         if (_GEN_44 & ~(~(io_in_bits_1_bits_vt_valid & io_in_bits_1_bits_sv_valid))) begin
-          $fatal; // @[VAlu.scala 161:15]
+          $fatal; // @[VAlu.scala 141:15]
         end
     `ifdef STOP_COND
       end
@@ -74349,8 +64791,8 @@
     `endif
         if (_GEN_44 & ~(~(io_in_bits_1_bits_vt_valid & io_in_bits_1_bits_sv_valid))) begin
           $fwrite(32'h80000002,
-            "Assertion failed\n    at VAlu.scala:161 assert(!(io.in.bits(i).bits.vt.valid && io.in.bits(i).bits.sv.valid))\n"
-            ); // @[VAlu.scala 161:15]
+            "Assertion failed\n    at VAlu.scala:141 assert(!(io.in.bits(i).bits.vt.valid && io.in.bits(i).bits.sv.valid))\n"
+            ); // @[VAlu.scala 141:15]
         end
     `ifdef PRINTF_COND
       end
@@ -74361,7 +64803,7 @@
       if (`STOP_COND) begin
     `endif
         if (_GEN_41 & _T_45 & _T_3 & ~(~io_in_bits_1_bits_m)) begin
-          $fatal; // @[VAlu.scala 165:17]
+          $fatal; // @[VAlu.scala 145:17]
         end
     `ifdef STOP_COND
       end
@@ -74372,7 +64814,7 @@
       if (`PRINTF_COND) begin
     `endif
         if (_GEN_41 & _T_45 & _T_3 & ~(~io_in_bits_1_bits_m)) begin
-          $fwrite(32'h80000002,"Assertion failed\n    at VAlu.scala:165 assert(io.in.bits(i).bits.m === false.B)\n"); // @[VAlu.scala 165:17]
+          $fwrite(32'h80000002,"Assertion failed\n    at VAlu.scala:145 assert(io.in.bits(i).bits.m === false.B)\n"); // @[VAlu.scala 145:17]
         end
     `ifdef PRINTF_COND
       end
@@ -74383,7 +64825,7 @@
       if (`STOP_COND) begin
     `endif
         if (_GEN_55 & ~(io_in_bits_1_bits_sz == 3'h4)) begin
-          $fatal; // @[VAlu.scala 166:17]
+          $fatal; // @[VAlu.scala 146:17]
         end
     `ifdef STOP_COND
       end
@@ -74394,7 +64836,7 @@
       if (`PRINTF_COND) begin
     `endif
         if (_GEN_55 & ~(io_in_bits_1_bits_sz == 3'h4)) begin
-          $fwrite(32'h80000002,"Assertion failed\n    at VAlu.scala:166 assert(io.in.bits(i).bits.sz === 4.U)\n"); // @[VAlu.scala 166:17]
+          $fwrite(32'h80000002,"Assertion failed\n    at VAlu.scala:146 assert(io.in.bits(i).bits.sz === 4.U)\n"); // @[VAlu.scala 146:17]
         end
     `ifdef PRINTF_COND
       end
@@ -74405,7 +64847,7 @@
       if (`STOP_COND) begin
     `endif
         if (_GEN_55 & ~(~io_in_bits_1_bits_sv_valid)) begin
-          $fatal; // @[VAlu.scala 167:17]
+          $fatal; // @[VAlu.scala 147:17]
         end
     `ifdef STOP_COND
       end
@@ -74417,7 +64859,7 @@
     `endif
         if (_GEN_55 & ~(~io_in_bits_1_bits_sv_valid)) begin
           $fwrite(32'h80000002,
-            "Assertion failed\n    at VAlu.scala:167 assert(io.in.bits(i).bits.sv.valid === false.B)\n"); // @[VAlu.scala 167:17]
+            "Assertion failed\n    at VAlu.scala:147 assert(io.in.bits(i).bits.sv.valid === false.B)\n"); // @[VAlu.scala 147:17]
         end
     `ifdef PRINTF_COND
       end
@@ -74428,7 +64870,7 @@
       if (`STOP_COND) begin
     `endif
         if (_GEN_55 & ~(sparse_1 < 2'h3)) begin
-          $fatal; // @[VAlu.scala 168:17]
+          $fatal; // @[VAlu.scala 148:17]
         end
     `ifdef STOP_COND
       end
@@ -74439,7 +64881,7 @@
       if (`PRINTF_COND) begin
     `endif
         if (_GEN_55 & ~(sparse_1 < 2'h3)) begin
-          $fwrite(32'h80000002,"Assertion failed\n    at VAlu.scala:168 assert(sparse < 3.U)\n"); // @[VAlu.scala 168:17]
+          $fwrite(32'h80000002,"Assertion failed\n    at VAlu.scala:148 assert(sparse < 3.U)\n"); // @[VAlu.scala 148:17]
         end
     `ifdef PRINTF_COND
       end
@@ -74450,7 +64892,7 @@
       if (`PRINTF_COND) begin
     `endif
         if (_T & io_in_bits_2_valid & _T_63 & ~reset) begin
-          $fwrite(32'h80000002,"**Op=%d unsupported\n",io_in_bits_2_bits_op); // @[VAlu.scala 157:17]
+          $fwrite(32'h80000002,"**Op=%d unsupported\n",io_in_bits_2_bits_op); // @[VAlu.scala 137:17]
         end
     `ifdef PRINTF_COND
       end
@@ -74461,7 +64903,7 @@
       if (`STOP_COND) begin
     `endif
         if (_GEN_81 & _T_3 & _T_63) begin
-          $fatal; // @[VAlu.scala 159:15]
+          $fatal; // @[VAlu.scala 139:15]
         end
     `ifdef STOP_COND
       end
@@ -74472,7 +64914,7 @@
       if (`PRINTF_COND) begin
     `endif
         if (_GEN_81 & _T_3 & _T_63) begin
-          $fwrite(32'h80000002,"Assertion failed\n    at VAlu.scala:159 assert(supported)\n"); // @[VAlu.scala 159:15]
+          $fwrite(32'h80000002,"Assertion failed\n    at VAlu.scala:139 assert(supported)\n"); // @[VAlu.scala 139:15]
         end
     `ifdef PRINTF_COND
       end
@@ -74483,7 +64925,7 @@
       if (`STOP_COND) begin
     `endif
         if (_GEN_84 & ~(~(io_in_bits_2_bits_vt_valid & io_in_bits_2_bits_sv_valid))) begin
-          $fatal; // @[VAlu.scala 161:15]
+          $fatal; // @[VAlu.scala 141:15]
         end
     `ifdef STOP_COND
       end
@@ -74495,8 +64937,8 @@
     `endif
         if (_GEN_84 & ~(~(io_in_bits_2_bits_vt_valid & io_in_bits_2_bits_sv_valid))) begin
           $fwrite(32'h80000002,
-            "Assertion failed\n    at VAlu.scala:161 assert(!(io.in.bits(i).bits.vt.valid && io.in.bits(i).bits.sv.valid))\n"
-            ); // @[VAlu.scala 161:15]
+            "Assertion failed\n    at VAlu.scala:141 assert(!(io.in.bits(i).bits.vt.valid && io.in.bits(i).bits.sv.valid))\n"
+            ); // @[VAlu.scala 141:15]
         end
     `ifdef PRINTF_COND
       end
@@ -74507,7 +64949,7 @@
       if (`STOP_COND) begin
     `endif
         if (_GEN_81 & _T_76 & _T_3 & ~(~io_in_bits_2_bits_m)) begin
-          $fatal; // @[VAlu.scala 165:17]
+          $fatal; // @[VAlu.scala 145:17]
         end
     `ifdef STOP_COND
       end
@@ -74518,7 +64960,7 @@
       if (`PRINTF_COND) begin
     `endif
         if (_GEN_81 & _T_76 & _T_3 & ~(~io_in_bits_2_bits_m)) begin
-          $fwrite(32'h80000002,"Assertion failed\n    at VAlu.scala:165 assert(io.in.bits(i).bits.m === false.B)\n"); // @[VAlu.scala 165:17]
+          $fwrite(32'h80000002,"Assertion failed\n    at VAlu.scala:145 assert(io.in.bits(i).bits.m === false.B)\n"); // @[VAlu.scala 145:17]
         end
     `ifdef PRINTF_COND
       end
@@ -74529,7 +64971,7 @@
       if (`STOP_COND) begin
     `endif
         if (_GEN_95 & ~(io_in_bits_2_bits_sz == 3'h4)) begin
-          $fatal; // @[VAlu.scala 166:17]
+          $fatal; // @[VAlu.scala 146:17]
         end
     `ifdef STOP_COND
       end
@@ -74540,7 +64982,7 @@
       if (`PRINTF_COND) begin
     `endif
         if (_GEN_95 & ~(io_in_bits_2_bits_sz == 3'h4)) begin
-          $fwrite(32'h80000002,"Assertion failed\n    at VAlu.scala:166 assert(io.in.bits(i).bits.sz === 4.U)\n"); // @[VAlu.scala 166:17]
+          $fwrite(32'h80000002,"Assertion failed\n    at VAlu.scala:146 assert(io.in.bits(i).bits.sz === 4.U)\n"); // @[VAlu.scala 146:17]
         end
     `ifdef PRINTF_COND
       end
@@ -74551,7 +64993,7 @@
       if (`STOP_COND) begin
     `endif
         if (_GEN_95 & ~(~io_in_bits_2_bits_sv_valid)) begin
-          $fatal; // @[VAlu.scala 167:17]
+          $fatal; // @[VAlu.scala 147:17]
         end
     `ifdef STOP_COND
       end
@@ -74563,7 +65005,7 @@
     `endif
         if (_GEN_95 & ~(~io_in_bits_2_bits_sv_valid)) begin
           $fwrite(32'h80000002,
-            "Assertion failed\n    at VAlu.scala:167 assert(io.in.bits(i).bits.sv.valid === false.B)\n"); // @[VAlu.scala 167:17]
+            "Assertion failed\n    at VAlu.scala:147 assert(io.in.bits(i).bits.sv.valid === false.B)\n"); // @[VAlu.scala 147:17]
         end
     `ifdef PRINTF_COND
       end
@@ -74574,7 +65016,7 @@
       if (`STOP_COND) begin
     `endif
         if (_GEN_95 & ~(sparse_2 < 2'h3)) begin
-          $fatal; // @[VAlu.scala 168:17]
+          $fatal; // @[VAlu.scala 148:17]
         end
     `ifdef STOP_COND
       end
@@ -74585,7 +65027,7 @@
       if (`PRINTF_COND) begin
     `endif
         if (_GEN_95 & ~(sparse_2 < 2'h3)) begin
-          $fwrite(32'h80000002,"Assertion failed\n    at VAlu.scala:168 assert(sparse < 3.U)\n"); // @[VAlu.scala 168:17]
+          $fwrite(32'h80000002,"Assertion failed\n    at VAlu.scala:148 assert(sparse < 3.U)\n"); // @[VAlu.scala 148:17]
         end
     `ifdef PRINTF_COND
       end
@@ -74596,7 +65038,7 @@
       if (`PRINTF_COND) begin
     `endif
         if (_T & io_in_bits_3_valid & _T_94 & ~reset) begin
-          $fwrite(32'h80000002,"**Op=%d unsupported\n",io_in_bits_3_bits_op); // @[VAlu.scala 157:17]
+          $fwrite(32'h80000002,"**Op=%d unsupported\n",io_in_bits_3_bits_op); // @[VAlu.scala 137:17]
         end
     `ifdef PRINTF_COND
       end
@@ -74607,7 +65049,7 @@
       if (`STOP_COND) begin
     `endif
         if (_GEN_121 & _T_3 & _T_94) begin
-          $fatal; // @[VAlu.scala 159:15]
+          $fatal; // @[VAlu.scala 139:15]
         end
     `ifdef STOP_COND
       end
@@ -74618,7 +65060,7 @@
       if (`PRINTF_COND) begin
     `endif
         if (_GEN_121 & _T_3 & _T_94) begin
-          $fwrite(32'h80000002,"Assertion failed\n    at VAlu.scala:159 assert(supported)\n"); // @[VAlu.scala 159:15]
+          $fwrite(32'h80000002,"Assertion failed\n    at VAlu.scala:139 assert(supported)\n"); // @[VAlu.scala 139:15]
         end
     `ifdef PRINTF_COND
       end
@@ -74629,7 +65071,7 @@
       if (`STOP_COND) begin
     `endif
         if (_GEN_124 & ~(~(io_in_bits_3_bits_vt_valid & io_in_bits_3_bits_sv_valid))) begin
-          $fatal; // @[VAlu.scala 161:15]
+          $fatal; // @[VAlu.scala 141:15]
         end
     `ifdef STOP_COND
       end
@@ -74641,8 +65083,8 @@
     `endif
         if (_GEN_124 & ~(~(io_in_bits_3_bits_vt_valid & io_in_bits_3_bits_sv_valid))) begin
           $fwrite(32'h80000002,
-            "Assertion failed\n    at VAlu.scala:161 assert(!(io.in.bits(i).bits.vt.valid && io.in.bits(i).bits.sv.valid))\n"
-            ); // @[VAlu.scala 161:15]
+            "Assertion failed\n    at VAlu.scala:141 assert(!(io.in.bits(i).bits.vt.valid && io.in.bits(i).bits.sv.valid))\n"
+            ); // @[VAlu.scala 141:15]
         end
     `ifdef PRINTF_COND
       end
@@ -74653,7 +65095,7 @@
       if (`STOP_COND) begin
     `endif
         if (_GEN_121 & _T_107 & _T_3 & ~(~io_in_bits_3_bits_m)) begin
-          $fatal; // @[VAlu.scala 165:17]
+          $fatal; // @[VAlu.scala 145:17]
         end
     `ifdef STOP_COND
       end
@@ -74664,7 +65106,7 @@
       if (`PRINTF_COND) begin
     `endif
         if (_GEN_121 & _T_107 & _T_3 & ~(~io_in_bits_3_bits_m)) begin
-          $fwrite(32'h80000002,"Assertion failed\n    at VAlu.scala:165 assert(io.in.bits(i).bits.m === false.B)\n"); // @[VAlu.scala 165:17]
+          $fwrite(32'h80000002,"Assertion failed\n    at VAlu.scala:145 assert(io.in.bits(i).bits.m === false.B)\n"); // @[VAlu.scala 145:17]
         end
     `ifdef PRINTF_COND
       end
@@ -74675,7 +65117,7 @@
       if (`STOP_COND) begin
     `endif
         if (_GEN_135 & ~(io_in_bits_3_bits_sz == 3'h4)) begin
-          $fatal; // @[VAlu.scala 166:17]
+          $fatal; // @[VAlu.scala 146:17]
         end
     `ifdef STOP_COND
       end
@@ -74686,7 +65128,7 @@
       if (`PRINTF_COND) begin
     `endif
         if (_GEN_135 & ~(io_in_bits_3_bits_sz == 3'h4)) begin
-          $fwrite(32'h80000002,"Assertion failed\n    at VAlu.scala:166 assert(io.in.bits(i).bits.sz === 4.U)\n"); // @[VAlu.scala 166:17]
+          $fwrite(32'h80000002,"Assertion failed\n    at VAlu.scala:146 assert(io.in.bits(i).bits.sz === 4.U)\n"); // @[VAlu.scala 146:17]
         end
     `ifdef PRINTF_COND
       end
@@ -74697,7 +65139,7 @@
       if (`STOP_COND) begin
     `endif
         if (_GEN_135 & ~(~io_in_bits_3_bits_sv_valid)) begin
-          $fatal; // @[VAlu.scala 167:17]
+          $fatal; // @[VAlu.scala 147:17]
         end
     `ifdef STOP_COND
       end
@@ -74709,7 +65151,7 @@
     `endif
         if (_GEN_135 & ~(~io_in_bits_3_bits_sv_valid)) begin
           $fwrite(32'h80000002,
-            "Assertion failed\n    at VAlu.scala:167 assert(io.in.bits(i).bits.sv.valid === false.B)\n"); // @[VAlu.scala 167:17]
+            "Assertion failed\n    at VAlu.scala:147 assert(io.in.bits(i).bits.sv.valid === false.B)\n"); // @[VAlu.scala 147:17]
         end
     `ifdef PRINTF_COND
       end
@@ -74720,7 +65162,7 @@
       if (`STOP_COND) begin
     `endif
         if (_GEN_135 & ~(sparse_3 < 2'h3)) begin
-          $fatal; // @[VAlu.scala 168:17]
+          $fatal; // @[VAlu.scala 148:17]
         end
     `ifdef STOP_COND
       end
@@ -74731,7 +65173,7 @@
       if (`PRINTF_COND) begin
     `endif
         if (_GEN_135 & ~(sparse_3 < 2'h3)) begin
-          $fwrite(32'h80000002,"Assertion failed\n    at VAlu.scala:168 assert(sparse < 3.U)\n"); // @[VAlu.scala 168:17]
+          $fwrite(32'h80000002,"Assertion failed\n    at VAlu.scala:148 assert(sparse < 3.U)\n"); // @[VAlu.scala 148:17]
         end
     `ifdef PRINTF_COND
       end
@@ -74739,9 +65181,9 @@
     `endif // SYNTHESIS
   end
   always @(posedge clock or posedge reset) begin
-    if (reset) begin // @[VAlu.scala 293:37]
-      alureg <= 1'h0; // @[VAlu.scala 289:19 290:19 291:19]
-    end else if (_T) begin // @[VAlu.scala 283:23]
+    if (reset) begin // @[VAlu.scala 273:37]
+      alureg <= 1'h0; // @[VAlu.scala 269:19 270:19 271:19]
+    end else if (_T) begin // @[VAlu.scala 263:23]
       if (io_in_bits_3_valid & ~io_in_bits_3_bits_cmdsync) begin
         alureg <= ~alusel_3;
       end else if (io_in_bits_2_valid & ~io_in_bits_2_bits_cmdsync) begin
@@ -79233,7 +69675,7 @@
   assign f__reset = reset;
   assign f__io_in_valid = io_in_valid; // @[VCmdq.scala 48:17]
   assign f__io_in_bits_0_valid = io_in_bits_0_valid; // @[VCmdq.scala 52:27]
-  assign f__io_in_bits_0_bits_tin_conv = io_in_bits_0_bits_op == 7'h62; // @[VConvCtrl.scala 55:24]
+  assign f__io_in_bits_0_bits_tin_conv = io_in_bits_0_bits_op == 7'h45; // @[VConvCtrl.scala 55:24]
   assign f__io_in_bits_0_bits_tin_init = io_in_bits_0_bits_op == 7'h1f; // @[VConvCtrl.scala 53:24]
   assign f__io_in_bits_0_bits_tin_tran = io_in_bits_0_bits_op == 7'h20; // @[VConvCtrl.scala 54:24]
   assign f__io_in_bits_0_bits_tin_wclr = io_in_bits_0_bits_op == 7'h5; // @[VConvCtrl.scala 52:24]
@@ -79252,7 +69694,7 @@
   assign f__io_in_bits_0_bits_tin_bsign = io_in_bits_0_bits_sv_data[31]; // @[VConvCtrl.scala 89:22]
   assign f__io_in_bits_0_bits_m = io_in_bits_0_bits_m; // @[VCmdq.scala 54:28]
   assign f__io_in_bits_1_valid = io_in_bits_1_valid; // @[VCmdq.scala 52:27]
-  assign f__io_in_bits_1_bits_tin_conv = io_in_bits_1_bits_op == 7'h62; // @[VConvCtrl.scala 55:24]
+  assign f__io_in_bits_1_bits_tin_conv = io_in_bits_1_bits_op == 7'h45; // @[VConvCtrl.scala 55:24]
   assign f__io_in_bits_1_bits_tin_init = io_in_bits_1_bits_op == 7'h1f; // @[VConvCtrl.scala 53:24]
   assign f__io_in_bits_1_bits_tin_tran = io_in_bits_1_bits_op == 7'h20; // @[VConvCtrl.scala 54:24]
   assign f__io_in_bits_1_bits_tin_wclr = io_in_bits_1_bits_op == 7'h5; // @[VConvCtrl.scala 52:24]
@@ -79271,7 +69713,7 @@
   assign f__io_in_bits_1_bits_tin_bsign = io_in_bits_1_bits_sv_data[31]; // @[VConvCtrl.scala 89:22]
   assign f__io_in_bits_1_bits_m = io_in_bits_1_bits_m; // @[VCmdq.scala 54:28]
   assign f__io_in_bits_2_valid = io_in_bits_2_valid; // @[VCmdq.scala 52:27]
-  assign f__io_in_bits_2_bits_tin_conv = io_in_bits_2_bits_op == 7'h62; // @[VConvCtrl.scala 55:24]
+  assign f__io_in_bits_2_bits_tin_conv = io_in_bits_2_bits_op == 7'h45; // @[VConvCtrl.scala 55:24]
   assign f__io_in_bits_2_bits_tin_init = io_in_bits_2_bits_op == 7'h1f; // @[VConvCtrl.scala 53:24]
   assign f__io_in_bits_2_bits_tin_tran = io_in_bits_2_bits_op == 7'h20; // @[VConvCtrl.scala 54:24]
   assign f__io_in_bits_2_bits_tin_wclr = io_in_bits_2_bits_op == 7'h5; // @[VConvCtrl.scala 52:24]
@@ -79290,7 +69732,7 @@
   assign f__io_in_bits_2_bits_tin_bsign = io_in_bits_2_bits_sv_data[31]; // @[VConvCtrl.scala 89:22]
   assign f__io_in_bits_2_bits_m = io_in_bits_2_bits_m; // @[VCmdq.scala 54:28]
   assign f__io_in_bits_3_valid = io_in_bits_3_valid; // @[VCmdq.scala 52:27]
-  assign f__io_in_bits_3_bits_tin_conv = io_in_bits_3_bits_op == 7'h62; // @[VConvCtrl.scala 55:24]
+  assign f__io_in_bits_3_bits_tin_conv = io_in_bits_3_bits_op == 7'h45; // @[VConvCtrl.scala 55:24]
   assign f__io_in_bits_3_bits_tin_init = io_in_bits_3_bits_op == 7'h1f; // @[VConvCtrl.scala 53:24]
   assign f__io_in_bits_3_bits_tin_tran = io_in_bits_3_bits_op == 7'h20; // @[VConvCtrl.scala 54:24]
   assign f__io_in_bits_3_bits_tin_wclr = io_in_bits_3_bits_op == 7'h5; // @[VConvCtrl.scala 52:24]
@@ -85237,121 +75679,121 @@
   reg  value_tin_last; // @[VCmdq.scala 37:18]
   reg  value_m; // @[VCmdq.scala 37:18]
   reg [4:0] step; // @[VCmdq.scala 42:21]
-  wire  _T = ~valid; // @[VLdSt.scala 119:12]
-  wire  _T_5 = value_tin_op == 7'h4; // @[VLdSt.scala 119:70]
-  wire  _T_8 = ~reset; // @[VLdSt.scala 119:11]
-  wire [7:0] fmaxvlb = _T_5 ? 8'h8 : 8'h20; // @[VLdSt.scala 125:22]
-  wire  _outlast1_T = ~value_m; // @[VLdSt.scala 127:20]
-  wire  _outlast1_T_1 = step == 5'h2; // @[VLdSt.scala 127:31]
-  wire  outlast1 = ~value_m | step == 5'h2; // @[VLdSt.scala 127:23]
-  wire  outlast2 = value_m ? step == 5'he : _outlast1_T_1; // @[VLdSt.scala 128:23]
-  wire  outlast = _T_5 ? outlast2 : outlast1; // @[VLdSt.scala 129:22]
-  wire  _last1_T_1 = step == 5'h3; // @[VLdSt.scala 131:28]
-  wire  last1 = _outlast1_T | step == 5'h3; // @[VLdSt.scala 131:20]
-  wire  last2 = value_m ? step == 5'hf : _last1_T_1; // @[VLdSt.scala 132:20]
-  wire  last = _T_5 ? last2 : last1; // @[VLdSt.scala 133:19]
-  wire  _out_vd_addr_T_2 = _T_5 & step[1:0] != 2'h3; // @[VLdSt.scala 137:29]
-  wire [5:0] _out_vd_addr_T_4 = value_tin_vd_addr + 6'h1; // @[VLdSt.scala 137:74]
-  wire [5:0] tin_vd_addr = _T_5 & step[1:0] != 2'h3 ? value_tin_vd_addr : _out_vd_addr_T_4; // @[VLdSt.scala 137:23]
-  wire [5:0] _out_vs_addr_T_4 = value_tin_vs_addr + 6'h1; // @[VLdSt.scala 138:74]
-  wire [5:0] tin_vs_addr = _out_vd_addr_T_2 ? value_tin_vs_addr : _out_vs_addr_T_4; // @[VLdSt.scala 138:23]
-  wire [31:0] tin_addr = value_tin_addr + value_tin_offset; // @[VLdSt.scala 140:27]
-  wire [7:0] _out_remain_T_2 = value_tin_remain - fmaxvlb; // @[VLdSt.scala 141:60]
-  wire [7:0] tin_remain = value_tin_remain <= fmaxvlb ? 8'h0 : _out_remain_T_2; // @[VLdSt.scala 141:22]
-  wire [4:0] _out_quad_T_2 = step + 5'h1; // @[VLdSt.scala 145:46]
-  wire [4:0] _out_quad_T_3 = _T_5 ? _out_quad_T_2 : 5'h0; // @[VLdSt.scala 145:20]
-  wire  f_io_in_bits_0_bits_tin_stride = io_in_bits_0_bits_f2[1]; // @[VLdSt.scala 85:23]
-  wire  f_io_in_bits_0_bits_tin_length = io_in_bits_0_bits_f2[0]; // @[VLdSt.scala 86:23]
+  wire  _T = ~valid; // @[VLdSt.scala 122:12]
+  wire  _T_5 = value_tin_op == 7'h4; // @[VLdSt.scala 122:70]
+  wire  _T_8 = ~reset; // @[VLdSt.scala 122:11]
+  wire [7:0] fmaxvlb = _T_5 ? 8'h8 : 8'h20; // @[VLdSt.scala 128:22]
+  wire  _outlast1_T = ~value_m; // @[VLdSt.scala 130:20]
+  wire  _outlast1_T_1 = step == 5'h2; // @[VLdSt.scala 130:31]
+  wire  outlast1 = ~value_m | step == 5'h2; // @[VLdSt.scala 130:23]
+  wire  outlast2 = value_m ? step == 5'he : _outlast1_T_1; // @[VLdSt.scala 131:23]
+  wire  outlast = _T_5 ? outlast2 : outlast1; // @[VLdSt.scala 132:22]
+  wire  _last1_T_1 = step == 5'h3; // @[VLdSt.scala 134:28]
+  wire  last1 = _outlast1_T | step == 5'h3; // @[VLdSt.scala 134:20]
+  wire  last2 = value_m ? step == 5'hf : _last1_T_1; // @[VLdSt.scala 135:20]
+  wire  last = _T_5 ? last2 : last1; // @[VLdSt.scala 136:19]
+  wire  _out_vd_addr_T_2 = _T_5 & step[1:0] != 2'h3; // @[VLdSt.scala 140:29]
+  wire [5:0] _out_vd_addr_T_4 = value_tin_vd_addr + 6'h1; // @[VLdSt.scala 140:74]
+  wire [5:0] tin_vd_addr = _T_5 & step[1:0] != 2'h3 ? value_tin_vd_addr : _out_vd_addr_T_4; // @[VLdSt.scala 140:23]
+  wire [5:0] _out_vs_addr_T_4 = value_tin_vs_addr + 6'h1; // @[VLdSt.scala 141:74]
+  wire [5:0] tin_vs_addr = _out_vd_addr_T_2 ? value_tin_vs_addr : _out_vs_addr_T_4; // @[VLdSt.scala 141:23]
+  wire [31:0] tin_addr = value_tin_addr + value_tin_offset; // @[VLdSt.scala 143:27]
+  wire [7:0] _out_remain_T_2 = value_tin_remain - fmaxvlb; // @[VLdSt.scala 144:60]
+  wire [7:0] tin_remain = value_tin_remain <= fmaxvlb ? 8'h0 : _out_remain_T_2; // @[VLdSt.scala 144:22]
+  wire [4:0] _out_quad_T_2 = step + 5'h1; // @[VLdSt.scala 148:46]
+  wire [4:0] _out_quad_T_3 = _T_5 ? _out_quad_T_2 : 5'h0; // @[VLdSt.scala 148:20]
+  wire  f_io_in_bits_0_bits_tin_stride = io_in_bits_0_bits_f2[1]; // @[VLdSt.scala 88:23]
+  wire  f_io_in_bits_0_bits_tin_length = io_in_bits_0_bits_f2[0]; // @[VLdSt.scala 89:23]
   wire [1:0] _f_io_in_bits_0_bits_tin_T_3 = io_in_bits_0_bits_sz[1] + io_in_bits_0_bits_sz[2]; // @[Bitwise.scala 48:55]
   wire [1:0] _GEN_63 = {{1'd0}, io_in_bits_0_bits_sz[0]}; // @[Bitwise.scala 48:55]
   wire [2:0] _f_io_in_bits_0_bits_tin_T_5 = _GEN_63 + _f_io_in_bits_0_bits_tin_T_3; // @[Bitwise.scala 48:55]
-  wire  _f_io_in_bits_0_bits_tin_T_13 = io_in_bits_0_bits_vd_valid | ~io_in_bits_0_bits_vs_valid; // @[VLdSt.scala 88:50]
-  wire  _f_io_in_bits_0_bits_tin_T_19 = io_in_bits_0_bits_op == 7'h4; // @[VLdSt.scala 89:20]
-  wire [7:0] f_io_in_bits_0_bits_tin_limit = io_in_bits_0_bits_m ? 8'h80 : 8'h20; // @[VLdSt.scala 92:20]
+  wire  _f_io_in_bits_0_bits_tin_T_13 = io_in_bits_0_bits_vd_valid | ~io_in_bits_0_bits_vs_valid; // @[VLdSt.scala 91:50]
+  wire  _f_io_in_bits_0_bits_tin_T_19 = io_in_bits_0_bits_op == 7'h4; // @[VLdSt.scala 92:20]
+  wire [7:0] f_io_in_bits_0_bits_tin_limit = io_in_bits_0_bits_m ? 8'h80 : 8'h20; // @[VLdSt.scala 95:20]
   wire [31:0] _f_io_in_bits_0_bits_tin_data_T_1 = io_in_bits_0_bits_sz[0] ? io_in_bits_0_bits_sv_data : 32'h0; // @[Library.scala 8:8]
   wire [32:0] _f_io_in_bits_0_bits_tin_data_T_3 = {io_in_bits_0_bits_sv_data,1'h0}; // @[Cat.scala 31:58]
   wire [32:0] _f_io_in_bits_0_bits_tin_data_T_4 = io_in_bits_0_bits_sz[1] ? _f_io_in_bits_0_bits_tin_data_T_3 : 33'h0; // @[Library.scala 8:8]
-  wire [32:0] _GEN_64 = {{1'd0}, _f_io_in_bits_0_bits_tin_data_T_1}; // @[VLdSt.scala 94:44]
-  wire [32:0] _f_io_in_bits_0_bits_tin_data_T_5 = _GEN_64 | _f_io_in_bits_0_bits_tin_data_T_4; // @[VLdSt.scala 94:44]
+  wire [32:0] _GEN_64 = {{1'd0}, _f_io_in_bits_0_bits_tin_data_T_1}; // @[VLdSt.scala 97:44]
+  wire [32:0] _f_io_in_bits_0_bits_tin_data_T_5 = _GEN_64 | _f_io_in_bits_0_bits_tin_data_T_4; // @[VLdSt.scala 97:44]
   wire [33:0] _f_io_in_bits_0_bits_tin_data_T_7 = {io_in_bits_0_bits_sv_data,2'h0}; // @[Cat.scala 31:58]
   wire [33:0] _f_io_in_bits_0_bits_tin_data_T_8 = io_in_bits_0_bits_sz[2] ? _f_io_in_bits_0_bits_tin_data_T_7 : 34'h0; // @[Library.scala 8:8]
-  wire [33:0] _GEN_65 = {{1'd0}, _f_io_in_bits_0_bits_tin_data_T_5}; // @[VLdSt.scala 95:59]
-  wire [33:0] f_io_in_bits_0_bits_tin_data = _GEN_65 | _f_io_in_bits_0_bits_tin_data_T_8; // @[VLdSt.scala 95:59]
-  wire [33:0] _GEN_66 = {{26'd0}, f_io_in_bits_0_bits_tin_limit}; // @[VLdSt.scala 99:28]
+  wire [33:0] _GEN_65 = {{1'd0}, _f_io_in_bits_0_bits_tin_data_T_5}; // @[VLdSt.scala 98:59]
+  wire [33:0] f_io_in_bits_0_bits_tin_data = _GEN_65 | _f_io_in_bits_0_bits_tin_data_T_8; // @[VLdSt.scala 98:59]
+  wire [33:0] _GEN_66 = {{26'd0}, f_io_in_bits_0_bits_tin_limit}; // @[VLdSt.scala 102:28]
   wire [33:0] _f_io_in_bits_0_bits_tin_remain1_T_1 = f_io_in_bits_0_bits_tin_data > _GEN_66 ? {{26'd0},
-    f_io_in_bits_0_bits_tin_limit} : f_io_in_bits_0_bits_tin_data; // @[VLdSt.scala 99:22]
-  wire [7:0] f_io_in_bits_0_bits_tin_remain1 = _f_io_in_bits_0_bits_tin_remain1_T_1[7:0]; // @[VLdSt.scala 99:49]
-  wire [7:0] _f_io_in_bits_0_bits_tin_out_offset_T_3 = _f_io_in_bits_0_bits_tin_T_19 ? 8'h8 : 8'h20; // @[VLdSt.scala 107:46]
-  wire  f_io_in_bits_1_bits_tin_stride = io_in_bits_1_bits_f2[1]; // @[VLdSt.scala 85:23]
-  wire  f_io_in_bits_1_bits_tin_length = io_in_bits_1_bits_f2[0]; // @[VLdSt.scala 86:23]
+    f_io_in_bits_0_bits_tin_limit} : f_io_in_bits_0_bits_tin_data; // @[VLdSt.scala 102:22]
+  wire [7:0] f_io_in_bits_0_bits_tin_remain1 = _f_io_in_bits_0_bits_tin_remain1_T_1[7:0]; // @[VLdSt.scala 102:49]
+  wire [7:0] _f_io_in_bits_0_bits_tin_out_offset_T_3 = _f_io_in_bits_0_bits_tin_T_19 ? 8'h8 : 8'h20; // @[VLdSt.scala 110:46]
+  wire  f_io_in_bits_1_bits_tin_stride = io_in_bits_1_bits_f2[1]; // @[VLdSt.scala 88:23]
+  wire  f_io_in_bits_1_bits_tin_length = io_in_bits_1_bits_f2[0]; // @[VLdSt.scala 89:23]
   wire [1:0] _f_io_in_bits_1_bits_tin_T_3 = io_in_bits_1_bits_sz[1] + io_in_bits_1_bits_sz[2]; // @[Bitwise.scala 48:55]
   wire [1:0] _GEN_67 = {{1'd0}, io_in_bits_1_bits_sz[0]}; // @[Bitwise.scala 48:55]
   wire [2:0] _f_io_in_bits_1_bits_tin_T_5 = _GEN_67 + _f_io_in_bits_1_bits_tin_T_3; // @[Bitwise.scala 48:55]
-  wire  _f_io_in_bits_1_bits_tin_T_13 = io_in_bits_1_bits_vd_valid | ~io_in_bits_1_bits_vs_valid; // @[VLdSt.scala 88:50]
-  wire  _f_io_in_bits_1_bits_tin_T_19 = io_in_bits_1_bits_op == 7'h4; // @[VLdSt.scala 89:20]
-  wire [7:0] f_io_in_bits_1_bits_tin_limit = io_in_bits_1_bits_m ? 8'h80 : 8'h20; // @[VLdSt.scala 92:20]
+  wire  _f_io_in_bits_1_bits_tin_T_13 = io_in_bits_1_bits_vd_valid | ~io_in_bits_1_bits_vs_valid; // @[VLdSt.scala 91:50]
+  wire  _f_io_in_bits_1_bits_tin_T_19 = io_in_bits_1_bits_op == 7'h4; // @[VLdSt.scala 92:20]
+  wire [7:0] f_io_in_bits_1_bits_tin_limit = io_in_bits_1_bits_m ? 8'h80 : 8'h20; // @[VLdSt.scala 95:20]
   wire [31:0] _f_io_in_bits_1_bits_tin_data_T_1 = io_in_bits_1_bits_sz[0] ? io_in_bits_1_bits_sv_data : 32'h0; // @[Library.scala 8:8]
   wire [32:0] _f_io_in_bits_1_bits_tin_data_T_3 = {io_in_bits_1_bits_sv_data,1'h0}; // @[Cat.scala 31:58]
   wire [32:0] _f_io_in_bits_1_bits_tin_data_T_4 = io_in_bits_1_bits_sz[1] ? _f_io_in_bits_1_bits_tin_data_T_3 : 33'h0; // @[Library.scala 8:8]
-  wire [32:0] _GEN_68 = {{1'd0}, _f_io_in_bits_1_bits_tin_data_T_1}; // @[VLdSt.scala 94:44]
-  wire [32:0] _f_io_in_bits_1_bits_tin_data_T_5 = _GEN_68 | _f_io_in_bits_1_bits_tin_data_T_4; // @[VLdSt.scala 94:44]
+  wire [32:0] _GEN_68 = {{1'd0}, _f_io_in_bits_1_bits_tin_data_T_1}; // @[VLdSt.scala 97:44]
+  wire [32:0] _f_io_in_bits_1_bits_tin_data_T_5 = _GEN_68 | _f_io_in_bits_1_bits_tin_data_T_4; // @[VLdSt.scala 97:44]
   wire [33:0] _f_io_in_bits_1_bits_tin_data_T_7 = {io_in_bits_1_bits_sv_data,2'h0}; // @[Cat.scala 31:58]
   wire [33:0] _f_io_in_bits_1_bits_tin_data_T_8 = io_in_bits_1_bits_sz[2] ? _f_io_in_bits_1_bits_tin_data_T_7 : 34'h0; // @[Library.scala 8:8]
-  wire [33:0] _GEN_69 = {{1'd0}, _f_io_in_bits_1_bits_tin_data_T_5}; // @[VLdSt.scala 95:59]
-  wire [33:0] f_io_in_bits_1_bits_tin_data = _GEN_69 | _f_io_in_bits_1_bits_tin_data_T_8; // @[VLdSt.scala 95:59]
-  wire [33:0] _GEN_70 = {{26'd0}, f_io_in_bits_1_bits_tin_limit}; // @[VLdSt.scala 99:28]
+  wire [33:0] _GEN_69 = {{1'd0}, _f_io_in_bits_1_bits_tin_data_T_5}; // @[VLdSt.scala 98:59]
+  wire [33:0] f_io_in_bits_1_bits_tin_data = _GEN_69 | _f_io_in_bits_1_bits_tin_data_T_8; // @[VLdSt.scala 98:59]
+  wire [33:0] _GEN_70 = {{26'd0}, f_io_in_bits_1_bits_tin_limit}; // @[VLdSt.scala 102:28]
   wire [33:0] _f_io_in_bits_1_bits_tin_remain1_T_1 = f_io_in_bits_1_bits_tin_data > _GEN_70 ? {{26'd0},
-    f_io_in_bits_1_bits_tin_limit} : f_io_in_bits_1_bits_tin_data; // @[VLdSt.scala 99:22]
-  wire [7:0] f_io_in_bits_1_bits_tin_remain1 = _f_io_in_bits_1_bits_tin_remain1_T_1[7:0]; // @[VLdSt.scala 99:49]
-  wire [7:0] _f_io_in_bits_1_bits_tin_out_offset_T_3 = _f_io_in_bits_1_bits_tin_T_19 ? 8'h8 : 8'h20; // @[VLdSt.scala 107:46]
-  wire  f_io_in_bits_2_bits_tin_stride = io_in_bits_2_bits_f2[1]; // @[VLdSt.scala 85:23]
-  wire  f_io_in_bits_2_bits_tin_length = io_in_bits_2_bits_f2[0]; // @[VLdSt.scala 86:23]
+    f_io_in_bits_1_bits_tin_limit} : f_io_in_bits_1_bits_tin_data; // @[VLdSt.scala 102:22]
+  wire [7:0] f_io_in_bits_1_bits_tin_remain1 = _f_io_in_bits_1_bits_tin_remain1_T_1[7:0]; // @[VLdSt.scala 102:49]
+  wire [7:0] _f_io_in_bits_1_bits_tin_out_offset_T_3 = _f_io_in_bits_1_bits_tin_T_19 ? 8'h8 : 8'h20; // @[VLdSt.scala 110:46]
+  wire  f_io_in_bits_2_bits_tin_stride = io_in_bits_2_bits_f2[1]; // @[VLdSt.scala 88:23]
+  wire  f_io_in_bits_2_bits_tin_length = io_in_bits_2_bits_f2[0]; // @[VLdSt.scala 89:23]
   wire [1:0] _f_io_in_bits_2_bits_tin_T_3 = io_in_bits_2_bits_sz[1] + io_in_bits_2_bits_sz[2]; // @[Bitwise.scala 48:55]
   wire [1:0] _GEN_71 = {{1'd0}, io_in_bits_2_bits_sz[0]}; // @[Bitwise.scala 48:55]
   wire [2:0] _f_io_in_bits_2_bits_tin_T_5 = _GEN_71 + _f_io_in_bits_2_bits_tin_T_3; // @[Bitwise.scala 48:55]
-  wire  _f_io_in_bits_2_bits_tin_T_13 = io_in_bits_2_bits_vd_valid | ~io_in_bits_2_bits_vs_valid; // @[VLdSt.scala 88:50]
-  wire  _f_io_in_bits_2_bits_tin_T_19 = io_in_bits_2_bits_op == 7'h4; // @[VLdSt.scala 89:20]
-  wire [7:0] f_io_in_bits_2_bits_tin_limit = io_in_bits_2_bits_m ? 8'h80 : 8'h20; // @[VLdSt.scala 92:20]
+  wire  _f_io_in_bits_2_bits_tin_T_13 = io_in_bits_2_bits_vd_valid | ~io_in_bits_2_bits_vs_valid; // @[VLdSt.scala 91:50]
+  wire  _f_io_in_bits_2_bits_tin_T_19 = io_in_bits_2_bits_op == 7'h4; // @[VLdSt.scala 92:20]
+  wire [7:0] f_io_in_bits_2_bits_tin_limit = io_in_bits_2_bits_m ? 8'h80 : 8'h20; // @[VLdSt.scala 95:20]
   wire [31:0] _f_io_in_bits_2_bits_tin_data_T_1 = io_in_bits_2_bits_sz[0] ? io_in_bits_2_bits_sv_data : 32'h0; // @[Library.scala 8:8]
   wire [32:0] _f_io_in_bits_2_bits_tin_data_T_3 = {io_in_bits_2_bits_sv_data,1'h0}; // @[Cat.scala 31:58]
   wire [32:0] _f_io_in_bits_2_bits_tin_data_T_4 = io_in_bits_2_bits_sz[1] ? _f_io_in_bits_2_bits_tin_data_T_3 : 33'h0; // @[Library.scala 8:8]
-  wire [32:0] _GEN_72 = {{1'd0}, _f_io_in_bits_2_bits_tin_data_T_1}; // @[VLdSt.scala 94:44]
-  wire [32:0] _f_io_in_bits_2_bits_tin_data_T_5 = _GEN_72 | _f_io_in_bits_2_bits_tin_data_T_4; // @[VLdSt.scala 94:44]
+  wire [32:0] _GEN_72 = {{1'd0}, _f_io_in_bits_2_bits_tin_data_T_1}; // @[VLdSt.scala 97:44]
+  wire [32:0] _f_io_in_bits_2_bits_tin_data_T_5 = _GEN_72 | _f_io_in_bits_2_bits_tin_data_T_4; // @[VLdSt.scala 97:44]
   wire [33:0] _f_io_in_bits_2_bits_tin_data_T_7 = {io_in_bits_2_bits_sv_data,2'h0}; // @[Cat.scala 31:58]
   wire [33:0] _f_io_in_bits_2_bits_tin_data_T_8 = io_in_bits_2_bits_sz[2] ? _f_io_in_bits_2_bits_tin_data_T_7 : 34'h0; // @[Library.scala 8:8]
-  wire [33:0] _GEN_73 = {{1'd0}, _f_io_in_bits_2_bits_tin_data_T_5}; // @[VLdSt.scala 95:59]
-  wire [33:0] f_io_in_bits_2_bits_tin_data = _GEN_73 | _f_io_in_bits_2_bits_tin_data_T_8; // @[VLdSt.scala 95:59]
-  wire [33:0] _GEN_74 = {{26'd0}, f_io_in_bits_2_bits_tin_limit}; // @[VLdSt.scala 99:28]
+  wire [33:0] _GEN_73 = {{1'd0}, _f_io_in_bits_2_bits_tin_data_T_5}; // @[VLdSt.scala 98:59]
+  wire [33:0] f_io_in_bits_2_bits_tin_data = _GEN_73 | _f_io_in_bits_2_bits_tin_data_T_8; // @[VLdSt.scala 98:59]
+  wire [33:0] _GEN_74 = {{26'd0}, f_io_in_bits_2_bits_tin_limit}; // @[VLdSt.scala 102:28]
   wire [33:0] _f_io_in_bits_2_bits_tin_remain1_T_1 = f_io_in_bits_2_bits_tin_data > _GEN_74 ? {{26'd0},
-    f_io_in_bits_2_bits_tin_limit} : f_io_in_bits_2_bits_tin_data; // @[VLdSt.scala 99:22]
-  wire [7:0] f_io_in_bits_2_bits_tin_remain1 = _f_io_in_bits_2_bits_tin_remain1_T_1[7:0]; // @[VLdSt.scala 99:49]
-  wire [7:0] _f_io_in_bits_2_bits_tin_out_offset_T_3 = _f_io_in_bits_2_bits_tin_T_19 ? 8'h8 : 8'h20; // @[VLdSt.scala 107:46]
-  wire  f_io_in_bits_3_bits_tin_stride = io_in_bits_3_bits_f2[1]; // @[VLdSt.scala 85:23]
-  wire  f_io_in_bits_3_bits_tin_length = io_in_bits_3_bits_f2[0]; // @[VLdSt.scala 86:23]
+    f_io_in_bits_2_bits_tin_limit} : f_io_in_bits_2_bits_tin_data; // @[VLdSt.scala 102:22]
+  wire [7:0] f_io_in_bits_2_bits_tin_remain1 = _f_io_in_bits_2_bits_tin_remain1_T_1[7:0]; // @[VLdSt.scala 102:49]
+  wire [7:0] _f_io_in_bits_2_bits_tin_out_offset_T_3 = _f_io_in_bits_2_bits_tin_T_19 ? 8'h8 : 8'h20; // @[VLdSt.scala 110:46]
+  wire  f_io_in_bits_3_bits_tin_stride = io_in_bits_3_bits_f2[1]; // @[VLdSt.scala 88:23]
+  wire  f_io_in_bits_3_bits_tin_length = io_in_bits_3_bits_f2[0]; // @[VLdSt.scala 89:23]
   wire [1:0] _f_io_in_bits_3_bits_tin_T_3 = io_in_bits_3_bits_sz[1] + io_in_bits_3_bits_sz[2]; // @[Bitwise.scala 48:55]
   wire [1:0] _GEN_75 = {{1'd0}, io_in_bits_3_bits_sz[0]}; // @[Bitwise.scala 48:55]
   wire [2:0] _f_io_in_bits_3_bits_tin_T_5 = _GEN_75 + _f_io_in_bits_3_bits_tin_T_3; // @[Bitwise.scala 48:55]
-  wire  _f_io_in_bits_3_bits_tin_T_13 = io_in_bits_3_bits_vd_valid | ~io_in_bits_3_bits_vs_valid; // @[VLdSt.scala 88:50]
-  wire  _f_io_in_bits_3_bits_tin_T_19 = io_in_bits_3_bits_op == 7'h4; // @[VLdSt.scala 89:20]
-  wire [7:0] f_io_in_bits_3_bits_tin_limit = io_in_bits_3_bits_m ? 8'h80 : 8'h20; // @[VLdSt.scala 92:20]
+  wire  _f_io_in_bits_3_bits_tin_T_13 = io_in_bits_3_bits_vd_valid | ~io_in_bits_3_bits_vs_valid; // @[VLdSt.scala 91:50]
+  wire  _f_io_in_bits_3_bits_tin_T_19 = io_in_bits_3_bits_op == 7'h4; // @[VLdSt.scala 92:20]
+  wire [7:0] f_io_in_bits_3_bits_tin_limit = io_in_bits_3_bits_m ? 8'h80 : 8'h20; // @[VLdSt.scala 95:20]
   wire [31:0] _f_io_in_bits_3_bits_tin_data_T_1 = io_in_bits_3_bits_sz[0] ? io_in_bits_3_bits_sv_data : 32'h0; // @[Library.scala 8:8]
   wire [32:0] _f_io_in_bits_3_bits_tin_data_T_3 = {io_in_bits_3_bits_sv_data,1'h0}; // @[Cat.scala 31:58]
   wire [32:0] _f_io_in_bits_3_bits_tin_data_T_4 = io_in_bits_3_bits_sz[1] ? _f_io_in_bits_3_bits_tin_data_T_3 : 33'h0; // @[Library.scala 8:8]
-  wire [32:0] _GEN_76 = {{1'd0}, _f_io_in_bits_3_bits_tin_data_T_1}; // @[VLdSt.scala 94:44]
-  wire [32:0] _f_io_in_bits_3_bits_tin_data_T_5 = _GEN_76 | _f_io_in_bits_3_bits_tin_data_T_4; // @[VLdSt.scala 94:44]
+  wire [32:0] _GEN_76 = {{1'd0}, _f_io_in_bits_3_bits_tin_data_T_1}; // @[VLdSt.scala 97:44]
+  wire [32:0] _f_io_in_bits_3_bits_tin_data_T_5 = _GEN_76 | _f_io_in_bits_3_bits_tin_data_T_4; // @[VLdSt.scala 97:44]
   wire [33:0] _f_io_in_bits_3_bits_tin_data_T_7 = {io_in_bits_3_bits_sv_data,2'h0}; // @[Cat.scala 31:58]
   wire [33:0] _f_io_in_bits_3_bits_tin_data_T_8 = io_in_bits_3_bits_sz[2] ? _f_io_in_bits_3_bits_tin_data_T_7 : 34'h0; // @[Library.scala 8:8]
-  wire [33:0] _GEN_77 = {{1'd0}, _f_io_in_bits_3_bits_tin_data_T_5}; // @[VLdSt.scala 95:59]
-  wire [33:0] f_io_in_bits_3_bits_tin_data = _GEN_77 | _f_io_in_bits_3_bits_tin_data_T_8; // @[VLdSt.scala 95:59]
-  wire [33:0] _GEN_78 = {{26'd0}, f_io_in_bits_3_bits_tin_limit}; // @[VLdSt.scala 99:28]
+  wire [33:0] _GEN_77 = {{1'd0}, _f_io_in_bits_3_bits_tin_data_T_5}; // @[VLdSt.scala 98:59]
+  wire [33:0] f_io_in_bits_3_bits_tin_data = _GEN_77 | _f_io_in_bits_3_bits_tin_data_T_8; // @[VLdSt.scala 98:59]
+  wire [33:0] _GEN_78 = {{26'd0}, f_io_in_bits_3_bits_tin_limit}; // @[VLdSt.scala 102:28]
   wire [33:0] _f_io_in_bits_3_bits_tin_remain1_T_1 = f_io_in_bits_3_bits_tin_data > _GEN_78 ? {{26'd0},
-    f_io_in_bits_3_bits_tin_limit} : f_io_in_bits_3_bits_tin_data; // @[VLdSt.scala 99:22]
-  wire [7:0] f_io_in_bits_3_bits_tin_remain1 = _f_io_in_bits_3_bits_tin_remain1_T_1[7:0]; // @[VLdSt.scala 99:49]
-  wire [7:0] _f_io_in_bits_3_bits_tin_out_offset_T_3 = _f_io_in_bits_3_bits_tin_T_19 ? 8'h8 : 8'h20; // @[VLdSt.scala 107:46]
+    f_io_in_bits_3_bits_tin_limit} : f_io_in_bits_3_bits_tin_data; // @[VLdSt.scala 102:22]
+  wire [7:0] f_io_in_bits_3_bits_tin_remain1 = _f_io_in_bits_3_bits_tin_remain1_T_1[7:0]; // @[VLdSt.scala 102:49]
+  wire [7:0] _f_io_in_bits_3_bits_tin_out_offset_T_3 = _f_io_in_bits_3_bits_tin_T_19 ? 8'h8 : 8'h20; // @[VLdSt.scala 110:46]
   wire  _T_11 = io_out_valid & io_out_ready; // @[VCmdq.scala 65:29]
   wire  _T_12 = ~last; // @[VCmdq.scala 66:11]
   wire  _GEN_1 = ~last & outlast; // @[VCmdq.scala 66:18 68:17 74:17]
-  wire [1:0] tin_quad = _out_quad_T_3[1:0]; // @[VLdSt.scala 121:19 145:14]
+  wire [1:0] tin_quad = _out_quad_T_3[1:0]; // @[VLdSt.scala 124:19 148:14]
   wire  _GEN_5 = ~last & value_tin_vs_valid; // @[VCmdq.scala 66:18 68:17 74:17]
   wire  _GEN_14 = ~last & value_m; // @[VCmdq.scala 66:18 69:15 75:15]
   wire  _GEN_16 = io_out_valid & io_out_ready ? _T_12 : valid; // @[VCmdq.scala 35:22 65:46]
@@ -86225,7 +76667,7 @@
   wire [63:0] active_active_11 = f_io_entry_7_valid ? active_active_active_11 : 64'h0; // @[Library.scala 8:8]
   wire [63:0] _active_T_18 = _active_T_17 | active_active_11; // @[VCmdq.scala 91:24]
   wire [5:0] _active_active0_T = {{1'd0}, step}; // @[VCmdq.scala 94:48]
-  wire [2:0] active_active0_stepq = _T_5 ? _active_active0_T[4:2] : _active_active0_T[2:0]; // @[VLdSt.scala 153:20]
+  wire [2:0] active_active0_stepq = _T_5 ? _active_active0_T[4:2] : _active_active0_T[2:0]; // @[VLdSt.scala 156:20]
   wire [3:0] active_active0_active_oh_shiftAmount = value_tin_vs_addr[5:2]; // @[VCommon.scala 13:27]
   wire [15:0] active_active0_active_oh = 16'h1 << active_active0_active_oh_shiftAmount; // @[OneHot.scala 64:12]
   wire [15:0] active_active0_active_oh0_lo_lo = {3'h0,active_active0_active_oh[3],3'h0,active_active0_active_oh[2],3'h0,
@@ -86300,7 +76742,7 @@
     ; // @[Library.scala 18:8]
   wire [63:0] active_active0_active_active = _active_active0_active_active_T_22 | _active_active0_active_active_T_29; // @[VCommon.scala 93:68]
   wire [63:0] active_active0 = value_tin_vs_valid ? active_active0_active_active : 64'h0; // @[Library.scala 8:8]
-  wire [2:0] active_active1_stepq = _T_5 ? _out_quad_T_2[4:2] : _out_quad_T_2[2:0]; // @[VLdSt.scala 153:20]
+  wire [2:0] active_active1_stepq = _T_5 ? _out_quad_T_2[4:2] : _out_quad_T_2[2:0]; // @[VLdSt.scala 156:20]
   wire  _active_active1_active_active_T_5 = _outlast1_T & active_active0_active_idx == 2'h0 | value_m &
     active_active1_stepq <= 3'h0; // @[VCommon.scala 91:42]
   wire [63:0] _active_active1_active_active_T_6 = _active_active1_active_active_T_5 ? active_active0_active_oh0 : 64'h0; // @[Library.scala 18:8]
@@ -86439,52 +76881,52 @@
   assign f_reset = reset;
   assign f_io_in_valid = io_in_valid; // @[VCmdq.scala 48:17]
   assign f_io_in_bits_0_valid = io_in_bits_0_valid; // @[VCmdq.scala 52:27]
-  assign f_io_in_bits_0_bits_tin_op = io_in_bits_0_bits_op; // @[VLdSt.scala 103:12 84:19]
-  assign f_io_in_bits_0_bits_tin_addr = io_in_bits_0_bits_sv_addr; // @[VLdSt.scala 106:14 84:19]
+  assign f_io_in_bits_0_bits_tin_op = io_in_bits_0_bits_op; // @[VLdSt.scala 106:12 87:19]
+  assign f_io_in_bits_0_bits_tin_addr = io_in_bits_0_bits_sv_addr; // @[VLdSt.scala 109:14 87:19]
   assign f_io_in_bits_0_bits_tin_offset = f_io_in_bits_0_bits_tin_stride ? f_io_in_bits_0_bits_tin_data[31:0] : {{24
-    'd0}, _f_io_in_bits_0_bits_tin_out_offset_T_3}; // @[VLdSt.scala 107:22]
-  assign f_io_in_bits_0_bits_tin_remain = f_io_in_bits_0_bits_tin_length ? f_io_in_bits_0_bits_tin_remain1 : 8'h80; // @[VLdSt.scala 108:22]
-  assign f_io_in_bits_0_bits_tin_vd_addr = io_in_bits_0_bits_vd_addr; // @[VLdSt.scala 109:12 84:19]
-  assign f_io_in_bits_0_bits_tin_vs_valid = io_in_bits_0_bits_vs_valid; // @[VLdSt.scala 110:12 84:19]
-  assign f_io_in_bits_0_bits_tin_vs_addr = io_in_bits_0_bits_vs_addr; // @[VLdSt.scala 110:12 84:19]
-  assign f_io_in_bits_0_bits_tin_vs_tag = io_in_bits_0_bits_vs_tag; // @[VLdSt.scala 110:12 84:19]
-  assign f_io_in_bits_0_bits_tin_last = ~io_in_bits_0_bits_m & io_in_bits_0_bits_op != 7'h4; // @[VLdSt.scala 111:23]
+    'd0}, _f_io_in_bits_0_bits_tin_out_offset_T_3}; // @[VLdSt.scala 110:22]
+  assign f_io_in_bits_0_bits_tin_remain = f_io_in_bits_0_bits_tin_length ? f_io_in_bits_0_bits_tin_remain1 : 8'h80; // @[VLdSt.scala 111:22]
+  assign f_io_in_bits_0_bits_tin_vd_addr = io_in_bits_0_bits_vd_addr; // @[VLdSt.scala 112:12 87:19]
+  assign f_io_in_bits_0_bits_tin_vs_valid = io_in_bits_0_bits_vs_valid; // @[VLdSt.scala 113:12 87:19]
+  assign f_io_in_bits_0_bits_tin_vs_addr = io_in_bits_0_bits_vs_addr; // @[VLdSt.scala 113:12 87:19]
+  assign f_io_in_bits_0_bits_tin_vs_tag = io_in_bits_0_bits_vs_tag; // @[VLdSt.scala 113:12 87:19]
+  assign f_io_in_bits_0_bits_tin_last = ~io_in_bits_0_bits_m & io_in_bits_0_bits_op != 7'h4; // @[VLdSt.scala 114:23]
   assign f_io_in_bits_0_bits_m = io_in_bits_0_bits_m; // @[VCmdq.scala 54:28]
   assign f_io_in_bits_1_valid = io_in_bits_1_valid; // @[VCmdq.scala 52:27]
-  assign f_io_in_bits_1_bits_tin_op = io_in_bits_1_bits_op; // @[VLdSt.scala 103:12 84:19]
-  assign f_io_in_bits_1_bits_tin_addr = io_in_bits_1_bits_sv_addr; // @[VLdSt.scala 106:14 84:19]
+  assign f_io_in_bits_1_bits_tin_op = io_in_bits_1_bits_op; // @[VLdSt.scala 106:12 87:19]
+  assign f_io_in_bits_1_bits_tin_addr = io_in_bits_1_bits_sv_addr; // @[VLdSt.scala 109:14 87:19]
   assign f_io_in_bits_1_bits_tin_offset = f_io_in_bits_1_bits_tin_stride ? f_io_in_bits_1_bits_tin_data[31:0] : {{24
-    'd0}, _f_io_in_bits_1_bits_tin_out_offset_T_3}; // @[VLdSt.scala 107:22]
-  assign f_io_in_bits_1_bits_tin_remain = f_io_in_bits_1_bits_tin_length ? f_io_in_bits_1_bits_tin_remain1 : 8'h80; // @[VLdSt.scala 108:22]
-  assign f_io_in_bits_1_bits_tin_vd_addr = io_in_bits_1_bits_vd_addr; // @[VLdSt.scala 109:12 84:19]
-  assign f_io_in_bits_1_bits_tin_vs_valid = io_in_bits_1_bits_vs_valid; // @[VLdSt.scala 110:12 84:19]
-  assign f_io_in_bits_1_bits_tin_vs_addr = io_in_bits_1_bits_vs_addr; // @[VLdSt.scala 110:12 84:19]
-  assign f_io_in_bits_1_bits_tin_vs_tag = io_in_bits_1_bits_vs_tag; // @[VLdSt.scala 110:12 84:19]
-  assign f_io_in_bits_1_bits_tin_last = ~io_in_bits_1_bits_m & io_in_bits_1_bits_op != 7'h4; // @[VLdSt.scala 111:23]
+    'd0}, _f_io_in_bits_1_bits_tin_out_offset_T_3}; // @[VLdSt.scala 110:22]
+  assign f_io_in_bits_1_bits_tin_remain = f_io_in_bits_1_bits_tin_length ? f_io_in_bits_1_bits_tin_remain1 : 8'h80; // @[VLdSt.scala 111:22]
+  assign f_io_in_bits_1_bits_tin_vd_addr = io_in_bits_1_bits_vd_addr; // @[VLdSt.scala 112:12 87:19]
+  assign f_io_in_bits_1_bits_tin_vs_valid = io_in_bits_1_bits_vs_valid; // @[VLdSt.scala 113:12 87:19]
+  assign f_io_in_bits_1_bits_tin_vs_addr = io_in_bits_1_bits_vs_addr; // @[VLdSt.scala 113:12 87:19]
+  assign f_io_in_bits_1_bits_tin_vs_tag = io_in_bits_1_bits_vs_tag; // @[VLdSt.scala 113:12 87:19]
+  assign f_io_in_bits_1_bits_tin_last = ~io_in_bits_1_bits_m & io_in_bits_1_bits_op != 7'h4; // @[VLdSt.scala 114:23]
   assign f_io_in_bits_1_bits_m = io_in_bits_1_bits_m; // @[VCmdq.scala 54:28]
   assign f_io_in_bits_2_valid = io_in_bits_2_valid; // @[VCmdq.scala 52:27]
-  assign f_io_in_bits_2_bits_tin_op = io_in_bits_2_bits_op; // @[VLdSt.scala 103:12 84:19]
-  assign f_io_in_bits_2_bits_tin_addr = io_in_bits_2_bits_sv_addr; // @[VLdSt.scala 106:14 84:19]
+  assign f_io_in_bits_2_bits_tin_op = io_in_bits_2_bits_op; // @[VLdSt.scala 106:12 87:19]
+  assign f_io_in_bits_2_bits_tin_addr = io_in_bits_2_bits_sv_addr; // @[VLdSt.scala 109:14 87:19]
   assign f_io_in_bits_2_bits_tin_offset = f_io_in_bits_2_bits_tin_stride ? f_io_in_bits_2_bits_tin_data[31:0] : {{24
-    'd0}, _f_io_in_bits_2_bits_tin_out_offset_T_3}; // @[VLdSt.scala 107:22]
-  assign f_io_in_bits_2_bits_tin_remain = f_io_in_bits_2_bits_tin_length ? f_io_in_bits_2_bits_tin_remain1 : 8'h80; // @[VLdSt.scala 108:22]
-  assign f_io_in_bits_2_bits_tin_vd_addr = io_in_bits_2_bits_vd_addr; // @[VLdSt.scala 109:12 84:19]
-  assign f_io_in_bits_2_bits_tin_vs_valid = io_in_bits_2_bits_vs_valid; // @[VLdSt.scala 110:12 84:19]
-  assign f_io_in_bits_2_bits_tin_vs_addr = io_in_bits_2_bits_vs_addr; // @[VLdSt.scala 110:12 84:19]
-  assign f_io_in_bits_2_bits_tin_vs_tag = io_in_bits_2_bits_vs_tag; // @[VLdSt.scala 110:12 84:19]
-  assign f_io_in_bits_2_bits_tin_last = ~io_in_bits_2_bits_m & io_in_bits_2_bits_op != 7'h4; // @[VLdSt.scala 111:23]
+    'd0}, _f_io_in_bits_2_bits_tin_out_offset_T_3}; // @[VLdSt.scala 110:22]
+  assign f_io_in_bits_2_bits_tin_remain = f_io_in_bits_2_bits_tin_length ? f_io_in_bits_2_bits_tin_remain1 : 8'h80; // @[VLdSt.scala 111:22]
+  assign f_io_in_bits_2_bits_tin_vd_addr = io_in_bits_2_bits_vd_addr; // @[VLdSt.scala 112:12 87:19]
+  assign f_io_in_bits_2_bits_tin_vs_valid = io_in_bits_2_bits_vs_valid; // @[VLdSt.scala 113:12 87:19]
+  assign f_io_in_bits_2_bits_tin_vs_addr = io_in_bits_2_bits_vs_addr; // @[VLdSt.scala 113:12 87:19]
+  assign f_io_in_bits_2_bits_tin_vs_tag = io_in_bits_2_bits_vs_tag; // @[VLdSt.scala 113:12 87:19]
+  assign f_io_in_bits_2_bits_tin_last = ~io_in_bits_2_bits_m & io_in_bits_2_bits_op != 7'h4; // @[VLdSt.scala 114:23]
   assign f_io_in_bits_2_bits_m = io_in_bits_2_bits_m; // @[VCmdq.scala 54:28]
   assign f_io_in_bits_3_valid = io_in_bits_3_valid; // @[VCmdq.scala 52:27]
-  assign f_io_in_bits_3_bits_tin_op = io_in_bits_3_bits_op; // @[VLdSt.scala 103:12 84:19]
-  assign f_io_in_bits_3_bits_tin_addr = io_in_bits_3_bits_sv_addr; // @[VLdSt.scala 106:14 84:19]
+  assign f_io_in_bits_3_bits_tin_op = io_in_bits_3_bits_op; // @[VLdSt.scala 106:12 87:19]
+  assign f_io_in_bits_3_bits_tin_addr = io_in_bits_3_bits_sv_addr; // @[VLdSt.scala 109:14 87:19]
   assign f_io_in_bits_3_bits_tin_offset = f_io_in_bits_3_bits_tin_stride ? f_io_in_bits_3_bits_tin_data[31:0] : {{24
-    'd0}, _f_io_in_bits_3_bits_tin_out_offset_T_3}; // @[VLdSt.scala 107:22]
-  assign f_io_in_bits_3_bits_tin_remain = f_io_in_bits_3_bits_tin_length ? f_io_in_bits_3_bits_tin_remain1 : 8'h80; // @[VLdSt.scala 108:22]
-  assign f_io_in_bits_3_bits_tin_vd_addr = io_in_bits_3_bits_vd_addr; // @[VLdSt.scala 109:12 84:19]
-  assign f_io_in_bits_3_bits_tin_vs_valid = io_in_bits_3_bits_vs_valid; // @[VLdSt.scala 110:12 84:19]
-  assign f_io_in_bits_3_bits_tin_vs_addr = io_in_bits_3_bits_vs_addr; // @[VLdSt.scala 110:12 84:19]
-  assign f_io_in_bits_3_bits_tin_vs_tag = io_in_bits_3_bits_vs_tag; // @[VLdSt.scala 110:12 84:19]
-  assign f_io_in_bits_3_bits_tin_last = ~io_in_bits_3_bits_m & io_in_bits_3_bits_op != 7'h4; // @[VLdSt.scala 111:23]
+    'd0}, _f_io_in_bits_3_bits_tin_out_offset_T_3}; // @[VLdSt.scala 110:22]
+  assign f_io_in_bits_3_bits_tin_remain = f_io_in_bits_3_bits_tin_length ? f_io_in_bits_3_bits_tin_remain1 : 8'h80; // @[VLdSt.scala 111:22]
+  assign f_io_in_bits_3_bits_tin_vd_addr = io_in_bits_3_bits_vd_addr; // @[VLdSt.scala 112:12 87:19]
+  assign f_io_in_bits_3_bits_tin_vs_valid = io_in_bits_3_bits_vs_valid; // @[VLdSt.scala 113:12 87:19]
+  assign f_io_in_bits_3_bits_tin_vs_addr = io_in_bits_3_bits_vs_addr; // @[VLdSt.scala 113:12 87:19]
+  assign f_io_in_bits_3_bits_tin_vs_tag = io_in_bits_3_bits_vs_tag; // @[VLdSt.scala 113:12 87:19]
+  assign f_io_in_bits_3_bits_tin_last = ~io_in_bits_3_bits_m & io_in_bits_3_bits_op != 7'h4; // @[VLdSt.scala 114:23]
   assign f_io_in_bits_3_bits_m = io_in_bits_3_bits_m; // @[VCmdq.scala 54:28]
   assign f_io_out_ready = _T | io_out_ready & last; // @[VCmdq.scala 57:28]
   always @(posedge clock) begin
@@ -86596,7 +77038,7 @@
       if (`STOP_COND) begin
     `endif
         if (~reset & ~(~valid | value_tin_op == 7'h2 | value_tin_op == 7'h3 | value_tin_op == 7'h4)) begin
-          $fatal; // @[VLdSt.scala 119:11]
+          $fatal; // @[VLdSt.scala 122:11]
         end
     `ifdef STOP_COND
       end
@@ -86608,8 +77050,8 @@
     `endif
         if (~reset & ~(~valid | value_tin_op == 7'h2 | value_tin_op == 7'h3 | value_tin_op == 7'h4)) begin
           $fwrite(32'h80000002,
-            "Assertion failed\n    at VLdSt.scala:119 assert(!valid || in.op === e.vld.U || in.op === e.vst.U || in.op === e.vstq.U)\n"
-            ); // @[VLdSt.scala 119:11]
+            "Assertion failed\n    at VLdSt.scala:122 assert(!valid || in.op === e.vld.U || in.op === e.vst.U || in.op === e.vstq.U)\n"
+            ); // @[VLdSt.scala 122:11]
         end
     `ifdef PRINTF_COND
       end
@@ -86620,7 +77062,7 @@
       if (`STOP_COND) begin
     `endif
         if (_T_8 & ~(_f_io_in_bits_0_bits_tin_T_5[1:0] <= 2'h1)) begin
-          $fatal; // @[VLdSt.scala 87:11]
+          $fatal; // @[VLdSt.scala 90:11]
         end
     `ifdef STOP_COND
       end
@@ -86631,7 +77073,7 @@
       if (`PRINTF_COND) begin
     `endif
         if (_T_8 & ~(_f_io_in_bits_0_bits_tin_T_5[1:0] <= 2'h1)) begin
-          $fwrite(32'h80000002,"Assertion failed\n    at VLdSt.scala:87 assert(PopCount(in.sz) <= 1.U)\n"); // @[VLdSt.scala 87:11]
+          $fwrite(32'h80000002,"Assertion failed\n    at VLdSt.scala:90 assert(PopCount(in.sz) <= 1.U)\n"); // @[VLdSt.scala 90:11]
         end
     `ifdef PRINTF_COND
       end
@@ -86643,7 +77085,7 @@
     `endif
         if (_T_8 & ~(~(io_in_bits_0_bits_op == 7'h3 & (io_in_bits_0_bits_vd_valid | ~io_in_bits_0_bits_vs_valid)))
           ) begin
-          $fatal; // @[VLdSt.scala 88:11]
+          $fatal; // @[VLdSt.scala 91:11]
         end
     `ifdef STOP_COND
       end
@@ -86656,8 +77098,8 @@
         if (_T_8 & ~(~(io_in_bits_0_bits_op == 7'h3 & (io_in_bits_0_bits_vd_valid | ~io_in_bits_0_bits_vs_valid)))
           ) begin
           $fwrite(32'h80000002,
-            "Assertion failed\n    at VLdSt.scala:88 assert(!(in.op === e.vst.U  && ( in.vd.valid || !in.vs.valid)))\n"
-            ); // @[VLdSt.scala 88:11]
+            "Assertion failed\n    at VLdSt.scala:91 assert(!(in.op === e.vst.U  && ( in.vd.valid || !in.vs.valid)))\n"
+            ); // @[VLdSt.scala 91:11]
         end
     `ifdef PRINTF_COND
       end
@@ -86668,7 +77110,7 @@
       if (`STOP_COND) begin
     `endif
         if (_T_8 & ~(~(io_in_bits_0_bits_op == 7'h4 & _f_io_in_bits_0_bits_tin_T_13))) begin
-          $fatal; // @[VLdSt.scala 89:11]
+          $fatal; // @[VLdSt.scala 92:11]
         end
     `ifdef STOP_COND
       end
@@ -86680,8 +77122,8 @@
     `endif
         if (_T_8 & ~(~(io_in_bits_0_bits_op == 7'h4 & _f_io_in_bits_0_bits_tin_T_13))) begin
           $fwrite(32'h80000002,
-            "Assertion failed\n    at VLdSt.scala:89 assert(!(in.op === e.vstq.U && ( in.vd.valid || !in.vs.valid)))\n"
-            ); // @[VLdSt.scala 89:11]
+            "Assertion failed\n    at VLdSt.scala:92 assert(!(in.op === e.vstq.U && ( in.vd.valid || !in.vs.valid)))\n"
+            ); // @[VLdSt.scala 92:11]
         end
     `ifdef PRINTF_COND
       end
@@ -86693,7 +77135,7 @@
     `endif
         if (_T_8 & ~(~(io_in_bits_0_bits_op == 7'h2 & (~io_in_bits_0_bits_vd_valid | io_in_bits_0_bits_vs_valid)))
           ) begin
-          $fatal; // @[VLdSt.scala 90:11]
+          $fatal; // @[VLdSt.scala 93:11]
         end
     `ifdef STOP_COND
       end
@@ -86706,8 +77148,8 @@
         if (_T_8 & ~(~(io_in_bits_0_bits_op == 7'h2 & (~io_in_bits_0_bits_vd_valid | io_in_bits_0_bits_vs_valid)))
           ) begin
           $fwrite(32'h80000002,
-            "Assertion failed\n    at VLdSt.scala:90 assert(!(in.op === e.vld.U  && (!in.vd.valid ||  in.vs.valid)))\n"
-            ); // @[VLdSt.scala 90:11]
+            "Assertion failed\n    at VLdSt.scala:93 assert(!(in.op === e.vld.U  && (!in.vd.valid ||  in.vs.valid)))\n"
+            ); // @[VLdSt.scala 93:11]
         end
     `ifdef PRINTF_COND
       end
@@ -86718,7 +77160,7 @@
       if (`STOP_COND) begin
     `endif
         if (_T_8 & ~(_f_io_in_bits_1_bits_tin_T_5[1:0] <= 2'h1)) begin
-          $fatal; // @[VLdSt.scala 87:11]
+          $fatal; // @[VLdSt.scala 90:11]
         end
     `ifdef STOP_COND
       end
@@ -86729,7 +77171,7 @@
       if (`PRINTF_COND) begin
     `endif
         if (_T_8 & ~(_f_io_in_bits_1_bits_tin_T_5[1:0] <= 2'h1)) begin
-          $fwrite(32'h80000002,"Assertion failed\n    at VLdSt.scala:87 assert(PopCount(in.sz) <= 1.U)\n"); // @[VLdSt.scala 87:11]
+          $fwrite(32'h80000002,"Assertion failed\n    at VLdSt.scala:90 assert(PopCount(in.sz) <= 1.U)\n"); // @[VLdSt.scala 90:11]
         end
     `ifdef PRINTF_COND
       end
@@ -86741,7 +77183,7 @@
     `endif
         if (_T_8 & ~(~(io_in_bits_1_bits_op == 7'h3 & (io_in_bits_1_bits_vd_valid | ~io_in_bits_1_bits_vs_valid)))
           ) begin
-          $fatal; // @[VLdSt.scala 88:11]
+          $fatal; // @[VLdSt.scala 91:11]
         end
     `ifdef STOP_COND
       end
@@ -86754,8 +77196,8 @@
         if (_T_8 & ~(~(io_in_bits_1_bits_op == 7'h3 & (io_in_bits_1_bits_vd_valid | ~io_in_bits_1_bits_vs_valid)))
           ) begin
           $fwrite(32'h80000002,
-            "Assertion failed\n    at VLdSt.scala:88 assert(!(in.op === e.vst.U  && ( in.vd.valid || !in.vs.valid)))\n"
-            ); // @[VLdSt.scala 88:11]
+            "Assertion failed\n    at VLdSt.scala:91 assert(!(in.op === e.vst.U  && ( in.vd.valid || !in.vs.valid)))\n"
+            ); // @[VLdSt.scala 91:11]
         end
     `ifdef PRINTF_COND
       end
@@ -86766,7 +77208,7 @@
       if (`STOP_COND) begin
     `endif
         if (_T_8 & ~(~(io_in_bits_1_bits_op == 7'h4 & _f_io_in_bits_1_bits_tin_T_13))) begin
-          $fatal; // @[VLdSt.scala 89:11]
+          $fatal; // @[VLdSt.scala 92:11]
         end
     `ifdef STOP_COND
       end
@@ -86778,8 +77220,8 @@
     `endif
         if (_T_8 & ~(~(io_in_bits_1_bits_op == 7'h4 & _f_io_in_bits_1_bits_tin_T_13))) begin
           $fwrite(32'h80000002,
-            "Assertion failed\n    at VLdSt.scala:89 assert(!(in.op === e.vstq.U && ( in.vd.valid || !in.vs.valid)))\n"
-            ); // @[VLdSt.scala 89:11]
+            "Assertion failed\n    at VLdSt.scala:92 assert(!(in.op === e.vstq.U && ( in.vd.valid || !in.vs.valid)))\n"
+            ); // @[VLdSt.scala 92:11]
         end
     `ifdef PRINTF_COND
       end
@@ -86791,7 +77233,7 @@
     `endif
         if (_T_8 & ~(~(io_in_bits_1_bits_op == 7'h2 & (~io_in_bits_1_bits_vd_valid | io_in_bits_1_bits_vs_valid)))
           ) begin
-          $fatal; // @[VLdSt.scala 90:11]
+          $fatal; // @[VLdSt.scala 93:11]
         end
     `ifdef STOP_COND
       end
@@ -86804,8 +77246,8 @@
         if (_T_8 & ~(~(io_in_bits_1_bits_op == 7'h2 & (~io_in_bits_1_bits_vd_valid | io_in_bits_1_bits_vs_valid)))
           ) begin
           $fwrite(32'h80000002,
-            "Assertion failed\n    at VLdSt.scala:90 assert(!(in.op === e.vld.U  && (!in.vd.valid ||  in.vs.valid)))\n"
-            ); // @[VLdSt.scala 90:11]
+            "Assertion failed\n    at VLdSt.scala:93 assert(!(in.op === e.vld.U  && (!in.vd.valid ||  in.vs.valid)))\n"
+            ); // @[VLdSt.scala 93:11]
         end
     `ifdef PRINTF_COND
       end
@@ -86816,7 +77258,7 @@
       if (`STOP_COND) begin
     `endif
         if (_T_8 & ~(_f_io_in_bits_2_bits_tin_T_5[1:0] <= 2'h1)) begin
-          $fatal; // @[VLdSt.scala 87:11]
+          $fatal; // @[VLdSt.scala 90:11]
         end
     `ifdef STOP_COND
       end
@@ -86827,7 +77269,7 @@
       if (`PRINTF_COND) begin
     `endif
         if (_T_8 & ~(_f_io_in_bits_2_bits_tin_T_5[1:0] <= 2'h1)) begin
-          $fwrite(32'h80000002,"Assertion failed\n    at VLdSt.scala:87 assert(PopCount(in.sz) <= 1.U)\n"); // @[VLdSt.scala 87:11]
+          $fwrite(32'h80000002,"Assertion failed\n    at VLdSt.scala:90 assert(PopCount(in.sz) <= 1.U)\n"); // @[VLdSt.scala 90:11]
         end
     `ifdef PRINTF_COND
       end
@@ -86839,7 +77281,7 @@
     `endif
         if (_T_8 & ~(~(io_in_bits_2_bits_op == 7'h3 & (io_in_bits_2_bits_vd_valid | ~io_in_bits_2_bits_vs_valid)))
           ) begin
-          $fatal; // @[VLdSt.scala 88:11]
+          $fatal; // @[VLdSt.scala 91:11]
         end
     `ifdef STOP_COND
       end
@@ -86852,8 +77294,8 @@
         if (_T_8 & ~(~(io_in_bits_2_bits_op == 7'h3 & (io_in_bits_2_bits_vd_valid | ~io_in_bits_2_bits_vs_valid)))
           ) begin
           $fwrite(32'h80000002,
-            "Assertion failed\n    at VLdSt.scala:88 assert(!(in.op === e.vst.U  && ( in.vd.valid || !in.vs.valid)))\n"
-            ); // @[VLdSt.scala 88:11]
+            "Assertion failed\n    at VLdSt.scala:91 assert(!(in.op === e.vst.U  && ( in.vd.valid || !in.vs.valid)))\n"
+            ); // @[VLdSt.scala 91:11]
         end
     `ifdef PRINTF_COND
       end
@@ -86864,7 +77306,7 @@
       if (`STOP_COND) begin
     `endif
         if (_T_8 & ~(~(io_in_bits_2_bits_op == 7'h4 & _f_io_in_bits_2_bits_tin_T_13))) begin
-          $fatal; // @[VLdSt.scala 89:11]
+          $fatal; // @[VLdSt.scala 92:11]
         end
     `ifdef STOP_COND
       end
@@ -86876,8 +77318,8 @@
     `endif
         if (_T_8 & ~(~(io_in_bits_2_bits_op == 7'h4 & _f_io_in_bits_2_bits_tin_T_13))) begin
           $fwrite(32'h80000002,
-            "Assertion failed\n    at VLdSt.scala:89 assert(!(in.op === e.vstq.U && ( in.vd.valid || !in.vs.valid)))\n"
-            ); // @[VLdSt.scala 89:11]
+            "Assertion failed\n    at VLdSt.scala:92 assert(!(in.op === e.vstq.U && ( in.vd.valid || !in.vs.valid)))\n"
+            ); // @[VLdSt.scala 92:11]
         end
     `ifdef PRINTF_COND
       end
@@ -86889,7 +77331,7 @@
     `endif
         if (_T_8 & ~(~(io_in_bits_2_bits_op == 7'h2 & (~io_in_bits_2_bits_vd_valid | io_in_bits_2_bits_vs_valid)))
           ) begin
-          $fatal; // @[VLdSt.scala 90:11]
+          $fatal; // @[VLdSt.scala 93:11]
         end
     `ifdef STOP_COND
       end
@@ -86902,8 +77344,8 @@
         if (_T_8 & ~(~(io_in_bits_2_bits_op == 7'h2 & (~io_in_bits_2_bits_vd_valid | io_in_bits_2_bits_vs_valid)))
           ) begin
           $fwrite(32'h80000002,
-            "Assertion failed\n    at VLdSt.scala:90 assert(!(in.op === e.vld.U  && (!in.vd.valid ||  in.vs.valid)))\n"
-            ); // @[VLdSt.scala 90:11]
+            "Assertion failed\n    at VLdSt.scala:93 assert(!(in.op === e.vld.U  && (!in.vd.valid ||  in.vs.valid)))\n"
+            ); // @[VLdSt.scala 93:11]
         end
     `ifdef PRINTF_COND
       end
@@ -86914,79 +77356,6 @@
       if (`STOP_COND) begin
     `endif
         if (_T_8 & ~(_f_io_in_bits_3_bits_tin_T_5[1:0] <= 2'h1)) begin
-          $fatal; // @[VLdSt.scala 87:11]
-        end
-    `ifdef STOP_COND
-      end
-    `endif
-    `endif // SYNTHESIS
-    `ifndef SYNTHESIS
-    `ifdef PRINTF_COND
-      if (`PRINTF_COND) begin
-    `endif
-        if (_T_8 & ~(_f_io_in_bits_3_bits_tin_T_5[1:0] <= 2'h1)) begin
-          $fwrite(32'h80000002,"Assertion failed\n    at VLdSt.scala:87 assert(PopCount(in.sz) <= 1.U)\n"); // @[VLdSt.scala 87:11]
-        end
-    `ifdef PRINTF_COND
-      end
-    `endif
-    `endif // SYNTHESIS
-    `ifndef SYNTHESIS
-    `ifdef STOP_COND
-      if (`STOP_COND) begin
-    `endif
-        if (_T_8 & ~(~(io_in_bits_3_bits_op == 7'h3 & (io_in_bits_3_bits_vd_valid | ~io_in_bits_3_bits_vs_valid)))
-          ) begin
-          $fatal; // @[VLdSt.scala 88:11]
-        end
-    `ifdef STOP_COND
-      end
-    `endif
-    `endif // SYNTHESIS
-    `ifndef SYNTHESIS
-    `ifdef PRINTF_COND
-      if (`PRINTF_COND) begin
-    `endif
-        if (_T_8 & ~(~(io_in_bits_3_bits_op == 7'h3 & (io_in_bits_3_bits_vd_valid | ~io_in_bits_3_bits_vs_valid)))
-          ) begin
-          $fwrite(32'h80000002,
-            "Assertion failed\n    at VLdSt.scala:88 assert(!(in.op === e.vst.U  && ( in.vd.valid || !in.vs.valid)))\n"
-            ); // @[VLdSt.scala 88:11]
-        end
-    `ifdef PRINTF_COND
-      end
-    `endif
-    `endif // SYNTHESIS
-    `ifndef SYNTHESIS
-    `ifdef STOP_COND
-      if (`STOP_COND) begin
-    `endif
-        if (_T_8 & ~(~(io_in_bits_3_bits_op == 7'h4 & _f_io_in_bits_3_bits_tin_T_13))) begin
-          $fatal; // @[VLdSt.scala 89:11]
-        end
-    `ifdef STOP_COND
-      end
-    `endif
-    `endif // SYNTHESIS
-    `ifndef SYNTHESIS
-    `ifdef PRINTF_COND
-      if (`PRINTF_COND) begin
-    `endif
-        if (_T_8 & ~(~(io_in_bits_3_bits_op == 7'h4 & _f_io_in_bits_3_bits_tin_T_13))) begin
-          $fwrite(32'h80000002,
-            "Assertion failed\n    at VLdSt.scala:89 assert(!(in.op === e.vstq.U && ( in.vd.valid || !in.vs.valid)))\n"
-            ); // @[VLdSt.scala 89:11]
-        end
-    `ifdef PRINTF_COND
-      end
-    `endif
-    `endif // SYNTHESIS
-    `ifndef SYNTHESIS
-    `ifdef STOP_COND
-      if (`STOP_COND) begin
-    `endif
-        if (_T_8 & ~(~(io_in_bits_3_bits_op == 7'h2 & (~io_in_bits_3_bits_vd_valid | io_in_bits_3_bits_vs_valid)))
-          ) begin
           $fatal; // @[VLdSt.scala 90:11]
         end
     `ifdef STOP_COND
@@ -86997,11 +77366,84 @@
     `ifdef PRINTF_COND
       if (`PRINTF_COND) begin
     `endif
+        if (_T_8 & ~(_f_io_in_bits_3_bits_tin_T_5[1:0] <= 2'h1)) begin
+          $fwrite(32'h80000002,"Assertion failed\n    at VLdSt.scala:90 assert(PopCount(in.sz) <= 1.U)\n"); // @[VLdSt.scala 90:11]
+        end
+    `ifdef PRINTF_COND
+      end
+    `endif
+    `endif // SYNTHESIS
+    `ifndef SYNTHESIS
+    `ifdef STOP_COND
+      if (`STOP_COND) begin
+    `endif
+        if (_T_8 & ~(~(io_in_bits_3_bits_op == 7'h3 & (io_in_bits_3_bits_vd_valid | ~io_in_bits_3_bits_vs_valid)))
+          ) begin
+          $fatal; // @[VLdSt.scala 91:11]
+        end
+    `ifdef STOP_COND
+      end
+    `endif
+    `endif // SYNTHESIS
+    `ifndef SYNTHESIS
+    `ifdef PRINTF_COND
+      if (`PRINTF_COND) begin
+    `endif
+        if (_T_8 & ~(~(io_in_bits_3_bits_op == 7'h3 & (io_in_bits_3_bits_vd_valid | ~io_in_bits_3_bits_vs_valid)))
+          ) begin
+          $fwrite(32'h80000002,
+            "Assertion failed\n    at VLdSt.scala:91 assert(!(in.op === e.vst.U  && ( in.vd.valid || !in.vs.valid)))\n"
+            ); // @[VLdSt.scala 91:11]
+        end
+    `ifdef PRINTF_COND
+      end
+    `endif
+    `endif // SYNTHESIS
+    `ifndef SYNTHESIS
+    `ifdef STOP_COND
+      if (`STOP_COND) begin
+    `endif
+        if (_T_8 & ~(~(io_in_bits_3_bits_op == 7'h4 & _f_io_in_bits_3_bits_tin_T_13))) begin
+          $fatal; // @[VLdSt.scala 92:11]
+        end
+    `ifdef STOP_COND
+      end
+    `endif
+    `endif // SYNTHESIS
+    `ifndef SYNTHESIS
+    `ifdef PRINTF_COND
+      if (`PRINTF_COND) begin
+    `endif
+        if (_T_8 & ~(~(io_in_bits_3_bits_op == 7'h4 & _f_io_in_bits_3_bits_tin_T_13))) begin
+          $fwrite(32'h80000002,
+            "Assertion failed\n    at VLdSt.scala:92 assert(!(in.op === e.vstq.U && ( in.vd.valid || !in.vs.valid)))\n"
+            ); // @[VLdSt.scala 92:11]
+        end
+    `ifdef PRINTF_COND
+      end
+    `endif
+    `endif // SYNTHESIS
+    `ifndef SYNTHESIS
+    `ifdef STOP_COND
+      if (`STOP_COND) begin
+    `endif
+        if (_T_8 & ~(~(io_in_bits_3_bits_op == 7'h2 & (~io_in_bits_3_bits_vd_valid | io_in_bits_3_bits_vs_valid)))
+          ) begin
+          $fatal; // @[VLdSt.scala 93:11]
+        end
+    `ifdef STOP_COND
+      end
+    `endif
+    `endif // SYNTHESIS
+    `ifndef SYNTHESIS
+    `ifdef PRINTF_COND
+      if (`PRINTF_COND) begin
+    `endif
         if (_T_8 & ~(~(io_in_bits_3_bits_op == 7'h2 & (~io_in_bits_3_bits_vd_valid | io_in_bits_3_bits_vs_valid)))
           ) begin
           $fwrite(32'h80000002,
-            "Assertion failed\n    at VLdSt.scala:90 assert(!(in.op === e.vld.U  && (!in.vd.valid ||  in.vs.valid)))\n"
-            ); // @[VLdSt.scala 90:11]
+            "Assertion failed\n    at VLdSt.scala:93 assert(!(in.op === e.vld.U  && (!in.vd.valid ||  in.vs.valid)))\n"
+            ); // @[VLdSt.scala 93:11]
         end
     `ifdef PRINTF_COND
       end
@@ -87160,7 +77602,7 @@
 `endif
 `endif // SYNTHESIS
 endmodule
-module Fifo_4(
+module Fifo(
   input         clock,
   input         reset,
   output        io_in_ready,
@@ -87543,7 +77985,7 @@
 `endif
 `endif // SYNTHESIS
 endmodule
-module Fifo_5(
+module Fifo_1(
   input          clock,
   input          reset,
   output         io_in_ready,
@@ -87790,7 +78232,7 @@
 `endif
 `endif // SYNTHESIS
 endmodule
-module Slice_5(
+module Slice_4(
   input        clock,
   input        reset,
   output       io_in_ready,
@@ -87946,7 +78388,7 @@
 `endif
 `endif // SYNTHESIS
 endmodule
-module Slice_6(
+module Slice_5(
   input          clock,
   input          reset,
   output         io_in_ready,
@@ -88242,88 +78684,88 @@
   wire [6:0] q_io_out_ready_idx = {q_io_out_ready_tag,q_io_out_bits_vs_addr}; // @[Cat.scala 31:58]
   wire [127:0] _q_io_out_ready_T_1 = io_vrfsb >> q_io_out_ready_idx; // @[VCommon.scala 122:21]
   wire  _q_io_out_ready_T_4 = ~q_io_out_bits_vs_valid | ~_q_io_out_ready_T_1[0]; // @[VCommon.scala 122:15]
-  wire  ctrlready = ctrl_io_in_ready & (io_read_ready | ~ctrl_io_in_bits_write); // @[VLdSt.scala 206:33]
-  reg  rdataEn; // @[VLdSt.scala 201:24]
-  reg [7:0] rdataSize; // @[VLdSt.scala 202:22]
-  reg [4:0] rdataAddr; // @[VLdSt.scala 203:22]
-  reg [4:0] rdataAshf; // @[VLdSt.scala 204:22]
-  wire  qoutEn = q_io_out_valid & q_io_out_ready; // @[VLdSt.scala 208:31]
-  wire  rdataEnNxt = qoutEn & ctrl_io_in_bits_write; // @[VLdSt.scala 209:27]
-  wire  _qmaxvlb_T = q_io_out_bits_op == 7'h4; // @[VLdSt.scala 211:38]
-  wire [7:0] qmaxvlb = q_io_out_bits_op == 7'h4 ? 8'h8 : 8'h20; // @[VLdSt.scala 211:20]
-  wire [7:0] qsize = q_io_out_bits_remain > qmaxvlb ? qmaxvlb : q_io_out_bits_remain; // @[VLdSt.scala 212:18]
-  wire [1:0] quad = q_io_out_bits_quad; // @[VLdSt.scala 216:34]
-  wire [9:0] _rdataAshf_T_1 = quad * 8'h8; // @[VLdSt.scala 219:45]
-  wire [31:0] _GEN_3 = {{22'd0}, _rdataAshf_T_1}; // @[VLdSt.scala 219:37]
-  wire [31:0] _rdataAshf_T_3 = q_io_out_bits_addr - _GEN_3; // @[VLdSt.scala 219:37]
-  wire [31:0] _GEN_1 = rdataEnNxt ? q_io_out_bits_addr : {{27'd0}, rdataAddr}; // @[VLdSt.scala 215:21 218:15 203:22]
-  wire [31:0] _GEN_2 = rdataEnNxt ? _rdataAshf_T_3 : {{27'd0}, rdataAshf}; // @[VLdSt.scala 215:21 219:15 204:22]
-  wire  rdataWmask_0 = rdataSize > 8'h0; // @[VLdSt.scala 223:32]
-  wire  rdataWmask_1 = rdataSize > 8'h1; // @[VLdSt.scala 223:32]
-  wire  rdataWmask_2 = rdataSize > 8'h2; // @[VLdSt.scala 223:32]
-  wire  rdataWmask_3 = rdataSize > 8'h3; // @[VLdSt.scala 223:32]
-  wire  rdataWmask_4 = rdataSize > 8'h4; // @[VLdSt.scala 223:32]
-  wire  rdataWmask_5 = rdataSize > 8'h5; // @[VLdSt.scala 223:32]
-  wire  rdataWmask_6 = rdataSize > 8'h6; // @[VLdSt.scala 223:32]
-  wire  rdataWmask_7 = rdataSize > 8'h7; // @[VLdSt.scala 223:32]
-  wire  rdataWmask_8 = rdataSize > 8'h8; // @[VLdSt.scala 223:32]
-  wire  rdataWmask_9 = rdataSize > 8'h9; // @[VLdSt.scala 223:32]
-  wire  rdataWmask_10 = rdataSize > 8'ha; // @[VLdSt.scala 223:32]
-  wire  rdataWmask_11 = rdataSize > 8'hb; // @[VLdSt.scala 223:32]
-  wire  rdataWmask_12 = rdataSize > 8'hc; // @[VLdSt.scala 223:32]
-  wire  rdataWmask_13 = rdataSize > 8'hd; // @[VLdSt.scala 223:32]
-  wire  rdataWmask_14 = rdataSize > 8'he; // @[VLdSt.scala 223:32]
-  wire  rdataWmask_15 = rdataSize > 8'hf; // @[VLdSt.scala 223:32]
-  wire  rdataWmask_16 = rdataSize > 8'h10; // @[VLdSt.scala 223:32]
-  wire  rdataWmask_17 = rdataSize > 8'h11; // @[VLdSt.scala 223:32]
-  wire  rdataWmask_18 = rdataSize > 8'h12; // @[VLdSt.scala 223:32]
-  wire  rdataWmask_19 = rdataSize > 8'h13; // @[VLdSt.scala 223:32]
-  wire  rdataWmask_20 = rdataSize > 8'h14; // @[VLdSt.scala 223:32]
-  wire  rdataWmask_21 = rdataSize > 8'h15; // @[VLdSt.scala 223:32]
-  wire  rdataWmask_22 = rdataSize > 8'h16; // @[VLdSt.scala 223:32]
-  wire  rdataWmask_23 = rdataSize > 8'h17; // @[VLdSt.scala 223:32]
-  wire  rdataWmask_24 = rdataSize > 8'h18; // @[VLdSt.scala 223:32]
-  wire  rdataWmask_25 = rdataSize > 8'h19; // @[VLdSt.scala 223:32]
-  wire  rdataWmask_26 = rdataSize > 8'h1a; // @[VLdSt.scala 223:32]
-  wire  rdataWmask_27 = rdataSize > 8'h1b; // @[VLdSt.scala 223:32]
-  wire  rdataWmask_28 = rdataSize > 8'h1c; // @[VLdSt.scala 223:32]
-  wire  rdataWmask_29 = rdataSize > 8'h1d; // @[VLdSt.scala 223:32]
-  wire  rdataWmask_30 = rdataSize > 8'h1e; // @[VLdSt.scala 223:32]
-  wire  rdataWmask_31 = rdataSize > 8'h1f; // @[VLdSt.scala 223:32]
-  wire  _T_4 = ~reset; // @[VLdSt.scala 235:9]
-  wire [7:0] data_io_in_bits_wdata_datain_0 = io_read_data[7:0]; // @[VLdSt.scala 47:24]
-  wire [7:0] data_io_in_bits_wdata_datain_1 = io_read_data[15:8]; // @[VLdSt.scala 47:24]
-  wire [7:0] data_io_in_bits_wdata_datain_2 = io_read_data[23:16]; // @[VLdSt.scala 47:24]
-  wire [7:0] data_io_in_bits_wdata_datain_3 = io_read_data[31:24]; // @[VLdSt.scala 47:24]
-  wire [7:0] data_io_in_bits_wdata_datain_4 = io_read_data[39:32]; // @[VLdSt.scala 47:24]
-  wire [7:0] data_io_in_bits_wdata_datain_5 = io_read_data[47:40]; // @[VLdSt.scala 47:24]
-  wire [7:0] data_io_in_bits_wdata_datain_6 = io_read_data[55:48]; // @[VLdSt.scala 47:24]
-  wire [7:0] data_io_in_bits_wdata_datain_7 = io_read_data[63:56]; // @[VLdSt.scala 47:24]
-  wire [7:0] data_io_in_bits_wdata_datain_8 = io_read_data[71:64]; // @[VLdSt.scala 47:24]
-  wire [7:0] data_io_in_bits_wdata_datain_9 = io_read_data[79:72]; // @[VLdSt.scala 47:24]
-  wire [7:0] data_io_in_bits_wdata_datain_10 = io_read_data[87:80]; // @[VLdSt.scala 47:24]
-  wire [7:0] data_io_in_bits_wdata_datain_11 = io_read_data[95:88]; // @[VLdSt.scala 47:24]
-  wire [7:0] data_io_in_bits_wdata_datain_12 = io_read_data[103:96]; // @[VLdSt.scala 47:24]
-  wire [7:0] data_io_in_bits_wdata_datain_13 = io_read_data[111:104]; // @[VLdSt.scala 47:24]
-  wire [7:0] data_io_in_bits_wdata_datain_14 = io_read_data[119:112]; // @[VLdSt.scala 47:24]
-  wire [7:0] data_io_in_bits_wdata_datain_15 = io_read_data[127:120]; // @[VLdSt.scala 47:24]
-  wire [7:0] data_io_in_bits_wdata_datain_16 = io_read_data[135:128]; // @[VLdSt.scala 47:24]
-  wire [7:0] data_io_in_bits_wdata_datain_17 = io_read_data[143:136]; // @[VLdSt.scala 47:24]
-  wire [7:0] data_io_in_bits_wdata_datain_18 = io_read_data[151:144]; // @[VLdSt.scala 47:24]
-  wire [7:0] data_io_in_bits_wdata_datain_19 = io_read_data[159:152]; // @[VLdSt.scala 47:24]
-  wire [7:0] data_io_in_bits_wdata_datain_20 = io_read_data[167:160]; // @[VLdSt.scala 47:24]
-  wire [7:0] data_io_in_bits_wdata_datain_21 = io_read_data[175:168]; // @[VLdSt.scala 47:24]
-  wire [7:0] data_io_in_bits_wdata_datain_22 = io_read_data[183:176]; // @[VLdSt.scala 47:24]
-  wire [7:0] data_io_in_bits_wdata_datain_23 = io_read_data[191:184]; // @[VLdSt.scala 47:24]
-  wire [7:0] data_io_in_bits_wdata_datain_24 = io_read_data[199:192]; // @[VLdSt.scala 47:24]
-  wire [7:0] data_io_in_bits_wdata_datain_25 = io_read_data[207:200]; // @[VLdSt.scala 47:24]
-  wire [7:0] data_io_in_bits_wdata_datain_26 = io_read_data[215:208]; // @[VLdSt.scala 47:24]
-  wire [7:0] data_io_in_bits_wdata_datain_27 = io_read_data[223:216]; // @[VLdSt.scala 47:24]
-  wire [7:0] data_io_in_bits_wdata_datain_28 = io_read_data[231:224]; // @[VLdSt.scala 47:24]
-  wire [7:0] data_io_in_bits_wdata_datain_29 = io_read_data[239:232]; // @[VLdSt.scala 47:24]
-  wire [7:0] data_io_in_bits_wdata_datain_30 = io_read_data[247:240]; // @[VLdSt.scala 47:24]
-  wire [7:0] data_io_in_bits_wdata_datain_31 = io_read_data[255:248]; // @[VLdSt.scala 47:24]
-  wire [4:0] data_io_in_bits_wdata_idx = 5'h0 - rdataAshf; // @[VLdSt.scala 52:53]
+  wire  ctrlready = ctrl_io_in_ready & (io_read_ready | ~ctrl_io_in_bits_write); // @[VLdSt.scala 209:33]
+  reg  rdataEn; // @[VLdSt.scala 204:24]
+  reg [7:0] rdataSize; // @[VLdSt.scala 205:22]
+  reg [4:0] rdataAddr; // @[VLdSt.scala 206:22]
+  reg [4:0] rdataAshf; // @[VLdSt.scala 207:22]
+  wire  qoutEn = q_io_out_valid & q_io_out_ready; // @[VLdSt.scala 211:31]
+  wire  rdataEnNxt = qoutEn & ctrl_io_in_bits_write; // @[VLdSt.scala 212:27]
+  wire  _qmaxvlb_T = q_io_out_bits_op == 7'h4; // @[VLdSt.scala 214:38]
+  wire [7:0] qmaxvlb = q_io_out_bits_op == 7'h4 ? 8'h8 : 8'h20; // @[VLdSt.scala 214:20]
+  wire [7:0] qsize = q_io_out_bits_remain > qmaxvlb ? qmaxvlb : q_io_out_bits_remain; // @[VLdSt.scala 215:18]
+  wire [1:0] quad = q_io_out_bits_quad; // @[VLdSt.scala 219:34]
+  wire [9:0] _rdataAshf_T_1 = quad * 8'h8; // @[VLdSt.scala 222:45]
+  wire [31:0] _GEN_3 = {{22'd0}, _rdataAshf_T_1}; // @[VLdSt.scala 222:37]
+  wire [31:0] _rdataAshf_T_3 = q_io_out_bits_addr - _GEN_3; // @[VLdSt.scala 222:37]
+  wire [31:0] _GEN_1 = rdataEnNxt ? q_io_out_bits_addr : {{27'd0}, rdataAddr}; // @[VLdSt.scala 218:21 221:15 206:22]
+  wire [31:0] _GEN_2 = rdataEnNxt ? _rdataAshf_T_3 : {{27'd0}, rdataAshf}; // @[VLdSt.scala 218:21 222:15 207:22]
+  wire  rdataWmask_0 = rdataSize > 8'h0; // @[VLdSt.scala 226:32]
+  wire  rdataWmask_1 = rdataSize > 8'h1; // @[VLdSt.scala 226:32]
+  wire  rdataWmask_2 = rdataSize > 8'h2; // @[VLdSt.scala 226:32]
+  wire  rdataWmask_3 = rdataSize > 8'h3; // @[VLdSt.scala 226:32]
+  wire  rdataWmask_4 = rdataSize > 8'h4; // @[VLdSt.scala 226:32]
+  wire  rdataWmask_5 = rdataSize > 8'h5; // @[VLdSt.scala 226:32]
+  wire  rdataWmask_6 = rdataSize > 8'h6; // @[VLdSt.scala 226:32]
+  wire  rdataWmask_7 = rdataSize > 8'h7; // @[VLdSt.scala 226:32]
+  wire  rdataWmask_8 = rdataSize > 8'h8; // @[VLdSt.scala 226:32]
+  wire  rdataWmask_9 = rdataSize > 8'h9; // @[VLdSt.scala 226:32]
+  wire  rdataWmask_10 = rdataSize > 8'ha; // @[VLdSt.scala 226:32]
+  wire  rdataWmask_11 = rdataSize > 8'hb; // @[VLdSt.scala 226:32]
+  wire  rdataWmask_12 = rdataSize > 8'hc; // @[VLdSt.scala 226:32]
+  wire  rdataWmask_13 = rdataSize > 8'hd; // @[VLdSt.scala 226:32]
+  wire  rdataWmask_14 = rdataSize > 8'he; // @[VLdSt.scala 226:32]
+  wire  rdataWmask_15 = rdataSize > 8'hf; // @[VLdSt.scala 226:32]
+  wire  rdataWmask_16 = rdataSize > 8'h10; // @[VLdSt.scala 226:32]
+  wire  rdataWmask_17 = rdataSize > 8'h11; // @[VLdSt.scala 226:32]
+  wire  rdataWmask_18 = rdataSize > 8'h12; // @[VLdSt.scala 226:32]
+  wire  rdataWmask_19 = rdataSize > 8'h13; // @[VLdSt.scala 226:32]
+  wire  rdataWmask_20 = rdataSize > 8'h14; // @[VLdSt.scala 226:32]
+  wire  rdataWmask_21 = rdataSize > 8'h15; // @[VLdSt.scala 226:32]
+  wire  rdataWmask_22 = rdataSize > 8'h16; // @[VLdSt.scala 226:32]
+  wire  rdataWmask_23 = rdataSize > 8'h17; // @[VLdSt.scala 226:32]
+  wire  rdataWmask_24 = rdataSize > 8'h18; // @[VLdSt.scala 226:32]
+  wire  rdataWmask_25 = rdataSize > 8'h19; // @[VLdSt.scala 226:32]
+  wire  rdataWmask_26 = rdataSize > 8'h1a; // @[VLdSt.scala 226:32]
+  wire  rdataWmask_27 = rdataSize > 8'h1b; // @[VLdSt.scala 226:32]
+  wire  rdataWmask_28 = rdataSize > 8'h1c; // @[VLdSt.scala 226:32]
+  wire  rdataWmask_29 = rdataSize > 8'h1d; // @[VLdSt.scala 226:32]
+  wire  rdataWmask_30 = rdataSize > 8'h1e; // @[VLdSt.scala 226:32]
+  wire  rdataWmask_31 = rdataSize > 8'h1f; // @[VLdSt.scala 226:32]
+  wire  _T_4 = ~reset; // @[VLdSt.scala 238:9]
+  wire [7:0] data_io_in_bits_wdata_datain_0 = io_read_data[7:0]; // @[VLdSt.scala 50:24]
+  wire [7:0] data_io_in_bits_wdata_datain_1 = io_read_data[15:8]; // @[VLdSt.scala 50:24]
+  wire [7:0] data_io_in_bits_wdata_datain_2 = io_read_data[23:16]; // @[VLdSt.scala 50:24]
+  wire [7:0] data_io_in_bits_wdata_datain_3 = io_read_data[31:24]; // @[VLdSt.scala 50:24]
+  wire [7:0] data_io_in_bits_wdata_datain_4 = io_read_data[39:32]; // @[VLdSt.scala 50:24]
+  wire [7:0] data_io_in_bits_wdata_datain_5 = io_read_data[47:40]; // @[VLdSt.scala 50:24]
+  wire [7:0] data_io_in_bits_wdata_datain_6 = io_read_data[55:48]; // @[VLdSt.scala 50:24]
+  wire [7:0] data_io_in_bits_wdata_datain_7 = io_read_data[63:56]; // @[VLdSt.scala 50:24]
+  wire [7:0] data_io_in_bits_wdata_datain_8 = io_read_data[71:64]; // @[VLdSt.scala 50:24]
+  wire [7:0] data_io_in_bits_wdata_datain_9 = io_read_data[79:72]; // @[VLdSt.scala 50:24]
+  wire [7:0] data_io_in_bits_wdata_datain_10 = io_read_data[87:80]; // @[VLdSt.scala 50:24]
+  wire [7:0] data_io_in_bits_wdata_datain_11 = io_read_data[95:88]; // @[VLdSt.scala 50:24]
+  wire [7:0] data_io_in_bits_wdata_datain_12 = io_read_data[103:96]; // @[VLdSt.scala 50:24]
+  wire [7:0] data_io_in_bits_wdata_datain_13 = io_read_data[111:104]; // @[VLdSt.scala 50:24]
+  wire [7:0] data_io_in_bits_wdata_datain_14 = io_read_data[119:112]; // @[VLdSt.scala 50:24]
+  wire [7:0] data_io_in_bits_wdata_datain_15 = io_read_data[127:120]; // @[VLdSt.scala 50:24]
+  wire [7:0] data_io_in_bits_wdata_datain_16 = io_read_data[135:128]; // @[VLdSt.scala 50:24]
+  wire [7:0] data_io_in_bits_wdata_datain_17 = io_read_data[143:136]; // @[VLdSt.scala 50:24]
+  wire [7:0] data_io_in_bits_wdata_datain_18 = io_read_data[151:144]; // @[VLdSt.scala 50:24]
+  wire [7:0] data_io_in_bits_wdata_datain_19 = io_read_data[159:152]; // @[VLdSt.scala 50:24]
+  wire [7:0] data_io_in_bits_wdata_datain_20 = io_read_data[167:160]; // @[VLdSt.scala 50:24]
+  wire [7:0] data_io_in_bits_wdata_datain_21 = io_read_data[175:168]; // @[VLdSt.scala 50:24]
+  wire [7:0] data_io_in_bits_wdata_datain_22 = io_read_data[183:176]; // @[VLdSt.scala 50:24]
+  wire [7:0] data_io_in_bits_wdata_datain_23 = io_read_data[191:184]; // @[VLdSt.scala 50:24]
+  wire [7:0] data_io_in_bits_wdata_datain_24 = io_read_data[199:192]; // @[VLdSt.scala 50:24]
+  wire [7:0] data_io_in_bits_wdata_datain_25 = io_read_data[207:200]; // @[VLdSt.scala 50:24]
+  wire [7:0] data_io_in_bits_wdata_datain_26 = io_read_data[215:208]; // @[VLdSt.scala 50:24]
+  wire [7:0] data_io_in_bits_wdata_datain_27 = io_read_data[223:216]; // @[VLdSt.scala 50:24]
+  wire [7:0] data_io_in_bits_wdata_datain_28 = io_read_data[231:224]; // @[VLdSt.scala 50:24]
+  wire [7:0] data_io_in_bits_wdata_datain_29 = io_read_data[239:232]; // @[VLdSt.scala 50:24]
+  wire [7:0] data_io_in_bits_wdata_datain_30 = io_read_data[247:240]; // @[VLdSt.scala 50:24]
+  wire [7:0] data_io_in_bits_wdata_datain_31 = io_read_data[255:248]; // @[VLdSt.scala 50:24]
+  wire [4:0] data_io_in_bits_wdata_idx = 5'h0 - rdataAshf; // @[VLdSt.scala 55:52]
   wire [7:0] data_io_in_bits_wdata_dataout_0_value__0 = 5'h0 == data_io_in_bits_wdata_idx ?
     data_io_in_bits_wdata_datain_0 : 8'h0; // @[Library.scala 101:22]
   wire [7:0] data_io_in_bits_wdata_dataout_0_value__1 = 5'h1 == data_io_in_bits_wdata_idx ?
@@ -88450,7 +78892,7 @@
     data_io_in_bits_wdata_dataout_0_value_3_3; // @[Library.scala 115:37]
   wire [7:0] data_io_in_bits_wdata_dataout_0_value_5_0 = data_io_in_bits_wdata_dataout_0_value_4_0 |
     data_io_in_bits_wdata_dataout_0_value_4_1; // @[Library.scala 115:37]
-  wire [4:0] data_io_in_bits_wdata_idx_1 = 5'h1 - rdataAshf; // @[VLdSt.scala 52:53]
+  wire [4:0] data_io_in_bits_wdata_idx_1 = 5'h1 - rdataAshf; // @[VLdSt.scala 55:52]
   wire [7:0] data_io_in_bits_wdata_dataout_1_value__0 = 5'h0 == data_io_in_bits_wdata_idx_1 ?
     data_io_in_bits_wdata_datain_0 : 8'h0; // @[Library.scala 101:22]
   wire [7:0] data_io_in_bits_wdata_dataout_1_value__1 = 5'h1 == data_io_in_bits_wdata_idx_1 ?
@@ -88577,7 +79019,7 @@
     data_io_in_bits_wdata_dataout_1_value_3_3; // @[Library.scala 115:37]
   wire [7:0] data_io_in_bits_wdata_dataout_1_value_5_0 = data_io_in_bits_wdata_dataout_1_value_4_0 |
     data_io_in_bits_wdata_dataout_1_value_4_1; // @[Library.scala 115:37]
-  wire [4:0] data_io_in_bits_wdata_idx_2 = 5'h2 - rdataAshf; // @[VLdSt.scala 52:53]
+  wire [4:0] data_io_in_bits_wdata_idx_2 = 5'h2 - rdataAshf; // @[VLdSt.scala 55:52]
   wire [7:0] data_io_in_bits_wdata_dataout_2_value__0 = 5'h0 == data_io_in_bits_wdata_idx_2 ?
     data_io_in_bits_wdata_datain_0 : 8'h0; // @[Library.scala 101:22]
   wire [7:0] data_io_in_bits_wdata_dataout_2_value__1 = 5'h1 == data_io_in_bits_wdata_idx_2 ?
@@ -88704,7 +79146,7 @@
     data_io_in_bits_wdata_dataout_2_value_3_3; // @[Library.scala 115:37]
   wire [7:0] data_io_in_bits_wdata_dataout_2_value_5_0 = data_io_in_bits_wdata_dataout_2_value_4_0 |
     data_io_in_bits_wdata_dataout_2_value_4_1; // @[Library.scala 115:37]
-  wire [4:0] data_io_in_bits_wdata_idx_3 = 5'h3 - rdataAshf; // @[VLdSt.scala 52:53]
+  wire [4:0] data_io_in_bits_wdata_idx_3 = 5'h3 - rdataAshf; // @[VLdSt.scala 55:52]
   wire [7:0] data_io_in_bits_wdata_dataout_3_value__0 = 5'h0 == data_io_in_bits_wdata_idx_3 ?
     data_io_in_bits_wdata_datain_0 : 8'h0; // @[Library.scala 101:22]
   wire [7:0] data_io_in_bits_wdata_dataout_3_value__1 = 5'h1 == data_io_in_bits_wdata_idx_3 ?
@@ -88831,7 +79273,7 @@
     data_io_in_bits_wdata_dataout_3_value_3_3; // @[Library.scala 115:37]
   wire [7:0] data_io_in_bits_wdata_dataout_3_value_5_0 = data_io_in_bits_wdata_dataout_3_value_4_0 |
     data_io_in_bits_wdata_dataout_3_value_4_1; // @[Library.scala 115:37]
-  wire [4:0] data_io_in_bits_wdata_idx_4 = 5'h4 - rdataAshf; // @[VLdSt.scala 52:53]
+  wire [4:0] data_io_in_bits_wdata_idx_4 = 5'h4 - rdataAshf; // @[VLdSt.scala 55:52]
   wire [7:0] data_io_in_bits_wdata_dataout_4_value__0 = 5'h0 == data_io_in_bits_wdata_idx_4 ?
     data_io_in_bits_wdata_datain_0 : 8'h0; // @[Library.scala 101:22]
   wire [7:0] data_io_in_bits_wdata_dataout_4_value__1 = 5'h1 == data_io_in_bits_wdata_idx_4 ?
@@ -88958,7 +79400,7 @@
     data_io_in_bits_wdata_dataout_4_value_3_3; // @[Library.scala 115:37]
   wire [7:0] data_io_in_bits_wdata_dataout_4_value_5_0 = data_io_in_bits_wdata_dataout_4_value_4_0 |
     data_io_in_bits_wdata_dataout_4_value_4_1; // @[Library.scala 115:37]
-  wire [4:0] data_io_in_bits_wdata_idx_5 = 5'h5 - rdataAshf; // @[VLdSt.scala 52:53]
+  wire [4:0] data_io_in_bits_wdata_idx_5 = 5'h5 - rdataAshf; // @[VLdSt.scala 55:52]
   wire [7:0] data_io_in_bits_wdata_dataout_5_value__0 = 5'h0 == data_io_in_bits_wdata_idx_5 ?
     data_io_in_bits_wdata_datain_0 : 8'h0; // @[Library.scala 101:22]
   wire [7:0] data_io_in_bits_wdata_dataout_5_value__1 = 5'h1 == data_io_in_bits_wdata_idx_5 ?
@@ -89085,7 +79527,7 @@
     data_io_in_bits_wdata_dataout_5_value_3_3; // @[Library.scala 115:37]
   wire [7:0] data_io_in_bits_wdata_dataout_5_value_5_0 = data_io_in_bits_wdata_dataout_5_value_4_0 |
     data_io_in_bits_wdata_dataout_5_value_4_1; // @[Library.scala 115:37]
-  wire [4:0] data_io_in_bits_wdata_idx_6 = 5'h6 - rdataAshf; // @[VLdSt.scala 52:53]
+  wire [4:0] data_io_in_bits_wdata_idx_6 = 5'h6 - rdataAshf; // @[VLdSt.scala 55:52]
   wire [7:0] data_io_in_bits_wdata_dataout_6_value__0 = 5'h0 == data_io_in_bits_wdata_idx_6 ?
     data_io_in_bits_wdata_datain_0 : 8'h0; // @[Library.scala 101:22]
   wire [7:0] data_io_in_bits_wdata_dataout_6_value__1 = 5'h1 == data_io_in_bits_wdata_idx_6 ?
@@ -89212,7 +79654,7 @@
     data_io_in_bits_wdata_dataout_6_value_3_3; // @[Library.scala 115:37]
   wire [7:0] data_io_in_bits_wdata_dataout_6_value_5_0 = data_io_in_bits_wdata_dataout_6_value_4_0 |
     data_io_in_bits_wdata_dataout_6_value_4_1; // @[Library.scala 115:37]
-  wire [4:0] data_io_in_bits_wdata_idx_7 = 5'h7 - rdataAshf; // @[VLdSt.scala 52:53]
+  wire [4:0] data_io_in_bits_wdata_idx_7 = 5'h7 - rdataAshf; // @[VLdSt.scala 55:52]
   wire [7:0] data_io_in_bits_wdata_dataout_7_value__0 = 5'h0 == data_io_in_bits_wdata_idx_7 ?
     data_io_in_bits_wdata_datain_0 : 8'h0; // @[Library.scala 101:22]
   wire [7:0] data_io_in_bits_wdata_dataout_7_value__1 = 5'h1 == data_io_in_bits_wdata_idx_7 ?
@@ -89339,7 +79781,7 @@
     data_io_in_bits_wdata_dataout_7_value_3_3; // @[Library.scala 115:37]
   wire [7:0] data_io_in_bits_wdata_dataout_7_value_5_0 = data_io_in_bits_wdata_dataout_7_value_4_0 |
     data_io_in_bits_wdata_dataout_7_value_4_1; // @[Library.scala 115:37]
-  wire [4:0] data_io_in_bits_wdata_idx_8 = 5'h8 - rdataAshf; // @[VLdSt.scala 52:53]
+  wire [4:0] data_io_in_bits_wdata_idx_8 = 5'h8 - rdataAshf; // @[VLdSt.scala 55:52]
   wire [7:0] data_io_in_bits_wdata_dataout_8_value__0 = 5'h0 == data_io_in_bits_wdata_idx_8 ?
     data_io_in_bits_wdata_datain_0 : 8'h0; // @[Library.scala 101:22]
   wire [7:0] data_io_in_bits_wdata_dataout_8_value__1 = 5'h1 == data_io_in_bits_wdata_idx_8 ?
@@ -89466,7 +79908,7 @@
     data_io_in_bits_wdata_dataout_8_value_3_3; // @[Library.scala 115:37]
   wire [7:0] data_io_in_bits_wdata_dataout_8_value_5_0 = data_io_in_bits_wdata_dataout_8_value_4_0 |
     data_io_in_bits_wdata_dataout_8_value_4_1; // @[Library.scala 115:37]
-  wire [4:0] data_io_in_bits_wdata_idx_9 = 5'h9 - rdataAshf; // @[VLdSt.scala 52:53]
+  wire [4:0] data_io_in_bits_wdata_idx_9 = 5'h9 - rdataAshf; // @[VLdSt.scala 55:52]
   wire [7:0] data_io_in_bits_wdata_dataout_9_value__0 = 5'h0 == data_io_in_bits_wdata_idx_9 ?
     data_io_in_bits_wdata_datain_0 : 8'h0; // @[Library.scala 101:22]
   wire [7:0] data_io_in_bits_wdata_dataout_9_value__1 = 5'h1 == data_io_in_bits_wdata_idx_9 ?
@@ -89593,7 +80035,7 @@
     data_io_in_bits_wdata_dataout_9_value_3_3; // @[Library.scala 115:37]
   wire [7:0] data_io_in_bits_wdata_dataout_9_value_5_0 = data_io_in_bits_wdata_dataout_9_value_4_0 |
     data_io_in_bits_wdata_dataout_9_value_4_1; // @[Library.scala 115:37]
-  wire [4:0] data_io_in_bits_wdata_idx_10 = 5'ha - rdataAshf; // @[VLdSt.scala 52:53]
+  wire [4:0] data_io_in_bits_wdata_idx_10 = 5'ha - rdataAshf; // @[VLdSt.scala 55:52]
   wire [7:0] data_io_in_bits_wdata_dataout_10_value__0 = 5'h0 == data_io_in_bits_wdata_idx_10 ?
     data_io_in_bits_wdata_datain_0 : 8'h0; // @[Library.scala 101:22]
   wire [7:0] data_io_in_bits_wdata_dataout_10_value__1 = 5'h1 == data_io_in_bits_wdata_idx_10 ?
@@ -89720,7 +80162,7 @@
     data_io_in_bits_wdata_dataout_10_value_3_3; // @[Library.scala 115:37]
   wire [7:0] data_io_in_bits_wdata_dataout_10_value_5_0 = data_io_in_bits_wdata_dataout_10_value_4_0 |
     data_io_in_bits_wdata_dataout_10_value_4_1; // @[Library.scala 115:37]
-  wire [4:0] data_io_in_bits_wdata_idx_11 = 5'hb - rdataAshf; // @[VLdSt.scala 52:53]
+  wire [4:0] data_io_in_bits_wdata_idx_11 = 5'hb - rdataAshf; // @[VLdSt.scala 55:52]
   wire [7:0] data_io_in_bits_wdata_dataout_11_value__0 = 5'h0 == data_io_in_bits_wdata_idx_11 ?
     data_io_in_bits_wdata_datain_0 : 8'h0; // @[Library.scala 101:22]
   wire [7:0] data_io_in_bits_wdata_dataout_11_value__1 = 5'h1 == data_io_in_bits_wdata_idx_11 ?
@@ -89847,7 +80289,7 @@
     data_io_in_bits_wdata_dataout_11_value_3_3; // @[Library.scala 115:37]
   wire [7:0] data_io_in_bits_wdata_dataout_11_value_5_0 = data_io_in_bits_wdata_dataout_11_value_4_0 |
     data_io_in_bits_wdata_dataout_11_value_4_1; // @[Library.scala 115:37]
-  wire [4:0] data_io_in_bits_wdata_idx_12 = 5'hc - rdataAshf; // @[VLdSt.scala 52:53]
+  wire [4:0] data_io_in_bits_wdata_idx_12 = 5'hc - rdataAshf; // @[VLdSt.scala 55:52]
   wire [7:0] data_io_in_bits_wdata_dataout_12_value__0 = 5'h0 == data_io_in_bits_wdata_idx_12 ?
     data_io_in_bits_wdata_datain_0 : 8'h0; // @[Library.scala 101:22]
   wire [7:0] data_io_in_bits_wdata_dataout_12_value__1 = 5'h1 == data_io_in_bits_wdata_idx_12 ?
@@ -89974,7 +80416,7 @@
     data_io_in_bits_wdata_dataout_12_value_3_3; // @[Library.scala 115:37]
   wire [7:0] data_io_in_bits_wdata_dataout_12_value_5_0 = data_io_in_bits_wdata_dataout_12_value_4_0 |
     data_io_in_bits_wdata_dataout_12_value_4_1; // @[Library.scala 115:37]
-  wire [4:0] data_io_in_bits_wdata_idx_13 = 5'hd - rdataAshf; // @[VLdSt.scala 52:53]
+  wire [4:0] data_io_in_bits_wdata_idx_13 = 5'hd - rdataAshf; // @[VLdSt.scala 55:52]
   wire [7:0] data_io_in_bits_wdata_dataout_13_value__0 = 5'h0 == data_io_in_bits_wdata_idx_13 ?
     data_io_in_bits_wdata_datain_0 : 8'h0; // @[Library.scala 101:22]
   wire [7:0] data_io_in_bits_wdata_dataout_13_value__1 = 5'h1 == data_io_in_bits_wdata_idx_13 ?
@@ -90101,7 +80543,7 @@
     data_io_in_bits_wdata_dataout_13_value_3_3; // @[Library.scala 115:37]
   wire [7:0] data_io_in_bits_wdata_dataout_13_value_5_0 = data_io_in_bits_wdata_dataout_13_value_4_0 |
     data_io_in_bits_wdata_dataout_13_value_4_1; // @[Library.scala 115:37]
-  wire [4:0] data_io_in_bits_wdata_idx_14 = 5'he - rdataAshf; // @[VLdSt.scala 52:53]
+  wire [4:0] data_io_in_bits_wdata_idx_14 = 5'he - rdataAshf; // @[VLdSt.scala 55:52]
   wire [7:0] data_io_in_bits_wdata_dataout_14_value__0 = 5'h0 == data_io_in_bits_wdata_idx_14 ?
     data_io_in_bits_wdata_datain_0 : 8'h0; // @[Library.scala 101:22]
   wire [7:0] data_io_in_bits_wdata_dataout_14_value__1 = 5'h1 == data_io_in_bits_wdata_idx_14 ?
@@ -90228,7 +80670,7 @@
     data_io_in_bits_wdata_dataout_14_value_3_3; // @[Library.scala 115:37]
   wire [7:0] data_io_in_bits_wdata_dataout_14_value_5_0 = data_io_in_bits_wdata_dataout_14_value_4_0 |
     data_io_in_bits_wdata_dataout_14_value_4_1; // @[Library.scala 115:37]
-  wire [4:0] data_io_in_bits_wdata_idx_15 = 5'hf - rdataAshf; // @[VLdSt.scala 52:53]
+  wire [4:0] data_io_in_bits_wdata_idx_15 = 5'hf - rdataAshf; // @[VLdSt.scala 55:52]
   wire [7:0] data_io_in_bits_wdata_dataout_15_value__0 = 5'h0 == data_io_in_bits_wdata_idx_15 ?
     data_io_in_bits_wdata_datain_0 : 8'h0; // @[Library.scala 101:22]
   wire [7:0] data_io_in_bits_wdata_dataout_15_value__1 = 5'h1 == data_io_in_bits_wdata_idx_15 ?
@@ -90355,7 +80797,7 @@
     data_io_in_bits_wdata_dataout_15_value_3_3; // @[Library.scala 115:37]
   wire [7:0] data_io_in_bits_wdata_dataout_15_value_5_0 = data_io_in_bits_wdata_dataout_15_value_4_0 |
     data_io_in_bits_wdata_dataout_15_value_4_1; // @[Library.scala 115:37]
-  wire [4:0] data_io_in_bits_wdata_idx_16 = 5'h10 - rdataAshf; // @[VLdSt.scala 52:53]
+  wire [4:0] data_io_in_bits_wdata_idx_16 = 5'h10 - rdataAshf; // @[VLdSt.scala 55:52]
   wire [7:0] data_io_in_bits_wdata_dataout_16_value__0 = 5'h0 == data_io_in_bits_wdata_idx_16 ?
     data_io_in_bits_wdata_datain_0 : 8'h0; // @[Library.scala 101:22]
   wire [7:0] data_io_in_bits_wdata_dataout_16_value__1 = 5'h1 == data_io_in_bits_wdata_idx_16 ?
@@ -90482,7 +80924,7 @@
     data_io_in_bits_wdata_dataout_16_value_3_3; // @[Library.scala 115:37]
   wire [7:0] data_io_in_bits_wdata_dataout_16_value_5_0 = data_io_in_bits_wdata_dataout_16_value_4_0 |
     data_io_in_bits_wdata_dataout_16_value_4_1; // @[Library.scala 115:37]
-  wire [4:0] data_io_in_bits_wdata_idx_17 = 5'h11 - rdataAshf; // @[VLdSt.scala 52:53]
+  wire [4:0] data_io_in_bits_wdata_idx_17 = 5'h11 - rdataAshf; // @[VLdSt.scala 55:52]
   wire [7:0] data_io_in_bits_wdata_dataout_17_value__0 = 5'h0 == data_io_in_bits_wdata_idx_17 ?
     data_io_in_bits_wdata_datain_0 : 8'h0; // @[Library.scala 101:22]
   wire [7:0] data_io_in_bits_wdata_dataout_17_value__1 = 5'h1 == data_io_in_bits_wdata_idx_17 ?
@@ -90609,7 +81051,7 @@
     data_io_in_bits_wdata_dataout_17_value_3_3; // @[Library.scala 115:37]
   wire [7:0] data_io_in_bits_wdata_dataout_17_value_5_0 = data_io_in_bits_wdata_dataout_17_value_4_0 |
     data_io_in_bits_wdata_dataout_17_value_4_1; // @[Library.scala 115:37]
-  wire [4:0] data_io_in_bits_wdata_idx_18 = 5'h12 - rdataAshf; // @[VLdSt.scala 52:53]
+  wire [4:0] data_io_in_bits_wdata_idx_18 = 5'h12 - rdataAshf; // @[VLdSt.scala 55:52]
   wire [7:0] data_io_in_bits_wdata_dataout_18_value__0 = 5'h0 == data_io_in_bits_wdata_idx_18 ?
     data_io_in_bits_wdata_datain_0 : 8'h0; // @[Library.scala 101:22]
   wire [7:0] data_io_in_bits_wdata_dataout_18_value__1 = 5'h1 == data_io_in_bits_wdata_idx_18 ?
@@ -90736,7 +81178,7 @@
     data_io_in_bits_wdata_dataout_18_value_3_3; // @[Library.scala 115:37]
   wire [7:0] data_io_in_bits_wdata_dataout_18_value_5_0 = data_io_in_bits_wdata_dataout_18_value_4_0 |
     data_io_in_bits_wdata_dataout_18_value_4_1; // @[Library.scala 115:37]
-  wire [4:0] data_io_in_bits_wdata_idx_19 = 5'h13 - rdataAshf; // @[VLdSt.scala 52:53]
+  wire [4:0] data_io_in_bits_wdata_idx_19 = 5'h13 - rdataAshf; // @[VLdSt.scala 55:52]
   wire [7:0] data_io_in_bits_wdata_dataout_19_value__0 = 5'h0 == data_io_in_bits_wdata_idx_19 ?
     data_io_in_bits_wdata_datain_0 : 8'h0; // @[Library.scala 101:22]
   wire [7:0] data_io_in_bits_wdata_dataout_19_value__1 = 5'h1 == data_io_in_bits_wdata_idx_19 ?
@@ -90863,7 +81305,7 @@
     data_io_in_bits_wdata_dataout_19_value_3_3; // @[Library.scala 115:37]
   wire [7:0] data_io_in_bits_wdata_dataout_19_value_5_0 = data_io_in_bits_wdata_dataout_19_value_4_0 |
     data_io_in_bits_wdata_dataout_19_value_4_1; // @[Library.scala 115:37]
-  wire [4:0] data_io_in_bits_wdata_idx_20 = 5'h14 - rdataAshf; // @[VLdSt.scala 52:53]
+  wire [4:0] data_io_in_bits_wdata_idx_20 = 5'h14 - rdataAshf; // @[VLdSt.scala 55:52]
   wire [7:0] data_io_in_bits_wdata_dataout_20_value__0 = 5'h0 == data_io_in_bits_wdata_idx_20 ?
     data_io_in_bits_wdata_datain_0 : 8'h0; // @[Library.scala 101:22]
   wire [7:0] data_io_in_bits_wdata_dataout_20_value__1 = 5'h1 == data_io_in_bits_wdata_idx_20 ?
@@ -90990,7 +81432,7 @@
     data_io_in_bits_wdata_dataout_20_value_3_3; // @[Library.scala 115:37]
   wire [7:0] data_io_in_bits_wdata_dataout_20_value_5_0 = data_io_in_bits_wdata_dataout_20_value_4_0 |
     data_io_in_bits_wdata_dataout_20_value_4_1; // @[Library.scala 115:37]
-  wire [4:0] data_io_in_bits_wdata_idx_21 = 5'h15 - rdataAshf; // @[VLdSt.scala 52:53]
+  wire [4:0] data_io_in_bits_wdata_idx_21 = 5'h15 - rdataAshf; // @[VLdSt.scala 55:52]
   wire [7:0] data_io_in_bits_wdata_dataout_21_value__0 = 5'h0 == data_io_in_bits_wdata_idx_21 ?
     data_io_in_bits_wdata_datain_0 : 8'h0; // @[Library.scala 101:22]
   wire [7:0] data_io_in_bits_wdata_dataout_21_value__1 = 5'h1 == data_io_in_bits_wdata_idx_21 ?
@@ -91117,7 +81559,7 @@
     data_io_in_bits_wdata_dataout_21_value_3_3; // @[Library.scala 115:37]
   wire [7:0] data_io_in_bits_wdata_dataout_21_value_5_0 = data_io_in_bits_wdata_dataout_21_value_4_0 |
     data_io_in_bits_wdata_dataout_21_value_4_1; // @[Library.scala 115:37]
-  wire [4:0] data_io_in_bits_wdata_idx_22 = 5'h16 - rdataAshf; // @[VLdSt.scala 52:53]
+  wire [4:0] data_io_in_bits_wdata_idx_22 = 5'h16 - rdataAshf; // @[VLdSt.scala 55:52]
   wire [7:0] data_io_in_bits_wdata_dataout_22_value__0 = 5'h0 == data_io_in_bits_wdata_idx_22 ?
     data_io_in_bits_wdata_datain_0 : 8'h0; // @[Library.scala 101:22]
   wire [7:0] data_io_in_bits_wdata_dataout_22_value__1 = 5'h1 == data_io_in_bits_wdata_idx_22 ?
@@ -91244,7 +81686,7 @@
     data_io_in_bits_wdata_dataout_22_value_3_3; // @[Library.scala 115:37]
   wire [7:0] data_io_in_bits_wdata_dataout_22_value_5_0 = data_io_in_bits_wdata_dataout_22_value_4_0 |
     data_io_in_bits_wdata_dataout_22_value_4_1; // @[Library.scala 115:37]
-  wire [4:0] data_io_in_bits_wdata_idx_23 = 5'h17 - rdataAshf; // @[VLdSt.scala 52:53]
+  wire [4:0] data_io_in_bits_wdata_idx_23 = 5'h17 - rdataAshf; // @[VLdSt.scala 55:52]
   wire [7:0] data_io_in_bits_wdata_dataout_23_value__0 = 5'h0 == data_io_in_bits_wdata_idx_23 ?
     data_io_in_bits_wdata_datain_0 : 8'h0; // @[Library.scala 101:22]
   wire [7:0] data_io_in_bits_wdata_dataout_23_value__1 = 5'h1 == data_io_in_bits_wdata_idx_23 ?
@@ -91371,7 +81813,7 @@
     data_io_in_bits_wdata_dataout_23_value_3_3; // @[Library.scala 115:37]
   wire [7:0] data_io_in_bits_wdata_dataout_23_value_5_0 = data_io_in_bits_wdata_dataout_23_value_4_0 |
     data_io_in_bits_wdata_dataout_23_value_4_1; // @[Library.scala 115:37]
-  wire [4:0] data_io_in_bits_wdata_idx_24 = 5'h18 - rdataAshf; // @[VLdSt.scala 52:53]
+  wire [4:0] data_io_in_bits_wdata_idx_24 = 5'h18 - rdataAshf; // @[VLdSt.scala 55:52]
   wire [7:0] data_io_in_bits_wdata_dataout_24_value__0 = 5'h0 == data_io_in_bits_wdata_idx_24 ?
     data_io_in_bits_wdata_datain_0 : 8'h0; // @[Library.scala 101:22]
   wire [7:0] data_io_in_bits_wdata_dataout_24_value__1 = 5'h1 == data_io_in_bits_wdata_idx_24 ?
@@ -91498,7 +81940,7 @@
     data_io_in_bits_wdata_dataout_24_value_3_3; // @[Library.scala 115:37]
   wire [7:0] data_io_in_bits_wdata_dataout_24_value_5_0 = data_io_in_bits_wdata_dataout_24_value_4_0 |
     data_io_in_bits_wdata_dataout_24_value_4_1; // @[Library.scala 115:37]
-  wire [4:0] data_io_in_bits_wdata_idx_25 = 5'h19 - rdataAshf; // @[VLdSt.scala 52:53]
+  wire [4:0] data_io_in_bits_wdata_idx_25 = 5'h19 - rdataAshf; // @[VLdSt.scala 55:52]
   wire [7:0] data_io_in_bits_wdata_dataout_25_value__0 = 5'h0 == data_io_in_bits_wdata_idx_25 ?
     data_io_in_bits_wdata_datain_0 : 8'h0; // @[Library.scala 101:22]
   wire [7:0] data_io_in_bits_wdata_dataout_25_value__1 = 5'h1 == data_io_in_bits_wdata_idx_25 ?
@@ -91625,7 +82067,7 @@
     data_io_in_bits_wdata_dataout_25_value_3_3; // @[Library.scala 115:37]
   wire [7:0] data_io_in_bits_wdata_dataout_25_value_5_0 = data_io_in_bits_wdata_dataout_25_value_4_0 |
     data_io_in_bits_wdata_dataout_25_value_4_1; // @[Library.scala 115:37]
-  wire [4:0] data_io_in_bits_wdata_idx_26 = 5'h1a - rdataAshf; // @[VLdSt.scala 52:53]
+  wire [4:0] data_io_in_bits_wdata_idx_26 = 5'h1a - rdataAshf; // @[VLdSt.scala 55:52]
   wire [7:0] data_io_in_bits_wdata_dataout_26_value__0 = 5'h0 == data_io_in_bits_wdata_idx_26 ?
     data_io_in_bits_wdata_datain_0 : 8'h0; // @[Library.scala 101:22]
   wire [7:0] data_io_in_bits_wdata_dataout_26_value__1 = 5'h1 == data_io_in_bits_wdata_idx_26 ?
@@ -91752,7 +82194,7 @@
     data_io_in_bits_wdata_dataout_26_value_3_3; // @[Library.scala 115:37]
   wire [7:0] data_io_in_bits_wdata_dataout_26_value_5_0 = data_io_in_bits_wdata_dataout_26_value_4_0 |
     data_io_in_bits_wdata_dataout_26_value_4_1; // @[Library.scala 115:37]
-  wire [4:0] data_io_in_bits_wdata_idx_27 = 5'h1b - rdataAshf; // @[VLdSt.scala 52:53]
+  wire [4:0] data_io_in_bits_wdata_idx_27 = 5'h1b - rdataAshf; // @[VLdSt.scala 55:52]
   wire [7:0] data_io_in_bits_wdata_dataout_27_value__0 = 5'h0 == data_io_in_bits_wdata_idx_27 ?
     data_io_in_bits_wdata_datain_0 : 8'h0; // @[Library.scala 101:22]
   wire [7:0] data_io_in_bits_wdata_dataout_27_value__1 = 5'h1 == data_io_in_bits_wdata_idx_27 ?
@@ -91879,7 +82321,7 @@
     data_io_in_bits_wdata_dataout_27_value_3_3; // @[Library.scala 115:37]
   wire [7:0] data_io_in_bits_wdata_dataout_27_value_5_0 = data_io_in_bits_wdata_dataout_27_value_4_0 |
     data_io_in_bits_wdata_dataout_27_value_4_1; // @[Library.scala 115:37]
-  wire [4:0] data_io_in_bits_wdata_idx_28 = 5'h1c - rdataAshf; // @[VLdSt.scala 52:53]
+  wire [4:0] data_io_in_bits_wdata_idx_28 = 5'h1c - rdataAshf; // @[VLdSt.scala 55:52]
   wire [7:0] data_io_in_bits_wdata_dataout_28_value__0 = 5'h0 == data_io_in_bits_wdata_idx_28 ?
     data_io_in_bits_wdata_datain_0 : 8'h0; // @[Library.scala 101:22]
   wire [7:0] data_io_in_bits_wdata_dataout_28_value__1 = 5'h1 == data_io_in_bits_wdata_idx_28 ?
@@ -92006,7 +82448,7 @@
     data_io_in_bits_wdata_dataout_28_value_3_3; // @[Library.scala 115:37]
   wire [7:0] data_io_in_bits_wdata_dataout_28_value_5_0 = data_io_in_bits_wdata_dataout_28_value_4_0 |
     data_io_in_bits_wdata_dataout_28_value_4_1; // @[Library.scala 115:37]
-  wire [4:0] data_io_in_bits_wdata_idx_29 = 5'h1d - rdataAshf; // @[VLdSt.scala 52:53]
+  wire [4:0] data_io_in_bits_wdata_idx_29 = 5'h1d - rdataAshf; // @[VLdSt.scala 55:52]
   wire [7:0] data_io_in_bits_wdata_dataout_29_value__0 = 5'h0 == data_io_in_bits_wdata_idx_29 ?
     data_io_in_bits_wdata_datain_0 : 8'h0; // @[Library.scala 101:22]
   wire [7:0] data_io_in_bits_wdata_dataout_29_value__1 = 5'h1 == data_io_in_bits_wdata_idx_29 ?
@@ -92133,7 +82575,7 @@
     data_io_in_bits_wdata_dataout_29_value_3_3; // @[Library.scala 115:37]
   wire [7:0] data_io_in_bits_wdata_dataout_29_value_5_0 = data_io_in_bits_wdata_dataout_29_value_4_0 |
     data_io_in_bits_wdata_dataout_29_value_4_1; // @[Library.scala 115:37]
-  wire [4:0] data_io_in_bits_wdata_idx_30 = 5'h1e - rdataAshf; // @[VLdSt.scala 52:53]
+  wire [4:0] data_io_in_bits_wdata_idx_30 = 5'h1e - rdataAshf; // @[VLdSt.scala 55:52]
   wire [7:0] data_io_in_bits_wdata_dataout_30_value__0 = 5'h0 == data_io_in_bits_wdata_idx_30 ?
     data_io_in_bits_wdata_datain_0 : 8'h0; // @[Library.scala 101:22]
   wire [7:0] data_io_in_bits_wdata_dataout_30_value__1 = 5'h1 == data_io_in_bits_wdata_idx_30 ?
@@ -92260,7 +82702,7 @@
     data_io_in_bits_wdata_dataout_30_value_3_3; // @[Library.scala 115:37]
   wire [7:0] data_io_in_bits_wdata_dataout_30_value_5_0 = data_io_in_bits_wdata_dataout_30_value_4_0 |
     data_io_in_bits_wdata_dataout_30_value_4_1; // @[Library.scala 115:37]
-  wire [4:0] data_io_in_bits_wdata_idx_31 = 5'h1f - rdataAshf; // @[VLdSt.scala 52:53]
+  wire [4:0] data_io_in_bits_wdata_idx_31 = 5'h1f - rdataAshf; // @[VLdSt.scala 55:52]
   wire [7:0] data_io_in_bits_wdata_dataout_31_value__0 = 5'h0 == data_io_in_bits_wdata_idx_31 ?
     data_io_in_bits_wdata_datain_0 : 8'h0; // @[Library.scala 101:22]
   wire [7:0] data_io_in_bits_wdata_dataout_31_value__1 = 5'h1 == data_io_in_bits_wdata_idx_31 ?
@@ -92391,63 +82833,63 @@
     data_io_in_bits_wdata_dataout_6_value_5_0,data_io_in_bits_wdata_dataout_5_value_5_0,
     data_io_in_bits_wdata_dataout_4_value_5_0,data_io_in_bits_wdata_dataout_3_value_5_0,
     data_io_in_bits_wdata_dataout_2_value_5_0,data_io_in_bits_wdata_dataout_1_value_5_0,
-    data_io_in_bits_wdata_dataout_0_value_5_0}; // @[VLdSt.scala 57:13]
+    data_io_in_bits_wdata_dataout_0_value_5_0}; // @[VLdSt.scala 60:13]
   wire [127:0] data_io_in_bits_wdata_lo = {data_io_in_bits_wdata_dataout_15_value_5_0,
     data_io_in_bits_wdata_dataout_14_value_5_0,data_io_in_bits_wdata_dataout_13_value_5_0,
     data_io_in_bits_wdata_dataout_12_value_5_0,data_io_in_bits_wdata_dataout_11_value_5_0,
     data_io_in_bits_wdata_dataout_10_value_5_0,data_io_in_bits_wdata_dataout_9_value_5_0,
-    data_io_in_bits_wdata_dataout_8_value_5_0,data_io_in_bits_wdata_lo_lo}; // @[VLdSt.scala 57:13]
+    data_io_in_bits_wdata_dataout_8_value_5_0,data_io_in_bits_wdata_lo_lo}; // @[VLdSt.scala 60:13]
   wire [63:0] data_io_in_bits_wdata_hi_lo = {data_io_in_bits_wdata_dataout_23_value_5_0,
     data_io_in_bits_wdata_dataout_22_value_5_0,data_io_in_bits_wdata_dataout_21_value_5_0,
     data_io_in_bits_wdata_dataout_20_value_5_0,data_io_in_bits_wdata_dataout_19_value_5_0,
     data_io_in_bits_wdata_dataout_18_value_5_0,data_io_in_bits_wdata_dataout_17_value_5_0,
-    data_io_in_bits_wdata_dataout_16_value_5_0}; // @[VLdSt.scala 57:13]
+    data_io_in_bits_wdata_dataout_16_value_5_0}; // @[VLdSt.scala 60:13]
   wire [127:0] data_io_in_bits_wdata_hi = {data_io_in_bits_wdata_dataout_31_value_5_0,
     data_io_in_bits_wdata_dataout_30_value_5_0,data_io_in_bits_wdata_dataout_29_value_5_0,
     data_io_in_bits_wdata_dataout_28_value_5_0,data_io_in_bits_wdata_dataout_27_value_5_0,
     data_io_in_bits_wdata_dataout_26_value_5_0,data_io_in_bits_wdata_dataout_25_value_5_0,
-    data_io_in_bits_wdata_dataout_24_value_5_0,data_io_in_bits_wdata_hi_lo}; // @[VLdSt.scala 57:13]
+    data_io_in_bits_wdata_dataout_24_value_5_0,data_io_in_bits_wdata_hi_lo}; // @[VLdSt.scala 60:13]
   wire [7:0] data_io_in_bits_wmask_lo_lo = {rdataWmask_7,rdataWmask_6,rdataWmask_5,rdataWmask_4,rdataWmask_3,
-    rdataWmask_2,rdataWmask_1,rdataWmask_0}; // @[VLdSt.scala 239:68]
+    rdataWmask_2,rdataWmask_1,rdataWmask_0}; // @[VLdSt.scala 242:68]
   wire [15:0] data_io_in_bits_wmask_lo = {rdataWmask_15,rdataWmask_14,rdataWmask_13,rdataWmask_12,rdataWmask_11,
-    rdataWmask_10,rdataWmask_9,rdataWmask_8,data_io_in_bits_wmask_lo_lo}; // @[VLdSt.scala 239:68]
+    rdataWmask_10,rdataWmask_9,rdataWmask_8,data_io_in_bits_wmask_lo_lo}; // @[VLdSt.scala 242:68]
   wire [7:0] data_io_in_bits_wmask_hi_lo = {rdataWmask_23,rdataWmask_22,rdataWmask_21,rdataWmask_20,rdataWmask_19,
-    rdataWmask_18,rdataWmask_17,rdataWmask_16}; // @[VLdSt.scala 239:68]
+    rdataWmask_18,rdataWmask_17,rdataWmask_16}; // @[VLdSt.scala 242:68]
   wire [31:0] _data_io_in_bits_wmask_T = {rdataWmask_31,rdataWmask_30,rdataWmask_29,rdataWmask_28,rdataWmask_27,
-    rdataWmask_26,rdataWmask_25,rdataWmask_24,data_io_in_bits_wmask_hi_lo,data_io_in_bits_wmask_lo}; // @[VLdSt.scala 239:68]
-  wire  data_io_in_bits_wmask_datain_0 = _data_io_in_bits_wmask_T[0]; // @[VLdSt.scala 47:24]
-  wire  data_io_in_bits_wmask_datain_1 = _data_io_in_bits_wmask_T[1]; // @[VLdSt.scala 47:24]
-  wire  data_io_in_bits_wmask_datain_2 = _data_io_in_bits_wmask_T[2]; // @[VLdSt.scala 47:24]
-  wire  data_io_in_bits_wmask_datain_3 = _data_io_in_bits_wmask_T[3]; // @[VLdSt.scala 47:24]
-  wire  data_io_in_bits_wmask_datain_4 = _data_io_in_bits_wmask_T[4]; // @[VLdSt.scala 47:24]
-  wire  data_io_in_bits_wmask_datain_5 = _data_io_in_bits_wmask_T[5]; // @[VLdSt.scala 47:24]
-  wire  data_io_in_bits_wmask_datain_6 = _data_io_in_bits_wmask_T[6]; // @[VLdSt.scala 47:24]
-  wire  data_io_in_bits_wmask_datain_7 = _data_io_in_bits_wmask_T[7]; // @[VLdSt.scala 47:24]
-  wire  data_io_in_bits_wmask_datain_8 = _data_io_in_bits_wmask_T[8]; // @[VLdSt.scala 47:24]
-  wire  data_io_in_bits_wmask_datain_9 = _data_io_in_bits_wmask_T[9]; // @[VLdSt.scala 47:24]
-  wire  data_io_in_bits_wmask_datain_10 = _data_io_in_bits_wmask_T[10]; // @[VLdSt.scala 47:24]
-  wire  data_io_in_bits_wmask_datain_11 = _data_io_in_bits_wmask_T[11]; // @[VLdSt.scala 47:24]
-  wire  data_io_in_bits_wmask_datain_12 = _data_io_in_bits_wmask_T[12]; // @[VLdSt.scala 47:24]
-  wire  data_io_in_bits_wmask_datain_13 = _data_io_in_bits_wmask_T[13]; // @[VLdSt.scala 47:24]
-  wire  data_io_in_bits_wmask_datain_14 = _data_io_in_bits_wmask_T[14]; // @[VLdSt.scala 47:24]
-  wire  data_io_in_bits_wmask_datain_15 = _data_io_in_bits_wmask_T[15]; // @[VLdSt.scala 47:24]
-  wire  data_io_in_bits_wmask_datain_16 = _data_io_in_bits_wmask_T[16]; // @[VLdSt.scala 47:24]
-  wire  data_io_in_bits_wmask_datain_17 = _data_io_in_bits_wmask_T[17]; // @[VLdSt.scala 47:24]
-  wire  data_io_in_bits_wmask_datain_18 = _data_io_in_bits_wmask_T[18]; // @[VLdSt.scala 47:24]
-  wire  data_io_in_bits_wmask_datain_19 = _data_io_in_bits_wmask_T[19]; // @[VLdSt.scala 47:24]
-  wire  data_io_in_bits_wmask_datain_20 = _data_io_in_bits_wmask_T[20]; // @[VLdSt.scala 47:24]
-  wire  data_io_in_bits_wmask_datain_21 = _data_io_in_bits_wmask_T[21]; // @[VLdSt.scala 47:24]
-  wire  data_io_in_bits_wmask_datain_22 = _data_io_in_bits_wmask_T[22]; // @[VLdSt.scala 47:24]
-  wire  data_io_in_bits_wmask_datain_23 = _data_io_in_bits_wmask_T[23]; // @[VLdSt.scala 47:24]
-  wire  data_io_in_bits_wmask_datain_24 = _data_io_in_bits_wmask_T[24]; // @[VLdSt.scala 47:24]
-  wire  data_io_in_bits_wmask_datain_25 = _data_io_in_bits_wmask_T[25]; // @[VLdSt.scala 47:24]
-  wire  data_io_in_bits_wmask_datain_26 = _data_io_in_bits_wmask_T[26]; // @[VLdSt.scala 47:24]
-  wire  data_io_in_bits_wmask_datain_27 = _data_io_in_bits_wmask_T[27]; // @[VLdSt.scala 47:24]
-  wire  data_io_in_bits_wmask_datain_28 = _data_io_in_bits_wmask_T[28]; // @[VLdSt.scala 47:24]
-  wire  data_io_in_bits_wmask_datain_29 = _data_io_in_bits_wmask_T[29]; // @[VLdSt.scala 47:24]
-  wire  data_io_in_bits_wmask_datain_30 = _data_io_in_bits_wmask_T[30]; // @[VLdSt.scala 47:24]
-  wire  data_io_in_bits_wmask_datain_31 = _data_io_in_bits_wmask_T[31]; // @[VLdSt.scala 47:24]
-  wire [4:0] data_io_in_bits_wmask_idx = 5'h0 - rdataAddr; // @[VLdSt.scala 52:53]
+    rdataWmask_26,rdataWmask_25,rdataWmask_24,data_io_in_bits_wmask_hi_lo,data_io_in_bits_wmask_lo}; // @[VLdSt.scala 242:68]
+  wire  data_io_in_bits_wmask_datain_0 = _data_io_in_bits_wmask_T[0]; // @[VLdSt.scala 50:24]
+  wire  data_io_in_bits_wmask_datain_1 = _data_io_in_bits_wmask_T[1]; // @[VLdSt.scala 50:24]
+  wire  data_io_in_bits_wmask_datain_2 = _data_io_in_bits_wmask_T[2]; // @[VLdSt.scala 50:24]
+  wire  data_io_in_bits_wmask_datain_3 = _data_io_in_bits_wmask_T[3]; // @[VLdSt.scala 50:24]
+  wire  data_io_in_bits_wmask_datain_4 = _data_io_in_bits_wmask_T[4]; // @[VLdSt.scala 50:24]
+  wire  data_io_in_bits_wmask_datain_5 = _data_io_in_bits_wmask_T[5]; // @[VLdSt.scala 50:24]
+  wire  data_io_in_bits_wmask_datain_6 = _data_io_in_bits_wmask_T[6]; // @[VLdSt.scala 50:24]
+  wire  data_io_in_bits_wmask_datain_7 = _data_io_in_bits_wmask_T[7]; // @[VLdSt.scala 50:24]
+  wire  data_io_in_bits_wmask_datain_8 = _data_io_in_bits_wmask_T[8]; // @[VLdSt.scala 50:24]
+  wire  data_io_in_bits_wmask_datain_9 = _data_io_in_bits_wmask_T[9]; // @[VLdSt.scala 50:24]
+  wire  data_io_in_bits_wmask_datain_10 = _data_io_in_bits_wmask_T[10]; // @[VLdSt.scala 50:24]
+  wire  data_io_in_bits_wmask_datain_11 = _data_io_in_bits_wmask_T[11]; // @[VLdSt.scala 50:24]
+  wire  data_io_in_bits_wmask_datain_12 = _data_io_in_bits_wmask_T[12]; // @[VLdSt.scala 50:24]
+  wire  data_io_in_bits_wmask_datain_13 = _data_io_in_bits_wmask_T[13]; // @[VLdSt.scala 50:24]
+  wire  data_io_in_bits_wmask_datain_14 = _data_io_in_bits_wmask_T[14]; // @[VLdSt.scala 50:24]
+  wire  data_io_in_bits_wmask_datain_15 = _data_io_in_bits_wmask_T[15]; // @[VLdSt.scala 50:24]
+  wire  data_io_in_bits_wmask_datain_16 = _data_io_in_bits_wmask_T[16]; // @[VLdSt.scala 50:24]
+  wire  data_io_in_bits_wmask_datain_17 = _data_io_in_bits_wmask_T[17]; // @[VLdSt.scala 50:24]
+  wire  data_io_in_bits_wmask_datain_18 = _data_io_in_bits_wmask_T[18]; // @[VLdSt.scala 50:24]
+  wire  data_io_in_bits_wmask_datain_19 = _data_io_in_bits_wmask_T[19]; // @[VLdSt.scala 50:24]
+  wire  data_io_in_bits_wmask_datain_20 = _data_io_in_bits_wmask_T[20]; // @[VLdSt.scala 50:24]
+  wire  data_io_in_bits_wmask_datain_21 = _data_io_in_bits_wmask_T[21]; // @[VLdSt.scala 50:24]
+  wire  data_io_in_bits_wmask_datain_22 = _data_io_in_bits_wmask_T[22]; // @[VLdSt.scala 50:24]
+  wire  data_io_in_bits_wmask_datain_23 = _data_io_in_bits_wmask_T[23]; // @[VLdSt.scala 50:24]
+  wire  data_io_in_bits_wmask_datain_24 = _data_io_in_bits_wmask_T[24]; // @[VLdSt.scala 50:24]
+  wire  data_io_in_bits_wmask_datain_25 = _data_io_in_bits_wmask_T[25]; // @[VLdSt.scala 50:24]
+  wire  data_io_in_bits_wmask_datain_26 = _data_io_in_bits_wmask_T[26]; // @[VLdSt.scala 50:24]
+  wire  data_io_in_bits_wmask_datain_27 = _data_io_in_bits_wmask_T[27]; // @[VLdSt.scala 50:24]
+  wire  data_io_in_bits_wmask_datain_28 = _data_io_in_bits_wmask_T[28]; // @[VLdSt.scala 50:24]
+  wire  data_io_in_bits_wmask_datain_29 = _data_io_in_bits_wmask_T[29]; // @[VLdSt.scala 50:24]
+  wire  data_io_in_bits_wmask_datain_30 = _data_io_in_bits_wmask_T[30]; // @[VLdSt.scala 50:24]
+  wire  data_io_in_bits_wmask_datain_31 = _data_io_in_bits_wmask_T[31]; // @[VLdSt.scala 50:24]
+  wire [4:0] data_io_in_bits_wmask_idx = 5'h0 - rdataAddr; // @[VLdSt.scala 55:52]
   wire  data_io_in_bits_wmask_dataout_0_value__0 = 5'h0 == data_io_in_bits_wmask_idx & data_io_in_bits_wmask_datain_0; // @[Library.scala 101:22]
   wire  data_io_in_bits_wmask_dataout_0_value__1 = 5'h1 == data_io_in_bits_wmask_idx & data_io_in_bits_wmask_datain_1; // @[Library.scala 101:22]
   wire  data_io_in_bits_wmask_dataout_0_value__2 = 5'h2 == data_io_in_bits_wmask_idx & data_io_in_bits_wmask_datain_2; // @[Library.scala 101:22]
@@ -92558,7 +83000,7 @@
     data_io_in_bits_wmask_dataout_0_value_3_3; // @[Library.scala 115:37]
   wire  data_io_in_bits_wmask_dataout_0_value_5_0 = data_io_in_bits_wmask_dataout_0_value_4_0 |
     data_io_in_bits_wmask_dataout_0_value_4_1; // @[Library.scala 115:37]
-  wire [4:0] data_io_in_bits_wmask_idx_1 = 5'h1 - rdataAddr; // @[VLdSt.scala 52:53]
+  wire [4:0] data_io_in_bits_wmask_idx_1 = 5'h1 - rdataAddr; // @[VLdSt.scala 55:52]
   wire  data_io_in_bits_wmask_dataout_1_value__0 = 5'h0 == data_io_in_bits_wmask_idx_1 & data_io_in_bits_wmask_datain_0; // @[Library.scala 101:22]
   wire  data_io_in_bits_wmask_dataout_1_value__1 = 5'h1 == data_io_in_bits_wmask_idx_1 & data_io_in_bits_wmask_datain_1; // @[Library.scala 101:22]
   wire  data_io_in_bits_wmask_dataout_1_value__2 = 5'h2 == data_io_in_bits_wmask_idx_1 & data_io_in_bits_wmask_datain_2; // @[Library.scala 101:22]
@@ -92675,7 +83117,7 @@
     data_io_in_bits_wmask_dataout_1_value_3_3; // @[Library.scala 115:37]
   wire  data_io_in_bits_wmask_dataout_1_value_5_0 = data_io_in_bits_wmask_dataout_1_value_4_0 |
     data_io_in_bits_wmask_dataout_1_value_4_1; // @[Library.scala 115:37]
-  wire [4:0] data_io_in_bits_wmask_idx_2 = 5'h2 - rdataAddr; // @[VLdSt.scala 52:53]
+  wire [4:0] data_io_in_bits_wmask_idx_2 = 5'h2 - rdataAddr; // @[VLdSt.scala 55:52]
   wire  data_io_in_bits_wmask_dataout_2_value__0 = 5'h0 == data_io_in_bits_wmask_idx_2 & data_io_in_bits_wmask_datain_0; // @[Library.scala 101:22]
   wire  data_io_in_bits_wmask_dataout_2_value__1 = 5'h1 == data_io_in_bits_wmask_idx_2 & data_io_in_bits_wmask_datain_1; // @[Library.scala 101:22]
   wire  data_io_in_bits_wmask_dataout_2_value__2 = 5'h2 == data_io_in_bits_wmask_idx_2 & data_io_in_bits_wmask_datain_2; // @[Library.scala 101:22]
@@ -92792,7 +83234,7 @@
     data_io_in_bits_wmask_dataout_2_value_3_3; // @[Library.scala 115:37]
   wire  data_io_in_bits_wmask_dataout_2_value_5_0 = data_io_in_bits_wmask_dataout_2_value_4_0 |
     data_io_in_bits_wmask_dataout_2_value_4_1; // @[Library.scala 115:37]
-  wire [4:0] data_io_in_bits_wmask_idx_3 = 5'h3 - rdataAddr; // @[VLdSt.scala 52:53]
+  wire [4:0] data_io_in_bits_wmask_idx_3 = 5'h3 - rdataAddr; // @[VLdSt.scala 55:52]
   wire  data_io_in_bits_wmask_dataout_3_value__0 = 5'h0 == data_io_in_bits_wmask_idx_3 & data_io_in_bits_wmask_datain_0; // @[Library.scala 101:22]
   wire  data_io_in_bits_wmask_dataout_3_value__1 = 5'h1 == data_io_in_bits_wmask_idx_3 & data_io_in_bits_wmask_datain_1; // @[Library.scala 101:22]
   wire  data_io_in_bits_wmask_dataout_3_value__2 = 5'h2 == data_io_in_bits_wmask_idx_3 & data_io_in_bits_wmask_datain_2; // @[Library.scala 101:22]
@@ -92909,7 +83351,7 @@
     data_io_in_bits_wmask_dataout_3_value_3_3; // @[Library.scala 115:37]
   wire  data_io_in_bits_wmask_dataout_3_value_5_0 = data_io_in_bits_wmask_dataout_3_value_4_0 |
     data_io_in_bits_wmask_dataout_3_value_4_1; // @[Library.scala 115:37]
-  wire [4:0] data_io_in_bits_wmask_idx_4 = 5'h4 - rdataAddr; // @[VLdSt.scala 52:53]
+  wire [4:0] data_io_in_bits_wmask_idx_4 = 5'h4 - rdataAddr; // @[VLdSt.scala 55:52]
   wire  data_io_in_bits_wmask_dataout_4_value__0 = 5'h0 == data_io_in_bits_wmask_idx_4 & data_io_in_bits_wmask_datain_0; // @[Library.scala 101:22]
   wire  data_io_in_bits_wmask_dataout_4_value__1 = 5'h1 == data_io_in_bits_wmask_idx_4 & data_io_in_bits_wmask_datain_1; // @[Library.scala 101:22]
   wire  data_io_in_bits_wmask_dataout_4_value__2 = 5'h2 == data_io_in_bits_wmask_idx_4 & data_io_in_bits_wmask_datain_2; // @[Library.scala 101:22]
@@ -93026,7 +83468,7 @@
     data_io_in_bits_wmask_dataout_4_value_3_3; // @[Library.scala 115:37]
   wire  data_io_in_bits_wmask_dataout_4_value_5_0 = data_io_in_bits_wmask_dataout_4_value_4_0 |
     data_io_in_bits_wmask_dataout_4_value_4_1; // @[Library.scala 115:37]
-  wire [4:0] data_io_in_bits_wmask_idx_5 = 5'h5 - rdataAddr; // @[VLdSt.scala 52:53]
+  wire [4:0] data_io_in_bits_wmask_idx_5 = 5'h5 - rdataAddr; // @[VLdSt.scala 55:52]
   wire  data_io_in_bits_wmask_dataout_5_value__0 = 5'h0 == data_io_in_bits_wmask_idx_5 & data_io_in_bits_wmask_datain_0; // @[Library.scala 101:22]
   wire  data_io_in_bits_wmask_dataout_5_value__1 = 5'h1 == data_io_in_bits_wmask_idx_5 & data_io_in_bits_wmask_datain_1; // @[Library.scala 101:22]
   wire  data_io_in_bits_wmask_dataout_5_value__2 = 5'h2 == data_io_in_bits_wmask_idx_5 & data_io_in_bits_wmask_datain_2; // @[Library.scala 101:22]
@@ -93143,7 +83585,7 @@
     data_io_in_bits_wmask_dataout_5_value_3_3; // @[Library.scala 115:37]
   wire  data_io_in_bits_wmask_dataout_5_value_5_0 = data_io_in_bits_wmask_dataout_5_value_4_0 |
     data_io_in_bits_wmask_dataout_5_value_4_1; // @[Library.scala 115:37]
-  wire [4:0] data_io_in_bits_wmask_idx_6 = 5'h6 - rdataAddr; // @[VLdSt.scala 52:53]
+  wire [4:0] data_io_in_bits_wmask_idx_6 = 5'h6 - rdataAddr; // @[VLdSt.scala 55:52]
   wire  data_io_in_bits_wmask_dataout_6_value__0 = 5'h0 == data_io_in_bits_wmask_idx_6 & data_io_in_bits_wmask_datain_0; // @[Library.scala 101:22]
   wire  data_io_in_bits_wmask_dataout_6_value__1 = 5'h1 == data_io_in_bits_wmask_idx_6 & data_io_in_bits_wmask_datain_1; // @[Library.scala 101:22]
   wire  data_io_in_bits_wmask_dataout_6_value__2 = 5'h2 == data_io_in_bits_wmask_idx_6 & data_io_in_bits_wmask_datain_2; // @[Library.scala 101:22]
@@ -93260,7 +83702,7 @@
     data_io_in_bits_wmask_dataout_6_value_3_3; // @[Library.scala 115:37]
   wire  data_io_in_bits_wmask_dataout_6_value_5_0 = data_io_in_bits_wmask_dataout_6_value_4_0 |
     data_io_in_bits_wmask_dataout_6_value_4_1; // @[Library.scala 115:37]
-  wire [4:0] data_io_in_bits_wmask_idx_7 = 5'h7 - rdataAddr; // @[VLdSt.scala 52:53]
+  wire [4:0] data_io_in_bits_wmask_idx_7 = 5'h7 - rdataAddr; // @[VLdSt.scala 55:52]
   wire  data_io_in_bits_wmask_dataout_7_value__0 = 5'h0 == data_io_in_bits_wmask_idx_7 & data_io_in_bits_wmask_datain_0; // @[Library.scala 101:22]
   wire  data_io_in_bits_wmask_dataout_7_value__1 = 5'h1 == data_io_in_bits_wmask_idx_7 & data_io_in_bits_wmask_datain_1; // @[Library.scala 101:22]
   wire  data_io_in_bits_wmask_dataout_7_value__2 = 5'h2 == data_io_in_bits_wmask_idx_7 & data_io_in_bits_wmask_datain_2; // @[Library.scala 101:22]
@@ -93377,7 +83819,7 @@
     data_io_in_bits_wmask_dataout_7_value_3_3; // @[Library.scala 115:37]
   wire  data_io_in_bits_wmask_dataout_7_value_5_0 = data_io_in_bits_wmask_dataout_7_value_4_0 |
     data_io_in_bits_wmask_dataout_7_value_4_1; // @[Library.scala 115:37]
-  wire [4:0] data_io_in_bits_wmask_idx_8 = 5'h8 - rdataAddr; // @[VLdSt.scala 52:53]
+  wire [4:0] data_io_in_bits_wmask_idx_8 = 5'h8 - rdataAddr; // @[VLdSt.scala 55:52]
   wire  data_io_in_bits_wmask_dataout_8_value__0 = 5'h0 == data_io_in_bits_wmask_idx_8 & data_io_in_bits_wmask_datain_0; // @[Library.scala 101:22]
   wire  data_io_in_bits_wmask_dataout_8_value__1 = 5'h1 == data_io_in_bits_wmask_idx_8 & data_io_in_bits_wmask_datain_1; // @[Library.scala 101:22]
   wire  data_io_in_bits_wmask_dataout_8_value__2 = 5'h2 == data_io_in_bits_wmask_idx_8 & data_io_in_bits_wmask_datain_2; // @[Library.scala 101:22]
@@ -93494,7 +83936,7 @@
     data_io_in_bits_wmask_dataout_8_value_3_3; // @[Library.scala 115:37]
   wire  data_io_in_bits_wmask_dataout_8_value_5_0 = data_io_in_bits_wmask_dataout_8_value_4_0 |
     data_io_in_bits_wmask_dataout_8_value_4_1; // @[Library.scala 115:37]
-  wire [4:0] data_io_in_bits_wmask_idx_9 = 5'h9 - rdataAddr; // @[VLdSt.scala 52:53]
+  wire [4:0] data_io_in_bits_wmask_idx_9 = 5'h9 - rdataAddr; // @[VLdSt.scala 55:52]
   wire  data_io_in_bits_wmask_dataout_9_value__0 = 5'h0 == data_io_in_bits_wmask_idx_9 & data_io_in_bits_wmask_datain_0; // @[Library.scala 101:22]
   wire  data_io_in_bits_wmask_dataout_9_value__1 = 5'h1 == data_io_in_bits_wmask_idx_9 & data_io_in_bits_wmask_datain_1; // @[Library.scala 101:22]
   wire  data_io_in_bits_wmask_dataout_9_value__2 = 5'h2 == data_io_in_bits_wmask_idx_9 & data_io_in_bits_wmask_datain_2; // @[Library.scala 101:22]
@@ -93611,7 +84053,7 @@
     data_io_in_bits_wmask_dataout_9_value_3_3; // @[Library.scala 115:37]
   wire  data_io_in_bits_wmask_dataout_9_value_5_0 = data_io_in_bits_wmask_dataout_9_value_4_0 |
     data_io_in_bits_wmask_dataout_9_value_4_1; // @[Library.scala 115:37]
-  wire [4:0] data_io_in_bits_wmask_idx_10 = 5'ha - rdataAddr; // @[VLdSt.scala 52:53]
+  wire [4:0] data_io_in_bits_wmask_idx_10 = 5'ha - rdataAddr; // @[VLdSt.scala 55:52]
   wire  data_io_in_bits_wmask_dataout_10_value__0 = 5'h0 == data_io_in_bits_wmask_idx_10 &
     data_io_in_bits_wmask_datain_0; // @[Library.scala 101:22]
   wire  data_io_in_bits_wmask_dataout_10_value__1 = 5'h1 == data_io_in_bits_wmask_idx_10 &
@@ -93738,7 +84180,7 @@
     data_io_in_bits_wmask_dataout_10_value_3_3; // @[Library.scala 115:37]
   wire  data_io_in_bits_wmask_dataout_10_value_5_0 = data_io_in_bits_wmask_dataout_10_value_4_0 |
     data_io_in_bits_wmask_dataout_10_value_4_1; // @[Library.scala 115:37]
-  wire [4:0] data_io_in_bits_wmask_idx_11 = 5'hb - rdataAddr; // @[VLdSt.scala 52:53]
+  wire [4:0] data_io_in_bits_wmask_idx_11 = 5'hb - rdataAddr; // @[VLdSt.scala 55:52]
   wire  data_io_in_bits_wmask_dataout_11_value__0 = 5'h0 == data_io_in_bits_wmask_idx_11 &
     data_io_in_bits_wmask_datain_0; // @[Library.scala 101:22]
   wire  data_io_in_bits_wmask_dataout_11_value__1 = 5'h1 == data_io_in_bits_wmask_idx_11 &
@@ -93865,7 +84307,7 @@
     data_io_in_bits_wmask_dataout_11_value_3_3; // @[Library.scala 115:37]
   wire  data_io_in_bits_wmask_dataout_11_value_5_0 = data_io_in_bits_wmask_dataout_11_value_4_0 |
     data_io_in_bits_wmask_dataout_11_value_4_1; // @[Library.scala 115:37]
-  wire [4:0] data_io_in_bits_wmask_idx_12 = 5'hc - rdataAddr; // @[VLdSt.scala 52:53]
+  wire [4:0] data_io_in_bits_wmask_idx_12 = 5'hc - rdataAddr; // @[VLdSt.scala 55:52]
   wire  data_io_in_bits_wmask_dataout_12_value__0 = 5'h0 == data_io_in_bits_wmask_idx_12 &
     data_io_in_bits_wmask_datain_0; // @[Library.scala 101:22]
   wire  data_io_in_bits_wmask_dataout_12_value__1 = 5'h1 == data_io_in_bits_wmask_idx_12 &
@@ -93992,7 +84434,7 @@
     data_io_in_bits_wmask_dataout_12_value_3_3; // @[Library.scala 115:37]
   wire  data_io_in_bits_wmask_dataout_12_value_5_0 = data_io_in_bits_wmask_dataout_12_value_4_0 |
     data_io_in_bits_wmask_dataout_12_value_4_1; // @[Library.scala 115:37]
-  wire [4:0] data_io_in_bits_wmask_idx_13 = 5'hd - rdataAddr; // @[VLdSt.scala 52:53]
+  wire [4:0] data_io_in_bits_wmask_idx_13 = 5'hd - rdataAddr; // @[VLdSt.scala 55:52]
   wire  data_io_in_bits_wmask_dataout_13_value__0 = 5'h0 == data_io_in_bits_wmask_idx_13 &
     data_io_in_bits_wmask_datain_0; // @[Library.scala 101:22]
   wire  data_io_in_bits_wmask_dataout_13_value__1 = 5'h1 == data_io_in_bits_wmask_idx_13 &
@@ -94119,7 +84561,7 @@
     data_io_in_bits_wmask_dataout_13_value_3_3; // @[Library.scala 115:37]
   wire  data_io_in_bits_wmask_dataout_13_value_5_0 = data_io_in_bits_wmask_dataout_13_value_4_0 |
     data_io_in_bits_wmask_dataout_13_value_4_1; // @[Library.scala 115:37]
-  wire [4:0] data_io_in_bits_wmask_idx_14 = 5'he - rdataAddr; // @[VLdSt.scala 52:53]
+  wire [4:0] data_io_in_bits_wmask_idx_14 = 5'he - rdataAddr; // @[VLdSt.scala 55:52]
   wire  data_io_in_bits_wmask_dataout_14_value__0 = 5'h0 == data_io_in_bits_wmask_idx_14 &
     data_io_in_bits_wmask_datain_0; // @[Library.scala 101:22]
   wire  data_io_in_bits_wmask_dataout_14_value__1 = 5'h1 == data_io_in_bits_wmask_idx_14 &
@@ -94246,7 +84688,7 @@
     data_io_in_bits_wmask_dataout_14_value_3_3; // @[Library.scala 115:37]
   wire  data_io_in_bits_wmask_dataout_14_value_5_0 = data_io_in_bits_wmask_dataout_14_value_4_0 |
     data_io_in_bits_wmask_dataout_14_value_4_1; // @[Library.scala 115:37]
-  wire [4:0] data_io_in_bits_wmask_idx_15 = 5'hf - rdataAddr; // @[VLdSt.scala 52:53]
+  wire [4:0] data_io_in_bits_wmask_idx_15 = 5'hf - rdataAddr; // @[VLdSt.scala 55:52]
   wire  data_io_in_bits_wmask_dataout_15_value__0 = 5'h0 == data_io_in_bits_wmask_idx_15 &
     data_io_in_bits_wmask_datain_0; // @[Library.scala 101:22]
   wire  data_io_in_bits_wmask_dataout_15_value__1 = 5'h1 == data_io_in_bits_wmask_idx_15 &
@@ -94373,7 +84815,7 @@
     data_io_in_bits_wmask_dataout_15_value_3_3; // @[Library.scala 115:37]
   wire  data_io_in_bits_wmask_dataout_15_value_5_0 = data_io_in_bits_wmask_dataout_15_value_4_0 |
     data_io_in_bits_wmask_dataout_15_value_4_1; // @[Library.scala 115:37]
-  wire [4:0] data_io_in_bits_wmask_idx_16 = 5'h10 - rdataAddr; // @[VLdSt.scala 52:53]
+  wire [4:0] data_io_in_bits_wmask_idx_16 = 5'h10 - rdataAddr; // @[VLdSt.scala 55:52]
   wire  data_io_in_bits_wmask_dataout_16_value__0 = 5'h0 == data_io_in_bits_wmask_idx_16 &
     data_io_in_bits_wmask_datain_0; // @[Library.scala 101:22]
   wire  data_io_in_bits_wmask_dataout_16_value__1 = 5'h1 == data_io_in_bits_wmask_idx_16 &
@@ -94500,7 +84942,7 @@
     data_io_in_bits_wmask_dataout_16_value_3_3; // @[Library.scala 115:37]
   wire  data_io_in_bits_wmask_dataout_16_value_5_0 = data_io_in_bits_wmask_dataout_16_value_4_0 |
     data_io_in_bits_wmask_dataout_16_value_4_1; // @[Library.scala 115:37]
-  wire [4:0] data_io_in_bits_wmask_idx_17 = 5'h11 - rdataAddr; // @[VLdSt.scala 52:53]
+  wire [4:0] data_io_in_bits_wmask_idx_17 = 5'h11 - rdataAddr; // @[VLdSt.scala 55:52]
   wire  data_io_in_bits_wmask_dataout_17_value__0 = 5'h0 == data_io_in_bits_wmask_idx_17 &
     data_io_in_bits_wmask_datain_0; // @[Library.scala 101:22]
   wire  data_io_in_bits_wmask_dataout_17_value__1 = 5'h1 == data_io_in_bits_wmask_idx_17 &
@@ -94627,7 +85069,7 @@
     data_io_in_bits_wmask_dataout_17_value_3_3; // @[Library.scala 115:37]
   wire  data_io_in_bits_wmask_dataout_17_value_5_0 = data_io_in_bits_wmask_dataout_17_value_4_0 |
     data_io_in_bits_wmask_dataout_17_value_4_1; // @[Library.scala 115:37]
-  wire [4:0] data_io_in_bits_wmask_idx_18 = 5'h12 - rdataAddr; // @[VLdSt.scala 52:53]
+  wire [4:0] data_io_in_bits_wmask_idx_18 = 5'h12 - rdataAddr; // @[VLdSt.scala 55:52]
   wire  data_io_in_bits_wmask_dataout_18_value__0 = 5'h0 == data_io_in_bits_wmask_idx_18 &
     data_io_in_bits_wmask_datain_0; // @[Library.scala 101:22]
   wire  data_io_in_bits_wmask_dataout_18_value__1 = 5'h1 == data_io_in_bits_wmask_idx_18 &
@@ -94754,7 +85196,7 @@
     data_io_in_bits_wmask_dataout_18_value_3_3; // @[Library.scala 115:37]
   wire  data_io_in_bits_wmask_dataout_18_value_5_0 = data_io_in_bits_wmask_dataout_18_value_4_0 |
     data_io_in_bits_wmask_dataout_18_value_4_1; // @[Library.scala 115:37]
-  wire [4:0] data_io_in_bits_wmask_idx_19 = 5'h13 - rdataAddr; // @[VLdSt.scala 52:53]
+  wire [4:0] data_io_in_bits_wmask_idx_19 = 5'h13 - rdataAddr; // @[VLdSt.scala 55:52]
   wire  data_io_in_bits_wmask_dataout_19_value__0 = 5'h0 == data_io_in_bits_wmask_idx_19 &
     data_io_in_bits_wmask_datain_0; // @[Library.scala 101:22]
   wire  data_io_in_bits_wmask_dataout_19_value__1 = 5'h1 == data_io_in_bits_wmask_idx_19 &
@@ -94881,7 +85323,7 @@
     data_io_in_bits_wmask_dataout_19_value_3_3; // @[Library.scala 115:37]
   wire  data_io_in_bits_wmask_dataout_19_value_5_0 = data_io_in_bits_wmask_dataout_19_value_4_0 |
     data_io_in_bits_wmask_dataout_19_value_4_1; // @[Library.scala 115:37]
-  wire [4:0] data_io_in_bits_wmask_idx_20 = 5'h14 - rdataAddr; // @[VLdSt.scala 52:53]
+  wire [4:0] data_io_in_bits_wmask_idx_20 = 5'h14 - rdataAddr; // @[VLdSt.scala 55:52]
   wire  data_io_in_bits_wmask_dataout_20_value__0 = 5'h0 == data_io_in_bits_wmask_idx_20 &
     data_io_in_bits_wmask_datain_0; // @[Library.scala 101:22]
   wire  data_io_in_bits_wmask_dataout_20_value__1 = 5'h1 == data_io_in_bits_wmask_idx_20 &
@@ -95008,7 +85450,7 @@
     data_io_in_bits_wmask_dataout_20_value_3_3; // @[Library.scala 115:37]
   wire  data_io_in_bits_wmask_dataout_20_value_5_0 = data_io_in_bits_wmask_dataout_20_value_4_0 |
     data_io_in_bits_wmask_dataout_20_value_4_1; // @[Library.scala 115:37]
-  wire [4:0] data_io_in_bits_wmask_idx_21 = 5'h15 - rdataAddr; // @[VLdSt.scala 52:53]
+  wire [4:0] data_io_in_bits_wmask_idx_21 = 5'h15 - rdataAddr; // @[VLdSt.scala 55:52]
   wire  data_io_in_bits_wmask_dataout_21_value__0 = 5'h0 == data_io_in_bits_wmask_idx_21 &
     data_io_in_bits_wmask_datain_0; // @[Library.scala 101:22]
   wire  data_io_in_bits_wmask_dataout_21_value__1 = 5'h1 == data_io_in_bits_wmask_idx_21 &
@@ -95135,7 +85577,7 @@
     data_io_in_bits_wmask_dataout_21_value_3_3; // @[Library.scala 115:37]
   wire  data_io_in_bits_wmask_dataout_21_value_5_0 = data_io_in_bits_wmask_dataout_21_value_4_0 |
     data_io_in_bits_wmask_dataout_21_value_4_1; // @[Library.scala 115:37]
-  wire [4:0] data_io_in_bits_wmask_idx_22 = 5'h16 - rdataAddr; // @[VLdSt.scala 52:53]
+  wire [4:0] data_io_in_bits_wmask_idx_22 = 5'h16 - rdataAddr; // @[VLdSt.scala 55:52]
   wire  data_io_in_bits_wmask_dataout_22_value__0 = 5'h0 == data_io_in_bits_wmask_idx_22 &
     data_io_in_bits_wmask_datain_0; // @[Library.scala 101:22]
   wire  data_io_in_bits_wmask_dataout_22_value__1 = 5'h1 == data_io_in_bits_wmask_idx_22 &
@@ -95262,7 +85704,7 @@
     data_io_in_bits_wmask_dataout_22_value_3_3; // @[Library.scala 115:37]
   wire  data_io_in_bits_wmask_dataout_22_value_5_0 = data_io_in_bits_wmask_dataout_22_value_4_0 |
     data_io_in_bits_wmask_dataout_22_value_4_1; // @[Library.scala 115:37]
-  wire [4:0] data_io_in_bits_wmask_idx_23 = 5'h17 - rdataAddr; // @[VLdSt.scala 52:53]
+  wire [4:0] data_io_in_bits_wmask_idx_23 = 5'h17 - rdataAddr; // @[VLdSt.scala 55:52]
   wire  data_io_in_bits_wmask_dataout_23_value__0 = 5'h0 == data_io_in_bits_wmask_idx_23 &
     data_io_in_bits_wmask_datain_0; // @[Library.scala 101:22]
   wire  data_io_in_bits_wmask_dataout_23_value__1 = 5'h1 == data_io_in_bits_wmask_idx_23 &
@@ -95389,7 +85831,7 @@
     data_io_in_bits_wmask_dataout_23_value_3_3; // @[Library.scala 115:37]
   wire  data_io_in_bits_wmask_dataout_23_value_5_0 = data_io_in_bits_wmask_dataout_23_value_4_0 |
     data_io_in_bits_wmask_dataout_23_value_4_1; // @[Library.scala 115:37]
-  wire [4:0] data_io_in_bits_wmask_idx_24 = 5'h18 - rdataAddr; // @[VLdSt.scala 52:53]
+  wire [4:0] data_io_in_bits_wmask_idx_24 = 5'h18 - rdataAddr; // @[VLdSt.scala 55:52]
   wire  data_io_in_bits_wmask_dataout_24_value__0 = 5'h0 == data_io_in_bits_wmask_idx_24 &
     data_io_in_bits_wmask_datain_0; // @[Library.scala 101:22]
   wire  data_io_in_bits_wmask_dataout_24_value__1 = 5'h1 == data_io_in_bits_wmask_idx_24 &
@@ -95516,7 +85958,7 @@
     data_io_in_bits_wmask_dataout_24_value_3_3; // @[Library.scala 115:37]
   wire  data_io_in_bits_wmask_dataout_24_value_5_0 = data_io_in_bits_wmask_dataout_24_value_4_0 |
     data_io_in_bits_wmask_dataout_24_value_4_1; // @[Library.scala 115:37]
-  wire [4:0] data_io_in_bits_wmask_idx_25 = 5'h19 - rdataAddr; // @[VLdSt.scala 52:53]
+  wire [4:0] data_io_in_bits_wmask_idx_25 = 5'h19 - rdataAddr; // @[VLdSt.scala 55:52]
   wire  data_io_in_bits_wmask_dataout_25_value__0 = 5'h0 == data_io_in_bits_wmask_idx_25 &
     data_io_in_bits_wmask_datain_0; // @[Library.scala 101:22]
   wire  data_io_in_bits_wmask_dataout_25_value__1 = 5'h1 == data_io_in_bits_wmask_idx_25 &
@@ -95643,7 +86085,7 @@
     data_io_in_bits_wmask_dataout_25_value_3_3; // @[Library.scala 115:37]
   wire  data_io_in_bits_wmask_dataout_25_value_5_0 = data_io_in_bits_wmask_dataout_25_value_4_0 |
     data_io_in_bits_wmask_dataout_25_value_4_1; // @[Library.scala 115:37]
-  wire [4:0] data_io_in_bits_wmask_idx_26 = 5'h1a - rdataAddr; // @[VLdSt.scala 52:53]
+  wire [4:0] data_io_in_bits_wmask_idx_26 = 5'h1a - rdataAddr; // @[VLdSt.scala 55:52]
   wire  data_io_in_bits_wmask_dataout_26_value__0 = 5'h0 == data_io_in_bits_wmask_idx_26 &
     data_io_in_bits_wmask_datain_0; // @[Library.scala 101:22]
   wire  data_io_in_bits_wmask_dataout_26_value__1 = 5'h1 == data_io_in_bits_wmask_idx_26 &
@@ -95770,7 +86212,7 @@
     data_io_in_bits_wmask_dataout_26_value_3_3; // @[Library.scala 115:37]
   wire  data_io_in_bits_wmask_dataout_26_value_5_0 = data_io_in_bits_wmask_dataout_26_value_4_0 |
     data_io_in_bits_wmask_dataout_26_value_4_1; // @[Library.scala 115:37]
-  wire [4:0] data_io_in_bits_wmask_idx_27 = 5'h1b - rdataAddr; // @[VLdSt.scala 52:53]
+  wire [4:0] data_io_in_bits_wmask_idx_27 = 5'h1b - rdataAddr; // @[VLdSt.scala 55:52]
   wire  data_io_in_bits_wmask_dataout_27_value__0 = 5'h0 == data_io_in_bits_wmask_idx_27 &
     data_io_in_bits_wmask_datain_0; // @[Library.scala 101:22]
   wire  data_io_in_bits_wmask_dataout_27_value__1 = 5'h1 == data_io_in_bits_wmask_idx_27 &
@@ -95897,7 +86339,7 @@
     data_io_in_bits_wmask_dataout_27_value_3_3; // @[Library.scala 115:37]
   wire  data_io_in_bits_wmask_dataout_27_value_5_0 = data_io_in_bits_wmask_dataout_27_value_4_0 |
     data_io_in_bits_wmask_dataout_27_value_4_1; // @[Library.scala 115:37]
-  wire [4:0] data_io_in_bits_wmask_idx_28 = 5'h1c - rdataAddr; // @[VLdSt.scala 52:53]
+  wire [4:0] data_io_in_bits_wmask_idx_28 = 5'h1c - rdataAddr; // @[VLdSt.scala 55:52]
   wire  data_io_in_bits_wmask_dataout_28_value__0 = 5'h0 == data_io_in_bits_wmask_idx_28 &
     data_io_in_bits_wmask_datain_0; // @[Library.scala 101:22]
   wire  data_io_in_bits_wmask_dataout_28_value__1 = 5'h1 == data_io_in_bits_wmask_idx_28 &
@@ -96024,7 +86466,7 @@
     data_io_in_bits_wmask_dataout_28_value_3_3; // @[Library.scala 115:37]
   wire  data_io_in_bits_wmask_dataout_28_value_5_0 = data_io_in_bits_wmask_dataout_28_value_4_0 |
     data_io_in_bits_wmask_dataout_28_value_4_1; // @[Library.scala 115:37]
-  wire [4:0] data_io_in_bits_wmask_idx_29 = 5'h1d - rdataAddr; // @[VLdSt.scala 52:53]
+  wire [4:0] data_io_in_bits_wmask_idx_29 = 5'h1d - rdataAddr; // @[VLdSt.scala 55:52]
   wire  data_io_in_bits_wmask_dataout_29_value__0 = 5'h0 == data_io_in_bits_wmask_idx_29 &
     data_io_in_bits_wmask_datain_0; // @[Library.scala 101:22]
   wire  data_io_in_bits_wmask_dataout_29_value__1 = 5'h1 == data_io_in_bits_wmask_idx_29 &
@@ -96151,7 +86593,7 @@
     data_io_in_bits_wmask_dataout_29_value_3_3; // @[Library.scala 115:37]
   wire  data_io_in_bits_wmask_dataout_29_value_5_0 = data_io_in_bits_wmask_dataout_29_value_4_0 |
     data_io_in_bits_wmask_dataout_29_value_4_1; // @[Library.scala 115:37]
-  wire [4:0] data_io_in_bits_wmask_idx_30 = 5'h1e - rdataAddr; // @[VLdSt.scala 52:53]
+  wire [4:0] data_io_in_bits_wmask_idx_30 = 5'h1e - rdataAddr; // @[VLdSt.scala 55:52]
   wire  data_io_in_bits_wmask_dataout_30_value__0 = 5'h0 == data_io_in_bits_wmask_idx_30 &
     data_io_in_bits_wmask_datain_0; // @[Library.scala 101:22]
   wire  data_io_in_bits_wmask_dataout_30_value__1 = 5'h1 == data_io_in_bits_wmask_idx_30 &
@@ -96278,7 +86720,7 @@
     data_io_in_bits_wmask_dataout_30_value_3_3; // @[Library.scala 115:37]
   wire  data_io_in_bits_wmask_dataout_30_value_5_0 = data_io_in_bits_wmask_dataout_30_value_4_0 |
     data_io_in_bits_wmask_dataout_30_value_4_1; // @[Library.scala 115:37]
-  wire [4:0] data_io_in_bits_wmask_idx_31 = 5'h1f - rdataAddr; // @[VLdSt.scala 52:53]
+  wire [4:0] data_io_in_bits_wmask_idx_31 = 5'h1f - rdataAddr; // @[VLdSt.scala 55:52]
   wire  data_io_in_bits_wmask_dataout_31_value__0 = 5'h0 == data_io_in_bits_wmask_idx_31 &
     data_io_in_bits_wmask_datain_0; // @[Library.scala 101:22]
   wire  data_io_in_bits_wmask_dataout_31_value__1 = 5'h1 == data_io_in_bits_wmask_idx_31 &
@@ -96409,128 +86851,128 @@
     data_io_in_bits_wmask_dataout_6_value_5_0,data_io_in_bits_wmask_dataout_5_value_5_0,
     data_io_in_bits_wmask_dataout_4_value_5_0,data_io_in_bits_wmask_dataout_3_value_5_0,
     data_io_in_bits_wmask_dataout_2_value_5_0,data_io_in_bits_wmask_dataout_1_value_5_0,
-    data_io_in_bits_wmask_dataout_0_value_5_0}; // @[VLdSt.scala 57:13]
+    data_io_in_bits_wmask_dataout_0_value_5_0}; // @[VLdSt.scala 60:13]
   wire [15:0] data_io_in_bits_wmask_lo_1 = {data_io_in_bits_wmask_dataout_15_value_5_0,
     data_io_in_bits_wmask_dataout_14_value_5_0,data_io_in_bits_wmask_dataout_13_value_5_0,
     data_io_in_bits_wmask_dataout_12_value_5_0,data_io_in_bits_wmask_dataout_11_value_5_0,
     data_io_in_bits_wmask_dataout_10_value_5_0,data_io_in_bits_wmask_dataout_9_value_5_0,
-    data_io_in_bits_wmask_dataout_8_value_5_0,data_io_in_bits_wmask_lo_lo_1}; // @[VLdSt.scala 57:13]
+    data_io_in_bits_wmask_dataout_8_value_5_0,data_io_in_bits_wmask_lo_lo_1}; // @[VLdSt.scala 60:13]
   wire [7:0] data_io_in_bits_wmask_hi_lo_1 = {data_io_in_bits_wmask_dataout_23_value_5_0,
     data_io_in_bits_wmask_dataout_22_value_5_0,data_io_in_bits_wmask_dataout_21_value_5_0,
     data_io_in_bits_wmask_dataout_20_value_5_0,data_io_in_bits_wmask_dataout_19_value_5_0,
     data_io_in_bits_wmask_dataout_18_value_5_0,data_io_in_bits_wmask_dataout_17_value_5_0,
-    data_io_in_bits_wmask_dataout_16_value_5_0}; // @[VLdSt.scala 57:13]
+    data_io_in_bits_wmask_dataout_16_value_5_0}; // @[VLdSt.scala 60:13]
   wire [15:0] data_io_in_bits_wmask_hi_1 = {data_io_in_bits_wmask_dataout_31_value_5_0,
     data_io_in_bits_wmask_dataout_30_value_5_0,data_io_in_bits_wmask_dataout_29_value_5_0,
     data_io_in_bits_wmask_dataout_28_value_5_0,data_io_in_bits_wmask_dataout_27_value_5_0,
     data_io_in_bits_wmask_dataout_26_value_5_0,data_io_in_bits_wmask_dataout_25_value_5_0,
-    data_io_in_bits_wmask_dataout_24_value_5_0,data_io_in_bits_wmask_hi_lo_1}; // @[VLdSt.scala 57:13]
-  wire  _ctrl_io_out_ready_T = ~ctrl_io_out_bits_write; // @[VLdSt.scala 242:63]
-  wire  _ctrl_io_out_ready_T_1 = data_io_out_valid | ~ctrl_io_out_bits_write; // @[VLdSt.scala 242:60]
-  reg  wdataEn; // @[VLdSt.scala 264:24]
-  wire  _maskb_1_T = 6'h1 < wrega_io_out_bits_size; // @[VLdSt.scala 284:27]
+    data_io_in_bits_wmask_dataout_24_value_5_0,data_io_in_bits_wmask_hi_lo_1}; // @[VLdSt.scala 60:13]
+  wire  _ctrl_io_out_ready_T = ~ctrl_io_out_bits_write; // @[VLdSt.scala 245:63]
+  wire  _ctrl_io_out_ready_T_1 = data_io_out_valid | ~ctrl_io_out_bits_write; // @[VLdSt.scala 245:60]
+  reg  wdataEn; // @[VLdSt.scala 267:24]
+  wire  _maskb_1_T = 6'h1 < wrega_io_out_bits_size; // @[VLdSt.scala 287:27]
   wire [7:0] maskb_1 = _maskb_1_T ? 8'hff : 8'h0; // @[Library.scala 8:8]
-  wire  _maskb_0_T = 6'h0 < wrega_io_out_bits_size; // @[VLdSt.scala 284:27]
+  wire  _maskb_0_T = 6'h0 < wrega_io_out_bits_size; // @[VLdSt.scala 287:27]
   wire [7:0] maskb_0 = _maskb_0_T ? 8'hff : 8'h0; // @[Library.scala 8:8]
-  wire  _maskb_3_T = 6'h3 < wrega_io_out_bits_size; // @[VLdSt.scala 284:27]
+  wire  _maskb_3_T = 6'h3 < wrega_io_out_bits_size; // @[VLdSt.scala 287:27]
   wire [7:0] maskb_3 = _maskb_3_T ? 8'hff : 8'h0; // @[Library.scala 8:8]
-  wire  _maskb_2_T = 6'h2 < wrega_io_out_bits_size; // @[VLdSt.scala 284:27]
+  wire  _maskb_2_T = 6'h2 < wrega_io_out_bits_size; // @[VLdSt.scala 287:27]
   wire [7:0] maskb_2 = _maskb_2_T ? 8'hff : 8'h0; // @[Library.scala 8:8]
-  wire  _maskb_5_T = 6'h5 < wrega_io_out_bits_size; // @[VLdSt.scala 284:27]
+  wire  _maskb_5_T = 6'h5 < wrega_io_out_bits_size; // @[VLdSt.scala 287:27]
   wire [7:0] maskb_5 = _maskb_5_T ? 8'hff : 8'h0; // @[Library.scala 8:8]
-  wire  _maskb_4_T = 6'h4 < wrega_io_out_bits_size; // @[VLdSt.scala 284:27]
+  wire  _maskb_4_T = 6'h4 < wrega_io_out_bits_size; // @[VLdSt.scala 287:27]
   wire [7:0] maskb_4 = _maskb_4_T ? 8'hff : 8'h0; // @[Library.scala 8:8]
-  wire  _maskb_7_T = 6'h7 < wrega_io_out_bits_size; // @[VLdSt.scala 284:27]
+  wire  _maskb_7_T = 6'h7 < wrega_io_out_bits_size; // @[VLdSt.scala 287:27]
   wire [7:0] maskb_7 = _maskb_7_T ? 8'hff : 8'h0; // @[Library.scala 8:8]
-  wire  _maskb_6_T = 6'h6 < wrega_io_out_bits_size; // @[VLdSt.scala 284:27]
+  wire  _maskb_6_T = 6'h6 < wrega_io_out_bits_size; // @[VLdSt.scala 287:27]
   wire [7:0] maskb_6 = _maskb_6_T ? 8'hff : 8'h0; // @[Library.scala 8:8]
-  wire [63:0] mask_lo_lo = {maskb_7,maskb_6,maskb_5,maskb_4,maskb_3,maskb_2,maskb_1,maskb_0}; // @[VLdSt.scala 281:20]
-  wire  _maskb_9_T = 6'h9 < wrega_io_out_bits_size; // @[VLdSt.scala 284:27]
+  wire [63:0] mask_lo_lo = {maskb_7,maskb_6,maskb_5,maskb_4,maskb_3,maskb_2,maskb_1,maskb_0}; // @[VLdSt.scala 284:20]
+  wire  _maskb_9_T = 6'h9 < wrega_io_out_bits_size; // @[VLdSt.scala 287:27]
   wire [7:0] maskb_9 = _maskb_9_T ? 8'hff : 8'h0; // @[Library.scala 8:8]
-  wire  _maskb_8_T = 6'h8 < wrega_io_out_bits_size; // @[VLdSt.scala 284:27]
+  wire  _maskb_8_T = 6'h8 < wrega_io_out_bits_size; // @[VLdSt.scala 287:27]
   wire [7:0] maskb_8 = _maskb_8_T ? 8'hff : 8'h0; // @[Library.scala 8:8]
-  wire  _maskb_11_T = 6'hb < wrega_io_out_bits_size; // @[VLdSt.scala 284:27]
+  wire  _maskb_11_T = 6'hb < wrega_io_out_bits_size; // @[VLdSt.scala 287:27]
   wire [7:0] maskb_11 = _maskb_11_T ? 8'hff : 8'h0; // @[Library.scala 8:8]
-  wire  _maskb_10_T = 6'ha < wrega_io_out_bits_size; // @[VLdSt.scala 284:27]
+  wire  _maskb_10_T = 6'ha < wrega_io_out_bits_size; // @[VLdSt.scala 287:27]
   wire [7:0] maskb_10 = _maskb_10_T ? 8'hff : 8'h0; // @[Library.scala 8:8]
-  wire  _maskb_13_T = 6'hd < wrega_io_out_bits_size; // @[VLdSt.scala 284:27]
+  wire  _maskb_13_T = 6'hd < wrega_io_out_bits_size; // @[VLdSt.scala 287:27]
   wire [7:0] maskb_13 = _maskb_13_T ? 8'hff : 8'h0; // @[Library.scala 8:8]
-  wire  _maskb_12_T = 6'hc < wrega_io_out_bits_size; // @[VLdSt.scala 284:27]
+  wire  _maskb_12_T = 6'hc < wrega_io_out_bits_size; // @[VLdSt.scala 287:27]
   wire [7:0] maskb_12 = _maskb_12_T ? 8'hff : 8'h0; // @[Library.scala 8:8]
-  wire  _maskb_15_T = 6'hf < wrega_io_out_bits_size; // @[VLdSt.scala 284:27]
+  wire  _maskb_15_T = 6'hf < wrega_io_out_bits_size; // @[VLdSt.scala 287:27]
   wire [7:0] maskb_15 = _maskb_15_T ? 8'hff : 8'h0; // @[Library.scala 8:8]
-  wire  _maskb_14_T = 6'he < wrega_io_out_bits_size; // @[VLdSt.scala 284:27]
+  wire  _maskb_14_T = 6'he < wrega_io_out_bits_size; // @[VLdSt.scala 287:27]
   wire [7:0] maskb_14 = _maskb_14_T ? 8'hff : 8'h0; // @[Library.scala 8:8]
-  wire [127:0] mask_lo = {maskb_15,maskb_14,maskb_13,maskb_12,maskb_11,maskb_10,maskb_9,maskb_8,mask_lo_lo}; // @[VLdSt.scala 281:20]
-  wire  _maskb_17_T = 6'h11 < wrega_io_out_bits_size; // @[VLdSt.scala 284:27]
+  wire [127:0] mask_lo = {maskb_15,maskb_14,maskb_13,maskb_12,maskb_11,maskb_10,maskb_9,maskb_8,mask_lo_lo}; // @[VLdSt.scala 284:20]
+  wire  _maskb_17_T = 6'h11 < wrega_io_out_bits_size; // @[VLdSt.scala 287:27]
   wire [7:0] maskb_17 = _maskb_17_T ? 8'hff : 8'h0; // @[Library.scala 8:8]
-  wire  _maskb_16_T = 6'h10 < wrega_io_out_bits_size; // @[VLdSt.scala 284:27]
+  wire  _maskb_16_T = 6'h10 < wrega_io_out_bits_size; // @[VLdSt.scala 287:27]
   wire [7:0] maskb_16 = _maskb_16_T ? 8'hff : 8'h0; // @[Library.scala 8:8]
-  wire  _maskb_19_T = 6'h13 < wrega_io_out_bits_size; // @[VLdSt.scala 284:27]
+  wire  _maskb_19_T = 6'h13 < wrega_io_out_bits_size; // @[VLdSt.scala 287:27]
   wire [7:0] maskb_19 = _maskb_19_T ? 8'hff : 8'h0; // @[Library.scala 8:8]
-  wire  _maskb_18_T = 6'h12 < wrega_io_out_bits_size; // @[VLdSt.scala 284:27]
+  wire  _maskb_18_T = 6'h12 < wrega_io_out_bits_size; // @[VLdSt.scala 287:27]
   wire [7:0] maskb_18 = _maskb_18_T ? 8'hff : 8'h0; // @[Library.scala 8:8]
-  wire  _maskb_21_T = 6'h15 < wrega_io_out_bits_size; // @[VLdSt.scala 284:27]
+  wire  _maskb_21_T = 6'h15 < wrega_io_out_bits_size; // @[VLdSt.scala 287:27]
   wire [7:0] maskb_21 = _maskb_21_T ? 8'hff : 8'h0; // @[Library.scala 8:8]
-  wire  _maskb_20_T = 6'h14 < wrega_io_out_bits_size; // @[VLdSt.scala 284:27]
+  wire  _maskb_20_T = 6'h14 < wrega_io_out_bits_size; // @[VLdSt.scala 287:27]
   wire [7:0] maskb_20 = _maskb_20_T ? 8'hff : 8'h0; // @[Library.scala 8:8]
-  wire  _maskb_23_T = 6'h17 < wrega_io_out_bits_size; // @[VLdSt.scala 284:27]
+  wire  _maskb_23_T = 6'h17 < wrega_io_out_bits_size; // @[VLdSt.scala 287:27]
   wire [7:0] maskb_23 = _maskb_23_T ? 8'hff : 8'h0; // @[Library.scala 8:8]
-  wire  _maskb_22_T = 6'h16 < wrega_io_out_bits_size; // @[VLdSt.scala 284:27]
+  wire  _maskb_22_T = 6'h16 < wrega_io_out_bits_size; // @[VLdSt.scala 287:27]
   wire [7:0] maskb_22 = _maskb_22_T ? 8'hff : 8'h0; // @[Library.scala 8:8]
-  wire [63:0] mask_hi_lo = {maskb_23,maskb_22,maskb_21,maskb_20,maskb_19,maskb_18,maskb_17,maskb_16}; // @[VLdSt.scala 281:20]
-  wire  _maskb_25_T = 6'h19 < wrega_io_out_bits_size; // @[VLdSt.scala 284:27]
+  wire [63:0] mask_hi_lo = {maskb_23,maskb_22,maskb_21,maskb_20,maskb_19,maskb_18,maskb_17,maskb_16}; // @[VLdSt.scala 284:20]
+  wire  _maskb_25_T = 6'h19 < wrega_io_out_bits_size; // @[VLdSt.scala 287:27]
   wire [7:0] maskb_25 = _maskb_25_T ? 8'hff : 8'h0; // @[Library.scala 8:8]
-  wire  _maskb_24_T = 6'h18 < wrega_io_out_bits_size; // @[VLdSt.scala 284:27]
+  wire  _maskb_24_T = 6'h18 < wrega_io_out_bits_size; // @[VLdSt.scala 287:27]
   wire [7:0] maskb_24 = _maskb_24_T ? 8'hff : 8'h0; // @[Library.scala 8:8]
-  wire  _maskb_27_T = 6'h1b < wrega_io_out_bits_size; // @[VLdSt.scala 284:27]
+  wire  _maskb_27_T = 6'h1b < wrega_io_out_bits_size; // @[VLdSt.scala 287:27]
   wire [7:0] maskb_27 = _maskb_27_T ? 8'hff : 8'h0; // @[Library.scala 8:8]
-  wire  _maskb_26_T = 6'h1a < wrega_io_out_bits_size; // @[VLdSt.scala 284:27]
+  wire  _maskb_26_T = 6'h1a < wrega_io_out_bits_size; // @[VLdSt.scala 287:27]
   wire [7:0] maskb_26 = _maskb_26_T ? 8'hff : 8'h0; // @[Library.scala 8:8]
-  wire  _maskb_29_T = 6'h1d < wrega_io_out_bits_size; // @[VLdSt.scala 284:27]
+  wire  _maskb_29_T = 6'h1d < wrega_io_out_bits_size; // @[VLdSt.scala 287:27]
   wire [7:0] maskb_29 = _maskb_29_T ? 8'hff : 8'h0; // @[Library.scala 8:8]
-  wire  _maskb_28_T = 6'h1c < wrega_io_out_bits_size; // @[VLdSt.scala 284:27]
+  wire  _maskb_28_T = 6'h1c < wrega_io_out_bits_size; // @[VLdSt.scala 287:27]
   wire [7:0] maskb_28 = _maskb_28_T ? 8'hff : 8'h0; // @[Library.scala 8:8]
-  wire  _maskb_31_T = 6'h1f < wrega_io_out_bits_size; // @[VLdSt.scala 284:27]
+  wire  _maskb_31_T = 6'h1f < wrega_io_out_bits_size; // @[VLdSt.scala 287:27]
   wire [7:0] maskb_31 = _maskb_31_T ? 8'hff : 8'h0; // @[Library.scala 8:8]
-  wire  _maskb_30_T = 6'h1e < wrega_io_out_bits_size; // @[VLdSt.scala 284:27]
+  wire  _maskb_30_T = 6'h1e < wrega_io_out_bits_size; // @[VLdSt.scala 287:27]
   wire [7:0] maskb_30 = _maskb_30_T ? 8'hff : 8'h0; // @[Library.scala 8:8]
-  wire [255:0] mask = {maskb_31,maskb_30,maskb_29,maskb_28,maskb_27,maskb_26,maskb_25,maskb_24,mask_hi_lo,mask_lo}; // @[VLdSt.scala 281:20]
-  wire [7:0] io_write_data_datain_0 = wregd_io_out_bits[7:0]; // @[VLdSt.scala 47:24]
-  wire [7:0] io_write_data_datain_1 = wregd_io_out_bits[15:8]; // @[VLdSt.scala 47:24]
-  wire [7:0] io_write_data_datain_2 = wregd_io_out_bits[23:16]; // @[VLdSt.scala 47:24]
-  wire [7:0] io_write_data_datain_3 = wregd_io_out_bits[31:24]; // @[VLdSt.scala 47:24]
-  wire [7:0] io_write_data_datain_4 = wregd_io_out_bits[39:32]; // @[VLdSt.scala 47:24]
-  wire [7:0] io_write_data_datain_5 = wregd_io_out_bits[47:40]; // @[VLdSt.scala 47:24]
-  wire [7:0] io_write_data_datain_6 = wregd_io_out_bits[55:48]; // @[VLdSt.scala 47:24]
-  wire [7:0] io_write_data_datain_7 = wregd_io_out_bits[63:56]; // @[VLdSt.scala 47:24]
-  wire [7:0] io_write_data_datain_8 = wregd_io_out_bits[71:64]; // @[VLdSt.scala 47:24]
-  wire [7:0] io_write_data_datain_9 = wregd_io_out_bits[79:72]; // @[VLdSt.scala 47:24]
-  wire [7:0] io_write_data_datain_10 = wregd_io_out_bits[87:80]; // @[VLdSt.scala 47:24]
-  wire [7:0] io_write_data_datain_11 = wregd_io_out_bits[95:88]; // @[VLdSt.scala 47:24]
-  wire [7:0] io_write_data_datain_12 = wregd_io_out_bits[103:96]; // @[VLdSt.scala 47:24]
-  wire [7:0] io_write_data_datain_13 = wregd_io_out_bits[111:104]; // @[VLdSt.scala 47:24]
-  wire [7:0] io_write_data_datain_14 = wregd_io_out_bits[119:112]; // @[VLdSt.scala 47:24]
-  wire [7:0] io_write_data_datain_15 = wregd_io_out_bits[127:120]; // @[VLdSt.scala 47:24]
-  wire [7:0] io_write_data_datain_16 = wregd_io_out_bits[135:128]; // @[VLdSt.scala 47:24]
-  wire [7:0] io_write_data_datain_17 = wregd_io_out_bits[143:136]; // @[VLdSt.scala 47:24]
-  wire [7:0] io_write_data_datain_18 = wregd_io_out_bits[151:144]; // @[VLdSt.scala 47:24]
-  wire [7:0] io_write_data_datain_19 = wregd_io_out_bits[159:152]; // @[VLdSt.scala 47:24]
-  wire [7:0] io_write_data_datain_20 = wregd_io_out_bits[167:160]; // @[VLdSt.scala 47:24]
-  wire [7:0] io_write_data_datain_21 = wregd_io_out_bits[175:168]; // @[VLdSt.scala 47:24]
-  wire [7:0] io_write_data_datain_22 = wregd_io_out_bits[183:176]; // @[VLdSt.scala 47:24]
-  wire [7:0] io_write_data_datain_23 = wregd_io_out_bits[191:184]; // @[VLdSt.scala 47:24]
-  wire [7:0] io_write_data_datain_24 = wregd_io_out_bits[199:192]; // @[VLdSt.scala 47:24]
-  wire [7:0] io_write_data_datain_25 = wregd_io_out_bits[207:200]; // @[VLdSt.scala 47:24]
-  wire [7:0] io_write_data_datain_26 = wregd_io_out_bits[215:208]; // @[VLdSt.scala 47:24]
-  wire [7:0] io_write_data_datain_27 = wregd_io_out_bits[223:216]; // @[VLdSt.scala 47:24]
-  wire [7:0] io_write_data_datain_28 = wregd_io_out_bits[231:224]; // @[VLdSt.scala 47:24]
-  wire [7:0] io_write_data_datain_29 = wregd_io_out_bits[239:232]; // @[VLdSt.scala 47:24]
-  wire [7:0] io_write_data_datain_30 = wregd_io_out_bits[247:240]; // @[VLdSt.scala 47:24]
-  wire [7:0] io_write_data_datain_31 = wregd_io_out_bits[255:248]; // @[VLdSt.scala 47:24]
-  wire [4:0] io_write_data_index = wrega_io_out_bits_addr; // @[VLdSt.scala 50:21]
-  wire [5:0] _io_write_data_idx_T = {{1'd0}, io_write_data_index}; // @[VLdSt.scala 52:36]
-  wire [4:0] io_write_data_idx = _io_write_data_idx_T[4:0]; // @[VLdSt.scala 52:36]
+  wire [255:0] mask = {maskb_31,maskb_30,maskb_29,maskb_28,maskb_27,maskb_26,maskb_25,maskb_24,mask_hi_lo,mask_lo}; // @[VLdSt.scala 284:20]
+  wire [7:0] io_write_data_datain_0 = wregd_io_out_bits[7:0]; // @[VLdSt.scala 50:24]
+  wire [7:0] io_write_data_datain_1 = wregd_io_out_bits[15:8]; // @[VLdSt.scala 50:24]
+  wire [7:0] io_write_data_datain_2 = wregd_io_out_bits[23:16]; // @[VLdSt.scala 50:24]
+  wire [7:0] io_write_data_datain_3 = wregd_io_out_bits[31:24]; // @[VLdSt.scala 50:24]
+  wire [7:0] io_write_data_datain_4 = wregd_io_out_bits[39:32]; // @[VLdSt.scala 50:24]
+  wire [7:0] io_write_data_datain_5 = wregd_io_out_bits[47:40]; // @[VLdSt.scala 50:24]
+  wire [7:0] io_write_data_datain_6 = wregd_io_out_bits[55:48]; // @[VLdSt.scala 50:24]
+  wire [7:0] io_write_data_datain_7 = wregd_io_out_bits[63:56]; // @[VLdSt.scala 50:24]
+  wire [7:0] io_write_data_datain_8 = wregd_io_out_bits[71:64]; // @[VLdSt.scala 50:24]
+  wire [7:0] io_write_data_datain_9 = wregd_io_out_bits[79:72]; // @[VLdSt.scala 50:24]
+  wire [7:0] io_write_data_datain_10 = wregd_io_out_bits[87:80]; // @[VLdSt.scala 50:24]
+  wire [7:0] io_write_data_datain_11 = wregd_io_out_bits[95:88]; // @[VLdSt.scala 50:24]
+  wire [7:0] io_write_data_datain_12 = wregd_io_out_bits[103:96]; // @[VLdSt.scala 50:24]
+  wire [7:0] io_write_data_datain_13 = wregd_io_out_bits[111:104]; // @[VLdSt.scala 50:24]
+  wire [7:0] io_write_data_datain_14 = wregd_io_out_bits[119:112]; // @[VLdSt.scala 50:24]
+  wire [7:0] io_write_data_datain_15 = wregd_io_out_bits[127:120]; // @[VLdSt.scala 50:24]
+  wire [7:0] io_write_data_datain_16 = wregd_io_out_bits[135:128]; // @[VLdSt.scala 50:24]
+  wire [7:0] io_write_data_datain_17 = wregd_io_out_bits[143:136]; // @[VLdSt.scala 50:24]
+  wire [7:0] io_write_data_datain_18 = wregd_io_out_bits[151:144]; // @[VLdSt.scala 50:24]
+  wire [7:0] io_write_data_datain_19 = wregd_io_out_bits[159:152]; // @[VLdSt.scala 50:24]
+  wire [7:0] io_write_data_datain_20 = wregd_io_out_bits[167:160]; // @[VLdSt.scala 50:24]
+  wire [7:0] io_write_data_datain_21 = wregd_io_out_bits[175:168]; // @[VLdSt.scala 50:24]
+  wire [7:0] io_write_data_datain_22 = wregd_io_out_bits[183:176]; // @[VLdSt.scala 50:24]
+  wire [7:0] io_write_data_datain_23 = wregd_io_out_bits[191:184]; // @[VLdSt.scala 50:24]
+  wire [7:0] io_write_data_datain_24 = wregd_io_out_bits[199:192]; // @[VLdSt.scala 50:24]
+  wire [7:0] io_write_data_datain_25 = wregd_io_out_bits[207:200]; // @[VLdSt.scala 50:24]
+  wire [7:0] io_write_data_datain_26 = wregd_io_out_bits[215:208]; // @[VLdSt.scala 50:24]
+  wire [7:0] io_write_data_datain_27 = wregd_io_out_bits[223:216]; // @[VLdSt.scala 50:24]
+  wire [7:0] io_write_data_datain_28 = wregd_io_out_bits[231:224]; // @[VLdSt.scala 50:24]
+  wire [7:0] io_write_data_datain_29 = wregd_io_out_bits[239:232]; // @[VLdSt.scala 50:24]
+  wire [7:0] io_write_data_datain_30 = wregd_io_out_bits[247:240]; // @[VLdSt.scala 50:24]
+  wire [7:0] io_write_data_datain_31 = wregd_io_out_bits[255:248]; // @[VLdSt.scala 50:24]
+  wire [4:0] io_write_data_index = wrega_io_out_bits_addr; // @[VLdSt.scala 53:21]
+  wire [5:0] _io_write_data_idx_T = {{1'd0}, io_write_data_index}; // @[VLdSt.scala 55:35]
+  wire [4:0] io_write_data_idx = _io_write_data_idx_T[4:0]; // @[VLdSt.scala 55:35]
   wire [7:0] io_write_data_dataout_0_value__0 = 5'h0 == io_write_data_idx ? io_write_data_datain_0 : 8'h0; // @[Library.scala 101:22]
   wire [7:0] io_write_data_dataout_0_value__1 = 5'h1 == io_write_data_idx ? io_write_data_datain_1 : 8'h0; // @[Library.scala 101:22]
   wire [7:0] io_write_data_dataout_0_value__2 = 5'h2 == io_write_data_idx ? io_write_data_datain_2 : 8'h0; // @[Library.scala 101:22]
@@ -96597,7 +87039,7 @@
   wire [7:0] io_write_data_dataout_0_value_4_0 = io_write_data_dataout_0_value_3_0 | io_write_data_dataout_0_value_3_1; // @[Library.scala 115:37]
   wire [7:0] io_write_data_dataout_0_value_4_1 = io_write_data_dataout_0_value_3_2 | io_write_data_dataout_0_value_3_3; // @[Library.scala 115:37]
   wire [7:0] io_write_data_dataout_0_value_5_0 = io_write_data_dataout_0_value_4_0 | io_write_data_dataout_0_value_4_1; // @[Library.scala 115:37]
-  wire [4:0] io_write_data_idx_1 = 5'h1 + io_write_data_index; // @[VLdSt.scala 52:36]
+  wire [4:0] io_write_data_idx_1 = 5'h1 + io_write_data_index; // @[VLdSt.scala 55:35]
   wire [7:0] io_write_data_dataout_1_value__0 = 5'h0 == io_write_data_idx_1 ? io_write_data_datain_0 : 8'h0; // @[Library.scala 101:22]
   wire [7:0] io_write_data_dataout_1_value__1 = 5'h1 == io_write_data_idx_1 ? io_write_data_datain_1 : 8'h0; // @[Library.scala 101:22]
   wire [7:0] io_write_data_dataout_1_value__2 = 5'h2 == io_write_data_idx_1 ? io_write_data_datain_2 : 8'h0; // @[Library.scala 101:22]
@@ -96664,7 +87106,7 @@
   wire [7:0] io_write_data_dataout_1_value_4_0 = io_write_data_dataout_1_value_3_0 | io_write_data_dataout_1_value_3_1; // @[Library.scala 115:37]
   wire [7:0] io_write_data_dataout_1_value_4_1 = io_write_data_dataout_1_value_3_2 | io_write_data_dataout_1_value_3_3; // @[Library.scala 115:37]
   wire [7:0] io_write_data_dataout_1_value_5_0 = io_write_data_dataout_1_value_4_0 | io_write_data_dataout_1_value_4_1; // @[Library.scala 115:37]
-  wire [4:0] io_write_data_idx_2 = 5'h2 + io_write_data_index; // @[VLdSt.scala 52:36]
+  wire [4:0] io_write_data_idx_2 = 5'h2 + io_write_data_index; // @[VLdSt.scala 55:35]
   wire [7:0] io_write_data_dataout_2_value__0 = 5'h0 == io_write_data_idx_2 ? io_write_data_datain_0 : 8'h0; // @[Library.scala 101:22]
   wire [7:0] io_write_data_dataout_2_value__1 = 5'h1 == io_write_data_idx_2 ? io_write_data_datain_1 : 8'h0; // @[Library.scala 101:22]
   wire [7:0] io_write_data_dataout_2_value__2 = 5'h2 == io_write_data_idx_2 ? io_write_data_datain_2 : 8'h0; // @[Library.scala 101:22]
@@ -96731,7 +87173,7 @@
   wire [7:0] io_write_data_dataout_2_value_4_0 = io_write_data_dataout_2_value_3_0 | io_write_data_dataout_2_value_3_1; // @[Library.scala 115:37]
   wire [7:0] io_write_data_dataout_2_value_4_1 = io_write_data_dataout_2_value_3_2 | io_write_data_dataout_2_value_3_3; // @[Library.scala 115:37]
   wire [7:0] io_write_data_dataout_2_value_5_0 = io_write_data_dataout_2_value_4_0 | io_write_data_dataout_2_value_4_1; // @[Library.scala 115:37]
-  wire [4:0] io_write_data_idx_3 = 5'h3 + io_write_data_index; // @[VLdSt.scala 52:36]
+  wire [4:0] io_write_data_idx_3 = 5'h3 + io_write_data_index; // @[VLdSt.scala 55:35]
   wire [7:0] io_write_data_dataout_3_value__0 = 5'h0 == io_write_data_idx_3 ? io_write_data_datain_0 : 8'h0; // @[Library.scala 101:22]
   wire [7:0] io_write_data_dataout_3_value__1 = 5'h1 == io_write_data_idx_3 ? io_write_data_datain_1 : 8'h0; // @[Library.scala 101:22]
   wire [7:0] io_write_data_dataout_3_value__2 = 5'h2 == io_write_data_idx_3 ? io_write_data_datain_2 : 8'h0; // @[Library.scala 101:22]
@@ -96798,7 +87240,7 @@
   wire [7:0] io_write_data_dataout_3_value_4_0 = io_write_data_dataout_3_value_3_0 | io_write_data_dataout_3_value_3_1; // @[Library.scala 115:37]
   wire [7:0] io_write_data_dataout_3_value_4_1 = io_write_data_dataout_3_value_3_2 | io_write_data_dataout_3_value_3_3; // @[Library.scala 115:37]
   wire [7:0] io_write_data_dataout_3_value_5_0 = io_write_data_dataout_3_value_4_0 | io_write_data_dataout_3_value_4_1; // @[Library.scala 115:37]
-  wire [4:0] io_write_data_idx_4 = 5'h4 + io_write_data_index; // @[VLdSt.scala 52:36]
+  wire [4:0] io_write_data_idx_4 = 5'h4 + io_write_data_index; // @[VLdSt.scala 55:35]
   wire [7:0] io_write_data_dataout_4_value__0 = 5'h0 == io_write_data_idx_4 ? io_write_data_datain_0 : 8'h0; // @[Library.scala 101:22]
   wire [7:0] io_write_data_dataout_4_value__1 = 5'h1 == io_write_data_idx_4 ? io_write_data_datain_1 : 8'h0; // @[Library.scala 101:22]
   wire [7:0] io_write_data_dataout_4_value__2 = 5'h2 == io_write_data_idx_4 ? io_write_data_datain_2 : 8'h0; // @[Library.scala 101:22]
@@ -96865,7 +87307,7 @@
   wire [7:0] io_write_data_dataout_4_value_4_0 = io_write_data_dataout_4_value_3_0 | io_write_data_dataout_4_value_3_1; // @[Library.scala 115:37]
   wire [7:0] io_write_data_dataout_4_value_4_1 = io_write_data_dataout_4_value_3_2 | io_write_data_dataout_4_value_3_3; // @[Library.scala 115:37]
   wire [7:0] io_write_data_dataout_4_value_5_0 = io_write_data_dataout_4_value_4_0 | io_write_data_dataout_4_value_4_1; // @[Library.scala 115:37]
-  wire [4:0] io_write_data_idx_5 = 5'h5 + io_write_data_index; // @[VLdSt.scala 52:36]
+  wire [4:0] io_write_data_idx_5 = 5'h5 + io_write_data_index; // @[VLdSt.scala 55:35]
   wire [7:0] io_write_data_dataout_5_value__0 = 5'h0 == io_write_data_idx_5 ? io_write_data_datain_0 : 8'h0; // @[Library.scala 101:22]
   wire [7:0] io_write_data_dataout_5_value__1 = 5'h1 == io_write_data_idx_5 ? io_write_data_datain_1 : 8'h0; // @[Library.scala 101:22]
   wire [7:0] io_write_data_dataout_5_value__2 = 5'h2 == io_write_data_idx_5 ? io_write_data_datain_2 : 8'h0; // @[Library.scala 101:22]
@@ -96932,7 +87374,7 @@
   wire [7:0] io_write_data_dataout_5_value_4_0 = io_write_data_dataout_5_value_3_0 | io_write_data_dataout_5_value_3_1; // @[Library.scala 115:37]
   wire [7:0] io_write_data_dataout_5_value_4_1 = io_write_data_dataout_5_value_3_2 | io_write_data_dataout_5_value_3_3; // @[Library.scala 115:37]
   wire [7:0] io_write_data_dataout_5_value_5_0 = io_write_data_dataout_5_value_4_0 | io_write_data_dataout_5_value_4_1; // @[Library.scala 115:37]
-  wire [4:0] io_write_data_idx_6 = 5'h6 + io_write_data_index; // @[VLdSt.scala 52:36]
+  wire [4:0] io_write_data_idx_6 = 5'h6 + io_write_data_index; // @[VLdSt.scala 55:35]
   wire [7:0] io_write_data_dataout_6_value__0 = 5'h0 == io_write_data_idx_6 ? io_write_data_datain_0 : 8'h0; // @[Library.scala 101:22]
   wire [7:0] io_write_data_dataout_6_value__1 = 5'h1 == io_write_data_idx_6 ? io_write_data_datain_1 : 8'h0; // @[Library.scala 101:22]
   wire [7:0] io_write_data_dataout_6_value__2 = 5'h2 == io_write_data_idx_6 ? io_write_data_datain_2 : 8'h0; // @[Library.scala 101:22]
@@ -96999,7 +87441,7 @@
   wire [7:0] io_write_data_dataout_6_value_4_0 = io_write_data_dataout_6_value_3_0 | io_write_data_dataout_6_value_3_1; // @[Library.scala 115:37]
   wire [7:0] io_write_data_dataout_6_value_4_1 = io_write_data_dataout_6_value_3_2 | io_write_data_dataout_6_value_3_3; // @[Library.scala 115:37]
   wire [7:0] io_write_data_dataout_6_value_5_0 = io_write_data_dataout_6_value_4_0 | io_write_data_dataout_6_value_4_1; // @[Library.scala 115:37]
-  wire [4:0] io_write_data_idx_7 = 5'h7 + io_write_data_index; // @[VLdSt.scala 52:36]
+  wire [4:0] io_write_data_idx_7 = 5'h7 + io_write_data_index; // @[VLdSt.scala 55:35]
   wire [7:0] io_write_data_dataout_7_value__0 = 5'h0 == io_write_data_idx_7 ? io_write_data_datain_0 : 8'h0; // @[Library.scala 101:22]
   wire [7:0] io_write_data_dataout_7_value__1 = 5'h1 == io_write_data_idx_7 ? io_write_data_datain_1 : 8'h0; // @[Library.scala 101:22]
   wire [7:0] io_write_data_dataout_7_value__2 = 5'h2 == io_write_data_idx_7 ? io_write_data_datain_2 : 8'h0; // @[Library.scala 101:22]
@@ -97066,7 +87508,7 @@
   wire [7:0] io_write_data_dataout_7_value_4_0 = io_write_data_dataout_7_value_3_0 | io_write_data_dataout_7_value_3_1; // @[Library.scala 115:37]
   wire [7:0] io_write_data_dataout_7_value_4_1 = io_write_data_dataout_7_value_3_2 | io_write_data_dataout_7_value_3_3; // @[Library.scala 115:37]
   wire [7:0] io_write_data_dataout_7_value_5_0 = io_write_data_dataout_7_value_4_0 | io_write_data_dataout_7_value_4_1; // @[Library.scala 115:37]
-  wire [4:0] io_write_data_idx_8 = 5'h8 + io_write_data_index; // @[VLdSt.scala 52:36]
+  wire [4:0] io_write_data_idx_8 = 5'h8 + io_write_data_index; // @[VLdSt.scala 55:35]
   wire [7:0] io_write_data_dataout_8_value__0 = 5'h0 == io_write_data_idx_8 ? io_write_data_datain_0 : 8'h0; // @[Library.scala 101:22]
   wire [7:0] io_write_data_dataout_8_value__1 = 5'h1 == io_write_data_idx_8 ? io_write_data_datain_1 : 8'h0; // @[Library.scala 101:22]
   wire [7:0] io_write_data_dataout_8_value__2 = 5'h2 == io_write_data_idx_8 ? io_write_data_datain_2 : 8'h0; // @[Library.scala 101:22]
@@ -97133,7 +87575,7 @@
   wire [7:0] io_write_data_dataout_8_value_4_0 = io_write_data_dataout_8_value_3_0 | io_write_data_dataout_8_value_3_1; // @[Library.scala 115:37]
   wire [7:0] io_write_data_dataout_8_value_4_1 = io_write_data_dataout_8_value_3_2 | io_write_data_dataout_8_value_3_3; // @[Library.scala 115:37]
   wire [7:0] io_write_data_dataout_8_value_5_0 = io_write_data_dataout_8_value_4_0 | io_write_data_dataout_8_value_4_1; // @[Library.scala 115:37]
-  wire [4:0] io_write_data_idx_9 = 5'h9 + io_write_data_index; // @[VLdSt.scala 52:36]
+  wire [4:0] io_write_data_idx_9 = 5'h9 + io_write_data_index; // @[VLdSt.scala 55:35]
   wire [7:0] io_write_data_dataout_9_value__0 = 5'h0 == io_write_data_idx_9 ? io_write_data_datain_0 : 8'h0; // @[Library.scala 101:22]
   wire [7:0] io_write_data_dataout_9_value__1 = 5'h1 == io_write_data_idx_9 ? io_write_data_datain_1 : 8'h0; // @[Library.scala 101:22]
   wire [7:0] io_write_data_dataout_9_value__2 = 5'h2 == io_write_data_idx_9 ? io_write_data_datain_2 : 8'h0; // @[Library.scala 101:22]
@@ -97200,7 +87642,7 @@
   wire [7:0] io_write_data_dataout_9_value_4_0 = io_write_data_dataout_9_value_3_0 | io_write_data_dataout_9_value_3_1; // @[Library.scala 115:37]
   wire [7:0] io_write_data_dataout_9_value_4_1 = io_write_data_dataout_9_value_3_2 | io_write_data_dataout_9_value_3_3; // @[Library.scala 115:37]
   wire [7:0] io_write_data_dataout_9_value_5_0 = io_write_data_dataout_9_value_4_0 | io_write_data_dataout_9_value_4_1; // @[Library.scala 115:37]
-  wire [4:0] io_write_data_idx_10 = 5'ha + io_write_data_index; // @[VLdSt.scala 52:36]
+  wire [4:0] io_write_data_idx_10 = 5'ha + io_write_data_index; // @[VLdSt.scala 55:35]
   wire [7:0] io_write_data_dataout_10_value__0 = 5'h0 == io_write_data_idx_10 ? io_write_data_datain_0 : 8'h0; // @[Library.scala 101:22]
   wire [7:0] io_write_data_dataout_10_value__1 = 5'h1 == io_write_data_idx_10 ? io_write_data_datain_1 : 8'h0; // @[Library.scala 101:22]
   wire [7:0] io_write_data_dataout_10_value__2 = 5'h2 == io_write_data_idx_10 ? io_write_data_datain_2 : 8'h0; // @[Library.scala 101:22]
@@ -97290,7 +87732,7 @@
     io_write_data_dataout_10_value_3_3; // @[Library.scala 115:37]
   wire [7:0] io_write_data_dataout_10_value_5_0 = io_write_data_dataout_10_value_4_0 |
     io_write_data_dataout_10_value_4_1; // @[Library.scala 115:37]
-  wire [4:0] io_write_data_idx_11 = 5'hb + io_write_data_index; // @[VLdSt.scala 52:36]
+  wire [4:0] io_write_data_idx_11 = 5'hb + io_write_data_index; // @[VLdSt.scala 55:35]
   wire [7:0] io_write_data_dataout_11_value__0 = 5'h0 == io_write_data_idx_11 ? io_write_data_datain_0 : 8'h0; // @[Library.scala 101:22]
   wire [7:0] io_write_data_dataout_11_value__1 = 5'h1 == io_write_data_idx_11 ? io_write_data_datain_1 : 8'h0; // @[Library.scala 101:22]
   wire [7:0] io_write_data_dataout_11_value__2 = 5'h2 == io_write_data_idx_11 ? io_write_data_datain_2 : 8'h0; // @[Library.scala 101:22]
@@ -97380,7 +87822,7 @@
     io_write_data_dataout_11_value_3_3; // @[Library.scala 115:37]
   wire [7:0] io_write_data_dataout_11_value_5_0 = io_write_data_dataout_11_value_4_0 |
     io_write_data_dataout_11_value_4_1; // @[Library.scala 115:37]
-  wire [4:0] io_write_data_idx_12 = 5'hc + io_write_data_index; // @[VLdSt.scala 52:36]
+  wire [4:0] io_write_data_idx_12 = 5'hc + io_write_data_index; // @[VLdSt.scala 55:35]
   wire [7:0] io_write_data_dataout_12_value__0 = 5'h0 == io_write_data_idx_12 ? io_write_data_datain_0 : 8'h0; // @[Library.scala 101:22]
   wire [7:0] io_write_data_dataout_12_value__1 = 5'h1 == io_write_data_idx_12 ? io_write_data_datain_1 : 8'h0; // @[Library.scala 101:22]
   wire [7:0] io_write_data_dataout_12_value__2 = 5'h2 == io_write_data_idx_12 ? io_write_data_datain_2 : 8'h0; // @[Library.scala 101:22]
@@ -97470,7 +87912,7 @@
     io_write_data_dataout_12_value_3_3; // @[Library.scala 115:37]
   wire [7:0] io_write_data_dataout_12_value_5_0 = io_write_data_dataout_12_value_4_0 |
     io_write_data_dataout_12_value_4_1; // @[Library.scala 115:37]
-  wire [4:0] io_write_data_idx_13 = 5'hd + io_write_data_index; // @[VLdSt.scala 52:36]
+  wire [4:0] io_write_data_idx_13 = 5'hd + io_write_data_index; // @[VLdSt.scala 55:35]
   wire [7:0] io_write_data_dataout_13_value__0 = 5'h0 == io_write_data_idx_13 ? io_write_data_datain_0 : 8'h0; // @[Library.scala 101:22]
   wire [7:0] io_write_data_dataout_13_value__1 = 5'h1 == io_write_data_idx_13 ? io_write_data_datain_1 : 8'h0; // @[Library.scala 101:22]
   wire [7:0] io_write_data_dataout_13_value__2 = 5'h2 == io_write_data_idx_13 ? io_write_data_datain_2 : 8'h0; // @[Library.scala 101:22]
@@ -97560,7 +88002,7 @@
     io_write_data_dataout_13_value_3_3; // @[Library.scala 115:37]
   wire [7:0] io_write_data_dataout_13_value_5_0 = io_write_data_dataout_13_value_4_0 |
     io_write_data_dataout_13_value_4_1; // @[Library.scala 115:37]
-  wire [4:0] io_write_data_idx_14 = 5'he + io_write_data_index; // @[VLdSt.scala 52:36]
+  wire [4:0] io_write_data_idx_14 = 5'he + io_write_data_index; // @[VLdSt.scala 55:35]
   wire [7:0] io_write_data_dataout_14_value__0 = 5'h0 == io_write_data_idx_14 ? io_write_data_datain_0 : 8'h0; // @[Library.scala 101:22]
   wire [7:0] io_write_data_dataout_14_value__1 = 5'h1 == io_write_data_idx_14 ? io_write_data_datain_1 : 8'h0; // @[Library.scala 101:22]
   wire [7:0] io_write_data_dataout_14_value__2 = 5'h2 == io_write_data_idx_14 ? io_write_data_datain_2 : 8'h0; // @[Library.scala 101:22]
@@ -97650,7 +88092,7 @@
     io_write_data_dataout_14_value_3_3; // @[Library.scala 115:37]
   wire [7:0] io_write_data_dataout_14_value_5_0 = io_write_data_dataout_14_value_4_0 |
     io_write_data_dataout_14_value_4_1; // @[Library.scala 115:37]
-  wire [4:0] io_write_data_idx_15 = 5'hf + io_write_data_index; // @[VLdSt.scala 52:36]
+  wire [4:0] io_write_data_idx_15 = 5'hf + io_write_data_index; // @[VLdSt.scala 55:35]
   wire [7:0] io_write_data_dataout_15_value__0 = 5'h0 == io_write_data_idx_15 ? io_write_data_datain_0 : 8'h0; // @[Library.scala 101:22]
   wire [7:0] io_write_data_dataout_15_value__1 = 5'h1 == io_write_data_idx_15 ? io_write_data_datain_1 : 8'h0; // @[Library.scala 101:22]
   wire [7:0] io_write_data_dataout_15_value__2 = 5'h2 == io_write_data_idx_15 ? io_write_data_datain_2 : 8'h0; // @[Library.scala 101:22]
@@ -97740,7 +88182,7 @@
     io_write_data_dataout_15_value_3_3; // @[Library.scala 115:37]
   wire [7:0] io_write_data_dataout_15_value_5_0 = io_write_data_dataout_15_value_4_0 |
     io_write_data_dataout_15_value_4_1; // @[Library.scala 115:37]
-  wire [4:0] io_write_data_idx_16 = 5'h10 + io_write_data_index; // @[VLdSt.scala 52:36]
+  wire [4:0] io_write_data_idx_16 = 5'h10 + io_write_data_index; // @[VLdSt.scala 55:35]
   wire [7:0] io_write_data_dataout_16_value__0 = 5'h0 == io_write_data_idx_16 ? io_write_data_datain_0 : 8'h0; // @[Library.scala 101:22]
   wire [7:0] io_write_data_dataout_16_value__1 = 5'h1 == io_write_data_idx_16 ? io_write_data_datain_1 : 8'h0; // @[Library.scala 101:22]
   wire [7:0] io_write_data_dataout_16_value__2 = 5'h2 == io_write_data_idx_16 ? io_write_data_datain_2 : 8'h0; // @[Library.scala 101:22]
@@ -97830,7 +88272,7 @@
     io_write_data_dataout_16_value_3_3; // @[Library.scala 115:37]
   wire [7:0] io_write_data_dataout_16_value_5_0 = io_write_data_dataout_16_value_4_0 |
     io_write_data_dataout_16_value_4_1; // @[Library.scala 115:37]
-  wire [4:0] io_write_data_idx_17 = 5'h11 + io_write_data_index; // @[VLdSt.scala 52:36]
+  wire [4:0] io_write_data_idx_17 = 5'h11 + io_write_data_index; // @[VLdSt.scala 55:35]
   wire [7:0] io_write_data_dataout_17_value__0 = 5'h0 == io_write_data_idx_17 ? io_write_data_datain_0 : 8'h0; // @[Library.scala 101:22]
   wire [7:0] io_write_data_dataout_17_value__1 = 5'h1 == io_write_data_idx_17 ? io_write_data_datain_1 : 8'h0; // @[Library.scala 101:22]
   wire [7:0] io_write_data_dataout_17_value__2 = 5'h2 == io_write_data_idx_17 ? io_write_data_datain_2 : 8'h0; // @[Library.scala 101:22]
@@ -97920,7 +88362,7 @@
     io_write_data_dataout_17_value_3_3; // @[Library.scala 115:37]
   wire [7:0] io_write_data_dataout_17_value_5_0 = io_write_data_dataout_17_value_4_0 |
     io_write_data_dataout_17_value_4_1; // @[Library.scala 115:37]
-  wire [4:0] io_write_data_idx_18 = 5'h12 + io_write_data_index; // @[VLdSt.scala 52:36]
+  wire [4:0] io_write_data_idx_18 = 5'h12 + io_write_data_index; // @[VLdSt.scala 55:35]
   wire [7:0] io_write_data_dataout_18_value__0 = 5'h0 == io_write_data_idx_18 ? io_write_data_datain_0 : 8'h0; // @[Library.scala 101:22]
   wire [7:0] io_write_data_dataout_18_value__1 = 5'h1 == io_write_data_idx_18 ? io_write_data_datain_1 : 8'h0; // @[Library.scala 101:22]
   wire [7:0] io_write_data_dataout_18_value__2 = 5'h2 == io_write_data_idx_18 ? io_write_data_datain_2 : 8'h0; // @[Library.scala 101:22]
@@ -98010,7 +88452,7 @@
     io_write_data_dataout_18_value_3_3; // @[Library.scala 115:37]
   wire [7:0] io_write_data_dataout_18_value_5_0 = io_write_data_dataout_18_value_4_0 |
     io_write_data_dataout_18_value_4_1; // @[Library.scala 115:37]
-  wire [4:0] io_write_data_idx_19 = 5'h13 + io_write_data_index; // @[VLdSt.scala 52:36]
+  wire [4:0] io_write_data_idx_19 = 5'h13 + io_write_data_index; // @[VLdSt.scala 55:35]
   wire [7:0] io_write_data_dataout_19_value__0 = 5'h0 == io_write_data_idx_19 ? io_write_data_datain_0 : 8'h0; // @[Library.scala 101:22]
   wire [7:0] io_write_data_dataout_19_value__1 = 5'h1 == io_write_data_idx_19 ? io_write_data_datain_1 : 8'h0; // @[Library.scala 101:22]
   wire [7:0] io_write_data_dataout_19_value__2 = 5'h2 == io_write_data_idx_19 ? io_write_data_datain_2 : 8'h0; // @[Library.scala 101:22]
@@ -98100,7 +88542,7 @@
     io_write_data_dataout_19_value_3_3; // @[Library.scala 115:37]
   wire [7:0] io_write_data_dataout_19_value_5_0 = io_write_data_dataout_19_value_4_0 |
     io_write_data_dataout_19_value_4_1; // @[Library.scala 115:37]
-  wire [4:0] io_write_data_idx_20 = 5'h14 + io_write_data_index; // @[VLdSt.scala 52:36]
+  wire [4:0] io_write_data_idx_20 = 5'h14 + io_write_data_index; // @[VLdSt.scala 55:35]
   wire [7:0] io_write_data_dataout_20_value__0 = 5'h0 == io_write_data_idx_20 ? io_write_data_datain_0 : 8'h0; // @[Library.scala 101:22]
   wire [7:0] io_write_data_dataout_20_value__1 = 5'h1 == io_write_data_idx_20 ? io_write_data_datain_1 : 8'h0; // @[Library.scala 101:22]
   wire [7:0] io_write_data_dataout_20_value__2 = 5'h2 == io_write_data_idx_20 ? io_write_data_datain_2 : 8'h0; // @[Library.scala 101:22]
@@ -98190,7 +88632,7 @@
     io_write_data_dataout_20_value_3_3; // @[Library.scala 115:37]
   wire [7:0] io_write_data_dataout_20_value_5_0 = io_write_data_dataout_20_value_4_0 |
     io_write_data_dataout_20_value_4_1; // @[Library.scala 115:37]
-  wire [4:0] io_write_data_idx_21 = 5'h15 + io_write_data_index; // @[VLdSt.scala 52:36]
+  wire [4:0] io_write_data_idx_21 = 5'h15 + io_write_data_index; // @[VLdSt.scala 55:35]
   wire [7:0] io_write_data_dataout_21_value__0 = 5'h0 == io_write_data_idx_21 ? io_write_data_datain_0 : 8'h0; // @[Library.scala 101:22]
   wire [7:0] io_write_data_dataout_21_value__1 = 5'h1 == io_write_data_idx_21 ? io_write_data_datain_1 : 8'h0; // @[Library.scala 101:22]
   wire [7:0] io_write_data_dataout_21_value__2 = 5'h2 == io_write_data_idx_21 ? io_write_data_datain_2 : 8'h0; // @[Library.scala 101:22]
@@ -98280,7 +88722,7 @@
     io_write_data_dataout_21_value_3_3; // @[Library.scala 115:37]
   wire [7:0] io_write_data_dataout_21_value_5_0 = io_write_data_dataout_21_value_4_0 |
     io_write_data_dataout_21_value_4_1; // @[Library.scala 115:37]
-  wire [4:0] io_write_data_idx_22 = 5'h16 + io_write_data_index; // @[VLdSt.scala 52:36]
+  wire [4:0] io_write_data_idx_22 = 5'h16 + io_write_data_index; // @[VLdSt.scala 55:35]
   wire [7:0] io_write_data_dataout_22_value__0 = 5'h0 == io_write_data_idx_22 ? io_write_data_datain_0 : 8'h0; // @[Library.scala 101:22]
   wire [7:0] io_write_data_dataout_22_value__1 = 5'h1 == io_write_data_idx_22 ? io_write_data_datain_1 : 8'h0; // @[Library.scala 101:22]
   wire [7:0] io_write_data_dataout_22_value__2 = 5'h2 == io_write_data_idx_22 ? io_write_data_datain_2 : 8'h0; // @[Library.scala 101:22]
@@ -98370,7 +88812,7 @@
     io_write_data_dataout_22_value_3_3; // @[Library.scala 115:37]
   wire [7:0] io_write_data_dataout_22_value_5_0 = io_write_data_dataout_22_value_4_0 |
     io_write_data_dataout_22_value_4_1; // @[Library.scala 115:37]
-  wire [4:0] io_write_data_idx_23 = 5'h17 + io_write_data_index; // @[VLdSt.scala 52:36]
+  wire [4:0] io_write_data_idx_23 = 5'h17 + io_write_data_index; // @[VLdSt.scala 55:35]
   wire [7:0] io_write_data_dataout_23_value__0 = 5'h0 == io_write_data_idx_23 ? io_write_data_datain_0 : 8'h0; // @[Library.scala 101:22]
   wire [7:0] io_write_data_dataout_23_value__1 = 5'h1 == io_write_data_idx_23 ? io_write_data_datain_1 : 8'h0; // @[Library.scala 101:22]
   wire [7:0] io_write_data_dataout_23_value__2 = 5'h2 == io_write_data_idx_23 ? io_write_data_datain_2 : 8'h0; // @[Library.scala 101:22]
@@ -98460,7 +88902,7 @@
     io_write_data_dataout_23_value_3_3; // @[Library.scala 115:37]
   wire [7:0] io_write_data_dataout_23_value_5_0 = io_write_data_dataout_23_value_4_0 |
     io_write_data_dataout_23_value_4_1; // @[Library.scala 115:37]
-  wire [4:0] io_write_data_idx_24 = 5'h18 + io_write_data_index; // @[VLdSt.scala 52:36]
+  wire [4:0] io_write_data_idx_24 = 5'h18 + io_write_data_index; // @[VLdSt.scala 55:35]
   wire [7:0] io_write_data_dataout_24_value__0 = 5'h0 == io_write_data_idx_24 ? io_write_data_datain_0 : 8'h0; // @[Library.scala 101:22]
   wire [7:0] io_write_data_dataout_24_value__1 = 5'h1 == io_write_data_idx_24 ? io_write_data_datain_1 : 8'h0; // @[Library.scala 101:22]
   wire [7:0] io_write_data_dataout_24_value__2 = 5'h2 == io_write_data_idx_24 ? io_write_data_datain_2 : 8'h0; // @[Library.scala 101:22]
@@ -98550,7 +88992,7 @@
     io_write_data_dataout_24_value_3_3; // @[Library.scala 115:37]
   wire [7:0] io_write_data_dataout_24_value_5_0 = io_write_data_dataout_24_value_4_0 |
     io_write_data_dataout_24_value_4_1; // @[Library.scala 115:37]
-  wire [4:0] io_write_data_idx_25 = 5'h19 + io_write_data_index; // @[VLdSt.scala 52:36]
+  wire [4:0] io_write_data_idx_25 = 5'h19 + io_write_data_index; // @[VLdSt.scala 55:35]
   wire [7:0] io_write_data_dataout_25_value__0 = 5'h0 == io_write_data_idx_25 ? io_write_data_datain_0 : 8'h0; // @[Library.scala 101:22]
   wire [7:0] io_write_data_dataout_25_value__1 = 5'h1 == io_write_data_idx_25 ? io_write_data_datain_1 : 8'h0; // @[Library.scala 101:22]
   wire [7:0] io_write_data_dataout_25_value__2 = 5'h2 == io_write_data_idx_25 ? io_write_data_datain_2 : 8'h0; // @[Library.scala 101:22]
@@ -98640,7 +89082,7 @@
     io_write_data_dataout_25_value_3_3; // @[Library.scala 115:37]
   wire [7:0] io_write_data_dataout_25_value_5_0 = io_write_data_dataout_25_value_4_0 |
     io_write_data_dataout_25_value_4_1; // @[Library.scala 115:37]
-  wire [4:0] io_write_data_idx_26 = 5'h1a + io_write_data_index; // @[VLdSt.scala 52:36]
+  wire [4:0] io_write_data_idx_26 = 5'h1a + io_write_data_index; // @[VLdSt.scala 55:35]
   wire [7:0] io_write_data_dataout_26_value__0 = 5'h0 == io_write_data_idx_26 ? io_write_data_datain_0 : 8'h0; // @[Library.scala 101:22]
   wire [7:0] io_write_data_dataout_26_value__1 = 5'h1 == io_write_data_idx_26 ? io_write_data_datain_1 : 8'h0; // @[Library.scala 101:22]
   wire [7:0] io_write_data_dataout_26_value__2 = 5'h2 == io_write_data_idx_26 ? io_write_data_datain_2 : 8'h0; // @[Library.scala 101:22]
@@ -98730,7 +89172,7 @@
     io_write_data_dataout_26_value_3_3; // @[Library.scala 115:37]
   wire [7:0] io_write_data_dataout_26_value_5_0 = io_write_data_dataout_26_value_4_0 |
     io_write_data_dataout_26_value_4_1; // @[Library.scala 115:37]
-  wire [4:0] io_write_data_idx_27 = 5'h1b + io_write_data_index; // @[VLdSt.scala 52:36]
+  wire [4:0] io_write_data_idx_27 = 5'h1b + io_write_data_index; // @[VLdSt.scala 55:35]
   wire [7:0] io_write_data_dataout_27_value__0 = 5'h0 == io_write_data_idx_27 ? io_write_data_datain_0 : 8'h0; // @[Library.scala 101:22]
   wire [7:0] io_write_data_dataout_27_value__1 = 5'h1 == io_write_data_idx_27 ? io_write_data_datain_1 : 8'h0; // @[Library.scala 101:22]
   wire [7:0] io_write_data_dataout_27_value__2 = 5'h2 == io_write_data_idx_27 ? io_write_data_datain_2 : 8'h0; // @[Library.scala 101:22]
@@ -98820,7 +89262,7 @@
     io_write_data_dataout_27_value_3_3; // @[Library.scala 115:37]
   wire [7:0] io_write_data_dataout_27_value_5_0 = io_write_data_dataout_27_value_4_0 |
     io_write_data_dataout_27_value_4_1; // @[Library.scala 115:37]
-  wire [4:0] io_write_data_idx_28 = 5'h1c + io_write_data_index; // @[VLdSt.scala 52:36]
+  wire [4:0] io_write_data_idx_28 = 5'h1c + io_write_data_index; // @[VLdSt.scala 55:35]
   wire [7:0] io_write_data_dataout_28_value__0 = 5'h0 == io_write_data_idx_28 ? io_write_data_datain_0 : 8'h0; // @[Library.scala 101:22]
   wire [7:0] io_write_data_dataout_28_value__1 = 5'h1 == io_write_data_idx_28 ? io_write_data_datain_1 : 8'h0; // @[Library.scala 101:22]
   wire [7:0] io_write_data_dataout_28_value__2 = 5'h2 == io_write_data_idx_28 ? io_write_data_datain_2 : 8'h0; // @[Library.scala 101:22]
@@ -98910,7 +89352,7 @@
     io_write_data_dataout_28_value_3_3; // @[Library.scala 115:37]
   wire [7:0] io_write_data_dataout_28_value_5_0 = io_write_data_dataout_28_value_4_0 |
     io_write_data_dataout_28_value_4_1; // @[Library.scala 115:37]
-  wire [4:0] io_write_data_idx_29 = 5'h1d + io_write_data_index; // @[VLdSt.scala 52:36]
+  wire [4:0] io_write_data_idx_29 = 5'h1d + io_write_data_index; // @[VLdSt.scala 55:35]
   wire [7:0] io_write_data_dataout_29_value__0 = 5'h0 == io_write_data_idx_29 ? io_write_data_datain_0 : 8'h0; // @[Library.scala 101:22]
   wire [7:0] io_write_data_dataout_29_value__1 = 5'h1 == io_write_data_idx_29 ? io_write_data_datain_1 : 8'h0; // @[Library.scala 101:22]
   wire [7:0] io_write_data_dataout_29_value__2 = 5'h2 == io_write_data_idx_29 ? io_write_data_datain_2 : 8'h0; // @[Library.scala 101:22]
@@ -99000,7 +89442,7 @@
     io_write_data_dataout_29_value_3_3; // @[Library.scala 115:37]
   wire [7:0] io_write_data_dataout_29_value_5_0 = io_write_data_dataout_29_value_4_0 |
     io_write_data_dataout_29_value_4_1; // @[Library.scala 115:37]
-  wire [4:0] io_write_data_idx_30 = 5'h1e + io_write_data_index; // @[VLdSt.scala 52:36]
+  wire [4:0] io_write_data_idx_30 = 5'h1e + io_write_data_index; // @[VLdSt.scala 55:35]
   wire [7:0] io_write_data_dataout_30_value__0 = 5'h0 == io_write_data_idx_30 ? io_write_data_datain_0 : 8'h0; // @[Library.scala 101:22]
   wire [7:0] io_write_data_dataout_30_value__1 = 5'h1 == io_write_data_idx_30 ? io_write_data_datain_1 : 8'h0; // @[Library.scala 101:22]
   wire [7:0] io_write_data_dataout_30_value__2 = 5'h2 == io_write_data_idx_30 ? io_write_data_datain_2 : 8'h0; // @[Library.scala 101:22]
@@ -99090,7 +89532,7 @@
     io_write_data_dataout_30_value_3_3; // @[Library.scala 115:37]
   wire [7:0] io_write_data_dataout_30_value_5_0 = io_write_data_dataout_30_value_4_0 |
     io_write_data_dataout_30_value_4_1; // @[Library.scala 115:37]
-  wire [4:0] io_write_data_idx_31 = 5'h1f + io_write_data_index; // @[VLdSt.scala 52:36]
+  wire [4:0] io_write_data_idx_31 = 5'h1f + io_write_data_index; // @[VLdSt.scala 55:35]
   wire [7:0] io_write_data_dataout_31_value__0 = 5'h0 == io_write_data_idx_31 ? io_write_data_datain_0 : 8'h0; // @[Library.scala 101:22]
   wire [7:0] io_write_data_dataout_31_value__1 = 5'h1 == io_write_data_idx_31 ? io_write_data_datain_1 : 8'h0; // @[Library.scala 101:22]
   wire [7:0] io_write_data_dataout_31_value__2 = 5'h2 == io_write_data_idx_31 ? io_write_data_datain_2 : 8'h0; // @[Library.scala 101:22]
@@ -99182,18 +89624,18 @@
     io_write_data_dataout_31_value_4_1; // @[Library.scala 115:37]
   wire [63:0] io_write_data_lo_lo = {io_write_data_dataout_7_value_5_0,io_write_data_dataout_6_value_5_0,
     io_write_data_dataout_5_value_5_0,io_write_data_dataout_4_value_5_0,io_write_data_dataout_3_value_5_0,
-    io_write_data_dataout_2_value_5_0,io_write_data_dataout_1_value_5_0,io_write_data_dataout_0_value_5_0}; // @[VLdSt.scala 57:13]
+    io_write_data_dataout_2_value_5_0,io_write_data_dataout_1_value_5_0,io_write_data_dataout_0_value_5_0}; // @[VLdSt.scala 60:13]
   wire [127:0] io_write_data_lo = {io_write_data_dataout_15_value_5_0,io_write_data_dataout_14_value_5_0,
     io_write_data_dataout_13_value_5_0,io_write_data_dataout_12_value_5_0,io_write_data_dataout_11_value_5_0,
     io_write_data_dataout_10_value_5_0,io_write_data_dataout_9_value_5_0,io_write_data_dataout_8_value_5_0,
-    io_write_data_lo_lo}; // @[VLdSt.scala 57:13]
+    io_write_data_lo_lo}; // @[VLdSt.scala 60:13]
   wire [63:0] io_write_data_hi_lo = {io_write_data_dataout_23_value_5_0,io_write_data_dataout_22_value_5_0,
     io_write_data_dataout_21_value_5_0,io_write_data_dataout_20_value_5_0,io_write_data_dataout_19_value_5_0,
-    io_write_data_dataout_18_value_5_0,io_write_data_dataout_17_value_5_0,io_write_data_dataout_16_value_5_0}; // @[VLdSt.scala 57:13]
+    io_write_data_dataout_18_value_5_0,io_write_data_dataout_17_value_5_0,io_write_data_dataout_16_value_5_0}; // @[VLdSt.scala 60:13]
   wire [255:0] _io_write_data_T = {io_write_data_dataout_31_value_5_0,io_write_data_dataout_30_value_5_0,
     io_write_data_dataout_29_value_5_0,io_write_data_dataout_28_value_5_0,io_write_data_dataout_27_value_5_0,
     io_write_data_dataout_26_value_5_0,io_write_data_dataout_25_value_5_0,io_write_data_dataout_24_value_5_0,
-    io_write_data_hi_lo,io_write_data_lo}; // @[VLdSt.scala 57:13]
+    io_write_data_hi_lo,io_write_data_lo}; // @[VLdSt.scala 60:13]
   VCmdq_3 q ( // @[VCmdq.scala 14:11]
     .clock(q_clock),
     .reset(q_reset),
@@ -99260,7 +89702,7 @@
     .io_out_bits_last(q_io_out_bits_last),
     .io_active(q_io_active)
   );
-  Fifo_4 ctrl ( // @[Fifo.scala 8:11]
+  Fifo ctrl ( // @[Fifo.scala 8:11]
     .clock(ctrl_clock),
     .reset(ctrl_reset),
     .io_in_ready(ctrl_io_in_ready),
@@ -99280,7 +89722,7 @@
     .io_out_bits_size(ctrl_io_out_bits_size),
     .io_out_bits_widx(ctrl_io_out_bits_widx)
   );
-  Fifo_5 data ( // @[Fifo.scala 8:11]
+  Fifo_1 data ( // @[Fifo.scala 8:11]
     .clock(data_clock),
     .reset(data_reset),
     .io_in_ready(data_io_in_ready),
@@ -99292,7 +89734,7 @@
     .io_out_bits_wdata(data_io_out_bits_wdata),
     .io_out_bits_wmask(data_io_out_bits_wmask)
   );
-  Slice_5 wrega ( // @[Slice.scala 9:11]
+  Slice_4 wrega ( // @[Slice.scala 9:11]
     .clock(wrega_clock),
     .reset(wrega_reset),
     .io_in_ready(wrega_io_in_ready),
@@ -99306,7 +89748,7 @@
     .io_out_bits_addr(wrega_io_out_bits_addr),
     .io_out_bits_size(wrega_io_out_bits_size)
   );
-  Slice_6 wregd ( // @[Slice.scala 9:11]
+  Slice_5 wregd ( // @[Slice.scala 9:11]
     .clock(wregd_clock),
     .reset(wregd_reset),
     .io_in_ready(wregd_io_in_ready),
@@ -99316,105 +89758,105 @@
     .io_out_valid(wregd_io_out_valid),
     .io_out_bits(wregd_io_out_bits)
   );
-  assign io_in_ready = q_io_in_ready; // @[VLdSt.scala 162:11]
-  assign io_active = q_io_active; // @[VLdSt.scala 293:13]
-  assign io_read_valid = q_io_out_valid & q_io_out_bits_vs_valid; // @[VLdSt.scala 169:35]
-  assign io_read_addr = q_io_out_bits_vs_addr; // @[VLdSt.scala 171:16]
-  assign io_write_valid = wrega_io_out_valid & wregd_io_out_valid; // @[VLdSt.scala 287:40]
-  assign io_write_addr = wrega_io_out_bits_widx; // @[VLdSt.scala 288:17]
-  assign io_write_data = _io_write_data_T & mask; // @[VLdSt.scala 289:80]
-  assign io_dbus_valid = ctrl_io_out_valid & _ctrl_io_out_ready_T_1; // @[VLdSt.scala 246:38]
-  assign io_dbus_write = ctrl_io_out_bits_write; // @[VLdSt.scala 247:17]
+  assign io_in_ready = q_io_in_ready; // @[VLdSt.scala 165:11]
+  assign io_active = q_io_active; // @[VLdSt.scala 296:13]
+  assign io_read_valid = q_io_out_valid & q_io_out_bits_vs_valid; // @[VLdSt.scala 172:35]
+  assign io_read_addr = q_io_out_bits_vs_addr; // @[VLdSt.scala 174:16]
+  assign io_write_valid = wrega_io_out_valid & wregd_io_out_valid; // @[VLdSt.scala 290:40]
+  assign io_write_addr = wrega_io_out_bits_widx; // @[VLdSt.scala 291:17]
+  assign io_write_data = _io_write_data_T & mask; // @[VLdSt.scala 292:80]
+  assign io_dbus_valid = ctrl_io_out_valid & _ctrl_io_out_ready_T_1; // @[VLdSt.scala 249:38]
+  assign io_dbus_write = ctrl_io_out_bits_write; // @[VLdSt.scala 250:17]
   assign io_dbus_addr = {1'h0,ctrl_io_out_bits_addr[30:0]}; // @[Cat.scala 31:58]
   assign io_dbus_adrx = {1'h0,ctrl_io_out_bits_adrx[30:0]}; // @[Cat.scala 31:58]
-  assign io_dbus_size = ctrl_io_out_bits_size; // @[VLdSt.scala 250:16]
-  assign io_dbus_wdata = data_io_out_bits_wdata; // @[VLdSt.scala 251:17]
-  assign io_dbus_wmask = data_io_out_bits_wmask; // @[VLdSt.scala 252:17]
-  assign io_last = ctrl_io_out_bits_last; // @[VLdSt.scala 258:11]
+  assign io_dbus_size = ctrl_io_out_bits_size; // @[VLdSt.scala 253:16]
+  assign io_dbus_wdata = data_io_out_bits_wdata; // @[VLdSt.scala 254:17]
+  assign io_dbus_wmask = data_io_out_bits_wmask; // @[VLdSt.scala 255:17]
+  assign io_last = ctrl_io_out_bits_last; // @[VLdSt.scala 261:11]
   assign q_clock = clock;
   assign q_reset = reset;
-  assign q_io_in_valid = io_in_valid; // @[VLdSt.scala 162:11]
-  assign q_io_in_bits_0_valid = io_in_bits_0_valid; // @[VLdSt.scala 162:11]
-  assign q_io_in_bits_0_bits_op = io_in_bits_0_bits_op; // @[VLdSt.scala 162:11]
-  assign q_io_in_bits_0_bits_f2 = io_in_bits_0_bits_f2; // @[VLdSt.scala 162:11]
-  assign q_io_in_bits_0_bits_sz = io_in_bits_0_bits_sz; // @[VLdSt.scala 162:11]
-  assign q_io_in_bits_0_bits_m = io_in_bits_0_bits_m; // @[VLdSt.scala 162:11]
-  assign q_io_in_bits_0_bits_vd_valid = io_in_bits_0_bits_vd_valid; // @[VLdSt.scala 162:11]
-  assign q_io_in_bits_0_bits_vd_addr = io_in_bits_0_bits_vd_addr; // @[VLdSt.scala 162:11]
-  assign q_io_in_bits_0_bits_vs_valid = io_in_bits_0_bits_vs_valid; // @[VLdSt.scala 162:11]
-  assign q_io_in_bits_0_bits_vs_addr = io_in_bits_0_bits_vs_addr; // @[VLdSt.scala 162:11]
-  assign q_io_in_bits_0_bits_vs_tag = io_in_bits_0_bits_vs_tag; // @[VLdSt.scala 162:11]
-  assign q_io_in_bits_0_bits_sv_addr = io_in_bits_0_bits_sv_addr; // @[VLdSt.scala 162:11]
-  assign q_io_in_bits_0_bits_sv_data = io_in_bits_0_bits_sv_data; // @[VLdSt.scala 162:11]
-  assign q_io_in_bits_1_valid = io_in_bits_1_valid; // @[VLdSt.scala 162:11]
-  assign q_io_in_bits_1_bits_op = io_in_bits_1_bits_op; // @[VLdSt.scala 162:11]
-  assign q_io_in_bits_1_bits_f2 = io_in_bits_1_bits_f2; // @[VLdSt.scala 162:11]
-  assign q_io_in_bits_1_bits_sz = io_in_bits_1_bits_sz; // @[VLdSt.scala 162:11]
-  assign q_io_in_bits_1_bits_m = io_in_bits_1_bits_m; // @[VLdSt.scala 162:11]
-  assign q_io_in_bits_1_bits_vd_valid = io_in_bits_1_bits_vd_valid; // @[VLdSt.scala 162:11]
-  assign q_io_in_bits_1_bits_vd_addr = io_in_bits_1_bits_vd_addr; // @[VLdSt.scala 162:11]
-  assign q_io_in_bits_1_bits_vs_valid = io_in_bits_1_bits_vs_valid; // @[VLdSt.scala 162:11]
-  assign q_io_in_bits_1_bits_vs_addr = io_in_bits_1_bits_vs_addr; // @[VLdSt.scala 162:11]
-  assign q_io_in_bits_1_bits_vs_tag = io_in_bits_1_bits_vs_tag; // @[VLdSt.scala 162:11]
-  assign q_io_in_bits_1_bits_sv_addr = io_in_bits_1_bits_sv_addr; // @[VLdSt.scala 162:11]
-  assign q_io_in_bits_1_bits_sv_data = io_in_bits_1_bits_sv_data; // @[VLdSt.scala 162:11]
-  assign q_io_in_bits_2_valid = io_in_bits_2_valid; // @[VLdSt.scala 162:11]
-  assign q_io_in_bits_2_bits_op = io_in_bits_2_bits_op; // @[VLdSt.scala 162:11]
-  assign q_io_in_bits_2_bits_f2 = io_in_bits_2_bits_f2; // @[VLdSt.scala 162:11]
-  assign q_io_in_bits_2_bits_sz = io_in_bits_2_bits_sz; // @[VLdSt.scala 162:11]
-  assign q_io_in_bits_2_bits_m = io_in_bits_2_bits_m; // @[VLdSt.scala 162:11]
-  assign q_io_in_bits_2_bits_vd_valid = io_in_bits_2_bits_vd_valid; // @[VLdSt.scala 162:11]
-  assign q_io_in_bits_2_bits_vd_addr = io_in_bits_2_bits_vd_addr; // @[VLdSt.scala 162:11]
-  assign q_io_in_bits_2_bits_vs_valid = io_in_bits_2_bits_vs_valid; // @[VLdSt.scala 162:11]
-  assign q_io_in_bits_2_bits_vs_addr = io_in_bits_2_bits_vs_addr; // @[VLdSt.scala 162:11]
-  assign q_io_in_bits_2_bits_vs_tag = io_in_bits_2_bits_vs_tag; // @[VLdSt.scala 162:11]
-  assign q_io_in_bits_2_bits_sv_addr = io_in_bits_2_bits_sv_addr; // @[VLdSt.scala 162:11]
-  assign q_io_in_bits_2_bits_sv_data = io_in_bits_2_bits_sv_data; // @[VLdSt.scala 162:11]
-  assign q_io_in_bits_3_valid = io_in_bits_3_valid; // @[VLdSt.scala 162:11]
-  assign q_io_in_bits_3_bits_op = io_in_bits_3_bits_op; // @[VLdSt.scala 162:11]
-  assign q_io_in_bits_3_bits_f2 = io_in_bits_3_bits_f2; // @[VLdSt.scala 162:11]
-  assign q_io_in_bits_3_bits_sz = io_in_bits_3_bits_sz; // @[VLdSt.scala 162:11]
-  assign q_io_in_bits_3_bits_m = io_in_bits_3_bits_m; // @[VLdSt.scala 162:11]
-  assign q_io_in_bits_3_bits_vd_valid = io_in_bits_3_bits_vd_valid; // @[VLdSt.scala 162:11]
-  assign q_io_in_bits_3_bits_vd_addr = io_in_bits_3_bits_vd_addr; // @[VLdSt.scala 162:11]
-  assign q_io_in_bits_3_bits_vs_valid = io_in_bits_3_bits_vs_valid; // @[VLdSt.scala 162:11]
-  assign q_io_in_bits_3_bits_vs_addr = io_in_bits_3_bits_vs_addr; // @[VLdSt.scala 162:11]
-  assign q_io_in_bits_3_bits_vs_tag = io_in_bits_3_bits_vs_tag; // @[VLdSt.scala 162:11]
-  assign q_io_in_bits_3_bits_sv_addr = io_in_bits_3_bits_sv_addr; // @[VLdSt.scala 162:11]
-  assign q_io_in_bits_3_bits_sv_data = io_in_bits_3_bits_sv_data; // @[VLdSt.scala 162:11]
-  assign q_io_out_ready = _q_io_out_ready_T_4 & ctrlready; // @[VLdSt.scala 165:65]
+  assign q_io_in_valid = io_in_valid; // @[VLdSt.scala 165:11]
+  assign q_io_in_bits_0_valid = io_in_bits_0_valid; // @[VLdSt.scala 165:11]
+  assign q_io_in_bits_0_bits_op = io_in_bits_0_bits_op; // @[VLdSt.scala 165:11]
+  assign q_io_in_bits_0_bits_f2 = io_in_bits_0_bits_f2; // @[VLdSt.scala 165:11]
+  assign q_io_in_bits_0_bits_sz = io_in_bits_0_bits_sz; // @[VLdSt.scala 165:11]
+  assign q_io_in_bits_0_bits_m = io_in_bits_0_bits_m; // @[VLdSt.scala 165:11]
+  assign q_io_in_bits_0_bits_vd_valid = io_in_bits_0_bits_vd_valid; // @[VLdSt.scala 165:11]
+  assign q_io_in_bits_0_bits_vd_addr = io_in_bits_0_bits_vd_addr; // @[VLdSt.scala 165:11]
+  assign q_io_in_bits_0_bits_vs_valid = io_in_bits_0_bits_vs_valid; // @[VLdSt.scala 165:11]
+  assign q_io_in_bits_0_bits_vs_addr = io_in_bits_0_bits_vs_addr; // @[VLdSt.scala 165:11]
+  assign q_io_in_bits_0_bits_vs_tag = io_in_bits_0_bits_vs_tag; // @[VLdSt.scala 165:11]
+  assign q_io_in_bits_0_bits_sv_addr = io_in_bits_0_bits_sv_addr; // @[VLdSt.scala 165:11]
+  assign q_io_in_bits_0_bits_sv_data = io_in_bits_0_bits_sv_data; // @[VLdSt.scala 165:11]
+  assign q_io_in_bits_1_valid = io_in_bits_1_valid; // @[VLdSt.scala 165:11]
+  assign q_io_in_bits_1_bits_op = io_in_bits_1_bits_op; // @[VLdSt.scala 165:11]
+  assign q_io_in_bits_1_bits_f2 = io_in_bits_1_bits_f2; // @[VLdSt.scala 165:11]
+  assign q_io_in_bits_1_bits_sz = io_in_bits_1_bits_sz; // @[VLdSt.scala 165:11]
+  assign q_io_in_bits_1_bits_m = io_in_bits_1_bits_m; // @[VLdSt.scala 165:11]
+  assign q_io_in_bits_1_bits_vd_valid = io_in_bits_1_bits_vd_valid; // @[VLdSt.scala 165:11]
+  assign q_io_in_bits_1_bits_vd_addr = io_in_bits_1_bits_vd_addr; // @[VLdSt.scala 165:11]
+  assign q_io_in_bits_1_bits_vs_valid = io_in_bits_1_bits_vs_valid; // @[VLdSt.scala 165:11]
+  assign q_io_in_bits_1_bits_vs_addr = io_in_bits_1_bits_vs_addr; // @[VLdSt.scala 165:11]
+  assign q_io_in_bits_1_bits_vs_tag = io_in_bits_1_bits_vs_tag; // @[VLdSt.scala 165:11]
+  assign q_io_in_bits_1_bits_sv_addr = io_in_bits_1_bits_sv_addr; // @[VLdSt.scala 165:11]
+  assign q_io_in_bits_1_bits_sv_data = io_in_bits_1_bits_sv_data; // @[VLdSt.scala 165:11]
+  assign q_io_in_bits_2_valid = io_in_bits_2_valid; // @[VLdSt.scala 165:11]
+  assign q_io_in_bits_2_bits_op = io_in_bits_2_bits_op; // @[VLdSt.scala 165:11]
+  assign q_io_in_bits_2_bits_f2 = io_in_bits_2_bits_f2; // @[VLdSt.scala 165:11]
+  assign q_io_in_bits_2_bits_sz = io_in_bits_2_bits_sz; // @[VLdSt.scala 165:11]
+  assign q_io_in_bits_2_bits_m = io_in_bits_2_bits_m; // @[VLdSt.scala 165:11]
+  assign q_io_in_bits_2_bits_vd_valid = io_in_bits_2_bits_vd_valid; // @[VLdSt.scala 165:11]
+  assign q_io_in_bits_2_bits_vd_addr = io_in_bits_2_bits_vd_addr; // @[VLdSt.scala 165:11]
+  assign q_io_in_bits_2_bits_vs_valid = io_in_bits_2_bits_vs_valid; // @[VLdSt.scala 165:11]
+  assign q_io_in_bits_2_bits_vs_addr = io_in_bits_2_bits_vs_addr; // @[VLdSt.scala 165:11]
+  assign q_io_in_bits_2_bits_vs_tag = io_in_bits_2_bits_vs_tag; // @[VLdSt.scala 165:11]
+  assign q_io_in_bits_2_bits_sv_addr = io_in_bits_2_bits_sv_addr; // @[VLdSt.scala 165:11]
+  assign q_io_in_bits_2_bits_sv_data = io_in_bits_2_bits_sv_data; // @[VLdSt.scala 165:11]
+  assign q_io_in_bits_3_valid = io_in_bits_3_valid; // @[VLdSt.scala 165:11]
+  assign q_io_in_bits_3_bits_op = io_in_bits_3_bits_op; // @[VLdSt.scala 165:11]
+  assign q_io_in_bits_3_bits_f2 = io_in_bits_3_bits_f2; // @[VLdSt.scala 165:11]
+  assign q_io_in_bits_3_bits_sz = io_in_bits_3_bits_sz; // @[VLdSt.scala 165:11]
+  assign q_io_in_bits_3_bits_m = io_in_bits_3_bits_m; // @[VLdSt.scala 165:11]
+  assign q_io_in_bits_3_bits_vd_valid = io_in_bits_3_bits_vd_valid; // @[VLdSt.scala 165:11]
+  assign q_io_in_bits_3_bits_vd_addr = io_in_bits_3_bits_vd_addr; // @[VLdSt.scala 165:11]
+  assign q_io_in_bits_3_bits_vs_valid = io_in_bits_3_bits_vs_valid; // @[VLdSt.scala 165:11]
+  assign q_io_in_bits_3_bits_vs_addr = io_in_bits_3_bits_vs_addr; // @[VLdSt.scala 165:11]
+  assign q_io_in_bits_3_bits_vs_tag = io_in_bits_3_bits_vs_tag; // @[VLdSt.scala 165:11]
+  assign q_io_in_bits_3_bits_sv_addr = io_in_bits_3_bits_sv_addr; // @[VLdSt.scala 165:11]
+  assign q_io_in_bits_3_bits_sv_data = io_in_bits_3_bits_sv_data; // @[VLdSt.scala 165:11]
+  assign q_io_out_ready = _q_io_out_ready_T_4 & ctrlready; // @[VLdSt.scala 168:65]
   assign ctrl_clock = clock;
   assign ctrl_reset = reset;
-  assign ctrl_io_in_valid = q_io_out_valid & q_io_out_ready; // @[VLdSt.scala 208:31]
-  assign ctrl_io_in_bits_last = q_io_out_bits_last; // @[VLdSt.scala 232:25]
-  assign ctrl_io_in_bits_write = q_io_out_bits_op == 7'h3 | _qmaxvlb_T; // @[VLdSt.scala 79:22]
-  assign ctrl_io_in_bits_addr = q_io_out_bits_addr; // @[VLdSt.scala 229:25]
-  assign ctrl_io_in_bits_adrx = q_io_out_bits_addr + 32'h20; // @[VLdSt.scala 230:47]
-  assign ctrl_io_in_bits_size = qsize[5:0]; // @[VLdSt.scala 231:25]
-  assign ctrl_io_in_bits_widx = q_io_out_bits_vd_addr; // @[VLdSt.scala 234:25]
-  assign ctrl_io_out_ready = io_dbus_ready & (data_io_out_valid | ~ctrl_io_out_bits_write); // @[VLdSt.scala 242:38]
+  assign ctrl_io_in_valid = q_io_out_valid & q_io_out_ready; // @[VLdSt.scala 211:31]
+  assign ctrl_io_in_bits_last = q_io_out_bits_last; // @[VLdSt.scala 235:25]
+  assign ctrl_io_in_bits_write = q_io_out_bits_op == 7'h3 | _qmaxvlb_T; // @[VLdSt.scala 82:22]
+  assign ctrl_io_in_bits_addr = q_io_out_bits_addr; // @[VLdSt.scala 232:25]
+  assign ctrl_io_in_bits_adrx = q_io_out_bits_addr + 32'h20; // @[VLdSt.scala 233:47]
+  assign ctrl_io_in_bits_size = qsize[5:0]; // @[VLdSt.scala 234:25]
+  assign ctrl_io_in_bits_widx = q_io_out_bits_vd_addr; // @[VLdSt.scala 237:25]
+  assign ctrl_io_out_ready = io_dbus_ready & (data_io_out_valid | ~ctrl_io_out_bits_write); // @[VLdSt.scala 245:38]
   assign data_clock = clock;
   assign data_reset = reset;
-  assign data_io_in_valid = rdataEn; // @[VLdSt.scala 237:20]
-  assign data_io_in_bits_wdata = {data_io_in_bits_wdata_hi,data_io_in_bits_wdata_lo}; // @[VLdSt.scala 57:13]
-  assign data_io_in_bits_wmask = {data_io_in_bits_wmask_hi_1,data_io_in_bits_wmask_lo_1}; // @[VLdSt.scala 57:13]
-  assign data_io_out_ready = io_dbus_ready & (ctrl_io_out_valid & ctrl_io_out_bits_write); // @[VLdSt.scala 243:38]
+  assign data_io_in_valid = rdataEn; // @[VLdSt.scala 240:20]
+  assign data_io_in_bits_wdata = {data_io_in_bits_wdata_hi,data_io_in_bits_wdata_lo}; // @[VLdSt.scala 60:13]
+  assign data_io_in_bits_wmask = {data_io_in_bits_wmask_hi_1,data_io_in_bits_wmask_lo_1}; // @[VLdSt.scala 60:13]
+  assign data_io_out_ready = io_dbus_ready & (ctrl_io_out_valid & ctrl_io_out_bits_write); // @[VLdSt.scala 246:38]
   assign wrega_clock = clock;
   assign wrega_reset = reset;
-  assign wrega_io_in_valid = ctrl_io_out_valid & io_dbus_ready & _ctrl_io_out_ready_T; // @[VLdSt.scala 268:59]
-  assign wrega_io_in_bits_widx = ctrl_io_out_bits_widx; // @[VLdSt.scala 269:25]
-  assign wrega_io_in_bits_addr = ctrl_io_out_bits_addr[4:0]; // @[VLdSt.scala 270:25]
-  assign wrega_io_in_bits_size = ctrl_io_out_bits_size; // @[VLdSt.scala 271:25]
-  assign wrega_io_out_ready = wregd_io_out_valid; // @[VLdSt.scala 272:22]
+  assign wrega_io_in_valid = ctrl_io_out_valid & io_dbus_ready & _ctrl_io_out_ready_T; // @[VLdSt.scala 271:59]
+  assign wrega_io_in_bits_widx = ctrl_io_out_bits_widx; // @[VLdSt.scala 272:25]
+  assign wrega_io_in_bits_addr = ctrl_io_out_bits_addr[4:0]; // @[VLdSt.scala 273:25]
+  assign wrega_io_in_bits_size = ctrl_io_out_bits_size; // @[VLdSt.scala 274:25]
+  assign wrega_io_out_ready = wregd_io_out_valid; // @[VLdSt.scala 275:22]
   assign wregd_clock = clock;
   assign wregd_reset = reset;
-  assign wregd_io_in_valid = wdataEn; // @[VLdSt.scala 275:21]
-  assign wregd_io_in_bits = io_dbus_rdata; // @[VLdSt.scala 276:20]
-  assign wregd_io_out_ready = wrega_io_out_valid; // @[VLdSt.scala 277:22]
+  assign wregd_io_in_valid = wdataEn; // @[VLdSt.scala 278:21]
+  assign wregd_io_in_bits = io_dbus_rdata; // @[VLdSt.scala 279:20]
+  assign wregd_io_out_ready = wrega_io_out_valid; // @[VLdSt.scala 280:22]
   always @(posedge clock) begin
-    if (rdataEnNxt) begin // @[VLdSt.scala 215:21]
-      if (q_io_out_bits_remain > qmaxvlb) begin // @[VLdSt.scala 212:18]
-        if (q_io_out_bits_op == 7'h4) begin // @[VLdSt.scala 211:20]
+    if (rdataEnNxt) begin // @[VLdSt.scala 218:21]
+      if (q_io_out_bits_remain > qmaxvlb) begin // @[VLdSt.scala 215:18]
+        if (q_io_out_bits_op == 7'h4) begin // @[VLdSt.scala 214:20]
           rdataSize <= 8'h8;
         end else begin
           rdataSize <= 8'h20;
@@ -99430,7 +89872,7 @@
       if (`STOP_COND) begin
     `endif
         if (~reset & ~(~(ctrl_io_in_valid & ~ctrl_io_in_ready))) begin
-          $fatal; // @[VLdSt.scala 235:9]
+          $fatal; // @[VLdSt.scala 238:9]
         end
     `ifdef STOP_COND
       end
@@ -99442,7 +89884,7 @@
     `endif
         if (~reset & ~(~(ctrl_io_in_valid & ~ctrl_io_in_ready))) begin
           $fwrite(32'h80000002,
-            "Assertion failed\n    at VLdSt.scala:235 assert(!(ctrl.io.in.valid && !ctrl.io.in.ready))\n"); // @[VLdSt.scala 235:9]
+            "Assertion failed\n    at VLdSt.scala:238 assert(!(ctrl.io.in.valid && !ctrl.io.in.ready))\n"); // @[VLdSt.scala 238:9]
         end
     `ifdef PRINTF_COND
       end
@@ -99453,7 +89895,7 @@
       if (`STOP_COND) begin
     `endif
         if (_T_4 & ~(~(data_io_in_valid & ~data_io_in_ready))) begin
-          $fatal; // @[VLdSt.scala 240:9]
+          $fatal; // @[VLdSt.scala 243:9]
         end
     `ifdef STOP_COND
       end
@@ -99465,7 +89907,7 @@
     `endif
         if (_T_4 & ~(~(data_io_in_valid & ~data_io_in_ready))) begin
           $fwrite(32'h80000002,
-            "Assertion failed\n    at VLdSt.scala:240 assert(!(data.io.in.valid && !data.io.in.ready))\n"); // @[VLdSt.scala 240:9]
+            "Assertion failed\n    at VLdSt.scala:243 assert(!(data.io.in.valid && !data.io.in.ready))\n"); // @[VLdSt.scala 243:9]
         end
     `ifdef PRINTF_COND
       end
@@ -99476,7 +89918,7 @@
       if (`STOP_COND) begin
     `endif
         if (_T_4 & ~(~(data_io_out_valid & ~ctrl_io_out_valid))) begin
-          $fatal; // @[VLdSt.scala 244:9]
+          $fatal; // @[VLdSt.scala 247:9]
         end
     `ifdef STOP_COND
       end
@@ -99488,7 +89930,7 @@
     `endif
         if (_T_4 & ~(~(data_io_out_valid & ~ctrl_io_out_valid))) begin
           $fwrite(32'h80000002,
-            "Assertion failed\n    at VLdSt.scala:244 assert(!(data.io.out.valid && !ctrl.io.out.valid))\n"); // @[VLdSt.scala 244:9]
+            "Assertion failed\n    at VLdSt.scala:247 assert(!(data.io.out.valid && !ctrl.io.out.valid))\n"); // @[VLdSt.scala 247:9]
         end
     `ifdef PRINTF_COND
       end
@@ -99499,75 +89941,6 @@
       if (`STOP_COND) begin
     `endif
         if (_T_4 & ~(~(ctrl_io_out_valid & ctrl_io_out_bits_addr[31]))) begin
-          $fatal; // @[VLdSt.scala 253:9]
-        end
-    `ifdef STOP_COND
-      end
-    `endif
-    `endif // SYNTHESIS
-    `ifndef SYNTHESIS
-    `ifdef PRINTF_COND
-      if (`PRINTF_COND) begin
-    `endif
-        if (_T_4 & ~(~(ctrl_io_out_valid & ctrl_io_out_bits_addr[31]))) begin
-          $fwrite(32'h80000002,
-            "Assertion failed\n    at VLdSt.scala:253 assert(!(ctrl.io.out.valid && ctrl.io.out.bits.addr(31)))\n"); // @[VLdSt.scala 253:9]
-        end
-    `ifdef PRINTF_COND
-      end
-    `endif
-    `endif // SYNTHESIS
-    `ifndef SYNTHESIS
-    `ifdef STOP_COND
-      if (`STOP_COND) begin
-    `endif
-        if (_T_4 & ~(~(ctrl_io_out_valid & ctrl_io_out_bits_adrx[31]))) begin
-          $fatal; // @[VLdSt.scala 254:9]
-        end
-    `ifdef STOP_COND
-      end
-    `endif
-    `endif // SYNTHESIS
-    `ifndef SYNTHESIS
-    `ifdef PRINTF_COND
-      if (`PRINTF_COND) begin
-    `endif
-        if (_T_4 & ~(~(ctrl_io_out_valid & ctrl_io_out_bits_adrx[31]))) begin
-          $fwrite(32'h80000002,
-            "Assertion failed\n    at VLdSt.scala:254 assert(!(ctrl.io.out.valid && ctrl.io.out.bits.adrx(31)))\n"); // @[VLdSt.scala 254:9]
-        end
-    `ifdef PRINTF_COND
-      end
-    `endif
-    `endif // SYNTHESIS
-    `ifndef SYNTHESIS
-    `ifdef STOP_COND
-      if (`STOP_COND) begin
-    `endif
-        if (_T_4 & ~(~(io_dbus_valid & io_dbus_addr[31]))) begin
-          $fatal; // @[VLdSt.scala 255:9]
-        end
-    `ifdef STOP_COND
-      end
-    `endif
-    `endif // SYNTHESIS
-    `ifndef SYNTHESIS
-    `ifdef PRINTF_COND
-      if (`PRINTF_COND) begin
-    `endif
-        if (_T_4 & ~(~(io_dbus_valid & io_dbus_addr[31]))) begin
-          $fwrite(32'h80000002,"Assertion failed\n    at VLdSt.scala:255 assert(!(io.dbus.valid && io.dbus.addr(31)))\n"
-            ); // @[VLdSt.scala 255:9]
-        end
-    `ifdef PRINTF_COND
-      end
-    `endif
-    `endif // SYNTHESIS
-    `ifndef SYNTHESIS
-    `ifdef STOP_COND
-      if (`STOP_COND) begin
-    `endif
-        if (_T_4 & ~(~(io_dbus_valid & io_dbus_adrx[31]))) begin
           $fatal; // @[VLdSt.scala 256:9]
         end
     `ifdef STOP_COND
@@ -99578,9 +89951,78 @@
     `ifdef PRINTF_COND
       if (`PRINTF_COND) begin
     `endif
+        if (_T_4 & ~(~(ctrl_io_out_valid & ctrl_io_out_bits_addr[31]))) begin
+          $fwrite(32'h80000002,
+            "Assertion failed\n    at VLdSt.scala:256 assert(!(ctrl.io.out.valid && ctrl.io.out.bits.addr(31)))\n"); // @[VLdSt.scala 256:9]
+        end
+    `ifdef PRINTF_COND
+      end
+    `endif
+    `endif // SYNTHESIS
+    `ifndef SYNTHESIS
+    `ifdef STOP_COND
+      if (`STOP_COND) begin
+    `endif
+        if (_T_4 & ~(~(ctrl_io_out_valid & ctrl_io_out_bits_adrx[31]))) begin
+          $fatal; // @[VLdSt.scala 257:9]
+        end
+    `ifdef STOP_COND
+      end
+    `endif
+    `endif // SYNTHESIS
+    `ifndef SYNTHESIS
+    `ifdef PRINTF_COND
+      if (`PRINTF_COND) begin
+    `endif
+        if (_T_4 & ~(~(ctrl_io_out_valid & ctrl_io_out_bits_adrx[31]))) begin
+          $fwrite(32'h80000002,
+            "Assertion failed\n    at VLdSt.scala:257 assert(!(ctrl.io.out.valid && ctrl.io.out.bits.adrx(31)))\n"); // @[VLdSt.scala 257:9]
+        end
+    `ifdef PRINTF_COND
+      end
+    `endif
+    `endif // SYNTHESIS
+    `ifndef SYNTHESIS
+    `ifdef STOP_COND
+      if (`STOP_COND) begin
+    `endif
+        if (_T_4 & ~(~(io_dbus_valid & io_dbus_addr[31]))) begin
+          $fatal; // @[VLdSt.scala 258:9]
+        end
+    `ifdef STOP_COND
+      end
+    `endif
+    `endif // SYNTHESIS
+    `ifndef SYNTHESIS
+    `ifdef PRINTF_COND
+      if (`PRINTF_COND) begin
+    `endif
+        if (_T_4 & ~(~(io_dbus_valid & io_dbus_addr[31]))) begin
+          $fwrite(32'h80000002,"Assertion failed\n    at VLdSt.scala:258 assert(!(io.dbus.valid && io.dbus.addr(31)))\n"
+            ); // @[VLdSt.scala 258:9]
+        end
+    `ifdef PRINTF_COND
+      end
+    `endif
+    `endif // SYNTHESIS
+    `ifndef SYNTHESIS
+    `ifdef STOP_COND
+      if (`STOP_COND) begin
+    `endif
         if (_T_4 & ~(~(io_dbus_valid & io_dbus_adrx[31]))) begin
-          $fwrite(32'h80000002,"Assertion failed\n    at VLdSt.scala:256 assert(!(io.dbus.valid && io.dbus.adrx(31)))\n"
-            ); // @[VLdSt.scala 256:9]
+          $fatal; // @[VLdSt.scala 259:9]
+        end
+    `ifdef STOP_COND
+      end
+    `endif
+    `endif // SYNTHESIS
+    `ifndef SYNTHESIS
+    `ifdef PRINTF_COND
+      if (`PRINTF_COND) begin
+    `endif
+        if (_T_4 & ~(~(io_dbus_valid & io_dbus_adrx[31]))) begin
+          $fwrite(32'h80000002,"Assertion failed\n    at VLdSt.scala:259 assert(!(io.dbus.valid && io.dbus.adrx(31)))\n"
+            ); // @[VLdSt.scala 259:9]
         end
     `ifdef PRINTF_COND
       end
@@ -99591,7 +90033,7 @@
       if (`STOP_COND) begin
     `endif
         if (_T_4 & ~(~(wrega_io_in_valid & ~wrega_io_in_ready))) begin
-          $fatal; // @[VLdSt.scala 273:9]
+          $fatal; // @[VLdSt.scala 276:9]
         end
     `ifdef STOP_COND
       end
@@ -99603,7 +90045,7 @@
     `endif
         if (_T_4 & ~(~(wrega_io_in_valid & ~wrega_io_in_ready))) begin
           $fwrite(32'h80000002,
-            "Assertion failed\n    at VLdSt.scala:273 assert(!(wrega.io.in.valid && !wrega.io.in.ready))\n"); // @[VLdSt.scala 273:9]
+            "Assertion failed\n    at VLdSt.scala:276 assert(!(wrega.io.in.valid && !wrega.io.in.ready))\n"); // @[VLdSt.scala 276:9]
         end
     `ifdef PRINTF_COND
       end
@@ -99614,7 +90056,7 @@
       if (`STOP_COND) begin
     `endif
         if (_T_4 & ~(~(wregd_io_in_valid & ~wregd_io_in_ready))) begin
-          $fatal; // @[VLdSt.scala 278:9]
+          $fatal; // @[VLdSt.scala 281:9]
         end
     `ifdef STOP_COND
       end
@@ -99626,7 +90068,7 @@
     `endif
         if (_T_4 & ~(~(wregd_io_in_valid & ~wregd_io_in_ready))) begin
           $fwrite(32'h80000002,
-            "Assertion failed\n    at VLdSt.scala:278 assert(!(wregd.io.in.valid && !wregd.io.in.ready))\n"); // @[VLdSt.scala 278:9]
+            "Assertion failed\n    at VLdSt.scala:281 assert(!(wregd.io.in.valid && !wregd.io.in.ready))\n"); // @[VLdSt.scala 281:9]
         end
     `ifdef PRINTF_COND
       end
@@ -99634,14 +90076,14 @@
     `endif // SYNTHESIS
   end
   always @(posedge clock or posedge reset) begin
-    if (reset) begin // @[VLdSt.scala 209:27]
+    if (reset) begin // @[VLdSt.scala 212:27]
       rdataEn <= 1'h0;
     end else begin
       rdataEn <= qoutEn & ctrl_io_in_bits_write;
     end
   end
   always @(posedge clock or posedge reset) begin
-    if (reset) begin // @[VLdSt.scala 266:45]
+    if (reset) begin // @[VLdSt.scala 269:45]
       wdataEn <= 1'h0;
     end else begin
       wdataEn <= io_dbus_valid & io_dbus_ready & ~io_dbus_write;
@@ -109442,7 +99884,7 @@
 `endif
 `endif // SYNTHESIS
 endmodule
-module Slice_7(
+module Slice_6(
   input         clock,
   input         reset,
   output        io_in_ready,
@@ -109581,7 +100023,7 @@
 `endif
 `endif // SYNTHESIS
 endmodule
-module Slice_8(
+module Slice_7(
   input          clock,
   input          reset,
   output         io_in_ready,
@@ -110021,7 +100463,7 @@
     .io_active(q_io_active),
     .io_nempty(q_io_nempty)
   );
-  Slice_7 ctrl ( // @[Slice.scala 9:11]
+  Slice_6 ctrl ( // @[Slice.scala 9:11]
     .clock(ctrl_clock),
     .reset(ctrl_reset),
     .io_in_ready(ctrl_io_in_ready),
@@ -110039,7 +100481,7 @@
     .io_out_bits_vstq(ctrl_io_out_bits_vstq),
     .io_out_bits_quad(ctrl_io_out_bits_quad)
   );
-  Slice_8 data ( // @[Slice.scala 9:11]
+  Slice_7 data ( // @[Slice.scala 9:11]
     .clock(data_clock),
     .reset(data_reset),
     .io_in_ready(data_io_in_ready),
@@ -121230,22 +111672,22 @@
   output         io_score_vinst_0_ready,
   input  [4:0]   io_score_vinst_0_addr,
   input  [31:0]  io_score_vinst_0_inst,
-  input  [5:0]   io_score_vinst_0_op,
+  input  [4:0]   io_score_vinst_0_op,
   input          io_score_vinst_1_valid,
   output         io_score_vinst_1_ready,
   input  [4:0]   io_score_vinst_1_addr,
   input  [31:0]  io_score_vinst_1_inst,
-  input  [5:0]   io_score_vinst_1_op,
+  input  [4:0]   io_score_vinst_1_op,
   input          io_score_vinst_2_valid,
   output         io_score_vinst_2_ready,
   input  [4:0]   io_score_vinst_2_addr,
   input  [31:0]  io_score_vinst_2_inst,
-  input  [5:0]   io_score_vinst_2_op,
+  input  [4:0]   io_score_vinst_2_op,
   input          io_score_vinst_3_valid,
   output         io_score_vinst_3_ready,
   input  [4:0]   io_score_vinst_3_addr,
   input  [31:0]  io_score_vinst_3_inst,
-  input  [5:0]   io_score_vinst_3_op,
+  input  [4:0]   io_score_vinst_3_op,
   input  [31:0]  io_score_rs_0_data,
   input  [31:0]  io_score_rs_1_data,
   input  [31:0]  io_score_rs_2_data,
@@ -121266,10 +111708,6 @@
   output         io_score_rd_3_valid,
   output [4:0]   io_score_rd_3_addr,
   output [31:0]  io_score_rd_3_data,
-  input  [31:0]  io_score_fs_0_data,
-  input  [31:0]  io_score_fs_1_data,
-  input  [31:0]  io_score_fs_2_data,
-  input  [31:0]  io_score_fs_3_data,
   output         io_score_mactive,
   output         io_score_undef,
   output         io_dbus_valid,
@@ -121305,22 +111743,22 @@
   wire  vinst_io_in_0_ready; // @[VInst.scala 9:18]
   wire [4:0] vinst_io_in_0_addr; // @[VInst.scala 9:18]
   wire [31:0] vinst_io_in_0_inst; // @[VInst.scala 9:18]
-  wire [5:0] vinst_io_in_0_op; // @[VInst.scala 9:18]
+  wire [4:0] vinst_io_in_0_op; // @[VInst.scala 9:18]
   wire  vinst_io_in_1_valid; // @[VInst.scala 9:18]
   wire  vinst_io_in_1_ready; // @[VInst.scala 9:18]
   wire [4:0] vinst_io_in_1_addr; // @[VInst.scala 9:18]
   wire [31:0] vinst_io_in_1_inst; // @[VInst.scala 9:18]
-  wire [5:0] vinst_io_in_1_op; // @[VInst.scala 9:18]
+  wire [4:0] vinst_io_in_1_op; // @[VInst.scala 9:18]
   wire  vinst_io_in_2_valid; // @[VInst.scala 9:18]
   wire  vinst_io_in_2_ready; // @[VInst.scala 9:18]
   wire [4:0] vinst_io_in_2_addr; // @[VInst.scala 9:18]
   wire [31:0] vinst_io_in_2_inst; // @[VInst.scala 9:18]
-  wire [5:0] vinst_io_in_2_op; // @[VInst.scala 9:18]
+  wire [4:0] vinst_io_in_2_op; // @[VInst.scala 9:18]
   wire  vinst_io_in_3_valid; // @[VInst.scala 9:18]
   wire  vinst_io_in_3_ready; // @[VInst.scala 9:18]
   wire [4:0] vinst_io_in_3_addr; // @[VInst.scala 9:18]
   wire [31:0] vinst_io_in_3_inst; // @[VInst.scala 9:18]
-  wire [5:0] vinst_io_in_3_op; // @[VInst.scala 9:18]
+  wire [4:0] vinst_io_in_3_op; // @[VInst.scala 9:18]
   wire [31:0] vinst_io_rs_0_data; // @[VInst.scala 9:18]
   wire [31:0] vinst_io_rs_1_data; // @[VInst.scala 9:18]
   wire [31:0] vinst_io_rs_2_data; // @[VInst.scala 9:18]
@@ -121341,10 +111779,6 @@
   wire  vinst_io_rd_3_valid; // @[VInst.scala 9:18]
   wire [4:0] vinst_io_rd_3_addr; // @[VInst.scala 9:18]
   wire [31:0] vinst_io_rd_3_data; // @[VInst.scala 9:18]
-  wire [31:0] vinst_io_fs_0_data; // @[VInst.scala 9:18]
-  wire [31:0] vinst_io_fs_1_data; // @[VInst.scala 9:18]
-  wire [31:0] vinst_io_fs_2_data; // @[VInst.scala 9:18]
-  wire [31:0] vinst_io_fs_3_data; // @[VInst.scala 9:18]
   wire  vinst_io_out_valid; // @[VInst.scala 9:18]
   wire  vinst_io_out_ready; // @[VInst.scala 9:18]
   wire  vinst_io_out_stall; // @[VInst.scala 9:18]
@@ -121544,174 +111978,174 @@
   wire [127:0] vdec_io_vrfsb_data; // @[VDecode.scala 9:18]
   wire  vdec_io_undef; // @[VDecode.scala 9:18]
   wire  vdec_io_nempty; // @[VDecode.scala 9:18]
-  wire  valu_clock; // @[VAlu.scala 29:18]
-  wire  valu_reset; // @[VAlu.scala 29:18]
-  wire  valu_io_in_ready; // @[VAlu.scala 29:18]
-  wire  valu_io_in_valid; // @[VAlu.scala 29:18]
-  wire  valu_io_in_bits_0_valid; // @[VAlu.scala 29:18]
-  wire [6:0] valu_io_in_bits_0_bits_op; // @[VAlu.scala 29:18]
-  wire [2:0] valu_io_in_bits_0_bits_f2; // @[VAlu.scala 29:18]
-  wire [2:0] valu_io_in_bits_0_bits_sz; // @[VAlu.scala 29:18]
-  wire  valu_io_in_bits_0_bits_m; // @[VAlu.scala 29:18]
-  wire [5:0] valu_io_in_bits_0_bits_vd_addr; // @[VAlu.scala 29:18]
-  wire [5:0] valu_io_in_bits_0_bits_ve_addr; // @[VAlu.scala 29:18]
-  wire [5:0] valu_io_in_bits_0_bits_vf_addr; // @[VAlu.scala 29:18]
-  wire [5:0] valu_io_in_bits_0_bits_vg_addr; // @[VAlu.scala 29:18]
-  wire  valu_io_in_bits_0_bits_vs_valid; // @[VAlu.scala 29:18]
-  wire [5:0] valu_io_in_bits_0_bits_vs_addr; // @[VAlu.scala 29:18]
-  wire [3:0] valu_io_in_bits_0_bits_vs_tag; // @[VAlu.scala 29:18]
-  wire  valu_io_in_bits_0_bits_vt_valid; // @[VAlu.scala 29:18]
-  wire [5:0] valu_io_in_bits_0_bits_vt_addr; // @[VAlu.scala 29:18]
-  wire [3:0] valu_io_in_bits_0_bits_vt_tag; // @[VAlu.scala 29:18]
-  wire  valu_io_in_bits_0_bits_vu_valid; // @[VAlu.scala 29:18]
-  wire [5:0] valu_io_in_bits_0_bits_vu_addr; // @[VAlu.scala 29:18]
-  wire [3:0] valu_io_in_bits_0_bits_vu_tag; // @[VAlu.scala 29:18]
-  wire  valu_io_in_bits_0_bits_vx_valid; // @[VAlu.scala 29:18]
-  wire [5:0] valu_io_in_bits_0_bits_vx_addr; // @[VAlu.scala 29:18]
-  wire [3:0] valu_io_in_bits_0_bits_vx_tag; // @[VAlu.scala 29:18]
-  wire  valu_io_in_bits_0_bits_vy_valid; // @[VAlu.scala 29:18]
-  wire [5:0] valu_io_in_bits_0_bits_vy_addr; // @[VAlu.scala 29:18]
-  wire [3:0] valu_io_in_bits_0_bits_vy_tag; // @[VAlu.scala 29:18]
-  wire  valu_io_in_bits_0_bits_vz_valid; // @[VAlu.scala 29:18]
-  wire [5:0] valu_io_in_bits_0_bits_vz_addr; // @[VAlu.scala 29:18]
-  wire [3:0] valu_io_in_bits_0_bits_vz_tag; // @[VAlu.scala 29:18]
-  wire  valu_io_in_bits_0_bits_sv_valid; // @[VAlu.scala 29:18]
-  wire [31:0] valu_io_in_bits_0_bits_sv_data; // @[VAlu.scala 29:18]
-  wire  valu_io_in_bits_0_bits_cmdsync; // @[VAlu.scala 29:18]
-  wire  valu_io_in_bits_1_valid; // @[VAlu.scala 29:18]
-  wire [6:0] valu_io_in_bits_1_bits_op; // @[VAlu.scala 29:18]
-  wire [2:0] valu_io_in_bits_1_bits_f2; // @[VAlu.scala 29:18]
-  wire [2:0] valu_io_in_bits_1_bits_sz; // @[VAlu.scala 29:18]
-  wire  valu_io_in_bits_1_bits_m; // @[VAlu.scala 29:18]
-  wire [5:0] valu_io_in_bits_1_bits_vd_addr; // @[VAlu.scala 29:18]
-  wire [5:0] valu_io_in_bits_1_bits_ve_addr; // @[VAlu.scala 29:18]
-  wire [5:0] valu_io_in_bits_1_bits_vf_addr; // @[VAlu.scala 29:18]
-  wire [5:0] valu_io_in_bits_1_bits_vg_addr; // @[VAlu.scala 29:18]
-  wire  valu_io_in_bits_1_bits_vs_valid; // @[VAlu.scala 29:18]
-  wire [5:0] valu_io_in_bits_1_bits_vs_addr; // @[VAlu.scala 29:18]
-  wire [3:0] valu_io_in_bits_1_bits_vs_tag; // @[VAlu.scala 29:18]
-  wire  valu_io_in_bits_1_bits_vt_valid; // @[VAlu.scala 29:18]
-  wire [5:0] valu_io_in_bits_1_bits_vt_addr; // @[VAlu.scala 29:18]
-  wire [3:0] valu_io_in_bits_1_bits_vt_tag; // @[VAlu.scala 29:18]
-  wire  valu_io_in_bits_1_bits_vu_valid; // @[VAlu.scala 29:18]
-  wire [5:0] valu_io_in_bits_1_bits_vu_addr; // @[VAlu.scala 29:18]
-  wire [3:0] valu_io_in_bits_1_bits_vu_tag; // @[VAlu.scala 29:18]
-  wire  valu_io_in_bits_1_bits_vx_valid; // @[VAlu.scala 29:18]
-  wire [5:0] valu_io_in_bits_1_bits_vx_addr; // @[VAlu.scala 29:18]
-  wire [3:0] valu_io_in_bits_1_bits_vx_tag; // @[VAlu.scala 29:18]
-  wire  valu_io_in_bits_1_bits_vy_valid; // @[VAlu.scala 29:18]
-  wire [5:0] valu_io_in_bits_1_bits_vy_addr; // @[VAlu.scala 29:18]
-  wire [3:0] valu_io_in_bits_1_bits_vy_tag; // @[VAlu.scala 29:18]
-  wire  valu_io_in_bits_1_bits_vz_valid; // @[VAlu.scala 29:18]
-  wire [5:0] valu_io_in_bits_1_bits_vz_addr; // @[VAlu.scala 29:18]
-  wire [3:0] valu_io_in_bits_1_bits_vz_tag; // @[VAlu.scala 29:18]
-  wire  valu_io_in_bits_1_bits_sv_valid; // @[VAlu.scala 29:18]
-  wire [31:0] valu_io_in_bits_1_bits_sv_data; // @[VAlu.scala 29:18]
-  wire  valu_io_in_bits_1_bits_cmdsync; // @[VAlu.scala 29:18]
-  wire  valu_io_in_bits_2_valid; // @[VAlu.scala 29:18]
-  wire [6:0] valu_io_in_bits_2_bits_op; // @[VAlu.scala 29:18]
-  wire [2:0] valu_io_in_bits_2_bits_f2; // @[VAlu.scala 29:18]
-  wire [2:0] valu_io_in_bits_2_bits_sz; // @[VAlu.scala 29:18]
-  wire  valu_io_in_bits_2_bits_m; // @[VAlu.scala 29:18]
-  wire [5:0] valu_io_in_bits_2_bits_vd_addr; // @[VAlu.scala 29:18]
-  wire [5:0] valu_io_in_bits_2_bits_ve_addr; // @[VAlu.scala 29:18]
-  wire [5:0] valu_io_in_bits_2_bits_vf_addr; // @[VAlu.scala 29:18]
-  wire [5:0] valu_io_in_bits_2_bits_vg_addr; // @[VAlu.scala 29:18]
-  wire  valu_io_in_bits_2_bits_vs_valid; // @[VAlu.scala 29:18]
-  wire [5:0] valu_io_in_bits_2_bits_vs_addr; // @[VAlu.scala 29:18]
-  wire [3:0] valu_io_in_bits_2_bits_vs_tag; // @[VAlu.scala 29:18]
-  wire  valu_io_in_bits_2_bits_vt_valid; // @[VAlu.scala 29:18]
-  wire [5:0] valu_io_in_bits_2_bits_vt_addr; // @[VAlu.scala 29:18]
-  wire [3:0] valu_io_in_bits_2_bits_vt_tag; // @[VAlu.scala 29:18]
-  wire  valu_io_in_bits_2_bits_vu_valid; // @[VAlu.scala 29:18]
-  wire [5:0] valu_io_in_bits_2_bits_vu_addr; // @[VAlu.scala 29:18]
-  wire [3:0] valu_io_in_bits_2_bits_vu_tag; // @[VAlu.scala 29:18]
-  wire  valu_io_in_bits_2_bits_vx_valid; // @[VAlu.scala 29:18]
-  wire [5:0] valu_io_in_bits_2_bits_vx_addr; // @[VAlu.scala 29:18]
-  wire [3:0] valu_io_in_bits_2_bits_vx_tag; // @[VAlu.scala 29:18]
-  wire  valu_io_in_bits_2_bits_vy_valid; // @[VAlu.scala 29:18]
-  wire [5:0] valu_io_in_bits_2_bits_vy_addr; // @[VAlu.scala 29:18]
-  wire [3:0] valu_io_in_bits_2_bits_vy_tag; // @[VAlu.scala 29:18]
-  wire  valu_io_in_bits_2_bits_vz_valid; // @[VAlu.scala 29:18]
-  wire [5:0] valu_io_in_bits_2_bits_vz_addr; // @[VAlu.scala 29:18]
-  wire [3:0] valu_io_in_bits_2_bits_vz_tag; // @[VAlu.scala 29:18]
-  wire  valu_io_in_bits_2_bits_sv_valid; // @[VAlu.scala 29:18]
-  wire [31:0] valu_io_in_bits_2_bits_sv_data; // @[VAlu.scala 29:18]
-  wire  valu_io_in_bits_2_bits_cmdsync; // @[VAlu.scala 29:18]
-  wire  valu_io_in_bits_3_valid; // @[VAlu.scala 29:18]
-  wire [6:0] valu_io_in_bits_3_bits_op; // @[VAlu.scala 29:18]
-  wire [2:0] valu_io_in_bits_3_bits_f2; // @[VAlu.scala 29:18]
-  wire [2:0] valu_io_in_bits_3_bits_sz; // @[VAlu.scala 29:18]
-  wire  valu_io_in_bits_3_bits_m; // @[VAlu.scala 29:18]
-  wire [5:0] valu_io_in_bits_3_bits_vd_addr; // @[VAlu.scala 29:18]
-  wire [5:0] valu_io_in_bits_3_bits_ve_addr; // @[VAlu.scala 29:18]
-  wire [5:0] valu_io_in_bits_3_bits_vf_addr; // @[VAlu.scala 29:18]
-  wire [5:0] valu_io_in_bits_3_bits_vg_addr; // @[VAlu.scala 29:18]
-  wire  valu_io_in_bits_3_bits_vs_valid; // @[VAlu.scala 29:18]
-  wire [5:0] valu_io_in_bits_3_bits_vs_addr; // @[VAlu.scala 29:18]
-  wire [3:0] valu_io_in_bits_3_bits_vs_tag; // @[VAlu.scala 29:18]
-  wire  valu_io_in_bits_3_bits_vt_valid; // @[VAlu.scala 29:18]
-  wire [5:0] valu_io_in_bits_3_bits_vt_addr; // @[VAlu.scala 29:18]
-  wire [3:0] valu_io_in_bits_3_bits_vt_tag; // @[VAlu.scala 29:18]
-  wire  valu_io_in_bits_3_bits_vu_valid; // @[VAlu.scala 29:18]
-  wire [5:0] valu_io_in_bits_3_bits_vu_addr; // @[VAlu.scala 29:18]
-  wire [3:0] valu_io_in_bits_3_bits_vu_tag; // @[VAlu.scala 29:18]
-  wire  valu_io_in_bits_3_bits_vx_valid; // @[VAlu.scala 29:18]
-  wire [5:0] valu_io_in_bits_3_bits_vx_addr; // @[VAlu.scala 29:18]
-  wire [3:0] valu_io_in_bits_3_bits_vx_tag; // @[VAlu.scala 29:18]
-  wire  valu_io_in_bits_3_bits_vy_valid; // @[VAlu.scala 29:18]
-  wire [5:0] valu_io_in_bits_3_bits_vy_addr; // @[VAlu.scala 29:18]
-  wire [3:0] valu_io_in_bits_3_bits_vy_tag; // @[VAlu.scala 29:18]
-  wire  valu_io_in_bits_3_bits_vz_valid; // @[VAlu.scala 29:18]
-  wire [5:0] valu_io_in_bits_3_bits_vz_addr; // @[VAlu.scala 29:18]
-  wire [3:0] valu_io_in_bits_3_bits_vz_tag; // @[VAlu.scala 29:18]
-  wire  valu_io_in_bits_3_bits_sv_valid; // @[VAlu.scala 29:18]
-  wire [31:0] valu_io_in_bits_3_bits_sv_data; // @[VAlu.scala 29:18]
-  wire  valu_io_in_bits_3_bits_cmdsync; // @[VAlu.scala 29:18]
-  wire [63:0] valu_io_active; // @[VAlu.scala 29:18]
-  wire [127:0] valu_io_vrfsb; // @[VAlu.scala 29:18]
-  wire  valu_io_read_0_valid; // @[VAlu.scala 29:18]
-  wire [5:0] valu_io_read_0_addr; // @[VAlu.scala 29:18]
-  wire [255:0] valu_io_read_0_data; // @[VAlu.scala 29:18]
-  wire  valu_io_read_1_valid; // @[VAlu.scala 29:18]
-  wire [5:0] valu_io_read_1_addr; // @[VAlu.scala 29:18]
-  wire [255:0] valu_io_read_1_data; // @[VAlu.scala 29:18]
-  wire  valu_io_read_2_valid; // @[VAlu.scala 29:18]
-  wire [5:0] valu_io_read_2_addr; // @[VAlu.scala 29:18]
-  wire [255:0] valu_io_read_2_data; // @[VAlu.scala 29:18]
-  wire  valu_io_read_3_valid; // @[VAlu.scala 29:18]
-  wire [5:0] valu_io_read_3_addr; // @[VAlu.scala 29:18]
-  wire [255:0] valu_io_read_3_data; // @[VAlu.scala 29:18]
-  wire  valu_io_read_4_valid; // @[VAlu.scala 29:18]
-  wire [5:0] valu_io_read_4_addr; // @[VAlu.scala 29:18]
-  wire [255:0] valu_io_read_4_data; // @[VAlu.scala 29:18]
-  wire  valu_io_read_5_valid; // @[VAlu.scala 29:18]
-  wire [5:0] valu_io_read_5_addr; // @[VAlu.scala 29:18]
-  wire [255:0] valu_io_read_5_data; // @[VAlu.scala 29:18]
-  wire  valu_io_write_0_valid; // @[VAlu.scala 29:18]
-  wire [5:0] valu_io_write_0_addr; // @[VAlu.scala 29:18]
-  wire [255:0] valu_io_write_0_data; // @[VAlu.scala 29:18]
-  wire  valu_io_write_1_valid; // @[VAlu.scala 29:18]
-  wire [5:0] valu_io_write_1_addr; // @[VAlu.scala 29:18]
-  wire [255:0] valu_io_write_1_data; // @[VAlu.scala 29:18]
-  wire  valu_io_write_2_valid; // @[VAlu.scala 29:18]
-  wire [5:0] valu_io_write_2_addr; // @[VAlu.scala 29:18]
-  wire [255:0] valu_io_write_2_data; // @[VAlu.scala 29:18]
-  wire  valu_io_write_3_valid; // @[VAlu.scala 29:18]
-  wire [5:0] valu_io_write_3_addr; // @[VAlu.scala 29:18]
-  wire [255:0] valu_io_write_3_data; // @[VAlu.scala 29:18]
-  wire  valu_io_whint_0_valid; // @[VAlu.scala 29:18]
-  wire [5:0] valu_io_whint_0_addr; // @[VAlu.scala 29:18]
-  wire  valu_io_whint_1_valid; // @[VAlu.scala 29:18]
-  wire [5:0] valu_io_whint_1_addr; // @[VAlu.scala 29:18]
-  wire  valu_io_whint_2_valid; // @[VAlu.scala 29:18]
-  wire [5:0] valu_io_whint_2_addr; // @[VAlu.scala 29:18]
-  wire  valu_io_whint_3_valid; // @[VAlu.scala 29:18]
-  wire [5:0] valu_io_whint_3_addr; // @[VAlu.scala 29:18]
-  wire  valu_io_scalar_0_valid; // @[VAlu.scala 29:18]
-  wire [31:0] valu_io_scalar_0_data; // @[VAlu.scala 29:18]
-  wire  valu_io_scalar_1_valid; // @[VAlu.scala 29:18]
-  wire [31:0] valu_io_scalar_1_data; // @[VAlu.scala 29:18]
+  wire  valu_clock; // @[VAlu.scala 9:18]
+  wire  valu_reset; // @[VAlu.scala 9:18]
+  wire  valu_io_in_ready; // @[VAlu.scala 9:18]
+  wire  valu_io_in_valid; // @[VAlu.scala 9:18]
+  wire  valu_io_in_bits_0_valid; // @[VAlu.scala 9:18]
+  wire [6:0] valu_io_in_bits_0_bits_op; // @[VAlu.scala 9:18]
+  wire [2:0] valu_io_in_bits_0_bits_f2; // @[VAlu.scala 9:18]
+  wire [2:0] valu_io_in_bits_0_bits_sz; // @[VAlu.scala 9:18]
+  wire  valu_io_in_bits_0_bits_m; // @[VAlu.scala 9:18]
+  wire [5:0] valu_io_in_bits_0_bits_vd_addr; // @[VAlu.scala 9:18]
+  wire [5:0] valu_io_in_bits_0_bits_ve_addr; // @[VAlu.scala 9:18]
+  wire [5:0] valu_io_in_bits_0_bits_vf_addr; // @[VAlu.scala 9:18]
+  wire [5:0] valu_io_in_bits_0_bits_vg_addr; // @[VAlu.scala 9:18]
+  wire  valu_io_in_bits_0_bits_vs_valid; // @[VAlu.scala 9:18]
+  wire [5:0] valu_io_in_bits_0_bits_vs_addr; // @[VAlu.scala 9:18]
+  wire [3:0] valu_io_in_bits_0_bits_vs_tag; // @[VAlu.scala 9:18]
+  wire  valu_io_in_bits_0_bits_vt_valid; // @[VAlu.scala 9:18]
+  wire [5:0] valu_io_in_bits_0_bits_vt_addr; // @[VAlu.scala 9:18]
+  wire [3:0] valu_io_in_bits_0_bits_vt_tag; // @[VAlu.scala 9:18]
+  wire  valu_io_in_bits_0_bits_vu_valid; // @[VAlu.scala 9:18]
+  wire [5:0] valu_io_in_bits_0_bits_vu_addr; // @[VAlu.scala 9:18]
+  wire [3:0] valu_io_in_bits_0_bits_vu_tag; // @[VAlu.scala 9:18]
+  wire  valu_io_in_bits_0_bits_vx_valid; // @[VAlu.scala 9:18]
+  wire [5:0] valu_io_in_bits_0_bits_vx_addr; // @[VAlu.scala 9:18]
+  wire [3:0] valu_io_in_bits_0_bits_vx_tag; // @[VAlu.scala 9:18]
+  wire  valu_io_in_bits_0_bits_vy_valid; // @[VAlu.scala 9:18]
+  wire [5:0] valu_io_in_bits_0_bits_vy_addr; // @[VAlu.scala 9:18]
+  wire [3:0] valu_io_in_bits_0_bits_vy_tag; // @[VAlu.scala 9:18]
+  wire  valu_io_in_bits_0_bits_vz_valid; // @[VAlu.scala 9:18]
+  wire [5:0] valu_io_in_bits_0_bits_vz_addr; // @[VAlu.scala 9:18]
+  wire [3:0] valu_io_in_bits_0_bits_vz_tag; // @[VAlu.scala 9:18]
+  wire  valu_io_in_bits_0_bits_sv_valid; // @[VAlu.scala 9:18]
+  wire [31:0] valu_io_in_bits_0_bits_sv_data; // @[VAlu.scala 9:18]
+  wire  valu_io_in_bits_0_bits_cmdsync; // @[VAlu.scala 9:18]
+  wire  valu_io_in_bits_1_valid; // @[VAlu.scala 9:18]
+  wire [6:0] valu_io_in_bits_1_bits_op; // @[VAlu.scala 9:18]
+  wire [2:0] valu_io_in_bits_1_bits_f2; // @[VAlu.scala 9:18]
+  wire [2:0] valu_io_in_bits_1_bits_sz; // @[VAlu.scala 9:18]
+  wire  valu_io_in_bits_1_bits_m; // @[VAlu.scala 9:18]
+  wire [5:0] valu_io_in_bits_1_bits_vd_addr; // @[VAlu.scala 9:18]
+  wire [5:0] valu_io_in_bits_1_bits_ve_addr; // @[VAlu.scala 9:18]
+  wire [5:0] valu_io_in_bits_1_bits_vf_addr; // @[VAlu.scala 9:18]
+  wire [5:0] valu_io_in_bits_1_bits_vg_addr; // @[VAlu.scala 9:18]
+  wire  valu_io_in_bits_1_bits_vs_valid; // @[VAlu.scala 9:18]
+  wire [5:0] valu_io_in_bits_1_bits_vs_addr; // @[VAlu.scala 9:18]
+  wire [3:0] valu_io_in_bits_1_bits_vs_tag; // @[VAlu.scala 9:18]
+  wire  valu_io_in_bits_1_bits_vt_valid; // @[VAlu.scala 9:18]
+  wire [5:0] valu_io_in_bits_1_bits_vt_addr; // @[VAlu.scala 9:18]
+  wire [3:0] valu_io_in_bits_1_bits_vt_tag; // @[VAlu.scala 9:18]
+  wire  valu_io_in_bits_1_bits_vu_valid; // @[VAlu.scala 9:18]
+  wire [5:0] valu_io_in_bits_1_bits_vu_addr; // @[VAlu.scala 9:18]
+  wire [3:0] valu_io_in_bits_1_bits_vu_tag; // @[VAlu.scala 9:18]
+  wire  valu_io_in_bits_1_bits_vx_valid; // @[VAlu.scala 9:18]
+  wire [5:0] valu_io_in_bits_1_bits_vx_addr; // @[VAlu.scala 9:18]
+  wire [3:0] valu_io_in_bits_1_bits_vx_tag; // @[VAlu.scala 9:18]
+  wire  valu_io_in_bits_1_bits_vy_valid; // @[VAlu.scala 9:18]
+  wire [5:0] valu_io_in_bits_1_bits_vy_addr; // @[VAlu.scala 9:18]
+  wire [3:0] valu_io_in_bits_1_bits_vy_tag; // @[VAlu.scala 9:18]
+  wire  valu_io_in_bits_1_bits_vz_valid; // @[VAlu.scala 9:18]
+  wire [5:0] valu_io_in_bits_1_bits_vz_addr; // @[VAlu.scala 9:18]
+  wire [3:0] valu_io_in_bits_1_bits_vz_tag; // @[VAlu.scala 9:18]
+  wire  valu_io_in_bits_1_bits_sv_valid; // @[VAlu.scala 9:18]
+  wire [31:0] valu_io_in_bits_1_bits_sv_data; // @[VAlu.scala 9:18]
+  wire  valu_io_in_bits_1_bits_cmdsync; // @[VAlu.scala 9:18]
+  wire  valu_io_in_bits_2_valid; // @[VAlu.scala 9:18]
+  wire [6:0] valu_io_in_bits_2_bits_op; // @[VAlu.scala 9:18]
+  wire [2:0] valu_io_in_bits_2_bits_f2; // @[VAlu.scala 9:18]
+  wire [2:0] valu_io_in_bits_2_bits_sz; // @[VAlu.scala 9:18]
+  wire  valu_io_in_bits_2_bits_m; // @[VAlu.scala 9:18]
+  wire [5:0] valu_io_in_bits_2_bits_vd_addr; // @[VAlu.scala 9:18]
+  wire [5:0] valu_io_in_bits_2_bits_ve_addr; // @[VAlu.scala 9:18]
+  wire [5:0] valu_io_in_bits_2_bits_vf_addr; // @[VAlu.scala 9:18]
+  wire [5:0] valu_io_in_bits_2_bits_vg_addr; // @[VAlu.scala 9:18]
+  wire  valu_io_in_bits_2_bits_vs_valid; // @[VAlu.scala 9:18]
+  wire [5:0] valu_io_in_bits_2_bits_vs_addr; // @[VAlu.scala 9:18]
+  wire [3:0] valu_io_in_bits_2_bits_vs_tag; // @[VAlu.scala 9:18]
+  wire  valu_io_in_bits_2_bits_vt_valid; // @[VAlu.scala 9:18]
+  wire [5:0] valu_io_in_bits_2_bits_vt_addr; // @[VAlu.scala 9:18]
+  wire [3:0] valu_io_in_bits_2_bits_vt_tag; // @[VAlu.scala 9:18]
+  wire  valu_io_in_bits_2_bits_vu_valid; // @[VAlu.scala 9:18]
+  wire [5:0] valu_io_in_bits_2_bits_vu_addr; // @[VAlu.scala 9:18]
+  wire [3:0] valu_io_in_bits_2_bits_vu_tag; // @[VAlu.scala 9:18]
+  wire  valu_io_in_bits_2_bits_vx_valid; // @[VAlu.scala 9:18]
+  wire [5:0] valu_io_in_bits_2_bits_vx_addr; // @[VAlu.scala 9:18]
+  wire [3:0] valu_io_in_bits_2_bits_vx_tag; // @[VAlu.scala 9:18]
+  wire  valu_io_in_bits_2_bits_vy_valid; // @[VAlu.scala 9:18]
+  wire [5:0] valu_io_in_bits_2_bits_vy_addr; // @[VAlu.scala 9:18]
+  wire [3:0] valu_io_in_bits_2_bits_vy_tag; // @[VAlu.scala 9:18]
+  wire  valu_io_in_bits_2_bits_vz_valid; // @[VAlu.scala 9:18]
+  wire [5:0] valu_io_in_bits_2_bits_vz_addr; // @[VAlu.scala 9:18]
+  wire [3:0] valu_io_in_bits_2_bits_vz_tag; // @[VAlu.scala 9:18]
+  wire  valu_io_in_bits_2_bits_sv_valid; // @[VAlu.scala 9:18]
+  wire [31:0] valu_io_in_bits_2_bits_sv_data; // @[VAlu.scala 9:18]
+  wire  valu_io_in_bits_2_bits_cmdsync; // @[VAlu.scala 9:18]
+  wire  valu_io_in_bits_3_valid; // @[VAlu.scala 9:18]
+  wire [6:0] valu_io_in_bits_3_bits_op; // @[VAlu.scala 9:18]
+  wire [2:0] valu_io_in_bits_3_bits_f2; // @[VAlu.scala 9:18]
+  wire [2:0] valu_io_in_bits_3_bits_sz; // @[VAlu.scala 9:18]
+  wire  valu_io_in_bits_3_bits_m; // @[VAlu.scala 9:18]
+  wire [5:0] valu_io_in_bits_3_bits_vd_addr; // @[VAlu.scala 9:18]
+  wire [5:0] valu_io_in_bits_3_bits_ve_addr; // @[VAlu.scala 9:18]
+  wire [5:0] valu_io_in_bits_3_bits_vf_addr; // @[VAlu.scala 9:18]
+  wire [5:0] valu_io_in_bits_3_bits_vg_addr; // @[VAlu.scala 9:18]
+  wire  valu_io_in_bits_3_bits_vs_valid; // @[VAlu.scala 9:18]
+  wire [5:0] valu_io_in_bits_3_bits_vs_addr; // @[VAlu.scala 9:18]
+  wire [3:0] valu_io_in_bits_3_bits_vs_tag; // @[VAlu.scala 9:18]
+  wire  valu_io_in_bits_3_bits_vt_valid; // @[VAlu.scala 9:18]
+  wire [5:0] valu_io_in_bits_3_bits_vt_addr; // @[VAlu.scala 9:18]
+  wire [3:0] valu_io_in_bits_3_bits_vt_tag; // @[VAlu.scala 9:18]
+  wire  valu_io_in_bits_3_bits_vu_valid; // @[VAlu.scala 9:18]
+  wire [5:0] valu_io_in_bits_3_bits_vu_addr; // @[VAlu.scala 9:18]
+  wire [3:0] valu_io_in_bits_3_bits_vu_tag; // @[VAlu.scala 9:18]
+  wire  valu_io_in_bits_3_bits_vx_valid; // @[VAlu.scala 9:18]
+  wire [5:0] valu_io_in_bits_3_bits_vx_addr; // @[VAlu.scala 9:18]
+  wire [3:0] valu_io_in_bits_3_bits_vx_tag; // @[VAlu.scala 9:18]
+  wire  valu_io_in_bits_3_bits_vy_valid; // @[VAlu.scala 9:18]
+  wire [5:0] valu_io_in_bits_3_bits_vy_addr; // @[VAlu.scala 9:18]
+  wire [3:0] valu_io_in_bits_3_bits_vy_tag; // @[VAlu.scala 9:18]
+  wire  valu_io_in_bits_3_bits_vz_valid; // @[VAlu.scala 9:18]
+  wire [5:0] valu_io_in_bits_3_bits_vz_addr; // @[VAlu.scala 9:18]
+  wire [3:0] valu_io_in_bits_3_bits_vz_tag; // @[VAlu.scala 9:18]
+  wire  valu_io_in_bits_3_bits_sv_valid; // @[VAlu.scala 9:18]
+  wire [31:0] valu_io_in_bits_3_bits_sv_data; // @[VAlu.scala 9:18]
+  wire  valu_io_in_bits_3_bits_cmdsync; // @[VAlu.scala 9:18]
+  wire [63:0] valu_io_active; // @[VAlu.scala 9:18]
+  wire [127:0] valu_io_vrfsb; // @[VAlu.scala 9:18]
+  wire  valu_io_read_0_valid; // @[VAlu.scala 9:18]
+  wire [5:0] valu_io_read_0_addr; // @[VAlu.scala 9:18]
+  wire [255:0] valu_io_read_0_data; // @[VAlu.scala 9:18]
+  wire  valu_io_read_1_valid; // @[VAlu.scala 9:18]
+  wire [5:0] valu_io_read_1_addr; // @[VAlu.scala 9:18]
+  wire [255:0] valu_io_read_1_data; // @[VAlu.scala 9:18]
+  wire  valu_io_read_2_valid; // @[VAlu.scala 9:18]
+  wire [5:0] valu_io_read_2_addr; // @[VAlu.scala 9:18]
+  wire [255:0] valu_io_read_2_data; // @[VAlu.scala 9:18]
+  wire  valu_io_read_3_valid; // @[VAlu.scala 9:18]
+  wire [5:0] valu_io_read_3_addr; // @[VAlu.scala 9:18]
+  wire [255:0] valu_io_read_3_data; // @[VAlu.scala 9:18]
+  wire  valu_io_read_4_valid; // @[VAlu.scala 9:18]
+  wire [5:0] valu_io_read_4_addr; // @[VAlu.scala 9:18]
+  wire [255:0] valu_io_read_4_data; // @[VAlu.scala 9:18]
+  wire  valu_io_read_5_valid; // @[VAlu.scala 9:18]
+  wire [5:0] valu_io_read_5_addr; // @[VAlu.scala 9:18]
+  wire [255:0] valu_io_read_5_data; // @[VAlu.scala 9:18]
+  wire  valu_io_write_0_valid; // @[VAlu.scala 9:18]
+  wire [5:0] valu_io_write_0_addr; // @[VAlu.scala 9:18]
+  wire [255:0] valu_io_write_0_data; // @[VAlu.scala 9:18]
+  wire  valu_io_write_1_valid; // @[VAlu.scala 9:18]
+  wire [5:0] valu_io_write_1_addr; // @[VAlu.scala 9:18]
+  wire [255:0] valu_io_write_1_data; // @[VAlu.scala 9:18]
+  wire  valu_io_write_2_valid; // @[VAlu.scala 9:18]
+  wire [5:0] valu_io_write_2_addr; // @[VAlu.scala 9:18]
+  wire [255:0] valu_io_write_2_data; // @[VAlu.scala 9:18]
+  wire  valu_io_write_3_valid; // @[VAlu.scala 9:18]
+  wire [5:0] valu_io_write_3_addr; // @[VAlu.scala 9:18]
+  wire [255:0] valu_io_write_3_data; // @[VAlu.scala 9:18]
+  wire  valu_io_whint_0_valid; // @[VAlu.scala 9:18]
+  wire [5:0] valu_io_whint_0_addr; // @[VAlu.scala 9:18]
+  wire  valu_io_whint_1_valid; // @[VAlu.scala 9:18]
+  wire [5:0] valu_io_whint_1_addr; // @[VAlu.scala 9:18]
+  wire  valu_io_whint_2_valid; // @[VAlu.scala 9:18]
+  wire [5:0] valu_io_whint_2_addr; // @[VAlu.scala 9:18]
+  wire  valu_io_whint_3_valid; // @[VAlu.scala 9:18]
+  wire [5:0] valu_io_whint_3_addr; // @[VAlu.scala 9:18]
+  wire  valu_io_scalar_0_valid; // @[VAlu.scala 9:18]
+  wire [31:0] valu_io_scalar_0_data; // @[VAlu.scala 9:18]
+  wire  valu_io_scalar_1_valid; // @[VAlu.scala 9:18]
+  wire [31:0] valu_io_scalar_1_data; // @[VAlu.scala 9:18]
   wire  vconv_clock; // @[VConvCtrl.scala 9:18]
   wire  vconv_reset; // @[VConvCtrl.scala 9:18]
   wire  vconv_io_in_ready; // @[VConvCtrl.scala 9:18]
@@ -122015,69 +112449,69 @@
   wire  vrf_io_vrfsb_set_valid; // @[VRegfile.scala 9:18]
   wire [127:0] vrf_io_vrfsb_set_bits; // @[VRegfile.scala 9:18]
   wire [127:0] vrf_io_vrfsb_data; // @[VRegfile.scala 9:18]
-  wire  _T = vst_io_read_valid & vst_io_read_ready; // @[VCore.scala 71:41]
-  wire  _T_1 = vldst_io_read_valid & vldst_io_read_ready; // @[VCore.scala 72:43]
+  wire  _T = vst_io_read_valid & vst_io_read_ready; // @[VCore.scala 69:41]
+  wire  _T_1 = vldst_io_read_valid & vldst_io_read_ready; // @[VCore.scala 70:43]
   wire [1:0] _T_2 = {_T,_T_1}; // @[Cat.scala 31:58]
   wire [1:0] _T_5 = _T_2[0] + _T_2[1]; // @[Bitwise.scala 48:55]
-  wire  _T_7 = _T_5 <= 2'h1; // @[VCore.scala 72:68]
-  wire  _T_9 = ~reset; // @[VCore.scala 71:9]
-  wire [63:0] _vdec_io_active_T = valu_io_active | vconv_io_active; // @[VCore.scala 78:36]
-  wire [63:0] _vdec_io_active_T_1 = _vdec_io_active_T | vldst_io_active; // @[VCore.scala 78:54]
-  wire  _aluvalid_T = vdec_io_out_3_valid & vdec_io_cmdq_3_alu; // @[VCore.scala 122:43]
-  wire  _aluvalid_T_1 = vdec_io_out_2_valid & vdec_io_cmdq_2_alu; // @[VCore.scala 123:43]
-  wire  _aluvalid_T_2 = vdec_io_out_1_valid & vdec_io_cmdq_1_alu; // @[VCore.scala 124:43]
-  wire  _aluvalid_T_3 = vdec_io_out_0_valid & vdec_io_cmdq_0_alu; // @[VCore.scala 125:43]
+  wire  _T_7 = _T_5 <= 2'h1; // @[VCore.scala 70:68]
+  wire  _T_9 = ~reset; // @[VCore.scala 69:9]
+  wire [63:0] _vdec_io_active_T = valu_io_active | vconv_io_active; // @[VCore.scala 76:36]
+  wire [63:0] _vdec_io_active_T_1 = _vdec_io_active_T | vldst_io_active; // @[VCore.scala 76:54]
+  wire  _aluvalid_T = vdec_io_out_3_valid & vdec_io_cmdq_3_alu; // @[VCore.scala 120:43]
+  wire  _aluvalid_T_1 = vdec_io_out_2_valid & vdec_io_cmdq_2_alu; // @[VCore.scala 121:43]
+  wire  _aluvalid_T_2 = vdec_io_out_1_valid & vdec_io_cmdq_1_alu; // @[VCore.scala 122:43]
+  wire  _aluvalid_T_3 = vdec_io_out_0_valid & vdec_io_cmdq_0_alu; // @[VCore.scala 123:43]
   wire [3:0] aluvalid = {_aluvalid_T,_aluvalid_T_1,_aluvalid_T_2,_aluvalid_T_3}; // @[Cat.scala 31:58]
-  wire  _aluready_T = valu_io_in_ready & vdec_io_cmdq_3_alu; // @[VCore.scala 127:39]
-  wire  _aluready_T_1 = valu_io_in_ready & vdec_io_cmdq_2_alu; // @[VCore.scala 128:39]
-  wire  _aluready_T_2 = valu_io_in_ready & vdec_io_cmdq_1_alu; // @[VCore.scala 129:39]
-  wire  _aluready_T_3 = valu_io_in_ready & vdec_io_cmdq_0_alu; // @[VCore.scala 130:39]
+  wire  _aluready_T = valu_io_in_ready & vdec_io_cmdq_3_alu; // @[VCore.scala 125:39]
+  wire  _aluready_T_1 = valu_io_in_ready & vdec_io_cmdq_2_alu; // @[VCore.scala 126:39]
+  wire  _aluready_T_2 = valu_io_in_ready & vdec_io_cmdq_1_alu; // @[VCore.scala 127:39]
+  wire  _aluready_T_3 = valu_io_in_ready & vdec_io_cmdq_0_alu; // @[VCore.scala 128:39]
   wire [3:0] aluready = {_aluready_T,_aluready_T_1,_aluready_T_2,_aluready_T_3}; // @[Cat.scala 31:58]
-  wire  _convvalid_T = vdec_io_out_3_valid & vdec_io_cmdq_3_conv; // @[VCore.scala 167:44]
-  wire  _convvalid_T_1 = vdec_io_out_2_valid & vdec_io_cmdq_2_conv; // @[VCore.scala 168:44]
-  wire  _convvalid_T_2 = vdec_io_out_1_valid & vdec_io_cmdq_1_conv; // @[VCore.scala 169:44]
-  wire  _convvalid_T_3 = vdec_io_out_0_valid & vdec_io_cmdq_0_conv; // @[VCore.scala 170:44]
+  wire  _convvalid_T = vdec_io_out_3_valid & vdec_io_cmdq_3_conv; // @[VCore.scala 165:44]
+  wire  _convvalid_T_1 = vdec_io_out_2_valid & vdec_io_cmdq_2_conv; // @[VCore.scala 166:44]
+  wire  _convvalid_T_2 = vdec_io_out_1_valid & vdec_io_cmdq_1_conv; // @[VCore.scala 167:44]
+  wire  _convvalid_T_3 = vdec_io_out_0_valid & vdec_io_cmdq_0_conv; // @[VCore.scala 168:44]
   wire [3:0] convvalid = {_convvalid_T,_convvalid_T_1,_convvalid_T_2,_convvalid_T_3}; // @[Cat.scala 31:58]
-  wire  _convready_T = vconv_io_in_ready & vdec_io_cmdq_3_conv; // @[VCore.scala 172:41]
-  wire  _convready_T_1 = vconv_io_in_ready & vdec_io_cmdq_2_conv; // @[VCore.scala 173:41]
-  wire  _convready_T_2 = vconv_io_in_ready & vdec_io_cmdq_1_conv; // @[VCore.scala 174:41]
-  wire  _convready_T_3 = vconv_io_in_ready & vdec_io_cmdq_0_conv; // @[VCore.scala 175:41]
+  wire  _convready_T = vconv_io_in_ready & vdec_io_cmdq_3_conv; // @[VCore.scala 170:41]
+  wire  _convready_T_1 = vconv_io_in_ready & vdec_io_cmdq_2_conv; // @[VCore.scala 171:41]
+  wire  _convready_T_2 = vconv_io_in_ready & vdec_io_cmdq_1_conv; // @[VCore.scala 172:41]
+  wire  _convready_T_3 = vconv_io_in_ready & vdec_io_cmdq_0_conv; // @[VCore.scala 173:41]
   wire [3:0] convready = {_convready_T,_convready_T_1,_convready_T_2,_convready_T_3}; // @[Cat.scala 31:58]
-  wire  _ldstvalid_T = vdec_io_out_3_valid & vdec_io_cmdq_3_ldst; // @[VCore.scala 190:44]
-  wire  _ldstvalid_T_1 = vdec_io_out_2_valid & vdec_io_cmdq_2_ldst; // @[VCore.scala 191:44]
-  wire  _ldstvalid_T_2 = vdec_io_out_1_valid & vdec_io_cmdq_1_ldst; // @[VCore.scala 192:44]
-  wire  _ldstvalid_T_3 = vdec_io_out_0_valid & vdec_io_cmdq_0_ldst; // @[VCore.scala 193:44]
+  wire  _ldstvalid_T = vdec_io_out_3_valid & vdec_io_cmdq_3_ldst; // @[VCore.scala 188:44]
+  wire  _ldstvalid_T_1 = vdec_io_out_2_valid & vdec_io_cmdq_2_ldst; // @[VCore.scala 189:44]
+  wire  _ldstvalid_T_2 = vdec_io_out_1_valid & vdec_io_cmdq_1_ldst; // @[VCore.scala 190:44]
+  wire  _ldstvalid_T_3 = vdec_io_out_0_valid & vdec_io_cmdq_0_ldst; // @[VCore.scala 191:44]
   wire [3:0] ldstvalid = {_ldstvalid_T,_ldstvalid_T_1,_ldstvalid_T_2,_ldstvalid_T_3}; // @[Cat.scala 31:58]
-  wire  _ldstready_T = vldst_io_in_ready & vdec_io_cmdq_3_ldst; // @[VCore.scala 195:41]
-  wire  _ldstready_T_1 = vldst_io_in_ready & vdec_io_cmdq_2_ldst; // @[VCore.scala 196:41]
-  wire  _ldstready_T_2 = vldst_io_in_ready & vdec_io_cmdq_1_ldst; // @[VCore.scala 197:41]
-  wire  _ldstready_T_3 = vldst_io_in_ready & vdec_io_cmdq_0_ldst; // @[VCore.scala 198:41]
+  wire  _ldstready_T = vldst_io_in_ready & vdec_io_cmdq_3_ldst; // @[VCore.scala 193:41]
+  wire  _ldstready_T_1 = vldst_io_in_ready & vdec_io_cmdq_2_ldst; // @[VCore.scala 194:41]
+  wire  _ldstready_T_2 = vldst_io_in_ready & vdec_io_cmdq_1_ldst; // @[VCore.scala 195:41]
+  wire  _ldstready_T_3 = vldst_io_in_ready & vdec_io_cmdq_0_ldst; // @[VCore.scala 196:41]
   wire [3:0] ldstready = {_ldstready_T,_ldstready_T_1,_ldstready_T_2,_ldstready_T_3}; // @[Cat.scala 31:58]
-  wire  _ldvalid_T = vdec_io_cmdq_3_ld & vdec_io_out_3_valid; // @[VCore.scala 220:37]
-  wire  _ldvalid_T_1 = vdec_io_cmdq_2_ld & vdec_io_out_2_valid; // @[VCore.scala 221:37]
-  wire  _ldvalid_T_2 = vdec_io_cmdq_1_ld & vdec_io_out_1_valid; // @[VCore.scala 222:37]
-  wire  _ldvalid_T_3 = vdec_io_cmdq_0_ld & vdec_io_out_0_valid; // @[VCore.scala 223:37]
+  wire  _ldvalid_T = vdec_io_cmdq_3_ld & vdec_io_out_3_valid; // @[VCore.scala 218:37]
+  wire  _ldvalid_T_1 = vdec_io_cmdq_2_ld & vdec_io_out_2_valid; // @[VCore.scala 219:37]
+  wire  _ldvalid_T_2 = vdec_io_cmdq_1_ld & vdec_io_out_1_valid; // @[VCore.scala 220:37]
+  wire  _ldvalid_T_3 = vdec_io_cmdq_0_ld & vdec_io_out_0_valid; // @[VCore.scala 221:37]
   wire [3:0] ldvalid = {_ldvalid_T,_ldvalid_T_1,_ldvalid_T_2,_ldvalid_T_3}; // @[Cat.scala 31:58]
-  wire  _ldready_T = vdec_io_cmdq_3_ld & vld_io_in_ready; // @[VCore.scala 225:37]
-  wire  _ldready_T_1 = vdec_io_cmdq_2_ld & vld_io_in_ready; // @[VCore.scala 226:37]
-  wire  _ldready_T_2 = vdec_io_cmdq_1_ld & vld_io_in_ready; // @[VCore.scala 227:37]
-  wire  _ldready_T_3 = vdec_io_cmdq_0_ld & vld_io_in_ready; // @[VCore.scala 228:37]
+  wire  _ldready_T = vdec_io_cmdq_3_ld & vld_io_in_ready; // @[VCore.scala 223:37]
+  wire  _ldready_T_1 = vdec_io_cmdq_2_ld & vld_io_in_ready; // @[VCore.scala 224:37]
+  wire  _ldready_T_2 = vdec_io_cmdq_1_ld & vld_io_in_ready; // @[VCore.scala 225:37]
+  wire  _ldready_T_3 = vdec_io_cmdq_0_ld & vld_io_in_ready; // @[VCore.scala 226:37]
   wire [3:0] ldready = {_ldready_T,_ldready_T_1,_ldready_T_2,_ldready_T_3}; // @[Cat.scala 31:58]
-  wire  _stvalid_T = vdec_io_out_3_valid & vdec_io_cmdq_3_st; // @[VCore.scala 244:39]
-  wire  _stvalid_T_1 = vdec_io_out_2_valid & vdec_io_cmdq_2_st; // @[VCore.scala 245:39]
-  wire  _stvalid_T_2 = vdec_io_out_1_valid & vdec_io_cmdq_1_st; // @[VCore.scala 246:39]
-  wire  _stvalid_T_3 = vdec_io_out_0_valid & vdec_io_cmdq_0_st; // @[VCore.scala 247:39]
+  wire  _stvalid_T = vdec_io_out_3_valid & vdec_io_cmdq_3_st; // @[VCore.scala 242:39]
+  wire  _stvalid_T_1 = vdec_io_out_2_valid & vdec_io_cmdq_2_st; // @[VCore.scala 243:39]
+  wire  _stvalid_T_2 = vdec_io_out_1_valid & vdec_io_cmdq_1_st; // @[VCore.scala 244:39]
+  wire  _stvalid_T_3 = vdec_io_out_0_valid & vdec_io_cmdq_0_st; // @[VCore.scala 245:39]
   wire [3:0] stvalid = {_stvalid_T,_stvalid_T_1,_stvalid_T_2,_stvalid_T_3}; // @[Cat.scala 31:58]
-  wire  _stready_T = vst_io_in_ready & vdec_io_cmdq_3_st; // @[VCore.scala 249:34]
-  wire  _stready_T_1 = vst_io_in_ready & vdec_io_cmdq_2_st; // @[VCore.scala 250:34]
-  wire  _stready_T_2 = vst_io_in_ready & vdec_io_cmdq_1_st; // @[VCore.scala 251:34]
-  wire  _stready_T_3 = vst_io_in_ready & vdec_io_cmdq_0_st; // @[VCore.scala 252:34]
+  wire  _stready_T = vst_io_in_ready & vdec_io_cmdq_3_st; // @[VCore.scala 247:34]
+  wire  _stready_T_1 = vst_io_in_ready & vdec_io_cmdq_2_st; // @[VCore.scala 248:34]
+  wire  _stready_T_2 = vst_io_in_ready & vdec_io_cmdq_1_st; // @[VCore.scala 249:34]
+  wire  _stready_T_3 = vst_io_in_ready & vdec_io_cmdq_0_st; // @[VCore.scala 250:34]
   wire [3:0] stready = {_stready_T,_stready_T_1,_stready_T_2,_stready_T_3}; // @[Cat.scala 31:58]
-  wire  _vdec_io_out_0_ready_T_6 = aluready[0] | convready[0] | ldstready[0] | ldready[0]; // @[VCore.scala 289:73]
-  wire  _vdec_io_out_1_ready_T_6 = aluready[1] | convready[1] | ldstready[1] | ldready[1]; // @[VCore.scala 289:73]
-  wire  _vdec_io_out_2_ready_T_6 = aluready[2] | convready[2] | ldstready[2] | ldready[2]; // @[VCore.scala 289:73]
-  wire  _vdec_io_out_3_ready_T_6 = aluready[3] | convready[3] | ldstready[3] | ldready[3]; // @[VCore.scala 289:73]
-  wire  _io_score_mactive_T_1 = vinst_io_nempty | vdec_io_nempty | vld_io_nempty; // @[VCore.scala 295:57]
+  wire  _vdec_io_out_0_ready_T_6 = aluready[0] | convready[0] | ldstready[0] | ldready[0]; // @[VCore.scala 287:73]
+  wire  _vdec_io_out_1_ready_T_6 = aluready[1] | convready[1] | ldstready[1] | ldready[1]; // @[VCore.scala 287:73]
+  wire  _vdec_io_out_2_ready_T_6 = aluready[2] | convready[2] | ldstready[2] | ldready[2]; // @[VCore.scala 287:73]
+  wire  _vdec_io_out_3_ready_T_6 = aluready[3] | convready[3] | ldstready[3] | ldready[3]; // @[VCore.scala 287:73]
+  wire  _io_score_mactive_T_1 = vinst_io_nempty | vdec_io_nempty | vld_io_nempty; // @[VCore.scala 293:57]
   VInst vinst ( // @[VInst.scala 9:18]
     .clock(vinst_clock),
     .reset(vinst_reset),
@@ -122121,10 +112555,6 @@
     .io_rd_3_valid(vinst_io_rd_3_valid),
     .io_rd_3_addr(vinst_io_rd_3_addr),
     .io_rd_3_data(vinst_io_rd_3_data),
-    .io_fs_0_data(vinst_io_fs_0_data),
-    .io_fs_1_data(vinst_io_fs_1_data),
-    .io_fs_2_data(vinst_io_fs_2_data),
-    .io_fs_3_data(vinst_io_fs_3_data),
     .io_out_valid(vinst_io_out_valid),
     .io_out_ready(vinst_io_out_ready),
     .io_out_stall(vinst_io_out_stall),
@@ -122327,7 +112757,7 @@
     .io_undef(vdec_io_undef),
     .io_nempty(vdec_io_nempty)
   );
-  VAlu valu ( // @[VAlu.scala 29:18]
+  VAlu valu ( // @[VAlu.scala 9:18]
     .clock(valu_clock),
     .reset(valu_reset),
     .io_in_ready(valu_io_in_ready),
@@ -122810,477 +113240,473 @@
     .io_vrfsb_set_bits(vrf_io_vrfsb_set_bits),
     .io_vrfsb_data(vrf_io_vrfsb_data)
   );
-  assign io_score_vinst_0_ready = vinst_io_in_0_ready; // @[VCore.scala 66:15]
-  assign io_score_vinst_1_ready = vinst_io_in_1_ready; // @[VCore.scala 66:15]
-  assign io_score_vinst_2_ready = vinst_io_in_2_ready; // @[VCore.scala 66:15]
-  assign io_score_vinst_3_ready = vinst_io_in_3_ready; // @[VCore.scala 66:15]
-  assign io_score_rd_0_valid = vinst_io_rd_0_valid; // @[VCore.scala 68:15]
-  assign io_score_rd_0_addr = vinst_io_rd_0_addr; // @[VCore.scala 68:15]
-  assign io_score_rd_0_data = vinst_io_rd_0_data; // @[VCore.scala 68:15]
-  assign io_score_rd_1_valid = vinst_io_rd_1_valid; // @[VCore.scala 68:15]
-  assign io_score_rd_1_addr = vinst_io_rd_1_addr; // @[VCore.scala 68:15]
-  assign io_score_rd_1_data = vinst_io_rd_1_data; // @[VCore.scala 68:15]
-  assign io_score_rd_2_valid = vinst_io_rd_2_valid; // @[VCore.scala 68:15]
-  assign io_score_rd_2_addr = vinst_io_rd_2_addr; // @[VCore.scala 68:15]
-  assign io_score_rd_2_data = vinst_io_rd_2_data; // @[VCore.scala 68:15]
-  assign io_score_rd_3_valid = vinst_io_rd_3_valid; // @[VCore.scala 68:15]
-  assign io_score_rd_3_addr = vinst_io_rd_3_addr; // @[VCore.scala 68:15]
-  assign io_score_rd_3_data = vinst_io_rd_3_data; // @[VCore.scala 68:15]
-  assign io_score_mactive = _io_score_mactive_T_1 | vst_io_nempty; // @[VCore.scala 296:37]
-  assign io_score_undef = vdec_io_undef; // @[VCore.scala 90:18]
-  assign io_dbus_valid = vldst_io_dbus_valid; // @[VCore.scala 212:11]
-  assign io_dbus_write = vldst_io_dbus_write; // @[VCore.scala 212:11]
-  assign io_dbus_addr = vldst_io_dbus_addr; // @[VCore.scala 212:11]
-  assign io_dbus_adrx = vldst_io_dbus_adrx; // @[VCore.scala 212:11]
-  assign io_dbus_size = vldst_io_dbus_size; // @[VCore.scala 212:11]
-  assign io_dbus_wdata = vldst_io_dbus_wdata; // @[VCore.scala 212:11]
-  assign io_dbus_wmask = vldst_io_dbus_wmask; // @[VCore.scala 212:11]
-  assign io_last = vldst_io_last; // @[VCore.scala 213:11]
-  assign io_ld_addr_valid = vld_io_axi_addr_valid; // @[VCore.scala 237:9]
-  assign io_ld_addr_bits_addr = vld_io_axi_addr_bits_addr; // @[VCore.scala 237:9]
-  assign io_ld_addr_bits_id = vld_io_axi_addr_bits_id; // @[VCore.scala 237:9]
-  assign io_st_addr_valid = vst_io_axi_addr_valid; // @[VCore.scala 261:9]
-  assign io_st_addr_bits_addr = vst_io_axi_addr_bits_addr; // @[VCore.scala 261:9]
-  assign io_st_addr_bits_id = vst_io_axi_addr_bits_id; // @[VCore.scala 261:9]
-  assign io_st_data_valid = vst_io_axi_data_valid; // @[VCore.scala 261:9]
-  assign io_st_data_bits_data = vst_io_axi_data_bits_data; // @[VCore.scala 261:9]
-  assign io_st_data_bits_strb = vst_io_axi_data_bits_strb; // @[VCore.scala 261:9]
+  assign io_score_vinst_0_ready = vinst_io_in_0_ready; // @[VCore.scala 65:15]
+  assign io_score_vinst_1_ready = vinst_io_in_1_ready; // @[VCore.scala 65:15]
+  assign io_score_vinst_2_ready = vinst_io_in_2_ready; // @[VCore.scala 65:15]
+  assign io_score_vinst_3_ready = vinst_io_in_3_ready; // @[VCore.scala 65:15]
+  assign io_score_rd_0_valid = vinst_io_rd_0_valid; // @[VCore.scala 67:15]
+  assign io_score_rd_0_addr = vinst_io_rd_0_addr; // @[VCore.scala 67:15]
+  assign io_score_rd_0_data = vinst_io_rd_0_data; // @[VCore.scala 67:15]
+  assign io_score_rd_1_valid = vinst_io_rd_1_valid; // @[VCore.scala 67:15]
+  assign io_score_rd_1_addr = vinst_io_rd_1_addr; // @[VCore.scala 67:15]
+  assign io_score_rd_1_data = vinst_io_rd_1_data; // @[VCore.scala 67:15]
+  assign io_score_rd_2_valid = vinst_io_rd_2_valid; // @[VCore.scala 67:15]
+  assign io_score_rd_2_addr = vinst_io_rd_2_addr; // @[VCore.scala 67:15]
+  assign io_score_rd_2_data = vinst_io_rd_2_data; // @[VCore.scala 67:15]
+  assign io_score_rd_3_valid = vinst_io_rd_3_valid; // @[VCore.scala 67:15]
+  assign io_score_rd_3_addr = vinst_io_rd_3_addr; // @[VCore.scala 67:15]
+  assign io_score_rd_3_data = vinst_io_rd_3_data; // @[VCore.scala 67:15]
+  assign io_score_mactive = _io_score_mactive_T_1 | vst_io_nempty; // @[VCore.scala 294:37]
+  assign io_score_undef = vdec_io_undef; // @[VCore.scala 88:18]
+  assign io_dbus_valid = vldst_io_dbus_valid; // @[VCore.scala 210:11]
+  assign io_dbus_write = vldst_io_dbus_write; // @[VCore.scala 210:11]
+  assign io_dbus_addr = vldst_io_dbus_addr; // @[VCore.scala 210:11]
+  assign io_dbus_adrx = vldst_io_dbus_adrx; // @[VCore.scala 210:11]
+  assign io_dbus_size = vldst_io_dbus_size; // @[VCore.scala 210:11]
+  assign io_dbus_wdata = vldst_io_dbus_wdata; // @[VCore.scala 210:11]
+  assign io_dbus_wmask = vldst_io_dbus_wmask; // @[VCore.scala 210:11]
+  assign io_last = vldst_io_last; // @[VCore.scala 211:11]
+  assign io_ld_addr_valid = vld_io_axi_addr_valid; // @[VCore.scala 235:9]
+  assign io_ld_addr_bits_addr = vld_io_axi_addr_bits_addr; // @[VCore.scala 235:9]
+  assign io_ld_addr_bits_id = vld_io_axi_addr_bits_id; // @[VCore.scala 235:9]
+  assign io_st_addr_valid = vst_io_axi_addr_valid; // @[VCore.scala 259:9]
+  assign io_st_addr_bits_addr = vst_io_axi_addr_bits_addr; // @[VCore.scala 259:9]
+  assign io_st_addr_bits_id = vst_io_axi_addr_bits_id; // @[VCore.scala 259:9]
+  assign io_st_data_valid = vst_io_axi_data_valid; // @[VCore.scala 259:9]
+  assign io_st_data_bits_data = vst_io_axi_data_bits_data; // @[VCore.scala 259:9]
+  assign io_st_data_bits_strb = vst_io_axi_data_bits_strb; // @[VCore.scala 259:9]
   assign vinst_clock = clock;
   assign vinst_reset = reset;
-  assign vinst_io_in_0_valid = io_score_vinst_0_valid; // @[VCore.scala 66:15]
-  assign vinst_io_in_0_addr = io_score_vinst_0_addr; // @[VCore.scala 66:15]
-  assign vinst_io_in_0_inst = io_score_vinst_0_inst; // @[VCore.scala 66:15]
-  assign vinst_io_in_0_op = io_score_vinst_0_op; // @[VCore.scala 66:15]
-  assign vinst_io_in_1_valid = io_score_vinst_1_valid; // @[VCore.scala 66:15]
-  assign vinst_io_in_1_addr = io_score_vinst_1_addr; // @[VCore.scala 66:15]
-  assign vinst_io_in_1_inst = io_score_vinst_1_inst; // @[VCore.scala 66:15]
-  assign vinst_io_in_1_op = io_score_vinst_1_op; // @[VCore.scala 66:15]
-  assign vinst_io_in_2_valid = io_score_vinst_2_valid; // @[VCore.scala 66:15]
-  assign vinst_io_in_2_addr = io_score_vinst_2_addr; // @[VCore.scala 66:15]
-  assign vinst_io_in_2_inst = io_score_vinst_2_inst; // @[VCore.scala 66:15]
-  assign vinst_io_in_2_op = io_score_vinst_2_op; // @[VCore.scala 66:15]
-  assign vinst_io_in_3_valid = io_score_vinst_3_valid; // @[VCore.scala 66:15]
-  assign vinst_io_in_3_addr = io_score_vinst_3_addr; // @[VCore.scala 66:15]
-  assign vinst_io_in_3_inst = io_score_vinst_3_inst; // @[VCore.scala 66:15]
-  assign vinst_io_in_3_op = io_score_vinst_3_op; // @[VCore.scala 66:15]
-  assign vinst_io_rs_0_data = io_score_rs_0_data; // @[VCore.scala 67:15]
-  assign vinst_io_rs_1_data = io_score_rs_1_data; // @[VCore.scala 67:15]
-  assign vinst_io_rs_2_data = io_score_rs_2_data; // @[VCore.scala 67:15]
-  assign vinst_io_rs_3_data = io_score_rs_3_data; // @[VCore.scala 67:15]
-  assign vinst_io_rs_4_data = io_score_rs_4_data; // @[VCore.scala 67:15]
-  assign vinst_io_rs_5_data = io_score_rs_5_data; // @[VCore.scala 67:15]
-  assign vinst_io_rs_6_data = io_score_rs_6_data; // @[VCore.scala 67:15]
-  assign vinst_io_rs_7_data = io_score_rs_7_data; // @[VCore.scala 67:15]
-  assign vinst_io_fs_0_data = io_score_fs_0_data; // @[VCore.scala 69:15]
-  assign vinst_io_fs_1_data = io_score_fs_1_data; // @[VCore.scala 69:15]
-  assign vinst_io_fs_2_data = io_score_fs_2_data; // @[VCore.scala 69:15]
-  assign vinst_io_fs_3_data = io_score_fs_3_data; // @[VCore.scala 69:15]
-  assign vinst_io_out_ready = vdec_io_in_ready; // @[VCore.scala 81:22]
-  assign vinst_io_out_stall = vdec_io_stall; // @[VCore.scala 84:22]
+  assign vinst_io_in_0_valid = io_score_vinst_0_valid; // @[VCore.scala 65:15]
+  assign vinst_io_in_0_addr = io_score_vinst_0_addr; // @[VCore.scala 65:15]
+  assign vinst_io_in_0_inst = io_score_vinst_0_inst; // @[VCore.scala 65:15]
+  assign vinst_io_in_0_op = io_score_vinst_0_op; // @[VCore.scala 65:15]
+  assign vinst_io_in_1_valid = io_score_vinst_1_valid; // @[VCore.scala 65:15]
+  assign vinst_io_in_1_addr = io_score_vinst_1_addr; // @[VCore.scala 65:15]
+  assign vinst_io_in_1_inst = io_score_vinst_1_inst; // @[VCore.scala 65:15]
+  assign vinst_io_in_1_op = io_score_vinst_1_op; // @[VCore.scala 65:15]
+  assign vinst_io_in_2_valid = io_score_vinst_2_valid; // @[VCore.scala 65:15]
+  assign vinst_io_in_2_addr = io_score_vinst_2_addr; // @[VCore.scala 65:15]
+  assign vinst_io_in_2_inst = io_score_vinst_2_inst; // @[VCore.scala 65:15]
+  assign vinst_io_in_2_op = io_score_vinst_2_op; // @[VCore.scala 65:15]
+  assign vinst_io_in_3_valid = io_score_vinst_3_valid; // @[VCore.scala 65:15]
+  assign vinst_io_in_3_addr = io_score_vinst_3_addr; // @[VCore.scala 65:15]
+  assign vinst_io_in_3_inst = io_score_vinst_3_inst; // @[VCore.scala 65:15]
+  assign vinst_io_in_3_op = io_score_vinst_3_op; // @[VCore.scala 65:15]
+  assign vinst_io_rs_0_data = io_score_rs_0_data; // @[VCore.scala 66:15]
+  assign vinst_io_rs_1_data = io_score_rs_1_data; // @[VCore.scala 66:15]
+  assign vinst_io_rs_2_data = io_score_rs_2_data; // @[VCore.scala 66:15]
+  assign vinst_io_rs_3_data = io_score_rs_3_data; // @[VCore.scala 66:15]
+  assign vinst_io_rs_4_data = io_score_rs_4_data; // @[VCore.scala 66:15]
+  assign vinst_io_rs_5_data = io_score_rs_5_data; // @[VCore.scala 66:15]
+  assign vinst_io_rs_6_data = io_score_rs_6_data; // @[VCore.scala 66:15]
+  assign vinst_io_rs_7_data = io_score_rs_7_data; // @[VCore.scala 66:15]
+  assign vinst_io_out_ready = vdec_io_in_ready; // @[VCore.scala 79:22]
+  assign vinst_io_out_stall = vdec_io_stall; // @[VCore.scala 82:22]
   assign vdec_clock = clock;
   assign vdec_reset = reset;
-  assign vdec_io_in_valid = vinst_io_out_valid; // @[VCore.scala 80:20]
-  assign vdec_io_in_bits_0_valid = vinst_io_out_lane_0_valid; // @[VCore.scala 87:24]
-  assign vdec_io_in_bits_0_bits_inst = vinst_io_out_lane_0_bits_inst; // @[VCore.scala 87:24]
-  assign vdec_io_in_bits_0_bits_addr = vinst_io_out_lane_0_bits_addr; // @[VCore.scala 87:24]
-  assign vdec_io_in_bits_0_bits_data = vinst_io_out_lane_0_bits_data; // @[VCore.scala 87:24]
-  assign vdec_io_in_bits_1_valid = vinst_io_out_lane_1_valid; // @[VCore.scala 87:24]
-  assign vdec_io_in_bits_1_bits_inst = vinst_io_out_lane_1_bits_inst; // @[VCore.scala 87:24]
-  assign vdec_io_in_bits_1_bits_addr = vinst_io_out_lane_1_bits_addr; // @[VCore.scala 87:24]
-  assign vdec_io_in_bits_1_bits_data = vinst_io_out_lane_1_bits_data; // @[VCore.scala 87:24]
-  assign vdec_io_in_bits_2_valid = vinst_io_out_lane_2_valid; // @[VCore.scala 87:24]
-  assign vdec_io_in_bits_2_bits_inst = vinst_io_out_lane_2_bits_inst; // @[VCore.scala 87:24]
-  assign vdec_io_in_bits_2_bits_addr = vinst_io_out_lane_2_bits_addr; // @[VCore.scala 87:24]
-  assign vdec_io_in_bits_2_bits_data = vinst_io_out_lane_2_bits_data; // @[VCore.scala 87:24]
-  assign vdec_io_in_bits_3_valid = vinst_io_out_lane_3_valid; // @[VCore.scala 87:24]
-  assign vdec_io_in_bits_3_bits_inst = vinst_io_out_lane_3_bits_inst; // @[VCore.scala 87:24]
-  assign vdec_io_in_bits_3_bits_addr = vinst_io_out_lane_3_bits_addr; // @[VCore.scala 87:24]
-  assign vdec_io_in_bits_3_bits_data = vinst_io_out_lane_3_bits_data; // @[VCore.scala 87:24]
-  assign vdec_io_out_0_ready = _vdec_io_out_0_ready_T_6 | stready[0]; // @[VCore.scala 290:40]
-  assign vdec_io_out_1_ready = _vdec_io_out_1_ready_T_6 | stready[1]; // @[VCore.scala 290:40]
-  assign vdec_io_out_2_ready = _vdec_io_out_2_ready_T_6 | stready[2]; // @[VCore.scala 290:40]
-  assign vdec_io_out_3_ready = _vdec_io_out_3_ready_T_6 | stready[3]; // @[VCore.scala 290:40]
-  assign vdec_io_active = _vdec_io_active_T_1 | vst_io_active; // @[VCore.scala 78:72]
-  assign vdec_io_vrfsb_data = vrf_io_vrfsb_data; // @[VCore.scala 76:17]
+  assign vdec_io_in_valid = vinst_io_out_valid; // @[VCore.scala 78:20]
+  assign vdec_io_in_bits_0_valid = vinst_io_out_lane_0_valid; // @[VCore.scala 85:24]
+  assign vdec_io_in_bits_0_bits_inst = vinst_io_out_lane_0_bits_inst; // @[VCore.scala 85:24]
+  assign vdec_io_in_bits_0_bits_addr = vinst_io_out_lane_0_bits_addr; // @[VCore.scala 85:24]
+  assign vdec_io_in_bits_0_bits_data = vinst_io_out_lane_0_bits_data; // @[VCore.scala 85:24]
+  assign vdec_io_in_bits_1_valid = vinst_io_out_lane_1_valid; // @[VCore.scala 85:24]
+  assign vdec_io_in_bits_1_bits_inst = vinst_io_out_lane_1_bits_inst; // @[VCore.scala 85:24]
+  assign vdec_io_in_bits_1_bits_addr = vinst_io_out_lane_1_bits_addr; // @[VCore.scala 85:24]
+  assign vdec_io_in_bits_1_bits_data = vinst_io_out_lane_1_bits_data; // @[VCore.scala 85:24]
+  assign vdec_io_in_bits_2_valid = vinst_io_out_lane_2_valid; // @[VCore.scala 85:24]
+  assign vdec_io_in_bits_2_bits_inst = vinst_io_out_lane_2_bits_inst; // @[VCore.scala 85:24]
+  assign vdec_io_in_bits_2_bits_addr = vinst_io_out_lane_2_bits_addr; // @[VCore.scala 85:24]
+  assign vdec_io_in_bits_2_bits_data = vinst_io_out_lane_2_bits_data; // @[VCore.scala 85:24]
+  assign vdec_io_in_bits_3_valid = vinst_io_out_lane_3_valid; // @[VCore.scala 85:24]
+  assign vdec_io_in_bits_3_bits_inst = vinst_io_out_lane_3_bits_inst; // @[VCore.scala 85:24]
+  assign vdec_io_in_bits_3_bits_addr = vinst_io_out_lane_3_bits_addr; // @[VCore.scala 85:24]
+  assign vdec_io_in_bits_3_bits_data = vinst_io_out_lane_3_bits_data; // @[VCore.scala 85:24]
+  assign vdec_io_out_0_ready = _vdec_io_out_0_ready_T_6 | stready[0]; // @[VCore.scala 288:40]
+  assign vdec_io_out_1_ready = _vdec_io_out_1_ready_T_6 | stready[1]; // @[VCore.scala 288:40]
+  assign vdec_io_out_2_ready = _vdec_io_out_2_ready_T_6 | stready[2]; // @[VCore.scala 288:40]
+  assign vdec_io_out_3_ready = _vdec_io_out_3_ready_T_6 | stready[3]; // @[VCore.scala 288:40]
+  assign vdec_io_active = _vdec_io_active_T_1 | vst_io_active; // @[VCore.scala 76:72]
+  assign vdec_io_vrfsb_data = vrf_io_vrfsb_data; // @[VCore.scala 74:17]
   assign valu_clock = clock;
   assign valu_reset = reset;
-  assign valu_io_in_valid = aluvalid != 4'h0; // @[VCore.scala 132:32]
-  assign valu_io_in_bits_0_valid = aluvalid[0]; // @[VCore.scala 135:41]
-  assign valu_io_in_bits_0_bits_op = vdec_io_out_0_bits_op; // @[VCore.scala 136:29]
-  assign valu_io_in_bits_0_bits_f2 = vdec_io_out_0_bits_f2; // @[VCore.scala 136:29]
-  assign valu_io_in_bits_0_bits_sz = vdec_io_out_0_bits_sz; // @[VCore.scala 136:29]
-  assign valu_io_in_bits_0_bits_m = vdec_io_out_0_bits_m; // @[VCore.scala 136:29]
-  assign valu_io_in_bits_0_bits_vd_addr = vdec_io_out_0_bits_vd_addr; // @[VCore.scala 136:29]
-  assign valu_io_in_bits_0_bits_ve_addr = vdec_io_out_0_bits_ve_addr; // @[VCore.scala 136:29]
-  assign valu_io_in_bits_0_bits_vf_addr = vdec_io_out_0_bits_vf_addr; // @[VCore.scala 136:29]
-  assign valu_io_in_bits_0_bits_vg_addr = vdec_io_out_0_bits_vg_addr; // @[VCore.scala 136:29]
-  assign valu_io_in_bits_0_bits_vs_valid = vdec_io_out_0_bits_vs_valid; // @[VCore.scala 136:29]
-  assign valu_io_in_bits_0_bits_vs_addr = vdec_io_out_0_bits_vs_addr; // @[VCore.scala 136:29]
-  assign valu_io_in_bits_0_bits_vs_tag = vdec_io_out_0_bits_vs_tag; // @[VCore.scala 136:29]
-  assign valu_io_in_bits_0_bits_vt_valid = vdec_io_out_0_bits_vt_valid; // @[VCore.scala 136:29]
-  assign valu_io_in_bits_0_bits_vt_addr = vdec_io_out_0_bits_vt_addr; // @[VCore.scala 136:29]
-  assign valu_io_in_bits_0_bits_vt_tag = vdec_io_out_0_bits_vt_tag; // @[VCore.scala 136:29]
-  assign valu_io_in_bits_0_bits_vu_valid = vdec_io_out_0_bits_vu_valid; // @[VCore.scala 136:29]
-  assign valu_io_in_bits_0_bits_vu_addr = vdec_io_out_0_bits_vu_addr; // @[VCore.scala 136:29]
-  assign valu_io_in_bits_0_bits_vu_tag = vdec_io_out_0_bits_vu_tag; // @[VCore.scala 136:29]
-  assign valu_io_in_bits_0_bits_vx_valid = vdec_io_out_0_bits_vx_valid; // @[VCore.scala 136:29]
-  assign valu_io_in_bits_0_bits_vx_addr = vdec_io_out_0_bits_vx_addr; // @[VCore.scala 136:29]
-  assign valu_io_in_bits_0_bits_vx_tag = vdec_io_out_0_bits_vx_tag; // @[VCore.scala 136:29]
-  assign valu_io_in_bits_0_bits_vy_valid = vdec_io_out_0_bits_vy_valid; // @[VCore.scala 136:29]
-  assign valu_io_in_bits_0_bits_vy_addr = vdec_io_out_0_bits_vy_addr; // @[VCore.scala 136:29]
-  assign valu_io_in_bits_0_bits_vy_tag = vdec_io_out_0_bits_vy_tag; // @[VCore.scala 136:29]
-  assign valu_io_in_bits_0_bits_vz_valid = vdec_io_out_0_bits_vz_valid; // @[VCore.scala 136:29]
-  assign valu_io_in_bits_0_bits_vz_addr = vdec_io_out_0_bits_vz_addr; // @[VCore.scala 136:29]
-  assign valu_io_in_bits_0_bits_vz_tag = vdec_io_out_0_bits_vz_tag; // @[VCore.scala 136:29]
-  assign valu_io_in_bits_0_bits_sv_valid = vdec_io_out_0_bits_sv_valid; // @[VCore.scala 136:29]
-  assign valu_io_in_bits_0_bits_sv_data = vdec_io_out_0_bits_sv_data; // @[VCore.scala 136:29]
-  assign valu_io_in_bits_0_bits_cmdsync = vdec_io_out_0_bits_cmdsync; // @[VCore.scala 136:29]
-  assign valu_io_in_bits_1_valid = aluvalid[1]; // @[VCore.scala 135:41]
-  assign valu_io_in_bits_1_bits_op = vdec_io_out_1_bits_op; // @[VCore.scala 136:29]
-  assign valu_io_in_bits_1_bits_f2 = vdec_io_out_1_bits_f2; // @[VCore.scala 136:29]
-  assign valu_io_in_bits_1_bits_sz = vdec_io_out_1_bits_sz; // @[VCore.scala 136:29]
-  assign valu_io_in_bits_1_bits_m = vdec_io_out_1_bits_m; // @[VCore.scala 136:29]
-  assign valu_io_in_bits_1_bits_vd_addr = vdec_io_out_1_bits_vd_addr; // @[VCore.scala 136:29]
-  assign valu_io_in_bits_1_bits_ve_addr = vdec_io_out_1_bits_ve_addr; // @[VCore.scala 136:29]
-  assign valu_io_in_bits_1_bits_vf_addr = vdec_io_out_1_bits_vf_addr; // @[VCore.scala 136:29]
-  assign valu_io_in_bits_1_bits_vg_addr = vdec_io_out_1_bits_vg_addr; // @[VCore.scala 136:29]
-  assign valu_io_in_bits_1_bits_vs_valid = vdec_io_out_1_bits_vs_valid; // @[VCore.scala 136:29]
-  assign valu_io_in_bits_1_bits_vs_addr = vdec_io_out_1_bits_vs_addr; // @[VCore.scala 136:29]
-  assign valu_io_in_bits_1_bits_vs_tag = vdec_io_out_1_bits_vs_tag; // @[VCore.scala 136:29]
-  assign valu_io_in_bits_1_bits_vt_valid = vdec_io_out_1_bits_vt_valid; // @[VCore.scala 136:29]
-  assign valu_io_in_bits_1_bits_vt_addr = vdec_io_out_1_bits_vt_addr; // @[VCore.scala 136:29]
-  assign valu_io_in_bits_1_bits_vt_tag = vdec_io_out_1_bits_vt_tag; // @[VCore.scala 136:29]
-  assign valu_io_in_bits_1_bits_vu_valid = vdec_io_out_1_bits_vu_valid; // @[VCore.scala 136:29]
-  assign valu_io_in_bits_1_bits_vu_addr = vdec_io_out_1_bits_vu_addr; // @[VCore.scala 136:29]
-  assign valu_io_in_bits_1_bits_vu_tag = vdec_io_out_1_bits_vu_tag; // @[VCore.scala 136:29]
-  assign valu_io_in_bits_1_bits_vx_valid = vdec_io_out_1_bits_vx_valid; // @[VCore.scala 136:29]
-  assign valu_io_in_bits_1_bits_vx_addr = vdec_io_out_1_bits_vx_addr; // @[VCore.scala 136:29]
-  assign valu_io_in_bits_1_bits_vx_tag = vdec_io_out_1_bits_vx_tag; // @[VCore.scala 136:29]
-  assign valu_io_in_bits_1_bits_vy_valid = vdec_io_out_1_bits_vy_valid; // @[VCore.scala 136:29]
-  assign valu_io_in_bits_1_bits_vy_addr = vdec_io_out_1_bits_vy_addr; // @[VCore.scala 136:29]
-  assign valu_io_in_bits_1_bits_vy_tag = vdec_io_out_1_bits_vy_tag; // @[VCore.scala 136:29]
-  assign valu_io_in_bits_1_bits_vz_valid = vdec_io_out_1_bits_vz_valid; // @[VCore.scala 136:29]
-  assign valu_io_in_bits_1_bits_vz_addr = vdec_io_out_1_bits_vz_addr; // @[VCore.scala 136:29]
-  assign valu_io_in_bits_1_bits_vz_tag = vdec_io_out_1_bits_vz_tag; // @[VCore.scala 136:29]
-  assign valu_io_in_bits_1_bits_sv_valid = vdec_io_out_1_bits_sv_valid; // @[VCore.scala 136:29]
-  assign valu_io_in_bits_1_bits_sv_data = vdec_io_out_1_bits_sv_data; // @[VCore.scala 136:29]
-  assign valu_io_in_bits_1_bits_cmdsync = vdec_io_out_1_bits_cmdsync; // @[VCore.scala 136:29]
-  assign valu_io_in_bits_2_valid = aluvalid[2]; // @[VCore.scala 135:41]
-  assign valu_io_in_bits_2_bits_op = vdec_io_out_2_bits_op; // @[VCore.scala 136:29]
-  assign valu_io_in_bits_2_bits_f2 = vdec_io_out_2_bits_f2; // @[VCore.scala 136:29]
-  assign valu_io_in_bits_2_bits_sz = vdec_io_out_2_bits_sz; // @[VCore.scala 136:29]
-  assign valu_io_in_bits_2_bits_m = vdec_io_out_2_bits_m; // @[VCore.scala 136:29]
-  assign valu_io_in_bits_2_bits_vd_addr = vdec_io_out_2_bits_vd_addr; // @[VCore.scala 136:29]
-  assign valu_io_in_bits_2_bits_ve_addr = vdec_io_out_2_bits_ve_addr; // @[VCore.scala 136:29]
-  assign valu_io_in_bits_2_bits_vf_addr = vdec_io_out_2_bits_vf_addr; // @[VCore.scala 136:29]
-  assign valu_io_in_bits_2_bits_vg_addr = vdec_io_out_2_bits_vg_addr; // @[VCore.scala 136:29]
-  assign valu_io_in_bits_2_bits_vs_valid = vdec_io_out_2_bits_vs_valid; // @[VCore.scala 136:29]
-  assign valu_io_in_bits_2_bits_vs_addr = vdec_io_out_2_bits_vs_addr; // @[VCore.scala 136:29]
-  assign valu_io_in_bits_2_bits_vs_tag = vdec_io_out_2_bits_vs_tag; // @[VCore.scala 136:29]
-  assign valu_io_in_bits_2_bits_vt_valid = vdec_io_out_2_bits_vt_valid; // @[VCore.scala 136:29]
-  assign valu_io_in_bits_2_bits_vt_addr = vdec_io_out_2_bits_vt_addr; // @[VCore.scala 136:29]
-  assign valu_io_in_bits_2_bits_vt_tag = vdec_io_out_2_bits_vt_tag; // @[VCore.scala 136:29]
-  assign valu_io_in_bits_2_bits_vu_valid = vdec_io_out_2_bits_vu_valid; // @[VCore.scala 136:29]
-  assign valu_io_in_bits_2_bits_vu_addr = vdec_io_out_2_bits_vu_addr; // @[VCore.scala 136:29]
-  assign valu_io_in_bits_2_bits_vu_tag = vdec_io_out_2_bits_vu_tag; // @[VCore.scala 136:29]
-  assign valu_io_in_bits_2_bits_vx_valid = vdec_io_out_2_bits_vx_valid; // @[VCore.scala 136:29]
-  assign valu_io_in_bits_2_bits_vx_addr = vdec_io_out_2_bits_vx_addr; // @[VCore.scala 136:29]
-  assign valu_io_in_bits_2_bits_vx_tag = vdec_io_out_2_bits_vx_tag; // @[VCore.scala 136:29]
-  assign valu_io_in_bits_2_bits_vy_valid = vdec_io_out_2_bits_vy_valid; // @[VCore.scala 136:29]
-  assign valu_io_in_bits_2_bits_vy_addr = vdec_io_out_2_bits_vy_addr; // @[VCore.scala 136:29]
-  assign valu_io_in_bits_2_bits_vy_tag = vdec_io_out_2_bits_vy_tag; // @[VCore.scala 136:29]
-  assign valu_io_in_bits_2_bits_vz_valid = vdec_io_out_2_bits_vz_valid; // @[VCore.scala 136:29]
-  assign valu_io_in_bits_2_bits_vz_addr = vdec_io_out_2_bits_vz_addr; // @[VCore.scala 136:29]
-  assign valu_io_in_bits_2_bits_vz_tag = vdec_io_out_2_bits_vz_tag; // @[VCore.scala 136:29]
-  assign valu_io_in_bits_2_bits_sv_valid = vdec_io_out_2_bits_sv_valid; // @[VCore.scala 136:29]
-  assign valu_io_in_bits_2_bits_sv_data = vdec_io_out_2_bits_sv_data; // @[VCore.scala 136:29]
-  assign valu_io_in_bits_2_bits_cmdsync = vdec_io_out_2_bits_cmdsync; // @[VCore.scala 136:29]
-  assign valu_io_in_bits_3_valid = aluvalid[3]; // @[VCore.scala 135:41]
-  assign valu_io_in_bits_3_bits_op = vdec_io_out_3_bits_op; // @[VCore.scala 136:29]
-  assign valu_io_in_bits_3_bits_f2 = vdec_io_out_3_bits_f2; // @[VCore.scala 136:29]
-  assign valu_io_in_bits_3_bits_sz = vdec_io_out_3_bits_sz; // @[VCore.scala 136:29]
-  assign valu_io_in_bits_3_bits_m = vdec_io_out_3_bits_m; // @[VCore.scala 136:29]
-  assign valu_io_in_bits_3_bits_vd_addr = vdec_io_out_3_bits_vd_addr; // @[VCore.scala 136:29]
-  assign valu_io_in_bits_3_bits_ve_addr = vdec_io_out_3_bits_ve_addr; // @[VCore.scala 136:29]
-  assign valu_io_in_bits_3_bits_vf_addr = vdec_io_out_3_bits_vf_addr; // @[VCore.scala 136:29]
-  assign valu_io_in_bits_3_bits_vg_addr = vdec_io_out_3_bits_vg_addr; // @[VCore.scala 136:29]
-  assign valu_io_in_bits_3_bits_vs_valid = vdec_io_out_3_bits_vs_valid; // @[VCore.scala 136:29]
-  assign valu_io_in_bits_3_bits_vs_addr = vdec_io_out_3_bits_vs_addr; // @[VCore.scala 136:29]
-  assign valu_io_in_bits_3_bits_vs_tag = vdec_io_out_3_bits_vs_tag; // @[VCore.scala 136:29]
-  assign valu_io_in_bits_3_bits_vt_valid = vdec_io_out_3_bits_vt_valid; // @[VCore.scala 136:29]
-  assign valu_io_in_bits_3_bits_vt_addr = vdec_io_out_3_bits_vt_addr; // @[VCore.scala 136:29]
-  assign valu_io_in_bits_3_bits_vt_tag = vdec_io_out_3_bits_vt_tag; // @[VCore.scala 136:29]
-  assign valu_io_in_bits_3_bits_vu_valid = vdec_io_out_3_bits_vu_valid; // @[VCore.scala 136:29]
-  assign valu_io_in_bits_3_bits_vu_addr = vdec_io_out_3_bits_vu_addr; // @[VCore.scala 136:29]
-  assign valu_io_in_bits_3_bits_vu_tag = vdec_io_out_3_bits_vu_tag; // @[VCore.scala 136:29]
-  assign valu_io_in_bits_3_bits_vx_valid = vdec_io_out_3_bits_vx_valid; // @[VCore.scala 136:29]
-  assign valu_io_in_bits_3_bits_vx_addr = vdec_io_out_3_bits_vx_addr; // @[VCore.scala 136:29]
-  assign valu_io_in_bits_3_bits_vx_tag = vdec_io_out_3_bits_vx_tag; // @[VCore.scala 136:29]
-  assign valu_io_in_bits_3_bits_vy_valid = vdec_io_out_3_bits_vy_valid; // @[VCore.scala 136:29]
-  assign valu_io_in_bits_3_bits_vy_addr = vdec_io_out_3_bits_vy_addr; // @[VCore.scala 136:29]
-  assign valu_io_in_bits_3_bits_vy_tag = vdec_io_out_3_bits_vy_tag; // @[VCore.scala 136:29]
-  assign valu_io_in_bits_3_bits_vz_valid = vdec_io_out_3_bits_vz_valid; // @[VCore.scala 136:29]
-  assign valu_io_in_bits_3_bits_vz_addr = vdec_io_out_3_bits_vz_addr; // @[VCore.scala 136:29]
-  assign valu_io_in_bits_3_bits_vz_tag = vdec_io_out_3_bits_vz_tag; // @[VCore.scala 136:29]
-  assign valu_io_in_bits_3_bits_sv_valid = vdec_io_out_3_bits_sv_valid; // @[VCore.scala 136:29]
-  assign valu_io_in_bits_3_bits_sv_data = vdec_io_out_3_bits_sv_data; // @[VCore.scala 136:29]
-  assign valu_io_in_bits_3_bits_cmdsync = vdec_io_out_3_bits_cmdsync; // @[VCore.scala 136:29]
-  assign valu_io_vrfsb = vrf_io_vrfsb_data; // @[VCore.scala 163:17]
-  assign valu_io_read_0_data = vrf_io_read_0_data; // @[VCore.scala 146:26]
-  assign valu_io_read_1_data = vrf_io_read_1_data; // @[VCore.scala 146:26]
-  assign valu_io_read_2_data = vrf_io_read_2_data; // @[VCore.scala 146:26]
-  assign valu_io_read_3_data = vrf_io_read_3_data; // @[VCore.scala 146:26]
-  assign valu_io_read_4_data = vrf_io_read_4_data; // @[VCore.scala 146:26]
-  assign valu_io_read_5_data = vrf_io_read_5_data; // @[VCore.scala 146:26]
+  assign valu_io_in_valid = aluvalid != 4'h0; // @[VCore.scala 130:32]
+  assign valu_io_in_bits_0_valid = aluvalid[0]; // @[VCore.scala 133:41]
+  assign valu_io_in_bits_0_bits_op = vdec_io_out_0_bits_op; // @[VCore.scala 134:29]
+  assign valu_io_in_bits_0_bits_f2 = vdec_io_out_0_bits_f2; // @[VCore.scala 134:29]
+  assign valu_io_in_bits_0_bits_sz = vdec_io_out_0_bits_sz; // @[VCore.scala 134:29]
+  assign valu_io_in_bits_0_bits_m = vdec_io_out_0_bits_m; // @[VCore.scala 134:29]
+  assign valu_io_in_bits_0_bits_vd_addr = vdec_io_out_0_bits_vd_addr; // @[VCore.scala 134:29]
+  assign valu_io_in_bits_0_bits_ve_addr = vdec_io_out_0_bits_ve_addr; // @[VCore.scala 134:29]
+  assign valu_io_in_bits_0_bits_vf_addr = vdec_io_out_0_bits_vf_addr; // @[VCore.scala 134:29]
+  assign valu_io_in_bits_0_bits_vg_addr = vdec_io_out_0_bits_vg_addr; // @[VCore.scala 134:29]
+  assign valu_io_in_bits_0_bits_vs_valid = vdec_io_out_0_bits_vs_valid; // @[VCore.scala 134:29]
+  assign valu_io_in_bits_0_bits_vs_addr = vdec_io_out_0_bits_vs_addr; // @[VCore.scala 134:29]
+  assign valu_io_in_bits_0_bits_vs_tag = vdec_io_out_0_bits_vs_tag; // @[VCore.scala 134:29]
+  assign valu_io_in_bits_0_bits_vt_valid = vdec_io_out_0_bits_vt_valid; // @[VCore.scala 134:29]
+  assign valu_io_in_bits_0_bits_vt_addr = vdec_io_out_0_bits_vt_addr; // @[VCore.scala 134:29]
+  assign valu_io_in_bits_0_bits_vt_tag = vdec_io_out_0_bits_vt_tag; // @[VCore.scala 134:29]
+  assign valu_io_in_bits_0_bits_vu_valid = vdec_io_out_0_bits_vu_valid; // @[VCore.scala 134:29]
+  assign valu_io_in_bits_0_bits_vu_addr = vdec_io_out_0_bits_vu_addr; // @[VCore.scala 134:29]
+  assign valu_io_in_bits_0_bits_vu_tag = vdec_io_out_0_bits_vu_tag; // @[VCore.scala 134:29]
+  assign valu_io_in_bits_0_bits_vx_valid = vdec_io_out_0_bits_vx_valid; // @[VCore.scala 134:29]
+  assign valu_io_in_bits_0_bits_vx_addr = vdec_io_out_0_bits_vx_addr; // @[VCore.scala 134:29]
+  assign valu_io_in_bits_0_bits_vx_tag = vdec_io_out_0_bits_vx_tag; // @[VCore.scala 134:29]
+  assign valu_io_in_bits_0_bits_vy_valid = vdec_io_out_0_bits_vy_valid; // @[VCore.scala 134:29]
+  assign valu_io_in_bits_0_bits_vy_addr = vdec_io_out_0_bits_vy_addr; // @[VCore.scala 134:29]
+  assign valu_io_in_bits_0_bits_vy_tag = vdec_io_out_0_bits_vy_tag; // @[VCore.scala 134:29]
+  assign valu_io_in_bits_0_bits_vz_valid = vdec_io_out_0_bits_vz_valid; // @[VCore.scala 134:29]
+  assign valu_io_in_bits_0_bits_vz_addr = vdec_io_out_0_bits_vz_addr; // @[VCore.scala 134:29]
+  assign valu_io_in_bits_0_bits_vz_tag = vdec_io_out_0_bits_vz_tag; // @[VCore.scala 134:29]
+  assign valu_io_in_bits_0_bits_sv_valid = vdec_io_out_0_bits_sv_valid; // @[VCore.scala 134:29]
+  assign valu_io_in_bits_0_bits_sv_data = vdec_io_out_0_bits_sv_data; // @[VCore.scala 134:29]
+  assign valu_io_in_bits_0_bits_cmdsync = vdec_io_out_0_bits_cmdsync; // @[VCore.scala 134:29]
+  assign valu_io_in_bits_1_valid = aluvalid[1]; // @[VCore.scala 133:41]
+  assign valu_io_in_bits_1_bits_op = vdec_io_out_1_bits_op; // @[VCore.scala 134:29]
+  assign valu_io_in_bits_1_bits_f2 = vdec_io_out_1_bits_f2; // @[VCore.scala 134:29]
+  assign valu_io_in_bits_1_bits_sz = vdec_io_out_1_bits_sz; // @[VCore.scala 134:29]
+  assign valu_io_in_bits_1_bits_m = vdec_io_out_1_bits_m; // @[VCore.scala 134:29]
+  assign valu_io_in_bits_1_bits_vd_addr = vdec_io_out_1_bits_vd_addr; // @[VCore.scala 134:29]
+  assign valu_io_in_bits_1_bits_ve_addr = vdec_io_out_1_bits_ve_addr; // @[VCore.scala 134:29]
+  assign valu_io_in_bits_1_bits_vf_addr = vdec_io_out_1_bits_vf_addr; // @[VCore.scala 134:29]
+  assign valu_io_in_bits_1_bits_vg_addr = vdec_io_out_1_bits_vg_addr; // @[VCore.scala 134:29]
+  assign valu_io_in_bits_1_bits_vs_valid = vdec_io_out_1_bits_vs_valid; // @[VCore.scala 134:29]
+  assign valu_io_in_bits_1_bits_vs_addr = vdec_io_out_1_bits_vs_addr; // @[VCore.scala 134:29]
+  assign valu_io_in_bits_1_bits_vs_tag = vdec_io_out_1_bits_vs_tag; // @[VCore.scala 134:29]
+  assign valu_io_in_bits_1_bits_vt_valid = vdec_io_out_1_bits_vt_valid; // @[VCore.scala 134:29]
+  assign valu_io_in_bits_1_bits_vt_addr = vdec_io_out_1_bits_vt_addr; // @[VCore.scala 134:29]
+  assign valu_io_in_bits_1_bits_vt_tag = vdec_io_out_1_bits_vt_tag; // @[VCore.scala 134:29]
+  assign valu_io_in_bits_1_bits_vu_valid = vdec_io_out_1_bits_vu_valid; // @[VCore.scala 134:29]
+  assign valu_io_in_bits_1_bits_vu_addr = vdec_io_out_1_bits_vu_addr; // @[VCore.scala 134:29]
+  assign valu_io_in_bits_1_bits_vu_tag = vdec_io_out_1_bits_vu_tag; // @[VCore.scala 134:29]
+  assign valu_io_in_bits_1_bits_vx_valid = vdec_io_out_1_bits_vx_valid; // @[VCore.scala 134:29]
+  assign valu_io_in_bits_1_bits_vx_addr = vdec_io_out_1_bits_vx_addr; // @[VCore.scala 134:29]
+  assign valu_io_in_bits_1_bits_vx_tag = vdec_io_out_1_bits_vx_tag; // @[VCore.scala 134:29]
+  assign valu_io_in_bits_1_bits_vy_valid = vdec_io_out_1_bits_vy_valid; // @[VCore.scala 134:29]
+  assign valu_io_in_bits_1_bits_vy_addr = vdec_io_out_1_bits_vy_addr; // @[VCore.scala 134:29]
+  assign valu_io_in_bits_1_bits_vy_tag = vdec_io_out_1_bits_vy_tag; // @[VCore.scala 134:29]
+  assign valu_io_in_bits_1_bits_vz_valid = vdec_io_out_1_bits_vz_valid; // @[VCore.scala 134:29]
+  assign valu_io_in_bits_1_bits_vz_addr = vdec_io_out_1_bits_vz_addr; // @[VCore.scala 134:29]
+  assign valu_io_in_bits_1_bits_vz_tag = vdec_io_out_1_bits_vz_tag; // @[VCore.scala 134:29]
+  assign valu_io_in_bits_1_bits_sv_valid = vdec_io_out_1_bits_sv_valid; // @[VCore.scala 134:29]
+  assign valu_io_in_bits_1_bits_sv_data = vdec_io_out_1_bits_sv_data; // @[VCore.scala 134:29]
+  assign valu_io_in_bits_1_bits_cmdsync = vdec_io_out_1_bits_cmdsync; // @[VCore.scala 134:29]
+  assign valu_io_in_bits_2_valid = aluvalid[2]; // @[VCore.scala 133:41]
+  assign valu_io_in_bits_2_bits_op = vdec_io_out_2_bits_op; // @[VCore.scala 134:29]
+  assign valu_io_in_bits_2_bits_f2 = vdec_io_out_2_bits_f2; // @[VCore.scala 134:29]
+  assign valu_io_in_bits_2_bits_sz = vdec_io_out_2_bits_sz; // @[VCore.scala 134:29]
+  assign valu_io_in_bits_2_bits_m = vdec_io_out_2_bits_m; // @[VCore.scala 134:29]
+  assign valu_io_in_bits_2_bits_vd_addr = vdec_io_out_2_bits_vd_addr; // @[VCore.scala 134:29]
+  assign valu_io_in_bits_2_bits_ve_addr = vdec_io_out_2_bits_ve_addr; // @[VCore.scala 134:29]
+  assign valu_io_in_bits_2_bits_vf_addr = vdec_io_out_2_bits_vf_addr; // @[VCore.scala 134:29]
+  assign valu_io_in_bits_2_bits_vg_addr = vdec_io_out_2_bits_vg_addr; // @[VCore.scala 134:29]
+  assign valu_io_in_bits_2_bits_vs_valid = vdec_io_out_2_bits_vs_valid; // @[VCore.scala 134:29]
+  assign valu_io_in_bits_2_bits_vs_addr = vdec_io_out_2_bits_vs_addr; // @[VCore.scala 134:29]
+  assign valu_io_in_bits_2_bits_vs_tag = vdec_io_out_2_bits_vs_tag; // @[VCore.scala 134:29]
+  assign valu_io_in_bits_2_bits_vt_valid = vdec_io_out_2_bits_vt_valid; // @[VCore.scala 134:29]
+  assign valu_io_in_bits_2_bits_vt_addr = vdec_io_out_2_bits_vt_addr; // @[VCore.scala 134:29]
+  assign valu_io_in_bits_2_bits_vt_tag = vdec_io_out_2_bits_vt_tag; // @[VCore.scala 134:29]
+  assign valu_io_in_bits_2_bits_vu_valid = vdec_io_out_2_bits_vu_valid; // @[VCore.scala 134:29]
+  assign valu_io_in_bits_2_bits_vu_addr = vdec_io_out_2_bits_vu_addr; // @[VCore.scala 134:29]
+  assign valu_io_in_bits_2_bits_vu_tag = vdec_io_out_2_bits_vu_tag; // @[VCore.scala 134:29]
+  assign valu_io_in_bits_2_bits_vx_valid = vdec_io_out_2_bits_vx_valid; // @[VCore.scala 134:29]
+  assign valu_io_in_bits_2_bits_vx_addr = vdec_io_out_2_bits_vx_addr; // @[VCore.scala 134:29]
+  assign valu_io_in_bits_2_bits_vx_tag = vdec_io_out_2_bits_vx_tag; // @[VCore.scala 134:29]
+  assign valu_io_in_bits_2_bits_vy_valid = vdec_io_out_2_bits_vy_valid; // @[VCore.scala 134:29]
+  assign valu_io_in_bits_2_bits_vy_addr = vdec_io_out_2_bits_vy_addr; // @[VCore.scala 134:29]
+  assign valu_io_in_bits_2_bits_vy_tag = vdec_io_out_2_bits_vy_tag; // @[VCore.scala 134:29]
+  assign valu_io_in_bits_2_bits_vz_valid = vdec_io_out_2_bits_vz_valid; // @[VCore.scala 134:29]
+  assign valu_io_in_bits_2_bits_vz_addr = vdec_io_out_2_bits_vz_addr; // @[VCore.scala 134:29]
+  assign valu_io_in_bits_2_bits_vz_tag = vdec_io_out_2_bits_vz_tag; // @[VCore.scala 134:29]
+  assign valu_io_in_bits_2_bits_sv_valid = vdec_io_out_2_bits_sv_valid; // @[VCore.scala 134:29]
+  assign valu_io_in_bits_2_bits_sv_data = vdec_io_out_2_bits_sv_data; // @[VCore.scala 134:29]
+  assign valu_io_in_bits_2_bits_cmdsync = vdec_io_out_2_bits_cmdsync; // @[VCore.scala 134:29]
+  assign valu_io_in_bits_3_valid = aluvalid[3]; // @[VCore.scala 133:41]
+  assign valu_io_in_bits_3_bits_op = vdec_io_out_3_bits_op; // @[VCore.scala 134:29]
+  assign valu_io_in_bits_3_bits_f2 = vdec_io_out_3_bits_f2; // @[VCore.scala 134:29]
+  assign valu_io_in_bits_3_bits_sz = vdec_io_out_3_bits_sz; // @[VCore.scala 134:29]
+  assign valu_io_in_bits_3_bits_m = vdec_io_out_3_bits_m; // @[VCore.scala 134:29]
+  assign valu_io_in_bits_3_bits_vd_addr = vdec_io_out_3_bits_vd_addr; // @[VCore.scala 134:29]
+  assign valu_io_in_bits_3_bits_ve_addr = vdec_io_out_3_bits_ve_addr; // @[VCore.scala 134:29]
+  assign valu_io_in_bits_3_bits_vf_addr = vdec_io_out_3_bits_vf_addr; // @[VCore.scala 134:29]
+  assign valu_io_in_bits_3_bits_vg_addr = vdec_io_out_3_bits_vg_addr; // @[VCore.scala 134:29]
+  assign valu_io_in_bits_3_bits_vs_valid = vdec_io_out_3_bits_vs_valid; // @[VCore.scala 134:29]
+  assign valu_io_in_bits_3_bits_vs_addr = vdec_io_out_3_bits_vs_addr; // @[VCore.scala 134:29]
+  assign valu_io_in_bits_3_bits_vs_tag = vdec_io_out_3_bits_vs_tag; // @[VCore.scala 134:29]
+  assign valu_io_in_bits_3_bits_vt_valid = vdec_io_out_3_bits_vt_valid; // @[VCore.scala 134:29]
+  assign valu_io_in_bits_3_bits_vt_addr = vdec_io_out_3_bits_vt_addr; // @[VCore.scala 134:29]
+  assign valu_io_in_bits_3_bits_vt_tag = vdec_io_out_3_bits_vt_tag; // @[VCore.scala 134:29]
+  assign valu_io_in_bits_3_bits_vu_valid = vdec_io_out_3_bits_vu_valid; // @[VCore.scala 134:29]
+  assign valu_io_in_bits_3_bits_vu_addr = vdec_io_out_3_bits_vu_addr; // @[VCore.scala 134:29]
+  assign valu_io_in_bits_3_bits_vu_tag = vdec_io_out_3_bits_vu_tag; // @[VCore.scala 134:29]
+  assign valu_io_in_bits_3_bits_vx_valid = vdec_io_out_3_bits_vx_valid; // @[VCore.scala 134:29]
+  assign valu_io_in_bits_3_bits_vx_addr = vdec_io_out_3_bits_vx_addr; // @[VCore.scala 134:29]
+  assign valu_io_in_bits_3_bits_vx_tag = vdec_io_out_3_bits_vx_tag; // @[VCore.scala 134:29]
+  assign valu_io_in_bits_3_bits_vy_valid = vdec_io_out_3_bits_vy_valid; // @[VCore.scala 134:29]
+  assign valu_io_in_bits_3_bits_vy_addr = vdec_io_out_3_bits_vy_addr; // @[VCore.scala 134:29]
+  assign valu_io_in_bits_3_bits_vy_tag = vdec_io_out_3_bits_vy_tag; // @[VCore.scala 134:29]
+  assign valu_io_in_bits_3_bits_vz_valid = vdec_io_out_3_bits_vz_valid; // @[VCore.scala 134:29]
+  assign valu_io_in_bits_3_bits_vz_addr = vdec_io_out_3_bits_vz_addr; // @[VCore.scala 134:29]
+  assign valu_io_in_bits_3_bits_vz_tag = vdec_io_out_3_bits_vz_tag; // @[VCore.scala 134:29]
+  assign valu_io_in_bits_3_bits_sv_valid = vdec_io_out_3_bits_sv_valid; // @[VCore.scala 134:29]
+  assign valu_io_in_bits_3_bits_sv_data = vdec_io_out_3_bits_sv_data; // @[VCore.scala 134:29]
+  assign valu_io_in_bits_3_bits_cmdsync = vdec_io_out_3_bits_cmdsync; // @[VCore.scala 134:29]
+  assign valu_io_vrfsb = vrf_io_vrfsb_data; // @[VCore.scala 161:17]
+  assign valu_io_read_0_data = vrf_io_read_0_data; // @[VCore.scala 144:26]
+  assign valu_io_read_1_data = vrf_io_read_1_data; // @[VCore.scala 144:26]
+  assign valu_io_read_2_data = vrf_io_read_2_data; // @[VCore.scala 144:26]
+  assign valu_io_read_3_data = vrf_io_read_3_data; // @[VCore.scala 144:26]
+  assign valu_io_read_4_data = vrf_io_read_4_data; // @[VCore.scala 144:26]
+  assign valu_io_read_5_data = vrf_io_read_5_data; // @[VCore.scala 144:26]
   assign vconv_clock = clock;
   assign vconv_reset = reset;
-  assign vconv_io_in_valid = convvalid != 4'h0; // @[VCore.scala 177:34]
-  assign vconv_io_in_bits_0_valid = convvalid[0]; // @[VCore.scala 180:43]
-  assign vconv_io_in_bits_0_bits_op = vdec_io_out_0_bits_op; // @[VCore.scala 181:30]
-  assign vconv_io_in_bits_0_bits_m = vdec_io_out_0_bits_m; // @[VCore.scala 181:30]
-  assign vconv_io_in_bits_0_bits_vs_addr = vdec_io_out_0_bits_vs_addr; // @[VCore.scala 181:30]
-  assign vconv_io_in_bits_0_bits_vu_addr = vdec_io_out_0_bits_vu_addr; // @[VCore.scala 181:30]
-  assign vconv_io_in_bits_0_bits_sv_data = vdec_io_out_0_bits_sv_data; // @[VCore.scala 181:30]
-  assign vconv_io_in_bits_1_valid = convvalid[1]; // @[VCore.scala 180:43]
-  assign vconv_io_in_bits_1_bits_op = vdec_io_out_1_bits_op; // @[VCore.scala 181:30]
-  assign vconv_io_in_bits_1_bits_m = vdec_io_out_1_bits_m; // @[VCore.scala 181:30]
-  assign vconv_io_in_bits_1_bits_vs_addr = vdec_io_out_1_bits_vs_addr; // @[VCore.scala 181:30]
-  assign vconv_io_in_bits_1_bits_vu_addr = vdec_io_out_1_bits_vu_addr; // @[VCore.scala 181:30]
-  assign vconv_io_in_bits_1_bits_sv_data = vdec_io_out_1_bits_sv_data; // @[VCore.scala 181:30]
-  assign vconv_io_in_bits_2_valid = convvalid[2]; // @[VCore.scala 180:43]
-  assign vconv_io_in_bits_2_bits_op = vdec_io_out_2_bits_op; // @[VCore.scala 181:30]
-  assign vconv_io_in_bits_2_bits_m = vdec_io_out_2_bits_m; // @[VCore.scala 181:30]
-  assign vconv_io_in_bits_2_bits_vs_addr = vdec_io_out_2_bits_vs_addr; // @[VCore.scala 181:30]
-  assign vconv_io_in_bits_2_bits_vu_addr = vdec_io_out_2_bits_vu_addr; // @[VCore.scala 181:30]
-  assign vconv_io_in_bits_2_bits_sv_data = vdec_io_out_2_bits_sv_data; // @[VCore.scala 181:30]
-  assign vconv_io_in_bits_3_valid = convvalid[3]; // @[VCore.scala 180:43]
-  assign vconv_io_in_bits_3_bits_op = vdec_io_out_3_bits_op; // @[VCore.scala 181:30]
-  assign vconv_io_in_bits_3_bits_m = vdec_io_out_3_bits_m; // @[VCore.scala 181:30]
-  assign vconv_io_in_bits_3_bits_vs_addr = vdec_io_out_3_bits_vs_addr; // @[VCore.scala 181:30]
-  assign vconv_io_in_bits_3_bits_vu_addr = vdec_io_out_3_bits_vu_addr; // @[VCore.scala 181:30]
-  assign vconv_io_in_bits_3_bits_sv_data = vdec_io_out_3_bits_sv_data; // @[VCore.scala 181:30]
-  assign vconv_io_vrfsb = vrf_io_vrfsb_data; // @[VCore.scala 186:18]
+  assign vconv_io_in_valid = convvalid != 4'h0; // @[VCore.scala 175:34]
+  assign vconv_io_in_bits_0_valid = convvalid[0]; // @[VCore.scala 178:43]
+  assign vconv_io_in_bits_0_bits_op = vdec_io_out_0_bits_op; // @[VCore.scala 179:30]
+  assign vconv_io_in_bits_0_bits_m = vdec_io_out_0_bits_m; // @[VCore.scala 179:30]
+  assign vconv_io_in_bits_0_bits_vs_addr = vdec_io_out_0_bits_vs_addr; // @[VCore.scala 179:30]
+  assign vconv_io_in_bits_0_bits_vu_addr = vdec_io_out_0_bits_vu_addr; // @[VCore.scala 179:30]
+  assign vconv_io_in_bits_0_bits_sv_data = vdec_io_out_0_bits_sv_data; // @[VCore.scala 179:30]
+  assign vconv_io_in_bits_1_valid = convvalid[1]; // @[VCore.scala 178:43]
+  assign vconv_io_in_bits_1_bits_op = vdec_io_out_1_bits_op; // @[VCore.scala 179:30]
+  assign vconv_io_in_bits_1_bits_m = vdec_io_out_1_bits_m; // @[VCore.scala 179:30]
+  assign vconv_io_in_bits_1_bits_vs_addr = vdec_io_out_1_bits_vs_addr; // @[VCore.scala 179:30]
+  assign vconv_io_in_bits_1_bits_vu_addr = vdec_io_out_1_bits_vu_addr; // @[VCore.scala 179:30]
+  assign vconv_io_in_bits_1_bits_sv_data = vdec_io_out_1_bits_sv_data; // @[VCore.scala 179:30]
+  assign vconv_io_in_bits_2_valid = convvalid[2]; // @[VCore.scala 178:43]
+  assign vconv_io_in_bits_2_bits_op = vdec_io_out_2_bits_op; // @[VCore.scala 179:30]
+  assign vconv_io_in_bits_2_bits_m = vdec_io_out_2_bits_m; // @[VCore.scala 179:30]
+  assign vconv_io_in_bits_2_bits_vs_addr = vdec_io_out_2_bits_vs_addr; // @[VCore.scala 179:30]
+  assign vconv_io_in_bits_2_bits_vu_addr = vdec_io_out_2_bits_vu_addr; // @[VCore.scala 179:30]
+  assign vconv_io_in_bits_2_bits_sv_data = vdec_io_out_2_bits_sv_data; // @[VCore.scala 179:30]
+  assign vconv_io_in_bits_3_valid = convvalid[3]; // @[VCore.scala 178:43]
+  assign vconv_io_in_bits_3_bits_op = vdec_io_out_3_bits_op; // @[VCore.scala 179:30]
+  assign vconv_io_in_bits_3_bits_m = vdec_io_out_3_bits_m; // @[VCore.scala 179:30]
+  assign vconv_io_in_bits_3_bits_vs_addr = vdec_io_out_3_bits_vs_addr; // @[VCore.scala 179:30]
+  assign vconv_io_in_bits_3_bits_vu_addr = vdec_io_out_3_bits_vu_addr; // @[VCore.scala 179:30]
+  assign vconv_io_in_bits_3_bits_sv_data = vdec_io_out_3_bits_sv_data; // @[VCore.scala 179:30]
+  assign vconv_io_vrfsb = vrf_io_vrfsb_data; // @[VCore.scala 184:18]
   assign vldst_clock = clock;
   assign vldst_reset = reset;
-  assign vldst_io_in_valid = ldstvalid != 4'h0; // @[VCore.scala 200:34]
-  assign vldst_io_in_bits_0_valid = ldstvalid[0]; // @[VCore.scala 203:43]
-  assign vldst_io_in_bits_0_bits_op = vdec_io_out_0_bits_op; // @[VCore.scala 204:30]
-  assign vldst_io_in_bits_0_bits_f2 = vdec_io_out_0_bits_f2; // @[VCore.scala 204:30]
-  assign vldst_io_in_bits_0_bits_sz = vdec_io_out_0_bits_sz; // @[VCore.scala 204:30]
-  assign vldst_io_in_bits_0_bits_m = vdec_io_out_0_bits_m; // @[VCore.scala 204:30]
-  assign vldst_io_in_bits_0_bits_vd_valid = vdec_io_out_0_bits_vd_valid; // @[VCore.scala 204:30]
-  assign vldst_io_in_bits_0_bits_vd_addr = vdec_io_out_0_bits_vd_addr; // @[VCore.scala 204:30]
-  assign vldst_io_in_bits_0_bits_vs_valid = vdec_io_out_0_bits_vs_valid; // @[VCore.scala 204:30]
-  assign vldst_io_in_bits_0_bits_vs_addr = vdec_io_out_0_bits_vs_addr; // @[VCore.scala 204:30]
-  assign vldst_io_in_bits_0_bits_vs_tag = vdec_io_out_0_bits_vs_tag; // @[VCore.scala 204:30]
-  assign vldst_io_in_bits_0_bits_sv_addr = vdec_io_out_0_bits_sv_addr; // @[VCore.scala 204:30]
-  assign vldst_io_in_bits_0_bits_sv_data = vdec_io_out_0_bits_sv_data; // @[VCore.scala 204:30]
-  assign vldst_io_in_bits_1_valid = ldstvalid[1]; // @[VCore.scala 203:43]
-  assign vldst_io_in_bits_1_bits_op = vdec_io_out_1_bits_op; // @[VCore.scala 204:30]
-  assign vldst_io_in_bits_1_bits_f2 = vdec_io_out_1_bits_f2; // @[VCore.scala 204:30]
-  assign vldst_io_in_bits_1_bits_sz = vdec_io_out_1_bits_sz; // @[VCore.scala 204:30]
-  assign vldst_io_in_bits_1_bits_m = vdec_io_out_1_bits_m; // @[VCore.scala 204:30]
-  assign vldst_io_in_bits_1_bits_vd_valid = vdec_io_out_1_bits_vd_valid; // @[VCore.scala 204:30]
-  assign vldst_io_in_bits_1_bits_vd_addr = vdec_io_out_1_bits_vd_addr; // @[VCore.scala 204:30]
-  assign vldst_io_in_bits_1_bits_vs_valid = vdec_io_out_1_bits_vs_valid; // @[VCore.scala 204:30]
-  assign vldst_io_in_bits_1_bits_vs_addr = vdec_io_out_1_bits_vs_addr; // @[VCore.scala 204:30]
-  assign vldst_io_in_bits_1_bits_vs_tag = vdec_io_out_1_bits_vs_tag; // @[VCore.scala 204:30]
-  assign vldst_io_in_bits_1_bits_sv_addr = vdec_io_out_1_bits_sv_addr; // @[VCore.scala 204:30]
-  assign vldst_io_in_bits_1_bits_sv_data = vdec_io_out_1_bits_sv_data; // @[VCore.scala 204:30]
-  assign vldst_io_in_bits_2_valid = ldstvalid[2]; // @[VCore.scala 203:43]
-  assign vldst_io_in_bits_2_bits_op = vdec_io_out_2_bits_op; // @[VCore.scala 204:30]
-  assign vldst_io_in_bits_2_bits_f2 = vdec_io_out_2_bits_f2; // @[VCore.scala 204:30]
-  assign vldst_io_in_bits_2_bits_sz = vdec_io_out_2_bits_sz; // @[VCore.scala 204:30]
-  assign vldst_io_in_bits_2_bits_m = vdec_io_out_2_bits_m; // @[VCore.scala 204:30]
-  assign vldst_io_in_bits_2_bits_vd_valid = vdec_io_out_2_bits_vd_valid; // @[VCore.scala 204:30]
-  assign vldst_io_in_bits_2_bits_vd_addr = vdec_io_out_2_bits_vd_addr; // @[VCore.scala 204:30]
-  assign vldst_io_in_bits_2_bits_vs_valid = vdec_io_out_2_bits_vs_valid; // @[VCore.scala 204:30]
-  assign vldst_io_in_bits_2_bits_vs_addr = vdec_io_out_2_bits_vs_addr; // @[VCore.scala 204:30]
-  assign vldst_io_in_bits_2_bits_vs_tag = vdec_io_out_2_bits_vs_tag; // @[VCore.scala 204:30]
-  assign vldst_io_in_bits_2_bits_sv_addr = vdec_io_out_2_bits_sv_addr; // @[VCore.scala 204:30]
-  assign vldst_io_in_bits_2_bits_sv_data = vdec_io_out_2_bits_sv_data; // @[VCore.scala 204:30]
-  assign vldst_io_in_bits_3_valid = ldstvalid[3]; // @[VCore.scala 203:43]
-  assign vldst_io_in_bits_3_bits_op = vdec_io_out_3_bits_op; // @[VCore.scala 204:30]
-  assign vldst_io_in_bits_3_bits_f2 = vdec_io_out_3_bits_f2; // @[VCore.scala 204:30]
-  assign vldst_io_in_bits_3_bits_sz = vdec_io_out_3_bits_sz; // @[VCore.scala 204:30]
-  assign vldst_io_in_bits_3_bits_m = vdec_io_out_3_bits_m; // @[VCore.scala 204:30]
-  assign vldst_io_in_bits_3_bits_vd_valid = vdec_io_out_3_bits_vd_valid; // @[VCore.scala 204:30]
-  assign vldst_io_in_bits_3_bits_vd_addr = vdec_io_out_3_bits_vd_addr; // @[VCore.scala 204:30]
-  assign vldst_io_in_bits_3_bits_vs_valid = vdec_io_out_3_bits_vs_valid; // @[VCore.scala 204:30]
-  assign vldst_io_in_bits_3_bits_vs_addr = vdec_io_out_3_bits_vs_addr; // @[VCore.scala 204:30]
-  assign vldst_io_in_bits_3_bits_vs_tag = vdec_io_out_3_bits_vs_tag; // @[VCore.scala 204:30]
-  assign vldst_io_in_bits_3_bits_sv_addr = vdec_io_out_3_bits_sv_addr; // @[VCore.scala 204:30]
-  assign vldst_io_in_bits_3_bits_sv_data = vdec_io_out_3_bits_sv_data; // @[VCore.scala 204:30]
-  assign vldst_io_vrfsb = vrf_io_vrfsb_data; // @[VCore.scala 210:18]
-  assign vldst_io_read_ready = ~vst_io_read_valid; // @[VCore.scala 207:26]
-  assign vldst_io_read_data = vrf_io_read_6_data; // @[VCore.scala 208:22]
-  assign vldst_io_dbus_ready = io_dbus_ready; // @[VCore.scala 212:11]
-  assign vldst_io_dbus_rdata = io_dbus_rdata; // @[VCore.scala 212:11]
+  assign vldst_io_in_valid = ldstvalid != 4'h0; // @[VCore.scala 198:34]
+  assign vldst_io_in_bits_0_valid = ldstvalid[0]; // @[VCore.scala 201:43]
+  assign vldst_io_in_bits_0_bits_op = vdec_io_out_0_bits_op; // @[VCore.scala 202:30]
+  assign vldst_io_in_bits_0_bits_f2 = vdec_io_out_0_bits_f2; // @[VCore.scala 202:30]
+  assign vldst_io_in_bits_0_bits_sz = vdec_io_out_0_bits_sz; // @[VCore.scala 202:30]
+  assign vldst_io_in_bits_0_bits_m = vdec_io_out_0_bits_m; // @[VCore.scala 202:30]
+  assign vldst_io_in_bits_0_bits_vd_valid = vdec_io_out_0_bits_vd_valid; // @[VCore.scala 202:30]
+  assign vldst_io_in_bits_0_bits_vd_addr = vdec_io_out_0_bits_vd_addr; // @[VCore.scala 202:30]
+  assign vldst_io_in_bits_0_bits_vs_valid = vdec_io_out_0_bits_vs_valid; // @[VCore.scala 202:30]
+  assign vldst_io_in_bits_0_bits_vs_addr = vdec_io_out_0_bits_vs_addr; // @[VCore.scala 202:30]
+  assign vldst_io_in_bits_0_bits_vs_tag = vdec_io_out_0_bits_vs_tag; // @[VCore.scala 202:30]
+  assign vldst_io_in_bits_0_bits_sv_addr = vdec_io_out_0_bits_sv_addr; // @[VCore.scala 202:30]
+  assign vldst_io_in_bits_0_bits_sv_data = vdec_io_out_0_bits_sv_data; // @[VCore.scala 202:30]
+  assign vldst_io_in_bits_1_valid = ldstvalid[1]; // @[VCore.scala 201:43]
+  assign vldst_io_in_bits_1_bits_op = vdec_io_out_1_bits_op; // @[VCore.scala 202:30]
+  assign vldst_io_in_bits_1_bits_f2 = vdec_io_out_1_bits_f2; // @[VCore.scala 202:30]
+  assign vldst_io_in_bits_1_bits_sz = vdec_io_out_1_bits_sz; // @[VCore.scala 202:30]
+  assign vldst_io_in_bits_1_bits_m = vdec_io_out_1_bits_m; // @[VCore.scala 202:30]
+  assign vldst_io_in_bits_1_bits_vd_valid = vdec_io_out_1_bits_vd_valid; // @[VCore.scala 202:30]
+  assign vldst_io_in_bits_1_bits_vd_addr = vdec_io_out_1_bits_vd_addr; // @[VCore.scala 202:30]
+  assign vldst_io_in_bits_1_bits_vs_valid = vdec_io_out_1_bits_vs_valid; // @[VCore.scala 202:30]
+  assign vldst_io_in_bits_1_bits_vs_addr = vdec_io_out_1_bits_vs_addr; // @[VCore.scala 202:30]
+  assign vldst_io_in_bits_1_bits_vs_tag = vdec_io_out_1_bits_vs_tag; // @[VCore.scala 202:30]
+  assign vldst_io_in_bits_1_bits_sv_addr = vdec_io_out_1_bits_sv_addr; // @[VCore.scala 202:30]
+  assign vldst_io_in_bits_1_bits_sv_data = vdec_io_out_1_bits_sv_data; // @[VCore.scala 202:30]
+  assign vldst_io_in_bits_2_valid = ldstvalid[2]; // @[VCore.scala 201:43]
+  assign vldst_io_in_bits_2_bits_op = vdec_io_out_2_bits_op; // @[VCore.scala 202:30]
+  assign vldst_io_in_bits_2_bits_f2 = vdec_io_out_2_bits_f2; // @[VCore.scala 202:30]
+  assign vldst_io_in_bits_2_bits_sz = vdec_io_out_2_bits_sz; // @[VCore.scala 202:30]
+  assign vldst_io_in_bits_2_bits_m = vdec_io_out_2_bits_m; // @[VCore.scala 202:30]
+  assign vldst_io_in_bits_2_bits_vd_valid = vdec_io_out_2_bits_vd_valid; // @[VCore.scala 202:30]
+  assign vldst_io_in_bits_2_bits_vd_addr = vdec_io_out_2_bits_vd_addr; // @[VCore.scala 202:30]
+  assign vldst_io_in_bits_2_bits_vs_valid = vdec_io_out_2_bits_vs_valid; // @[VCore.scala 202:30]
+  assign vldst_io_in_bits_2_bits_vs_addr = vdec_io_out_2_bits_vs_addr; // @[VCore.scala 202:30]
+  assign vldst_io_in_bits_2_bits_vs_tag = vdec_io_out_2_bits_vs_tag; // @[VCore.scala 202:30]
+  assign vldst_io_in_bits_2_bits_sv_addr = vdec_io_out_2_bits_sv_addr; // @[VCore.scala 202:30]
+  assign vldst_io_in_bits_2_bits_sv_data = vdec_io_out_2_bits_sv_data; // @[VCore.scala 202:30]
+  assign vldst_io_in_bits_3_valid = ldstvalid[3]; // @[VCore.scala 201:43]
+  assign vldst_io_in_bits_3_bits_op = vdec_io_out_3_bits_op; // @[VCore.scala 202:30]
+  assign vldst_io_in_bits_3_bits_f2 = vdec_io_out_3_bits_f2; // @[VCore.scala 202:30]
+  assign vldst_io_in_bits_3_bits_sz = vdec_io_out_3_bits_sz; // @[VCore.scala 202:30]
+  assign vldst_io_in_bits_3_bits_m = vdec_io_out_3_bits_m; // @[VCore.scala 202:30]
+  assign vldst_io_in_bits_3_bits_vd_valid = vdec_io_out_3_bits_vd_valid; // @[VCore.scala 202:30]
+  assign vldst_io_in_bits_3_bits_vd_addr = vdec_io_out_3_bits_vd_addr; // @[VCore.scala 202:30]
+  assign vldst_io_in_bits_3_bits_vs_valid = vdec_io_out_3_bits_vs_valid; // @[VCore.scala 202:30]
+  assign vldst_io_in_bits_3_bits_vs_addr = vdec_io_out_3_bits_vs_addr; // @[VCore.scala 202:30]
+  assign vldst_io_in_bits_3_bits_vs_tag = vdec_io_out_3_bits_vs_tag; // @[VCore.scala 202:30]
+  assign vldst_io_in_bits_3_bits_sv_addr = vdec_io_out_3_bits_sv_addr; // @[VCore.scala 202:30]
+  assign vldst_io_in_bits_3_bits_sv_data = vdec_io_out_3_bits_sv_data; // @[VCore.scala 202:30]
+  assign vldst_io_vrfsb = vrf_io_vrfsb_data; // @[VCore.scala 208:18]
+  assign vldst_io_read_ready = ~vst_io_read_valid; // @[VCore.scala 205:26]
+  assign vldst_io_read_data = vrf_io_read_6_data; // @[VCore.scala 206:22]
+  assign vldst_io_dbus_ready = io_dbus_ready; // @[VCore.scala 210:11]
+  assign vldst_io_dbus_rdata = io_dbus_rdata; // @[VCore.scala 210:11]
   assign vld_clock = clock;
   assign vld_reset = reset;
-  assign vld_io_in_valid = ldvalid != 4'h0; // @[VCore.scala 230:30]
-  assign vld_io_in_bits_0_valid = ldvalid[0]; // @[VCore.scala 233:39]
-  assign vld_io_in_bits_0_bits_op = vdec_io_out_0_bits_op; // @[VCore.scala 234:28]
-  assign vld_io_in_bits_0_bits_f2 = vdec_io_out_0_bits_f2; // @[VCore.scala 234:28]
-  assign vld_io_in_bits_0_bits_sz = vdec_io_out_0_bits_sz; // @[VCore.scala 234:28]
-  assign vld_io_in_bits_0_bits_m = vdec_io_out_0_bits_m; // @[VCore.scala 234:28]
-  assign vld_io_in_bits_0_bits_vd_valid = vdec_io_out_0_bits_vd_valid; // @[VCore.scala 234:28]
-  assign vld_io_in_bits_0_bits_vd_addr = vdec_io_out_0_bits_vd_addr; // @[VCore.scala 234:28]
-  assign vld_io_in_bits_0_bits_vs_valid = vdec_io_out_0_bits_vs_valid; // @[VCore.scala 234:28]
-  assign vld_io_in_bits_0_bits_sv_addr = vdec_io_out_0_bits_sv_addr; // @[VCore.scala 234:28]
-  assign vld_io_in_bits_0_bits_sv_data = vdec_io_out_0_bits_sv_data; // @[VCore.scala 234:28]
-  assign vld_io_in_bits_1_valid = ldvalid[1]; // @[VCore.scala 233:39]
-  assign vld_io_in_bits_1_bits_op = vdec_io_out_1_bits_op; // @[VCore.scala 234:28]
-  assign vld_io_in_bits_1_bits_f2 = vdec_io_out_1_bits_f2; // @[VCore.scala 234:28]
-  assign vld_io_in_bits_1_bits_sz = vdec_io_out_1_bits_sz; // @[VCore.scala 234:28]
-  assign vld_io_in_bits_1_bits_m = vdec_io_out_1_bits_m; // @[VCore.scala 234:28]
-  assign vld_io_in_bits_1_bits_vd_valid = vdec_io_out_1_bits_vd_valid; // @[VCore.scala 234:28]
-  assign vld_io_in_bits_1_bits_vd_addr = vdec_io_out_1_bits_vd_addr; // @[VCore.scala 234:28]
-  assign vld_io_in_bits_1_bits_vs_valid = vdec_io_out_1_bits_vs_valid; // @[VCore.scala 234:28]
-  assign vld_io_in_bits_1_bits_sv_addr = vdec_io_out_1_bits_sv_addr; // @[VCore.scala 234:28]
-  assign vld_io_in_bits_1_bits_sv_data = vdec_io_out_1_bits_sv_data; // @[VCore.scala 234:28]
-  assign vld_io_in_bits_2_valid = ldvalid[2]; // @[VCore.scala 233:39]
-  assign vld_io_in_bits_2_bits_op = vdec_io_out_2_bits_op; // @[VCore.scala 234:28]
-  assign vld_io_in_bits_2_bits_f2 = vdec_io_out_2_bits_f2; // @[VCore.scala 234:28]
-  assign vld_io_in_bits_2_bits_sz = vdec_io_out_2_bits_sz; // @[VCore.scala 234:28]
-  assign vld_io_in_bits_2_bits_m = vdec_io_out_2_bits_m; // @[VCore.scala 234:28]
-  assign vld_io_in_bits_2_bits_vd_valid = vdec_io_out_2_bits_vd_valid; // @[VCore.scala 234:28]
-  assign vld_io_in_bits_2_bits_vd_addr = vdec_io_out_2_bits_vd_addr; // @[VCore.scala 234:28]
-  assign vld_io_in_bits_2_bits_vs_valid = vdec_io_out_2_bits_vs_valid; // @[VCore.scala 234:28]
-  assign vld_io_in_bits_2_bits_sv_addr = vdec_io_out_2_bits_sv_addr; // @[VCore.scala 234:28]
-  assign vld_io_in_bits_2_bits_sv_data = vdec_io_out_2_bits_sv_data; // @[VCore.scala 234:28]
-  assign vld_io_in_bits_3_valid = ldvalid[3]; // @[VCore.scala 233:39]
-  assign vld_io_in_bits_3_bits_op = vdec_io_out_3_bits_op; // @[VCore.scala 234:28]
-  assign vld_io_in_bits_3_bits_f2 = vdec_io_out_3_bits_f2; // @[VCore.scala 234:28]
-  assign vld_io_in_bits_3_bits_sz = vdec_io_out_3_bits_sz; // @[VCore.scala 234:28]
-  assign vld_io_in_bits_3_bits_m = vdec_io_out_3_bits_m; // @[VCore.scala 234:28]
-  assign vld_io_in_bits_3_bits_vd_valid = vdec_io_out_3_bits_vd_valid; // @[VCore.scala 234:28]
-  assign vld_io_in_bits_3_bits_vd_addr = vdec_io_out_3_bits_vd_addr; // @[VCore.scala 234:28]
-  assign vld_io_in_bits_3_bits_vs_valid = vdec_io_out_3_bits_vs_valid; // @[VCore.scala 234:28]
-  assign vld_io_in_bits_3_bits_sv_addr = vdec_io_out_3_bits_sv_addr; // @[VCore.scala 234:28]
-  assign vld_io_in_bits_3_bits_sv_data = vdec_io_out_3_bits_sv_data; // @[VCore.scala 234:28]
-  assign vld_io_axi_addr_ready = io_ld_addr_ready; // @[VCore.scala 237:9]
-  assign vld_io_axi_data_valid = io_ld_data_valid; // @[VCore.scala 237:9]
-  assign vld_io_axi_data_bits_id = io_ld_data_bits_id; // @[VCore.scala 237:9]
-  assign vld_io_axi_data_bits_data = io_ld_data_bits_data; // @[VCore.scala 237:9]
+  assign vld_io_in_valid = ldvalid != 4'h0; // @[VCore.scala 228:30]
+  assign vld_io_in_bits_0_valid = ldvalid[0]; // @[VCore.scala 231:39]
+  assign vld_io_in_bits_0_bits_op = vdec_io_out_0_bits_op; // @[VCore.scala 232:28]
+  assign vld_io_in_bits_0_bits_f2 = vdec_io_out_0_bits_f2; // @[VCore.scala 232:28]
+  assign vld_io_in_bits_0_bits_sz = vdec_io_out_0_bits_sz; // @[VCore.scala 232:28]
+  assign vld_io_in_bits_0_bits_m = vdec_io_out_0_bits_m; // @[VCore.scala 232:28]
+  assign vld_io_in_bits_0_bits_vd_valid = vdec_io_out_0_bits_vd_valid; // @[VCore.scala 232:28]
+  assign vld_io_in_bits_0_bits_vd_addr = vdec_io_out_0_bits_vd_addr; // @[VCore.scala 232:28]
+  assign vld_io_in_bits_0_bits_vs_valid = vdec_io_out_0_bits_vs_valid; // @[VCore.scala 232:28]
+  assign vld_io_in_bits_0_bits_sv_addr = vdec_io_out_0_bits_sv_addr; // @[VCore.scala 232:28]
+  assign vld_io_in_bits_0_bits_sv_data = vdec_io_out_0_bits_sv_data; // @[VCore.scala 232:28]
+  assign vld_io_in_bits_1_valid = ldvalid[1]; // @[VCore.scala 231:39]
+  assign vld_io_in_bits_1_bits_op = vdec_io_out_1_bits_op; // @[VCore.scala 232:28]
+  assign vld_io_in_bits_1_bits_f2 = vdec_io_out_1_bits_f2; // @[VCore.scala 232:28]
+  assign vld_io_in_bits_1_bits_sz = vdec_io_out_1_bits_sz; // @[VCore.scala 232:28]
+  assign vld_io_in_bits_1_bits_m = vdec_io_out_1_bits_m; // @[VCore.scala 232:28]
+  assign vld_io_in_bits_1_bits_vd_valid = vdec_io_out_1_bits_vd_valid; // @[VCore.scala 232:28]
+  assign vld_io_in_bits_1_bits_vd_addr = vdec_io_out_1_bits_vd_addr; // @[VCore.scala 232:28]
+  assign vld_io_in_bits_1_bits_vs_valid = vdec_io_out_1_bits_vs_valid; // @[VCore.scala 232:28]
+  assign vld_io_in_bits_1_bits_sv_addr = vdec_io_out_1_bits_sv_addr; // @[VCore.scala 232:28]
+  assign vld_io_in_bits_1_bits_sv_data = vdec_io_out_1_bits_sv_data; // @[VCore.scala 232:28]
+  assign vld_io_in_bits_2_valid = ldvalid[2]; // @[VCore.scala 231:39]
+  assign vld_io_in_bits_2_bits_op = vdec_io_out_2_bits_op; // @[VCore.scala 232:28]
+  assign vld_io_in_bits_2_bits_f2 = vdec_io_out_2_bits_f2; // @[VCore.scala 232:28]
+  assign vld_io_in_bits_2_bits_sz = vdec_io_out_2_bits_sz; // @[VCore.scala 232:28]
+  assign vld_io_in_bits_2_bits_m = vdec_io_out_2_bits_m; // @[VCore.scala 232:28]
+  assign vld_io_in_bits_2_bits_vd_valid = vdec_io_out_2_bits_vd_valid; // @[VCore.scala 232:28]
+  assign vld_io_in_bits_2_bits_vd_addr = vdec_io_out_2_bits_vd_addr; // @[VCore.scala 232:28]
+  assign vld_io_in_bits_2_bits_vs_valid = vdec_io_out_2_bits_vs_valid; // @[VCore.scala 232:28]
+  assign vld_io_in_bits_2_bits_sv_addr = vdec_io_out_2_bits_sv_addr; // @[VCore.scala 232:28]
+  assign vld_io_in_bits_2_bits_sv_data = vdec_io_out_2_bits_sv_data; // @[VCore.scala 232:28]
+  assign vld_io_in_bits_3_valid = ldvalid[3]; // @[VCore.scala 231:39]
+  assign vld_io_in_bits_3_bits_op = vdec_io_out_3_bits_op; // @[VCore.scala 232:28]
+  assign vld_io_in_bits_3_bits_f2 = vdec_io_out_3_bits_f2; // @[VCore.scala 232:28]
+  assign vld_io_in_bits_3_bits_sz = vdec_io_out_3_bits_sz; // @[VCore.scala 232:28]
+  assign vld_io_in_bits_3_bits_m = vdec_io_out_3_bits_m; // @[VCore.scala 232:28]
+  assign vld_io_in_bits_3_bits_vd_valid = vdec_io_out_3_bits_vd_valid; // @[VCore.scala 232:28]
+  assign vld_io_in_bits_3_bits_vd_addr = vdec_io_out_3_bits_vd_addr; // @[VCore.scala 232:28]
+  assign vld_io_in_bits_3_bits_vs_valid = vdec_io_out_3_bits_vs_valid; // @[VCore.scala 232:28]
+  assign vld_io_in_bits_3_bits_sv_addr = vdec_io_out_3_bits_sv_addr; // @[VCore.scala 232:28]
+  assign vld_io_in_bits_3_bits_sv_data = vdec_io_out_3_bits_sv_data; // @[VCore.scala 232:28]
+  assign vld_io_axi_addr_ready = io_ld_addr_ready; // @[VCore.scala 235:9]
+  assign vld_io_axi_data_valid = io_ld_data_valid; // @[VCore.scala 235:9]
+  assign vld_io_axi_data_bits_id = io_ld_data_bits_id; // @[VCore.scala 235:9]
+  assign vld_io_axi_data_bits_data = io_ld_data_bits_data; // @[VCore.scala 235:9]
   assign vst_clock = clock;
   assign vst_reset = reset;
-  assign vst_io_in_valid = stvalid != 4'h0; // @[VCore.scala 254:30]
-  assign vst_io_in_bits_0_valid = stvalid[0]; // @[VCore.scala 257:39]
-  assign vst_io_in_bits_0_bits_op = vdec_io_out_0_bits_op; // @[VCore.scala 258:28]
-  assign vst_io_in_bits_0_bits_f2 = vdec_io_out_0_bits_f2; // @[VCore.scala 258:28]
-  assign vst_io_in_bits_0_bits_sz = vdec_io_out_0_bits_sz; // @[VCore.scala 258:28]
-  assign vst_io_in_bits_0_bits_m = vdec_io_out_0_bits_m; // @[VCore.scala 258:28]
-  assign vst_io_in_bits_0_bits_vs_valid = vdec_io_out_0_bits_vs_valid; // @[VCore.scala 258:28]
-  assign vst_io_in_bits_0_bits_vs_addr = vdec_io_out_0_bits_vs_addr; // @[VCore.scala 258:28]
-  assign vst_io_in_bits_0_bits_vs_tag = vdec_io_out_0_bits_vs_tag; // @[VCore.scala 258:28]
-  assign vst_io_in_bits_0_bits_sv_addr = vdec_io_out_0_bits_sv_addr; // @[VCore.scala 258:28]
-  assign vst_io_in_bits_0_bits_sv_data = vdec_io_out_0_bits_sv_data; // @[VCore.scala 258:28]
-  assign vst_io_in_bits_1_valid = stvalid[1]; // @[VCore.scala 257:39]
-  assign vst_io_in_bits_1_bits_op = vdec_io_out_1_bits_op; // @[VCore.scala 258:28]
-  assign vst_io_in_bits_1_bits_f2 = vdec_io_out_1_bits_f2; // @[VCore.scala 258:28]
-  assign vst_io_in_bits_1_bits_sz = vdec_io_out_1_bits_sz; // @[VCore.scala 258:28]
-  assign vst_io_in_bits_1_bits_m = vdec_io_out_1_bits_m; // @[VCore.scala 258:28]
-  assign vst_io_in_bits_1_bits_vs_valid = vdec_io_out_1_bits_vs_valid; // @[VCore.scala 258:28]
-  assign vst_io_in_bits_1_bits_vs_addr = vdec_io_out_1_bits_vs_addr; // @[VCore.scala 258:28]
-  assign vst_io_in_bits_1_bits_vs_tag = vdec_io_out_1_bits_vs_tag; // @[VCore.scala 258:28]
-  assign vst_io_in_bits_1_bits_sv_addr = vdec_io_out_1_bits_sv_addr; // @[VCore.scala 258:28]
-  assign vst_io_in_bits_1_bits_sv_data = vdec_io_out_1_bits_sv_data; // @[VCore.scala 258:28]
-  assign vst_io_in_bits_2_valid = stvalid[2]; // @[VCore.scala 257:39]
-  assign vst_io_in_bits_2_bits_op = vdec_io_out_2_bits_op; // @[VCore.scala 258:28]
-  assign vst_io_in_bits_2_bits_f2 = vdec_io_out_2_bits_f2; // @[VCore.scala 258:28]
-  assign vst_io_in_bits_2_bits_sz = vdec_io_out_2_bits_sz; // @[VCore.scala 258:28]
-  assign vst_io_in_bits_2_bits_m = vdec_io_out_2_bits_m; // @[VCore.scala 258:28]
-  assign vst_io_in_bits_2_bits_vs_valid = vdec_io_out_2_bits_vs_valid; // @[VCore.scala 258:28]
-  assign vst_io_in_bits_2_bits_vs_addr = vdec_io_out_2_bits_vs_addr; // @[VCore.scala 258:28]
-  assign vst_io_in_bits_2_bits_vs_tag = vdec_io_out_2_bits_vs_tag; // @[VCore.scala 258:28]
-  assign vst_io_in_bits_2_bits_sv_addr = vdec_io_out_2_bits_sv_addr; // @[VCore.scala 258:28]
-  assign vst_io_in_bits_2_bits_sv_data = vdec_io_out_2_bits_sv_data; // @[VCore.scala 258:28]
-  assign vst_io_in_bits_3_valid = stvalid[3]; // @[VCore.scala 257:39]
-  assign vst_io_in_bits_3_bits_op = vdec_io_out_3_bits_op; // @[VCore.scala 258:28]
-  assign vst_io_in_bits_3_bits_f2 = vdec_io_out_3_bits_f2; // @[VCore.scala 258:28]
-  assign vst_io_in_bits_3_bits_sz = vdec_io_out_3_bits_sz; // @[VCore.scala 258:28]
-  assign vst_io_in_bits_3_bits_m = vdec_io_out_3_bits_m; // @[VCore.scala 258:28]
-  assign vst_io_in_bits_3_bits_vs_valid = vdec_io_out_3_bits_vs_valid; // @[VCore.scala 258:28]
-  assign vst_io_in_bits_3_bits_vs_addr = vdec_io_out_3_bits_vs_addr; // @[VCore.scala 258:28]
-  assign vst_io_in_bits_3_bits_vs_tag = vdec_io_out_3_bits_vs_tag; // @[VCore.scala 258:28]
-  assign vst_io_in_bits_3_bits_sv_addr = vdec_io_out_3_bits_sv_addr; // @[VCore.scala 258:28]
-  assign vst_io_in_bits_3_bits_sv_data = vdec_io_out_3_bits_sv_data; // @[VCore.scala 258:28]
-  assign vst_io_vrfsb = vrf_io_vrfsb_data; // @[VCore.scala 263:16]
-  assign vst_io_read_ready = 1'h1; // @[VCore.scala 265:21]
-  assign vst_io_read_data = vrf_io_read_6_data; // @[VCore.scala 266:20]
-  assign vst_io_axi_addr_ready = io_st_addr_ready; // @[VCore.scala 261:9]
-  assign vst_io_axi_data_ready = io_st_data_ready; // @[VCore.scala 261:9]
-  assign vst_io_axi_resp_valid = io_st_resp_valid; // @[VCore.scala 261:9]
+  assign vst_io_in_valid = stvalid != 4'h0; // @[VCore.scala 252:30]
+  assign vst_io_in_bits_0_valid = stvalid[0]; // @[VCore.scala 255:39]
+  assign vst_io_in_bits_0_bits_op = vdec_io_out_0_bits_op; // @[VCore.scala 256:28]
+  assign vst_io_in_bits_0_bits_f2 = vdec_io_out_0_bits_f2; // @[VCore.scala 256:28]
+  assign vst_io_in_bits_0_bits_sz = vdec_io_out_0_bits_sz; // @[VCore.scala 256:28]
+  assign vst_io_in_bits_0_bits_m = vdec_io_out_0_bits_m; // @[VCore.scala 256:28]
+  assign vst_io_in_bits_0_bits_vs_valid = vdec_io_out_0_bits_vs_valid; // @[VCore.scala 256:28]
+  assign vst_io_in_bits_0_bits_vs_addr = vdec_io_out_0_bits_vs_addr; // @[VCore.scala 256:28]
+  assign vst_io_in_bits_0_bits_vs_tag = vdec_io_out_0_bits_vs_tag; // @[VCore.scala 256:28]
+  assign vst_io_in_bits_0_bits_sv_addr = vdec_io_out_0_bits_sv_addr; // @[VCore.scala 256:28]
+  assign vst_io_in_bits_0_bits_sv_data = vdec_io_out_0_bits_sv_data; // @[VCore.scala 256:28]
+  assign vst_io_in_bits_1_valid = stvalid[1]; // @[VCore.scala 255:39]
+  assign vst_io_in_bits_1_bits_op = vdec_io_out_1_bits_op; // @[VCore.scala 256:28]
+  assign vst_io_in_bits_1_bits_f2 = vdec_io_out_1_bits_f2; // @[VCore.scala 256:28]
+  assign vst_io_in_bits_1_bits_sz = vdec_io_out_1_bits_sz; // @[VCore.scala 256:28]
+  assign vst_io_in_bits_1_bits_m = vdec_io_out_1_bits_m; // @[VCore.scala 256:28]
+  assign vst_io_in_bits_1_bits_vs_valid = vdec_io_out_1_bits_vs_valid; // @[VCore.scala 256:28]
+  assign vst_io_in_bits_1_bits_vs_addr = vdec_io_out_1_bits_vs_addr; // @[VCore.scala 256:28]
+  assign vst_io_in_bits_1_bits_vs_tag = vdec_io_out_1_bits_vs_tag; // @[VCore.scala 256:28]
+  assign vst_io_in_bits_1_bits_sv_addr = vdec_io_out_1_bits_sv_addr; // @[VCore.scala 256:28]
+  assign vst_io_in_bits_1_bits_sv_data = vdec_io_out_1_bits_sv_data; // @[VCore.scala 256:28]
+  assign vst_io_in_bits_2_valid = stvalid[2]; // @[VCore.scala 255:39]
+  assign vst_io_in_bits_2_bits_op = vdec_io_out_2_bits_op; // @[VCore.scala 256:28]
+  assign vst_io_in_bits_2_bits_f2 = vdec_io_out_2_bits_f2; // @[VCore.scala 256:28]
+  assign vst_io_in_bits_2_bits_sz = vdec_io_out_2_bits_sz; // @[VCore.scala 256:28]
+  assign vst_io_in_bits_2_bits_m = vdec_io_out_2_bits_m; // @[VCore.scala 256:28]
+  assign vst_io_in_bits_2_bits_vs_valid = vdec_io_out_2_bits_vs_valid; // @[VCore.scala 256:28]
+  assign vst_io_in_bits_2_bits_vs_addr = vdec_io_out_2_bits_vs_addr; // @[VCore.scala 256:28]
+  assign vst_io_in_bits_2_bits_vs_tag = vdec_io_out_2_bits_vs_tag; // @[VCore.scala 256:28]
+  assign vst_io_in_bits_2_bits_sv_addr = vdec_io_out_2_bits_sv_addr; // @[VCore.scala 256:28]
+  assign vst_io_in_bits_2_bits_sv_data = vdec_io_out_2_bits_sv_data; // @[VCore.scala 256:28]
+  assign vst_io_in_bits_3_valid = stvalid[3]; // @[VCore.scala 255:39]
+  assign vst_io_in_bits_3_bits_op = vdec_io_out_3_bits_op; // @[VCore.scala 256:28]
+  assign vst_io_in_bits_3_bits_f2 = vdec_io_out_3_bits_f2; // @[VCore.scala 256:28]
+  assign vst_io_in_bits_3_bits_sz = vdec_io_out_3_bits_sz; // @[VCore.scala 256:28]
+  assign vst_io_in_bits_3_bits_m = vdec_io_out_3_bits_m; // @[VCore.scala 256:28]
+  assign vst_io_in_bits_3_bits_vs_valid = vdec_io_out_3_bits_vs_valid; // @[VCore.scala 256:28]
+  assign vst_io_in_bits_3_bits_vs_addr = vdec_io_out_3_bits_vs_addr; // @[VCore.scala 256:28]
+  assign vst_io_in_bits_3_bits_vs_tag = vdec_io_out_3_bits_vs_tag; // @[VCore.scala 256:28]
+  assign vst_io_in_bits_3_bits_sv_addr = vdec_io_out_3_bits_sv_addr; // @[VCore.scala 256:28]
+  assign vst_io_in_bits_3_bits_sv_data = vdec_io_out_3_bits_sv_data; // @[VCore.scala 256:28]
+  assign vst_io_vrfsb = vrf_io_vrfsb_data; // @[VCore.scala 261:16]
+  assign vst_io_read_ready = 1'h1; // @[VCore.scala 263:21]
+  assign vst_io_read_data = vrf_io_read_6_data; // @[VCore.scala 264:20]
+  assign vst_io_axi_addr_ready = io_st_addr_ready; // @[VCore.scala 259:9]
+  assign vst_io_axi_data_ready = io_st_data_ready; // @[VCore.scala 259:9]
+  assign vst_io_axi_resp_valid = io_st_resp_valid; // @[VCore.scala 259:9]
   assign vrf_clock = clock;
   assign vrf_reset = reset;
-  assign vrf_io_read_0_valid = valu_io_read_0_valid; // @[VCore.scala 140:26]
-  assign vrf_io_read_0_addr = valu_io_read_0_addr; // @[VCore.scala 141:25]
-  assign vrf_io_read_1_valid = valu_io_read_1_valid; // @[VCore.scala 140:26]
-  assign vrf_io_read_1_addr = valu_io_read_1_addr; // @[VCore.scala 141:25]
-  assign vrf_io_read_2_valid = valu_io_read_2_valid; // @[VCore.scala 140:26]
-  assign vrf_io_read_2_addr = valu_io_read_2_addr; // @[VCore.scala 141:25]
-  assign vrf_io_read_3_valid = valu_io_read_3_valid; // @[VCore.scala 140:26]
-  assign vrf_io_read_3_addr = valu_io_read_3_addr; // @[VCore.scala 141:25]
-  assign vrf_io_read_4_valid = valu_io_read_4_valid; // @[VCore.scala 140:26]
-  assign vrf_io_read_4_addr = valu_io_read_4_addr; // @[VCore.scala 141:25]
-  assign vrf_io_read_5_valid = valu_io_read_5_valid; // @[VCore.scala 140:26]
-  assign vrf_io_read_5_addr = valu_io_read_5_addr; // @[VCore.scala 141:25]
-  assign vrf_io_read_6_valid = vst_io_read_valid | vldst_io_read_valid; // @[VCore.scala 280:45]
-  assign vrf_io_read_6_addr = vst_io_read_valid ? vst_io_read_addr : vldst_io_read_addr; // @[VCore.scala 281:29]
-  assign vrf_io_scalar_0_valid = valu_io_scalar_0_valid; // @[VCore.scala 159:28]
-  assign vrf_io_scalar_0_data = valu_io_scalar_0_data; // @[VCore.scala 160:27]
-  assign vrf_io_scalar_1_valid = valu_io_scalar_1_valid; // @[VCore.scala 159:28]
-  assign vrf_io_scalar_1_data = valu_io_scalar_1_data; // @[VCore.scala 160:27]
-  assign vrf_io_write_0_valid = valu_io_write_0_valid; // @[VCore.scala 150:27]
-  assign vrf_io_write_0_addr = valu_io_write_0_addr; // @[VCore.scala 151:26]
-  assign vrf_io_write_0_data = valu_io_write_0_data; // @[VCore.scala 152:26]
-  assign vrf_io_write_1_valid = valu_io_write_1_valid; // @[VCore.scala 150:27]
-  assign vrf_io_write_1_addr = valu_io_write_1_addr; // @[VCore.scala 151:26]
-  assign vrf_io_write_1_data = valu_io_write_1_data; // @[VCore.scala 152:26]
-  assign vrf_io_write_2_valid = valu_io_write_2_valid; // @[VCore.scala 150:27]
-  assign vrf_io_write_2_addr = valu_io_write_2_addr; // @[VCore.scala 151:26]
-  assign vrf_io_write_2_data = valu_io_write_2_data; // @[VCore.scala 152:26]
-  assign vrf_io_write_3_valid = valu_io_write_3_valid; // @[VCore.scala 150:27]
-  assign vrf_io_write_3_addr = valu_io_write_3_addr; // @[VCore.scala 151:26]
-  assign vrf_io_write_3_data = valu_io_write_3_data; // @[VCore.scala 152:26]
-  assign vrf_io_write_4_valid = vldst_io_write_valid; // @[VCore.scala 270:25]
-  assign vrf_io_write_4_addr = vldst_io_write_addr; // @[VCore.scala 271:24]
-  assign vrf_io_write_4_data = vldst_io_write_data; // @[VCore.scala 272:24]
-  assign vrf_io_write_5_valid = vld_io_write_valid; // @[VCore.scala 274:25]
-  assign vrf_io_write_5_addr = vld_io_write_addr; // @[VCore.scala 275:24]
-  assign vrf_io_write_5_data = vld_io_write_data; // @[VCore.scala 276:24]
-  assign vrf_io_whint_0_valid = valu_io_whint_0_valid; // @[VCore.scala 154:27]
-  assign vrf_io_whint_0_addr = valu_io_whint_0_addr; // @[VCore.scala 155:26]
-  assign vrf_io_whint_1_valid = valu_io_whint_1_valid; // @[VCore.scala 154:27]
-  assign vrf_io_whint_1_addr = valu_io_whint_1_addr; // @[VCore.scala 155:26]
-  assign vrf_io_whint_2_valid = valu_io_whint_2_valid; // @[VCore.scala 154:27]
-  assign vrf_io_whint_2_addr = valu_io_whint_2_addr; // @[VCore.scala 155:26]
-  assign vrf_io_whint_3_valid = valu_io_whint_3_valid; // @[VCore.scala 154:27]
-  assign vrf_io_whint_3_addr = valu_io_whint_3_addr; // @[VCore.scala 155:26]
-  assign vrf_io_conv_valid = vconv_io_out_valid; // @[VCore.scala 184:15]
-  assign vrf_io_conv_ready = vconv_io_out_ready; // @[VCore.scala 184:15]
-  assign vrf_io_conv_op_conv = vconv_io_out_op_conv; // @[VCore.scala 184:15]
-  assign vrf_io_conv_op_init = vconv_io_out_op_init; // @[VCore.scala 184:15]
-  assign vrf_io_conv_op_tran = vconv_io_out_op_tran; // @[VCore.scala 184:15]
-  assign vrf_io_conv_op_wclr = vconv_io_out_op_wclr; // @[VCore.scala 184:15]
-  assign vrf_io_conv_addr1 = vconv_io_out_addr1; // @[VCore.scala 184:15]
-  assign vrf_io_conv_addr2 = vconv_io_out_addr2; // @[VCore.scala 184:15]
-  assign vrf_io_conv_mode = vconv_io_out_mode; // @[VCore.scala 184:15]
-  assign vrf_io_conv_index = vconv_io_out_index; // @[VCore.scala 184:15]
-  assign vrf_io_conv_abias = vconv_io_out_abias; // @[VCore.scala 184:15]
-  assign vrf_io_conv_bbias = vconv_io_out_bbias; // @[VCore.scala 184:15]
-  assign vrf_io_conv_asign = vconv_io_out_asign; // @[VCore.scala 184:15]
-  assign vrf_io_conv_bsign = vconv_io_out_bsign; // @[VCore.scala 184:15]
-  assign vrf_io_vrfsb_set_valid = vdec_io_vrfsb_set_valid; // @[VCore.scala 76:17]
-  assign vrf_io_vrfsb_set_bits = vdec_io_vrfsb_set_bits; // @[VCore.scala 76:17]
+  assign vrf_io_read_0_valid = valu_io_read_0_valid; // @[VCore.scala 138:26]
+  assign vrf_io_read_0_addr = valu_io_read_0_addr; // @[VCore.scala 139:25]
+  assign vrf_io_read_1_valid = valu_io_read_1_valid; // @[VCore.scala 138:26]
+  assign vrf_io_read_1_addr = valu_io_read_1_addr; // @[VCore.scala 139:25]
+  assign vrf_io_read_2_valid = valu_io_read_2_valid; // @[VCore.scala 138:26]
+  assign vrf_io_read_2_addr = valu_io_read_2_addr; // @[VCore.scala 139:25]
+  assign vrf_io_read_3_valid = valu_io_read_3_valid; // @[VCore.scala 138:26]
+  assign vrf_io_read_3_addr = valu_io_read_3_addr; // @[VCore.scala 139:25]
+  assign vrf_io_read_4_valid = valu_io_read_4_valid; // @[VCore.scala 138:26]
+  assign vrf_io_read_4_addr = valu_io_read_4_addr; // @[VCore.scala 139:25]
+  assign vrf_io_read_5_valid = valu_io_read_5_valid; // @[VCore.scala 138:26]
+  assign vrf_io_read_5_addr = valu_io_read_5_addr; // @[VCore.scala 139:25]
+  assign vrf_io_read_6_valid = vst_io_read_valid | vldst_io_read_valid; // @[VCore.scala 278:45]
+  assign vrf_io_read_6_addr = vst_io_read_valid ? vst_io_read_addr : vldst_io_read_addr; // @[VCore.scala 279:29]
+  assign vrf_io_scalar_0_valid = valu_io_scalar_0_valid; // @[VCore.scala 157:28]
+  assign vrf_io_scalar_0_data = valu_io_scalar_0_data; // @[VCore.scala 158:27]
+  assign vrf_io_scalar_1_valid = valu_io_scalar_1_valid; // @[VCore.scala 157:28]
+  assign vrf_io_scalar_1_data = valu_io_scalar_1_data; // @[VCore.scala 158:27]
+  assign vrf_io_write_0_valid = valu_io_write_0_valid; // @[VCore.scala 148:27]
+  assign vrf_io_write_0_addr = valu_io_write_0_addr; // @[VCore.scala 149:26]
+  assign vrf_io_write_0_data = valu_io_write_0_data; // @[VCore.scala 150:26]
+  assign vrf_io_write_1_valid = valu_io_write_1_valid; // @[VCore.scala 148:27]
+  assign vrf_io_write_1_addr = valu_io_write_1_addr; // @[VCore.scala 149:26]
+  assign vrf_io_write_1_data = valu_io_write_1_data; // @[VCore.scala 150:26]
+  assign vrf_io_write_2_valid = valu_io_write_2_valid; // @[VCore.scala 148:27]
+  assign vrf_io_write_2_addr = valu_io_write_2_addr; // @[VCore.scala 149:26]
+  assign vrf_io_write_2_data = valu_io_write_2_data; // @[VCore.scala 150:26]
+  assign vrf_io_write_3_valid = valu_io_write_3_valid; // @[VCore.scala 148:27]
+  assign vrf_io_write_3_addr = valu_io_write_3_addr; // @[VCore.scala 149:26]
+  assign vrf_io_write_3_data = valu_io_write_3_data; // @[VCore.scala 150:26]
+  assign vrf_io_write_4_valid = vldst_io_write_valid; // @[VCore.scala 268:25]
+  assign vrf_io_write_4_addr = vldst_io_write_addr; // @[VCore.scala 269:24]
+  assign vrf_io_write_4_data = vldst_io_write_data; // @[VCore.scala 270:24]
+  assign vrf_io_write_5_valid = vld_io_write_valid; // @[VCore.scala 272:25]
+  assign vrf_io_write_5_addr = vld_io_write_addr; // @[VCore.scala 273:24]
+  assign vrf_io_write_5_data = vld_io_write_data; // @[VCore.scala 274:24]
+  assign vrf_io_whint_0_valid = valu_io_whint_0_valid; // @[VCore.scala 152:27]
+  assign vrf_io_whint_0_addr = valu_io_whint_0_addr; // @[VCore.scala 153:26]
+  assign vrf_io_whint_1_valid = valu_io_whint_1_valid; // @[VCore.scala 152:27]
+  assign vrf_io_whint_1_addr = valu_io_whint_1_addr; // @[VCore.scala 153:26]
+  assign vrf_io_whint_2_valid = valu_io_whint_2_valid; // @[VCore.scala 152:27]
+  assign vrf_io_whint_2_addr = valu_io_whint_2_addr; // @[VCore.scala 153:26]
+  assign vrf_io_whint_3_valid = valu_io_whint_3_valid; // @[VCore.scala 152:27]
+  assign vrf_io_whint_3_addr = valu_io_whint_3_addr; // @[VCore.scala 153:26]
+  assign vrf_io_conv_valid = vconv_io_out_valid; // @[VCore.scala 182:15]
+  assign vrf_io_conv_ready = vconv_io_out_ready; // @[VCore.scala 182:15]
+  assign vrf_io_conv_op_conv = vconv_io_out_op_conv; // @[VCore.scala 182:15]
+  assign vrf_io_conv_op_init = vconv_io_out_op_init; // @[VCore.scala 182:15]
+  assign vrf_io_conv_op_tran = vconv_io_out_op_tran; // @[VCore.scala 182:15]
+  assign vrf_io_conv_op_wclr = vconv_io_out_op_wclr; // @[VCore.scala 182:15]
+  assign vrf_io_conv_addr1 = vconv_io_out_addr1; // @[VCore.scala 182:15]
+  assign vrf_io_conv_addr2 = vconv_io_out_addr2; // @[VCore.scala 182:15]
+  assign vrf_io_conv_mode = vconv_io_out_mode; // @[VCore.scala 182:15]
+  assign vrf_io_conv_index = vconv_io_out_index; // @[VCore.scala 182:15]
+  assign vrf_io_conv_abias = vconv_io_out_abias; // @[VCore.scala 182:15]
+  assign vrf_io_conv_bbias = vconv_io_out_bbias; // @[VCore.scala 182:15]
+  assign vrf_io_conv_asign = vconv_io_out_asign; // @[VCore.scala 182:15]
+  assign vrf_io_conv_bsign = vconv_io_out_bsign; // @[VCore.scala 182:15]
+  assign vrf_io_vrfsb_set_valid = vdec_io_vrfsb_set_valid; // @[VCore.scala 74:17]
+  assign vrf_io_vrfsb_set_bits = vdec_io_vrfsb_set_bits; // @[VCore.scala 74:17]
   always @(posedge clock) begin
     `ifndef SYNTHESIS
     `ifdef STOP_COND
       if (`STOP_COND) begin
     `endif
         if (~reset & ~_T_7) begin
-          $fatal; // @[VCore.scala 71:9]
+          $fatal; // @[VCore.scala 69:9]
         end
     `ifdef STOP_COND
       end
@@ -123292,7 +113718,7 @@
     `endif
         if (~reset & ~_T_7) begin
           $fwrite(32'h80000002,
-            "Assertion failed\n    at VCore.scala:71 assert(PopCount(Cat(vst.io.read.valid && vst.io.read.ready,\n"); // @[VCore.scala 71:9]
+            "Assertion failed\n    at VCore.scala:69 assert(PopCount(Cat(vst.io.read.valid && vst.io.read.ready,\n"); // @[VCore.scala 69:9]
         end
     `ifdef PRINTF_COND
       end
@@ -123303,7 +113729,7 @@
       if (`STOP_COND) begin
     `endif
         if (_T_9 & ~(~(vdec_io_in_valid & ~vdec_io_in_ready))) begin
-          $fatal; // @[VCore.scala 82:9]
+          $fatal; // @[VCore.scala 80:9]
         end
     `ifdef STOP_COND
       end
@@ -123315,7 +113741,7 @@
     `endif
         if (_T_9 & ~(~(vdec_io_in_valid & ~vdec_io_in_ready))) begin
           $fwrite(32'h80000002,
-            "Assertion failed\n    at VCore.scala:82 assert(!(vdec.io.in.valid && !vdec.io.in.ready))\n"); // @[VCore.scala 82:9]
+            "Assertion failed\n    at VCore.scala:80 assert(!(vdec.io.in.valid && !vdec.io.in.ready))\n"); // @[VCore.scala 80:9]
         end
     `ifdef PRINTF_COND
       end
@@ -123651,22 +114077,22 @@
   wire  score_io_vcore_vinst_0_ready; // @[SCore.scala 9:18]
   wire [4:0] score_io_vcore_vinst_0_addr; // @[SCore.scala 9:18]
   wire [31:0] score_io_vcore_vinst_0_inst; // @[SCore.scala 9:18]
-  wire [5:0] score_io_vcore_vinst_0_op; // @[SCore.scala 9:18]
+  wire [4:0] score_io_vcore_vinst_0_op; // @[SCore.scala 9:18]
   wire  score_io_vcore_vinst_1_valid; // @[SCore.scala 9:18]
   wire  score_io_vcore_vinst_1_ready; // @[SCore.scala 9:18]
   wire [4:0] score_io_vcore_vinst_1_addr; // @[SCore.scala 9:18]
   wire [31:0] score_io_vcore_vinst_1_inst; // @[SCore.scala 9:18]
-  wire [5:0] score_io_vcore_vinst_1_op; // @[SCore.scala 9:18]
+  wire [4:0] score_io_vcore_vinst_1_op; // @[SCore.scala 9:18]
   wire  score_io_vcore_vinst_2_valid; // @[SCore.scala 9:18]
   wire  score_io_vcore_vinst_2_ready; // @[SCore.scala 9:18]
   wire [4:0] score_io_vcore_vinst_2_addr; // @[SCore.scala 9:18]
   wire [31:0] score_io_vcore_vinst_2_inst; // @[SCore.scala 9:18]
-  wire [5:0] score_io_vcore_vinst_2_op; // @[SCore.scala 9:18]
+  wire [4:0] score_io_vcore_vinst_2_op; // @[SCore.scala 9:18]
   wire  score_io_vcore_vinst_3_valid; // @[SCore.scala 9:18]
   wire  score_io_vcore_vinst_3_ready; // @[SCore.scala 9:18]
   wire [4:0] score_io_vcore_vinst_3_addr; // @[SCore.scala 9:18]
   wire [31:0] score_io_vcore_vinst_3_inst; // @[SCore.scala 9:18]
-  wire [5:0] score_io_vcore_vinst_3_op; // @[SCore.scala 9:18]
+  wire [4:0] score_io_vcore_vinst_3_op; // @[SCore.scala 9:18]
   wire [31:0] score_io_vcore_rs_0_data; // @[SCore.scala 9:18]
   wire [31:0] score_io_vcore_rs_1_data; // @[SCore.scala 9:18]
   wire [31:0] score_io_vcore_rs_2_data; // @[SCore.scala 9:18]
@@ -123687,10 +114113,6 @@
   wire  score_io_vcore_rd_3_valid; // @[SCore.scala 9:18]
   wire [4:0] score_io_vcore_rd_3_addr; // @[SCore.scala 9:18]
   wire [31:0] score_io_vcore_rd_3_data; // @[SCore.scala 9:18]
-  wire [31:0] score_io_vcore_fs_0_data; // @[SCore.scala 9:18]
-  wire [31:0] score_io_vcore_fs_1_data; // @[SCore.scala 9:18]
-  wire [31:0] score_io_vcore_fs_2_data; // @[SCore.scala 9:18]
-  wire [31:0] score_io_vcore_fs_3_data; // @[SCore.scala 9:18]
   wire  score_io_vcore_mactive; // @[SCore.scala 9:18]
   wire  score_io_vcore_undef; // @[SCore.scala 9:18]
   wire  score_io_iflush_valid; // @[SCore.scala 9:18]
@@ -123706,22 +114128,22 @@
   wire  vcore_io_score_vinst_0_ready; // @[VCore.scala 9:18]
   wire [4:0] vcore_io_score_vinst_0_addr; // @[VCore.scala 9:18]
   wire [31:0] vcore_io_score_vinst_0_inst; // @[VCore.scala 9:18]
-  wire [5:0] vcore_io_score_vinst_0_op; // @[VCore.scala 9:18]
+  wire [4:0] vcore_io_score_vinst_0_op; // @[VCore.scala 9:18]
   wire  vcore_io_score_vinst_1_valid; // @[VCore.scala 9:18]
   wire  vcore_io_score_vinst_1_ready; // @[VCore.scala 9:18]
   wire [4:0] vcore_io_score_vinst_1_addr; // @[VCore.scala 9:18]
   wire [31:0] vcore_io_score_vinst_1_inst; // @[VCore.scala 9:18]
-  wire [5:0] vcore_io_score_vinst_1_op; // @[VCore.scala 9:18]
+  wire [4:0] vcore_io_score_vinst_1_op; // @[VCore.scala 9:18]
   wire  vcore_io_score_vinst_2_valid; // @[VCore.scala 9:18]
   wire  vcore_io_score_vinst_2_ready; // @[VCore.scala 9:18]
   wire [4:0] vcore_io_score_vinst_2_addr; // @[VCore.scala 9:18]
   wire [31:0] vcore_io_score_vinst_2_inst; // @[VCore.scala 9:18]
-  wire [5:0] vcore_io_score_vinst_2_op; // @[VCore.scala 9:18]
+  wire [4:0] vcore_io_score_vinst_2_op; // @[VCore.scala 9:18]
   wire  vcore_io_score_vinst_3_valid; // @[VCore.scala 9:18]
   wire  vcore_io_score_vinst_3_ready; // @[VCore.scala 9:18]
   wire [4:0] vcore_io_score_vinst_3_addr; // @[VCore.scala 9:18]
   wire [31:0] vcore_io_score_vinst_3_inst; // @[VCore.scala 9:18]
-  wire [5:0] vcore_io_score_vinst_3_op; // @[VCore.scala 9:18]
+  wire [4:0] vcore_io_score_vinst_3_op; // @[VCore.scala 9:18]
   wire [31:0] vcore_io_score_rs_0_data; // @[VCore.scala 9:18]
   wire [31:0] vcore_io_score_rs_1_data; // @[VCore.scala 9:18]
   wire [31:0] vcore_io_score_rs_2_data; // @[VCore.scala 9:18]
@@ -123742,10 +114164,6 @@
   wire  vcore_io_score_rd_3_valid; // @[VCore.scala 9:18]
   wire [4:0] vcore_io_score_rd_3_addr; // @[VCore.scala 9:18]
   wire [31:0] vcore_io_score_rd_3_data; // @[VCore.scala 9:18]
-  wire [31:0] vcore_io_score_fs_0_data; // @[VCore.scala 9:18]
-  wire [31:0] vcore_io_score_fs_1_data; // @[VCore.scala 9:18]
-  wire [31:0] vcore_io_score_fs_2_data; // @[VCore.scala 9:18]
-  wire [31:0] vcore_io_score_fs_3_data; // @[VCore.scala 9:18]
   wire  vcore_io_score_mactive; // @[VCore.scala 9:18]
   wire  vcore_io_score_undef; // @[VCore.scala 9:18]
   wire  vcore_io_dbus_valid; // @[VCore.scala 9:18]
@@ -123891,10 +114309,6 @@
     .io_vcore_rd_3_valid(score_io_vcore_rd_3_valid),
     .io_vcore_rd_3_addr(score_io_vcore_rd_3_addr),
     .io_vcore_rd_3_data(score_io_vcore_rd_3_data),
-    .io_vcore_fs_0_data(score_io_vcore_fs_0_data),
-    .io_vcore_fs_1_data(score_io_vcore_fs_1_data),
-    .io_vcore_fs_2_data(score_io_vcore_fs_2_data),
-    .io_vcore_fs_3_data(score_io_vcore_fs_3_data),
     .io_vcore_mactive(score_io_vcore_mactive),
     .io_vcore_undef(score_io_vcore_undef),
     .io_iflush_valid(score_io_iflush_valid),
@@ -123948,10 +114362,6 @@
     .io_score_rd_3_valid(vcore_io_score_rd_3_valid),
     .io_score_rd_3_addr(vcore_io_score_rd_3_addr),
     .io_score_rd_3_data(vcore_io_score_rd_3_data),
-    .io_score_fs_0_data(vcore_io_score_fs_0_data),
-    .io_score_fs_1_data(vcore_io_score_fs_1_data),
-    .io_score_fs_2_data(vcore_io_score_fs_2_data),
-    .io_score_fs_3_data(vcore_io_score_fs_3_data),
     .io_score_mactive(vcore_io_score_mactive),
     .io_score_undef(vcore_io_score_undef),
     .io_dbus_valid(vcore_io_dbus_valid),
@@ -124122,10 +114532,6 @@
   assign vcore_io_score_rs_5_data = score_io_vcore_rs_5_data; // @[Core.scala 48:18]
   assign vcore_io_score_rs_6_data = score_io_vcore_rs_6_data; // @[Core.scala 48:18]
   assign vcore_io_score_rs_7_data = score_io_vcore_rs_7_data; // @[Core.scala 48:18]
-  assign vcore_io_score_fs_0_data = score_io_vcore_fs_0_data; // @[Core.scala 48:18]
-  assign vcore_io_score_fs_1_data = score_io_vcore_fs_1_data; // @[Core.scala 48:18]
-  assign vcore_io_score_fs_2_data = score_io_vcore_fs_2_data; // @[Core.scala 48:18]
-  assign vcore_io_score_fs_3_data = score_io_vcore_fs_3_data; // @[Core.scala 48:18]
   assign vcore_io_dbus_ready = dbusmux_io_vcore_ready; // @[Core.scala 55:20]
   assign vcore_io_dbus_rdata = dbusmux_io_vcore_rdata; // @[Core.scala 55:20]
   assign vcore_io_ld_addr_ready = io_axi0_read_addr_ready; // @[Core.scala 67:17]
@@ -206281,7 +196687,7 @@
 `endif
 `endif // SYNTHESIS
 endmodule
-module Slice_9(
+module Slice_8(
   input         clock,
   input         reset,
   output        io_in_ready,
@@ -206437,7 +196843,7 @@
 `endif
 `endif // SYNTHESIS
 endmodule
-module Slice_10(
+module Slice_9(
   input          clock,
   input          reset,
   output         io_in_ready,
@@ -206574,7 +196980,7 @@
 `endif
 `endif // SYNTHESIS
 endmodule
-module Slice_11(
+module Slice_10(
   input          clock,
   input          reset,
   output         io_in_ready,
@@ -206878,7 +197284,7 @@
   wire [1:0] _T_127 = _T_122[0] + _T_122[1]; // @[Bitwise.scala 48:55]
   wire [1:0] _T_129 = _T_122[2] + _T_122[3]; // @[Bitwise.scala 48:55]
   wire [2:0] _T_131 = _T_127 + _T_129; // @[Bitwise.scala 48:55]
-  Slice_9 cctrl ( // @[Slice.scala 9:11]
+  Slice_8 cctrl ( // @[Slice.scala 9:11]
     .clock(cctrl_clock),
     .reset(cctrl_reset),
     .io_in_ready(cctrl_io_in_ready),
@@ -206892,7 +197298,7 @@
     .io_out_bits_caddr(cctrl_io_out_bits_caddr),
     .io_out_bits_cid(cctrl_io_out_bits_cid)
   );
-  Slice_10 wdata ( // @[Slice.scala 9:11]
+  Slice_9 wdata ( // @[Slice.scala 9:11]
     .clock(wdata_clock),
     .reset(wdata_reset),
     .io_in_ready(wdata_io_in_ready),
@@ -206904,7 +197310,7 @@
     .io_out_bits_wdata(wdata_io_out_bits_wdata),
     .io_out_bits_wmask(wdata_io_out_bits_wmask)
   );
-  Slice_11 rdata ( // @[Slice.scala 9:11]
+  Slice_10 rdata ( // @[Slice.scala 9:11]
     .clock(rdata_clock),
     .reset(rdata_reset),
     .io_in_ready(rdata_io_in_ready),
diff --git a/sw/device/tests/BUILD b/sw/device/tests/BUILD
index 0bee4f2..48a45e5 100644
--- a/sw/device/tests/BUILD
+++ b/sw/device/tests/BUILD
@@ -852,15 +852,13 @@
 
 matcha_dv_test(
     name = "sensor_ctrl_wakeup_test",
-    srcs = ["@lowrisc_opentitan//sw/device/tests:sensor_ctrl_wakeup.c"],
+    srcs = ["sensor_ctrl_wakeup.c"],
     deps = [
-        ":test_dv_lib_opentitan",
-        "//hw/top_matcha/ip/sensor_ctrl/data:sensor_ctrl_regs",
+        ":test_dv_lib",
         "//sw/device/lib/dif:rv_plic_sec",
-        "@lowrisc_opentitan//sw/device/lib/arch:device",
+        "//sw/device/lib/testing:isr_testutils",
         "@lowrisc_opentitan//sw/device/lib/dif:pwrmgr",
         "@lowrisc_opentitan//sw/device/lib/dif:sensor_ctrl",
-        "@lowrisc_opentitan//sw/device/lib/testing:isr_testutils",
         "@lowrisc_opentitan//sw/device/lib/testing:pwrmgr_testutils",
         "@lowrisc_opentitan//sw/device/lib/testing:rv_plic_testutils",
     ],
diff --git a/sw/device/tests/sensor_ctrl_wakeup.c b/sw/device/tests/sensor_ctrl_wakeup.c
new file mode 100644
index 0000000..d1529b0
--- /dev/null
+++ b/sw/device/tests/sensor_ctrl_wakeup.c
@@ -0,0 +1,133 @@
+// Copyright 2023 Google LLC.
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+
+#include "hw/top_matcha/sw/autogen/top_matcha.h"
+#include "sensor_ctrl_regs.h"  // Generated.
+#include "sw/device/lib/base/mmio.h"
+#include "sw/device/lib/dif/dif_pwrmgr.h"
+#include "sw/device/lib/dif/dif_rv_plic.h"
+#include "sw/device/lib/dif/dif_sensor_ctrl.h"
+#include "sw/device/lib/runtime/ibex.h"
+#include "sw/device/lib/runtime/irq.h"
+#include "sw/device/lib/runtime/log.h"
+#include "sw/device/lib/testing/autogen/isr_testutils.h"
+#include "sw/device/lib/testing/pwrmgr_testutils.h"
+#include "sw/device/lib/testing/rv_plic_testutils.h"
+#include "sw/device/lib/testing/test_framework/check.h"
+#include "sw/device/lib/testing/test_framework/ottf_main.h"
+
+OTTF_DEFINE_TEST_CONFIG();
+
+static dif_pwrmgr_t pwrmgr;
+static dif_rv_plic_t plic;
+static plic_isr_ctx_t plic_ctx = {.rv_plic = &plic,
+                                  .hart_id = kTopMatchaPlicTargetIbex0};
+
+static pwrmgr_isr_ctx_t pwrmgr_isr_ctx = {
+    .pwrmgr = &pwrmgr,
+    .plic_pwrmgr_start_irq_id = kTopMatchaPlicIrqIdPwrmgrAonWakeup,
+    .expected_irq = kDifPwrmgrIrqWakeup,
+    .is_only_irq = true};
+
+static bool get_wakeup_status(void) {
+  dif_pwrmgr_request_sources_t wake_req = -1;
+  CHECK_DIF_OK(dif_pwrmgr_get_current_request_sources(
+      &pwrmgr, kDifPwrmgrReqTypeWakeup, &wake_req));
+  return (wake_req > 0);
+}
+
+/**
+ * External interrupt handler.
+ */
+void ottf_external_isr(void) {
+  dif_pwrmgr_irq_t irq_id;
+  top_matcha_plic_peripheral_t peripheral;
+
+  isr_testutils_pwrmgr_isr(plic_ctx, pwrmgr_isr_ctx, &peripheral, &irq_id);
+
+  // Check that both the peripheral and the irq id is correct
+  CHECK(peripheral == kTopMatchaPlicPeripheralPwrmgrAon,
+        "IRQ peripheral: %d is incorrect", peripheral);
+  CHECK(irq_id == kDifPwrmgrIrqWakeup, "IRQ ID: %d is incorrect", irq_id);
+}
+
+bool test_main(void) {
+  dif_sensor_ctrl_t sensor_ctrl;
+
+  // Enable global and external IRQ at Ibex.
+  irq_global_ctrl(true);
+  irq_external_ctrl(true);
+
+  // Initialize the PLIC.
+  mmio_region_t plic_base_addr =
+      mmio_region_from_addr(TOP_MATCHA_RV_PLIC_BASE_ADDR);
+  CHECK_DIF_OK(dif_rv_plic_init(plic_base_addr, &plic));
+
+  // Initialize pwrmgr
+  CHECK_DIF_OK(dif_pwrmgr_init(
+      mmio_region_from_addr(TOP_MATCHA_PWRMGR_AON_BASE_ADDR), &pwrmgr));
+
+  // Initialize sensor_ctrl
+  CHECK_DIF_OK(dif_sensor_ctrl_init(
+      mmio_region_from_addr(TOP_MATCHA_SENSOR_CTRL_BASE_ADDR), &sensor_ctrl));
+
+  // Enable all the AON interrupts used in this test.
+  rv_plic_testutils_irq_range_enable(&plic, kTopMatchaPlicTargetIbex0,
+                                     kTopMatchaPlicIrqIdPwrmgrAonWakeup,
+                                     kTopMatchaPlicIrqIdPwrmgrAonWakeup);
+
+  // Enable pwrmgr interrupt
+  CHECK_DIF_OK(dif_pwrmgr_irq_set_enabled(&pwrmgr, 0, kDifToggleEnabled));
+
+  // Capture the number of events to test
+  uint32_t sensor_ctrl_events = SENSOR_CTRL_PARAM_NUM_ALERT_EVENTS;
+
+  dif_pwrmgr_domain_config_t sleep_config =
+      kDifPwrmgrDomainOptionMainPowerInLowPower;
+
+  for (size_t i = 0; i < sensor_ctrl_events; ++i) {
+    LOG_INFO("Testing sensor_ctrl event %d", i);
+
+    // Setup event trigger
+    CHECK_DIF_OK(dif_sensor_ctrl_set_ast_event_trigger(&sensor_ctrl, i,
+                                                       kDifToggleEnabled));
+
+    // Normal sleep.
+    pwrmgr_testutils_enable_low_power(&pwrmgr, kDifPwrmgrWakeupRequestSourceSix,
+                                      sleep_config);
+
+    // Enter low power mode.
+    LOG_INFO("Issue WFI to enter sleep");
+    wait_for_interrupt();
+
+    // Wakeup from sleep.
+    LOG_INFO("Wake from sleep");
+
+    dif_sensor_ctrl_events_t events;
+    CHECK_DIF_OK(dif_sensor_ctrl_get_recov_events(&sensor_ctrl, &events));
+
+    if (events != (1 << i)) {
+      LOG_ERROR("Recoverable event 0x%x does not match expectation %d", events,
+                i);
+    }
+
+    // clear event trigger
+    CHECK_DIF_OK(dif_sensor_ctrl_set_ast_event_trigger(&sensor_ctrl, i,
+                                                       kDifToggleDisabled));
+
+    // since there is synchronization delay to trigger clearing and actual event
+    // de-assertion, clear and poll until it is finished before moving on
+    while (events) {
+      CHECK_DIF_OK(dif_sensor_ctrl_clear_recov_event(&sensor_ctrl, i));
+      CHECK_DIF_OK(dif_sensor_ctrl_get_recov_events(&sensor_ctrl, &events));
+    }
+
+    // ensure the de-asserted events have cleared from the wakeup pipeline
+    // within 30us
+    IBEX_SPIN_FOR(!get_wakeup_status(), 30);
+  }
+
+  return true;
+}