diff --git a/BUILD.bazel b/BUILD.bazel
index 65b32d7..e9d9ac9 100644
--- a/BUILD.bazel
+++ b/BUILD.bazel
@@ -13,8 +13,6 @@
         "@lowrisc_opentitan//hw/ip:BUILD",
         "@lowrisc_opentitan//hw/lint:BUILD",
         "@lowrisc_opentitan//hw/vendor:BUILD",
-        # Place the following file to make compilation works
-        "//hw:check_tool_requirements.core",
         "@axi2sramcrs//:BUILD",
         "@isp_yocto//:BUILD",
     ] + select({
diff --git a/hw/BUILD b/hw/BUILD
index cd7f31a..a2c652e 100644
--- a/hw/BUILD
+++ b/hw/BUILD
@@ -4,7 +4,7 @@
 # SPDX-License-Identifier: Apache-2.0
 
 load("@bazel_skylib//rules:common_settings.bzl", "string_list_flag")
-load("@lowrisc_opentitan//rules:fusesoc.bzl", "fusesoc_build")
+load("//rules:matcha.bzl", "target_fusesoc_build")
 
 package(default_visibility = ["//visibility:public"])
 
@@ -18,31 +18,29 @@
     ],
 )
 
-fusesoc_build(
-    name = "verilator_real",
-    srcs = [
-        ":all_files",
-        "//hw/top_matcha/dv/verilator:all_files",
-    ],
-    cores = [
-        "//:cores",
-    ],
-    data = ["@lowrisc_opentitan//hw/ip/otbn:all_files"],
-    make_options = ":make_options",
+target_fusesoc_build(
+    name = "matcha",
     output_groups = {
         "binary": ["sim-verilator/Vchip_sim_tb"],
     },
-    systems = ["lowrisc:dv:chip_verilator_sim"],
-    tags = [
-        "manual",
-        "verilator",
-    ],
-    target = "sim",
+)
+
+target_fusesoc_build(
+    name = "sencha",
+    output_groups = {
+        "binary": ["sim-verilator/Vsencha_sim_tb"],
+    },
 )
 
 filegroup(
-    name = "verilator_bin",
-    srcs = [":verilator_real"],
+    name = "matcha_verilator_bin",
+    srcs = [":matcha_verilator_real"],
+    output_group = "binary",
+)
+
+filegroup(
+    name = "sencha_verilator_bin",
+    srcs = [":sencha_verilator_real"],
     output_group = "binary",
 )
 
@@ -69,10 +67,20 @@
 )
 
 alias(
-    name = "verilator",
+    name = "matcha_verilator",
     actual = select({
         ":disable_verilator_build": ":verilator_stub",
-        "//conditions:default": ":verilator_bin",
+        "//conditions:default": ":matcha_verilator_bin",
+    }),
+    tags = ["verilator"],
+    visibility = ["//visibility:public"],
+)
+
+alias(
+    name = "sencha_verilator",
+    actual = select({
+        ":disable_verilator_build": ":verilator_stub",
+        "//conditions:default": ":sencha_verilator_bin",
     }),
     tags = ["verilator"],
     visibility = ["//visibility:public"],
@@ -82,7 +90,6 @@
     name = "all_files",
     srcs = glob(["**"]) + [
         "//hw/ip:all_files",
-        "//hw/top_matcha:all_files",
         "@lowrisc_opentitan//hw/dv:all_files",
     ] + select({
         "//rules:airgapped_env": [
diff --git a/hw/bitstream/vivado/BUILD b/hw/bitstream/vivado/BUILD
index 8c5b5f2..437241b 100644
--- a/hw/bitstream/vivado/BUILD
+++ b/hw/bitstream/vivado/BUILD
@@ -37,7 +37,11 @@
         _FPGA_NEXUS_TESTROM,
         _FPGA_NEXUS_OTP_RMA,
     ],
-    cores = ["//:cores"],
+    cores = [
+        "//:cores",
+        "//hw/ip:BUILD",
+        "//hw/top_matcha:BUILD"
+    ],
     data = ["@lowrisc_opentitan//hw/ip/otbn:all_files"],
     flags = [
         "--BootRomInitFile=" + _FPGA_NEXUS_TESTROM_PATH,
diff --git a/hw/dv/tools/dvsim/fusesoc.hjson b/hw/dv/tools/dvsim/fusesoc.hjson
index 80650b1..9f75086 100644
--- a/hw/dv/tools/dvsim/fusesoc.hjson
+++ b/hw/dv/tools/dvsim/fusesoc.hjson
@@ -22,7 +22,9 @@
           "--cores-root {titan_root}/hw/vendor",
           "--cores-root {proj_root}/../ip/isp/ispyocto",
           "--cores-root {proj_root}/../ip/isp/axi2sramcrs",
-          "--cores-root {proj_root}/hw"]
+          "--cores-root {proj_root}/hw/dv",
+          "--cores-root {proj_root}/hw/ip",
+          "--cores-root {proj_root}/hw/top_matcha"]
   sv_flist_gen_dir:   "{build_dir}/sim-vcs"
   sv_flist:           "{sv_flist_gen_dir}/{fusesoc_core_}.scr"
   sv_flist_gen_flags: ["--flag=fileset_{design_level}"]
diff --git a/hw/ip/BUILD b/hw/ip/BUILD
index bf8cea7..36f4d20 100644
--- a/hw/ip/BUILD
+++ b/hw/ip/BUILD
@@ -12,6 +12,7 @@
     srcs = glob(["**"]) + [
         "//hw/ip/dma:all_files",
         "//hw/ip/i2s:all_files",
+        "//hw/ip/isp_wrapper/data:all_files",
         "//hw/ip/ml_top/data:all_files",
         "//hw/ip/rv_core_smc:all_files",
         "//hw/ip/smc_ctrl:all_files",
@@ -25,6 +26,7 @@
         "//hw/ip/cam_ctrl/data:cam_ctrl.hjson",
         "//hw/ip/dma/data:dma.hjson",
         "//hw/ip/i2s/data:i2s.hjson",
+        "//hw/ip/isp_wrapper/data:isp_wrapper.hjson",
         "//hw/ip/ml_top/data:ml_top.hjson",
         "//hw/ip/rv_core_smc/data:rv_core_smc.hjson",
         "//hw/ip/smc_ctrl/data:smc_ctrl.hjson",
diff --git a/hw/top_matcha/ip/ahb/headers.core b/hw/ip/ahb/headers.core
similarity index 100%
rename from hw/top_matcha/ip/ahb/headers.core
rename to hw/ip/ahb/headers.core
diff --git a/hw/top_matcha/ip/ahb/rtl/ahb_pkg.sv b/hw/ip/ahb/rtl/ahb_pkg.sv
similarity index 100%
rename from hw/top_matcha/ip/ahb/rtl/ahb_pkg.sv
rename to hw/ip/ahb/rtl/ahb_pkg.sv
diff --git a/hw/top_matcha/ip/axi/headers.core b/hw/ip/axi/headers.core
similarity index 100%
rename from hw/top_matcha/ip/axi/headers.core
rename to hw/ip/axi/headers.core
diff --git a/hw/top_matcha/ip/axi/rtl/axi_pkg.sv b/hw/ip/axi/rtl/axi_pkg.sv
similarity index 100%
rename from hw/top_matcha/ip/axi/rtl/axi_pkg.sv
rename to hw/ip/axi/rtl/axi_pkg.sv
diff --git a/hw/top_matcha/ip/isp_wrapper/data/BUILD b/hw/ip/isp_wrapper/data/BUILD
similarity index 100%
rename from hw/top_matcha/ip/isp_wrapper/data/BUILD
rename to hw/ip/isp_wrapper/data/BUILD
diff --git a/hw/top_matcha/ip/isp_wrapper/data/isp_wrapper.hjson b/hw/ip/isp_wrapper/data/isp_wrapper.hjson
similarity index 100%
rename from hw/top_matcha/ip/isp_wrapper/data/isp_wrapper.hjson
rename to hw/ip/isp_wrapper/data/isp_wrapper.hjson
diff --git a/hw/top_matcha/ip/isp_wrapper/isp_wrapper.core b/hw/ip/isp_wrapper/isp_wrapper.core
similarity index 100%
rename from hw/top_matcha/ip/isp_wrapper/isp_wrapper.core
rename to hw/ip/isp_wrapper/isp_wrapper.core
diff --git a/hw/top_matcha/ip/isp_wrapper/lint/isp_wrapper.vlt b/hw/ip/isp_wrapper/lint/isp_wrapper.vlt
similarity index 100%
rename from hw/top_matcha/ip/isp_wrapper/lint/isp_wrapper.vlt
rename to hw/ip/isp_wrapper/lint/isp_wrapper.vlt
diff --git a/hw/top_matcha/ip/isp_wrapper/lint/isp_wrapper.waiver b/hw/ip/isp_wrapper/lint/isp_wrapper.waiver
similarity index 100%
rename from hw/top_matcha/ip/isp_wrapper/lint/isp_wrapper.waiver
rename to hw/ip/isp_wrapper/lint/isp_wrapper.waiver
diff --git a/hw/top_matcha/ip/isp_wrapper/rtl/isp_wrapper.sv b/hw/ip/isp_wrapper/rtl/isp_wrapper.sv
similarity index 100%
rename from hw/top_matcha/ip/isp_wrapper/rtl/isp_wrapper.sv
rename to hw/ip/isp_wrapper/rtl/isp_wrapper.sv
diff --git a/hw/top_matcha/ip/isp_wrapper/rtl/isp_wrapper_reg_pkg.sv b/hw/ip/isp_wrapper/rtl/isp_wrapper_reg_pkg.sv
similarity index 100%
rename from hw/top_matcha/ip/isp_wrapper/rtl/isp_wrapper_reg_pkg.sv
rename to hw/ip/isp_wrapper/rtl/isp_wrapper_reg_pkg.sv
diff --git a/hw/top_matcha/ip/isp_wrapper/rtl/isp_wrapper_reg_top.sv b/hw/ip/isp_wrapper/rtl/isp_wrapper_reg_top.sv
similarity index 100%
rename from hw/top_matcha/ip/isp_wrapper/rtl/isp_wrapper_reg_top.sv
rename to hw/ip/isp_wrapper/rtl/isp_wrapper_reg_top.sv
diff --git a/hw/top_matcha/ip/tlul2ahblite/lint/tlul2ahblite.vlt b/hw/ip/tlul2ahblite/lint/tlul2ahblite.vlt
similarity index 100%
rename from hw/top_matcha/ip/tlul2ahblite/lint/tlul2ahblite.vlt
rename to hw/ip/tlul2ahblite/lint/tlul2ahblite.vlt
diff --git a/hw/top_matcha/ip/tlul2ahblite/lint/tlul2ahblite.waiver b/hw/ip/tlul2ahblite/lint/tlul2ahblite.waiver
similarity index 100%
rename from hw/top_matcha/ip/tlul2ahblite/lint/tlul2ahblite.waiver
rename to hw/ip/tlul2ahblite/lint/tlul2ahblite.waiver
diff --git a/hw/top_matcha/ip/tlul2ahblite/rtl/ahblite_enc.v b/hw/ip/tlul2ahblite/rtl/ahblite_enc.v
similarity index 100%
rename from hw/top_matcha/ip/tlul2ahblite/rtl/ahblite_enc.v
rename to hw/ip/tlul2ahblite/rtl/ahblite_enc.v
diff --git a/hw/top_matcha/ip/tlul2ahblite/rtl/tlul2ahblite.v b/hw/ip/tlul2ahblite/rtl/tlul2ahblite.v
similarity index 100%
rename from hw/top_matcha/ip/tlul2ahblite/rtl/tlul2ahblite.v
rename to hw/ip/tlul2ahblite/rtl/tlul2ahblite.v
diff --git a/hw/top_matcha/ip/tlul2ahblite/rtl/tlul_dec.v b/hw/ip/tlul2ahblite/rtl/tlul_dec.v
similarity index 100%
rename from hw/top_matcha/ip/tlul2ahblite/rtl/tlul_dec.v
rename to hw/ip/tlul2ahblite/rtl/tlul_dec.v
diff --git a/hw/top_matcha/ip/tlul2ahblite/tlul2ahblite.core b/hw/ip/tlul2ahblite/tlul2ahblite.core
similarity index 100%
rename from hw/top_matcha/ip/tlul2ahblite/tlul2ahblite.core
rename to hw/ip/tlul2ahblite/tlul2ahblite.core
diff --git a/hw/top_matcha/ip/tlul2axi4/rtl/axi_enc.v b/hw/ip/tlul2axi4/rtl/axi_enc.v
similarity index 100%
rename from hw/top_matcha/ip/tlul2axi4/rtl/axi_enc.v
rename to hw/ip/tlul2axi4/rtl/axi_enc.v
diff --git a/hw/top_matcha/ip/tlul2axi4/rtl/tlul2axi.v b/hw/ip/tlul2axi4/rtl/tlul2axi.v
similarity index 100%
rename from hw/top_matcha/ip/tlul2axi4/rtl/tlul2axi.v
rename to hw/ip/tlul2axi4/rtl/tlul2axi.v
diff --git a/hw/top_matcha/ip/tlul2axi4/rtl/tlul_dec.v b/hw/ip/tlul2axi4/rtl/tlul_dec.v
similarity index 100%
rename from hw/top_matcha/ip/tlul2axi4/rtl/tlul_dec.v
rename to hw/ip/tlul2axi4/rtl/tlul_dec.v
diff --git a/hw/top_matcha/dv/verilator/chip_sim.core b/hw/top_matcha/dv/verilator/chip_sim.core
index 16a53ea..7806dd4 100644
--- a/hw/top_matcha/dv/verilator/chip_sim.core
+++ b/hw/top_matcha/dv/verilator/chip_sim.core
@@ -3,7 +3,7 @@
 # Copyright lowRISC contributors
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
-name: "lowrisc:dv:chip_verilator_sim:0.1"
+name: "lowrisc:dv:matcha_verilator_sim:0.1"
 description: "Matcha toplevel for simulation with Verilator"
 filesets:
   files_sim_verilator:
diff --git a/hw/top_matcha/ip/BUILD b/hw/top_matcha/ip/BUILD
index 1de1728..0c5555b 100644
--- a/hw/top_matcha/ip/BUILD
+++ b/hw/top_matcha/ip/BUILD
@@ -13,7 +13,6 @@
         "//hw/top_matcha/ip/ast:all_files",
         "//hw/top_matcha/ip/clkmgr:all_files",
         "//hw/top_matcha/ip/flash_ctrl:all_files",
-        "//hw/top_matcha/ip/isp_wrapper/data:all_files",
         "//hw/top_matcha/ip/padctrl:all_files",
         "//hw/top_matcha/ip/pinmux:all_files",
         "//hw/top_matcha/ip/pwrmgr:all_files",
@@ -28,7 +27,6 @@
         "//hw/top_matcha/ip/ast/data:ast.hjson",
         "//hw/top_matcha/ip/clkmgr/data/autogen:clkmgr.hjson",
         "//hw/top_matcha/ip/flash_ctrl/data/autogen:flash_ctrl.hjson",
-        "//hw/top_matcha/ip/isp_wrapper/data:isp_wrapper.hjson",
         "//hw/top_matcha/ip/pwrmgr/data/autogen:pwrmgr.hjson",
         "//hw/top_matcha/ip/rstmgr/data/autogen:rstmgr.hjson",
         "//hw/top_matcha/ip/sensor_ctrl/data:sensor_ctrl.hjson",
diff --git a/rules/matcha.bzl b/rules/matcha.bzl
index 1166ccb..5527117 100644
--- a/rules/matcha.bzl
+++ b/rules/matcha.bzl
@@ -4,13 +4,9 @@
 
 """Rules to build Matcha for the RiscV target"""
 
-load("@rules_pkg//:pkg.bzl", "pkg_tar")
 load(
-    "@lowrisc_opentitan//rules:rv.bzl",
-    "rv_rule",
-    _OPENTITAN_CPU = "OPENTITAN_CPU",
-    _OPENTITAN_PLATFORM = "OPENTITAN_PLATFORM",
-    _opentitan_transition = "opentitan_transition",
+    "@lowrisc_opentitan//rules:fusesoc.bzl",
+    "fusesoc_build",
 )
 load(
     "@lowrisc_opentitan//rules:opentitan.bzl",
@@ -19,7 +15,15 @@
     "scramble_flash_vmem",
     "sign_bin",
 )
+load(
+    "@lowrisc_opentitan//rules:rv.bzl",
+    "rv_rule",
+    _OPENTITAN_CPU = "OPENTITAN_CPU",
+    _OPENTITAN_PLATFORM = "OPENTITAN_PLATFORM",
+    _opentitan_transition = "opentitan_transition",
+)
 load("@rules_cc//cc:find_cc_toolchain.bzl", "find_cc_toolchain")
+load("@rules_pkg//:pkg.bzl", "pkg_tar")
 
 # Re-exports of names from transition.bzl; many files in the repo use opentitan.bzl
 # to get to them.
@@ -119,6 +123,7 @@
 )
 
 ArchiveInfo = provider(fields = ["archive_infos"])
+
 def _pick_correct_archive_for_device(ctx):
     cc_infos = []
     for dep in ctx.attr.deps:
@@ -140,7 +145,6 @@
     },
     fragments = ["cpp"],
     toolchains = ["@rules_cc//cc:toolchain_type"],
-
 )
 
 def opentitan_rom_binary(
@@ -745,7 +749,7 @@
         srcs = [vmem_32_name],
         outs = [vmem_256_name],
         cmd = cmd,
-        tools = ["@matcha//util:gen_vmem_256"]
+        tools = ["@matcha//util:gen_vmem_256"],
     )
     native.filegroup(
         name = name,
@@ -755,3 +759,34 @@
             vmem_name,
         ],
     )
+
+def target_fusesoc_build(name, output_groups):
+    """A helper macro for building verilator targets.
+
+    Args:
+      name: The name of the top level target.
+      output_groups: Verilator testbench passed to fusesoc_build.
+    """
+
+    fusesoc_build(
+        name = "{}_verilator_real".format(name),
+        srcs = [
+            ":all_files",
+            "//hw/top_{}:all_files".format(name),
+            "//hw/top_{}/dv/verilator:all_files".format(name),
+        ],
+        cores = [
+            "//:cores",
+            "//hw/ip:BUILD",
+            "//hw/top_{}:BUILD".format(name),
+        ],
+        data = ["@lowrisc_opentitan//hw/ip/otbn:all_files"],
+        make_options = ":make_options",
+        output_groups = output_groups,
+        systems = ["lowrisc:dv:{}_verilator_sim".format(name)],
+        tags = [
+            "manual",
+            "verilator",
+        ],
+        target = "sim",
+    )
diff --git a/rules/matcha_test.bzl b/rules/matcha_test.bzl
index 2e9fff9..115413b 100644
--- a/rules/matcha_test.bzl
+++ b/rules/matcha_test.bzl
@@ -28,7 +28,7 @@
         ml_flash_binary = None,
         rom_img = "@//sw/device/lib/testing/test_rom:test_rom_sim_verilator_scr_vmem",
         otp_img = "@//hw/top_matcha/data:otp_img_rma",
-        verilator_testbench = "@//hw:verilator",
+        verilator_testbench = "@//hw:matcha_verilator",
         timeout = "moderate",
         tags = [],
         **kwargs):
diff --git a/sw/device/examples/hello_world/BUILD b/sw/device/examples/hello_world/BUILD
index b9b2189..95bb48f 100644
--- a/sw/device/examples/hello_world/BUILD
+++ b/sw/device/examples/hello_world/BUILD
@@ -48,7 +48,7 @@
     timeout = "long",
     srcs = [":run_verilator_hello_world.sh"],
     args = [
-        "$(location //hw:verilator)",
+        "$(location //hw:matcha_verilator)",
         "$(location //sw/device/lib/testing/test_rom:test_rom_sim_verilator_scr_vmem)",
         "$(location :hello_world_sim_verilator_vmem)",
         "$(location //hw/top_matcha/data:otp_img_rma)",
@@ -56,7 +56,7 @@
     data = [
         ":hello_world_sim_verilator_vmem",
         ":hello_world_test_expected_gpio.txt",
-        "//hw:verilator",
+        "//hw:matcha_verilator",
         "//hw/top_matcha/data:otp_img_rma",
         "//sw/device/lib/testing/test_rom:test_rom_sim_verilator_scr_vmem",
     ],
@@ -71,7 +71,7 @@
     timeout = "long",
     srcs = [":run_verilator_hello_world.sh"],
     args = [
-        "$(location //hw:verilator)",
+        "$(location //hw:matcha_verilator)",
         "$(location //sw/device/lib/testing/test_rom:test_rom_sim_verilator_scr_vmem)",
         "$(location :hello_world_sim_verilator_vmem)",
         "$(location //hw/top_matcha/data:otp_img_rma)",
@@ -79,7 +79,7 @@
     ],
     data = [
         ":hello_world_sim_verilator_vmem",
-        "//hw:verilator",
+        "//hw:matcha_verilator",
         "//hw/top_matcha/data:otp_img_rma",
         "//sw/device/lib/testing/test_rom:test_rom_sim_verilator_scr_vmem",
     ],
diff --git a/sw/device/examples/hello_world/run_verilator_hello_world.sh b/sw/device/examples/hello_world/run_verilator_hello_world.sh
index f5ba0f1..d57b351 100755
--- a/sw/device/examples/hello_world/run_verilator_hello_world.sh
+++ b/sw/device/examples/hello_world/run_verilator_hello_world.sh
@@ -52,7 +52,7 @@
 OTP_BIN=$4
 
 if [[ ! -f $(realpath ${VCHIP_TB}) ]]; then
-  echo "Verilator testbench not found. Please make sure //hw:verilator is in data."
+  echo "Verilator testbench not found. Please make sure //hw:{target}_verilator is in data."
   exit 1
 fi
 
diff --git a/sw/device/lib/dif/BUILD b/sw/device/lib/dif/BUILD
index 0eef654..c907a26 100644
--- a/sw/device/lib/dif/BUILD
+++ b/sw/device/lib/dif/BUILD
@@ -63,7 +63,7 @@
         "@isp_yocto//include:yocto_isp_register_address.h",
     ],
     deps = [
-        "//hw/top_matcha/ip/isp_wrapper/data:isp_wrapper_regs",
+        "//hw/ip/isp_wrapper/data:isp_wrapper_regs",
         "@lowrisc_opentitan//sw/device/lib/base:macros",
         "@lowrisc_opentitan//sw/device/lib/base:memory",
         "@lowrisc_opentitan//sw/device/lib/base:mmio",
diff --git a/util/bazel_airgapped.patch b/util/bazel_airgapped.patch
index f87ec0b..147a60d 100644
--- a/util/bazel_airgapped.patch
+++ b/util/bazel_airgapped.patch
@@ -1,9 +1,9 @@
 diff --git a/BUILD.bazel b/BUILD.bazel
-index b131709..b297981 100644
+index e9d9ac9..2118808 100644
 --- a/BUILD.bazel
 +++ b/BUILD.bazel
-@@ -17,14 +17,7 @@ filegroup(
-         "//hw:check_tool_requirements.core",
+@@ -15,14 +15,7 @@ filegroup(
+         "@lowrisc_opentitan//hw/vendor:BUILD",
          "@axi2sramcrs//:BUILD",
          "@isp_yocto//:BUILD",
 -    ] + select({
@@ -21,12 +21,12 @@
 +    ],
  )
 diff --git a/hw/BUILD b/hw/BUILD
-index cd7f31a..13d43fa 100644
+index 392bca0..657fbd7 100644
 --- a/hw/BUILD
 +++ b/hw/BUILD
-@@ -84,14 +84,7 @@ filegroup(
+@@ -127,14 +127,7 @@ filegroup(
+     srcs = glob(["**"]) + [
          "//hw/ip:all_files",
-         "//hw/top_matcha:all_files",
          "@lowrisc_opentitan//hw/dv:all_files",
 -    ] + select({
 -        "//rules:airgapped_env": [
@@ -44,7 +44,7 @@
  )
 diff --git a/hw/ip/dma/chisel/BUILD b/hw/ip/dma/chisel/BUILD
 deleted file mode 100644
-index 2a102ea..0000000
+index 1272457..0000000
 --- a/hw/ip/dma/chisel/BUILD
 +++ /dev/null
 @@ -1,45 +0,0 @@
diff --git a/util/topgen_matcha.py b/util/topgen_matcha.py
index 9f7ee44..d9055f8 100755
--- a/util/topgen_matcha.py
+++ b/util/topgen_matcha.py
@@ -24,7 +24,8 @@
 import shutil
 import sys
 import tempfile
-from collections import OrderedDict
+import datetime
+from collections import OrderedDict, defaultdict
 from copy import deepcopy
 from io import StringIO
 from pathlib import Path
@@ -65,7 +66,7 @@
 // ------------------- W A R N I N G: A U T O - G E N E R A T E D   C O D E !! -------------------//
 // PLEASE DO NOT HAND-EDIT THIS FILE. IT HAS BEEN AUTO-GENERATED WITH THE FOLLOWING COMMAND:
 """
-genhdr = """// Copyright 2023 Google LLC
+genhdr = """// Copyright {} Google LLC
 //
 // Licensed under the Apache License, Version 2.0 (the "License");
 // you may not use this file except in compliance with the License.
@@ -110,6 +111,11 @@
 SHODAN_COMMON_IP = [x.stem for x in search_ips(SRCTREE_TOP / "hw/ip")]
 
 
+COPYRIGHT_YEAR = defaultdict(lambda: str(datetime.date.today().year))
+COPYRIGHT_YEAR["matcha"] = "2023"
+COPYRIGHT_YEAR["sencha"] = "2024"
+
+
 def is_intr_to_smc(module):
     """Return whether a particular module whose interrupt to SMC core.
     """
@@ -174,7 +180,7 @@
 
         # Generate output of crossbar with complete fields
         xbar_hjson_path = xbar_path / "xbar_{}.gen.hjson".format(xbar.name)
-        xbar_hjson_path.write_text(genhdr + gencmd +
+        xbar_hjson_path.write_text(genhdr.format(COPYRIGHT_YEAR[topname]) + gencmd +
                                    hjson.dumps(obj, for_json=True) + '\n')
 
         if not tlgen.elaborate(xbar):
@@ -434,7 +440,7 @@
         return
 
     with hjson_gen_path.open(mode="w", encoding="UTF-8") as fout:
-        fout.write(genhdr + gencmd + out)
+        fout.write(genhdr.format(COPYRIGHT_YEAR[topname]) + gencmd + out)
 
     # Generate reg file
     generate_regfile_from_path(hjson_gen_path, rtl_path, original_rtl_path)
@@ -485,7 +491,7 @@
             return
 
         with outputs[idx].open(mode="w", encoding="UTF-8") as fout:
-            fout.write(genhdr + out)
+            fout.write(genhdr.format(COPYRIGHT_YEAR[top["name"]]) + out)
 
     # Generate reg files
     generate_regfile_from_path(hjson_out, rtl_path, original_rtl_path)
@@ -544,7 +550,7 @@
 
     hjson_path = doc_path / "pwrmgr.hjson"
     with hjson_path.open(mode="w", encoding="UTF-8") as fout:
-        fout.write(genhdr + out)
+        fout.write(genhdr.format(COPYRIGHT_YEAR[top["name"]]) + out)
 
     # Generate reg files
     generate_regfile_from_path(hjson_path, rtl_path, original_rtl_path)
@@ -628,7 +634,7 @@
             return
 
         with outputs[idx].open(mode="w", encoding="UTF-8") as fout:
-            fout.write(genhdr + out)
+            fout.write(genhdr.format(COPYRIGHT_YEAR[topcfg["name"]]) + out)
 
     # Generate reg files
     hjson_path = outputs[0]
@@ -688,7 +694,7 @@
             return
 
         with outputs[idx].open(mode="w", encoding="UTF-8") as fout:
-            fout.write(genhdr + out)
+            fout.write(genhdr.format(COPYRIGHT_YEAR[topcfg["name"]]) + out)
 
     # Generate reg files
     hjson_path = outputs[0]
@@ -712,15 +718,19 @@
 
         hjson_path = hjson_dir / f"{ip}.hjson"
 
-        genrtl_dir = out_path / "ip/{}/rtl".format(ip)
-        genrtl_dir.mkdir(parents=True, exist_ok=True)
-
         if ip in SHODAN_COMMON_IP:
           orig_rtl_path = Path(__file__).resolve(
           ).parent / f"../hw/ip/{ip}/rtl"
+          # Common IPs should not generate new reg tops for different targets.
+          # The line below is added to indicate if a shodan IP should be moved
+          # to a top-level target.
+          genrtl_dir = SRCTREE_TOP / "hw/ip/{}/rtl".format(ip)
         else:
           orig_rtl_path = Path(__file__).resolve(
           ).parent / f"../hw/top_{topname}/ip/{ip}/rtl"
+          genrtl_dir = out_path / "ip/{}/rtl".format(ip)
+
+        genrtl_dir.mkdir(parents=True, exist_ok=True)
 
         log.info("Generating top modules {}, hjson: {}, output: {}".format(
             ip, hjson_path, genrtl_dir))
@@ -1323,13 +1333,13 @@
 //                --hjson-only \\
 //                --rnd_cnst_seed {completecfg["rnd_cnst_seed"]}
 """
-        genhjson_path.write_text(genhdr + gencmd +
+        genhjson_path.write_text(genhdr.format(COPYRIGHT_YEAR[topname]) + gencmd +
                                  hjson.dumps(rom_ctrl_cfg, for_json=True) +
                                  '\n')
         # Generate top.gen.hjson right before rendering
         genhjson_path = genhjson_dir / ("top_%s.gen.hjson" %
                                         completecfg["name"])
-        genhjson_path.write_text(genhdr + gencmd +
+        genhjson_path.write_text(genhdr.format(COPYRIGHT_YEAR[topcfg["name"]]) + gencmd +
                                  hjson.dumps(completecfg, for_json=True) + '\n')
 
     if not args.no_top or args.top_only:
@@ -1360,20 +1370,6 @@
 """.format(topname=topname, seed=completecfg["rnd_cnst_seed"],
            out_path=os.path.relpath(out_path, SRCTREE_TOP))
 
-        # SystemVerilog Top:
-        # "toplevel.sv.tpl" -> "rtl/autogen/top_{topname}.sv"
-        render_template(TOPGEN_TEMPLATE_MATCHA_PATH / "toplevel.sv.tpl",
-                        out_path / f"rtl/autogen/top_{topname}.sv",
-                        gencmd=gencmd)
-
-        # Multiple chip-levels (ASIC, FPGA, Verilator, etc)
-        for target in topcfg["targets"]:
-            target_name = target["name"]
-            render_template(TOPGEN_TEMPLATE_MATCHA_PATH / "chiplevel.sv.tpl",
-                            out_path /
-                            f"rtl/autogen/chip_{topname}_{target_name}.sv",
-                            gencmd=gencmd,
-                            target=target)
 
         # The C / SV file needs some complex information, so we initialize this
         # object to store it.
@@ -1383,6 +1379,24 @@
             completecfg)
         c_helper = TopGenCTest(sec_topcfg, name_to_block)
         c_helper = create_smc_c_helper(c_helper, smc_topcfg, name_to_block)
+        c_helper.date = COPYRIGHT_YEAR[topname]
+
+        # SystemVerilog Top:
+        # "toplevel.sv.tpl" -> "rtl/autogen/top_{topname}.sv"
+        render_template(TOPGEN_TEMPLATE_MATCHA_PATH / "toplevel.sv.tpl",
+                        out_path / f"rtl/autogen/top_{topname}.sv",
+                        helper=c_helper,
+                        gencmd=gencmd)
+
+        # Multiple chip-levels (ASIC, FPGA, Verilator, etc)
+        for target in topcfg["targets"]:
+            target_name = target["name"]
+            render_template(TOPGEN_TEMPLATE_MATCHA_PATH / "chiplevel.sv.tpl",
+                            out_path /
+                            f"rtl/autogen/chip_{topname}_{target_name}.sv",
+                            helper=c_helper,
+                            gencmd=gencmd,
+                            target=target)
 
         # The Rust file needs some complex information, so we initialize this
         # object to store it.
@@ -1470,7 +1484,9 @@
             if fname == "tb__xbar_connect.sv":
                 xbar_chip_data_path = TOPGEN_TEMPLATE_MATCHA_PATH / tpl_fname
             template_contents = generate_top(completecfg, name_to_block,
-                                             str(xbar_chip_data_path), gencmd=gencmd)
+                                             str(xbar_chip_data_path),
+                                             helper=c_helper,
+                                             gencmd=gencmd)
 
             rendered_dir = out_path / "dv/autogen"
             rendered_dir.mkdir(parents=True, exist_ok=True)
diff --git a/util/topgen_matcha/templates/alert_test.c.tpl b/util/topgen_matcha/templates/alert_test.c.tpl
index c43d47c..91d08c4 100644
--- a/util/topgen_matcha/templates/alert_test.c.tpl
+++ b/util/topgen_matcha/templates/alert_test.c.tpl
@@ -1,4 +1,4 @@
-// Copyright 2023 Google LLC
+// Copyright ${helper.date} Google LLC
 // Copyright lowRISC contributors
 //
 // Licensed under the Apache License, Version 2.0 (the "License");
@@ -38,7 +38,7 @@
 #include "sw/device/lib/testing/test_framework/ottf_test_config.h"
 
 #include "alert_handler_regs.h"  // Generated.
-#include "hw/top_matcha/sw/autogen/top_matcha.h"
+#include "hw/top_${top["name"]}/sw/autogen/top_${top["name"]}.h"
 
 OTTF_DEFINE_TEST_CONFIG();
 
@@ -54,7 +54,7 @@
  */
 static void init_peripherals(void) {
   mmio_region_t base_addr;
-  base_addr = mmio_region_from_addr(TOP_MATCHA_ALERT_HANDLER_BASE_ADDR);
+  base_addr = mmio_region_from_addr(TOP_${top["name"].upper()}_ALERT_HANDLER_BASE_ADDR);
   CHECK_DIF_OK(dif_alert_handler_init(base_addr, &alert_handler));
 
   % for p in helper.alert_peripherals:
diff --git a/util/topgen_matcha/templates/chiplevel.sv.tpl b/util/topgen_matcha/templates/chiplevel.sv.tpl
index e0a14ef..1fdcf86 100644
--- a/util/topgen_matcha/templates/chiplevel.sv.tpl
+++ b/util/topgen_matcha/templates/chiplevel.sv.tpl
@@ -1,4 +1,4 @@
-// Copyright 2023 Google LLC
+// Copyright ${helper.date} Google LLC
 // Copyright lowRISC contributors
 //
 // Licensed under the Apache License, Version 2.0 (the "License");
diff --git a/util/topgen_matcha/templates/plic_all_irqs_test.c.tpl b/util/topgen_matcha/templates/plic_all_irqs_test.c.tpl
index 26b50e2..97baa0c 100644
--- a/util/topgen_matcha/templates/plic_all_irqs_test.c.tpl
+++ b/util/topgen_matcha/templates/plic_all_irqs_test.c.tpl
@@ -1,4 +1,4 @@
-// Copyright 2023 Google LLC
+// Copyright ${helper.date} Google LLC
 // Copyright lowRISC contributors
 //
 // Licensed under the Apache License, Version 2.0 (the "License");
diff --git a/util/topgen_matcha/templates/tb__xbar_connect.sv.tpl b/util/topgen_matcha/templates/tb__xbar_connect.sv.tpl
index 85771ea..905cffc 100644
--- a/util/topgen_matcha/templates/tb__xbar_connect.sv.tpl
+++ b/util/topgen_matcha/templates/tb__xbar_connect.sv.tpl
@@ -1,4 +1,4 @@
-// Copyright 2023 Google LLC
+// Copyright ${helper.date} Google LLC
 // Copyright lowRISC contributors
 //
 // Licensed under the Apache License, Version 2.0 (the "License");
diff --git a/util/topgen_matcha/templates/toplevel.c.tpl b/util/topgen_matcha/templates/toplevel.c.tpl
index 0dd12f0..bceee4d 100644
--- a/util/topgen_matcha/templates/toplevel.c.tpl
+++ b/util/topgen_matcha/templates/toplevel.c.tpl
@@ -1,4 +1,4 @@
-// Copyright 2023 Google LLC
+// Copyright ${helper.date} Google LLC
 // Copyright lowRISC contributors
 //
 // Licensed under the Apache License, Version 2.0 (the "License");
diff --git a/util/topgen_matcha/templates/toplevel.h.tpl b/util/topgen_matcha/templates/toplevel.h.tpl
index eb740b5..f5cae19 100644
--- a/util/topgen_matcha/templates/toplevel.h.tpl
+++ b/util/topgen_matcha/templates/toplevel.h.tpl
@@ -1,4 +1,4 @@
-// Copyright 2023 Google LLC
+// Copyright ${helper.date} Google LLC
 // Copyright lowRISC contributors
 //
 // Licensed under the Apache License, Version 2.0 (the "License");
diff --git a/util/topgen_matcha/templates/toplevel.sv.tpl b/util/topgen_matcha/templates/toplevel.sv.tpl
index 5c9f7a9..6cd9ec8 100644
--- a/util/topgen_matcha/templates/toplevel.sv.tpl
+++ b/util/topgen_matcha/templates/toplevel.sv.tpl
@@ -1,4 +1,4 @@
-// Copyright 2023 Google LLC
+// Copyright ${helper.date} Google LLC
 // Copyright lowRISC contributors
 //
 // Licensed under the Apache License, Version 2.0 (the "License");
@@ -479,7 +479,7 @@
 % for m in top["module"]:
 <%
 ## Hacked here to skip the second tlul_mailbox ip instantiation.
-## In the top_matcha.hjson, we instantiated two modules of tlul_mailbox from the same IP,
+## In the top_{target}.hjson, we instantiated two modules of tlul_mailbox from the same IP,
 ## only to generate two separate interrupt, tlul and registers of tlul_mailbox to two different
 ## cores (security and smc). However only one IP in the RTL top level need to be instantiated.
 if (not lib.is_inst(m)) or (m["name"] == "tlul_mailbox_smc") :
diff --git a/util/topgen_matcha/templates/toplevel_smc_irq.h.tpl b/util/topgen_matcha/templates/toplevel_smc_irq.h.tpl
index 33d29d5..2162fbe 100644
--- a/util/topgen_matcha/templates/toplevel_smc_irq.h.tpl
+++ b/util/topgen_matcha/templates/toplevel_smc_irq.h.tpl
@@ -1,4 +1,4 @@
-// Copyright 2023 Google LLC
+// Copyright ${helper.date} Google LLC
 //
 // Licensed under the Apache License, Version 2.0 (the "License");
 // you may not use this file except in compliance with the License.