diff --git a/hw/ip/dma/chisel/src/DMATop.scala b/hw/ip/dma/chisel/src/DMATop.scala
index 564e7e3..7406fbc 100644
--- a/hw/ip/dma/chisel/src/DMATop.scala
+++ b/hw/ip/dma/chisel/src/DMATop.scala
@@ -22,7 +22,8 @@
 import DMAController.Frontend._
 import DMAController.Worker.{InterruptBundle, WorkerCSRWrapper, SyncBundle}
 import DMAController.DMAConfig._
-import _root_.circt.stage.ChiselStage
+import _root_.circt.stage.{ChiselStage,FirtoolOption}
+import chisel3.stage.ChiselGeneratorAnnotation
 
 class DMATop extends Module {
 
@@ -64,5 +65,8 @@
 }
 
 object EmitDMA extends App{
-  ChiselStage.emitSystemVerilogFile(new DMATop, args)
+  (new ChiselStage).execute(
+    Array("--target", "systemverilog") ++ args,
+    Seq(ChiselGeneratorAnnotation(() => new DMATop)) ++ Seq(FirtoolOption("-enable-layers=Verification"))
+  )
 }