[sencha/hw] Reduce SMC SRAM from 4MB to 512KB
- Reduced since we no longer plan to support Cantrip OS on Sencha,
obviating the need for large SRAM in an effort to reduce die size for
a potential future test chip
Change-Id: Ic30e1cbd3b70b7189642762f75d8f221d6619e88
diff --git a/hw/top_sencha/data/top_sencha.hjson b/hw/top_sencha/data/top_sencha.hjson
index be0c1ed..c745e84 100644
--- a/hw/top_sencha/data/top_sencha.hjson
+++ b/hw/top_sencha/data/top_sencha.hjson
@@ -1041,7 +1041,6 @@
// Memories (ROM, RAM, eFlash) are defined at the top.
// It utilizes the primitive cells but configurable
// All memories wrapped up in relevant controllers
- // ram_smc returned to 4MB
memory: [
{ name: "ram_smc",
clock_srcs: {clk_i: "smc"},
@@ -1055,7 +1054,7 @@
}
type: "ram_1p",
base_addr: "0x50000000",
- size: "0x400000",
+ size: "0x80000",
inter_signal_list: [
{ struct: "tl"
package: "tlul_pkg"
diff --git a/hw/top_sencha/dv/autogen/xbar_env_pkg__params.sv b/hw/top_sencha/dv/autogen/xbar_env_pkg__params.sv
index 6f89304..3b1a329 100644
--- a/hw/top_sencha/dv/autogen/xbar_env_pkg__params.sv
+++ b/hw/top_sencha/dv/autogen/xbar_env_pkg__params.sv
@@ -164,7 +164,7 @@
'{32'h54030000, 32'h540300ff}
}},
'{"ram_smc", '{
- '{32'h50000000, 32'h503fffff}
+ '{32'h50000000, 32'h5007ffff}
}},
'{"smc_uart", '{
'{32'h54000000, 32'h5400003f}
diff --git a/hw/top_sencha/dv/autogen/xbar_tgl_excl.cfg b/hw/top_sencha/dv/autogen/xbar_tgl_excl.cfg
index c358482..d95716d 100644
--- a/hw/top_sencha/dv/autogen/xbar_tgl_excl.cfg
+++ b/hw/top_sencha/dv/autogen/xbar_tgl_excl.cfg
@@ -219,7 +219,7 @@
-node tb.dut*.u_rv_core_ibex_smc cfg_tl_*i.a_address[27:27]
-node tb.dut*.u_rv_core_ibex_smc cfg_tl_*i.a_address[29:29]
-node tb.dut*.u_rv_core_ibex_smc cfg_tl_*i.a_address[31:31]
--node tb.dut*.u_ram_smc tl_*i.a_address[27:22]
+-node tb.dut*.u_ram_smc tl_*i.a_address[27:19]
-node tb.dut*.u_ram_smc tl_*i.a_address[29:29]
-node tb.dut*.u_ram_smc tl_*i.a_address[31:31]
-node tb.dut*.u_smc_uart tl_*i.a_address[25:6]
diff --git a/hw/top_sencha/dv/verilator/chip_sim_tb.cc b/hw/top_sencha/dv/verilator/chip_sim_tb.cc
index 2beb1c9..77de8c7 100644
--- a/hw/top_sencha/dv/verilator/chip_sim_tb.cc
+++ b/hw/top_sencha/dv/verilator/chip_sim_tb.cc
@@ -54,7 +54,7 @@
ram1p_adv_scope,
0x4000 / 4, 4);
MemArea ram_smc(top_scope + ".u_ram1p_ram_smc.u_mem.gen_generic.u_impl_generic",
- 0x400000 / 4, 4);
+ 0x80000 / 4, 4);
MemArea ml_dmem(top_scope + ".u_ml_top.u_ml_dmem.u_ram1p_dmem.u_mem.gen_generic.u_impl_generic",
0x400000 / 32, 32);
diff --git a/hw/top_sencha/ip/xbar_smc/data/autogen/xbar_smc.gen.hjson b/hw/top_sencha/ip/xbar_smc/data/autogen/xbar_smc.gen.hjson
index c214c1b..df01b1c 100644
--- a/hw/top_sencha/ip/xbar_smc/data/autogen/xbar_smc.gen.hjson
+++ b/hw/top_sencha/ip/xbar_smc/data/autogen/xbar_smc.gen.hjson
@@ -246,7 +246,7 @@
[
{
base_addr: 0x50000000
- size_byte: 0x400000
+ size_byte: 0x80000
}
]
xbar: false
diff --git a/hw/top_sencha/ip/xbar_smc/dv/autogen/xbar_cover.cfg b/hw/top_sencha/ip/xbar_smc/dv/autogen/xbar_cover.cfg
index d636d14..3d8e80a 100644
--- a/hw/top_sencha/ip/xbar_smc/dv/autogen/xbar_cover.cfg
+++ b/hw/top_sencha/ip/xbar_smc/dv/autogen/xbar_cover.cfg
@@ -26,7 +26,7 @@
-node tb.dut tl_rv_core_ibex_smc__cfg_o.a_address[27:27]
-node tb.dut tl_rv_core_ibex_smc__cfg_o.a_address[29:29]
-node tb.dut tl_rv_core_ibex_smc__cfg_o.a_address[31:31]
--node tb.dut tl_ram_smc_o.a_address[27:22]
+-node tb.dut tl_ram_smc_o.a_address[27:19]
-node tb.dut tl_ram_smc_o.a_address[29:29]
-node tb.dut tl_ram_smc_o.a_address[31:31]
-node tb.dut tl_smc_uart_o.a_address[25:6]
diff --git a/hw/top_sencha/ip/xbar_smc/dv/autogen/xbar_env_pkg__params.sv b/hw/top_sencha/ip/xbar_smc/dv/autogen/xbar_env_pkg__params.sv
index b557ab1..a9c3eb4 100644
--- a/hw/top_sencha/ip/xbar_smc/dv/autogen/xbar_env_pkg__params.sv
+++ b/hw/top_sencha/ip/xbar_smc/dv/autogen/xbar_env_pkg__params.sv
@@ -14,7 +14,7 @@
'{32'h54030000, 32'h540300ff}
}},
'{"ram_smc", '{
- '{32'h50000000, 32'h503fffff}
+ '{32'h50000000, 32'h5007ffff}
}},
'{"smc_uart", '{
'{32'h54000000, 32'h5400003f}
diff --git a/hw/top_sencha/ip/xbar_smc/rtl/autogen/tl_smc_pkg.sv b/hw/top_sencha/ip/xbar_smc/rtl/autogen/tl_smc_pkg.sv
index c9661f8..d13fe00 100644
--- a/hw/top_sencha/ip/xbar_smc/rtl/autogen/tl_smc_pkg.sv
+++ b/hw/top_sencha/ip/xbar_smc/rtl/autogen/tl_smc_pkg.sv
@@ -28,7 +28,7 @@
localparam logic [31:0] ADDR_MASK_RV_PLIC_SMC = 32'h 07ffffff;
localparam logic [31:0] ADDR_MASK_RV_CORE_IBEX_SMC__CFG = 32'h 000000ff;
- localparam logic [31:0] ADDR_MASK_RAM_SMC = 32'h 003fffff;
+ localparam logic [31:0] ADDR_MASK_RAM_SMC = 32'h 0007ffff;
localparam logic [31:0] ADDR_MASK_SMC_UART = 32'h 0000003f;
localparam logic [31:0] ADDR_MASK_RV_TIMER_SMC = 32'h 000001ff;
localparam logic [31:0] ADDR_MASK_TLUL_MAILBOX_SMC = 32'h 0000003f;
diff --git a/hw/top_sencha/rtl/autogen/top_sencha.sv b/hw/top_sencha/rtl/autogen/top_sencha.sv
index 525f3a2..996e2b1 100644
--- a/hw/top_sencha/rtl/autogen/top_sencha.sv
+++ b/hw/top_sencha/rtl/autogen/top_sencha.sv
@@ -1063,7 +1063,7 @@
// sram device
logic ram_smc_req;
logic ram_smc_we;
- logic [19:0] ram_smc_addr;
+ logic [16:0] ram_smc_addr;
logic [31:0] ram_smc_wdata;
logic [31:0] ram_smc_wmask;
logic [31:0] ram_smc_rdata;
@@ -1092,7 +1092,7 @@
prim_ram_1p_adv #(
.Width(32),
- .Depth(1048576),
+ .Depth(131072),
.DataBitsPerMask(8),
// TODO: enable parity once supported by the simulation infrastructure
.EnableParity(0)
diff --git a/hw/top_sencha/rtl/autogen/top_sencha_pkg.sv b/hw/top_sencha/rtl/autogen/top_sencha_pkg.sv
index 7726939..a2a7c0d 100644
--- a/hw/top_sencha/rtl/autogen/top_sencha_pkg.sv
+++ b/hw/top_sencha/rtl/autogen/top_sencha_pkg.sv
@@ -688,7 +688,7 @@
/**
* Memory size for ram_smc in top sencha.
*/
- parameter int unsigned TOP_SENCHA_RAM_SMC_SIZE_BYTES = 32'h400000;
+ parameter int unsigned TOP_SENCHA_RAM_SMC_SIZE_BYTES = 32'h80000;
/**
* Memory base address for ram_ret_aon in top sencha.
diff --git a/hw/top_sencha/sw/autogen/top_sencha.h b/hw/top_sencha/sw/autogen/top_sencha.h
index a8572e3..4a4b6e4 100644
--- a/hw/top_sencha/sw/autogen/top_sencha.h
+++ b/hw/top_sencha/sw/autogen/top_sencha.h
@@ -1252,7 +1252,7 @@
/**
* Memory size for ram_smc in top sencha.
*/
-#define TOP_SENCHA_RAM_SMC_SIZE_BYTES 0x400000u
+#define TOP_SENCHA_RAM_SMC_SIZE_BYTES 0x80000u
/**
* Memory base address for ram_ret_aon in top sencha.
diff --git a/hw/top_sencha/sw/autogen/top_sencha_memory.h b/hw/top_sencha/sw/autogen/top_sencha_memory.h
index 03afdcb..3e90663 100644
--- a/hw/top_sencha/sw/autogen/top_sencha_memory.h
+++ b/hw/top_sencha/sw/autogen/top_sencha_memory.h
@@ -80,7 +80,7 @@
/**
* Memory size for ram_smc in top sencha.
*/
-#define TOP_SENCHA_RAM_SMC_SIZE_BYTES 0x400000
+#define TOP_SENCHA_RAM_SMC_SIZE_BYTES 0x80000
/**
diff --git a/hw/top_sencha/sw/autogen/top_sencha_memory.ld b/hw/top_sencha/sw/autogen/top_sencha_memory.ld
index 6dfb4e8..01746d6 100644
--- a/hw/top_sencha/sw/autogen/top_sencha_memory.ld
+++ b/hw/top_sencha/sw/autogen/top_sencha_memory.ld
@@ -13,7 +13,7 @@
ram_main(rwx) : ORIGIN = 0x10000000, LENGTH = 0x20000
rom(rx) : ORIGIN = 0x00008000, LENGTH = 0x8000
ram_ml_dmem(rwx) : ORIGIN = 0x5A000000, LENGTH = 0x400000
- ram_smc(rw) : ORIGIN = 0x50000000, LENGTH = 0x400000
+ ram_smc(rw) : ORIGIN = 0x50000000, LENGTH = 0x80000
rom_ext_virtual(rx) : ORIGIN = 0x90000000, LENGTH = 0x80000
owner_virtual(rx) : ORIGIN = 0xa0000000, LENGTH = 0x80000
}
