)]}'
{
  "commit": "a460a7ca2727f8082781293119ab2dcd666e39e1",
  "tree": "925e377d4ebf4223f8fb87e24dd8385f76f28acd",
  "parents": [
    "63706d1b9933e5f42b21c4a6650172f522a68ba6"
  ],
  "author": {
    "name": "Michael Hoang",
    "email": "hoangm@google.com",
    "time": "Wed Aug 07 22:15:50 2024 +0000"
  },
  "committer": {
    "name": "Michael Hoang",
    "email": "hoangm@google.com",
    "time": "Thu Aug 08 15:38:49 2024 +0000"
  },
  "message": "Add targets.bzl for top level targets\n\n- Used in verilator and future fpga targets to easily extend bazel\n  targets\n- Rename chip_sim_tb to matcha_sim_tb\n\nChange-Id: I36a45aba0f6ef293bf4b9c270dc1ea9c9f759428\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "85d820d2687c4f5f55789315a2c36927e2ea52a5",
      "old_mode": 33188,
      "old_path": "hw/BUILD",
      "new_id": "a5722c22de37c853b173a6a8344fa63d93dcd7cc",
      "new_mode": 33188,
      "new_path": "hw/BUILD"
    },
    {
      "type": "modify",
      "old_id": "7806dd43266391aacd8144f69e0d57330041df92",
      "old_mode": 33188,
      "old_path": "hw/top_matcha/dv/verilator/chip_sim.core",
      "new_id": "d287c974bd105af9b9d9b1beccde9e3e57987a2e",
      "new_mode": 33188,
      "new_path": "hw/top_matcha/dv/verilator/chip_sim.core"
    },
    {
      "type": "modify",
      "old_id": "9ff7a15c8c6cd37db484dcf7c4cdfd65ed5f6f79",
      "old_mode": 33188,
      "old_path": "hw/top_matcha/dv/verilator/chip_sim_tb.cc",
      "new_id": "d76a1faa81fb32afc73a151bf0ab6042d82dc7e1",
      "new_mode": 33188,
      "new_path": "hw/top_matcha/dv/verilator/chip_sim_tb.cc"
    },
    {
      "type": "modify",
      "old_id": "e1068122e9914bb79eeb4c01944d086834273a37",
      "old_mode": 33188,
      "old_path": "hw/top_matcha/dv/verilator/chip_sim_tb.sv",
      "new_id": "e4a4932975692fe31eb555a51f422c3d4d5ff131",
      "new_mode": 33188,
      "new_path": "hw/top_matcha/dv/verilator/chip_sim_tb.sv"
    },
    {
      "type": "modify",
      "old_id": "33fc3a7c76658409fbd2f13ea7f1385c2f78614a",
      "old_mode": 33188,
      "old_path": "hw/top_sencha/dv/verilator/chip_sim.core",
      "new_id": "d49956d7d0eca4095b60808459ebf67c56c867ce",
      "new_mode": 33188,
      "new_path": "hw/top_sencha/dv/verilator/chip_sim.core"
    },
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "32ba99666c92515c99022c9bde1b37b94031cb28",
      "new_mode": 33188,
      "new_path": "rules/targets.bzl"
    },
    {
      "type": "delete",
      "old_id": "f186b851056aa0af9a767f45fa289298bbdf8c1b",
      "old_mode": 33188,
      "old_path": "rules/verilator.bzl",
      "new_id": "0000000000000000000000000000000000000000",
      "new_mode": 0,
      "new_path": "/dev/null"
    }
  ]
}