sw/device/tests/smc/smc_ml_top_irq_test.c

// Copyright 2022 Google LLC.
// Copyright lowRISC contributors.
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0

#include "hw/top_matcha/sw/autogen/top_matcha.h"
#include "sw/device/lib/arch/device.h"
#include "sw/device/lib/dif/dif_ml_top.h"
#include "sw/device/lib/dif/dif_rv_plic.h"
#include "sw/device/lib/dif/dif_uart.h"
#include "sw/device/lib/runtime/irq.h"
#include "sw/device/lib/runtime/log.h"
#include "sw/device/lib/runtime/print.h"
#include "sw/device/lib/testing/test_framework/check.h"
#include "sw/device/lib/testing/test_framework/ottf_test_config.h"
#include "sw/device/lib/testing/test_framework/test_util.h"

OTTF_DEFINE_TEST_CONFIG();

static dif_uart_t smc_uart;
static dif_ml_top_t ml_top;
static dif_rv_plic_t plic_smc;

// These flags are used in the test routine to verify that a corresponding
// interrupt has elapsed, and has been serviced. These are declared as volatile
// since they are referenced in the ISR routine as well as in the main program
// flow.
// TODO(ykwang): host_req and data_fault are not handled yet.
static volatile bool ml_top_finish_handled;
static volatile bool ml_top_fault_handled;

/**
 * ML_TOP ISR.
 *
 * Services ML_TOP interrupts, sets the appropriate flags that are used to
 * determine success or failure of the test.
 */
static void handle_ml_top_isr(const dif_rv_plic_irq_id_t interrupt_id) {
  // NOTE: This initialization is superfluous, since the `default` case below
  // is effectively noreturn, but the compiler is unable to prove this.
  dif_ml_top_irq_t ml_top_irq = 0;

  switch (interrupt_id) {
    case kTopMatchaPlicIrqIdMlTopFinish:
      CHECK(!ml_top_finish_handled,
            "ML_TOP finish IRQ asserted more than once");
      ml_top_irq = kDifMlTopIrqFinish;
      ml_top_finish_handled = true;
      break;
    case kTopMatchaPlicIrqIdMlTopFault:
      CHECK(!ml_top_fault_handled,
            "ML_TOP instruction fault IRQ asserted more than once");
      ml_top_irq = kDifMlTopIrqFault;
      ml_top_fault_handled = true;
      break;
    default:
      LOG_FATAL("ISR is not implemented!");
  }

  CHECK_DIF_OK(dif_ml_top_irq_acknowledge(&ml_top, ml_top_irq));
}

/**
 * External ISR.
 *
 * Handles all peripheral interrupts on Ibex. PLIC asserts an external interrupt
 * line to the CPU, which results in a call to this OTTF ISR. This ISR
 * overrides the default OTTF implementation.
 */
void ottf_external_isr(void) {
  //// Claim the IRQ by reading the Ibex specific CC register.
  dif_rv_plic_irq_id_t interrupt_id;
  CHECK_DIF_OK(dif_rv_plic_irq_claim(&plic_smc, kTopMatchaPlicTargetIbex0Smc,
                                     &interrupt_id));

  // Check if the interrupted peripheral is UART.
  top_matcha_plic_peripheral_smc_t peripheral_id =
      top_matcha_plic_interrupt_for_peripheral_smc[interrupt_id];
  CHECK(peripheral_id == kTopMatchaPlicPeripheralMlTop,
        "ISR interrupted peripheral is not ML_TOP!");
  switch (peripheral_id) {
    case kTopMatchaPlicPeripheralMlTop:
      handle_ml_top_isr(interrupt_id);
      break;
    default:
      LOG_FATAL("Peripheral is not implemented!");
  }

  // Complete the IRQ by writing the IRQ source to the Ibex specific CC
  // register.
  CHECK_DIF_OK(dif_rv_plic_irq_complete(&plic_smc, kTopMatchaPlicTargetIbex0Smc,
                                        interrupt_id));
}

/**
 * Configures all the relevant interrupts in ML_TOP.
 */
static void ml_top_configure_irqs(dif_ml_top_t *ml_top) {
  CHECK_DIF_OK(dif_ml_top_irq_set_enabled(ml_top, kDifMlTopIrqFinish,
                                          kDifToggleEnabled));
  CHECK_DIF_OK(
      dif_ml_top_irq_set_enabled(ml_top, kDifMlTopIrqFault, kDifToggleEnabled));
}

/**
 * Configures all the relevant interrupts in PLIC_SMC.
 */
static void plic_smc_configure_irqs(dif_rv_plic_t *plic) {
  // Set IRQ priorities to MAX
  CHECK_DIF_OK(dif_rv_plic_irq_set_priority(
      plic, kTopMatchaPlicIrqIdMlTopFinish, kDifRvPlicMaxPriority));
  CHECK_DIF_OK(dif_rv_plic_irq_set_priority(plic, kTopMatchaPlicIrqIdMlTopFault,
                                            kDifRvPlicMaxPriority));

  // Set Ibex IRQ priority threshold level
  CHECK_DIF_OK(dif_rv_plic_target_set_threshold(
      plic, kTopMatchaPlicTargetIbex0Smc, kDifRvPlicMinPriority));

  // Enable IRQs in PLIC
  CHECK_DIF_OK(dif_rv_plic_irq_set_enabled(plic, kTopMatchaPlicIrqIdMlTopFinish,
                                           kTopMatchaPlicTargetIbex0Smc,
                                           kDifToggleEnabled));
  CHECK_DIF_OK(dif_rv_plic_irq_set_enabled(plic, kTopMatchaPlicIrqIdMlTopFault,
                                           kTopMatchaPlicTargetIbex0Smc,
                                           kDifToggleEnabled));
}

static void execute_test() {
  // Force ML_TOP finish interrupt.
  ml_top_finish_handled = false;
  CHECK_DIF_OK(dif_ml_top_irq_force(&ml_top, kDifMlTopIrqFinish, true));
  // Check if the IRQ has occured and has been handled appropriately.
  if (!ml_top_finish_handled) {
    busy_spin_micros(1000);
  }
  CHECK(ml_top_finish_handled, "ML_TOP finish IRQ has not been handled!");

  ml_top_fault_handled = false;
  CHECK_DIF_OK(dif_ml_top_irq_force(&ml_top, kDifMlTopIrqFault, true));
  // Check if the IRQ has occured and has been handled appropriately.
  if (!ml_top_fault_handled) {
    busy_spin_micros(1000);
  }
  CHECK(ml_top_fault_handled, "ML_TOP fault IRQ has not been handled!");
}

void _ottf_main(void) {
  // Initialize the SMC UART to enable logging for non-DV simulation platforms.
  if (kDeviceType != kDeviceSimDV) {
    init_uart(TOP_MATCHA_SMC_UART_BASE_ADDR, &smc_uart);
  }
  LOG_INFO("Hello Shodan! let's do a ML_TOP IRQ test!");
  test_status_set(kTestStatusInTest);
  irq_global_ctrl(true);
  irq_external_ctrl(true);

  // Initialize each dif device.
  CHECK_DIF_OK(dif_rv_plic_init(
      mmio_region_from_addr(TOP_MATCHA_RV_PLIC_SMC_BASE_ADDR), &plic_smc));
  CHECK_DIF_OK(dif_ml_top_init(
      mmio_region_from_addr(TOP_MATCHA_ML_TOP_CORE_BASE_ADDR), &ml_top));

  // Configure irqs for ml_top.
  ml_top_configure_irqs(&ml_top);
  plic_smc_configure_irqs(&plic_smc);

  execute_test();

  LOG_INFO("End of ML_TOP IRQ test.");
  test_status_set(kTestStatusPassed);
}