blob: 5d19bd65054bd0c09ab4000a5d2f538f02181a60 [file] [log] [blame]
// Copyright Google Inc.
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0
#ifndef MATCHA_HW_TOP_MATCHA_SW_AUTOGEN_TOP_MATCHA_IRQ_H_
#define MATCHA_HW_TOP_MATCHA_SW_AUTOGEN_TOP_MATCHA_IRQ_H_
/**
* @file
* @brief Assembler-only Top-specific Definitions
*
* This file contains preprocessor definitions for use within assembly code.
*/
#ifdef __ASSEMBLER__
/**
* SMC PLIC Interrupt Source.
*
* Enumeration of all SMC PLIC interrupt sources. The interrupt sources belonging to
* the same peripheral are guaranteed to be consecutive.
*/
#define TOP_MATCHA_PLIC_IRQ_ID_NONE_SMC 0 /**< No Interrupt */
#define TOP_MATCHA_PLIC_IRQ_ID_SMC_UART_TX_WATERMARK 1 /**< smc_uart_tx_watermark */
#define TOP_MATCHA_PLIC_IRQ_ID_SMC_UART_RX_WATERMARK 2 /**< smc_uart_rx_watermark */
#define TOP_MATCHA_PLIC_IRQ_ID_SMC_UART_TX_EMPTY 3 /**< smc_uart_tx_empty */
#define TOP_MATCHA_PLIC_IRQ_ID_SMC_UART_RX_OVERFLOW 4 /**< smc_uart_rx_overflow */
#define TOP_MATCHA_PLIC_IRQ_ID_SMC_UART_RX_FRAME_ERR 5 /**< smc_uart_rx_frame_err */
#define TOP_MATCHA_PLIC_IRQ_ID_SMC_UART_RX_BREAK_ERR 6 /**< smc_uart_rx_break_err */
#define TOP_MATCHA_PLIC_IRQ_ID_SMC_UART_RX_TIMEOUT 7 /**< smc_uart_rx_timeout */
#define TOP_MATCHA_PLIC_IRQ_ID_SMC_UART_RX_PARITY_ERR 8 /**< smc_uart_rx_parity_err */
#define TOP_MATCHA_PLIC_IRQ_ID_RV_TIMER_SMC_TIMER_EXPIRED_HART0_TIMER0 9 /**< rv_timer_smc_timer_expired_hart0_timer0 */
#define TOP_MATCHA_PLIC_IRQ_ID_CAM_I2C_FMT_THRESHOLD 10 /**< cam_i2c_fmt_threshold */
#define TOP_MATCHA_PLIC_IRQ_ID_CAM_I2C_RX_THRESHOLD 11 /**< cam_i2c_rx_threshold */
#define TOP_MATCHA_PLIC_IRQ_ID_CAM_I2C_FMT_OVERFLOW 12 /**< cam_i2c_fmt_overflow */
#define TOP_MATCHA_PLIC_IRQ_ID_CAM_I2C_RX_OVERFLOW 13 /**< cam_i2c_rx_overflow */
#define TOP_MATCHA_PLIC_IRQ_ID_CAM_I2C_NAK 14 /**< cam_i2c_nak */
#define TOP_MATCHA_PLIC_IRQ_ID_CAM_I2C_SCL_INTERFERENCE 15 /**< cam_i2c_scl_interference */
#define TOP_MATCHA_PLIC_IRQ_ID_CAM_I2C_SDA_INTERFERENCE 16 /**< cam_i2c_sda_interference */
#define TOP_MATCHA_PLIC_IRQ_ID_CAM_I2C_STRETCH_TIMEOUT 17 /**< cam_i2c_stretch_timeout */
#define TOP_MATCHA_PLIC_IRQ_ID_CAM_I2C_SDA_UNSTABLE 18 /**< cam_i2c_sda_unstable */
#define TOP_MATCHA_PLIC_IRQ_ID_CAM_I2C_CMD_COMPLETE 19 /**< cam_i2c_cmd_complete */
#define TOP_MATCHA_PLIC_IRQ_ID_CAM_I2C_TX_STRETCH 20 /**< cam_i2c_tx_stretch */
#define TOP_MATCHA_PLIC_IRQ_ID_CAM_I2C_TX_OVERFLOW 21 /**< cam_i2c_tx_overflow */
#define TOP_MATCHA_PLIC_IRQ_ID_CAM_I2C_ACQ_FULL 22 /**< cam_i2c_acq_full */
#define TOP_MATCHA_PLIC_IRQ_ID_CAM_I2C_UNEXP_STOP 23 /**< cam_i2c_unexp_stop */
#define TOP_MATCHA_PLIC_IRQ_ID_CAM_I2C_HOST_TIMEOUT 24 /**< cam_i2c_host_timeout */
#define TOP_MATCHA_PLIC_IRQ_ID_CAM_CTRL_CAM_MOTION_DETECT 25 /**< cam_ctrl_cam_motion_detect */
#define TOP_MATCHA_PLIC_IRQ_ID_ISP_WRAPPER_ISP 26 /**< isp_wrapper_isp */
#define TOP_MATCHA_PLIC_IRQ_ID_ISP_WRAPPER_MI 27 /**< isp_wrapper_mi */
#define TOP_MATCHA_PLIC_IRQ_ID_DMA_SMC_WRITER_DONE 28 /**< dma_smc_writer_done */
#define TOP_MATCHA_PLIC_IRQ_ID_DMA_SMC_READER_DONE 29 /**< dma_smc_reader_done */
#define TOP_MATCHA_PLIC_IRQ_ID_TLUL_MAILBOX_SMC_WTIRQ 30 /**< tlul_mailbox_smc_wtirq */
#define TOP_MATCHA_PLIC_IRQ_ID_TLUL_MAILBOX_SMC_RTIRQ 31 /**< tlul_mailbox_smc_rtirq */
#define TOP_MATCHA_PLIC_IRQ_ID_TLUL_MAILBOX_SMC_EIRQ 32 /**< tlul_mailbox_smc_eirq */
#define TOP_MATCHA_PLIC_IRQ_ID_ML_TOP_HOST_REQ 33 /**< ml_top_host_req */
#define TOP_MATCHA_PLIC_IRQ_ID_ML_TOP_FINISH 34 /**< ml_top_finish */
#define TOP_MATCHA_PLIC_IRQ_ID_ML_TOP_FAULT 35 /**< ml_top_fault */
#define TOP_MATCHA_PLIC_IRQ_ID_SPI_HOST2_ERROR 36 /**< spi_host2_error */
#define TOP_MATCHA_PLIC_IRQ_ID_SPI_HOST2_SPI_EVENT 37 /**< spi_host2_spi_event */
#define TOP_MATCHA_PLIC_IRQ_ID_RV_TIMER_SMC2_TIMER_EXPIRED_HART0_TIMER0 38 /**< rv_timer_smc2_timer_expired_hart0_timer0 */
#define TOP_MATCHA_PLIC_IRQ_ID_I2S0_TX_WATERMARK 39 /**< i2s0_tx_watermark */
#define TOP_MATCHA_PLIC_IRQ_ID_I2S0_RX_WATERMARK 40 /**< i2s0_rx_watermark */
#define TOP_MATCHA_PLIC_IRQ_ID_I2S0_TX_EMPTY 41 /**< i2s0_tx_empty */
#define TOP_MATCHA_PLIC_IRQ_ID_I2S0_RX_OVERFLOW 42 /**< i2s0_rx_overflow */
#define TOP_MATCHA_PLIC_IRQ_ID_LAST_SMC 42 /**< \internal The Last Valid Interrupt ID. */
#endif // __ASSEMBLER__
#endif // MATCHA_HW_TOP_MATCHA_SW_AUTOGEN_TOP_MATCHA_IRQ_H_