hw/top_matcha/sw/autogen/top_matcha_memory.h

// Copyright lowRISC contributors.
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0

#ifndef MATCHA_HW_TOP_MATCHA_SW_AUTOGEN_TOP_MATCHA_MEMORY_H_
#define MATCHA_HW_TOP_MATCHA_SW_AUTOGEN_TOP_MATCHA_MEMORY_H_

/**
 * @file
 * @brief Assembler-only Top-Specific Definitions.
 *
 * This file contains preprocessor definitions for use within assembly code.
 *
 * These are not shared with C/C++ code because these are only allowed to be
 * preprocessor definitions, no data or type declarations are allowed. The
 * assembler is also stricter about literals (not allowing suffixes for
 * signed/unsigned which are sensible to use for unsigned values in C/C++).
 */

// Include guard for assembler
#ifdef __ASSEMBLER__


/**
 * Memory base for sram_ctrl_ret_aon_ram_ret_aon in top matcha.
 */
#define TOP_MATCHA_RAM_RET_AON_BASE_ADDR 0x40600000

/**
 * Memory size for sram_ctrl_ret_aon_ram_ret_aon in top matcha.
 */
#define TOP_MATCHA_RAM_RET_AON_SIZE_BYTES 0x1000

/**
 * Memory base for flash_ctrl_eflash in top matcha.
 */
#define TOP_MATCHA_EFLASH_BASE_ADDR 0x20000000

/**
 * Memory size for flash_ctrl_eflash in top matcha.
 */
#define TOP_MATCHA_EFLASH_SIZE_BYTES 0x100000

/**
 * Memory base for sram_ctrl_main_ram_main in top matcha.
 */
#define TOP_MATCHA_RAM_MAIN_BASE_ADDR 0x10000000

/**
 * Memory size for sram_ctrl_main_ram_main in top matcha.
 */
#define TOP_MATCHA_RAM_MAIN_SIZE_BYTES 0x20000

/**
 * Memory base for rom_ctrl_rom in top matcha.
 */
#define TOP_MATCHA_ROM_BASE_ADDR 0x00008000

/**
 * Memory size for rom_ctrl_rom in top matcha.
 */
#define TOP_MATCHA_ROM_SIZE_BYTES 0x8000

/**
 * Memory base for ml_top_ram_ml_dmem in top matcha.
 */
#define TOP_MATCHA_RAM_ML_DMEM_BASE_ADDR 0x5A000000

/**
 * Memory size for ml_top_ram_ml_dmem in top matcha.
 */
#define TOP_MATCHA_RAM_ML_DMEM_SIZE_BYTES 0x400000


/**
 * Memory base address for ram_smc in top matcha.
 */
#define TOP_MATCHA_RAM_SMC_BASE_ADDR 0x50000000

/**
 * Memory size for ram_smc in top matcha.
 */
#define TOP_MATCHA_RAM_SMC_SIZE_BYTES 0x400000


/**
 * Peripheral base address for uart0 in top matcha.
 *
 * This should be used with #mmio_region_from_addr to access the memory-mapped
 * registers associated with the peripheral (usually via a DIF).
 */
#define TOP_MATCHA_UART0_BASE_ADDR 0x40000000

/**
 * Peripheral size for uart0 in top matcha.
 *
 * This is the size (in bytes) of the peripheral's reserved memory area. All
 * memory-mapped registers associated with this peripheral should have an
 * address between #TOP_MATCHA_UART0_BASE_ADDR and
 * `TOP_MATCHA_UART0_BASE_ADDR + TOP_MATCHA_UART0_SIZE_BYTES`.
 */
#define TOP_MATCHA_UART0_SIZE_BYTES 0x40
/**
 * Peripheral base address for uart1 in top matcha.
 *
 * This should be used with #mmio_region_from_addr to access the memory-mapped
 * registers associated with the peripheral (usually via a DIF).
 */
#define TOP_MATCHA_UART1_BASE_ADDR 0x40010000

/**
 * Peripheral size for uart1 in top matcha.
 *
 * This is the size (in bytes) of the peripheral's reserved memory area. All
 * memory-mapped registers associated with this peripheral should have an
 * address between #TOP_MATCHA_UART1_BASE_ADDR and
 * `TOP_MATCHA_UART1_BASE_ADDR + TOP_MATCHA_UART1_SIZE_BYTES`.
 */
#define TOP_MATCHA_UART1_SIZE_BYTES 0x40
/**
 * Peripheral base address for uart2 in top matcha.
 *
 * This should be used with #mmio_region_from_addr to access the memory-mapped
 * registers associated with the peripheral (usually via a DIF).
 */
#define TOP_MATCHA_UART2_BASE_ADDR 0x40020000

/**
 * Peripheral size for uart2 in top matcha.
 *
 * This is the size (in bytes) of the peripheral's reserved memory area. All
 * memory-mapped registers associated with this peripheral should have an
 * address between #TOP_MATCHA_UART2_BASE_ADDR and
 * `TOP_MATCHA_UART2_BASE_ADDR + TOP_MATCHA_UART2_SIZE_BYTES`.
 */
#define TOP_MATCHA_UART2_SIZE_BYTES 0x40
/**
 * Peripheral base address for uart3 in top matcha.
 *
 * This should be used with #mmio_region_from_addr to access the memory-mapped
 * registers associated with the peripheral (usually via a DIF).
 */
#define TOP_MATCHA_UART3_BASE_ADDR 0x40030000

/**
 * Peripheral size for uart3 in top matcha.
 *
 * This is the size (in bytes) of the peripheral's reserved memory area. All
 * memory-mapped registers associated with this peripheral should have an
 * address between #TOP_MATCHA_UART3_BASE_ADDR and
 * `TOP_MATCHA_UART3_BASE_ADDR + TOP_MATCHA_UART3_SIZE_BYTES`.
 */
#define TOP_MATCHA_UART3_SIZE_BYTES 0x40
/**
 * Peripheral base address for gpio in top matcha.
 *
 * This should be used with #mmio_region_from_addr to access the memory-mapped
 * registers associated with the peripheral (usually via a DIF).
 */
#define TOP_MATCHA_GPIO_BASE_ADDR 0x40040000

/**
 * Peripheral size for gpio in top matcha.
 *
 * This is the size (in bytes) of the peripheral's reserved memory area. All
 * memory-mapped registers associated with this peripheral should have an
 * address between #TOP_MATCHA_GPIO_BASE_ADDR and
 * `TOP_MATCHA_GPIO_BASE_ADDR + TOP_MATCHA_GPIO_SIZE_BYTES`.
 */
#define TOP_MATCHA_GPIO_SIZE_BYTES 0x40
/**
 * Peripheral base address for spi_device in top matcha.
 *
 * This should be used with #mmio_region_from_addr to access the memory-mapped
 * registers associated with the peripheral (usually via a DIF).
 */
#define TOP_MATCHA_SPI_DEVICE_BASE_ADDR 0x40050000

/**
 * Peripheral size for spi_device in top matcha.
 *
 * This is the size (in bytes) of the peripheral's reserved memory area. All
 * memory-mapped registers associated with this peripheral should have an
 * address between #TOP_MATCHA_SPI_DEVICE_BASE_ADDR and
 * `TOP_MATCHA_SPI_DEVICE_BASE_ADDR + TOP_MATCHA_SPI_DEVICE_SIZE_BYTES`.
 */
#define TOP_MATCHA_SPI_DEVICE_SIZE_BYTES 0x2000
/**
 * Peripheral base address for i2c0 in top matcha.
 *
 * This should be used with #mmio_region_from_addr to access the memory-mapped
 * registers associated with the peripheral (usually via a DIF).
 */
#define TOP_MATCHA_I2C0_BASE_ADDR 0x40080000

/**
 * Peripheral size for i2c0 in top matcha.
 *
 * This is the size (in bytes) of the peripheral's reserved memory area. All
 * memory-mapped registers associated with this peripheral should have an
 * address between #TOP_MATCHA_I2C0_BASE_ADDR and
 * `TOP_MATCHA_I2C0_BASE_ADDR + TOP_MATCHA_I2C0_SIZE_BYTES`.
 */
#define TOP_MATCHA_I2C0_SIZE_BYTES 0x80
/**
 * Peripheral base address for i2c1 in top matcha.
 *
 * This should be used with #mmio_region_from_addr to access the memory-mapped
 * registers associated with the peripheral (usually via a DIF).
 */
#define TOP_MATCHA_I2C1_BASE_ADDR 0x40090000

/**
 * Peripheral size for i2c1 in top matcha.
 *
 * This is the size (in bytes) of the peripheral's reserved memory area. All
 * memory-mapped registers associated with this peripheral should have an
 * address between #TOP_MATCHA_I2C1_BASE_ADDR and
 * `TOP_MATCHA_I2C1_BASE_ADDR + TOP_MATCHA_I2C1_SIZE_BYTES`.
 */
#define TOP_MATCHA_I2C1_SIZE_BYTES 0x80
/**
 * Peripheral base address for i2c2 in top matcha.
 *
 * This should be used with #mmio_region_from_addr to access the memory-mapped
 * registers associated with the peripheral (usually via a DIF).
 */
#define TOP_MATCHA_I2C2_BASE_ADDR 0x400A0000

/**
 * Peripheral size for i2c2 in top matcha.
 *
 * This is the size (in bytes) of the peripheral's reserved memory area. All
 * memory-mapped registers associated with this peripheral should have an
 * address between #TOP_MATCHA_I2C2_BASE_ADDR and
 * `TOP_MATCHA_I2C2_BASE_ADDR + TOP_MATCHA_I2C2_SIZE_BYTES`.
 */
#define TOP_MATCHA_I2C2_SIZE_BYTES 0x80
/**
 * Peripheral base address for pattgen in top matcha.
 *
 * This should be used with #mmio_region_from_addr to access the memory-mapped
 * registers associated with the peripheral (usually via a DIF).
 */
#define TOP_MATCHA_PATTGEN_BASE_ADDR 0x400E0000

/**
 * Peripheral size for pattgen in top matcha.
 *
 * This is the size (in bytes) of the peripheral's reserved memory area. All
 * memory-mapped registers associated with this peripheral should have an
 * address between #TOP_MATCHA_PATTGEN_BASE_ADDR and
 * `TOP_MATCHA_PATTGEN_BASE_ADDR + TOP_MATCHA_PATTGEN_SIZE_BYTES`.
 */
#define TOP_MATCHA_PATTGEN_SIZE_BYTES 0x40
/**
 * Peripheral base address for rv_timer in top matcha.
 *
 * This should be used with #mmio_region_from_addr to access the memory-mapped
 * registers associated with the peripheral (usually via a DIF).
 */
#define TOP_MATCHA_RV_TIMER_BASE_ADDR 0x40100000

/**
 * Peripheral size for rv_timer in top matcha.
 *
 * This is the size (in bytes) of the peripheral's reserved memory area. All
 * memory-mapped registers associated with this peripheral should have an
 * address between #TOP_MATCHA_RV_TIMER_BASE_ADDR and
 * `TOP_MATCHA_RV_TIMER_BASE_ADDR + TOP_MATCHA_RV_TIMER_SIZE_BYTES`.
 */
#define TOP_MATCHA_RV_TIMER_SIZE_BYTES 0x200
/**
 * Peripheral base address for core device on otp_ctrl in top matcha.
 *
 * This should be used with #mmio_region_from_addr to access the memory-mapped
 * registers associated with the peripheral (usually via a DIF).
 */
#define TOP_MATCHA_OTP_CTRL_CORE_BASE_ADDR 0x40130000

/**
 * Peripheral size for core device on otp_ctrl in top matcha.
 *
 * This is the size (in bytes) of the peripheral's reserved memory area. All
 * memory-mapped registers associated with this peripheral should have an
 * address between #TOP_MATCHA_OTP_CTRL_CORE_BASE_ADDR and
 * `TOP_MATCHA_OTP_CTRL_CORE_BASE_ADDR + TOP_MATCHA_OTP_CTRL_CORE_SIZE_BYTES`.
 */
#define TOP_MATCHA_OTP_CTRL_CORE_SIZE_BYTES 0x2000
/**
 * Peripheral base address for prim device on otp_ctrl in top matcha.
 *
 * This should be used with #mmio_region_from_addr to access the memory-mapped
 * registers associated with the peripheral (usually via a DIF).
 */
#define TOP_MATCHA_OTP_CTRL_PRIM_BASE_ADDR 0x40132000

/**
 * Peripheral size for prim device on otp_ctrl in top matcha.
 *
 * This is the size (in bytes) of the peripheral's reserved memory area. All
 * memory-mapped registers associated with this peripheral should have an
 * address between #TOP_MATCHA_OTP_CTRL_PRIM_BASE_ADDR and
 * `TOP_MATCHA_OTP_CTRL_PRIM_BASE_ADDR + TOP_MATCHA_OTP_CTRL_PRIM_SIZE_BYTES`.
 */
#define TOP_MATCHA_OTP_CTRL_PRIM_SIZE_BYTES 0x20
/**
 * Peripheral base address for lc_ctrl in top matcha.
 *
 * This should be used with #mmio_region_from_addr to access the memory-mapped
 * registers associated with the peripheral (usually via a DIF).
 */
#define TOP_MATCHA_LC_CTRL_BASE_ADDR 0x40140000

/**
 * Peripheral size for lc_ctrl in top matcha.
 *
 * This is the size (in bytes) of the peripheral's reserved memory area. All
 * memory-mapped registers associated with this peripheral should have an
 * address between #TOP_MATCHA_LC_CTRL_BASE_ADDR and
 * `TOP_MATCHA_LC_CTRL_BASE_ADDR + TOP_MATCHA_LC_CTRL_SIZE_BYTES`.
 */
#define TOP_MATCHA_LC_CTRL_SIZE_BYTES 0x100
/**
 * Peripheral base address for alert_handler in top matcha.
 *
 * This should be used with #mmio_region_from_addr to access the memory-mapped
 * registers associated with the peripheral (usually via a DIF).
 */
#define TOP_MATCHA_ALERT_HANDLER_BASE_ADDR 0x40150000

/**
 * Peripheral size for alert_handler in top matcha.
 *
 * This is the size (in bytes) of the peripheral's reserved memory area. All
 * memory-mapped registers associated with this peripheral should have an
 * address between #TOP_MATCHA_ALERT_HANDLER_BASE_ADDR and
 * `TOP_MATCHA_ALERT_HANDLER_BASE_ADDR + TOP_MATCHA_ALERT_HANDLER_SIZE_BYTES`.
 */
#define TOP_MATCHA_ALERT_HANDLER_SIZE_BYTES 0x800
/**
 * Peripheral base address for spi_host0 in top matcha.
 *
 * This should be used with #mmio_region_from_addr to access the memory-mapped
 * registers associated with the peripheral (usually via a DIF).
 */
#define TOP_MATCHA_SPI_HOST0_BASE_ADDR 0x40300000

/**
 * Peripheral size for spi_host0 in top matcha.
 *
 * This is the size (in bytes) of the peripheral's reserved memory area. All
 * memory-mapped registers associated with this peripheral should have an
 * address between #TOP_MATCHA_SPI_HOST0_BASE_ADDR and
 * `TOP_MATCHA_SPI_HOST0_BASE_ADDR + TOP_MATCHA_SPI_HOST0_SIZE_BYTES`.
 */
#define TOP_MATCHA_SPI_HOST0_SIZE_BYTES 0x40
/**
 * Peripheral base address for spi_host1 in top matcha.
 *
 * This should be used with #mmio_region_from_addr to access the memory-mapped
 * registers associated with the peripheral (usually via a DIF).
 */
#define TOP_MATCHA_SPI_HOST1_BASE_ADDR 0x40310000

/**
 * Peripheral size for spi_host1 in top matcha.
 *
 * This is the size (in bytes) of the peripheral's reserved memory area. All
 * memory-mapped registers associated with this peripheral should have an
 * address between #TOP_MATCHA_SPI_HOST1_BASE_ADDR and
 * `TOP_MATCHA_SPI_HOST1_BASE_ADDR + TOP_MATCHA_SPI_HOST1_SIZE_BYTES`.
 */
#define TOP_MATCHA_SPI_HOST1_SIZE_BYTES 0x40
/**
 * Peripheral base address for usbdev in top matcha.
 *
 * This should be used with #mmio_region_from_addr to access the memory-mapped
 * registers associated with the peripheral (usually via a DIF).
 */
#define TOP_MATCHA_USBDEV_BASE_ADDR 0x40320000

/**
 * Peripheral size for usbdev in top matcha.
 *
 * This is the size (in bytes) of the peripheral's reserved memory area. All
 * memory-mapped registers associated with this peripheral should have an
 * address between #TOP_MATCHA_USBDEV_BASE_ADDR and
 * `TOP_MATCHA_USBDEV_BASE_ADDR + TOP_MATCHA_USBDEV_SIZE_BYTES`.
 */
#define TOP_MATCHA_USBDEV_SIZE_BYTES 0x1000
/**
 * Peripheral base address for pwrmgr_aon in top matcha.
 *
 * This should be used with #mmio_region_from_addr to access the memory-mapped
 * registers associated with the peripheral (usually via a DIF).
 */
#define TOP_MATCHA_PWRMGR_AON_BASE_ADDR 0x40400000

/**
 * Peripheral size for pwrmgr_aon in top matcha.
 *
 * This is the size (in bytes) of the peripheral's reserved memory area. All
 * memory-mapped registers associated with this peripheral should have an
 * address between #TOP_MATCHA_PWRMGR_AON_BASE_ADDR and
 * `TOP_MATCHA_PWRMGR_AON_BASE_ADDR + TOP_MATCHA_PWRMGR_AON_SIZE_BYTES`.
 */
#define TOP_MATCHA_PWRMGR_AON_SIZE_BYTES 0x80
/**
 * Peripheral base address for rstmgr_aon in top matcha.
 *
 * This should be used with #mmio_region_from_addr to access the memory-mapped
 * registers associated with the peripheral (usually via a DIF).
 */
#define TOP_MATCHA_RSTMGR_AON_BASE_ADDR 0x40410000

/**
 * Peripheral size for rstmgr_aon in top matcha.
 *
 * This is the size (in bytes) of the peripheral's reserved memory area. All
 * memory-mapped registers associated with this peripheral should have an
 * address between #TOP_MATCHA_RSTMGR_AON_BASE_ADDR and
 * `TOP_MATCHA_RSTMGR_AON_BASE_ADDR + TOP_MATCHA_RSTMGR_AON_SIZE_BYTES`.
 */
#define TOP_MATCHA_RSTMGR_AON_SIZE_BYTES 0x100
/**
 * Peripheral base address for clkmgr_aon in top matcha.
 *
 * This should be used with #mmio_region_from_addr to access the memory-mapped
 * registers associated with the peripheral (usually via a DIF).
 */
#define TOP_MATCHA_CLKMGR_AON_BASE_ADDR 0x40420000

/**
 * Peripheral size for clkmgr_aon in top matcha.
 *
 * This is the size (in bytes) of the peripheral's reserved memory area. All
 * memory-mapped registers associated with this peripheral should have an
 * address between #TOP_MATCHA_CLKMGR_AON_BASE_ADDR and
 * `TOP_MATCHA_CLKMGR_AON_BASE_ADDR + TOP_MATCHA_CLKMGR_AON_SIZE_BYTES`.
 */
#define TOP_MATCHA_CLKMGR_AON_SIZE_BYTES 0x80
/**
 * Peripheral base address for sysrst_ctrl_aon in top matcha.
 *
 * This should be used with #mmio_region_from_addr to access the memory-mapped
 * registers associated with the peripheral (usually via a DIF).
 */
#define TOP_MATCHA_SYSRST_CTRL_AON_BASE_ADDR 0x40430000

/**
 * Peripheral size for sysrst_ctrl_aon in top matcha.
 *
 * This is the size (in bytes) of the peripheral's reserved memory area. All
 * memory-mapped registers associated with this peripheral should have an
 * address between #TOP_MATCHA_SYSRST_CTRL_AON_BASE_ADDR and
 * `TOP_MATCHA_SYSRST_CTRL_AON_BASE_ADDR + TOP_MATCHA_SYSRST_CTRL_AON_SIZE_BYTES`.
 */
#define TOP_MATCHA_SYSRST_CTRL_AON_SIZE_BYTES 0x100
/**
 * Peripheral base address for adc_ctrl_aon in top matcha.
 *
 * This should be used with #mmio_region_from_addr to access the memory-mapped
 * registers associated with the peripheral (usually via a DIF).
 */
#define TOP_MATCHA_ADC_CTRL_AON_BASE_ADDR 0x40440000

/**
 * Peripheral size for adc_ctrl_aon in top matcha.
 *
 * This is the size (in bytes) of the peripheral's reserved memory area. All
 * memory-mapped registers associated with this peripheral should have an
 * address between #TOP_MATCHA_ADC_CTRL_AON_BASE_ADDR and
 * `TOP_MATCHA_ADC_CTRL_AON_BASE_ADDR + TOP_MATCHA_ADC_CTRL_AON_SIZE_BYTES`.
 */
#define TOP_MATCHA_ADC_CTRL_AON_SIZE_BYTES 0x80
/**
 * Peripheral base address for pwm_aon in top matcha.
 *
 * This should be used with #mmio_region_from_addr to access the memory-mapped
 * registers associated with the peripheral (usually via a DIF).
 */
#define TOP_MATCHA_PWM_AON_BASE_ADDR 0x40450000

/**
 * Peripheral size for pwm_aon in top matcha.
 *
 * This is the size (in bytes) of the peripheral's reserved memory area. All
 * memory-mapped registers associated with this peripheral should have an
 * address between #TOP_MATCHA_PWM_AON_BASE_ADDR and
 * `TOP_MATCHA_PWM_AON_BASE_ADDR + TOP_MATCHA_PWM_AON_SIZE_BYTES`.
 */
#define TOP_MATCHA_PWM_AON_SIZE_BYTES 0x80
/**
 * Peripheral base address for pinmux_aon in top matcha.
 *
 * This should be used with #mmio_region_from_addr to access the memory-mapped
 * registers associated with the peripheral (usually via a DIF).
 */
#define TOP_MATCHA_PINMUX_AON_BASE_ADDR 0x40460000

/**
 * Peripheral size for pinmux_aon in top matcha.
 *
 * This is the size (in bytes) of the peripheral's reserved memory area. All
 * memory-mapped registers associated with this peripheral should have an
 * address between #TOP_MATCHA_PINMUX_AON_BASE_ADDR and
 * `TOP_MATCHA_PINMUX_AON_BASE_ADDR + TOP_MATCHA_PINMUX_AON_SIZE_BYTES`.
 */
#define TOP_MATCHA_PINMUX_AON_SIZE_BYTES 0x1000
/**
 * Peripheral base address for aon_timer_aon in top matcha.
 *
 * This should be used with #mmio_region_from_addr to access the memory-mapped
 * registers associated with the peripheral (usually via a DIF).
 */
#define TOP_MATCHA_AON_TIMER_AON_BASE_ADDR 0x40470000

/**
 * Peripheral size for aon_timer_aon in top matcha.
 *
 * This is the size (in bytes) of the peripheral's reserved memory area. All
 * memory-mapped registers associated with this peripheral should have an
 * address between #TOP_MATCHA_AON_TIMER_AON_BASE_ADDR and
 * `TOP_MATCHA_AON_TIMER_AON_BASE_ADDR + TOP_MATCHA_AON_TIMER_AON_SIZE_BYTES`.
 */
#define TOP_MATCHA_AON_TIMER_AON_SIZE_BYTES 0x40
/**
 * Peripheral base address for ast in top matcha.
 *
 * This should be used with #mmio_region_from_addr to access the memory-mapped
 * registers associated with the peripheral (usually via a DIF).
 */
#define TOP_MATCHA_AST_BASE_ADDR 0x40480000

/**
 * Peripheral size for ast in top matcha.
 *
 * This is the size (in bytes) of the peripheral's reserved memory area. All
 * memory-mapped registers associated with this peripheral should have an
 * address between #TOP_MATCHA_AST_BASE_ADDR and
 * `TOP_MATCHA_AST_BASE_ADDR + TOP_MATCHA_AST_SIZE_BYTES`.
 */
#define TOP_MATCHA_AST_SIZE_BYTES 0x400
/**
 * Peripheral base address for sensor_ctrl in top matcha.
 *
 * This should be used with #mmio_region_from_addr to access the memory-mapped
 * registers associated with the peripheral (usually via a DIF).
 */
#define TOP_MATCHA_SENSOR_CTRL_BASE_ADDR 0x40490000

/**
 * Peripheral size for sensor_ctrl in top matcha.
 *
 * This is the size (in bytes) of the peripheral's reserved memory area. All
 * memory-mapped registers associated with this peripheral should have an
 * address between #TOP_MATCHA_SENSOR_CTRL_BASE_ADDR and
 * `TOP_MATCHA_SENSOR_CTRL_BASE_ADDR + TOP_MATCHA_SENSOR_CTRL_SIZE_BYTES`.
 */
#define TOP_MATCHA_SENSOR_CTRL_SIZE_BYTES 0x40
/**
 * Peripheral base address for regs device on sram_ctrl_ret_aon in top matcha.
 *
 * This should be used with #mmio_region_from_addr to access the memory-mapped
 * registers associated with the peripheral (usually via a DIF).
 */
#define TOP_MATCHA_SRAM_CTRL_RET_AON_REGS_BASE_ADDR 0x40500000

/**
 * Peripheral size for regs device on sram_ctrl_ret_aon in top matcha.
 *
 * This is the size (in bytes) of the peripheral's reserved memory area. All
 * memory-mapped registers associated with this peripheral should have an
 * address between #TOP_MATCHA_SRAM_CTRL_RET_AON_REGS_BASE_ADDR and
 * `TOP_MATCHA_SRAM_CTRL_RET_AON_REGS_BASE_ADDR + TOP_MATCHA_SRAM_CTRL_RET_AON_REGS_SIZE_BYTES`.
 */
#define TOP_MATCHA_SRAM_CTRL_RET_AON_REGS_SIZE_BYTES 0x20
/**
 * Peripheral base address for ram device on sram_ctrl_ret_aon in top matcha.
 *
 * This should be used with #mmio_region_from_addr to access the memory-mapped
 * registers associated with the peripheral (usually via a DIF).
 */
#define TOP_MATCHA_SRAM_CTRL_RET_AON_RAM_BASE_ADDR 0x40600000

/**
 * Peripheral size for ram device on sram_ctrl_ret_aon in top matcha.
 *
 * This is the size (in bytes) of the peripheral's reserved memory area. All
 * memory-mapped registers associated with this peripheral should have an
 * address between #TOP_MATCHA_SRAM_CTRL_RET_AON_RAM_BASE_ADDR and
 * `TOP_MATCHA_SRAM_CTRL_RET_AON_RAM_BASE_ADDR + TOP_MATCHA_SRAM_CTRL_RET_AON_RAM_SIZE_BYTES`.
 */
#define TOP_MATCHA_SRAM_CTRL_RET_AON_RAM_SIZE_BYTES 0x1000
/**
 * Peripheral base address for core device on flash_ctrl in top matcha.
 *
 * This should be used with #mmio_region_from_addr to access the memory-mapped
 * registers associated with the peripheral (usually via a DIF).
 */
#define TOP_MATCHA_FLASH_CTRL_CORE_BASE_ADDR 0x41000000

/**
 * Peripheral size for core device on flash_ctrl in top matcha.
 *
 * This is the size (in bytes) of the peripheral's reserved memory area. All
 * memory-mapped registers associated with this peripheral should have an
 * address between #TOP_MATCHA_FLASH_CTRL_CORE_BASE_ADDR and
 * `TOP_MATCHA_FLASH_CTRL_CORE_BASE_ADDR + TOP_MATCHA_FLASH_CTRL_CORE_SIZE_BYTES`.
 */
#define TOP_MATCHA_FLASH_CTRL_CORE_SIZE_BYTES 0x200
/**
 * Peripheral base address for prim device on flash_ctrl in top matcha.
 *
 * This should be used with #mmio_region_from_addr to access the memory-mapped
 * registers associated with the peripheral (usually via a DIF).
 */
#define TOP_MATCHA_FLASH_CTRL_PRIM_BASE_ADDR 0x41008000

/**
 * Peripheral size for prim device on flash_ctrl in top matcha.
 *
 * This is the size (in bytes) of the peripheral's reserved memory area. All
 * memory-mapped registers associated with this peripheral should have an
 * address between #TOP_MATCHA_FLASH_CTRL_PRIM_BASE_ADDR and
 * `TOP_MATCHA_FLASH_CTRL_PRIM_BASE_ADDR + TOP_MATCHA_FLASH_CTRL_PRIM_SIZE_BYTES`.
 */
#define TOP_MATCHA_FLASH_CTRL_PRIM_SIZE_BYTES 0x80
/**
 * Peripheral base address for mem device on flash_ctrl in top matcha.
 *
 * This should be used with #mmio_region_from_addr to access the memory-mapped
 * registers associated with the peripheral (usually via a DIF).
 */
#define TOP_MATCHA_FLASH_CTRL_MEM_BASE_ADDR 0x20000000

/**
 * Peripheral size for mem device on flash_ctrl in top matcha.
 *
 * This is the size (in bytes) of the peripheral's reserved memory area. All
 * memory-mapped registers associated with this peripheral should have an
 * address between #TOP_MATCHA_FLASH_CTRL_MEM_BASE_ADDR and
 * `TOP_MATCHA_FLASH_CTRL_MEM_BASE_ADDR + TOP_MATCHA_FLASH_CTRL_MEM_SIZE_BYTES`.
 */
#define TOP_MATCHA_FLASH_CTRL_MEM_SIZE_BYTES 0x100000
/**
 * Peripheral base address for regs device on rv_dm in top matcha.
 *
 * This should be used with #mmio_region_from_addr to access the memory-mapped
 * registers associated with the peripheral (usually via a DIF).
 */
#define TOP_MATCHA_RV_DM_REGS_BASE_ADDR 0x6000

/**
 * Peripheral size for regs device on rv_dm in top matcha.
 *
 * This is the size (in bytes) of the peripheral's reserved memory area. All
 * memory-mapped registers associated with this peripheral should have an
 * address between #TOP_MATCHA_RV_DM_REGS_BASE_ADDR and
 * `TOP_MATCHA_RV_DM_REGS_BASE_ADDR + TOP_MATCHA_RV_DM_REGS_SIZE_BYTES`.
 */
#define TOP_MATCHA_RV_DM_REGS_SIZE_BYTES 0x4
/**
 * Peripheral base address for mem device on rv_dm in top matcha.
 *
 * This should be used with #mmio_region_from_addr to access the memory-mapped
 * registers associated with the peripheral (usually via a DIF).
 */
#define TOP_MATCHA_RV_DM_MEM_BASE_ADDR 0x4000

/**
 * Peripheral size for mem device on rv_dm in top matcha.
 *
 * This is the size (in bytes) of the peripheral's reserved memory area. All
 * memory-mapped registers associated with this peripheral should have an
 * address between #TOP_MATCHA_RV_DM_MEM_BASE_ADDR and
 * `TOP_MATCHA_RV_DM_MEM_BASE_ADDR + TOP_MATCHA_RV_DM_MEM_SIZE_BYTES`.
 */
#define TOP_MATCHA_RV_DM_MEM_SIZE_BYTES 0x1000
/**
 * Peripheral base address for rv_plic in top matcha.
 *
 * This should be used with #mmio_region_from_addr to access the memory-mapped
 * registers associated with the peripheral (usually via a DIF).
 */
#define TOP_MATCHA_RV_PLIC_BASE_ADDR 0x48000000

/**
 * Peripheral size for rv_plic in top matcha.
 *
 * This is the size (in bytes) of the peripheral's reserved memory area. All
 * memory-mapped registers associated with this peripheral should have an
 * address between #TOP_MATCHA_RV_PLIC_BASE_ADDR and
 * `TOP_MATCHA_RV_PLIC_BASE_ADDR + TOP_MATCHA_RV_PLIC_SIZE_BYTES`.
 */
#define TOP_MATCHA_RV_PLIC_SIZE_BYTES 0x8000000
/**
 * Peripheral base address for aes in top matcha.
 *
 * This should be used with #mmio_region_from_addr to access the memory-mapped
 * registers associated with the peripheral (usually via a DIF).
 */
#define TOP_MATCHA_AES_BASE_ADDR 0x41100000

/**
 * Peripheral size for aes in top matcha.
 *
 * This is the size (in bytes) of the peripheral's reserved memory area. All
 * memory-mapped registers associated with this peripheral should have an
 * address between #TOP_MATCHA_AES_BASE_ADDR and
 * `TOP_MATCHA_AES_BASE_ADDR + TOP_MATCHA_AES_SIZE_BYTES`.
 */
#define TOP_MATCHA_AES_SIZE_BYTES 0x100
/**
 * Peripheral base address for hmac in top matcha.
 *
 * This should be used with #mmio_region_from_addr to access the memory-mapped
 * registers associated with the peripheral (usually via a DIF).
 */
#define TOP_MATCHA_HMAC_BASE_ADDR 0x41110000

/**
 * Peripheral size for hmac in top matcha.
 *
 * This is the size (in bytes) of the peripheral's reserved memory area. All
 * memory-mapped registers associated with this peripheral should have an
 * address between #TOP_MATCHA_HMAC_BASE_ADDR and
 * `TOP_MATCHA_HMAC_BASE_ADDR + TOP_MATCHA_HMAC_SIZE_BYTES`.
 */
#define TOP_MATCHA_HMAC_SIZE_BYTES 0x1000
/**
 * Peripheral base address for kmac in top matcha.
 *
 * This should be used with #mmio_region_from_addr to access the memory-mapped
 * registers associated with the peripheral (usually via a DIF).
 */
#define TOP_MATCHA_KMAC_BASE_ADDR 0x41120000

/**
 * Peripheral size for kmac in top matcha.
 *
 * This is the size (in bytes) of the peripheral's reserved memory area. All
 * memory-mapped registers associated with this peripheral should have an
 * address between #TOP_MATCHA_KMAC_BASE_ADDR and
 * `TOP_MATCHA_KMAC_BASE_ADDR + TOP_MATCHA_KMAC_SIZE_BYTES`.
 */
#define TOP_MATCHA_KMAC_SIZE_BYTES 0x1000
/**
 * Peripheral base address for otbn in top matcha.
 *
 * This should be used with #mmio_region_from_addr to access the memory-mapped
 * registers associated with the peripheral (usually via a DIF).
 */
#define TOP_MATCHA_OTBN_BASE_ADDR 0x41130000

/**
 * Peripheral size for otbn in top matcha.
 *
 * This is the size (in bytes) of the peripheral's reserved memory area. All
 * memory-mapped registers associated with this peripheral should have an
 * address between #TOP_MATCHA_OTBN_BASE_ADDR and
 * `TOP_MATCHA_OTBN_BASE_ADDR + TOP_MATCHA_OTBN_SIZE_BYTES`.
 */
#define TOP_MATCHA_OTBN_SIZE_BYTES 0x10000
/**
 * Peripheral base address for keymgr in top matcha.
 *
 * This should be used with #mmio_region_from_addr to access the memory-mapped
 * registers associated with the peripheral (usually via a DIF).
 */
#define TOP_MATCHA_KEYMGR_BASE_ADDR 0x41140000

/**
 * Peripheral size for keymgr in top matcha.
 *
 * This is the size (in bytes) of the peripheral's reserved memory area. All
 * memory-mapped registers associated with this peripheral should have an
 * address between #TOP_MATCHA_KEYMGR_BASE_ADDR and
 * `TOP_MATCHA_KEYMGR_BASE_ADDR + TOP_MATCHA_KEYMGR_SIZE_BYTES`.
 */
#define TOP_MATCHA_KEYMGR_SIZE_BYTES 0x100
/**
 * Peripheral base address for csrng in top matcha.
 *
 * This should be used with #mmio_region_from_addr to access the memory-mapped
 * registers associated with the peripheral (usually via a DIF).
 */
#define TOP_MATCHA_CSRNG_BASE_ADDR 0x41150000

/**
 * Peripheral size for csrng in top matcha.
 *
 * This is the size (in bytes) of the peripheral's reserved memory area. All
 * memory-mapped registers associated with this peripheral should have an
 * address between #TOP_MATCHA_CSRNG_BASE_ADDR and
 * `TOP_MATCHA_CSRNG_BASE_ADDR + TOP_MATCHA_CSRNG_SIZE_BYTES`.
 */
#define TOP_MATCHA_CSRNG_SIZE_BYTES 0x80
/**
 * Peripheral base address for entropy_src in top matcha.
 *
 * This should be used with #mmio_region_from_addr to access the memory-mapped
 * registers associated with the peripheral (usually via a DIF).
 */
#define TOP_MATCHA_ENTROPY_SRC_BASE_ADDR 0x41160000

/**
 * Peripheral size for entropy_src in top matcha.
 *
 * This is the size (in bytes) of the peripheral's reserved memory area. All
 * memory-mapped registers associated with this peripheral should have an
 * address between #TOP_MATCHA_ENTROPY_SRC_BASE_ADDR and
 * `TOP_MATCHA_ENTROPY_SRC_BASE_ADDR + TOP_MATCHA_ENTROPY_SRC_SIZE_BYTES`.
 */
#define TOP_MATCHA_ENTROPY_SRC_SIZE_BYTES 0x100
/**
 * Peripheral base address for edn0 in top matcha.
 *
 * This should be used with #mmio_region_from_addr to access the memory-mapped
 * registers associated with the peripheral (usually via a DIF).
 */
#define TOP_MATCHA_EDN0_BASE_ADDR 0x41170000

/**
 * Peripheral size for edn0 in top matcha.
 *
 * This is the size (in bytes) of the peripheral's reserved memory area. All
 * memory-mapped registers associated with this peripheral should have an
 * address between #TOP_MATCHA_EDN0_BASE_ADDR and
 * `TOP_MATCHA_EDN0_BASE_ADDR + TOP_MATCHA_EDN0_SIZE_BYTES`.
 */
#define TOP_MATCHA_EDN0_SIZE_BYTES 0x80
/**
 * Peripheral base address for edn1 in top matcha.
 *
 * This should be used with #mmio_region_from_addr to access the memory-mapped
 * registers associated with the peripheral (usually via a DIF).
 */
#define TOP_MATCHA_EDN1_BASE_ADDR 0x41180000

/**
 * Peripheral size for edn1 in top matcha.
 *
 * This is the size (in bytes) of the peripheral's reserved memory area. All
 * memory-mapped registers associated with this peripheral should have an
 * address between #TOP_MATCHA_EDN1_BASE_ADDR and
 * `TOP_MATCHA_EDN1_BASE_ADDR + TOP_MATCHA_EDN1_SIZE_BYTES`.
 */
#define TOP_MATCHA_EDN1_SIZE_BYTES 0x80
/**
 * Peripheral base address for regs device on sram_ctrl_main in top matcha.
 *
 * This should be used with #mmio_region_from_addr to access the memory-mapped
 * registers associated with the peripheral (usually via a DIF).
 */
#define TOP_MATCHA_SRAM_CTRL_MAIN_REGS_BASE_ADDR 0x411C0000

/**
 * Peripheral size for regs device on sram_ctrl_main in top matcha.
 *
 * This is the size (in bytes) of the peripheral's reserved memory area. All
 * memory-mapped registers associated with this peripheral should have an
 * address between #TOP_MATCHA_SRAM_CTRL_MAIN_REGS_BASE_ADDR and
 * `TOP_MATCHA_SRAM_CTRL_MAIN_REGS_BASE_ADDR + TOP_MATCHA_SRAM_CTRL_MAIN_REGS_SIZE_BYTES`.
 */
#define TOP_MATCHA_SRAM_CTRL_MAIN_REGS_SIZE_BYTES 0x20
/**
 * Peripheral base address for ram device on sram_ctrl_main in top matcha.
 *
 * This should be used with #mmio_region_from_addr to access the memory-mapped
 * registers associated with the peripheral (usually via a DIF).
 */
#define TOP_MATCHA_SRAM_CTRL_MAIN_RAM_BASE_ADDR 0x10000000

/**
 * Peripheral size for ram device on sram_ctrl_main in top matcha.
 *
 * This is the size (in bytes) of the peripheral's reserved memory area. All
 * memory-mapped registers associated with this peripheral should have an
 * address between #TOP_MATCHA_SRAM_CTRL_MAIN_RAM_BASE_ADDR and
 * `TOP_MATCHA_SRAM_CTRL_MAIN_RAM_BASE_ADDR + TOP_MATCHA_SRAM_CTRL_MAIN_RAM_SIZE_BYTES`.
 */
#define TOP_MATCHA_SRAM_CTRL_MAIN_RAM_SIZE_BYTES 0x20000
/**
 * Peripheral base address for regs device on rom_ctrl in top matcha.
 *
 * This should be used with #mmio_region_from_addr to access the memory-mapped
 * registers associated with the peripheral (usually via a DIF).
 */
#define TOP_MATCHA_ROM_CTRL_REGS_BASE_ADDR 0x411E0000

/**
 * Peripheral size for regs device on rom_ctrl in top matcha.
 *
 * This is the size (in bytes) of the peripheral's reserved memory area. All
 * memory-mapped registers associated with this peripheral should have an
 * address between #TOP_MATCHA_ROM_CTRL_REGS_BASE_ADDR and
 * `TOP_MATCHA_ROM_CTRL_REGS_BASE_ADDR + TOP_MATCHA_ROM_CTRL_REGS_SIZE_BYTES`.
 */
#define TOP_MATCHA_ROM_CTRL_REGS_SIZE_BYTES 0x80
/**
 * Peripheral base address for rom device on rom_ctrl in top matcha.
 *
 * This should be used with #mmio_region_from_addr to access the memory-mapped
 * registers associated with the peripheral (usually via a DIF).
 */
#define TOP_MATCHA_ROM_CTRL_ROM_BASE_ADDR 0x8000

/**
 * Peripheral size for rom device on rom_ctrl in top matcha.
 *
 * This is the size (in bytes) of the peripheral's reserved memory area. All
 * memory-mapped registers associated with this peripheral should have an
 * address between #TOP_MATCHA_ROM_CTRL_ROM_BASE_ADDR and
 * `TOP_MATCHA_ROM_CTRL_ROM_BASE_ADDR + TOP_MATCHA_ROM_CTRL_ROM_SIZE_BYTES`.
 */
#define TOP_MATCHA_ROM_CTRL_ROM_SIZE_BYTES 0x8000
/**
 * Peripheral base address for cfg device on rv_core_ibex_sec in top matcha.
 *
 * This should be used with #mmio_region_from_addr to access the memory-mapped
 * registers associated with the peripheral (usually via a DIF).
 */
#define TOP_MATCHA_RV_CORE_IBEX_SEC_CFG_BASE_ADDR 0x411F0000

/**
 * Peripheral size for cfg device on rv_core_ibex_sec in top matcha.
 *
 * This is the size (in bytes) of the peripheral's reserved memory area. All
 * memory-mapped registers associated with this peripheral should have an
 * address between #TOP_MATCHA_RV_CORE_IBEX_SEC_CFG_BASE_ADDR and
 * `TOP_MATCHA_RV_CORE_IBEX_SEC_CFG_BASE_ADDR + TOP_MATCHA_RV_CORE_IBEX_SEC_CFG_SIZE_BYTES`.
 */
#define TOP_MATCHA_RV_CORE_IBEX_SEC_CFG_SIZE_BYTES 0x100
/**
 * Peripheral base address for dma0 in top matcha.
 *
 * This should be used with #mmio_region_from_addr to access the memory-mapped
 * registers associated with the peripheral (usually via a DIF).
 */
#define TOP_MATCHA_DMA0_BASE_ADDR 0x40200000

/**
 * Peripheral size for dma0 in top matcha.
 *
 * This is the size (in bytes) of the peripheral's reserved memory area. All
 * memory-mapped registers associated with this peripheral should have an
 * address between #TOP_MATCHA_DMA0_BASE_ADDR and
 * `TOP_MATCHA_DMA0_BASE_ADDR + TOP_MATCHA_DMA0_SIZE_BYTES`.
 */
#define TOP_MATCHA_DMA0_SIZE_BYTES 0x40
/**
 * Peripheral base address for smc_uart in top matcha.
 *
 * This should be used with #mmio_region_from_addr to access the memory-mapped
 * registers associated with the peripheral (usually via a DIF).
 */
#define TOP_MATCHA_SMC_UART_BASE_ADDR 0x54000000

/**
 * Peripheral size for smc_uart in top matcha.
 *
 * This is the size (in bytes) of the peripheral's reserved memory area. All
 * memory-mapped registers associated with this peripheral should have an
 * address between #TOP_MATCHA_SMC_UART_BASE_ADDR and
 * `TOP_MATCHA_SMC_UART_BASE_ADDR + TOP_MATCHA_SMC_UART_SIZE_BYTES`.
 */
#define TOP_MATCHA_SMC_UART_SIZE_BYTES 0x40
/**
 * Peripheral base address for rv_timer_smc in top matcha.
 *
 * This should be used with #mmio_region_from_addr to access the memory-mapped
 * registers associated with the peripheral (usually via a DIF).
 */
#define TOP_MATCHA_RV_TIMER_SMC_BASE_ADDR 0x54010000

/**
 * Peripheral size for rv_timer_smc in top matcha.
 *
 * This is the size (in bytes) of the peripheral's reserved memory area. All
 * memory-mapped registers associated with this peripheral should have an
 * address between #TOP_MATCHA_RV_TIMER_SMC_BASE_ADDR and
 * `TOP_MATCHA_RV_TIMER_SMC_BASE_ADDR + TOP_MATCHA_RV_TIMER_SMC_SIZE_BYTES`.
 */
#define TOP_MATCHA_RV_TIMER_SMC_SIZE_BYTES 0x200
/**
 * Peripheral base address for smc_ctrl in top matcha.
 *
 * This should be used with #mmio_region_from_addr to access the memory-mapped
 * registers associated with the peripheral (usually via a DIF).
 */
#define TOP_MATCHA_SMC_CTRL_BASE_ADDR 0x54020000

/**
 * Peripheral size for smc_ctrl in top matcha.
 *
 * This is the size (in bytes) of the peripheral's reserved memory area. All
 * memory-mapped registers associated with this peripheral should have an
 * address between #TOP_MATCHA_SMC_CTRL_BASE_ADDR and
 * `TOP_MATCHA_SMC_CTRL_BASE_ADDR + TOP_MATCHA_SMC_CTRL_SIZE_BYTES`.
 */
#define TOP_MATCHA_SMC_CTRL_SIZE_BYTES 0x8
/**
 * Peripheral base address for cam_i2c in top matcha.
 *
 * This should be used with #mmio_region_from_addr to access the memory-mapped
 * registers associated with the peripheral (usually via a DIF).
 */
#define TOP_MATCHA_CAM_I2C_BASE_ADDR 0x54040000

/**
 * Peripheral size for cam_i2c in top matcha.
 *
 * This is the size (in bytes) of the peripheral's reserved memory area. All
 * memory-mapped registers associated with this peripheral should have an
 * address between #TOP_MATCHA_CAM_I2C_BASE_ADDR and
 * `TOP_MATCHA_CAM_I2C_BASE_ADDR + TOP_MATCHA_CAM_I2C_SIZE_BYTES`.
 */
#define TOP_MATCHA_CAM_I2C_SIZE_BYTES 0x80
/**
 * Peripheral base address for cam_ctrl in top matcha.
 *
 * This should be used with #mmio_region_from_addr to access the memory-mapped
 * registers associated with the peripheral (usually via a DIF).
 */
#define TOP_MATCHA_CAM_CTRL_BASE_ADDR 0x54050000

/**
 * Peripheral size for cam_ctrl in top matcha.
 *
 * This is the size (in bytes) of the peripheral's reserved memory area. All
 * memory-mapped registers associated with this peripheral should have an
 * address between #TOP_MATCHA_CAM_CTRL_BASE_ADDR and
 * `TOP_MATCHA_CAM_CTRL_BASE_ADDR + TOP_MATCHA_CAM_CTRL_SIZE_BYTES`.
 */
#define TOP_MATCHA_CAM_CTRL_SIZE_BYTES 0x10
/**
 * Peripheral base address for isp_wrapper in top matcha.
 *
 * This should be used with #mmio_region_from_addr to access the memory-mapped
 * registers associated with the peripheral (usually via a DIF).
 */
#define TOP_MATCHA_ISP_WRAPPER_BASE_ADDR 0x54060000

/**
 * Peripheral size for isp_wrapper in top matcha.
 *
 * This is the size (in bytes) of the peripheral's reserved memory area. All
 * memory-mapped registers associated with this peripheral should have an
 * address between #TOP_MATCHA_ISP_WRAPPER_BASE_ADDR and
 * `TOP_MATCHA_ISP_WRAPPER_BASE_ADDR + TOP_MATCHA_ISP_WRAPPER_SIZE_BYTES`.
 */
#define TOP_MATCHA_ISP_WRAPPER_SIZE_BYTES 0x1000
/**
 * Peripheral base address for dma_smc in top matcha.
 *
 * This should be used with #mmio_region_from_addr to access the memory-mapped
 * registers associated with the peripheral (usually via a DIF).
 */
#define TOP_MATCHA_DMA_SMC_BASE_ADDR 0x54070000

/**
 * Peripheral size for dma_smc in top matcha.
 *
 * This is the size (in bytes) of the peripheral's reserved memory area. All
 * memory-mapped registers associated with this peripheral should have an
 * address between #TOP_MATCHA_DMA_SMC_BASE_ADDR and
 * `TOP_MATCHA_DMA_SMC_BASE_ADDR + TOP_MATCHA_DMA_SMC_SIZE_BYTES`.
 */
#define TOP_MATCHA_DMA_SMC_SIZE_BYTES 0x40
/**
 * Peripheral base address for rv_plic_smc in top matcha.
 *
 * This should be used with #mmio_region_from_addr to access the memory-mapped
 * registers associated with the peripheral (usually via a DIF).
 */
#define TOP_MATCHA_RV_PLIC_SMC_BASE_ADDR 0x60000000

/**
 * Peripheral size for rv_plic_smc in top matcha.
 *
 * This is the size (in bytes) of the peripheral's reserved memory area. All
 * memory-mapped registers associated with this peripheral should have an
 * address between #TOP_MATCHA_RV_PLIC_SMC_BASE_ADDR and
 * `TOP_MATCHA_RV_PLIC_SMC_BASE_ADDR + TOP_MATCHA_RV_PLIC_SMC_SIZE_BYTES`.
 */
#define TOP_MATCHA_RV_PLIC_SMC_SIZE_BYTES 0x8000000
/**
 * Peripheral base address for tlul_mailbox_sec in top matcha.
 *
 * This should be used with #mmio_region_from_addr to access the memory-mapped
 * registers associated with the peripheral (usually via a DIF).
 */
#define TOP_MATCHA_TLUL_MAILBOX_SEC_BASE_ADDR 0x40800000

/**
 * Peripheral size for tlul_mailbox_sec in top matcha.
 *
 * This is the size (in bytes) of the peripheral's reserved memory area. All
 * memory-mapped registers associated with this peripheral should have an
 * address between #TOP_MATCHA_TLUL_MAILBOX_SEC_BASE_ADDR and
 * `TOP_MATCHA_TLUL_MAILBOX_SEC_BASE_ADDR + TOP_MATCHA_TLUL_MAILBOX_SEC_SIZE_BYTES`.
 */
#define TOP_MATCHA_TLUL_MAILBOX_SEC_SIZE_BYTES 0x40
/**
 * Peripheral base address for tlul_mailbox_smc in top matcha.
 *
 * This should be used with #mmio_region_from_addr to access the memory-mapped
 * registers associated with the peripheral (usually via a DIF).
 */
#define TOP_MATCHA_TLUL_MAILBOX_SMC_BASE_ADDR 0x540F1000

/**
 * Peripheral size for tlul_mailbox_smc in top matcha.
 *
 * This is the size (in bytes) of the peripheral's reserved memory area. All
 * memory-mapped registers associated with this peripheral should have an
 * address between #TOP_MATCHA_TLUL_MAILBOX_SMC_BASE_ADDR and
 * `TOP_MATCHA_TLUL_MAILBOX_SMC_BASE_ADDR + TOP_MATCHA_TLUL_MAILBOX_SMC_SIZE_BYTES`.
 */
#define TOP_MATCHA_TLUL_MAILBOX_SMC_SIZE_BYTES 0x40
/**
 * Peripheral base address for core device on ml_top in top matcha.
 *
 * This should be used with #mmio_region_from_addr to access the memory-mapped
 * registers associated with the peripheral (usually via a DIF).
 */
#define TOP_MATCHA_ML_TOP_CORE_BASE_ADDR 0x5C000000

/**
 * Peripheral size for core device on ml_top in top matcha.
 *
 * This is the size (in bytes) of the peripheral's reserved memory area. All
 * memory-mapped registers associated with this peripheral should have an
 * address between #TOP_MATCHA_ML_TOP_CORE_BASE_ADDR and
 * `TOP_MATCHA_ML_TOP_CORE_BASE_ADDR + TOP_MATCHA_ML_TOP_CORE_SIZE_BYTES`.
 */
#define TOP_MATCHA_ML_TOP_CORE_SIZE_BYTES 0x40
/**
 * Peripheral base address for dmem device on ml_top in top matcha.
 *
 * This should be used with #mmio_region_from_addr to access the memory-mapped
 * registers associated with the peripheral (usually via a DIF).
 */
#define TOP_MATCHA_ML_TOP_DMEM_BASE_ADDR 0x5A000000

/**
 * Peripheral size for dmem device on ml_top in top matcha.
 *
 * This is the size (in bytes) of the peripheral's reserved memory area. All
 * memory-mapped registers associated with this peripheral should have an
 * address between #TOP_MATCHA_ML_TOP_DMEM_BASE_ADDR and
 * `TOP_MATCHA_ML_TOP_DMEM_BASE_ADDR + TOP_MATCHA_ML_TOP_DMEM_SIZE_BYTES`.
 */
#define TOP_MATCHA_ML_TOP_DMEM_SIZE_BYTES 0x400000
/**
 * Peripheral base address for spi_host2 in top matcha.
 *
 * This should be used with #mmio_region_from_addr to access the memory-mapped
 * registers associated with the peripheral (usually via a DIF).
 */
#define TOP_MATCHA_SPI_HOST2_BASE_ADDR 0x54090000

/**
 * Peripheral size for spi_host2 in top matcha.
 *
 * This is the size (in bytes) of the peripheral's reserved memory area. All
 * memory-mapped registers associated with this peripheral should have an
 * address between #TOP_MATCHA_SPI_HOST2_BASE_ADDR and
 * `TOP_MATCHA_SPI_HOST2_BASE_ADDR + TOP_MATCHA_SPI_HOST2_SIZE_BYTES`.
 */
#define TOP_MATCHA_SPI_HOST2_SIZE_BYTES 0x40
/**
 * Peripheral base address for rv_timer_smc2 in top matcha.
 *
 * This should be used with #mmio_region_from_addr to access the memory-mapped
 * registers associated with the peripheral (usually via a DIF).
 */
#define TOP_MATCHA_RV_TIMER_SMC2_BASE_ADDR 0x54011000

/**
 * Peripheral size for rv_timer_smc2 in top matcha.
 *
 * This is the size (in bytes) of the peripheral's reserved memory area. All
 * memory-mapped registers associated with this peripheral should have an
 * address between #TOP_MATCHA_RV_TIMER_SMC2_BASE_ADDR and
 * `TOP_MATCHA_RV_TIMER_SMC2_BASE_ADDR + TOP_MATCHA_RV_TIMER_SMC2_SIZE_BYTES`.
 */
#define TOP_MATCHA_RV_TIMER_SMC2_SIZE_BYTES 0x200
/**
 * Peripheral base address for i2s0 in top matcha.
 *
 * This should be used with #mmio_region_from_addr to access the memory-mapped
 * registers associated with the peripheral (usually via a DIF).
 */
#define TOP_MATCHA_I2S0_BASE_ADDR 0x54100000

/**
 * Peripheral size for i2s0 in top matcha.
 *
 * This is the size (in bytes) of the peripheral's reserved memory area. All
 * memory-mapped registers associated with this peripheral should have an
 * address between #TOP_MATCHA_I2S0_BASE_ADDR and
 * `TOP_MATCHA_I2S0_BASE_ADDR + TOP_MATCHA_I2S0_SIZE_BYTES`.
 */
#define TOP_MATCHA_I2S0_SIZE_BYTES 0x40
/**
 * Peripheral base address for cfg device on rv_core_ibex_smc in top matcha.
 *
 * This should be used with #mmio_region_from_addr to access the memory-mapped
 * registers associated with the peripheral (usually via a DIF).
 */
#define TOP_MATCHA_RV_CORE_IBEX_SMC_CFG_BASE_ADDR 0x54030000

/**
 * Peripheral size for cfg device on rv_core_ibex_smc in top matcha.
 *
 * This is the size (in bytes) of the peripheral's reserved memory area. All
 * memory-mapped registers associated with this peripheral should have an
 * address between #TOP_MATCHA_RV_CORE_IBEX_SMC_CFG_BASE_ADDR and
 * `TOP_MATCHA_RV_CORE_IBEX_SMC_CFG_BASE_ADDR + TOP_MATCHA_RV_CORE_IBEX_SMC_CFG_SIZE_BYTES`.
 */
#define TOP_MATCHA_RV_CORE_IBEX_SMC_CFG_SIZE_BYTES 0x100

/**
 * MMIO Region
 *
 * MMIO region excludes any memory that is separate from the module
 * configuration space, i.e. ROM, main SRAM, and flash are excluded but
 * retention SRAM, spi_device memory, or usbdev memory are included.
 */
#define TOP_MATCHA_MMIO_BASE_ADDR 0x40000000
#define TOP_MATCHA_MMIO_SIZE_BYTES 0x28000000

#endif  // __ASSEMBLER__

#endif  // MATCHA_HW_TOP_MATCHA_SW_AUTOGEN_TOP_MATCHA_MEMORY_H_