hw/top_matcha/sw/autogen/top_matcha.h

// Copyright Google Inc.
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0

#ifndef MATCHA_HW_TOP_MATCHA_SW_AUTOGEN_TOP_MATCHA_H_
#define MATCHA_HW_TOP_MATCHA_SW_AUTOGEN_TOP_MATCHA_H_

/**
 * @file
 * @brief Top-specific Definitions
 *
 * This file contains preprocessor and type definitions for use within the
 * device C/C++ codebase.
 *
 * These definitions are for information that depends on the top-specific chip
 * configuration, which includes:
 * - Device Memory Information (for Peripherals and Memory)
 * - PLIC Interrupt ID Names and Source Mappings
 * - Alert ID Names and Source Mappings
 * - Pinmux Pin/Select Names
 * - Power Manager Wakeups
 */

#ifdef __cplusplus
extern "C" {
#endif

/**
 * Peripheral base address for uart0 in top matcha.
 *
 * This should be used with #mmio_region_from_addr to access the memory-mapped
 * registers associated with the peripheral (usually via a DIF).
 */
#define TOP_MATCHA_UART0_BASE_ADDR 0x40000000u

/**
 * Peripheral size for uart0 in top matcha.
 *
 * This is the size (in bytes) of the peripheral's reserved memory area. All
 * memory-mapped registers associated with this peripheral should have an
 * address between #TOP_MATCHA_UART0_BASE_ADDR and
 * `TOP_MATCHA_UART0_BASE_ADDR + TOP_MATCHA_UART0_SIZE_BYTES`.
 */
#define TOP_MATCHA_UART0_SIZE_BYTES 0x40u

/**
 * Peripheral base address for uart1 in top matcha.
 *
 * This should be used with #mmio_region_from_addr to access the memory-mapped
 * registers associated with the peripheral (usually via a DIF).
 */
#define TOP_MATCHA_UART1_BASE_ADDR 0x40010000u

/**
 * Peripheral size for uart1 in top matcha.
 *
 * This is the size (in bytes) of the peripheral's reserved memory area. All
 * memory-mapped registers associated with this peripheral should have an
 * address between #TOP_MATCHA_UART1_BASE_ADDR and
 * `TOP_MATCHA_UART1_BASE_ADDR + TOP_MATCHA_UART1_SIZE_BYTES`.
 */
#define TOP_MATCHA_UART1_SIZE_BYTES 0x40u

/**
 * Peripheral base address for uart2 in top matcha.
 *
 * This should be used with #mmio_region_from_addr to access the memory-mapped
 * registers associated with the peripheral (usually via a DIF).
 */
#define TOP_MATCHA_UART2_BASE_ADDR 0x40020000u

/**
 * Peripheral size for uart2 in top matcha.
 *
 * This is the size (in bytes) of the peripheral's reserved memory area. All
 * memory-mapped registers associated with this peripheral should have an
 * address between #TOP_MATCHA_UART2_BASE_ADDR and
 * `TOP_MATCHA_UART2_BASE_ADDR + TOP_MATCHA_UART2_SIZE_BYTES`.
 */
#define TOP_MATCHA_UART2_SIZE_BYTES 0x40u

/**
 * Peripheral base address for uart3 in top matcha.
 *
 * This should be used with #mmio_region_from_addr to access the memory-mapped
 * registers associated with the peripheral (usually via a DIF).
 */
#define TOP_MATCHA_UART3_BASE_ADDR 0x40030000u

/**
 * Peripheral size for uart3 in top matcha.
 *
 * This is the size (in bytes) of the peripheral's reserved memory area. All
 * memory-mapped registers associated with this peripheral should have an
 * address between #TOP_MATCHA_UART3_BASE_ADDR and
 * `TOP_MATCHA_UART3_BASE_ADDR + TOP_MATCHA_UART3_SIZE_BYTES`.
 */
#define TOP_MATCHA_UART3_SIZE_BYTES 0x40u

/**
 * Peripheral base address for gpio in top matcha.
 *
 * This should be used with #mmio_region_from_addr to access the memory-mapped
 * registers associated with the peripheral (usually via a DIF).
 */
#define TOP_MATCHA_GPIO_BASE_ADDR 0x40040000u

/**
 * Peripheral size for gpio in top matcha.
 *
 * This is the size (in bytes) of the peripheral's reserved memory area. All
 * memory-mapped registers associated with this peripheral should have an
 * address between #TOP_MATCHA_GPIO_BASE_ADDR and
 * `TOP_MATCHA_GPIO_BASE_ADDR + TOP_MATCHA_GPIO_SIZE_BYTES`.
 */
#define TOP_MATCHA_GPIO_SIZE_BYTES 0x40u

/**
 * Peripheral base address for spi_device in top matcha.
 *
 * This should be used with #mmio_region_from_addr to access the memory-mapped
 * registers associated with the peripheral (usually via a DIF).
 */
#define TOP_MATCHA_SPI_DEVICE_BASE_ADDR 0x40050000u

/**
 * Peripheral size for spi_device in top matcha.
 *
 * This is the size (in bytes) of the peripheral's reserved memory area. All
 * memory-mapped registers associated with this peripheral should have an
 * address between #TOP_MATCHA_SPI_DEVICE_BASE_ADDR and
 * `TOP_MATCHA_SPI_DEVICE_BASE_ADDR + TOP_MATCHA_SPI_DEVICE_SIZE_BYTES`.
 */
#define TOP_MATCHA_SPI_DEVICE_SIZE_BYTES 0x2000u

/**
 * Peripheral base address for i2c0 in top matcha.
 *
 * This should be used with #mmio_region_from_addr to access the memory-mapped
 * registers associated with the peripheral (usually via a DIF).
 */
#define TOP_MATCHA_I2C0_BASE_ADDR 0x40080000u

/**
 * Peripheral size for i2c0 in top matcha.
 *
 * This is the size (in bytes) of the peripheral's reserved memory area. All
 * memory-mapped registers associated with this peripheral should have an
 * address between #TOP_MATCHA_I2C0_BASE_ADDR and
 * `TOP_MATCHA_I2C0_BASE_ADDR + TOP_MATCHA_I2C0_SIZE_BYTES`.
 */
#define TOP_MATCHA_I2C0_SIZE_BYTES 0x80u

/**
 * Peripheral base address for i2c1 in top matcha.
 *
 * This should be used with #mmio_region_from_addr to access the memory-mapped
 * registers associated with the peripheral (usually via a DIF).
 */
#define TOP_MATCHA_I2C1_BASE_ADDR 0x40090000u

/**
 * Peripheral size for i2c1 in top matcha.
 *
 * This is the size (in bytes) of the peripheral's reserved memory area. All
 * memory-mapped registers associated with this peripheral should have an
 * address between #TOP_MATCHA_I2C1_BASE_ADDR and
 * `TOP_MATCHA_I2C1_BASE_ADDR + TOP_MATCHA_I2C1_SIZE_BYTES`.
 */
#define TOP_MATCHA_I2C1_SIZE_BYTES 0x80u

/**
 * Peripheral base address for i2c2 in top matcha.
 *
 * This should be used with #mmio_region_from_addr to access the memory-mapped
 * registers associated with the peripheral (usually via a DIF).
 */
#define TOP_MATCHA_I2C2_BASE_ADDR 0x400A0000u

/**
 * Peripheral size for i2c2 in top matcha.
 *
 * This is the size (in bytes) of the peripheral's reserved memory area. All
 * memory-mapped registers associated with this peripheral should have an
 * address between #TOP_MATCHA_I2C2_BASE_ADDR and
 * `TOP_MATCHA_I2C2_BASE_ADDR + TOP_MATCHA_I2C2_SIZE_BYTES`.
 */
#define TOP_MATCHA_I2C2_SIZE_BYTES 0x80u

/**
 * Peripheral base address for pattgen in top matcha.
 *
 * This should be used with #mmio_region_from_addr to access the memory-mapped
 * registers associated with the peripheral (usually via a DIF).
 */
#define TOP_MATCHA_PATTGEN_BASE_ADDR 0x400E0000u

/**
 * Peripheral size for pattgen in top matcha.
 *
 * This is the size (in bytes) of the peripheral's reserved memory area. All
 * memory-mapped registers associated with this peripheral should have an
 * address between #TOP_MATCHA_PATTGEN_BASE_ADDR and
 * `TOP_MATCHA_PATTGEN_BASE_ADDR + TOP_MATCHA_PATTGEN_SIZE_BYTES`.
 */
#define TOP_MATCHA_PATTGEN_SIZE_BYTES 0x40u

/**
 * Peripheral base address for rv_timer in top matcha.
 *
 * This should be used with #mmio_region_from_addr to access the memory-mapped
 * registers associated with the peripheral (usually via a DIF).
 */
#define TOP_MATCHA_RV_TIMER_BASE_ADDR 0x40100000u

/**
 * Peripheral size for rv_timer in top matcha.
 *
 * This is the size (in bytes) of the peripheral's reserved memory area. All
 * memory-mapped registers associated with this peripheral should have an
 * address between #TOP_MATCHA_RV_TIMER_BASE_ADDR and
 * `TOP_MATCHA_RV_TIMER_BASE_ADDR + TOP_MATCHA_RV_TIMER_SIZE_BYTES`.
 */
#define TOP_MATCHA_RV_TIMER_SIZE_BYTES 0x200u

/**
 * Peripheral base address for core device on otp_ctrl in top matcha.
 *
 * This should be used with #mmio_region_from_addr to access the memory-mapped
 * registers associated with the peripheral (usually via a DIF).
 */
#define TOP_MATCHA_OTP_CTRL_CORE_BASE_ADDR 0x40130000u

/**
 * Peripheral size for core device on otp_ctrl in top matcha.
 *
 * This is the size (in bytes) of the peripheral's reserved memory area. All
 * memory-mapped registers associated with this peripheral should have an
 * address between #TOP_MATCHA_OTP_CTRL_CORE_BASE_ADDR and
 * `TOP_MATCHA_OTP_CTRL_CORE_BASE_ADDR + TOP_MATCHA_OTP_CTRL_CORE_SIZE_BYTES`.
 */
#define TOP_MATCHA_OTP_CTRL_CORE_SIZE_BYTES 0x2000u

/**
 * Peripheral base address for prim device on otp_ctrl in top matcha.
 *
 * This should be used with #mmio_region_from_addr to access the memory-mapped
 * registers associated with the peripheral (usually via a DIF).
 */
#define TOP_MATCHA_OTP_CTRL_PRIM_BASE_ADDR 0x40132000u

/**
 * Peripheral size for prim device on otp_ctrl in top matcha.
 *
 * This is the size (in bytes) of the peripheral's reserved memory area. All
 * memory-mapped registers associated with this peripheral should have an
 * address between #TOP_MATCHA_OTP_CTRL_PRIM_BASE_ADDR and
 * `TOP_MATCHA_OTP_CTRL_PRIM_BASE_ADDR + TOP_MATCHA_OTP_CTRL_PRIM_SIZE_BYTES`.
 */
#define TOP_MATCHA_OTP_CTRL_PRIM_SIZE_BYTES 0x20u

/**
 * Peripheral base address for lc_ctrl in top matcha.
 *
 * This should be used with #mmio_region_from_addr to access the memory-mapped
 * registers associated with the peripheral (usually via a DIF).
 */
#define TOP_MATCHA_LC_CTRL_BASE_ADDR 0x40140000u

/**
 * Peripheral size for lc_ctrl in top matcha.
 *
 * This is the size (in bytes) of the peripheral's reserved memory area. All
 * memory-mapped registers associated with this peripheral should have an
 * address between #TOP_MATCHA_LC_CTRL_BASE_ADDR and
 * `TOP_MATCHA_LC_CTRL_BASE_ADDR + TOP_MATCHA_LC_CTRL_SIZE_BYTES`.
 */
#define TOP_MATCHA_LC_CTRL_SIZE_BYTES 0x100u

/**
 * Peripheral base address for alert_handler in top matcha.
 *
 * This should be used with #mmio_region_from_addr to access the memory-mapped
 * registers associated with the peripheral (usually via a DIF).
 */
#define TOP_MATCHA_ALERT_HANDLER_BASE_ADDR 0x40150000u

/**
 * Peripheral size for alert_handler in top matcha.
 *
 * This is the size (in bytes) of the peripheral's reserved memory area. All
 * memory-mapped registers associated with this peripheral should have an
 * address between #TOP_MATCHA_ALERT_HANDLER_BASE_ADDR and
 * `TOP_MATCHA_ALERT_HANDLER_BASE_ADDR + TOP_MATCHA_ALERT_HANDLER_SIZE_BYTES`.
 */
#define TOP_MATCHA_ALERT_HANDLER_SIZE_BYTES 0x800u

/**
 * Peripheral base address for spi_host0 in top matcha.
 *
 * This should be used with #mmio_region_from_addr to access the memory-mapped
 * registers associated with the peripheral (usually via a DIF).
 */
#define TOP_MATCHA_SPI_HOST0_BASE_ADDR 0x40300000u

/**
 * Peripheral size for spi_host0 in top matcha.
 *
 * This is the size (in bytes) of the peripheral's reserved memory area. All
 * memory-mapped registers associated with this peripheral should have an
 * address between #TOP_MATCHA_SPI_HOST0_BASE_ADDR and
 * `TOP_MATCHA_SPI_HOST0_BASE_ADDR + TOP_MATCHA_SPI_HOST0_SIZE_BYTES`.
 */
#define TOP_MATCHA_SPI_HOST0_SIZE_BYTES 0x40u

/**
 * Peripheral base address for spi_host1 in top matcha.
 *
 * This should be used with #mmio_region_from_addr to access the memory-mapped
 * registers associated with the peripheral (usually via a DIF).
 */
#define TOP_MATCHA_SPI_HOST1_BASE_ADDR 0x40310000u

/**
 * Peripheral size for spi_host1 in top matcha.
 *
 * This is the size (in bytes) of the peripheral's reserved memory area. All
 * memory-mapped registers associated with this peripheral should have an
 * address between #TOP_MATCHA_SPI_HOST1_BASE_ADDR and
 * `TOP_MATCHA_SPI_HOST1_BASE_ADDR + TOP_MATCHA_SPI_HOST1_SIZE_BYTES`.
 */
#define TOP_MATCHA_SPI_HOST1_SIZE_BYTES 0x40u

/**
 * Peripheral base address for usbdev in top matcha.
 *
 * This should be used with #mmio_region_from_addr to access the memory-mapped
 * registers associated with the peripheral (usually via a DIF).
 */
#define TOP_MATCHA_USBDEV_BASE_ADDR 0x40320000u

/**
 * Peripheral size for usbdev in top matcha.
 *
 * This is the size (in bytes) of the peripheral's reserved memory area. All
 * memory-mapped registers associated with this peripheral should have an
 * address between #TOP_MATCHA_USBDEV_BASE_ADDR and
 * `TOP_MATCHA_USBDEV_BASE_ADDR + TOP_MATCHA_USBDEV_SIZE_BYTES`.
 */
#define TOP_MATCHA_USBDEV_SIZE_BYTES 0x1000u

/**
 * Peripheral base address for pwrmgr_aon in top matcha.
 *
 * This should be used with #mmio_region_from_addr to access the memory-mapped
 * registers associated with the peripheral (usually via a DIF).
 */
#define TOP_MATCHA_PWRMGR_AON_BASE_ADDR 0x40400000u

/**
 * Peripheral size for pwrmgr_aon in top matcha.
 *
 * This is the size (in bytes) of the peripheral's reserved memory area. All
 * memory-mapped registers associated with this peripheral should have an
 * address between #TOP_MATCHA_PWRMGR_AON_BASE_ADDR and
 * `TOP_MATCHA_PWRMGR_AON_BASE_ADDR + TOP_MATCHA_PWRMGR_AON_SIZE_BYTES`.
 */
#define TOP_MATCHA_PWRMGR_AON_SIZE_BYTES 0x80u

/**
 * Peripheral base address for rstmgr_aon in top matcha.
 *
 * This should be used with #mmio_region_from_addr to access the memory-mapped
 * registers associated with the peripheral (usually via a DIF).
 */
#define TOP_MATCHA_RSTMGR_AON_BASE_ADDR 0x40410000u

/**
 * Peripheral size for rstmgr_aon in top matcha.
 *
 * This is the size (in bytes) of the peripheral's reserved memory area. All
 * memory-mapped registers associated with this peripheral should have an
 * address between #TOP_MATCHA_RSTMGR_AON_BASE_ADDR and
 * `TOP_MATCHA_RSTMGR_AON_BASE_ADDR + TOP_MATCHA_RSTMGR_AON_SIZE_BYTES`.
 */
#define TOP_MATCHA_RSTMGR_AON_SIZE_BYTES 0x100u

/**
 * Peripheral base address for clkmgr_aon in top matcha.
 *
 * This should be used with #mmio_region_from_addr to access the memory-mapped
 * registers associated with the peripheral (usually via a DIF).
 */
#define TOP_MATCHA_CLKMGR_AON_BASE_ADDR 0x40420000u

/**
 * Peripheral size for clkmgr_aon in top matcha.
 *
 * This is the size (in bytes) of the peripheral's reserved memory area. All
 * memory-mapped registers associated with this peripheral should have an
 * address between #TOP_MATCHA_CLKMGR_AON_BASE_ADDR and
 * `TOP_MATCHA_CLKMGR_AON_BASE_ADDR + TOP_MATCHA_CLKMGR_AON_SIZE_BYTES`.
 */
#define TOP_MATCHA_CLKMGR_AON_SIZE_BYTES 0x80u

/**
 * Peripheral base address for sysrst_ctrl_aon in top matcha.
 *
 * This should be used with #mmio_region_from_addr to access the memory-mapped
 * registers associated with the peripheral (usually via a DIF).
 */
#define TOP_MATCHA_SYSRST_CTRL_AON_BASE_ADDR 0x40430000u

/**
 * Peripheral size for sysrst_ctrl_aon in top matcha.
 *
 * This is the size (in bytes) of the peripheral's reserved memory area. All
 * memory-mapped registers associated with this peripheral should have an
 * address between #TOP_MATCHA_SYSRST_CTRL_AON_BASE_ADDR and
 * `TOP_MATCHA_SYSRST_CTRL_AON_BASE_ADDR + TOP_MATCHA_SYSRST_CTRL_AON_SIZE_BYTES`.
 */
#define TOP_MATCHA_SYSRST_CTRL_AON_SIZE_BYTES 0x100u

/**
 * Peripheral base address for adc_ctrl_aon in top matcha.
 *
 * This should be used with #mmio_region_from_addr to access the memory-mapped
 * registers associated with the peripheral (usually via a DIF).
 */
#define TOP_MATCHA_ADC_CTRL_AON_BASE_ADDR 0x40440000u

/**
 * Peripheral size for adc_ctrl_aon in top matcha.
 *
 * This is the size (in bytes) of the peripheral's reserved memory area. All
 * memory-mapped registers associated with this peripheral should have an
 * address between #TOP_MATCHA_ADC_CTRL_AON_BASE_ADDR and
 * `TOP_MATCHA_ADC_CTRL_AON_BASE_ADDR + TOP_MATCHA_ADC_CTRL_AON_SIZE_BYTES`.
 */
#define TOP_MATCHA_ADC_CTRL_AON_SIZE_BYTES 0x80u

/**
 * Peripheral base address for pwm_aon in top matcha.
 *
 * This should be used with #mmio_region_from_addr to access the memory-mapped
 * registers associated with the peripheral (usually via a DIF).
 */
#define TOP_MATCHA_PWM_AON_BASE_ADDR 0x40450000u

/**
 * Peripheral size for pwm_aon in top matcha.
 *
 * This is the size (in bytes) of the peripheral's reserved memory area. All
 * memory-mapped registers associated with this peripheral should have an
 * address between #TOP_MATCHA_PWM_AON_BASE_ADDR and
 * `TOP_MATCHA_PWM_AON_BASE_ADDR + TOP_MATCHA_PWM_AON_SIZE_BYTES`.
 */
#define TOP_MATCHA_PWM_AON_SIZE_BYTES 0x80u

/**
 * Peripheral base address for pinmux_aon in top matcha.
 *
 * This should be used with #mmio_region_from_addr to access the memory-mapped
 * registers associated with the peripheral (usually via a DIF).
 */
#define TOP_MATCHA_PINMUX_AON_BASE_ADDR 0x40460000u

/**
 * Peripheral size for pinmux_aon in top matcha.
 *
 * This is the size (in bytes) of the peripheral's reserved memory area. All
 * memory-mapped registers associated with this peripheral should have an
 * address between #TOP_MATCHA_PINMUX_AON_BASE_ADDR and
 * `TOP_MATCHA_PINMUX_AON_BASE_ADDR + TOP_MATCHA_PINMUX_AON_SIZE_BYTES`.
 */
#define TOP_MATCHA_PINMUX_AON_SIZE_BYTES 0x1000u

/**
 * Peripheral base address for aon_timer_aon in top matcha.
 *
 * This should be used with #mmio_region_from_addr to access the memory-mapped
 * registers associated with the peripheral (usually via a DIF).
 */
#define TOP_MATCHA_AON_TIMER_AON_BASE_ADDR 0x40470000u

/**
 * Peripheral size for aon_timer_aon in top matcha.
 *
 * This is the size (in bytes) of the peripheral's reserved memory area. All
 * memory-mapped registers associated with this peripheral should have an
 * address between #TOP_MATCHA_AON_TIMER_AON_BASE_ADDR and
 * `TOP_MATCHA_AON_TIMER_AON_BASE_ADDR + TOP_MATCHA_AON_TIMER_AON_SIZE_BYTES`.
 */
#define TOP_MATCHA_AON_TIMER_AON_SIZE_BYTES 0x40u

/**
 * Peripheral base address for ast in top matcha.
 *
 * This should be used with #mmio_region_from_addr to access the memory-mapped
 * registers associated with the peripheral (usually via a DIF).
 */
#define TOP_MATCHA_AST_BASE_ADDR 0x40480000u

/**
 * Peripheral size for ast in top matcha.
 *
 * This is the size (in bytes) of the peripheral's reserved memory area. All
 * memory-mapped registers associated with this peripheral should have an
 * address between #TOP_MATCHA_AST_BASE_ADDR and
 * `TOP_MATCHA_AST_BASE_ADDR + TOP_MATCHA_AST_SIZE_BYTES`.
 */
#define TOP_MATCHA_AST_SIZE_BYTES 0x400u

/**
 * Peripheral base address for sensor_ctrl in top matcha.
 *
 * This should be used with #mmio_region_from_addr to access the memory-mapped
 * registers associated with the peripheral (usually via a DIF).
 */
#define TOP_MATCHA_SENSOR_CTRL_BASE_ADDR 0x40490000u

/**
 * Peripheral size for sensor_ctrl in top matcha.
 *
 * This is the size (in bytes) of the peripheral's reserved memory area. All
 * memory-mapped registers associated with this peripheral should have an
 * address between #TOP_MATCHA_SENSOR_CTRL_BASE_ADDR and
 * `TOP_MATCHA_SENSOR_CTRL_BASE_ADDR + TOP_MATCHA_SENSOR_CTRL_SIZE_BYTES`.
 */
#define TOP_MATCHA_SENSOR_CTRL_SIZE_BYTES 0x40u

/**
 * Peripheral base address for regs device on sram_ctrl_ret_aon in top matcha.
 *
 * This should be used with #mmio_region_from_addr to access the memory-mapped
 * registers associated with the peripheral (usually via a DIF).
 */
#define TOP_MATCHA_SRAM_CTRL_RET_AON_REGS_BASE_ADDR 0x40500000u

/**
 * Peripheral size for regs device on sram_ctrl_ret_aon in top matcha.
 *
 * This is the size (in bytes) of the peripheral's reserved memory area. All
 * memory-mapped registers associated with this peripheral should have an
 * address between #TOP_MATCHA_SRAM_CTRL_RET_AON_REGS_BASE_ADDR and
 * `TOP_MATCHA_SRAM_CTRL_RET_AON_REGS_BASE_ADDR + TOP_MATCHA_SRAM_CTRL_RET_AON_REGS_SIZE_BYTES`.
 */
#define TOP_MATCHA_SRAM_CTRL_RET_AON_REGS_SIZE_BYTES 0x20u

/**
 * Peripheral base address for ram device on sram_ctrl_ret_aon in top matcha.
 *
 * This should be used with #mmio_region_from_addr to access the memory-mapped
 * registers associated with the peripheral (usually via a DIF).
 */
#define TOP_MATCHA_SRAM_CTRL_RET_AON_RAM_BASE_ADDR 0x40600000u

/**
 * Peripheral size for ram device on sram_ctrl_ret_aon in top matcha.
 *
 * This is the size (in bytes) of the peripheral's reserved memory area. All
 * memory-mapped registers associated with this peripheral should have an
 * address between #TOP_MATCHA_SRAM_CTRL_RET_AON_RAM_BASE_ADDR and
 * `TOP_MATCHA_SRAM_CTRL_RET_AON_RAM_BASE_ADDR + TOP_MATCHA_SRAM_CTRL_RET_AON_RAM_SIZE_BYTES`.
 */
#define TOP_MATCHA_SRAM_CTRL_RET_AON_RAM_SIZE_BYTES 0x1000u

/**
 * Peripheral base address for core device on flash_ctrl in top matcha.
 *
 * This should be used with #mmio_region_from_addr to access the memory-mapped
 * registers associated with the peripheral (usually via a DIF).
 */
#define TOP_MATCHA_FLASH_CTRL_CORE_BASE_ADDR 0x41000000u

/**
 * Peripheral size for core device on flash_ctrl in top matcha.
 *
 * This is the size (in bytes) of the peripheral's reserved memory area. All
 * memory-mapped registers associated with this peripheral should have an
 * address between #TOP_MATCHA_FLASH_CTRL_CORE_BASE_ADDR and
 * `TOP_MATCHA_FLASH_CTRL_CORE_BASE_ADDR + TOP_MATCHA_FLASH_CTRL_CORE_SIZE_BYTES`.
 */
#define TOP_MATCHA_FLASH_CTRL_CORE_SIZE_BYTES 0x200u

/**
 * Peripheral base address for prim device on flash_ctrl in top matcha.
 *
 * This should be used with #mmio_region_from_addr to access the memory-mapped
 * registers associated with the peripheral (usually via a DIF).
 */
#define TOP_MATCHA_FLASH_CTRL_PRIM_BASE_ADDR 0x41008000u

/**
 * Peripheral size for prim device on flash_ctrl in top matcha.
 *
 * This is the size (in bytes) of the peripheral's reserved memory area. All
 * memory-mapped registers associated with this peripheral should have an
 * address between #TOP_MATCHA_FLASH_CTRL_PRIM_BASE_ADDR and
 * `TOP_MATCHA_FLASH_CTRL_PRIM_BASE_ADDR + TOP_MATCHA_FLASH_CTRL_PRIM_SIZE_BYTES`.
 */
#define TOP_MATCHA_FLASH_CTRL_PRIM_SIZE_BYTES 0x80u

/**
 * Peripheral base address for mem device on flash_ctrl in top matcha.
 *
 * This should be used with #mmio_region_from_addr to access the memory-mapped
 * registers associated with the peripheral (usually via a DIF).
 */
#define TOP_MATCHA_FLASH_CTRL_MEM_BASE_ADDR 0x20000000u

/**
 * Peripheral size for mem device on flash_ctrl in top matcha.
 *
 * This is the size (in bytes) of the peripheral's reserved memory area. All
 * memory-mapped registers associated with this peripheral should have an
 * address between #TOP_MATCHA_FLASH_CTRL_MEM_BASE_ADDR and
 * `TOP_MATCHA_FLASH_CTRL_MEM_BASE_ADDR + TOP_MATCHA_FLASH_CTRL_MEM_SIZE_BYTES`.
 */
#define TOP_MATCHA_FLASH_CTRL_MEM_SIZE_BYTES 0x100000u

/**
 * Peripheral base address for regs device on rv_dm in top matcha.
 *
 * This should be used with #mmio_region_from_addr to access the memory-mapped
 * registers associated with the peripheral (usually via a DIF).
 */
#define TOP_MATCHA_RV_DM_REGS_BASE_ADDR 0x6000u

/**
 * Peripheral size for regs device on rv_dm in top matcha.
 *
 * This is the size (in bytes) of the peripheral's reserved memory area. All
 * memory-mapped registers associated with this peripheral should have an
 * address between #TOP_MATCHA_RV_DM_REGS_BASE_ADDR and
 * `TOP_MATCHA_RV_DM_REGS_BASE_ADDR + TOP_MATCHA_RV_DM_REGS_SIZE_BYTES`.
 */
#define TOP_MATCHA_RV_DM_REGS_SIZE_BYTES 0x4u

/**
 * Peripheral base address for mem device on rv_dm in top matcha.
 *
 * This should be used with #mmio_region_from_addr to access the memory-mapped
 * registers associated with the peripheral (usually via a DIF).
 */
#define TOP_MATCHA_RV_DM_MEM_BASE_ADDR 0x4000u

/**
 * Peripheral size for mem device on rv_dm in top matcha.
 *
 * This is the size (in bytes) of the peripheral's reserved memory area. All
 * memory-mapped registers associated with this peripheral should have an
 * address between #TOP_MATCHA_RV_DM_MEM_BASE_ADDR and
 * `TOP_MATCHA_RV_DM_MEM_BASE_ADDR + TOP_MATCHA_RV_DM_MEM_SIZE_BYTES`.
 */
#define TOP_MATCHA_RV_DM_MEM_SIZE_BYTES 0x1000u

/**
 * Peripheral base address for rv_plic in top matcha.
 *
 * This should be used with #mmio_region_from_addr to access the memory-mapped
 * registers associated with the peripheral (usually via a DIF).
 */
#define TOP_MATCHA_RV_PLIC_BASE_ADDR 0x48000000u

/**
 * Peripheral size for rv_plic in top matcha.
 *
 * This is the size (in bytes) of the peripheral's reserved memory area. All
 * memory-mapped registers associated with this peripheral should have an
 * address between #TOP_MATCHA_RV_PLIC_BASE_ADDR and
 * `TOP_MATCHA_RV_PLIC_BASE_ADDR + TOP_MATCHA_RV_PLIC_SIZE_BYTES`.
 */
#define TOP_MATCHA_RV_PLIC_SIZE_BYTES 0x8000000u

/**
 * Peripheral base address for aes in top matcha.
 *
 * This should be used with #mmio_region_from_addr to access the memory-mapped
 * registers associated with the peripheral (usually via a DIF).
 */
#define TOP_MATCHA_AES_BASE_ADDR 0x41100000u

/**
 * Peripheral size for aes in top matcha.
 *
 * This is the size (in bytes) of the peripheral's reserved memory area. All
 * memory-mapped registers associated with this peripheral should have an
 * address between #TOP_MATCHA_AES_BASE_ADDR and
 * `TOP_MATCHA_AES_BASE_ADDR + TOP_MATCHA_AES_SIZE_BYTES`.
 */
#define TOP_MATCHA_AES_SIZE_BYTES 0x100u

/**
 * Peripheral base address for hmac in top matcha.
 *
 * This should be used with #mmio_region_from_addr to access the memory-mapped
 * registers associated with the peripheral (usually via a DIF).
 */
#define TOP_MATCHA_HMAC_BASE_ADDR 0x41110000u

/**
 * Peripheral size for hmac in top matcha.
 *
 * This is the size (in bytes) of the peripheral's reserved memory area. All
 * memory-mapped registers associated with this peripheral should have an
 * address between #TOP_MATCHA_HMAC_BASE_ADDR and
 * `TOP_MATCHA_HMAC_BASE_ADDR + TOP_MATCHA_HMAC_SIZE_BYTES`.
 */
#define TOP_MATCHA_HMAC_SIZE_BYTES 0x1000u

/**
 * Peripheral base address for kmac in top matcha.
 *
 * This should be used with #mmio_region_from_addr to access the memory-mapped
 * registers associated with the peripheral (usually via a DIF).
 */
#define TOP_MATCHA_KMAC_BASE_ADDR 0x41120000u

/**
 * Peripheral size for kmac in top matcha.
 *
 * This is the size (in bytes) of the peripheral's reserved memory area. All
 * memory-mapped registers associated with this peripheral should have an
 * address between #TOP_MATCHA_KMAC_BASE_ADDR and
 * `TOP_MATCHA_KMAC_BASE_ADDR + TOP_MATCHA_KMAC_SIZE_BYTES`.
 */
#define TOP_MATCHA_KMAC_SIZE_BYTES 0x1000u

/**
 * Peripheral base address for otbn in top matcha.
 *
 * This should be used with #mmio_region_from_addr to access the memory-mapped
 * registers associated with the peripheral (usually via a DIF).
 */
#define TOP_MATCHA_OTBN_BASE_ADDR 0x41130000u

/**
 * Peripheral size for otbn in top matcha.
 *
 * This is the size (in bytes) of the peripheral's reserved memory area. All
 * memory-mapped registers associated with this peripheral should have an
 * address between #TOP_MATCHA_OTBN_BASE_ADDR and
 * `TOP_MATCHA_OTBN_BASE_ADDR + TOP_MATCHA_OTBN_SIZE_BYTES`.
 */
#define TOP_MATCHA_OTBN_SIZE_BYTES 0x10000u

/**
 * Peripheral base address for keymgr in top matcha.
 *
 * This should be used with #mmio_region_from_addr to access the memory-mapped
 * registers associated with the peripheral (usually via a DIF).
 */
#define TOP_MATCHA_KEYMGR_BASE_ADDR 0x41140000u

/**
 * Peripheral size for keymgr in top matcha.
 *
 * This is the size (in bytes) of the peripheral's reserved memory area. All
 * memory-mapped registers associated with this peripheral should have an
 * address between #TOP_MATCHA_KEYMGR_BASE_ADDR and
 * `TOP_MATCHA_KEYMGR_BASE_ADDR + TOP_MATCHA_KEYMGR_SIZE_BYTES`.
 */
#define TOP_MATCHA_KEYMGR_SIZE_BYTES 0x100u

/**
 * Peripheral base address for csrng in top matcha.
 *
 * This should be used with #mmio_region_from_addr to access the memory-mapped
 * registers associated with the peripheral (usually via a DIF).
 */
#define TOP_MATCHA_CSRNG_BASE_ADDR 0x41150000u

/**
 * Peripheral size for csrng in top matcha.
 *
 * This is the size (in bytes) of the peripheral's reserved memory area. All
 * memory-mapped registers associated with this peripheral should have an
 * address between #TOP_MATCHA_CSRNG_BASE_ADDR and
 * `TOP_MATCHA_CSRNG_BASE_ADDR + TOP_MATCHA_CSRNG_SIZE_BYTES`.
 */
#define TOP_MATCHA_CSRNG_SIZE_BYTES 0x80u

/**
 * Peripheral base address for entropy_src in top matcha.
 *
 * This should be used with #mmio_region_from_addr to access the memory-mapped
 * registers associated with the peripheral (usually via a DIF).
 */
#define TOP_MATCHA_ENTROPY_SRC_BASE_ADDR 0x41160000u

/**
 * Peripheral size for entropy_src in top matcha.
 *
 * This is the size (in bytes) of the peripheral's reserved memory area. All
 * memory-mapped registers associated with this peripheral should have an
 * address between #TOP_MATCHA_ENTROPY_SRC_BASE_ADDR and
 * `TOP_MATCHA_ENTROPY_SRC_BASE_ADDR + TOP_MATCHA_ENTROPY_SRC_SIZE_BYTES`.
 */
#define TOP_MATCHA_ENTROPY_SRC_SIZE_BYTES 0x100u

/**
 * Peripheral base address for edn0 in top matcha.
 *
 * This should be used with #mmio_region_from_addr to access the memory-mapped
 * registers associated with the peripheral (usually via a DIF).
 */
#define TOP_MATCHA_EDN0_BASE_ADDR 0x41170000u

/**
 * Peripheral size for edn0 in top matcha.
 *
 * This is the size (in bytes) of the peripheral's reserved memory area. All
 * memory-mapped registers associated with this peripheral should have an
 * address between #TOP_MATCHA_EDN0_BASE_ADDR and
 * `TOP_MATCHA_EDN0_BASE_ADDR + TOP_MATCHA_EDN0_SIZE_BYTES`.
 */
#define TOP_MATCHA_EDN0_SIZE_BYTES 0x80u

/**
 * Peripheral base address for edn1 in top matcha.
 *
 * This should be used with #mmio_region_from_addr to access the memory-mapped
 * registers associated with the peripheral (usually via a DIF).
 */
#define TOP_MATCHA_EDN1_BASE_ADDR 0x41180000u

/**
 * Peripheral size for edn1 in top matcha.
 *
 * This is the size (in bytes) of the peripheral's reserved memory area. All
 * memory-mapped registers associated with this peripheral should have an
 * address between #TOP_MATCHA_EDN1_BASE_ADDR and
 * `TOP_MATCHA_EDN1_BASE_ADDR + TOP_MATCHA_EDN1_SIZE_BYTES`.
 */
#define TOP_MATCHA_EDN1_SIZE_BYTES 0x80u

/**
 * Peripheral base address for regs device on sram_ctrl_main in top matcha.
 *
 * This should be used with #mmio_region_from_addr to access the memory-mapped
 * registers associated with the peripheral (usually via a DIF).
 */
#define TOP_MATCHA_SRAM_CTRL_MAIN_REGS_BASE_ADDR 0x411C0000u

/**
 * Peripheral size for regs device on sram_ctrl_main in top matcha.
 *
 * This is the size (in bytes) of the peripheral's reserved memory area. All
 * memory-mapped registers associated with this peripheral should have an
 * address between #TOP_MATCHA_SRAM_CTRL_MAIN_REGS_BASE_ADDR and
 * `TOP_MATCHA_SRAM_CTRL_MAIN_REGS_BASE_ADDR + TOP_MATCHA_SRAM_CTRL_MAIN_REGS_SIZE_BYTES`.
 */
#define TOP_MATCHA_SRAM_CTRL_MAIN_REGS_SIZE_BYTES 0x20u

/**
 * Peripheral base address for ram device on sram_ctrl_main in top matcha.
 *
 * This should be used with #mmio_region_from_addr to access the memory-mapped
 * registers associated with the peripheral (usually via a DIF).
 */
#define TOP_MATCHA_SRAM_CTRL_MAIN_RAM_BASE_ADDR 0x10000000u

/**
 * Peripheral size for ram device on sram_ctrl_main in top matcha.
 *
 * This is the size (in bytes) of the peripheral's reserved memory area. All
 * memory-mapped registers associated with this peripheral should have an
 * address between #TOP_MATCHA_SRAM_CTRL_MAIN_RAM_BASE_ADDR and
 * `TOP_MATCHA_SRAM_CTRL_MAIN_RAM_BASE_ADDR + TOP_MATCHA_SRAM_CTRL_MAIN_RAM_SIZE_BYTES`.
 */
#define TOP_MATCHA_SRAM_CTRL_MAIN_RAM_SIZE_BYTES 0x20000u

/**
 * Peripheral base address for regs device on rom_ctrl in top matcha.
 *
 * This should be used with #mmio_region_from_addr to access the memory-mapped
 * registers associated with the peripheral (usually via a DIF).
 */
#define TOP_MATCHA_ROM_CTRL_REGS_BASE_ADDR 0x411E0000u

/**
 * Peripheral size for regs device on rom_ctrl in top matcha.
 *
 * This is the size (in bytes) of the peripheral's reserved memory area. All
 * memory-mapped registers associated with this peripheral should have an
 * address between #TOP_MATCHA_ROM_CTRL_REGS_BASE_ADDR and
 * `TOP_MATCHA_ROM_CTRL_REGS_BASE_ADDR + TOP_MATCHA_ROM_CTRL_REGS_SIZE_BYTES`.
 */
#define TOP_MATCHA_ROM_CTRL_REGS_SIZE_BYTES 0x80u

/**
 * Peripheral base address for rom device on rom_ctrl in top matcha.
 *
 * This should be used with #mmio_region_from_addr to access the memory-mapped
 * registers associated with the peripheral (usually via a DIF).
 */
#define TOP_MATCHA_ROM_CTRL_ROM_BASE_ADDR 0x8000u

/**
 * Peripheral size for rom device on rom_ctrl in top matcha.
 *
 * This is the size (in bytes) of the peripheral's reserved memory area. All
 * memory-mapped registers associated with this peripheral should have an
 * address between #TOP_MATCHA_ROM_CTRL_ROM_BASE_ADDR and
 * `TOP_MATCHA_ROM_CTRL_ROM_BASE_ADDR + TOP_MATCHA_ROM_CTRL_ROM_SIZE_BYTES`.
 */
#define TOP_MATCHA_ROM_CTRL_ROM_SIZE_BYTES 0x8000u

/**
 * Peripheral base address for cfg device on rv_core_ibex_sec in top matcha.
 *
 * This should be used with #mmio_region_from_addr to access the memory-mapped
 * registers associated with the peripheral (usually via a DIF).
 */
#define TOP_MATCHA_RV_CORE_IBEX_SEC_CFG_BASE_ADDR 0x411F0000u

/**
 * Peripheral size for cfg device on rv_core_ibex_sec in top matcha.
 *
 * This is the size (in bytes) of the peripheral's reserved memory area. All
 * memory-mapped registers associated with this peripheral should have an
 * address between #TOP_MATCHA_RV_CORE_IBEX_SEC_CFG_BASE_ADDR and
 * `TOP_MATCHA_RV_CORE_IBEX_SEC_CFG_BASE_ADDR + TOP_MATCHA_RV_CORE_IBEX_SEC_CFG_SIZE_BYTES`.
 */
#define TOP_MATCHA_RV_CORE_IBEX_SEC_CFG_SIZE_BYTES 0x100u

/**
 * Peripheral base address for dma0 in top matcha.
 *
 * This should be used with #mmio_region_from_addr to access the memory-mapped
 * registers associated with the peripheral (usually via a DIF).
 */
#define TOP_MATCHA_DMA0_BASE_ADDR 0x40200000u

/**
 * Peripheral size for dma0 in top matcha.
 *
 * This is the size (in bytes) of the peripheral's reserved memory area. All
 * memory-mapped registers associated with this peripheral should have an
 * address between #TOP_MATCHA_DMA0_BASE_ADDR and
 * `TOP_MATCHA_DMA0_BASE_ADDR + TOP_MATCHA_DMA0_SIZE_BYTES`.
 */
#define TOP_MATCHA_DMA0_SIZE_BYTES 0x40u

/**
 * Peripheral base address for smc_uart in top matcha.
 *
 * This should be used with #mmio_region_from_addr to access the memory-mapped
 * registers associated with the peripheral (usually via a DIF).
 */
#define TOP_MATCHA_SMC_UART_BASE_ADDR 0x54000000u

/**
 * Peripheral size for smc_uart in top matcha.
 *
 * This is the size (in bytes) of the peripheral's reserved memory area. All
 * memory-mapped registers associated with this peripheral should have an
 * address between #TOP_MATCHA_SMC_UART_BASE_ADDR and
 * `TOP_MATCHA_SMC_UART_BASE_ADDR + TOP_MATCHA_SMC_UART_SIZE_BYTES`.
 */
#define TOP_MATCHA_SMC_UART_SIZE_BYTES 0x40u

/**
 * Peripheral base address for rv_timer_smc in top matcha.
 *
 * This should be used with #mmio_region_from_addr to access the memory-mapped
 * registers associated with the peripheral (usually via a DIF).
 */
#define TOP_MATCHA_RV_TIMER_SMC_BASE_ADDR 0x54010000u

/**
 * Peripheral size for rv_timer_smc in top matcha.
 *
 * This is the size (in bytes) of the peripheral's reserved memory area. All
 * memory-mapped registers associated with this peripheral should have an
 * address between #TOP_MATCHA_RV_TIMER_SMC_BASE_ADDR and
 * `TOP_MATCHA_RV_TIMER_SMC_BASE_ADDR + TOP_MATCHA_RV_TIMER_SMC_SIZE_BYTES`.
 */
#define TOP_MATCHA_RV_TIMER_SMC_SIZE_BYTES 0x200u

/**
 * Peripheral base address for smc_ctrl in top matcha.
 *
 * This should be used with #mmio_region_from_addr to access the memory-mapped
 * registers associated with the peripheral (usually via a DIF).
 */
#define TOP_MATCHA_SMC_CTRL_BASE_ADDR 0x54020000u

/**
 * Peripheral size for smc_ctrl in top matcha.
 *
 * This is the size (in bytes) of the peripheral's reserved memory area. All
 * memory-mapped registers associated with this peripheral should have an
 * address between #TOP_MATCHA_SMC_CTRL_BASE_ADDR and
 * `TOP_MATCHA_SMC_CTRL_BASE_ADDR + TOP_MATCHA_SMC_CTRL_SIZE_BYTES`.
 */
#define TOP_MATCHA_SMC_CTRL_SIZE_BYTES 0x8u

/**
 * Peripheral base address for cam_i2c in top matcha.
 *
 * This should be used with #mmio_region_from_addr to access the memory-mapped
 * registers associated with the peripheral (usually via a DIF).
 */
#define TOP_MATCHA_CAM_I2C_BASE_ADDR 0x54040000u

/**
 * Peripheral size for cam_i2c in top matcha.
 *
 * This is the size (in bytes) of the peripheral's reserved memory area. All
 * memory-mapped registers associated with this peripheral should have an
 * address between #TOP_MATCHA_CAM_I2C_BASE_ADDR and
 * `TOP_MATCHA_CAM_I2C_BASE_ADDR + TOP_MATCHA_CAM_I2C_SIZE_BYTES`.
 */
#define TOP_MATCHA_CAM_I2C_SIZE_BYTES 0x80u

/**
 * Peripheral base address for cam_ctrl in top matcha.
 *
 * This should be used with #mmio_region_from_addr to access the memory-mapped
 * registers associated with the peripheral (usually via a DIF).
 */
#define TOP_MATCHA_CAM_CTRL_BASE_ADDR 0x54050000u

/**
 * Peripheral size for cam_ctrl in top matcha.
 *
 * This is the size (in bytes) of the peripheral's reserved memory area. All
 * memory-mapped registers associated with this peripheral should have an
 * address between #TOP_MATCHA_CAM_CTRL_BASE_ADDR and
 * `TOP_MATCHA_CAM_CTRL_BASE_ADDR + TOP_MATCHA_CAM_CTRL_SIZE_BYTES`.
 */
#define TOP_MATCHA_CAM_CTRL_SIZE_BYTES 0x10u

/**
 * Peripheral base address for isp_wrapper in top matcha.
 *
 * This should be used with #mmio_region_from_addr to access the memory-mapped
 * registers associated with the peripheral (usually via a DIF).
 */
#define TOP_MATCHA_ISP_WRAPPER_BASE_ADDR 0x54060000u

/**
 * Peripheral size for isp_wrapper in top matcha.
 *
 * This is the size (in bytes) of the peripheral's reserved memory area. All
 * memory-mapped registers associated with this peripheral should have an
 * address between #TOP_MATCHA_ISP_WRAPPER_BASE_ADDR and
 * `TOP_MATCHA_ISP_WRAPPER_BASE_ADDR + TOP_MATCHA_ISP_WRAPPER_SIZE_BYTES`.
 */
#define TOP_MATCHA_ISP_WRAPPER_SIZE_BYTES 0x1000u

/**
 * Peripheral base address for dma_smc in top matcha.
 *
 * This should be used with #mmio_region_from_addr to access the memory-mapped
 * registers associated with the peripheral (usually via a DIF).
 */
#define TOP_MATCHA_DMA_SMC_BASE_ADDR 0x54070000u

/**
 * Peripheral size for dma_smc in top matcha.
 *
 * This is the size (in bytes) of the peripheral's reserved memory area. All
 * memory-mapped registers associated with this peripheral should have an
 * address between #TOP_MATCHA_DMA_SMC_BASE_ADDR and
 * `TOP_MATCHA_DMA_SMC_BASE_ADDR + TOP_MATCHA_DMA_SMC_SIZE_BYTES`.
 */
#define TOP_MATCHA_DMA_SMC_SIZE_BYTES 0x40u

/**
 * Peripheral base address for rv_plic_smc in top matcha.
 *
 * This should be used with #mmio_region_from_addr to access the memory-mapped
 * registers associated with the peripheral (usually via a DIF).
 */
#define TOP_MATCHA_RV_PLIC_SMC_BASE_ADDR 0x60000000u

/**
 * Peripheral size for rv_plic_smc in top matcha.
 *
 * This is the size (in bytes) of the peripheral's reserved memory area. All
 * memory-mapped registers associated with this peripheral should have an
 * address between #TOP_MATCHA_RV_PLIC_SMC_BASE_ADDR and
 * `TOP_MATCHA_RV_PLIC_SMC_BASE_ADDR + TOP_MATCHA_RV_PLIC_SMC_SIZE_BYTES`.
 */
#define TOP_MATCHA_RV_PLIC_SMC_SIZE_BYTES 0x8000000u

/**
 * Peripheral base address for tlul_mailbox_sec in top matcha.
 *
 * This should be used with #mmio_region_from_addr to access the memory-mapped
 * registers associated with the peripheral (usually via a DIF).
 */
#define TOP_MATCHA_TLUL_MAILBOX_SEC_BASE_ADDR 0x40800000u

/**
 * Peripheral size for tlul_mailbox_sec in top matcha.
 *
 * This is the size (in bytes) of the peripheral's reserved memory area. All
 * memory-mapped registers associated with this peripheral should have an
 * address between #TOP_MATCHA_TLUL_MAILBOX_SEC_BASE_ADDR and
 * `TOP_MATCHA_TLUL_MAILBOX_SEC_BASE_ADDR + TOP_MATCHA_TLUL_MAILBOX_SEC_SIZE_BYTES`.
 */
#define TOP_MATCHA_TLUL_MAILBOX_SEC_SIZE_BYTES 0x40u

/**
 * Peripheral base address for tlul_mailbox_smc in top matcha.
 *
 * This should be used with #mmio_region_from_addr to access the memory-mapped
 * registers associated with the peripheral (usually via a DIF).
 */
#define TOP_MATCHA_TLUL_MAILBOX_SMC_BASE_ADDR 0x540F1000u

/**
 * Peripheral size for tlul_mailbox_smc in top matcha.
 *
 * This is the size (in bytes) of the peripheral's reserved memory area. All
 * memory-mapped registers associated with this peripheral should have an
 * address between #TOP_MATCHA_TLUL_MAILBOX_SMC_BASE_ADDR and
 * `TOP_MATCHA_TLUL_MAILBOX_SMC_BASE_ADDR + TOP_MATCHA_TLUL_MAILBOX_SMC_SIZE_BYTES`.
 */
#define TOP_MATCHA_TLUL_MAILBOX_SMC_SIZE_BYTES 0x40u

/**
 * Peripheral base address for core device on ml_top in top matcha.
 *
 * This should be used with #mmio_region_from_addr to access the memory-mapped
 * registers associated with the peripheral (usually via a DIF).
 */
#define TOP_MATCHA_ML_TOP_CORE_BASE_ADDR 0x5C000000u

/**
 * Peripheral size for core device on ml_top in top matcha.
 *
 * This is the size (in bytes) of the peripheral's reserved memory area. All
 * memory-mapped registers associated with this peripheral should have an
 * address between #TOP_MATCHA_ML_TOP_CORE_BASE_ADDR and
 * `TOP_MATCHA_ML_TOP_CORE_BASE_ADDR + TOP_MATCHA_ML_TOP_CORE_SIZE_BYTES`.
 */
#define TOP_MATCHA_ML_TOP_CORE_SIZE_BYTES 0x40u

/**
 * Peripheral base address for dmem device on ml_top in top matcha.
 *
 * This should be used with #mmio_region_from_addr to access the memory-mapped
 * registers associated with the peripheral (usually via a DIF).
 */
#define TOP_MATCHA_ML_TOP_DMEM_BASE_ADDR 0x5A000000u

/**
 * Peripheral size for dmem device on ml_top in top matcha.
 *
 * This is the size (in bytes) of the peripheral's reserved memory area. All
 * memory-mapped registers associated with this peripheral should have an
 * address between #TOP_MATCHA_ML_TOP_DMEM_BASE_ADDR and
 * `TOP_MATCHA_ML_TOP_DMEM_BASE_ADDR + TOP_MATCHA_ML_TOP_DMEM_SIZE_BYTES`.
 */
#define TOP_MATCHA_ML_TOP_DMEM_SIZE_BYTES 0x400000u

/**
 * Peripheral base address for spi_host2 in top matcha.
 *
 * This should be used with #mmio_region_from_addr to access the memory-mapped
 * registers associated with the peripheral (usually via a DIF).
 */
#define TOP_MATCHA_SPI_HOST2_BASE_ADDR 0x54090000u

/**
 * Peripheral size for spi_host2 in top matcha.
 *
 * This is the size (in bytes) of the peripheral's reserved memory area. All
 * memory-mapped registers associated with this peripheral should have an
 * address between #TOP_MATCHA_SPI_HOST2_BASE_ADDR and
 * `TOP_MATCHA_SPI_HOST2_BASE_ADDR + TOP_MATCHA_SPI_HOST2_SIZE_BYTES`.
 */
#define TOP_MATCHA_SPI_HOST2_SIZE_BYTES 0x40u

/**
 * Peripheral base address for rv_timer_smc2 in top matcha.
 *
 * This should be used with #mmio_region_from_addr to access the memory-mapped
 * registers associated with the peripheral (usually via a DIF).
 */
#define TOP_MATCHA_RV_TIMER_SMC2_BASE_ADDR 0x54011000u

/**
 * Peripheral size for rv_timer_smc2 in top matcha.
 *
 * This is the size (in bytes) of the peripheral's reserved memory area. All
 * memory-mapped registers associated with this peripheral should have an
 * address between #TOP_MATCHA_RV_TIMER_SMC2_BASE_ADDR and
 * `TOP_MATCHA_RV_TIMER_SMC2_BASE_ADDR + TOP_MATCHA_RV_TIMER_SMC2_SIZE_BYTES`.
 */
#define TOP_MATCHA_RV_TIMER_SMC2_SIZE_BYTES 0x200u

/**
 * Peripheral base address for i2s0 in top matcha.
 *
 * This should be used with #mmio_region_from_addr to access the memory-mapped
 * registers associated with the peripheral (usually via a DIF).
 */
#define TOP_MATCHA_I2S0_BASE_ADDR 0x54100000u

/**
 * Peripheral size for i2s0 in top matcha.
 *
 * This is the size (in bytes) of the peripheral's reserved memory area. All
 * memory-mapped registers associated with this peripheral should have an
 * address between #TOP_MATCHA_I2S0_BASE_ADDR and
 * `TOP_MATCHA_I2S0_BASE_ADDR + TOP_MATCHA_I2S0_SIZE_BYTES`.
 */
#define TOP_MATCHA_I2S0_SIZE_BYTES 0x40u

/**
 * Peripheral base address for cfg device on rv_core_ibex_smc in top matcha.
 *
 * This should be used with #mmio_region_from_addr to access the memory-mapped
 * registers associated with the peripheral (usually via a DIF).
 */
#define TOP_MATCHA_RV_CORE_IBEX_SMC_CFG_BASE_ADDR 0x54030000u

/**
 * Peripheral size for cfg device on rv_core_ibex_smc in top matcha.
 *
 * This is the size (in bytes) of the peripheral's reserved memory area. All
 * memory-mapped registers associated with this peripheral should have an
 * address between #TOP_MATCHA_RV_CORE_IBEX_SMC_CFG_BASE_ADDR and
 * `TOP_MATCHA_RV_CORE_IBEX_SMC_CFG_BASE_ADDR + TOP_MATCHA_RV_CORE_IBEX_SMC_CFG_SIZE_BYTES`.
 */
#define TOP_MATCHA_RV_CORE_IBEX_SMC_CFG_SIZE_BYTES 0x100u


/**
 * Memory base address for ram_smc in top matcha.
 */
#define TOP_MATCHA_RAM_SMC_BASE_ADDR 0x50000000u

/**
 * Memory size for ram_smc in top matcha.
 */
#define TOP_MATCHA_RAM_SMC_SIZE_BYTES 0x400000u

/**
 * Memory base address for ram_ret_aon in top matcha.
 */
#define TOP_MATCHA_RAM_RET_AON_BASE_ADDR 0x40600000u

/**
 * Memory size for ram_ret_aon in top matcha.
 */
#define TOP_MATCHA_RAM_RET_AON_SIZE_BYTES 0x1000u

/**
 * Memory base address for eflash in top matcha.
 */
#define TOP_MATCHA_EFLASH_BASE_ADDR 0x20000000u

/**
 * Memory size for eflash in top matcha.
 */
#define TOP_MATCHA_EFLASH_SIZE_BYTES 0x100000u

/**
 * Memory base address for ram_main in top matcha.
 */
#define TOP_MATCHA_RAM_MAIN_BASE_ADDR 0x10000000u

/**
 * Memory size for ram_main in top matcha.
 */
#define TOP_MATCHA_RAM_MAIN_SIZE_BYTES 0x20000u

/**
 * Memory base address for rom in top matcha.
 */
#define TOP_MATCHA_ROM_BASE_ADDR 0x8000u

/**
 * Memory size for rom in top matcha.
 */
#define TOP_MATCHA_ROM_SIZE_BYTES 0x8000u

/**
 * Memory base address for ram_ml_dmem in top matcha.
 */
#define TOP_MATCHA_RAM_ML_DMEM_BASE_ADDR 0x5A000000u

/**
 * Memory size for ram_ml_dmem in top matcha.
 */
#define TOP_MATCHA_RAM_ML_DMEM_SIZE_BYTES 0x400000u


/**
 * PLIC Interrupt Source Peripheral.
 *
 * Enumeration used to determine which peripheral asserted the corresponding
 * interrupt.
 */
typedef enum top_matcha_plic_peripheral {
  kTopMatchaPlicPeripheralUnknown = 0, /**< Unknown Peripheral */
  kTopMatchaPlicPeripheralUart0 = 1, /**< uart0 */
  kTopMatchaPlicPeripheralUart1 = 2, /**< uart1 */
  kTopMatchaPlicPeripheralUart2 = 3, /**< uart2 */
  kTopMatchaPlicPeripheralUart3 = 4, /**< uart3 */
  kTopMatchaPlicPeripheralGpio = 5, /**< gpio */
  kTopMatchaPlicPeripheralSpiDevice = 6, /**< spi_device */
  kTopMatchaPlicPeripheralI2c0 = 7, /**< i2c0 */
  kTopMatchaPlicPeripheralI2c1 = 8, /**< i2c1 */
  kTopMatchaPlicPeripheralI2c2 = 9, /**< i2c2 */
  kTopMatchaPlicPeripheralPattgen = 10, /**< pattgen */
  kTopMatchaPlicPeripheralRvTimer = 11, /**< rv_timer */
  kTopMatchaPlicPeripheralOtpCtrl = 12, /**< otp_ctrl */
  kTopMatchaPlicPeripheralAlertHandler = 13, /**< alert_handler */
  kTopMatchaPlicPeripheralSpiHost0 = 14, /**< spi_host0 */
  kTopMatchaPlicPeripheralSpiHost1 = 15, /**< spi_host1 */
  kTopMatchaPlicPeripheralUsbdev = 16, /**< usbdev */
  kTopMatchaPlicPeripheralPwrmgrAon = 17, /**< pwrmgr_aon */
  kTopMatchaPlicPeripheralSysrstCtrlAon = 18, /**< sysrst_ctrl_aon */
  kTopMatchaPlicPeripheralAdcCtrlAon = 19, /**< adc_ctrl_aon */
  kTopMatchaPlicPeripheralAonTimerAon = 20, /**< aon_timer_aon */
  kTopMatchaPlicPeripheralSensorCtrl = 21, /**< sensor_ctrl */
  kTopMatchaPlicPeripheralFlashCtrl = 22, /**< flash_ctrl */
  kTopMatchaPlicPeripheralHmac = 23, /**< hmac */
  kTopMatchaPlicPeripheralKmac = 24, /**< kmac */
  kTopMatchaPlicPeripheralOtbn = 25, /**< otbn */
  kTopMatchaPlicPeripheralKeymgr = 26, /**< keymgr */
  kTopMatchaPlicPeripheralCsrng = 27, /**< csrng */
  kTopMatchaPlicPeripheralEntropySrc = 28, /**< entropy_src */
  kTopMatchaPlicPeripheralEdn0 = 29, /**< edn0 */
  kTopMatchaPlicPeripheralEdn1 = 30, /**< edn1 */
  kTopMatchaPlicPeripheralDma0 = 31, /**< dma0 */
  kTopMatchaPlicPeripheralTlulMailboxSec = 32, /**< tlul_mailbox_sec */
  kTopMatchaPlicPeripheralLast = 32, /**< \internal Final PLIC peripheral */
} top_matcha_plic_peripheral_t;

typedef enum top_matcha_plic_peripheral_smc {
  kTopMatchaPlicPeripheralUnknownSmc = 0, /**< Unknown Peripheral */
  kTopMatchaPlicPeripheralSmcUart = 1, /**< smc_uart */
  kTopMatchaPlicPeripheralRvTimerSmc = 2, /**< rv_timer_smc */
  kTopMatchaPlicPeripheralCamI2c = 3, /**< cam_i2c */
  kTopMatchaPlicPeripheralCamCtrl = 4, /**< cam_ctrl */
  kTopMatchaPlicPeripheralIspWrapper = 5, /**< isp_wrapper */
  kTopMatchaPlicPeripheralDmaSmc = 6, /**< dma_smc */
  kTopMatchaPlicPeripheralTlulMailboxSmc = 7, /**< tlul_mailbox_smc */
  kTopMatchaPlicPeripheralMlTop = 8, /**< ml_top */
  kTopMatchaPlicPeripheralSpiHost2 = 9, /**< spi_host2 */
  kTopMatchaPlicPeripheralRvTimerSmc2 = 10, /**< rv_timer_smc2 */
  kTopMatchaPlicPeripheralI2s0 = 11, /**< i2s0 */
  kTopMatchaPlicPeripheralLastSmc = 11, /**< \internal Final PLIC peripheral */
} top_matcha_plic_peripheral_smc_t;

/**
 * PLIC Interrupt Source.
 *
 * Enumeration of all PLIC interrupt sources. The interrupt sources belonging to
 * the same peripheral are guaranteed to be consecutive.
 */
typedef enum top_matcha_plic_irq_id {
  kTopMatchaPlicIrqIdNone = 0, /**< No Interrupt */
  kTopMatchaPlicIrqIdUart0TxWatermark = 1, /**< uart0_tx_watermark */
  kTopMatchaPlicIrqIdUart0RxWatermark = 2, /**< uart0_rx_watermark */
  kTopMatchaPlicIrqIdUart0TxEmpty = 3, /**< uart0_tx_empty */
  kTopMatchaPlicIrqIdUart0RxOverflow = 4, /**< uart0_rx_overflow */
  kTopMatchaPlicIrqIdUart0RxFrameErr = 5, /**< uart0_rx_frame_err */
  kTopMatchaPlicIrqIdUart0RxBreakErr = 6, /**< uart0_rx_break_err */
  kTopMatchaPlicIrqIdUart0RxTimeout = 7, /**< uart0_rx_timeout */
  kTopMatchaPlicIrqIdUart0RxParityErr = 8, /**< uart0_rx_parity_err */
  kTopMatchaPlicIrqIdUart1TxWatermark = 9, /**< uart1_tx_watermark */
  kTopMatchaPlicIrqIdUart1RxWatermark = 10, /**< uart1_rx_watermark */
  kTopMatchaPlicIrqIdUart1TxEmpty = 11, /**< uart1_tx_empty */
  kTopMatchaPlicIrqIdUart1RxOverflow = 12, /**< uart1_rx_overflow */
  kTopMatchaPlicIrqIdUart1RxFrameErr = 13, /**< uart1_rx_frame_err */
  kTopMatchaPlicIrqIdUart1RxBreakErr = 14, /**< uart1_rx_break_err */
  kTopMatchaPlicIrqIdUart1RxTimeout = 15, /**< uart1_rx_timeout */
  kTopMatchaPlicIrqIdUart1RxParityErr = 16, /**< uart1_rx_parity_err */
  kTopMatchaPlicIrqIdUart2TxWatermark = 17, /**< uart2_tx_watermark */
  kTopMatchaPlicIrqIdUart2RxWatermark = 18, /**< uart2_rx_watermark */
  kTopMatchaPlicIrqIdUart2TxEmpty = 19, /**< uart2_tx_empty */
  kTopMatchaPlicIrqIdUart2RxOverflow = 20, /**< uart2_rx_overflow */
  kTopMatchaPlicIrqIdUart2RxFrameErr = 21, /**< uart2_rx_frame_err */
  kTopMatchaPlicIrqIdUart2RxBreakErr = 22, /**< uart2_rx_break_err */
  kTopMatchaPlicIrqIdUart2RxTimeout = 23, /**< uart2_rx_timeout */
  kTopMatchaPlicIrqIdUart2RxParityErr = 24, /**< uart2_rx_parity_err */
  kTopMatchaPlicIrqIdUart3TxWatermark = 25, /**< uart3_tx_watermark */
  kTopMatchaPlicIrqIdUart3RxWatermark = 26, /**< uart3_rx_watermark */
  kTopMatchaPlicIrqIdUart3TxEmpty = 27, /**< uart3_tx_empty */
  kTopMatchaPlicIrqIdUart3RxOverflow = 28, /**< uart3_rx_overflow */
  kTopMatchaPlicIrqIdUart3RxFrameErr = 29, /**< uart3_rx_frame_err */
  kTopMatchaPlicIrqIdUart3RxBreakErr = 30, /**< uart3_rx_break_err */
  kTopMatchaPlicIrqIdUart3RxTimeout = 31, /**< uart3_rx_timeout */
  kTopMatchaPlicIrqIdUart3RxParityErr = 32, /**< uart3_rx_parity_err */
  kTopMatchaPlicIrqIdGpioGpio0 = 33, /**< gpio_gpio 0 */
  kTopMatchaPlicIrqIdGpioGpio1 = 34, /**< gpio_gpio 1 */
  kTopMatchaPlicIrqIdGpioGpio2 = 35, /**< gpio_gpio 2 */
  kTopMatchaPlicIrqIdGpioGpio3 = 36, /**< gpio_gpio 3 */
  kTopMatchaPlicIrqIdGpioGpio4 = 37, /**< gpio_gpio 4 */
  kTopMatchaPlicIrqIdGpioGpio5 = 38, /**< gpio_gpio 5 */
  kTopMatchaPlicIrqIdGpioGpio6 = 39, /**< gpio_gpio 6 */
  kTopMatchaPlicIrqIdGpioGpio7 = 40, /**< gpio_gpio 7 */
  kTopMatchaPlicIrqIdGpioGpio8 = 41, /**< gpio_gpio 8 */
  kTopMatchaPlicIrqIdGpioGpio9 = 42, /**< gpio_gpio 9 */
  kTopMatchaPlicIrqIdGpioGpio10 = 43, /**< gpio_gpio 10 */
  kTopMatchaPlicIrqIdGpioGpio11 = 44, /**< gpio_gpio 11 */
  kTopMatchaPlicIrqIdGpioGpio12 = 45, /**< gpio_gpio 12 */
  kTopMatchaPlicIrqIdGpioGpio13 = 46, /**< gpio_gpio 13 */
  kTopMatchaPlicIrqIdGpioGpio14 = 47, /**< gpio_gpio 14 */
  kTopMatchaPlicIrqIdGpioGpio15 = 48, /**< gpio_gpio 15 */
  kTopMatchaPlicIrqIdGpioGpio16 = 49, /**< gpio_gpio 16 */
  kTopMatchaPlicIrqIdGpioGpio17 = 50, /**< gpio_gpio 17 */
  kTopMatchaPlicIrqIdGpioGpio18 = 51, /**< gpio_gpio 18 */
  kTopMatchaPlicIrqIdGpioGpio19 = 52, /**< gpio_gpio 19 */
  kTopMatchaPlicIrqIdGpioGpio20 = 53, /**< gpio_gpio 20 */
  kTopMatchaPlicIrqIdGpioGpio21 = 54, /**< gpio_gpio 21 */
  kTopMatchaPlicIrqIdGpioGpio22 = 55, /**< gpio_gpio 22 */
  kTopMatchaPlicIrqIdGpioGpio23 = 56, /**< gpio_gpio 23 */
  kTopMatchaPlicIrqIdGpioGpio24 = 57, /**< gpio_gpio 24 */
  kTopMatchaPlicIrqIdGpioGpio25 = 58, /**< gpio_gpio 25 */
  kTopMatchaPlicIrqIdGpioGpio26 = 59, /**< gpio_gpio 26 */
  kTopMatchaPlicIrqIdGpioGpio27 = 60, /**< gpio_gpio 27 */
  kTopMatchaPlicIrqIdGpioGpio28 = 61, /**< gpio_gpio 28 */
  kTopMatchaPlicIrqIdGpioGpio29 = 62, /**< gpio_gpio 29 */
  kTopMatchaPlicIrqIdGpioGpio30 = 63, /**< gpio_gpio 30 */
  kTopMatchaPlicIrqIdGpioGpio31 = 64, /**< gpio_gpio 31 */
  kTopMatchaPlicIrqIdSpiDeviceGenericRxFull = 65, /**< spi_device_generic_rx_full */
  kTopMatchaPlicIrqIdSpiDeviceGenericRxWatermark = 66, /**< spi_device_generic_rx_watermark */
  kTopMatchaPlicIrqIdSpiDeviceGenericTxWatermark = 67, /**< spi_device_generic_tx_watermark */
  kTopMatchaPlicIrqIdSpiDeviceGenericRxError = 68, /**< spi_device_generic_rx_error */
  kTopMatchaPlicIrqIdSpiDeviceGenericRxOverflow = 69, /**< spi_device_generic_rx_overflow */
  kTopMatchaPlicIrqIdSpiDeviceGenericTxUnderflow = 70, /**< spi_device_generic_tx_underflow */
  kTopMatchaPlicIrqIdSpiDeviceUploadCmdfifoNotEmpty = 71, /**< spi_device_upload_cmdfifo_not_empty */
  kTopMatchaPlicIrqIdSpiDeviceUploadPayloadNotEmpty = 72, /**< spi_device_upload_payload_not_empty */
  kTopMatchaPlicIrqIdSpiDeviceUploadPayloadOverflow = 73, /**< spi_device_upload_payload_overflow */
  kTopMatchaPlicIrqIdSpiDeviceReadbufWatermark = 74, /**< spi_device_readbuf_watermark */
  kTopMatchaPlicIrqIdSpiDeviceReadbufFlip = 75, /**< spi_device_readbuf_flip */
  kTopMatchaPlicIrqIdSpiDeviceTpmHeaderNotEmpty = 76, /**< spi_device_tpm_header_not_empty */
  kTopMatchaPlicIrqIdI2c0FmtThreshold = 77, /**< i2c0_fmt_threshold */
  kTopMatchaPlicIrqIdI2c0RxThreshold = 78, /**< i2c0_rx_threshold */
  kTopMatchaPlicIrqIdI2c0FmtOverflow = 79, /**< i2c0_fmt_overflow */
  kTopMatchaPlicIrqIdI2c0RxOverflow = 80, /**< i2c0_rx_overflow */
  kTopMatchaPlicIrqIdI2c0Nak = 81, /**< i2c0_nak */
  kTopMatchaPlicIrqIdI2c0SclInterference = 82, /**< i2c0_scl_interference */
  kTopMatchaPlicIrqIdI2c0SdaInterference = 83, /**< i2c0_sda_interference */
  kTopMatchaPlicIrqIdI2c0StretchTimeout = 84, /**< i2c0_stretch_timeout */
  kTopMatchaPlicIrqIdI2c0SdaUnstable = 85, /**< i2c0_sda_unstable */
  kTopMatchaPlicIrqIdI2c0CmdComplete = 86, /**< i2c0_cmd_complete */
  kTopMatchaPlicIrqIdI2c0TxStretch = 87, /**< i2c0_tx_stretch */
  kTopMatchaPlicIrqIdI2c0TxOverflow = 88, /**< i2c0_tx_overflow */
  kTopMatchaPlicIrqIdI2c0AcqFull = 89, /**< i2c0_acq_full */
  kTopMatchaPlicIrqIdI2c0UnexpStop = 90, /**< i2c0_unexp_stop */
  kTopMatchaPlicIrqIdI2c0HostTimeout = 91, /**< i2c0_host_timeout */
  kTopMatchaPlicIrqIdI2c1FmtThreshold = 92, /**< i2c1_fmt_threshold */
  kTopMatchaPlicIrqIdI2c1RxThreshold = 93, /**< i2c1_rx_threshold */
  kTopMatchaPlicIrqIdI2c1FmtOverflow = 94, /**< i2c1_fmt_overflow */
  kTopMatchaPlicIrqIdI2c1RxOverflow = 95, /**< i2c1_rx_overflow */
  kTopMatchaPlicIrqIdI2c1Nak = 96, /**< i2c1_nak */
  kTopMatchaPlicIrqIdI2c1SclInterference = 97, /**< i2c1_scl_interference */
  kTopMatchaPlicIrqIdI2c1SdaInterference = 98, /**< i2c1_sda_interference */
  kTopMatchaPlicIrqIdI2c1StretchTimeout = 99, /**< i2c1_stretch_timeout */
  kTopMatchaPlicIrqIdI2c1SdaUnstable = 100, /**< i2c1_sda_unstable */
  kTopMatchaPlicIrqIdI2c1CmdComplete = 101, /**< i2c1_cmd_complete */
  kTopMatchaPlicIrqIdI2c1TxStretch = 102, /**< i2c1_tx_stretch */
  kTopMatchaPlicIrqIdI2c1TxOverflow = 103, /**< i2c1_tx_overflow */
  kTopMatchaPlicIrqIdI2c1AcqFull = 104, /**< i2c1_acq_full */
  kTopMatchaPlicIrqIdI2c1UnexpStop = 105, /**< i2c1_unexp_stop */
  kTopMatchaPlicIrqIdI2c1HostTimeout = 106, /**< i2c1_host_timeout */
  kTopMatchaPlicIrqIdI2c2FmtThreshold = 107, /**< i2c2_fmt_threshold */
  kTopMatchaPlicIrqIdI2c2RxThreshold = 108, /**< i2c2_rx_threshold */
  kTopMatchaPlicIrqIdI2c2FmtOverflow = 109, /**< i2c2_fmt_overflow */
  kTopMatchaPlicIrqIdI2c2RxOverflow = 110, /**< i2c2_rx_overflow */
  kTopMatchaPlicIrqIdI2c2Nak = 111, /**< i2c2_nak */
  kTopMatchaPlicIrqIdI2c2SclInterference = 112, /**< i2c2_scl_interference */
  kTopMatchaPlicIrqIdI2c2SdaInterference = 113, /**< i2c2_sda_interference */
  kTopMatchaPlicIrqIdI2c2StretchTimeout = 114, /**< i2c2_stretch_timeout */
  kTopMatchaPlicIrqIdI2c2SdaUnstable = 115, /**< i2c2_sda_unstable */
  kTopMatchaPlicIrqIdI2c2CmdComplete = 116, /**< i2c2_cmd_complete */
  kTopMatchaPlicIrqIdI2c2TxStretch = 117, /**< i2c2_tx_stretch */
  kTopMatchaPlicIrqIdI2c2TxOverflow = 118, /**< i2c2_tx_overflow */
  kTopMatchaPlicIrqIdI2c2AcqFull = 119, /**< i2c2_acq_full */
  kTopMatchaPlicIrqIdI2c2UnexpStop = 120, /**< i2c2_unexp_stop */
  kTopMatchaPlicIrqIdI2c2HostTimeout = 121, /**< i2c2_host_timeout */
  kTopMatchaPlicIrqIdPattgenDoneCh0 = 122, /**< pattgen_done_ch0 */
  kTopMatchaPlicIrqIdPattgenDoneCh1 = 123, /**< pattgen_done_ch1 */
  kTopMatchaPlicIrqIdRvTimerTimerExpiredHart0Timer0 = 124, /**< rv_timer_timer_expired_hart0_timer0 */
  kTopMatchaPlicIrqIdOtpCtrlOtpOperationDone = 125, /**< otp_ctrl_otp_operation_done */
  kTopMatchaPlicIrqIdOtpCtrlOtpError = 126, /**< otp_ctrl_otp_error */
  kTopMatchaPlicIrqIdAlertHandlerClassa = 127, /**< alert_handler_classa */
  kTopMatchaPlicIrqIdAlertHandlerClassb = 128, /**< alert_handler_classb */
  kTopMatchaPlicIrqIdAlertHandlerClassc = 129, /**< alert_handler_classc */
  kTopMatchaPlicIrqIdAlertHandlerClassd = 130, /**< alert_handler_classd */
  kTopMatchaPlicIrqIdSpiHost0Error = 131, /**< spi_host0_error */
  kTopMatchaPlicIrqIdSpiHost0SpiEvent = 132, /**< spi_host0_spi_event */
  kTopMatchaPlicIrqIdSpiHost1Error = 133, /**< spi_host1_error */
  kTopMatchaPlicIrqIdSpiHost1SpiEvent = 134, /**< spi_host1_spi_event */
  kTopMatchaPlicIrqIdUsbdevPktReceived = 135, /**< usbdev_pkt_received */
  kTopMatchaPlicIrqIdUsbdevPktSent = 136, /**< usbdev_pkt_sent */
  kTopMatchaPlicIrqIdUsbdevDisconnected = 137, /**< usbdev_disconnected */
  kTopMatchaPlicIrqIdUsbdevHostLost = 138, /**< usbdev_host_lost */
  kTopMatchaPlicIrqIdUsbdevLinkReset = 139, /**< usbdev_link_reset */
  kTopMatchaPlicIrqIdUsbdevLinkSuspend = 140, /**< usbdev_link_suspend */
  kTopMatchaPlicIrqIdUsbdevLinkResume = 141, /**< usbdev_link_resume */
  kTopMatchaPlicIrqIdUsbdevAvEmpty = 142, /**< usbdev_av_empty */
  kTopMatchaPlicIrqIdUsbdevRxFull = 143, /**< usbdev_rx_full */
  kTopMatchaPlicIrqIdUsbdevAvOverflow = 144, /**< usbdev_av_overflow */
  kTopMatchaPlicIrqIdUsbdevLinkInErr = 145, /**< usbdev_link_in_err */
  kTopMatchaPlicIrqIdUsbdevRxCrcErr = 146, /**< usbdev_rx_crc_err */
  kTopMatchaPlicIrqIdUsbdevRxPidErr = 147, /**< usbdev_rx_pid_err */
  kTopMatchaPlicIrqIdUsbdevRxBitstuffErr = 148, /**< usbdev_rx_bitstuff_err */
  kTopMatchaPlicIrqIdUsbdevFrame = 149, /**< usbdev_frame */
  kTopMatchaPlicIrqIdUsbdevPowered = 150, /**< usbdev_powered */
  kTopMatchaPlicIrqIdUsbdevLinkOutErr = 151, /**< usbdev_link_out_err */
  kTopMatchaPlicIrqIdPwrmgrAonWakeup = 152, /**< pwrmgr_aon_wakeup */
  kTopMatchaPlicIrqIdSysrstCtrlAonEventDetected = 153, /**< sysrst_ctrl_aon_event_detected */
  kTopMatchaPlicIrqIdAdcCtrlAonMatchDone = 154, /**< adc_ctrl_aon_match_done */
  kTopMatchaPlicIrqIdAonTimerAonWkupTimerExpired = 155, /**< aon_timer_aon_wkup_timer_expired */
  kTopMatchaPlicIrqIdAonTimerAonWdogTimerBark = 156, /**< aon_timer_aon_wdog_timer_bark */
  kTopMatchaPlicIrqIdSensorCtrlIoStatusChange = 157, /**< sensor_ctrl_io_status_change */
  kTopMatchaPlicIrqIdSensorCtrlInitStatusChange = 158, /**< sensor_ctrl_init_status_change */
  kTopMatchaPlicIrqIdFlashCtrlProgEmpty = 159, /**< flash_ctrl_prog_empty */
  kTopMatchaPlicIrqIdFlashCtrlProgLvl = 160, /**< flash_ctrl_prog_lvl */
  kTopMatchaPlicIrqIdFlashCtrlRdFull = 161, /**< flash_ctrl_rd_full */
  kTopMatchaPlicIrqIdFlashCtrlRdLvl = 162, /**< flash_ctrl_rd_lvl */
  kTopMatchaPlicIrqIdFlashCtrlOpDone = 163, /**< flash_ctrl_op_done */
  kTopMatchaPlicIrqIdFlashCtrlCorrErr = 164, /**< flash_ctrl_corr_err */
  kTopMatchaPlicIrqIdHmacHmacDone = 165, /**< hmac_hmac_done */
  kTopMatchaPlicIrqIdHmacFifoEmpty = 166, /**< hmac_fifo_empty */
  kTopMatchaPlicIrqIdHmacHmacErr = 167, /**< hmac_hmac_err */
  kTopMatchaPlicIrqIdKmacKmacDone = 168, /**< kmac_kmac_done */
  kTopMatchaPlicIrqIdKmacFifoEmpty = 169, /**< kmac_fifo_empty */
  kTopMatchaPlicIrqIdKmacKmacErr = 170, /**< kmac_kmac_err */
  kTopMatchaPlicIrqIdOtbnDone = 171, /**< otbn_done */
  kTopMatchaPlicIrqIdKeymgrOpDone = 172, /**< keymgr_op_done */
  kTopMatchaPlicIrqIdCsrngCsCmdReqDone = 173, /**< csrng_cs_cmd_req_done */
  kTopMatchaPlicIrqIdCsrngCsEntropyReq = 174, /**< csrng_cs_entropy_req */
  kTopMatchaPlicIrqIdCsrngCsHwInstExc = 175, /**< csrng_cs_hw_inst_exc */
  kTopMatchaPlicIrqIdCsrngCsFatalErr = 176, /**< csrng_cs_fatal_err */
  kTopMatchaPlicIrqIdEntropySrcEsEntropyValid = 177, /**< entropy_src_es_entropy_valid */
  kTopMatchaPlicIrqIdEntropySrcEsHealthTestFailed = 178, /**< entropy_src_es_health_test_failed */
  kTopMatchaPlicIrqIdEntropySrcEsObserveFifoReady = 179, /**< entropy_src_es_observe_fifo_ready */
  kTopMatchaPlicIrqIdEntropySrcEsFatalErr = 180, /**< entropy_src_es_fatal_err */
  kTopMatchaPlicIrqIdEdn0EdnCmdReqDone = 181, /**< edn0_edn_cmd_req_done */
  kTopMatchaPlicIrqIdEdn0EdnFatalErr = 182, /**< edn0_edn_fatal_err */
  kTopMatchaPlicIrqIdEdn1EdnCmdReqDone = 183, /**< edn1_edn_cmd_req_done */
  kTopMatchaPlicIrqIdEdn1EdnFatalErr = 184, /**< edn1_edn_fatal_err */
  kTopMatchaPlicIrqIdDma0WriterDone = 185, /**< dma0_writer_done */
  kTopMatchaPlicIrqIdDma0ReaderDone = 186, /**< dma0_reader_done */
  kTopMatchaPlicIrqIdTlulMailboxSecWtirq = 187, /**< tlul_mailbox_sec_wtirq */
  kTopMatchaPlicIrqIdTlulMailboxSecRtirq = 188, /**< tlul_mailbox_sec_rtirq */
  kTopMatchaPlicIrqIdTlulMailboxSecEirq = 189, /**< tlul_mailbox_sec_eirq */
  kTopMatchaPlicIrqIdLast = 189, /**< \internal The Last Valid Interrupt ID. */
} top_matcha_plic_irq_id_t;

typedef enum top_matcha_plic_irq_id_smc {
  kTopMatchaPlicIrqIdNoneSmc = 0, /**< No Interrupt */
  kTopMatchaPlicIrqIdSmcUartTxWatermark = 1, /**< smc_uart_tx_watermark */
  kTopMatchaPlicIrqIdSmcUartRxWatermark = 2, /**< smc_uart_rx_watermark */
  kTopMatchaPlicIrqIdSmcUartTxEmpty = 3, /**< smc_uart_tx_empty */
  kTopMatchaPlicIrqIdSmcUartRxOverflow = 4, /**< smc_uart_rx_overflow */
  kTopMatchaPlicIrqIdSmcUartRxFrameErr = 5, /**< smc_uart_rx_frame_err */
  kTopMatchaPlicIrqIdSmcUartRxBreakErr = 6, /**< smc_uart_rx_break_err */
  kTopMatchaPlicIrqIdSmcUartRxTimeout = 7, /**< smc_uart_rx_timeout */
  kTopMatchaPlicIrqIdSmcUartRxParityErr = 8, /**< smc_uart_rx_parity_err */
  kTopMatchaPlicIrqIdRvTimerSmcTimerExpiredHart0Timer0 = 9, /**< rv_timer_smc_timer_expired_hart0_timer0 */
  kTopMatchaPlicIrqIdCamI2cFmtThreshold = 10, /**< cam_i2c_fmt_threshold */
  kTopMatchaPlicIrqIdCamI2cRxThreshold = 11, /**< cam_i2c_rx_threshold */
  kTopMatchaPlicIrqIdCamI2cFmtOverflow = 12, /**< cam_i2c_fmt_overflow */
  kTopMatchaPlicIrqIdCamI2cRxOverflow = 13, /**< cam_i2c_rx_overflow */
  kTopMatchaPlicIrqIdCamI2cNak = 14, /**< cam_i2c_nak */
  kTopMatchaPlicIrqIdCamI2cSclInterference = 15, /**< cam_i2c_scl_interference */
  kTopMatchaPlicIrqIdCamI2cSdaInterference = 16, /**< cam_i2c_sda_interference */
  kTopMatchaPlicIrqIdCamI2cStretchTimeout = 17, /**< cam_i2c_stretch_timeout */
  kTopMatchaPlicIrqIdCamI2cSdaUnstable = 18, /**< cam_i2c_sda_unstable */
  kTopMatchaPlicIrqIdCamI2cCmdComplete = 19, /**< cam_i2c_cmd_complete */
  kTopMatchaPlicIrqIdCamI2cTxStretch = 20, /**< cam_i2c_tx_stretch */
  kTopMatchaPlicIrqIdCamI2cTxOverflow = 21, /**< cam_i2c_tx_overflow */
  kTopMatchaPlicIrqIdCamI2cAcqFull = 22, /**< cam_i2c_acq_full */
  kTopMatchaPlicIrqIdCamI2cUnexpStop = 23, /**< cam_i2c_unexp_stop */
  kTopMatchaPlicIrqIdCamI2cHostTimeout = 24, /**< cam_i2c_host_timeout */
  kTopMatchaPlicIrqIdCamCtrlCamMotionDetect = 25, /**< cam_ctrl_cam_motion_detect */
  kTopMatchaPlicIrqIdIspWrapperIsp = 26, /**< isp_wrapper_isp */
  kTopMatchaPlicIrqIdIspWrapperMi = 27, /**< isp_wrapper_mi */
  kTopMatchaPlicIrqIdDmaSmcWriterDone = 28, /**< dma_smc_writer_done */
  kTopMatchaPlicIrqIdDmaSmcReaderDone = 29, /**< dma_smc_reader_done */
  kTopMatchaPlicIrqIdTlulMailboxSmcWtirq = 30, /**< tlul_mailbox_smc_wtirq */
  kTopMatchaPlicIrqIdTlulMailboxSmcRtirq = 31, /**< tlul_mailbox_smc_rtirq */
  kTopMatchaPlicIrqIdTlulMailboxSmcEirq = 32, /**< tlul_mailbox_smc_eirq */
  kTopMatchaPlicIrqIdMlTopHostReq = 33, /**< ml_top_host_req */
  kTopMatchaPlicIrqIdMlTopFinish = 34, /**< ml_top_finish */
  kTopMatchaPlicIrqIdMlTopFault = 35, /**< ml_top_fault */
  kTopMatchaPlicIrqIdSpiHost2Error = 36, /**< spi_host2_error */
  kTopMatchaPlicIrqIdSpiHost2SpiEvent = 37, /**< spi_host2_spi_event */
  kTopMatchaPlicIrqIdRvTimerSmc2TimerExpiredHart0Timer0 = 38, /**< rv_timer_smc2_timer_expired_hart0_timer0 */
  kTopMatchaPlicIrqIdI2s0TxWatermark = 39, /**< i2s0_tx_watermark */
  kTopMatchaPlicIrqIdI2s0RxWatermark = 40, /**< i2s0_rx_watermark */
  kTopMatchaPlicIrqIdI2s0TxEmpty = 41, /**< i2s0_tx_empty */
  kTopMatchaPlicIrqIdI2s0RxOverflow = 42, /**< i2s0_rx_overflow */
  kTopMatchaPlicIrqIdLastSmc = 42, /**< \internal The Last Valid Interrupt ID. */
} top_matcha_plic_irq_id_smc_t;

/**
 * PLIC Interrupt Source to Peripheral Map
 *
 * This array is a mapping from `top_matcha_plic_irq_id_t` to
 * `top_matcha_plic_peripheral_t`.
 */
extern const top_matcha_plic_peripheral_t
    top_matcha_plic_interrupt_for_peripheral[190];

extern const top_matcha_plic_peripheral_smc_t
    top_matcha_plic_interrupt_for_peripheral_smc[43];

/**
 * PLIC Interrupt Target.
 *
 * Enumeration used to determine which set of IE, CC, threshold registers to
 * access for a given interrupt target.
 */
typedef enum top_matcha_plic_target {
  kTopMatchaPlicTargetIbex0 = 0, /**< Ibex Core 0 */
  kTopMatchaPlicTargetIbex1 = 1, /**< Ibex Core 1 */
  kTopMatchaPlicTargetLast = 1, /**< \internal Final PLIC target */
} top_matcha_plic_target_t;

typedef enum top_matcha_plic_target_smc {
  kTopMatchaPlicTargetIbex0Smc = 0, /**< Ibex Core 0 */
  kTopMatchaPlicTargetLastSmc = 0, /**< \internal Final PLIC target */
} top_matcha_plic_target_smc_t;

/**
 * Alert Handler Source Peripheral.
 *
 * Enumeration used to determine which peripheral asserted the corresponding
 * alert.
 */
typedef enum top_matcha_alert_peripheral {
  kTopMatchaAlertPeripheralUart0 = 0, /**< uart0 */
  kTopMatchaAlertPeripheralUart1 = 1, /**< uart1 */
  kTopMatchaAlertPeripheralUart2 = 2, /**< uart2 */
  kTopMatchaAlertPeripheralUart3 = 3, /**< uart3 */
  kTopMatchaAlertPeripheralGpio = 4, /**< gpio */
  kTopMatchaAlertPeripheralSpiDevice = 5, /**< spi_device */
  kTopMatchaAlertPeripheralI2c0 = 6, /**< i2c0 */
  kTopMatchaAlertPeripheralI2c1 = 7, /**< i2c1 */
  kTopMatchaAlertPeripheralI2c2 = 8, /**< i2c2 */
  kTopMatchaAlertPeripheralPattgen = 9, /**< pattgen */
  kTopMatchaAlertPeripheralRvTimer = 10, /**< rv_timer */
  kTopMatchaAlertPeripheralOtpCtrl = 11, /**< otp_ctrl */
  kTopMatchaAlertPeripheralLcCtrl = 12, /**< lc_ctrl */
  kTopMatchaAlertPeripheralSpiHost0 = 13, /**< spi_host0 */
  kTopMatchaAlertPeripheralSpiHost1 = 14, /**< spi_host1 */
  kTopMatchaAlertPeripheralUsbdev = 15, /**< usbdev */
  kTopMatchaAlertPeripheralPwrmgrAon = 16, /**< pwrmgr_aon */
  kTopMatchaAlertPeripheralRstmgrAon = 17, /**< rstmgr_aon */
  kTopMatchaAlertPeripheralClkmgrAon = 18, /**< clkmgr_aon */
  kTopMatchaAlertPeripheralSysrstCtrlAon = 19, /**< sysrst_ctrl_aon */
  kTopMatchaAlertPeripheralAdcCtrlAon = 20, /**< adc_ctrl_aon */
  kTopMatchaAlertPeripheralPwmAon = 21, /**< pwm_aon */
  kTopMatchaAlertPeripheralPinmuxAon = 22, /**< pinmux_aon */
  kTopMatchaAlertPeripheralAonTimerAon = 23, /**< aon_timer_aon */
  kTopMatchaAlertPeripheralSensorCtrl = 24, /**< sensor_ctrl */
  kTopMatchaAlertPeripheralSramCtrlRetAon = 25, /**< sram_ctrl_ret_aon */
  kTopMatchaAlertPeripheralFlashCtrl = 26, /**< flash_ctrl */
  kTopMatchaAlertPeripheralRvDm = 27, /**< rv_dm */
  kTopMatchaAlertPeripheralRvPlic = 28, /**< rv_plic */
  kTopMatchaAlertPeripheralAes = 29, /**< aes */
  kTopMatchaAlertPeripheralHmac = 30, /**< hmac */
  kTopMatchaAlertPeripheralKmac = 31, /**< kmac */
  kTopMatchaAlertPeripheralOtbn = 32, /**< otbn */
  kTopMatchaAlertPeripheralKeymgr = 33, /**< keymgr */
  kTopMatchaAlertPeripheralCsrng = 34, /**< csrng */
  kTopMatchaAlertPeripheralEntropySrc = 35, /**< entropy_src */
  kTopMatchaAlertPeripheralEdn0 = 36, /**< edn0 */
  kTopMatchaAlertPeripheralEdn1 = 37, /**< edn1 */
  kTopMatchaAlertPeripheralSramCtrlMain = 38, /**< sram_ctrl_main */
  kTopMatchaAlertPeripheralRomCtrl = 39, /**< rom_ctrl */
  kTopMatchaAlertPeripheralRvCoreIbexSec = 40, /**< rv_core_ibex_sec */
  kTopMatchaAlertPeripheralSmcUart = 41, /**< smc_uart */
  kTopMatchaAlertPeripheralRvTimerSmc = 42, /**< rv_timer_smc */
  kTopMatchaAlertPeripheralCamI2c = 43, /**< cam_i2c */
  kTopMatchaAlertPeripheralRvPlicSmc = 44, /**< rv_plic_smc */
  kTopMatchaAlertPeripheralSpiHost2 = 45, /**< spi_host2 */
  kTopMatchaAlertPeripheralRvTimerSmc2 = 46, /**< rv_timer_smc2 */
  kTopMatchaAlertPeripheralRvCoreIbexSmc = 47, /**< rv_core_ibex_smc */
  kTopMatchaAlertPeripheralLast = 47, /**< \internal Final Alert peripheral */
} top_matcha_alert_peripheral_t;

/**
 * Alert Handler Alert Source.
 *
 * Enumeration of all Alert Handler Alert Sources. The alert sources belonging to
 * the same peripheral are guaranteed to be consecutive.
 */
typedef enum top_matcha_alert_id {
  kTopMatchaAlertIdUart0FatalFault = 0, /**< uart0_fatal_fault */
  kTopMatchaAlertIdUart1FatalFault = 1, /**< uart1_fatal_fault */
  kTopMatchaAlertIdUart2FatalFault = 2, /**< uart2_fatal_fault */
  kTopMatchaAlertIdUart3FatalFault = 3, /**< uart3_fatal_fault */
  kTopMatchaAlertIdGpioFatalFault = 4, /**< gpio_fatal_fault */
  kTopMatchaAlertIdSpiDeviceFatalFault = 5, /**< spi_device_fatal_fault */
  kTopMatchaAlertIdI2c0FatalFault = 6, /**< i2c0_fatal_fault */
  kTopMatchaAlertIdI2c1FatalFault = 7, /**< i2c1_fatal_fault */
  kTopMatchaAlertIdI2c2FatalFault = 8, /**< i2c2_fatal_fault */
  kTopMatchaAlertIdPattgenFatalFault = 9, /**< pattgen_fatal_fault */
  kTopMatchaAlertIdRvTimerFatalFault = 10, /**< rv_timer_fatal_fault */
  kTopMatchaAlertIdOtpCtrlFatalMacroError = 11, /**< otp_ctrl_fatal_macro_error */
  kTopMatchaAlertIdOtpCtrlFatalCheckError = 12, /**< otp_ctrl_fatal_check_error */
  kTopMatchaAlertIdOtpCtrlFatalBusIntegError = 13, /**< otp_ctrl_fatal_bus_integ_error */
  kTopMatchaAlertIdOtpCtrlFatalPrimOtpAlert = 14, /**< otp_ctrl_fatal_prim_otp_alert */
  kTopMatchaAlertIdOtpCtrlRecovPrimOtpAlert = 15, /**< otp_ctrl_recov_prim_otp_alert */
  kTopMatchaAlertIdLcCtrlFatalProgError = 16, /**< lc_ctrl_fatal_prog_error */
  kTopMatchaAlertIdLcCtrlFatalStateError = 17, /**< lc_ctrl_fatal_state_error */
  kTopMatchaAlertIdLcCtrlFatalBusIntegError = 18, /**< lc_ctrl_fatal_bus_integ_error */
  kTopMatchaAlertIdSpiHost0FatalFault = 19, /**< spi_host0_fatal_fault */
  kTopMatchaAlertIdSpiHost1FatalFault = 20, /**< spi_host1_fatal_fault */
  kTopMatchaAlertIdUsbdevFatalFault = 21, /**< usbdev_fatal_fault */
  kTopMatchaAlertIdPwrmgrAonFatalFault = 22, /**< pwrmgr_aon_fatal_fault */
  kTopMatchaAlertIdRstmgrAonFatalFault = 23, /**< rstmgr_aon_fatal_fault */
  kTopMatchaAlertIdRstmgrAonFatalCnstyFault = 24, /**< rstmgr_aon_fatal_cnsty_fault */
  kTopMatchaAlertIdClkmgrAonRecovFault = 25, /**< clkmgr_aon_recov_fault */
  kTopMatchaAlertIdClkmgrAonFatalFault = 26, /**< clkmgr_aon_fatal_fault */
  kTopMatchaAlertIdSysrstCtrlAonFatalFault = 27, /**< sysrst_ctrl_aon_fatal_fault */
  kTopMatchaAlertIdAdcCtrlAonFatalFault = 28, /**< adc_ctrl_aon_fatal_fault */
  kTopMatchaAlertIdPwmAonFatalFault = 29, /**< pwm_aon_fatal_fault */
  kTopMatchaAlertIdPinmuxAonFatalFault = 30, /**< pinmux_aon_fatal_fault */
  kTopMatchaAlertIdAonTimerAonFatalFault = 31, /**< aon_timer_aon_fatal_fault */
  kTopMatchaAlertIdSensorCtrlRecovAlert = 32, /**< sensor_ctrl_recov_alert */
  kTopMatchaAlertIdSensorCtrlFatalAlert = 33, /**< sensor_ctrl_fatal_alert */
  kTopMatchaAlertIdSramCtrlRetAonFatalError = 34, /**< sram_ctrl_ret_aon_fatal_error */
  kTopMatchaAlertIdFlashCtrlRecovErr = 35, /**< flash_ctrl_recov_err */
  kTopMatchaAlertIdFlashCtrlFatalStdErr = 36, /**< flash_ctrl_fatal_std_err */
  kTopMatchaAlertIdFlashCtrlFatalErr = 37, /**< flash_ctrl_fatal_err */
  kTopMatchaAlertIdFlashCtrlFatalPrimFlashAlert = 38, /**< flash_ctrl_fatal_prim_flash_alert */
  kTopMatchaAlertIdFlashCtrlRecovPrimFlashAlert = 39, /**< flash_ctrl_recov_prim_flash_alert */
  kTopMatchaAlertIdRvDmFatalFault = 40, /**< rv_dm_fatal_fault */
  kTopMatchaAlertIdRvPlicFatalFault = 41, /**< rv_plic_fatal_fault */
  kTopMatchaAlertIdAesRecovCtrlUpdateErr = 42, /**< aes_recov_ctrl_update_err */
  kTopMatchaAlertIdAesFatalFault = 43, /**< aes_fatal_fault */
  kTopMatchaAlertIdHmacFatalFault = 44, /**< hmac_fatal_fault */
  kTopMatchaAlertIdKmacRecovOperationErr = 45, /**< kmac_recov_operation_err */
  kTopMatchaAlertIdKmacFatalFaultErr = 46, /**< kmac_fatal_fault_err */
  kTopMatchaAlertIdOtbnFatal = 47, /**< otbn_fatal */
  kTopMatchaAlertIdOtbnRecov = 48, /**< otbn_recov */
  kTopMatchaAlertIdKeymgrRecovOperationErr = 49, /**< keymgr_recov_operation_err */
  kTopMatchaAlertIdKeymgrFatalFaultErr = 50, /**< keymgr_fatal_fault_err */
  kTopMatchaAlertIdCsrngRecovAlert = 51, /**< csrng_recov_alert */
  kTopMatchaAlertIdCsrngFatalAlert = 52, /**< csrng_fatal_alert */
  kTopMatchaAlertIdEntropySrcRecovAlert = 53, /**< entropy_src_recov_alert */
  kTopMatchaAlertIdEntropySrcFatalAlert = 54, /**< entropy_src_fatal_alert */
  kTopMatchaAlertIdEdn0RecovAlert = 55, /**< edn0_recov_alert */
  kTopMatchaAlertIdEdn0FatalAlert = 56, /**< edn0_fatal_alert */
  kTopMatchaAlertIdEdn1RecovAlert = 57, /**< edn1_recov_alert */
  kTopMatchaAlertIdEdn1FatalAlert = 58, /**< edn1_fatal_alert */
  kTopMatchaAlertIdSramCtrlMainFatalError = 59, /**< sram_ctrl_main_fatal_error */
  kTopMatchaAlertIdRomCtrlFatal = 60, /**< rom_ctrl_fatal */
  kTopMatchaAlertIdRvCoreIbexSecFatalSwErr = 61, /**< rv_core_ibex_sec_fatal_sw_err */
  kTopMatchaAlertIdRvCoreIbexSecRecovSwErr = 62, /**< rv_core_ibex_sec_recov_sw_err */
  kTopMatchaAlertIdRvCoreIbexSecFatalHwErr = 63, /**< rv_core_ibex_sec_fatal_hw_err */
  kTopMatchaAlertIdRvCoreIbexSecRecovHwErr = 64, /**< rv_core_ibex_sec_recov_hw_err */
  kTopMatchaAlertIdSmcUartFatalFault = 65, /**< smc_uart_fatal_fault */
  kTopMatchaAlertIdRvTimerSmcFatalFault = 66, /**< rv_timer_smc_fatal_fault */
  kTopMatchaAlertIdCamI2cFatalFault = 67, /**< cam_i2c_fatal_fault */
  kTopMatchaAlertIdRvPlicSmcFatalFault = 68, /**< rv_plic_smc_fatal_fault */
  kTopMatchaAlertIdSpiHost2FatalFault = 69, /**< spi_host2_fatal_fault */
  kTopMatchaAlertIdRvTimerSmc2FatalFault = 70, /**< rv_timer_smc2_fatal_fault */
  kTopMatchaAlertIdRvCoreIbexSmcFatalSwErr = 71, /**< rv_core_ibex_smc_fatal_sw_err */
  kTopMatchaAlertIdRvCoreIbexSmcRecovSwErr = 72, /**< rv_core_ibex_smc_recov_sw_err */
  kTopMatchaAlertIdRvCoreIbexSmcFatalHwErr = 73, /**< rv_core_ibex_smc_fatal_hw_err */
  kTopMatchaAlertIdRvCoreIbexSmcRecovHwErr = 74, /**< rv_core_ibex_smc_recov_hw_err */
  kTopMatchaAlertIdLast = 74, /**< \internal The Last Valid Alert ID. */
} top_matcha_alert_id_t;

/**
 * Alert Handler Alert Source to Peripheral Map
 *
 * This array is a mapping from `top_matcha_alert_id_t` to
 * `top_matcha_alert_peripheral_t`.
 */
extern const top_matcha_alert_peripheral_t
    top_matcha_alert_for_peripheral[75];

#define PINMUX_MIO_PERIPH_INSEL_IDX_OFFSET 2

// PERIPH_INSEL ranges from 0 to NUM_MIO_PADS + 2 -1}
//  0 and 1 are tied to value 0 and 1
#define NUM_MIO_PADS 53
#define NUM_DIO_PADS 16

#define PINMUX_PERIPH_OUTSEL_IDX_OFFSET 3

/**
 * Pinmux Peripheral Input.
 */
typedef enum top_matcha_pinmux_peripheral_in {
  kTopMatchaPinmuxPeripheralInGpioGpio0 = 0, /**< Peripheral Input 0 */
  kTopMatchaPinmuxPeripheralInGpioGpio1 = 1, /**< Peripheral Input 1 */
  kTopMatchaPinmuxPeripheralInGpioGpio2 = 2, /**< Peripheral Input 2 */
  kTopMatchaPinmuxPeripheralInGpioGpio3 = 3, /**< Peripheral Input 3 */
  kTopMatchaPinmuxPeripheralInGpioGpio4 = 4, /**< Peripheral Input 4 */
  kTopMatchaPinmuxPeripheralInGpioGpio5 = 5, /**< Peripheral Input 5 */
  kTopMatchaPinmuxPeripheralInGpioGpio6 = 6, /**< Peripheral Input 6 */
  kTopMatchaPinmuxPeripheralInGpioGpio7 = 7, /**< Peripheral Input 7 */
  kTopMatchaPinmuxPeripheralInGpioGpio8 = 8, /**< Peripheral Input 8 */
  kTopMatchaPinmuxPeripheralInGpioGpio9 = 9, /**< Peripheral Input 9 */
  kTopMatchaPinmuxPeripheralInGpioGpio10 = 10, /**< Peripheral Input 10 */
  kTopMatchaPinmuxPeripheralInGpioGpio11 = 11, /**< Peripheral Input 11 */
  kTopMatchaPinmuxPeripheralInGpioGpio12 = 12, /**< Peripheral Input 12 */
  kTopMatchaPinmuxPeripheralInGpioGpio13 = 13, /**< Peripheral Input 13 */
  kTopMatchaPinmuxPeripheralInGpioGpio14 = 14, /**< Peripheral Input 14 */
  kTopMatchaPinmuxPeripheralInGpioGpio15 = 15, /**< Peripheral Input 15 */
  kTopMatchaPinmuxPeripheralInGpioGpio16 = 16, /**< Peripheral Input 16 */
  kTopMatchaPinmuxPeripheralInGpioGpio17 = 17, /**< Peripheral Input 17 */
  kTopMatchaPinmuxPeripheralInGpioGpio18 = 18, /**< Peripheral Input 18 */
  kTopMatchaPinmuxPeripheralInGpioGpio19 = 19, /**< Peripheral Input 19 */
  kTopMatchaPinmuxPeripheralInGpioGpio20 = 20, /**< Peripheral Input 20 */
  kTopMatchaPinmuxPeripheralInGpioGpio21 = 21, /**< Peripheral Input 21 */
  kTopMatchaPinmuxPeripheralInGpioGpio22 = 22, /**< Peripheral Input 22 */
  kTopMatchaPinmuxPeripheralInGpioGpio23 = 23, /**< Peripheral Input 23 */
  kTopMatchaPinmuxPeripheralInGpioGpio24 = 24, /**< Peripheral Input 24 */
  kTopMatchaPinmuxPeripheralInGpioGpio25 = 25, /**< Peripheral Input 25 */
  kTopMatchaPinmuxPeripheralInGpioGpio26 = 26, /**< Peripheral Input 26 */
  kTopMatchaPinmuxPeripheralInGpioGpio27 = 27, /**< Peripheral Input 27 */
  kTopMatchaPinmuxPeripheralInGpioGpio28 = 28, /**< Peripheral Input 28 */
  kTopMatchaPinmuxPeripheralInGpioGpio29 = 29, /**< Peripheral Input 29 */
  kTopMatchaPinmuxPeripheralInGpioGpio30 = 30, /**< Peripheral Input 30 */
  kTopMatchaPinmuxPeripheralInGpioGpio31 = 31, /**< Peripheral Input 31 */
  kTopMatchaPinmuxPeripheralInI2c0Sda = 32, /**< Peripheral Input 32 */
  kTopMatchaPinmuxPeripheralInI2c0Scl = 33, /**< Peripheral Input 33 */
  kTopMatchaPinmuxPeripheralInI2c1Sda = 34, /**< Peripheral Input 34 */
  kTopMatchaPinmuxPeripheralInI2c1Scl = 35, /**< Peripheral Input 35 */
  kTopMatchaPinmuxPeripheralInI2c2Sda = 36, /**< Peripheral Input 36 */
  kTopMatchaPinmuxPeripheralInI2c2Scl = 37, /**< Peripheral Input 37 */
  kTopMatchaPinmuxPeripheralInCamI2cSda = 38, /**< Peripheral Input 38 */
  kTopMatchaPinmuxPeripheralInCamI2cScl = 39, /**< Peripheral Input 39 */
  kTopMatchaPinmuxPeripheralInSpiHost1Sd0 = 40, /**< Peripheral Input 40 */
  kTopMatchaPinmuxPeripheralInSpiHost1Sd1 = 41, /**< Peripheral Input 41 */
  kTopMatchaPinmuxPeripheralInSpiHost1Sd2 = 42, /**< Peripheral Input 42 */
  kTopMatchaPinmuxPeripheralInSpiHost1Sd3 = 43, /**< Peripheral Input 43 */
  kTopMatchaPinmuxPeripheralInSpiHost2Sd0 = 44, /**< Peripheral Input 44 */
  kTopMatchaPinmuxPeripheralInSpiHost2Sd1 = 45, /**< Peripheral Input 45 */
  kTopMatchaPinmuxPeripheralInSpiHost2Sd2 = 46, /**< Peripheral Input 46 */
  kTopMatchaPinmuxPeripheralInSpiHost2Sd3 = 47, /**< Peripheral Input 47 */
  kTopMatchaPinmuxPeripheralInUart0Rx = 48, /**< Peripheral Input 48 */
  kTopMatchaPinmuxPeripheralInUart1Rx = 49, /**< Peripheral Input 49 */
  kTopMatchaPinmuxPeripheralInUart2Rx = 50, /**< Peripheral Input 50 */
  kTopMatchaPinmuxPeripheralInSmcUartRx = 51, /**< Peripheral Input 51 */
  kTopMatchaPinmuxPeripheralInCamCtrlCamInt = 52, /**< Peripheral Input 52 */
  kTopMatchaPinmuxPeripheralInIspWrapperSPclk = 53, /**< Peripheral Input 53 */
  kTopMatchaPinmuxPeripheralInIspWrapperSData0 = 54, /**< Peripheral Input 54 */
  kTopMatchaPinmuxPeripheralInIspWrapperSData1 = 55, /**< Peripheral Input 55 */
  kTopMatchaPinmuxPeripheralInIspWrapperSData2 = 56, /**< Peripheral Input 56 */
  kTopMatchaPinmuxPeripheralInIspWrapperSData3 = 57, /**< Peripheral Input 57 */
  kTopMatchaPinmuxPeripheralInIspWrapperSData4 = 58, /**< Peripheral Input 58 */
  kTopMatchaPinmuxPeripheralInIspWrapperSData5 = 59, /**< Peripheral Input 59 */
  kTopMatchaPinmuxPeripheralInIspWrapperSData6 = 60, /**< Peripheral Input 60 */
  kTopMatchaPinmuxPeripheralInIspWrapperSData7 = 61, /**< Peripheral Input 61 */
  kTopMatchaPinmuxPeripheralInIspWrapperSHsync = 62, /**< Peripheral Input 62 */
  kTopMatchaPinmuxPeripheralInIspWrapperSVsync = 63, /**< Peripheral Input 63 */
  kTopMatchaPinmuxPeripheralInI2s0RxSd = 64, /**< Peripheral Input 64 */
  kTopMatchaPinmuxPeripheralInSpiDeviceTpmCsb = 65, /**< Peripheral Input 65 */
  kTopMatchaPinmuxPeripheralInFlashCtrlTck = 66, /**< Peripheral Input 66 */
  kTopMatchaPinmuxPeripheralInFlashCtrlTms = 67, /**< Peripheral Input 67 */
  kTopMatchaPinmuxPeripheralInFlashCtrlTdi = 68, /**< Peripheral Input 68 */
  kTopMatchaPinmuxPeripheralInSysrstCtrlAonAcPresent = 69, /**< Peripheral Input 69 */
  kTopMatchaPinmuxPeripheralInSysrstCtrlAonKey0In = 70, /**< Peripheral Input 70 */
  kTopMatchaPinmuxPeripheralInSysrstCtrlAonKey1In = 71, /**< Peripheral Input 71 */
  kTopMatchaPinmuxPeripheralInSysrstCtrlAonKey2In = 72, /**< Peripheral Input 72 */
  kTopMatchaPinmuxPeripheralInSysrstCtrlAonPwrbIn = 73, /**< Peripheral Input 73 */
  kTopMatchaPinmuxPeripheralInSysrstCtrlAonLidOpen = 74, /**< Peripheral Input 74 */
  kTopMatchaPinmuxPeripheralInUsbdevSense = 75, /**< Peripheral Input 75 */
  kTopMatchaPinmuxPeripheralInLast = 75, /**< \internal Last valid peripheral input */
} top_matcha_pinmux_peripheral_in_t;

/**
 * Pinmux MIO Input Selector.
 */
typedef enum top_matcha_pinmux_insel {
  kTopMatchaPinmuxInselConstantZero = 0, /**< Tie constantly to zero */
  kTopMatchaPinmuxInselConstantOne = 1, /**< Tie constantly to one */
  kTopMatchaPinmuxInselIoa0 = 2, /**< MIO Pad 0 */
  kTopMatchaPinmuxInselIoa1 = 3, /**< MIO Pad 1 */
  kTopMatchaPinmuxInselIoa2 = 4, /**< MIO Pad 2 */
  kTopMatchaPinmuxInselIoa3 = 5, /**< MIO Pad 3 */
  kTopMatchaPinmuxInselIoa4 = 6, /**< MIO Pad 4 */
  kTopMatchaPinmuxInselIoa5 = 7, /**< MIO Pad 5 */
  kTopMatchaPinmuxInselIoa6 = 8, /**< MIO Pad 6 */
  kTopMatchaPinmuxInselIoa7 = 9, /**< MIO Pad 7 */
  kTopMatchaPinmuxInselIoa8 = 10, /**< MIO Pad 8 */
  kTopMatchaPinmuxInselIob0 = 11, /**< MIO Pad 9 */
  kTopMatchaPinmuxInselIob1 = 12, /**< MIO Pad 10 */
  kTopMatchaPinmuxInselIob2 = 13, /**< MIO Pad 11 */
  kTopMatchaPinmuxInselIob3 = 14, /**< MIO Pad 12 */
  kTopMatchaPinmuxInselIob4 = 15, /**< MIO Pad 13 */
  kTopMatchaPinmuxInselIob5 = 16, /**< MIO Pad 14 */
  kTopMatchaPinmuxInselIob6 = 17, /**< MIO Pad 15 */
  kTopMatchaPinmuxInselIob7 = 18, /**< MIO Pad 16 */
  kTopMatchaPinmuxInselIob8 = 19, /**< MIO Pad 17 */
  kTopMatchaPinmuxInselIob9 = 20, /**< MIO Pad 18 */
  kTopMatchaPinmuxInselIob10 = 21, /**< MIO Pad 19 */
  kTopMatchaPinmuxInselIob11 = 22, /**< MIO Pad 20 */
  kTopMatchaPinmuxInselIob12 = 23, /**< MIO Pad 21 */
  kTopMatchaPinmuxInselIoc0 = 24, /**< MIO Pad 22 */
  kTopMatchaPinmuxInselIoc1 = 25, /**< MIO Pad 23 */
  kTopMatchaPinmuxInselIoc2 = 26, /**< MIO Pad 24 */
  kTopMatchaPinmuxInselIoc3 = 27, /**< MIO Pad 25 */
  kTopMatchaPinmuxInselIoc4 = 28, /**< MIO Pad 26 */
  kTopMatchaPinmuxInselIoc5 = 29, /**< MIO Pad 27 */
  kTopMatchaPinmuxInselIoc6 = 30, /**< MIO Pad 28 */
  kTopMatchaPinmuxInselIoc7 = 31, /**< MIO Pad 29 */
  kTopMatchaPinmuxInselIoc8 = 32, /**< MIO Pad 30 */
  kTopMatchaPinmuxInselIoc9 = 33, /**< MIO Pad 31 */
  kTopMatchaPinmuxInselIoc10 = 34, /**< MIO Pad 32 */
  kTopMatchaPinmuxInselIoc11 = 35, /**< MIO Pad 33 */
  kTopMatchaPinmuxInselIoc12 = 36, /**< MIO Pad 34 */
  kTopMatchaPinmuxInselIor0 = 37, /**< MIO Pad 35 */
  kTopMatchaPinmuxInselIor1 = 38, /**< MIO Pad 36 */
  kTopMatchaPinmuxInselIor2 = 39, /**< MIO Pad 37 */
  kTopMatchaPinmuxInselIor3 = 40, /**< MIO Pad 38 */
  kTopMatchaPinmuxInselIor4 = 41, /**< MIO Pad 39 */
  kTopMatchaPinmuxInselIor5 = 42, /**< MIO Pad 40 */
  kTopMatchaPinmuxInselIor6 = 43, /**< MIO Pad 41 */
  kTopMatchaPinmuxInselIor7 = 44, /**< MIO Pad 42 */
  kTopMatchaPinmuxInselIor10 = 45, /**< MIO Pad 43 */
  kTopMatchaPinmuxInselIor11 = 46, /**< MIO Pad 44 */
  kTopMatchaPinmuxInselIor12 = 47, /**< MIO Pad 45 */
  kTopMatchaPinmuxInselIor13 = 48, /**< MIO Pad 46 */
  kTopMatchaPinmuxInselIod0 = 49, /**< MIO Pad 47 */
  kTopMatchaPinmuxInselIod1 = 50, /**< MIO Pad 48 */
  kTopMatchaPinmuxInselIod2 = 51, /**< MIO Pad 49 */
  kTopMatchaPinmuxInselIod3 = 52, /**< MIO Pad 50 */
  kTopMatchaPinmuxInselIod4 = 53, /**< MIO Pad 51 */
  kTopMatchaPinmuxInselIod5 = 54, /**< MIO Pad 52 */
  kTopMatchaPinmuxInselLast = 54, /**< \internal Last valid insel value */
} top_matcha_pinmux_insel_t;

/**
 * Pinmux MIO Output.
 */
typedef enum top_matcha_pinmux_mio_out {
  kTopMatchaPinmuxMioOutIoa0 = 0, /**< MIO Pad 0 */
  kTopMatchaPinmuxMioOutIoa1 = 1, /**< MIO Pad 1 */
  kTopMatchaPinmuxMioOutIoa2 = 2, /**< MIO Pad 2 */
  kTopMatchaPinmuxMioOutIoa3 = 3, /**< MIO Pad 3 */
  kTopMatchaPinmuxMioOutIoa4 = 4, /**< MIO Pad 4 */
  kTopMatchaPinmuxMioOutIoa5 = 5, /**< MIO Pad 5 */
  kTopMatchaPinmuxMioOutIoa6 = 6, /**< MIO Pad 6 */
  kTopMatchaPinmuxMioOutIoa7 = 7, /**< MIO Pad 7 */
  kTopMatchaPinmuxMioOutIoa8 = 8, /**< MIO Pad 8 */
  kTopMatchaPinmuxMioOutIob0 = 9, /**< MIO Pad 9 */
  kTopMatchaPinmuxMioOutIob1 = 10, /**< MIO Pad 10 */
  kTopMatchaPinmuxMioOutIob2 = 11, /**< MIO Pad 11 */
  kTopMatchaPinmuxMioOutIob3 = 12, /**< MIO Pad 12 */
  kTopMatchaPinmuxMioOutIob4 = 13, /**< MIO Pad 13 */
  kTopMatchaPinmuxMioOutIob5 = 14, /**< MIO Pad 14 */
  kTopMatchaPinmuxMioOutIob6 = 15, /**< MIO Pad 15 */
  kTopMatchaPinmuxMioOutIob7 = 16, /**< MIO Pad 16 */
  kTopMatchaPinmuxMioOutIob8 = 17, /**< MIO Pad 17 */
  kTopMatchaPinmuxMioOutIob9 = 18, /**< MIO Pad 18 */
  kTopMatchaPinmuxMioOutIob10 = 19, /**< MIO Pad 19 */
  kTopMatchaPinmuxMioOutIob11 = 20, /**< MIO Pad 20 */
  kTopMatchaPinmuxMioOutIob12 = 21, /**< MIO Pad 21 */
  kTopMatchaPinmuxMioOutIoc0 = 22, /**< MIO Pad 22 */
  kTopMatchaPinmuxMioOutIoc1 = 23, /**< MIO Pad 23 */
  kTopMatchaPinmuxMioOutIoc2 = 24, /**< MIO Pad 24 */
  kTopMatchaPinmuxMioOutIoc3 = 25, /**< MIO Pad 25 */
  kTopMatchaPinmuxMioOutIoc4 = 26, /**< MIO Pad 26 */
  kTopMatchaPinmuxMioOutIoc5 = 27, /**< MIO Pad 27 */
  kTopMatchaPinmuxMioOutIoc6 = 28, /**< MIO Pad 28 */
  kTopMatchaPinmuxMioOutIoc7 = 29, /**< MIO Pad 29 */
  kTopMatchaPinmuxMioOutIoc8 = 30, /**< MIO Pad 30 */
  kTopMatchaPinmuxMioOutIoc9 = 31, /**< MIO Pad 31 */
  kTopMatchaPinmuxMioOutIoc10 = 32, /**< MIO Pad 32 */
  kTopMatchaPinmuxMioOutIoc11 = 33, /**< MIO Pad 33 */
  kTopMatchaPinmuxMioOutIoc12 = 34, /**< MIO Pad 34 */
  kTopMatchaPinmuxMioOutIor0 = 35, /**< MIO Pad 35 */
  kTopMatchaPinmuxMioOutIor1 = 36, /**< MIO Pad 36 */
  kTopMatchaPinmuxMioOutIor2 = 37, /**< MIO Pad 37 */
  kTopMatchaPinmuxMioOutIor3 = 38, /**< MIO Pad 38 */
  kTopMatchaPinmuxMioOutIor4 = 39, /**< MIO Pad 39 */
  kTopMatchaPinmuxMioOutIor5 = 40, /**< MIO Pad 40 */
  kTopMatchaPinmuxMioOutIor6 = 41, /**< MIO Pad 41 */
  kTopMatchaPinmuxMioOutIor7 = 42, /**< MIO Pad 42 */
  kTopMatchaPinmuxMioOutIor10 = 43, /**< MIO Pad 43 */
  kTopMatchaPinmuxMioOutIor11 = 44, /**< MIO Pad 44 */
  kTopMatchaPinmuxMioOutIor12 = 45, /**< MIO Pad 45 */
  kTopMatchaPinmuxMioOutIor13 = 46, /**< MIO Pad 46 */
  kTopMatchaPinmuxMioOutIod0 = 47, /**< MIO Pad 47 */
  kTopMatchaPinmuxMioOutIod1 = 48, /**< MIO Pad 48 */
  kTopMatchaPinmuxMioOutIod2 = 49, /**< MIO Pad 49 */
  kTopMatchaPinmuxMioOutIod3 = 50, /**< MIO Pad 50 */
  kTopMatchaPinmuxMioOutIod4 = 51, /**< MIO Pad 51 */
  kTopMatchaPinmuxMioOutIod5 = 52, /**< MIO Pad 52 */
  kTopMatchaPinmuxMioOutLast = 52, /**< \internal Last valid mio output */
} top_matcha_pinmux_mio_out_t;

/**
 * Pinmux Peripheral Output Selector.
 */
typedef enum top_matcha_pinmux_outsel {
  kTopMatchaPinmuxOutselConstantZero = 0, /**< Tie constantly to zero */
  kTopMatchaPinmuxOutselConstantOne = 1, /**< Tie constantly to one */
  kTopMatchaPinmuxOutselConstantHighZ = 2, /**< Tie constantly to high-Z */
  kTopMatchaPinmuxOutselGpioGpio0 = 3, /**< Peripheral Output 0 */
  kTopMatchaPinmuxOutselGpioGpio1 = 4, /**< Peripheral Output 1 */
  kTopMatchaPinmuxOutselGpioGpio2 = 5, /**< Peripheral Output 2 */
  kTopMatchaPinmuxOutselGpioGpio3 = 6, /**< Peripheral Output 3 */
  kTopMatchaPinmuxOutselGpioGpio4 = 7, /**< Peripheral Output 4 */
  kTopMatchaPinmuxOutselGpioGpio5 = 8, /**< Peripheral Output 5 */
  kTopMatchaPinmuxOutselGpioGpio6 = 9, /**< Peripheral Output 6 */
  kTopMatchaPinmuxOutselGpioGpio7 = 10, /**< Peripheral Output 7 */
  kTopMatchaPinmuxOutselGpioGpio8 = 11, /**< Peripheral Output 8 */
  kTopMatchaPinmuxOutselGpioGpio9 = 12, /**< Peripheral Output 9 */
  kTopMatchaPinmuxOutselGpioGpio10 = 13, /**< Peripheral Output 10 */
  kTopMatchaPinmuxOutselGpioGpio11 = 14, /**< Peripheral Output 11 */
  kTopMatchaPinmuxOutselGpioGpio12 = 15, /**< Peripheral Output 12 */
  kTopMatchaPinmuxOutselGpioGpio13 = 16, /**< Peripheral Output 13 */
  kTopMatchaPinmuxOutselGpioGpio14 = 17, /**< Peripheral Output 14 */
  kTopMatchaPinmuxOutselGpioGpio15 = 18, /**< Peripheral Output 15 */
  kTopMatchaPinmuxOutselGpioGpio16 = 19, /**< Peripheral Output 16 */
  kTopMatchaPinmuxOutselGpioGpio17 = 20, /**< Peripheral Output 17 */
  kTopMatchaPinmuxOutselGpioGpio18 = 21, /**< Peripheral Output 18 */
  kTopMatchaPinmuxOutselGpioGpio19 = 22, /**< Peripheral Output 19 */
  kTopMatchaPinmuxOutselGpioGpio20 = 23, /**< Peripheral Output 20 */
  kTopMatchaPinmuxOutselGpioGpio21 = 24, /**< Peripheral Output 21 */
  kTopMatchaPinmuxOutselGpioGpio22 = 25, /**< Peripheral Output 22 */
  kTopMatchaPinmuxOutselGpioGpio23 = 26, /**< Peripheral Output 23 */
  kTopMatchaPinmuxOutselGpioGpio24 = 27, /**< Peripheral Output 24 */
  kTopMatchaPinmuxOutselGpioGpio25 = 28, /**< Peripheral Output 25 */
  kTopMatchaPinmuxOutselGpioGpio26 = 29, /**< Peripheral Output 26 */
  kTopMatchaPinmuxOutselGpioGpio27 = 30, /**< Peripheral Output 27 */
  kTopMatchaPinmuxOutselGpioGpio28 = 31, /**< Peripheral Output 28 */
  kTopMatchaPinmuxOutselGpioGpio29 = 32, /**< Peripheral Output 29 */
  kTopMatchaPinmuxOutselGpioGpio30 = 33, /**< Peripheral Output 30 */
  kTopMatchaPinmuxOutselGpioGpio31 = 34, /**< Peripheral Output 31 */
  kTopMatchaPinmuxOutselI2c0Sda = 35, /**< Peripheral Output 32 */
  kTopMatchaPinmuxOutselI2c0Scl = 36, /**< Peripheral Output 33 */
  kTopMatchaPinmuxOutselI2c1Sda = 37, /**< Peripheral Output 34 */
  kTopMatchaPinmuxOutselI2c1Scl = 38, /**< Peripheral Output 35 */
  kTopMatchaPinmuxOutselI2c2Sda = 39, /**< Peripheral Output 36 */
  kTopMatchaPinmuxOutselI2c2Scl = 40, /**< Peripheral Output 37 */
  kTopMatchaPinmuxOutselCamI2cSda = 41, /**< Peripheral Output 38 */
  kTopMatchaPinmuxOutselCamI2cScl = 42, /**< Peripheral Output 39 */
  kTopMatchaPinmuxOutselSpiHost1Sd0 = 43, /**< Peripheral Output 40 */
  kTopMatchaPinmuxOutselSpiHost1Sd1 = 44, /**< Peripheral Output 41 */
  kTopMatchaPinmuxOutselSpiHost1Sd2 = 45, /**< Peripheral Output 42 */
  kTopMatchaPinmuxOutselSpiHost1Sd3 = 46, /**< Peripheral Output 43 */
  kTopMatchaPinmuxOutselSpiHost2Sd0 = 47, /**< Peripheral Output 44 */
  kTopMatchaPinmuxOutselSpiHost2Sd1 = 48, /**< Peripheral Output 45 */
  kTopMatchaPinmuxOutselSpiHost2Sd2 = 49, /**< Peripheral Output 46 */
  kTopMatchaPinmuxOutselSpiHost2Sd3 = 50, /**< Peripheral Output 47 */
  kTopMatchaPinmuxOutselUart0Tx = 51, /**< Peripheral Output 48 */
  kTopMatchaPinmuxOutselUart1Tx = 52, /**< Peripheral Output 49 */
  kTopMatchaPinmuxOutselUart2Tx = 53, /**< Peripheral Output 50 */
  kTopMatchaPinmuxOutselSmcUartTx = 54, /**< Peripheral Output 51 */
  kTopMatchaPinmuxOutselCamCtrlCamTrig = 55, /**< Peripheral Output 52 */
  kTopMatchaPinmuxOutselI2s0RxSclk = 56, /**< Peripheral Output 53 */
  kTopMatchaPinmuxOutselI2s0RxWs = 57, /**< Peripheral Output 54 */
  kTopMatchaPinmuxOutselI2s0TxSclk = 58, /**< Peripheral Output 55 */
  kTopMatchaPinmuxOutselI2s0TxWs = 59, /**< Peripheral Output 56 */
  kTopMatchaPinmuxOutselI2s0TxSd = 60, /**< Peripheral Output 57 */
  kTopMatchaPinmuxOutselPattgenPda0Tx = 61, /**< Peripheral Output 58 */
  kTopMatchaPinmuxOutselPattgenPcl0Tx = 62, /**< Peripheral Output 59 */
  kTopMatchaPinmuxOutselPattgenPda1Tx = 63, /**< Peripheral Output 60 */
  kTopMatchaPinmuxOutselPattgenPcl1Tx = 64, /**< Peripheral Output 61 */
  kTopMatchaPinmuxOutselSpiHost1Sck = 65, /**< Peripheral Output 62 */
  kTopMatchaPinmuxOutselSpiHost1Csb = 66, /**< Peripheral Output 63 */
  kTopMatchaPinmuxOutselSpiHost2Sck = 67, /**< Peripheral Output 64 */
  kTopMatchaPinmuxOutselSpiHost2Csb = 68, /**< Peripheral Output 65 */
  kTopMatchaPinmuxOutselFlashCtrlTdo = 69, /**< Peripheral Output 66 */
  kTopMatchaPinmuxOutselSensorCtrlAstDebugOut0 = 70, /**< Peripheral Output 67 */
  kTopMatchaPinmuxOutselSensorCtrlAstDebugOut1 = 71, /**< Peripheral Output 68 */
  kTopMatchaPinmuxOutselSensorCtrlAstDebugOut2 = 72, /**< Peripheral Output 69 */
  kTopMatchaPinmuxOutselSensorCtrlAstDebugOut3 = 73, /**< Peripheral Output 70 */
  kTopMatchaPinmuxOutselSensorCtrlAstDebugOut4 = 74, /**< Peripheral Output 71 */
  kTopMatchaPinmuxOutselSensorCtrlAstDebugOut5 = 75, /**< Peripheral Output 72 */
  kTopMatchaPinmuxOutselSensorCtrlAstDebugOut6 = 76, /**< Peripheral Output 73 */
  kTopMatchaPinmuxOutselSensorCtrlAstDebugOut7 = 77, /**< Peripheral Output 74 */
  kTopMatchaPinmuxOutselSensorCtrlAstDebugOut8 = 78, /**< Peripheral Output 75 */
  kTopMatchaPinmuxOutselPwmAonPwm0 = 79, /**< Peripheral Output 76 */
  kTopMatchaPinmuxOutselPwmAonPwm1 = 80, /**< Peripheral Output 77 */
  kTopMatchaPinmuxOutselPwmAonPwm2 = 81, /**< Peripheral Output 78 */
  kTopMatchaPinmuxOutselPwmAonPwm3 = 82, /**< Peripheral Output 79 */
  kTopMatchaPinmuxOutselPwmAonPwm4 = 83, /**< Peripheral Output 80 */
  kTopMatchaPinmuxOutselPwmAonPwm5 = 84, /**< Peripheral Output 81 */
  kTopMatchaPinmuxOutselOtpCtrlTest0 = 85, /**< Peripheral Output 82 */
  kTopMatchaPinmuxOutselSysrstCtrlAonBatDisable = 86, /**< Peripheral Output 83 */
  kTopMatchaPinmuxOutselSysrstCtrlAonKey0Out = 87, /**< Peripheral Output 84 */
  kTopMatchaPinmuxOutselSysrstCtrlAonKey1Out = 88, /**< Peripheral Output 85 */
  kTopMatchaPinmuxOutselSysrstCtrlAonKey2Out = 89, /**< Peripheral Output 86 */
  kTopMatchaPinmuxOutselSysrstCtrlAonPwrbOut = 90, /**< Peripheral Output 87 */
  kTopMatchaPinmuxOutselSysrstCtrlAonZ3Wakeup = 91, /**< Peripheral Output 88 */
  kTopMatchaPinmuxOutselLast = 91, /**< \internal Last valid outsel value */
} top_matcha_pinmux_outsel_t;

/**
 * Dedicated Pad Selects
 */
typedef enum top_matcha_direct_pads {
  kTopMatchaDirectPadsUsbdevUsbDp = 0, /**<  */
  kTopMatchaDirectPadsUsbdevUsbDn = 1, /**<  */
  kTopMatchaDirectPadsSpiHost0Sd0 = 2, /**<  */
  kTopMatchaDirectPadsSpiHost0Sd1 = 3, /**<  */
  kTopMatchaDirectPadsSpiHost0Sd2 = 4, /**<  */
  kTopMatchaDirectPadsSpiHost0Sd3 = 5, /**<  */
  kTopMatchaDirectPadsSpiDeviceSd0 = 6, /**<  */
  kTopMatchaDirectPadsSpiDeviceSd1 = 7, /**<  */
  kTopMatchaDirectPadsSpiDeviceSd2 = 8, /**<  */
  kTopMatchaDirectPadsSpiDeviceSd3 = 9, /**<  */
  kTopMatchaDirectPadsSysrstCtrlAonEcRstL = 10, /**<  */
  kTopMatchaDirectPadsSysrstCtrlAonFlashWpL = 11, /**<  */
  kTopMatchaDirectPadsSpiDeviceSck = 12, /**<  */
  kTopMatchaDirectPadsSpiDeviceCsb = 13, /**<  */
  kTopMatchaDirectPadsSpiHost0Sck = 14, /**<  */
  kTopMatchaDirectPadsSpiHost0Csb = 15, /**<  */
  kTopMatchaDirectPadsLast = 15, /**< \internal Last valid direct pad */
} top_matcha_direct_pads_t;

/**
 * Muxed Pad Selects
 */
typedef enum top_matcha_muxed_pads {
  kTopMatchaMuxedPadsIoa0 = 0, /**<  */
  kTopMatchaMuxedPadsIoa1 = 1, /**<  */
  kTopMatchaMuxedPadsIoa2 = 2, /**<  */
  kTopMatchaMuxedPadsIoa3 = 3, /**<  */
  kTopMatchaMuxedPadsIoa4 = 4, /**<  */
  kTopMatchaMuxedPadsIoa5 = 5, /**<  */
  kTopMatchaMuxedPadsIoa6 = 6, /**<  */
  kTopMatchaMuxedPadsIoa7 = 7, /**<  */
  kTopMatchaMuxedPadsIoa8 = 8, /**<  */
  kTopMatchaMuxedPadsIob0 = 9, /**<  */
  kTopMatchaMuxedPadsIob1 = 10, /**<  */
  kTopMatchaMuxedPadsIob2 = 11, /**<  */
  kTopMatchaMuxedPadsIob3 = 12, /**<  */
  kTopMatchaMuxedPadsIob4 = 13, /**<  */
  kTopMatchaMuxedPadsIob5 = 14, /**<  */
  kTopMatchaMuxedPadsIob6 = 15, /**<  */
  kTopMatchaMuxedPadsIob7 = 16, /**<  */
  kTopMatchaMuxedPadsIob8 = 17, /**<  */
  kTopMatchaMuxedPadsIob9 = 18, /**<  */
  kTopMatchaMuxedPadsIob10 = 19, /**<  */
  kTopMatchaMuxedPadsIob11 = 20, /**<  */
  kTopMatchaMuxedPadsIob12 = 21, /**<  */
  kTopMatchaMuxedPadsIoc0 = 22, /**<  */
  kTopMatchaMuxedPadsIoc1 = 23, /**<  */
  kTopMatchaMuxedPadsIoc2 = 24, /**<  */
  kTopMatchaMuxedPadsIoc3 = 25, /**<  */
  kTopMatchaMuxedPadsIoc4 = 26, /**<  */
  kTopMatchaMuxedPadsIoc5 = 27, /**<  */
  kTopMatchaMuxedPadsIoc6 = 28, /**<  */
  kTopMatchaMuxedPadsIoc7 = 29, /**<  */
  kTopMatchaMuxedPadsIoc8 = 30, /**<  */
  kTopMatchaMuxedPadsIoc9 = 31, /**<  */
  kTopMatchaMuxedPadsIoc10 = 32, /**<  */
  kTopMatchaMuxedPadsIoc11 = 33, /**<  */
  kTopMatchaMuxedPadsIoc12 = 34, /**<  */
  kTopMatchaMuxedPadsIor0 = 35, /**<  */
  kTopMatchaMuxedPadsIor1 = 36, /**<  */
  kTopMatchaMuxedPadsIor2 = 37, /**<  */
  kTopMatchaMuxedPadsIor3 = 38, /**<  */
  kTopMatchaMuxedPadsIor4 = 39, /**<  */
  kTopMatchaMuxedPadsIor5 = 40, /**<  */
  kTopMatchaMuxedPadsIor6 = 41, /**<  */
  kTopMatchaMuxedPadsIor7 = 42, /**<  */
  kTopMatchaMuxedPadsIor10 = 43, /**<  */
  kTopMatchaMuxedPadsIor11 = 44, /**<  */
  kTopMatchaMuxedPadsIor12 = 45, /**<  */
  kTopMatchaMuxedPadsIor13 = 46, /**<  */
  kTopMatchaMuxedPadsIod0 = 47, /**<  */
  kTopMatchaMuxedPadsIod1 = 48, /**<  */
  kTopMatchaMuxedPadsIod2 = 49, /**<  */
  kTopMatchaMuxedPadsIod3 = 50, /**<  */
  kTopMatchaMuxedPadsIod4 = 51, /**<  */
  kTopMatchaMuxedPadsIod5 = 52, /**<  */
  kTopMatchaMuxedPadsLast = 52, /**< \internal Last valid muxed pad */
} top_matcha_muxed_pads_t;

/**
 * Power Manager Wakeup Signals
 */
typedef enum top_matcha_power_manager_wake_ups {
  kTopMatchaPowerManagerWakeUpsSysrstCtrlAonWkupReq = 0, /**<  */
  kTopMatchaPowerManagerWakeUpsAdcCtrlAonWkupReq = 1, /**<  */
  kTopMatchaPowerManagerWakeUpsPinmuxAonPinWkupReq = 2, /**<  */
  kTopMatchaPowerManagerWakeUpsPinmuxAonUsbWkupReq = 3, /**<  */
  kTopMatchaPowerManagerWakeUpsAonTimerAonWkupReq = 4, /**<  */
  kTopMatchaPowerManagerWakeUpsSensorCtrlWkupReq = 5, /**<  */
  kTopMatchaPowerManagerWakeUpsLast = 5, /**< \internal Last valid pwrmgr wakeup signal */
} top_matcha_power_manager_wake_ups_t;

/**
 * Reset Manager Software Controlled Resets
 */
typedef enum top_matcha_reset_manager_sw_resets {
  kTopMatchaResetManagerSwResetsSpiDevice = 0, /**<  */
  kTopMatchaResetManagerSwResetsSpiHost0 = 1, /**<  */
  kTopMatchaResetManagerSwResetsSpiHost1 = 2, /**<  */
  kTopMatchaResetManagerSwResetsSpiHost2 = 3, /**<  */
  kTopMatchaResetManagerSwResetsUsb = 4, /**<  */
  kTopMatchaResetManagerSwResetsUsbAon = 5, /**<  */
  kTopMatchaResetManagerSwResetsI2c0 = 6, /**<  */
  kTopMatchaResetManagerSwResetsI2c1 = 7, /**<  */
  kTopMatchaResetManagerSwResetsI2c2 = 8, /**<  */
  kTopMatchaResetManagerSwResetsSmc = 9, /**<  */
  kTopMatchaResetManagerSwResetsMl = 10, /**<  */
  kTopMatchaResetManagerSwResetsCamI2c = 11, /**<  */
  kTopMatchaResetManagerSwResetsVideo = 12, /**<  */
  kTopMatchaResetManagerSwResetsAudio = 13, /**<  */
  kTopMatchaResetManagerSwResetsLast = 13, /**< \internal Last valid rstmgr software reset request */
} top_matcha_reset_manager_sw_resets_t;

/**
 * Power Manager Reset Request Signals
 */
typedef enum top_matcha_power_manager_reset_requests {
  kTopMatchaPowerManagerResetRequestsSysrstCtrlAonRstReq = 0, /**<  */
  kTopMatchaPowerManagerResetRequestsAonTimerAonAonTimerRstReq = 1, /**<  */
  kTopMatchaPowerManagerResetRequestsLast = 1, /**< \internal Last valid pwrmgr reset_request signal */
} top_matcha_power_manager_reset_requests_t;

/**
 * Clock Manager Software-Controlled ("Gated") Clocks.
 *
 * The Software has full control over these clocks.
 */
typedef enum top_matcha_gateable_clocks {
  kTopMatchaGateableClocksIoDiv4Peri = 0, /**< Clock clk_io_div4_peri in group peri */
  kTopMatchaGateableClocksIoDiv2Peri = 1, /**< Clock clk_io_div2_peri in group peri */
  kTopMatchaGateableClocksIoPeri = 2, /**< Clock clk_io_peri in group peri */
  kTopMatchaGateableClocksUsbPeri = 3, /**< Clock clk_usb_peri in group peri */
  kTopMatchaGateableClocksVideoPeri = 4, /**< Clock clk_video_peri in group peri */
  kTopMatchaGateableClocksMlPeri = 5, /**< Clock clk_ml_peri in group peri */
  kTopMatchaGateableClocksAudioPeri = 6, /**< Clock clk_audio_peri in group peri */
  kTopMatchaGateableClocksSmcPeri = 7, /**< Clock clk_smc_peri in group peri */
  kTopMatchaGateableClocksLast = 7, /**< \internal Last Valid Gateable Clock */
} top_matcha_gateable_clocks_t;

/**
 * Clock Manager Software-Hinted Clocks.
 *
 * The Software has partial control over these clocks. It can ask them to stop,
 * but the clock manager is in control of whether the clock actually is stopped.
 */
typedef enum top_matcha_hintable_clocks {
  kTopMatchaHintableClocksMainAes = 0, /**< Clock clk_main_aes in group trans */
  kTopMatchaHintableClocksMainHmac = 1, /**< Clock clk_main_hmac in group trans */
  kTopMatchaHintableClocksMainKmac = 2, /**< Clock clk_main_kmac in group trans */
  kTopMatchaHintableClocksMainOtbn = 3, /**< Clock clk_main_otbn in group trans */
  kTopMatchaHintableClocksLast = 3, /**< \internal Last Valid Hintable Clock */
} top_matcha_hintable_clocks_t;

/**
 * MMIO Region
 *
 * MMIO region excludes any memory that is separate from the module
 * configuration space, i.e. ROM, main SRAM, and flash are excluded but
 * retention SRAM, spi_device memory, or usbdev memory are included.
 */
#define TOP_MATCHA_MMIO_BASE_ADDR 0x40000000u
#define TOP_MATCHA_MMIO_SIZE_BYTES 0x28000000u

// Header Extern Guard
#ifdef __cplusplus
}  // extern "C"
#endif

#endif  // MATCHA_HW_TOP_MATCHA_SW_AUTOGEN_TOP_MATCHA_H_