hw/top_matcha/rtl/autogen/top_matcha_pkg.sv

// Copyright lowRISC contributors.
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0
//
// ------------------- W A R N I N G: A U T O - G E N E R A T E D   C O D E !! -------------------//
// PLEASE DO NOT HAND-EDIT THIS FILE. IT HAS BEEN AUTO-GENERATED WITH THE FOLLOWING COMMAND:
//
// util/topgen_matcha.py -t hw/top_matcha/data/top_matcha.hjson \
//                -o hw/top_matcha/ \
//                --rnd_cnst_seed 4881560218908238235

package top_matcha_pkg;
  /**
   * Peripheral base address for uart0 in top matcha.
   */
  parameter int unsigned TOP_MATCHA_UART0_BASE_ADDR = 32'h40000000;

  /**
   * Peripheral size in bytes for uart0 in top matcha.
   */
  parameter int unsigned TOP_MATCHA_UART0_SIZE_BYTES = 32'h40;

  /**
   * Peripheral base address for uart1 in top matcha.
   */
  parameter int unsigned TOP_MATCHA_UART1_BASE_ADDR = 32'h40010000;

  /**
   * Peripheral size in bytes for uart1 in top matcha.
   */
  parameter int unsigned TOP_MATCHA_UART1_SIZE_BYTES = 32'h40;

  /**
   * Peripheral base address for uart2 in top matcha.
   */
  parameter int unsigned TOP_MATCHA_UART2_BASE_ADDR = 32'h40020000;

  /**
   * Peripheral size in bytes for uart2 in top matcha.
   */
  parameter int unsigned TOP_MATCHA_UART2_SIZE_BYTES = 32'h40;

  /**
   * Peripheral base address for uart3 in top matcha.
   */
  parameter int unsigned TOP_MATCHA_UART3_BASE_ADDR = 32'h40030000;

  /**
   * Peripheral size in bytes for uart3 in top matcha.
   */
  parameter int unsigned TOP_MATCHA_UART3_SIZE_BYTES = 32'h40;

  /**
   * Peripheral base address for gpio in top matcha.
   */
  parameter int unsigned TOP_MATCHA_GPIO_BASE_ADDR = 32'h40040000;

  /**
   * Peripheral size in bytes for gpio in top matcha.
   */
  parameter int unsigned TOP_MATCHA_GPIO_SIZE_BYTES = 32'h40;

  /**
   * Peripheral base address for spi_device in top matcha.
   */
  parameter int unsigned TOP_MATCHA_SPI_DEVICE_BASE_ADDR = 32'h40050000;

  /**
   * Peripheral size in bytes for spi_device in top matcha.
   */
  parameter int unsigned TOP_MATCHA_SPI_DEVICE_SIZE_BYTES = 32'h2000;

  /**
   * Peripheral base address for i2c0 in top matcha.
   */
  parameter int unsigned TOP_MATCHA_I2C0_BASE_ADDR = 32'h40080000;

  /**
   * Peripheral size in bytes for i2c0 in top matcha.
   */
  parameter int unsigned TOP_MATCHA_I2C0_SIZE_BYTES = 32'h80;

  /**
   * Peripheral base address for i2c1 in top matcha.
   */
  parameter int unsigned TOP_MATCHA_I2C1_BASE_ADDR = 32'h40090000;

  /**
   * Peripheral size in bytes for i2c1 in top matcha.
   */
  parameter int unsigned TOP_MATCHA_I2C1_SIZE_BYTES = 32'h80;

  /**
   * Peripheral base address for i2c2 in top matcha.
   */
  parameter int unsigned TOP_MATCHA_I2C2_BASE_ADDR = 32'h400A0000;

  /**
   * Peripheral size in bytes for i2c2 in top matcha.
   */
  parameter int unsigned TOP_MATCHA_I2C2_SIZE_BYTES = 32'h80;

  /**
   * Peripheral base address for pattgen in top matcha.
   */
  parameter int unsigned TOP_MATCHA_PATTGEN_BASE_ADDR = 32'h400E0000;

  /**
   * Peripheral size in bytes for pattgen in top matcha.
   */
  parameter int unsigned TOP_MATCHA_PATTGEN_SIZE_BYTES = 32'h40;

  /**
   * Peripheral base address for rv_timer in top matcha.
   */
  parameter int unsigned TOP_MATCHA_RV_TIMER_BASE_ADDR = 32'h40100000;

  /**
   * Peripheral size in bytes for rv_timer in top matcha.
   */
  parameter int unsigned TOP_MATCHA_RV_TIMER_SIZE_BYTES = 32'h200;

  /**
   * Peripheral base address for core device on otp_ctrl in top matcha.
   */
  parameter int unsigned TOP_MATCHA_OTP_CTRL_CORE_BASE_ADDR = 32'h40130000;

  /**
   * Peripheral size in bytes for core device on otp_ctrl in top matcha.
   */
  parameter int unsigned TOP_MATCHA_OTP_CTRL_CORE_SIZE_BYTES = 32'h2000;

  /**
   * Peripheral base address for prim device on otp_ctrl in top matcha.
   */
  parameter int unsigned TOP_MATCHA_OTP_CTRL_PRIM_BASE_ADDR = 32'h40132000;

  /**
   * Peripheral size in bytes for prim device on otp_ctrl in top matcha.
   */
  parameter int unsigned TOP_MATCHA_OTP_CTRL_PRIM_SIZE_BYTES = 32'h20;

  /**
   * Peripheral base address for lc_ctrl in top matcha.
   */
  parameter int unsigned TOP_MATCHA_LC_CTRL_BASE_ADDR = 32'h40140000;

  /**
   * Peripheral size in bytes for lc_ctrl in top matcha.
   */
  parameter int unsigned TOP_MATCHA_LC_CTRL_SIZE_BYTES = 32'h100;

  /**
   * Peripheral base address for alert_handler in top matcha.
   */
  parameter int unsigned TOP_MATCHA_ALERT_HANDLER_BASE_ADDR = 32'h40150000;

  /**
   * Peripheral size in bytes for alert_handler in top matcha.
   */
  parameter int unsigned TOP_MATCHA_ALERT_HANDLER_SIZE_BYTES = 32'h800;

  /**
   * Peripheral base address for spi_host0 in top matcha.
   */
  parameter int unsigned TOP_MATCHA_SPI_HOST0_BASE_ADDR = 32'h40300000;

  /**
   * Peripheral size in bytes for spi_host0 in top matcha.
   */
  parameter int unsigned TOP_MATCHA_SPI_HOST0_SIZE_BYTES = 32'h40;

  /**
   * Peripheral base address for spi_host1 in top matcha.
   */
  parameter int unsigned TOP_MATCHA_SPI_HOST1_BASE_ADDR = 32'h40310000;

  /**
   * Peripheral size in bytes for spi_host1 in top matcha.
   */
  parameter int unsigned TOP_MATCHA_SPI_HOST1_SIZE_BYTES = 32'h40;

  /**
   * Peripheral base address for usbdev in top matcha.
   */
  parameter int unsigned TOP_MATCHA_USBDEV_BASE_ADDR = 32'h40320000;

  /**
   * Peripheral size in bytes for usbdev in top matcha.
   */
  parameter int unsigned TOP_MATCHA_USBDEV_SIZE_BYTES = 32'h1000;

  /**
   * Peripheral base address for pwrmgr_aon in top matcha.
   */
  parameter int unsigned TOP_MATCHA_PWRMGR_AON_BASE_ADDR = 32'h40400000;

  /**
   * Peripheral size in bytes for pwrmgr_aon in top matcha.
   */
  parameter int unsigned TOP_MATCHA_PWRMGR_AON_SIZE_BYTES = 32'h80;

  /**
   * Peripheral base address for rstmgr_aon in top matcha.
   */
  parameter int unsigned TOP_MATCHA_RSTMGR_AON_BASE_ADDR = 32'h40410000;

  /**
   * Peripheral size in bytes for rstmgr_aon in top matcha.
   */
  parameter int unsigned TOP_MATCHA_RSTMGR_AON_SIZE_BYTES = 32'h100;

  /**
   * Peripheral base address for clkmgr_aon in top matcha.
   */
  parameter int unsigned TOP_MATCHA_CLKMGR_AON_BASE_ADDR = 32'h40420000;

  /**
   * Peripheral size in bytes for clkmgr_aon in top matcha.
   */
  parameter int unsigned TOP_MATCHA_CLKMGR_AON_SIZE_BYTES = 32'h80;

  /**
   * Peripheral base address for sysrst_ctrl_aon in top matcha.
   */
  parameter int unsigned TOP_MATCHA_SYSRST_CTRL_AON_BASE_ADDR = 32'h40430000;

  /**
   * Peripheral size in bytes for sysrst_ctrl_aon in top matcha.
   */
  parameter int unsigned TOP_MATCHA_SYSRST_CTRL_AON_SIZE_BYTES = 32'h100;

  /**
   * Peripheral base address for adc_ctrl_aon in top matcha.
   */
  parameter int unsigned TOP_MATCHA_ADC_CTRL_AON_BASE_ADDR = 32'h40440000;

  /**
   * Peripheral size in bytes for adc_ctrl_aon in top matcha.
   */
  parameter int unsigned TOP_MATCHA_ADC_CTRL_AON_SIZE_BYTES = 32'h80;

  /**
   * Peripheral base address for pwm_aon in top matcha.
   */
  parameter int unsigned TOP_MATCHA_PWM_AON_BASE_ADDR = 32'h40450000;

  /**
   * Peripheral size in bytes for pwm_aon in top matcha.
   */
  parameter int unsigned TOP_MATCHA_PWM_AON_SIZE_BYTES = 32'h80;

  /**
   * Peripheral base address for pinmux_aon in top matcha.
   */
  parameter int unsigned TOP_MATCHA_PINMUX_AON_BASE_ADDR = 32'h40460000;

  /**
   * Peripheral size in bytes for pinmux_aon in top matcha.
   */
  parameter int unsigned TOP_MATCHA_PINMUX_AON_SIZE_BYTES = 32'h1000;

  /**
   * Peripheral base address for aon_timer_aon in top matcha.
   */
  parameter int unsigned TOP_MATCHA_AON_TIMER_AON_BASE_ADDR = 32'h40470000;

  /**
   * Peripheral size in bytes for aon_timer_aon in top matcha.
   */
  parameter int unsigned TOP_MATCHA_AON_TIMER_AON_SIZE_BYTES = 32'h40;

  /**
   * Peripheral base address for ast in top matcha.
   */
  parameter int unsigned TOP_MATCHA_AST_BASE_ADDR = 32'h40480000;

  /**
   * Peripheral size in bytes for ast in top matcha.
   */
  parameter int unsigned TOP_MATCHA_AST_SIZE_BYTES = 32'h400;

  /**
   * Peripheral base address for sensor_ctrl in top matcha.
   */
  parameter int unsigned TOP_MATCHA_SENSOR_CTRL_BASE_ADDR = 32'h40490000;

  /**
   * Peripheral size in bytes for sensor_ctrl in top matcha.
   */
  parameter int unsigned TOP_MATCHA_SENSOR_CTRL_SIZE_BYTES = 32'h40;

  /**
   * Peripheral base address for regs device on sram_ctrl_ret_aon in top matcha.
   */
  parameter int unsigned TOP_MATCHA_SRAM_CTRL_RET_AON_REGS_BASE_ADDR = 32'h40500000;

  /**
   * Peripheral size in bytes for regs device on sram_ctrl_ret_aon in top matcha.
   */
  parameter int unsigned TOP_MATCHA_SRAM_CTRL_RET_AON_REGS_SIZE_BYTES = 32'h20;

  /**
   * Peripheral base address for ram device on sram_ctrl_ret_aon in top matcha.
   */
  parameter int unsigned TOP_MATCHA_SRAM_CTRL_RET_AON_RAM_BASE_ADDR = 32'h40600000;

  /**
   * Peripheral size in bytes for ram device on sram_ctrl_ret_aon in top matcha.
   */
  parameter int unsigned TOP_MATCHA_SRAM_CTRL_RET_AON_RAM_SIZE_BYTES = 32'h1000;

  /**
   * Peripheral base address for core device on flash_ctrl in top matcha.
   */
  parameter int unsigned TOP_MATCHA_FLASH_CTRL_CORE_BASE_ADDR = 32'h41000000;

  /**
   * Peripheral size in bytes for core device on flash_ctrl in top matcha.
   */
  parameter int unsigned TOP_MATCHA_FLASH_CTRL_CORE_SIZE_BYTES = 32'h200;

  /**
   * Peripheral base address for prim device on flash_ctrl in top matcha.
   */
  parameter int unsigned TOP_MATCHA_FLASH_CTRL_PRIM_BASE_ADDR = 32'h41008000;

  /**
   * Peripheral size in bytes for prim device on flash_ctrl in top matcha.
   */
  parameter int unsigned TOP_MATCHA_FLASH_CTRL_PRIM_SIZE_BYTES = 32'h80;

  /**
   * Peripheral base address for mem device on flash_ctrl in top matcha.
   */
  parameter int unsigned TOP_MATCHA_FLASH_CTRL_MEM_BASE_ADDR = 32'h20000000;

  /**
   * Peripheral size in bytes for mem device on flash_ctrl in top matcha.
   */
  parameter int unsigned TOP_MATCHA_FLASH_CTRL_MEM_SIZE_BYTES = 32'h100000;

  /**
   * Peripheral base address for regs device on rv_dm in top matcha.
   */
  parameter int unsigned TOP_MATCHA_RV_DM_REGS_BASE_ADDR = 32'h6000;

  /**
   * Peripheral size in bytes for regs device on rv_dm in top matcha.
   */
  parameter int unsigned TOP_MATCHA_RV_DM_REGS_SIZE_BYTES = 32'h4;

  /**
   * Peripheral base address for mem device on rv_dm in top matcha.
   */
  parameter int unsigned TOP_MATCHA_RV_DM_MEM_BASE_ADDR = 32'h4000;

  /**
   * Peripheral size in bytes for mem device on rv_dm in top matcha.
   */
  parameter int unsigned TOP_MATCHA_RV_DM_MEM_SIZE_BYTES = 32'h1000;

  /**
   * Peripheral base address for rv_plic in top matcha.
   */
  parameter int unsigned TOP_MATCHA_RV_PLIC_BASE_ADDR = 32'h48000000;

  /**
   * Peripheral size in bytes for rv_plic in top matcha.
   */
  parameter int unsigned TOP_MATCHA_RV_PLIC_SIZE_BYTES = 32'h8000000;

  /**
   * Peripheral base address for aes in top matcha.
   */
  parameter int unsigned TOP_MATCHA_AES_BASE_ADDR = 32'h41100000;

  /**
   * Peripheral size in bytes for aes in top matcha.
   */
  parameter int unsigned TOP_MATCHA_AES_SIZE_BYTES = 32'h100;

  /**
   * Peripheral base address for hmac in top matcha.
   */
  parameter int unsigned TOP_MATCHA_HMAC_BASE_ADDR = 32'h41110000;

  /**
   * Peripheral size in bytes for hmac in top matcha.
   */
  parameter int unsigned TOP_MATCHA_HMAC_SIZE_BYTES = 32'h1000;

  /**
   * Peripheral base address for kmac in top matcha.
   */
  parameter int unsigned TOP_MATCHA_KMAC_BASE_ADDR = 32'h41120000;

  /**
   * Peripheral size in bytes for kmac in top matcha.
   */
  parameter int unsigned TOP_MATCHA_KMAC_SIZE_BYTES = 32'h1000;

  /**
   * Peripheral base address for otbn in top matcha.
   */
  parameter int unsigned TOP_MATCHA_OTBN_BASE_ADDR = 32'h41130000;

  /**
   * Peripheral size in bytes for otbn in top matcha.
   */
  parameter int unsigned TOP_MATCHA_OTBN_SIZE_BYTES = 32'h10000;

  /**
   * Peripheral base address for keymgr in top matcha.
   */
  parameter int unsigned TOP_MATCHA_KEYMGR_BASE_ADDR = 32'h41140000;

  /**
   * Peripheral size in bytes for keymgr in top matcha.
   */
  parameter int unsigned TOP_MATCHA_KEYMGR_SIZE_BYTES = 32'h100;

  /**
   * Peripheral base address for csrng in top matcha.
   */
  parameter int unsigned TOP_MATCHA_CSRNG_BASE_ADDR = 32'h41150000;

  /**
   * Peripheral size in bytes for csrng in top matcha.
   */
  parameter int unsigned TOP_MATCHA_CSRNG_SIZE_BYTES = 32'h80;

  /**
   * Peripheral base address for entropy_src in top matcha.
   */
  parameter int unsigned TOP_MATCHA_ENTROPY_SRC_BASE_ADDR = 32'h41160000;

  /**
   * Peripheral size in bytes for entropy_src in top matcha.
   */
  parameter int unsigned TOP_MATCHA_ENTROPY_SRC_SIZE_BYTES = 32'h100;

  /**
   * Peripheral base address for edn0 in top matcha.
   */
  parameter int unsigned TOP_MATCHA_EDN0_BASE_ADDR = 32'h41170000;

  /**
   * Peripheral size in bytes for edn0 in top matcha.
   */
  parameter int unsigned TOP_MATCHA_EDN0_SIZE_BYTES = 32'h80;

  /**
   * Peripheral base address for edn1 in top matcha.
   */
  parameter int unsigned TOP_MATCHA_EDN1_BASE_ADDR = 32'h41180000;

  /**
   * Peripheral size in bytes for edn1 in top matcha.
   */
  parameter int unsigned TOP_MATCHA_EDN1_SIZE_BYTES = 32'h80;

  /**
   * Peripheral base address for regs device on sram_ctrl_main in top matcha.
   */
  parameter int unsigned TOP_MATCHA_SRAM_CTRL_MAIN_REGS_BASE_ADDR = 32'h411C0000;

  /**
   * Peripheral size in bytes for regs device on sram_ctrl_main in top matcha.
   */
  parameter int unsigned TOP_MATCHA_SRAM_CTRL_MAIN_REGS_SIZE_BYTES = 32'h20;

  /**
   * Peripheral base address for ram device on sram_ctrl_main in top matcha.
   */
  parameter int unsigned TOP_MATCHA_SRAM_CTRL_MAIN_RAM_BASE_ADDR = 32'h10000000;

  /**
   * Peripheral size in bytes for ram device on sram_ctrl_main in top matcha.
   */
  parameter int unsigned TOP_MATCHA_SRAM_CTRL_MAIN_RAM_SIZE_BYTES = 32'h20000;

  /**
   * Peripheral base address for regs device on rom_ctrl in top matcha.
   */
  parameter int unsigned TOP_MATCHA_ROM_CTRL_REGS_BASE_ADDR = 32'h411E0000;

  /**
   * Peripheral size in bytes for regs device on rom_ctrl in top matcha.
   */
  parameter int unsigned TOP_MATCHA_ROM_CTRL_REGS_SIZE_BYTES = 32'h80;

  /**
   * Peripheral base address for rom device on rom_ctrl in top matcha.
   */
  parameter int unsigned TOP_MATCHA_ROM_CTRL_ROM_BASE_ADDR = 32'h8000;

  /**
   * Peripheral size in bytes for rom device on rom_ctrl in top matcha.
   */
  parameter int unsigned TOP_MATCHA_ROM_CTRL_ROM_SIZE_BYTES = 32'h8000;

  /**
   * Peripheral base address for cfg device on rv_core_ibex_sec in top matcha.
   */
  parameter int unsigned TOP_MATCHA_RV_CORE_IBEX_SEC_CFG_BASE_ADDR = 32'h411F0000;

  /**
   * Peripheral size in bytes for cfg device on rv_core_ibex_sec in top matcha.
   */
  parameter int unsigned TOP_MATCHA_RV_CORE_IBEX_SEC_CFG_SIZE_BYTES = 32'h100;

  /**
   * Peripheral base address for dma0 in top matcha.
   */
  parameter int unsigned TOP_MATCHA_DMA0_BASE_ADDR = 32'h40200000;

  /**
   * Peripheral size in bytes for dma0 in top matcha.
   */
  parameter int unsigned TOP_MATCHA_DMA0_SIZE_BYTES = 32'h40;

  /**
   * Peripheral base address for smc_uart in top matcha.
   */
  parameter int unsigned TOP_MATCHA_SMC_UART_BASE_ADDR = 32'h54000000;

  /**
   * Peripheral size in bytes for smc_uart in top matcha.
   */
  parameter int unsigned TOP_MATCHA_SMC_UART_SIZE_BYTES = 32'h40;

  /**
   * Peripheral base address for rv_timer_smc in top matcha.
   */
  parameter int unsigned TOP_MATCHA_RV_TIMER_SMC_BASE_ADDR = 32'h54010000;

  /**
   * Peripheral size in bytes for rv_timer_smc in top matcha.
   */
  parameter int unsigned TOP_MATCHA_RV_TIMER_SMC_SIZE_BYTES = 32'h200;

  /**
   * Peripheral base address for smc_ctrl in top matcha.
   */
  parameter int unsigned TOP_MATCHA_SMC_CTRL_BASE_ADDR = 32'h54020000;

  /**
   * Peripheral size in bytes for smc_ctrl in top matcha.
   */
  parameter int unsigned TOP_MATCHA_SMC_CTRL_SIZE_BYTES = 32'h8;

  /**
   * Peripheral base address for cam_i2c in top matcha.
   */
  parameter int unsigned TOP_MATCHA_CAM_I2C_BASE_ADDR = 32'h54040000;

  /**
   * Peripheral size in bytes for cam_i2c in top matcha.
   */
  parameter int unsigned TOP_MATCHA_CAM_I2C_SIZE_BYTES = 32'h80;

  /**
   * Peripheral base address for cam_ctrl in top matcha.
   */
  parameter int unsigned TOP_MATCHA_CAM_CTRL_BASE_ADDR = 32'h54050000;

  /**
   * Peripheral size in bytes for cam_ctrl in top matcha.
   */
  parameter int unsigned TOP_MATCHA_CAM_CTRL_SIZE_BYTES = 32'h10;

  /**
   * Peripheral base address for isp_wrapper in top matcha.
   */
  parameter int unsigned TOP_MATCHA_ISP_WRAPPER_BASE_ADDR = 32'h54060000;

  /**
   * Peripheral size in bytes for isp_wrapper in top matcha.
   */
  parameter int unsigned TOP_MATCHA_ISP_WRAPPER_SIZE_BYTES = 32'h1000;

  /**
   * Peripheral base address for dma_smc in top matcha.
   */
  parameter int unsigned TOP_MATCHA_DMA_SMC_BASE_ADDR = 32'h54070000;

  /**
   * Peripheral size in bytes for dma_smc in top matcha.
   */
  parameter int unsigned TOP_MATCHA_DMA_SMC_SIZE_BYTES = 32'h40;

  /**
   * Peripheral base address for rv_plic_smc in top matcha.
   */
  parameter int unsigned TOP_MATCHA_RV_PLIC_SMC_BASE_ADDR = 32'h60000000;

  /**
   * Peripheral size in bytes for rv_plic_smc in top matcha.
   */
  parameter int unsigned TOP_MATCHA_RV_PLIC_SMC_SIZE_BYTES = 32'h8000000;

  /**
   * Peripheral base address for tlul_mailbox_sec in top matcha.
   */
  parameter int unsigned TOP_MATCHA_TLUL_MAILBOX_SEC_BASE_ADDR = 32'h40800000;

  /**
   * Peripheral size in bytes for tlul_mailbox_sec in top matcha.
   */
  parameter int unsigned TOP_MATCHA_TLUL_MAILBOX_SEC_SIZE_BYTES = 32'h40;

  /**
   * Peripheral base address for tlul_mailbox_smc in top matcha.
   */
  parameter int unsigned TOP_MATCHA_TLUL_MAILBOX_SMC_BASE_ADDR = 32'h540F1000;

  /**
   * Peripheral size in bytes for tlul_mailbox_smc in top matcha.
   */
  parameter int unsigned TOP_MATCHA_TLUL_MAILBOX_SMC_SIZE_BYTES = 32'h40;

  /**
   * Peripheral base address for core device on ml_top in top matcha.
   */
  parameter int unsigned TOP_MATCHA_ML_TOP_CORE_BASE_ADDR = 32'h5C000000;

  /**
   * Peripheral size in bytes for core device on ml_top in top matcha.
   */
  parameter int unsigned TOP_MATCHA_ML_TOP_CORE_SIZE_BYTES = 32'h40;

  /**
   * Peripheral base address for dmem device on ml_top in top matcha.
   */
  parameter int unsigned TOP_MATCHA_ML_TOP_DMEM_BASE_ADDR = 32'h5A000000;

  /**
   * Peripheral size in bytes for dmem device on ml_top in top matcha.
   */
  parameter int unsigned TOP_MATCHA_ML_TOP_DMEM_SIZE_BYTES = 32'h400000;

  /**
   * Peripheral base address for spi_host2 in top matcha.
   */
  parameter int unsigned TOP_MATCHA_SPI_HOST2_BASE_ADDR = 32'h54090000;

  /**
   * Peripheral size in bytes for spi_host2 in top matcha.
   */
  parameter int unsigned TOP_MATCHA_SPI_HOST2_SIZE_BYTES = 32'h40;

  /**
   * Peripheral base address for rv_timer_smc2 in top matcha.
   */
  parameter int unsigned TOP_MATCHA_RV_TIMER_SMC2_BASE_ADDR = 32'h54011000;

  /**
   * Peripheral size in bytes for rv_timer_smc2 in top matcha.
   */
  parameter int unsigned TOP_MATCHA_RV_TIMER_SMC2_SIZE_BYTES = 32'h200;

  /**
   * Peripheral base address for i2s0 in top matcha.
   */
  parameter int unsigned TOP_MATCHA_I2S0_BASE_ADDR = 32'h54100000;

  /**
   * Peripheral size in bytes for i2s0 in top matcha.
   */
  parameter int unsigned TOP_MATCHA_I2S0_SIZE_BYTES = 32'h40;

  /**
   * Peripheral base address for cfg device on rv_core_ibex_smc in top matcha.
   */
  parameter int unsigned TOP_MATCHA_RV_CORE_IBEX_SMC_CFG_BASE_ADDR = 32'h54030000;

  /**
   * Peripheral size in bytes for cfg device on rv_core_ibex_smc in top matcha.
   */
  parameter int unsigned TOP_MATCHA_RV_CORE_IBEX_SMC_CFG_SIZE_BYTES = 32'h100;

  /**
   * Memory base address for ram_smc in top matcha.
   */
  parameter int unsigned TOP_MATCHA_RAM_SMC_BASE_ADDR = 32'h50000000;

  /**
   * Memory size for ram_smc in top matcha.
   */
  parameter int unsigned TOP_MATCHA_RAM_SMC_SIZE_BYTES = 32'h400000;

  /**
   * Memory base address for ram_ret_aon in top matcha.
   */
  parameter int unsigned TOP_MATCHA_RAM_RET_AON_BASE_ADDR = 32'h40600000;

  /**
   * Memory size for ram_ret_aon in top matcha.
   */
  parameter int unsigned TOP_MATCHA_RAM_RET_AON_SIZE_BYTES = 32'h1000;

  /**
   * Memory base address for eflash in top matcha.
   */
  parameter int unsigned TOP_MATCHA_EFLASH_BASE_ADDR = 32'h20000000;

  /**
   * Memory size for eflash in top matcha.
   */
  parameter int unsigned TOP_MATCHA_EFLASH_SIZE_BYTES = 32'h100000;

  /**
   * Memory base address for ram_main in top matcha.
   */
  parameter int unsigned TOP_MATCHA_RAM_MAIN_BASE_ADDR = 32'h10000000;

  /**
   * Memory size for ram_main in top matcha.
   */
  parameter int unsigned TOP_MATCHA_RAM_MAIN_SIZE_BYTES = 32'h20000;

  /**
   * Memory base address for rom in top matcha.
   */
  parameter int unsigned TOP_MATCHA_ROM_BASE_ADDR = 32'h8000;

  /**
   * Memory size for rom in top matcha.
   */
  parameter int unsigned TOP_MATCHA_ROM_SIZE_BYTES = 32'h8000;

  /**
   * Memory base address for ram_ml_dmem in top matcha.
   */
  parameter int unsigned TOP_MATCHA_RAM_ML_DMEM_BASE_ADDR = 32'h5a000000;

  /**
   * Memory size for ram_ml_dmem in top matcha.
   */
  parameter int unsigned TOP_MATCHA_RAM_ML_DMEM_SIZE_BYTES = 32'h400000;


  // Enumeration of alert modules
  typedef enum int unsigned {
    TopMatchaAlertPeripheralUart0 = 0,
    TopMatchaAlertPeripheralUart1 = 1,
    TopMatchaAlertPeripheralUart2 = 2,
    TopMatchaAlertPeripheralUart3 = 3,
    TopMatchaAlertPeripheralGpio = 4,
    TopMatchaAlertPeripheralSpiDevice = 5,
    TopMatchaAlertPeripheralI2c0 = 6,
    TopMatchaAlertPeripheralI2c1 = 7,
    TopMatchaAlertPeripheralI2c2 = 8,
    TopMatchaAlertPeripheralPattgen = 9,
    TopMatchaAlertPeripheralRvTimer = 10,
    TopMatchaAlertPeripheralOtpCtrl = 11,
    TopMatchaAlertPeripheralLcCtrl = 12,
    TopMatchaAlertPeripheralSpiHost0 = 13,
    TopMatchaAlertPeripheralSpiHost1 = 14,
    TopMatchaAlertPeripheralUsbdev = 15,
    TopMatchaAlertPeripheralPwrmgrAon = 16,
    TopMatchaAlertPeripheralRstmgrAon = 17,
    TopMatchaAlertPeripheralClkmgrAon = 18,
    TopMatchaAlertPeripheralSysrstCtrlAon = 19,
    TopMatchaAlertPeripheralAdcCtrlAon = 20,
    TopMatchaAlertPeripheralPwmAon = 21,
    TopMatchaAlertPeripheralPinmuxAon = 22,
    TopMatchaAlertPeripheralAonTimerAon = 23,
    TopMatchaAlertPeripheralSensorCtrl = 24,
    TopMatchaAlertPeripheralSramCtrlRetAon = 25,
    TopMatchaAlertPeripheralFlashCtrl = 26,
    TopMatchaAlertPeripheralRvDm = 27,
    TopMatchaAlertPeripheralRvPlic = 28,
    TopMatchaAlertPeripheralAes = 29,
    TopMatchaAlertPeripheralHmac = 30,
    TopMatchaAlertPeripheralKmac = 31,
    TopMatchaAlertPeripheralOtbn = 32,
    TopMatchaAlertPeripheralKeymgr = 33,
    TopMatchaAlertPeripheralCsrng = 34,
    TopMatchaAlertPeripheralEntropySrc = 35,
    TopMatchaAlertPeripheralEdn0 = 36,
    TopMatchaAlertPeripheralEdn1 = 37,
    TopMatchaAlertPeripheralSramCtrlMain = 38,
    TopMatchaAlertPeripheralRomCtrl = 39,
    TopMatchaAlertPeripheralRvCoreIbexSec = 40,
    TopMatchaAlertPeripheralSmcUart = 41,
    TopMatchaAlertPeripheralRvTimerSmc = 42,
    TopMatchaAlertPeripheralCamI2c = 43,
    TopMatchaAlertPeripheralRvPlicSmc = 44,
    TopMatchaAlertPeripheralSpiHost2 = 45,
    TopMatchaAlertPeripheralRvTimerSmc2 = 46,
    TopMatchaAlertPeripheralRvCoreIbexSmc = 47,
    TopEarlgreyAlertPeripheralCount
  } alert_peripheral_e;

  // Enumeration of alerts
  typedef enum int unsigned {
    TopMatchaAlertIdUart0FatalFault = 0,
    TopMatchaAlertIdUart1FatalFault = 1,
    TopMatchaAlertIdUart2FatalFault = 2,
    TopMatchaAlertIdUart3FatalFault = 3,
    TopMatchaAlertIdGpioFatalFault = 4,
    TopMatchaAlertIdSpiDeviceFatalFault = 5,
    TopMatchaAlertIdI2c0FatalFault = 6,
    TopMatchaAlertIdI2c1FatalFault = 7,
    TopMatchaAlertIdI2c2FatalFault = 8,
    TopMatchaAlertIdPattgenFatalFault = 9,
    TopMatchaAlertIdRvTimerFatalFault = 10,
    TopMatchaAlertIdOtpCtrlFatalMacroError = 11,
    TopMatchaAlertIdOtpCtrlFatalCheckError = 12,
    TopMatchaAlertIdOtpCtrlFatalBusIntegError = 13,
    TopMatchaAlertIdOtpCtrlFatalPrimOtpAlert = 14,
    TopMatchaAlertIdOtpCtrlRecovPrimOtpAlert = 15,
    TopMatchaAlertIdLcCtrlFatalProgError = 16,
    TopMatchaAlertIdLcCtrlFatalStateError = 17,
    TopMatchaAlertIdLcCtrlFatalBusIntegError = 18,
    TopMatchaAlertIdSpiHost0FatalFault = 19,
    TopMatchaAlertIdSpiHost1FatalFault = 20,
    TopMatchaAlertIdUsbdevFatalFault = 21,
    TopMatchaAlertIdPwrmgrAonFatalFault = 22,
    TopMatchaAlertIdRstmgrAonFatalFault = 23,
    TopMatchaAlertIdRstmgrAonFatalCnstyFault = 24,
    TopMatchaAlertIdClkmgrAonRecovFault = 25,
    TopMatchaAlertIdClkmgrAonFatalFault = 26,
    TopMatchaAlertIdSysrstCtrlAonFatalFault = 27,
    TopMatchaAlertIdAdcCtrlAonFatalFault = 28,
    TopMatchaAlertIdPwmAonFatalFault = 29,
    TopMatchaAlertIdPinmuxAonFatalFault = 30,
    TopMatchaAlertIdAonTimerAonFatalFault = 31,
    TopMatchaAlertIdSensorCtrlRecovAlert = 32,
    TopMatchaAlertIdSensorCtrlFatalAlert = 33,
    TopMatchaAlertIdSramCtrlRetAonFatalError = 34,
    TopMatchaAlertIdFlashCtrlRecovErr = 35,
    TopMatchaAlertIdFlashCtrlFatalStdErr = 36,
    TopMatchaAlertIdFlashCtrlFatalErr = 37,
    TopMatchaAlertIdFlashCtrlFatalPrimFlashAlert = 38,
    TopMatchaAlertIdFlashCtrlRecovPrimFlashAlert = 39,
    TopMatchaAlertIdRvDmFatalFault = 40,
    TopMatchaAlertIdRvPlicFatalFault = 41,
    TopMatchaAlertIdAesRecovCtrlUpdateErr = 42,
    TopMatchaAlertIdAesFatalFault = 43,
    TopMatchaAlertIdHmacFatalFault = 44,
    TopMatchaAlertIdKmacRecovOperationErr = 45,
    TopMatchaAlertIdKmacFatalFaultErr = 46,
    TopMatchaAlertIdOtbnFatal = 47,
    TopMatchaAlertIdOtbnRecov = 48,
    TopMatchaAlertIdKeymgrRecovOperationErr = 49,
    TopMatchaAlertIdKeymgrFatalFaultErr = 50,
    TopMatchaAlertIdCsrngRecovAlert = 51,
    TopMatchaAlertIdCsrngFatalAlert = 52,
    TopMatchaAlertIdEntropySrcRecovAlert = 53,
    TopMatchaAlertIdEntropySrcFatalAlert = 54,
    TopMatchaAlertIdEdn0RecovAlert = 55,
    TopMatchaAlertIdEdn0FatalAlert = 56,
    TopMatchaAlertIdEdn1RecovAlert = 57,
    TopMatchaAlertIdEdn1FatalAlert = 58,
    TopMatchaAlertIdSramCtrlMainFatalError = 59,
    TopMatchaAlertIdRomCtrlFatal = 60,
    TopMatchaAlertIdRvCoreIbexSecFatalSwErr = 61,
    TopMatchaAlertIdRvCoreIbexSecRecovSwErr = 62,
    TopMatchaAlertIdRvCoreIbexSecFatalHwErr = 63,
    TopMatchaAlertIdRvCoreIbexSecRecovHwErr = 64,
    TopMatchaAlertIdSmcUartFatalFault = 65,
    TopMatchaAlertIdRvTimerSmcFatalFault = 66,
    TopMatchaAlertIdCamI2cFatalFault = 67,
    TopMatchaAlertIdRvPlicSmcFatalFault = 68,
    TopMatchaAlertIdSpiHost2FatalFault = 69,
    TopMatchaAlertIdRvTimerSmc2FatalFault = 70,
    TopMatchaAlertIdRvCoreIbexSmcFatalSwErr = 71,
    TopMatchaAlertIdRvCoreIbexSmcRecovSwErr = 72,
    TopMatchaAlertIdRvCoreIbexSmcFatalHwErr = 73,
    TopMatchaAlertIdRvCoreIbexSmcRecovHwErr = 74,
    TopEarlgreyAlertIdCount
  } alert_id_e;

  // Enumeration of IO power domains.
  // Only used in ASIC target.
  typedef enum logic [2:0] {
    IoBankVcc = 0,
    IoBankAvcc = 1,
    IoBankVioa = 2,
    IoBankViob = 3,
    IoBankCount = 4
  } pwr_dom_e;

  // Enumeration for MIO signals on the top-level.
  typedef enum int unsigned {
    MioInGpioGpio0 = 0,
    MioInGpioGpio1 = 1,
    MioInGpioGpio2 = 2,
    MioInGpioGpio3 = 3,
    MioInGpioGpio4 = 4,
    MioInGpioGpio5 = 5,
    MioInGpioGpio6 = 6,
    MioInGpioGpio7 = 7,
    MioInGpioGpio8 = 8,
    MioInGpioGpio9 = 9,
    MioInGpioGpio10 = 10,
    MioInGpioGpio11 = 11,
    MioInGpioGpio12 = 12,
    MioInGpioGpio13 = 13,
    MioInGpioGpio14 = 14,
    MioInGpioGpio15 = 15,
    MioInGpioGpio16 = 16,
    MioInGpioGpio17 = 17,
    MioInGpioGpio18 = 18,
    MioInGpioGpio19 = 19,
    MioInGpioGpio20 = 20,
    MioInGpioGpio21 = 21,
    MioInGpioGpio22 = 22,
    MioInGpioGpio23 = 23,
    MioInGpioGpio24 = 24,
    MioInGpioGpio25 = 25,
    MioInGpioGpio26 = 26,
    MioInGpioGpio27 = 27,
    MioInGpioGpio28 = 28,
    MioInGpioGpio29 = 29,
    MioInGpioGpio30 = 30,
    MioInGpioGpio31 = 31,
    MioInI2c0Sda = 32,
    MioInI2c0Scl = 33,
    MioInI2c1Sda = 34,
    MioInI2c1Scl = 35,
    MioInI2c2Sda = 36,
    MioInI2c2Scl = 37,
    MioInCamI2cSda = 38,
    MioInCamI2cScl = 39,
    MioInSpiHost1Sd0 = 40,
    MioInSpiHost1Sd1 = 41,
    MioInSpiHost1Sd2 = 42,
    MioInSpiHost1Sd3 = 43,
    MioInSpiHost2Sd0 = 44,
    MioInSpiHost2Sd1 = 45,
    MioInSpiHost2Sd2 = 46,
    MioInSpiHost2Sd3 = 47,
    MioInUart0Rx = 48,
    MioInUart1Rx = 49,
    MioInUart2Rx = 50,
    MioInSmcUartRx = 51,
    MioInCamCtrlCamInt = 52,
    MioInIspWrapperSPclk = 53,
    MioInIspWrapperSData0 = 54,
    MioInIspWrapperSData1 = 55,
    MioInIspWrapperSData2 = 56,
    MioInIspWrapperSData3 = 57,
    MioInIspWrapperSData4 = 58,
    MioInIspWrapperSData5 = 59,
    MioInIspWrapperSData6 = 60,
    MioInIspWrapperSData7 = 61,
    MioInIspWrapperSHsync = 62,
    MioInIspWrapperSVsync = 63,
    MioInI2s0RxSd = 64,
    MioInSpiDeviceTpmCsb = 65,
    MioInFlashCtrlTck = 66,
    MioInFlashCtrlTms = 67,
    MioInFlashCtrlTdi = 68,
    MioInSysrstCtrlAonAcPresent = 69,
    MioInSysrstCtrlAonKey0In = 70,
    MioInSysrstCtrlAonKey1In = 71,
    MioInSysrstCtrlAonKey2In = 72,
    MioInSysrstCtrlAonPwrbIn = 73,
    MioInSysrstCtrlAonLidOpen = 74,
    MioInUsbdevSense = 75,
    MioInCount = 76
  } mio_in_e;

  typedef enum {
    MioOutGpioGpio0 = 0,
    MioOutGpioGpio1 = 1,
    MioOutGpioGpio2 = 2,
    MioOutGpioGpio3 = 3,
    MioOutGpioGpio4 = 4,
    MioOutGpioGpio5 = 5,
    MioOutGpioGpio6 = 6,
    MioOutGpioGpio7 = 7,
    MioOutGpioGpio8 = 8,
    MioOutGpioGpio9 = 9,
    MioOutGpioGpio10 = 10,
    MioOutGpioGpio11 = 11,
    MioOutGpioGpio12 = 12,
    MioOutGpioGpio13 = 13,
    MioOutGpioGpio14 = 14,
    MioOutGpioGpio15 = 15,
    MioOutGpioGpio16 = 16,
    MioOutGpioGpio17 = 17,
    MioOutGpioGpio18 = 18,
    MioOutGpioGpio19 = 19,
    MioOutGpioGpio20 = 20,
    MioOutGpioGpio21 = 21,
    MioOutGpioGpio22 = 22,
    MioOutGpioGpio23 = 23,
    MioOutGpioGpio24 = 24,
    MioOutGpioGpio25 = 25,
    MioOutGpioGpio26 = 26,
    MioOutGpioGpio27 = 27,
    MioOutGpioGpio28 = 28,
    MioOutGpioGpio29 = 29,
    MioOutGpioGpio30 = 30,
    MioOutGpioGpio31 = 31,
    MioOutI2c0Sda = 32,
    MioOutI2c0Scl = 33,
    MioOutI2c1Sda = 34,
    MioOutI2c1Scl = 35,
    MioOutI2c2Sda = 36,
    MioOutI2c2Scl = 37,
    MioOutCamI2cSda = 38,
    MioOutCamI2cScl = 39,
    MioOutSpiHost1Sd0 = 40,
    MioOutSpiHost1Sd1 = 41,
    MioOutSpiHost1Sd2 = 42,
    MioOutSpiHost1Sd3 = 43,
    MioOutSpiHost2Sd0 = 44,
    MioOutSpiHost2Sd1 = 45,
    MioOutSpiHost2Sd2 = 46,
    MioOutSpiHost2Sd3 = 47,
    MioOutUart0Tx = 48,
    MioOutUart1Tx = 49,
    MioOutUart2Tx = 50,
    MioOutSmcUartTx = 51,
    MioOutCamCtrlCamTrig = 52,
    MioOutI2s0RxSclk = 53,
    MioOutI2s0RxWs = 54,
    MioOutI2s0TxSclk = 55,
    MioOutI2s0TxWs = 56,
    MioOutI2s0TxSd = 57,
    MioOutPattgenPda0Tx = 58,
    MioOutPattgenPcl0Tx = 59,
    MioOutPattgenPda1Tx = 60,
    MioOutPattgenPcl1Tx = 61,
    MioOutSpiHost1Sck = 62,
    MioOutSpiHost1Csb = 63,
    MioOutSpiHost2Sck = 64,
    MioOutSpiHost2Csb = 65,
    MioOutFlashCtrlTdo = 66,
    MioOutSensorCtrlAstDebugOut0 = 67,
    MioOutSensorCtrlAstDebugOut1 = 68,
    MioOutSensorCtrlAstDebugOut2 = 69,
    MioOutSensorCtrlAstDebugOut3 = 70,
    MioOutSensorCtrlAstDebugOut4 = 71,
    MioOutSensorCtrlAstDebugOut5 = 72,
    MioOutSensorCtrlAstDebugOut6 = 73,
    MioOutSensorCtrlAstDebugOut7 = 74,
    MioOutSensorCtrlAstDebugOut8 = 75,
    MioOutPwmAonPwm0 = 76,
    MioOutPwmAonPwm1 = 77,
    MioOutPwmAonPwm2 = 78,
    MioOutPwmAonPwm3 = 79,
    MioOutPwmAonPwm4 = 80,
    MioOutPwmAonPwm5 = 81,
    MioOutOtpCtrlTest0 = 82,
    MioOutSysrstCtrlAonBatDisable = 83,
    MioOutSysrstCtrlAonKey0Out = 84,
    MioOutSysrstCtrlAonKey1Out = 85,
    MioOutSysrstCtrlAonKey2Out = 86,
    MioOutSysrstCtrlAonPwrbOut = 87,
    MioOutSysrstCtrlAonZ3Wakeup = 88,
    MioOutCount = 89
  } mio_out_e;

  // Enumeration for DIO signals, used on both the top and chip-levels.
  typedef enum int unsigned {
    DioUsbdevUsbDp = 0,
    DioUsbdevUsbDn = 1,
    DioSpiHost0Sd0 = 2,
    DioSpiHost0Sd1 = 3,
    DioSpiHost0Sd2 = 4,
    DioSpiHost0Sd3 = 5,
    DioSpiDeviceSd0 = 6,
    DioSpiDeviceSd1 = 7,
    DioSpiDeviceSd2 = 8,
    DioSpiDeviceSd3 = 9,
    DioSysrstCtrlAonEcRstL = 10,
    DioSysrstCtrlAonFlashWpL = 11,
    DioSpiDeviceSck = 12,
    DioSpiDeviceCsb = 13,
    DioSpiHost0Sck = 14,
    DioSpiHost0Csb = 15,
    DioCount = 16
  } dio_e;

  // Enumeration for the types of pads.
  typedef enum {
    MioPad,
    DioPad
  } pad_type_e;

  // Raw MIO/DIO input array indices on chip-level.
  // TODO: Does not account for target specific stubbed/added pads.
  // Need to make a target-specific package for those.
  typedef enum int unsigned {
    MioPadIoa0 = 0,
    MioPadIoa1 = 1,
    MioPadIoa2 = 2,
    MioPadIoa3 = 3,
    MioPadIoa4 = 4,
    MioPadIoa5 = 5,
    MioPadIoa6 = 6,
    MioPadIoa7 = 7,
    MioPadIoa8 = 8,
    MioPadIob0 = 9,
    MioPadIob1 = 10,
    MioPadIob2 = 11,
    MioPadIob3 = 12,
    MioPadIob4 = 13,
    MioPadIob5 = 14,
    MioPadIob6 = 15,
    MioPadIob7 = 16,
    MioPadIob8 = 17,
    MioPadIob9 = 18,
    MioPadIob10 = 19,
    MioPadIob11 = 20,
    MioPadIob12 = 21,
    MioPadIoc0 = 22,
    MioPadIoc1 = 23,
    MioPadIoc2 = 24,
    MioPadIoc3 = 25,
    MioPadIoc4 = 26,
    MioPadIoc5 = 27,
    MioPadIoc6 = 28,
    MioPadIoc7 = 29,
    MioPadIoc8 = 30,
    MioPadIoc9 = 31,
    MioPadIoc10 = 32,
    MioPadIoc11 = 33,
    MioPadIoc12 = 34,
    MioPadIor0 = 35,
    MioPadIor1 = 36,
    MioPadIor2 = 37,
    MioPadIor3 = 38,
    MioPadIor4 = 39,
    MioPadIor5 = 40,
    MioPadIor6 = 41,
    MioPadIor7 = 42,
    MioPadIor10 = 43,
    MioPadIor11 = 44,
    MioPadIor12 = 45,
    MioPadIor13 = 46,
    MioPadIod0 = 47,
    MioPadIod1 = 48,
    MioPadIod2 = 49,
    MioPadIod3 = 50,
    MioPadIod4 = 51,
    MioPadIod5 = 52,
    MioPadCount
  } mio_pad_e;

  typedef enum int unsigned {
    DioPadPorN = 0,
    DioPadUsbP = 1,
    DioPadUsbN = 2,
    DioPadCc1 = 3,
    DioPadCc2 = 4,
    DioPadFlashTestVolt = 5,
    DioPadFlashTestMode0 = 6,
    DioPadFlashTestMode1 = 7,
    DioPadOtpExtVolt = 8,
    DioPadSpiHostD0 = 9,
    DioPadSpiHostD1 = 10,
    DioPadSpiHostD2 = 11,
    DioPadSpiHostD3 = 12,
    DioPadSpiHostClk = 13,
    DioPadSpiHostCsL = 14,
    DioPadSpiDevD0 = 15,
    DioPadSpiDevD1 = 16,
    DioPadSpiDevD2 = 17,
    DioPadSpiDevD3 = 18,
    DioPadSpiDevClk = 19,
    DioPadSpiDevCsL = 20,
    DioPadIor8 = 21,
    DioPadIor9 = 22,
    DioPadCount
  } dio_pad_e;

  // List of peripheral instantiated in this chip.
  typedef enum {
    PeripheralAdcCtrlAon,
    PeripheralAes,
    PeripheralAlertHandler,
    PeripheralAonTimerAon,
    PeripheralAst,
    PeripheralCamCtrl,
    PeripheralCamI2c,
    PeripheralClkmgrAon,
    PeripheralCsrng,
    PeripheralDma0,
    PeripheralDmaSmc,
    PeripheralEdn0,
    PeripheralEdn1,
    PeripheralEntropySrc,
    PeripheralFlashCtrl,
    PeripheralGpio,
    PeripheralHmac,
    PeripheralI2c0,
    PeripheralI2c1,
    PeripheralI2c2,
    PeripheralI2s0,
    PeripheralIspWrapper,
    PeripheralKeymgr,
    PeripheralKmac,
    PeripheralLcCtrl,
    PeripheralMlTop,
    PeripheralOtbn,
    PeripheralOtpCtrl,
    PeripheralPattgen,
    PeripheralPinmuxAon,
    PeripheralPwmAon,
    PeripheralPwrmgrAon,
    PeripheralRomCtrl,
    PeripheralRstmgrAon,
    PeripheralRvCoreIbexSec,
    PeripheralRvCoreIbexSmc,
    PeripheralRvDm,
    PeripheralRvPlic,
    PeripheralRvPlicSmc,
    PeripheralRvTimer,
    PeripheralRvTimerSmc,
    PeripheralRvTimerSmc2,
    PeripheralSensorCtrl,
    PeripheralSmcCtrl,
    PeripheralSmcUart,
    PeripheralSpiDevice,
    PeripheralSpiHost0,
    PeripheralSpiHost1,
    PeripheralSpiHost2,
    PeripheralSramCtrlMain,
    PeripheralSramCtrlRetAon,
    PeripheralSysrstCtrlAon,
    PeripheralTlulMailboxSec,
    PeripheralTlulMailboxSmc,
    PeripheralUart0,
    PeripheralUart1,
    PeripheralUart2,
    PeripheralUart3,
    PeripheralUsbdev,
    PeripheralCount
  } peripheral_e;

  // TODO: Enumeration for PLIC Interrupt source peripheral.
  // TODO: Enumeration for PLIC Interrupt Ids.

// MACROs for AST analog simulation support
`ifdef ANALOGSIM
  `define INOUT_AI input ast_pkg::awire_t
  `define INOUT_AO output ast_pkg::awire_t
`else
  `define INOUT_AI inout
  `define INOUT_AO inout
`endif

endpackage