| // Copyright 2022 Google LLC. |
| // Licensed under the Apache License, Version 2.0, see LICENSE for details. |
| // SPDX-License-Identifier: Apache-2.0 |
| // |
| // ------------------- W A R N I N G: A U T O - G E N E R A T E D C O D E !! -------------------// |
| // PLEASE DO NOT HAND-EDIT THIS FILE. IT HAS BEEN AUTO-GENERATED WITH THE FOLLOWING COMMAND: |
| // |
| // util/topgen_matcha.py -t hw/top_matcha/data/top_matcha.hjson \ |
| // -o hw/top_matcha/ \ |
| // --rnd_cnst_seed 4881560218908238235 |
| |
| module top_matcha #( |
| // Manually defined parameters |
| |
| // Auto-inferred parameters |
| // parameters for uart0 |
| // parameters for uart1 |
| // parameters for uart2 |
| // parameters for uart3 |
| // parameters for gpio |
| parameter bit GpioGpioAsyncOn = 1, |
| // parameters for spi_device |
| // parameters for i2c0 |
| // parameters for i2c1 |
| // parameters for i2c2 |
| // parameters for pattgen |
| // parameters for rv_timer |
| // parameters for otp_ctrl |
| parameter OtpCtrlMemInitFile = "", |
| // parameters for lc_ctrl |
| parameter logic [15:0] LcCtrlChipGen = 16'h 0000, |
| parameter logic [15:0] LcCtrlChipRev = 16'h 0000, |
| parameter logic [31:0] LcCtrlIdcodeValue = jtag_id_pkg::JTAG_IDCODE, |
| // parameters for alert_handler |
| // parameters for spi_host0 |
| // parameters for spi_host1 |
| // parameters for usbdev |
| parameter bit UsbdevStub = 0, |
| parameter int UsbdevRcvrWakeTimeUs = 100, |
| // parameters for pwrmgr_aon |
| // parameters for rstmgr_aon |
| parameter bit SecRstmgrAonCheck = 1'b1, |
| parameter int SecRstmgrAonMaxSyncDelay = 2, |
| // parameters for clkmgr_aon |
| // parameters for sysrst_ctrl_aon |
| // parameters for adc_ctrl_aon |
| // parameters for pwm_aon |
| // parameters for pinmux_aon |
| parameter pinmux_pkg::target_cfg_t PinmuxAonTargetCfg = pinmux_pkg::DefaultTargetCfg, |
| // parameters for aon_timer_aon |
| // parameters for sensor_ctrl |
| // parameters for sram_ctrl_ret_aon |
| parameter bit SramCtrlRetAonInstrExec = 0, |
| // parameters for flash_ctrl |
| parameter bit SecFlashCtrlScrambleEn = 1, |
| parameter int FlashCtrlProgFifoDepth = 4, |
| parameter int FlashCtrlRdFifoDepth = 16, |
| // parameters for rv_dm |
| parameter logic [31:0] RvDmIdcodeValue = jtag_id_pkg::JTAG_IDCODE, |
| // parameters for rv_plic |
| // parameters for aes |
| parameter bit SecAesMasking = 1, |
| parameter aes_pkg::sbox_impl_e SecAesSBoxImpl = aes_pkg::SBoxImplDom, |
| parameter int unsigned SecAesStartTriggerDelay = 0, |
| parameter bit SecAesAllowForcingMasks = 1'b0, |
| parameter bit SecAesSkipPRNGReseeding = 1'b0, |
| // parameters for hmac |
| // parameters for kmac |
| parameter bit KmacEnMasking = 1, |
| parameter bit KmacSwKeyMasked = 0, |
| parameter int SecKmacCmdDelay = 0, |
| parameter bit SecKmacIdleAcceptSwMsg = 0, |
| // parameters for otbn |
| parameter bit OtbnStub = 0, |
| parameter otbn_pkg::regfile_e OtbnRegFile = otbn_pkg::RegFileFF, |
| parameter bit SecOtbnMuteUrnd = 0, |
| parameter bit SecOtbnSkipUrndReseedAtStart = 0, |
| // parameters for keymgr |
| parameter bit KeymgrKmacEnMasking = 1, |
| // parameters for csrng |
| parameter aes_pkg::sbox_impl_e CsrngSBoxImpl = aes_pkg::SBoxImplCanright, |
| // parameters for entropy_src |
| parameter bit EntropySrcStub = 0, |
| // parameters for edn0 |
| // parameters for edn1 |
| // parameters for sram_ctrl_main |
| parameter bit SramCtrlMainInstrExec = 1, |
| // parameters for rom_ctrl |
| parameter RomCtrlBootRomInitFile = "", |
| parameter bit SecRomCtrlDisableScrambling = 1'b0, |
| // parameters for rv_core_ibex_sec |
| parameter bit RvCoreIbexSecPMPEnable = 1, |
| parameter int unsigned RvCoreIbexSecPMPGranularity = 0, |
| parameter int unsigned RvCoreIbexSecPMPNumRegions = 16, |
| parameter int unsigned RvCoreIbexSecMHPMCounterNum = 10, |
| parameter int unsigned RvCoreIbexSecMHPMCounterWidth = 32, |
| parameter bit RvCoreIbexSecRV32E = 0, |
| parameter ibex_pkg::rv32m_e RvCoreIbexSecRV32M = ibex_pkg::RV32MSingleCycle, |
| parameter ibex_pkg::rv32b_e RvCoreIbexSecRV32B = ibex_pkg::RV32BOTEarlGrey, |
| parameter ibex_pkg::regfile_e RvCoreIbexSecRegFile = ibex_pkg::RegFileFF, |
| parameter bit RvCoreIbexSecBranchTargetALU = 1, |
| parameter bit RvCoreIbexSecWritebackStage = 1, |
| parameter bit RvCoreIbexSecICache = 1, |
| parameter bit RvCoreIbexSecICacheECC = 1, |
| parameter bit RvCoreIbexSecICacheScramble = 1, |
| parameter bit RvCoreIbexSecBranchPredictor = 0, |
| parameter bit RvCoreIbexSecDbgTriggerEn = 1, |
| parameter int RvCoreIbexSecDbgHwBreakNum = 4, |
| parameter bit RvCoreIbexSecSecureIbex = 1, |
| parameter int unsigned RvCoreIbexSecDmHaltAddr = |
| tl_main_pkg::ADDR_SPACE_DBG + dm::HaltAddress[31:0], |
| parameter int unsigned RvCoreIbexSecDmExceptionAddr = |
| tl_main_pkg::ADDR_SPACE_DBG + dm::ExceptionAddress[31:0], |
| parameter bit RvCoreIbexSecPipeLine = 0, |
| // parameters for dma0 |
| // parameters for smc_uart |
| // parameters for rv_timer_smc |
| // parameters for smc_ctrl |
| // parameters for cam_i2c |
| // parameters for cam_ctrl |
| // parameters for isp_wrapper |
| parameter int IspWrapperAhbLiteDataWidth = 32, |
| parameter int IspWrapperTimeoutLimit = 65535, |
| // parameters for dma_smc |
| // parameters for rv_plic_smc |
| // parameters for tlul_mailbox_sec |
| parameter int TlulMailboxSecMailboxDepth = 8, |
| // parameters for tlul_mailbox_smc |
| parameter int TlulMailboxSmcMailboxDepth = 8, |
| // parameters for ml_top |
| // parameters for spi_host2 |
| // parameters for rv_timer_smc2 |
| // parameters for i2s0 |
| // parameters for rv_core_ibex_smc |
| parameter bit RvCoreIbexSmcPMPEnable = 0, |
| parameter int unsigned RvCoreIbexSmcPMPGranularity = 0, |
| parameter int unsigned RvCoreIbexSmcPMPNumRegions = 16, |
| parameter int unsigned RvCoreIbexSmcMHPMCounterNum = 10, |
| parameter int unsigned RvCoreIbexSmcMHPMCounterWidth = 32, |
| parameter bit RvCoreIbexSmcRV32E = 0, |
| parameter smc_pkg::rv32m_e RvCoreIbexSmcRV32M = smc_pkg::RV32MSingleCycle, |
| parameter smc_pkg::rv32b_e RvCoreIbexSmcRV32B = smc_pkg::RV32BNone, |
| parameter bit RvCoreIbexSmcRV32A = 1, |
| parameter smc_pkg::regfile_e RvCoreIbexSmcRegFile = smc_pkg::RegFileFF, |
| parameter bit RvCoreIbexSmcBranchTargetALU = 0, |
| parameter bit RvCoreIbexSmcWritebackStage = 0, |
| parameter bit RvCoreIbexSmcICache = 0, |
| parameter bit RvCoreIbexSmcICacheECC = 0, |
| parameter bit RvCoreIbexSmcICacheScramble = 0, |
| parameter bit RvCoreIbexSmcBranchPredictor = 0, |
| parameter bit RvCoreIbexSmcDbgTriggerEn = 1, |
| parameter int RvCoreIbexSmcDbgHwBreakNum = 1, |
| parameter bit RvCoreIbexSmcSecureSmc = 0, |
| parameter int unsigned RvCoreIbexSmcDmHaltAddr = |
| tl_main_pkg::ADDR_SPACE_DBG + dm::HaltAddress[31:0], |
| parameter int unsigned RvCoreIbexSmcDmExceptionAddr = |
| tl_main_pkg::ADDR_SPACE_DBG + dm::ExceptionAddress[31:0], |
| parameter bit RvCoreIbexSmcPipeLine = 0, |
| parameter int RvCoreIbexSmcITLBEntries = 64, |
| parameter int RvCoreIbexSmcDTLBEntries = 64, |
| parameter int RvCoreIbexSmcASIDWidth = 9 |
| ) ( |
| // Multiplexed I/O |
| input [52:0] mio_in_i, |
| output logic [52:0] mio_out_o, |
| output logic [52:0] mio_oe_o, |
| // Dedicated I/O |
| input [15:0] dio_in_i, |
| output logic [15:0] dio_out_o, |
| output logic [15:0] dio_oe_o, |
| |
| // pad attributes to padring |
| output prim_pad_wrapper_pkg::pad_attr_t [pinmux_reg_pkg::NMioPads-1:0] mio_attr_o, |
| output prim_pad_wrapper_pkg::pad_attr_t [pinmux_reg_pkg::NDioPads-1:0] dio_attr_o, |
| |
| |
| // Inter-module Signal External type |
| output ast_pkg::adc_ast_req_t adc_req_o, |
| input ast_pkg::adc_ast_rsp_t adc_rsp_i, |
| input edn_pkg::edn_req_t ast_edn_req_i, |
| output edn_pkg::edn_rsp_t ast_edn_rsp_o, |
| output lc_ctrl_pkg::lc_tx_t ast_lc_dft_en_o, |
| input ast_pkg::ast_obs_ctrl_t obs_ctrl_i, |
| input prim_ram_1p_pkg::ram_1p_cfg_t ram_1p_cfg_i, |
| input prim_ram_2p_pkg::ram_2p_cfg_t ram_2p_cfg_i, |
| input prim_rom_pkg::rom_cfg_t rom_cfg_i, |
| output prim_mubi_pkg::mubi4_t clk_main_jitter_en_o, |
| output prim_mubi_pkg::mubi4_t io_clk_byp_req_o, |
| input prim_mubi_pkg::mubi4_t io_clk_byp_ack_i, |
| output prim_mubi_pkg::mubi4_t all_clk_byp_req_o, |
| input prim_mubi_pkg::mubi4_t all_clk_byp_ack_i, |
| output prim_mubi_pkg::mubi4_t hi_speed_sel_o, |
| input prim_mubi_pkg::mubi4_t div_step_down_req_i, |
| input prim_mubi_pkg::mubi4_t calib_rdy_i, |
| input prim_mubi_pkg::mubi4_t flash_bist_enable_i, |
| input logic flash_power_down_h_i, |
| input logic flash_power_ready_h_i, |
| inout [1:0] flash_test_mode_a_io, |
| inout flash_test_voltage_h_io, |
| output logic [7:0] flash_obs_o, |
| output entropy_src_pkg::entropy_src_rng_req_t es_rng_req_o, |
| input entropy_src_pkg::entropy_src_rng_rsp_t es_rng_rsp_i, |
| output logic es_rng_fips_o, |
| output tlul_pkg::tl_h2d_t ast_tl_req_o, |
| input tlul_pkg::tl_d2h_t ast_tl_rsp_i, |
| output pinmux_pkg::dft_strap_test_req_t dft_strap_test_o, |
| input logic dft_hold_tap_sel_i, |
| output logic usb_dp_pullup_en_o, |
| output logic usb_dn_pullup_en_o, |
| output pwrmgr_pkg::pwr_ast_req_t pwrmgr_ast_req_o, |
| input pwrmgr_pkg::pwr_ast_rsp_t pwrmgr_ast_rsp_i, |
| output otp_ctrl_pkg::otp_ast_req_t otp_ctrl_otp_ast_pwr_seq_o, |
| input otp_ctrl_pkg::otp_ast_rsp_t otp_ctrl_otp_ast_pwr_seq_h_i, |
| inout otp_ext_voltage_h_io, |
| output logic [7:0] otp_obs_o, |
| input logic [1:0] por_n_i, |
| input logic [31:0] fpga_info_i, |
| input ast_pkg::ast_alert_req_t sensor_ctrl_ast_alert_req_i, |
| output ast_pkg::ast_alert_rsp_t sensor_ctrl_ast_alert_rsp_o, |
| input ast_pkg::ast_status_t sensor_ctrl_ast_status_i, |
| input logic [8:0] ast2pinmux_i, |
| input prim_mubi_pkg::mubi4_t ast_init_done_i, |
| output logic sck_monitor_o, |
| input logic usbdev_usb_rx_d_i, |
| output logic usbdev_usb_tx_d_o, |
| output logic usbdev_usb_tx_se0_o, |
| output logic usbdev_usb_tx_use_d_se0_o, |
| output logic usbdev_usb_rx_enable_o, |
| output logic usbdev_usb_ref_val_o, |
| output logic usbdev_usb_ref_pulse_o, |
| |
| |
| // All externally supplied clocks |
| input clk_main_i, |
| input clk_io_i, |
| input clk_usb_i, |
| input clk_aon_i, |
| input clk_ml_i, |
| input clk_smc_i, |
| input clk_video_i, |
| input clk_audio_i, |
| |
| // All clocks forwarded to ast |
| output clkmgr_pkg::clkmgr_out_t clks_ast_o, |
| output rstmgr_pkg::rstmgr_out_t rsts_ast_o, |
| |
| input scan_rst_ni, // reset used for test mode |
| input scan_en_i, |
| input prim_mubi_pkg::mubi4_t scanmode_i // lc_ctrl_pkg::On for Scan |
| ); |
| |
| import tlul_pkg::*; |
| import top_pkg::*; |
| import tl_main_pkg::*; |
| import tl_smc_pkg::*; |
| import top_matcha_pkg::*; |
| // Compile-time random constants |
| import top_matcha_rnd_cnst_pkg::*; |
| |
| // Signals |
| logic [75:0] mio_p2d; |
| logic [88:0] mio_d2p; |
| logic [88:0] mio_en_d2p; |
| logic [15:0] dio_p2d; |
| logic [15:0] dio_d2p; |
| logic [15:0] dio_en_d2p; |
| // uart0 |
| logic cio_uart0_rx_p2d; |
| logic cio_uart0_tx_d2p; |
| logic cio_uart0_tx_en_d2p; |
| // uart1 |
| logic cio_uart1_rx_p2d; |
| logic cio_uart1_tx_d2p; |
| logic cio_uart1_tx_en_d2p; |
| // uart2 |
| logic cio_uart2_rx_p2d; |
| logic cio_uart2_tx_d2p; |
| logic cio_uart2_tx_en_d2p; |
| // uart3 |
| logic cio_uart3_rx_p2d; |
| logic cio_uart3_tx_d2p; |
| logic cio_uart3_tx_en_d2p; |
| // gpio |
| logic [31:0] cio_gpio_gpio_p2d; |
| logic [31:0] cio_gpio_gpio_d2p; |
| logic [31:0] cio_gpio_gpio_en_d2p; |
| // spi_device |
| logic cio_spi_device_sck_p2d; |
| logic cio_spi_device_csb_p2d; |
| logic cio_spi_device_tpm_csb_p2d; |
| logic [3:0] cio_spi_device_sd_p2d; |
| logic [3:0] cio_spi_device_sd_d2p; |
| logic [3:0] cio_spi_device_sd_en_d2p; |
| // i2c0 |
| logic cio_i2c0_sda_p2d; |
| logic cio_i2c0_scl_p2d; |
| logic cio_i2c0_sda_d2p; |
| logic cio_i2c0_sda_en_d2p; |
| logic cio_i2c0_scl_d2p; |
| logic cio_i2c0_scl_en_d2p; |
| // i2c1 |
| logic cio_i2c1_sda_p2d; |
| logic cio_i2c1_scl_p2d; |
| logic cio_i2c1_sda_d2p; |
| logic cio_i2c1_sda_en_d2p; |
| logic cio_i2c1_scl_d2p; |
| logic cio_i2c1_scl_en_d2p; |
| // i2c2 |
| logic cio_i2c2_sda_p2d; |
| logic cio_i2c2_scl_p2d; |
| logic cio_i2c2_sda_d2p; |
| logic cio_i2c2_sda_en_d2p; |
| logic cio_i2c2_scl_d2p; |
| logic cio_i2c2_scl_en_d2p; |
| // pattgen |
| logic cio_pattgen_pda0_tx_d2p; |
| logic cio_pattgen_pda0_tx_en_d2p; |
| logic cio_pattgen_pcl0_tx_d2p; |
| logic cio_pattgen_pcl0_tx_en_d2p; |
| logic cio_pattgen_pda1_tx_d2p; |
| logic cio_pattgen_pda1_tx_en_d2p; |
| logic cio_pattgen_pcl1_tx_d2p; |
| logic cio_pattgen_pcl1_tx_en_d2p; |
| // rv_timer |
| // otp_ctrl |
| logic [7:0] cio_otp_ctrl_test_d2p; |
| logic [7:0] cio_otp_ctrl_test_en_d2p; |
| // lc_ctrl |
| // alert_handler |
| // spi_host0 |
| logic [3:0] cio_spi_host0_sd_p2d; |
| logic cio_spi_host0_sck_d2p; |
| logic cio_spi_host0_sck_en_d2p; |
| logic cio_spi_host0_csb_d2p; |
| logic cio_spi_host0_csb_en_d2p; |
| logic [3:0] cio_spi_host0_sd_d2p; |
| logic [3:0] cio_spi_host0_sd_en_d2p; |
| // spi_host1 |
| logic [3:0] cio_spi_host1_sd_p2d; |
| logic cio_spi_host1_sck_d2p; |
| logic cio_spi_host1_sck_en_d2p; |
| logic cio_spi_host1_csb_d2p; |
| logic cio_spi_host1_csb_en_d2p; |
| logic [3:0] cio_spi_host1_sd_d2p; |
| logic [3:0] cio_spi_host1_sd_en_d2p; |
| // usbdev |
| logic cio_usbdev_sense_p2d; |
| logic cio_usbdev_usb_dp_p2d; |
| logic cio_usbdev_usb_dn_p2d; |
| logic cio_usbdev_usb_dp_d2p; |
| logic cio_usbdev_usb_dp_en_d2p; |
| logic cio_usbdev_usb_dn_d2p; |
| logic cio_usbdev_usb_dn_en_d2p; |
| // pwrmgr_aon |
| // rstmgr_aon |
| // clkmgr_aon |
| // sysrst_ctrl_aon |
| logic cio_sysrst_ctrl_aon_ac_present_p2d; |
| logic cio_sysrst_ctrl_aon_key0_in_p2d; |
| logic cio_sysrst_ctrl_aon_key1_in_p2d; |
| logic cio_sysrst_ctrl_aon_key2_in_p2d; |
| logic cio_sysrst_ctrl_aon_pwrb_in_p2d; |
| logic cio_sysrst_ctrl_aon_lid_open_p2d; |
| logic cio_sysrst_ctrl_aon_ec_rst_l_p2d; |
| logic cio_sysrst_ctrl_aon_flash_wp_l_p2d; |
| logic cio_sysrst_ctrl_aon_bat_disable_d2p; |
| logic cio_sysrst_ctrl_aon_bat_disable_en_d2p; |
| logic cio_sysrst_ctrl_aon_key0_out_d2p; |
| logic cio_sysrst_ctrl_aon_key0_out_en_d2p; |
| logic cio_sysrst_ctrl_aon_key1_out_d2p; |
| logic cio_sysrst_ctrl_aon_key1_out_en_d2p; |
| logic cio_sysrst_ctrl_aon_key2_out_d2p; |
| logic cio_sysrst_ctrl_aon_key2_out_en_d2p; |
| logic cio_sysrst_ctrl_aon_pwrb_out_d2p; |
| logic cio_sysrst_ctrl_aon_pwrb_out_en_d2p; |
| logic cio_sysrst_ctrl_aon_z3_wakeup_d2p; |
| logic cio_sysrst_ctrl_aon_z3_wakeup_en_d2p; |
| logic cio_sysrst_ctrl_aon_ec_rst_l_d2p; |
| logic cio_sysrst_ctrl_aon_ec_rst_l_en_d2p; |
| logic cio_sysrst_ctrl_aon_flash_wp_l_d2p; |
| logic cio_sysrst_ctrl_aon_flash_wp_l_en_d2p; |
| // adc_ctrl_aon |
| // pwm_aon |
| logic [5:0] cio_pwm_aon_pwm_d2p; |
| logic [5:0] cio_pwm_aon_pwm_en_d2p; |
| // pinmux_aon |
| // aon_timer_aon |
| // sensor_ctrl |
| logic [8:0] cio_sensor_ctrl_ast_debug_out_d2p; |
| logic [8:0] cio_sensor_ctrl_ast_debug_out_en_d2p; |
| // sram_ctrl_ret_aon |
| // flash_ctrl |
| logic cio_flash_ctrl_tck_p2d; |
| logic cio_flash_ctrl_tms_p2d; |
| logic cio_flash_ctrl_tdi_p2d; |
| logic cio_flash_ctrl_tdo_d2p; |
| logic cio_flash_ctrl_tdo_en_d2p; |
| // rv_dm |
| // rv_plic |
| // aes |
| // hmac |
| // kmac |
| // otbn |
| // keymgr |
| // csrng |
| // entropy_src |
| // edn0 |
| // edn1 |
| // sram_ctrl_main |
| // rom_ctrl |
| // rv_core_ibex_sec |
| // dma0 |
| // smc_uart |
| logic cio_smc_uart_rx_p2d; |
| logic cio_smc_uart_tx_d2p; |
| logic cio_smc_uart_tx_en_d2p; |
| // rv_timer_smc |
| // smc_ctrl |
| // cam_i2c |
| logic cio_cam_i2c_sda_p2d; |
| logic cio_cam_i2c_scl_p2d; |
| logic cio_cam_i2c_sda_d2p; |
| logic cio_cam_i2c_sda_en_d2p; |
| logic cio_cam_i2c_scl_d2p; |
| logic cio_cam_i2c_scl_en_d2p; |
| // cam_ctrl |
| logic cio_cam_ctrl_cam_int_p2d; |
| logic cio_cam_ctrl_cam_trig_d2p; |
| logic cio_cam_ctrl_cam_trig_en_d2p; |
| // isp_wrapper |
| logic cio_isp_wrapper_s_pclk_p2d; |
| logic [7:0] cio_isp_wrapper_s_data_p2d; |
| logic cio_isp_wrapper_s_hsync_p2d; |
| logic cio_isp_wrapper_s_vsync_p2d; |
| // dma_smc |
| // rv_plic_smc |
| // tlul_mailbox_sec |
| // tlul_mailbox_smc |
| // ml_top |
| // spi_host2 |
| logic [3:0] cio_spi_host2_sd_p2d; |
| logic cio_spi_host2_sck_d2p; |
| logic cio_spi_host2_sck_en_d2p; |
| logic cio_spi_host2_csb_d2p; |
| logic cio_spi_host2_csb_en_d2p; |
| logic [3:0] cio_spi_host2_sd_d2p; |
| logic [3:0] cio_spi_host2_sd_en_d2p; |
| // rv_timer_smc2 |
| // i2s0 |
| logic cio_i2s0_rx_sd_p2d; |
| logic cio_i2s0_rx_sclk_d2p; |
| logic cio_i2s0_rx_sclk_en_d2p; |
| logic cio_i2s0_rx_ws_d2p; |
| logic cio_i2s0_rx_ws_en_d2p; |
| logic cio_i2s0_tx_sclk_d2p; |
| logic cio_i2s0_tx_sclk_en_d2p; |
| logic cio_i2s0_tx_ws_d2p; |
| logic cio_i2s0_tx_ws_en_d2p; |
| logic cio_i2s0_tx_sd_d2p; |
| logic cio_i2s0_tx_sd_en_d2p; |
| // rv_core_ibex_smc |
| |
| |
| logic [189:0] sec_intr_vector; |
| // Interrupt source list for Security core |
| logic intr_uart0_tx_watermark; |
| logic intr_uart0_rx_watermark; |
| logic intr_uart0_tx_empty; |
| logic intr_uart0_rx_overflow; |
| logic intr_uart0_rx_frame_err; |
| logic intr_uart0_rx_break_err; |
| logic intr_uart0_rx_timeout; |
| logic intr_uart0_rx_parity_err; |
| logic intr_uart1_tx_watermark; |
| logic intr_uart1_rx_watermark; |
| logic intr_uart1_tx_empty; |
| logic intr_uart1_rx_overflow; |
| logic intr_uart1_rx_frame_err; |
| logic intr_uart1_rx_break_err; |
| logic intr_uart1_rx_timeout; |
| logic intr_uart1_rx_parity_err; |
| logic intr_uart2_tx_watermark; |
| logic intr_uart2_rx_watermark; |
| logic intr_uart2_tx_empty; |
| logic intr_uart2_rx_overflow; |
| logic intr_uart2_rx_frame_err; |
| logic intr_uart2_rx_break_err; |
| logic intr_uart2_rx_timeout; |
| logic intr_uart2_rx_parity_err; |
| logic intr_uart3_tx_watermark; |
| logic intr_uart3_rx_watermark; |
| logic intr_uart3_tx_empty; |
| logic intr_uart3_rx_overflow; |
| logic intr_uart3_rx_frame_err; |
| logic intr_uart3_rx_break_err; |
| logic intr_uart3_rx_timeout; |
| logic intr_uart3_rx_parity_err; |
| logic [31:0] intr_gpio_gpio; |
| logic intr_spi_device_generic_rx_full; |
| logic intr_spi_device_generic_rx_watermark; |
| logic intr_spi_device_generic_tx_watermark; |
| logic intr_spi_device_generic_rx_error; |
| logic intr_spi_device_generic_rx_overflow; |
| logic intr_spi_device_generic_tx_underflow; |
| logic intr_spi_device_upload_cmdfifo_not_empty; |
| logic intr_spi_device_upload_payload_not_empty; |
| logic intr_spi_device_upload_payload_overflow; |
| logic intr_spi_device_readbuf_watermark; |
| logic intr_spi_device_readbuf_flip; |
| logic intr_spi_device_tpm_header_not_empty; |
| logic intr_i2c0_fmt_threshold; |
| logic intr_i2c0_rx_threshold; |
| logic intr_i2c0_fmt_overflow; |
| logic intr_i2c0_rx_overflow; |
| logic intr_i2c0_nak; |
| logic intr_i2c0_scl_interference; |
| logic intr_i2c0_sda_interference; |
| logic intr_i2c0_stretch_timeout; |
| logic intr_i2c0_sda_unstable; |
| logic intr_i2c0_cmd_complete; |
| logic intr_i2c0_tx_stretch; |
| logic intr_i2c0_tx_overflow; |
| logic intr_i2c0_acq_full; |
| logic intr_i2c0_unexp_stop; |
| logic intr_i2c0_host_timeout; |
| logic intr_i2c1_fmt_threshold; |
| logic intr_i2c1_rx_threshold; |
| logic intr_i2c1_fmt_overflow; |
| logic intr_i2c1_rx_overflow; |
| logic intr_i2c1_nak; |
| logic intr_i2c1_scl_interference; |
| logic intr_i2c1_sda_interference; |
| logic intr_i2c1_stretch_timeout; |
| logic intr_i2c1_sda_unstable; |
| logic intr_i2c1_cmd_complete; |
| logic intr_i2c1_tx_stretch; |
| logic intr_i2c1_tx_overflow; |
| logic intr_i2c1_acq_full; |
| logic intr_i2c1_unexp_stop; |
| logic intr_i2c1_host_timeout; |
| logic intr_i2c2_fmt_threshold; |
| logic intr_i2c2_rx_threshold; |
| logic intr_i2c2_fmt_overflow; |
| logic intr_i2c2_rx_overflow; |
| logic intr_i2c2_nak; |
| logic intr_i2c2_scl_interference; |
| logic intr_i2c2_sda_interference; |
| logic intr_i2c2_stretch_timeout; |
| logic intr_i2c2_sda_unstable; |
| logic intr_i2c2_cmd_complete; |
| logic intr_i2c2_tx_stretch; |
| logic intr_i2c2_tx_overflow; |
| logic intr_i2c2_acq_full; |
| logic intr_i2c2_unexp_stop; |
| logic intr_i2c2_host_timeout; |
| logic intr_pattgen_done_ch0; |
| logic intr_pattgen_done_ch1; |
| logic intr_rv_timer_timer_expired_hart0_timer0; |
| logic intr_otp_ctrl_otp_operation_done; |
| logic intr_otp_ctrl_otp_error; |
| logic intr_alert_handler_classa; |
| logic intr_alert_handler_classb; |
| logic intr_alert_handler_classc; |
| logic intr_alert_handler_classd; |
| logic intr_spi_host0_error; |
| logic intr_spi_host0_spi_event; |
| logic intr_spi_host1_error; |
| logic intr_spi_host1_spi_event; |
| logic intr_usbdev_pkt_received; |
| logic intr_usbdev_pkt_sent; |
| logic intr_usbdev_disconnected; |
| logic intr_usbdev_host_lost; |
| logic intr_usbdev_link_reset; |
| logic intr_usbdev_link_suspend; |
| logic intr_usbdev_link_resume; |
| logic intr_usbdev_av_empty; |
| logic intr_usbdev_rx_full; |
| logic intr_usbdev_av_overflow; |
| logic intr_usbdev_link_in_err; |
| logic intr_usbdev_rx_crc_err; |
| logic intr_usbdev_rx_pid_err; |
| logic intr_usbdev_rx_bitstuff_err; |
| logic intr_usbdev_frame; |
| logic intr_usbdev_powered; |
| logic intr_usbdev_link_out_err; |
| logic intr_pwrmgr_aon_wakeup; |
| logic intr_sysrst_ctrl_aon_event_detected; |
| logic intr_adc_ctrl_aon_match_done; |
| logic intr_aon_timer_aon_wkup_timer_expired; |
| logic intr_aon_timer_aon_wdog_timer_bark; |
| logic intr_sensor_ctrl_io_status_change; |
| logic intr_sensor_ctrl_init_status_change; |
| logic intr_flash_ctrl_prog_empty; |
| logic intr_flash_ctrl_prog_lvl; |
| logic intr_flash_ctrl_rd_full; |
| logic intr_flash_ctrl_rd_lvl; |
| logic intr_flash_ctrl_op_done; |
| logic intr_flash_ctrl_corr_err; |
| logic intr_hmac_hmac_done; |
| logic intr_hmac_fifo_empty; |
| logic intr_hmac_hmac_err; |
| logic intr_kmac_kmac_done; |
| logic intr_kmac_fifo_empty; |
| logic intr_kmac_kmac_err; |
| logic intr_otbn_done; |
| logic intr_keymgr_op_done; |
| logic intr_csrng_cs_cmd_req_done; |
| logic intr_csrng_cs_entropy_req; |
| logic intr_csrng_cs_hw_inst_exc; |
| logic intr_csrng_cs_fatal_err; |
| logic intr_entropy_src_es_entropy_valid; |
| logic intr_entropy_src_es_health_test_failed; |
| logic intr_entropy_src_es_observe_fifo_ready; |
| logic intr_entropy_src_es_fatal_err; |
| logic intr_edn0_edn_cmd_req_done; |
| logic intr_edn0_edn_fatal_err; |
| logic intr_edn1_edn_cmd_req_done; |
| logic intr_edn1_edn_fatal_err; |
| logic intr_dma0_writer_done; |
| logic intr_dma0_reader_done; |
| logic intr_tlul_mailbox_sec_wtirq; |
| logic intr_tlul_mailbox_sec_rtirq; |
| logic intr_tlul_mailbox_sec_eirq; |
| |
| // smc_intr_vector for SMC core |
| logic [42:0] smc_intr_vector; |
| // Interrupt source list for SMC core |
| logic intr_smc_uart_tx_watermark; |
| logic intr_smc_uart_rx_watermark; |
| logic intr_smc_uart_tx_empty; |
| logic intr_smc_uart_rx_overflow; |
| logic intr_smc_uart_rx_frame_err; |
| logic intr_smc_uart_rx_break_err; |
| logic intr_smc_uart_rx_timeout; |
| logic intr_smc_uart_rx_parity_err; |
| logic intr_rv_timer_smc_timer_expired_hart0_timer0; |
| logic intr_cam_i2c_fmt_threshold; |
| logic intr_cam_i2c_rx_threshold; |
| logic intr_cam_i2c_fmt_overflow; |
| logic intr_cam_i2c_rx_overflow; |
| logic intr_cam_i2c_nak; |
| logic intr_cam_i2c_scl_interference; |
| logic intr_cam_i2c_sda_interference; |
| logic intr_cam_i2c_stretch_timeout; |
| logic intr_cam_i2c_sda_unstable; |
| logic intr_cam_i2c_cmd_complete; |
| logic intr_cam_i2c_tx_stretch; |
| logic intr_cam_i2c_tx_overflow; |
| logic intr_cam_i2c_acq_full; |
| logic intr_cam_i2c_unexp_stop; |
| logic intr_cam_i2c_host_timeout; |
| logic intr_cam_ctrl_cam_motion_detect; |
| logic intr_isp_wrapper_isp; |
| logic intr_isp_wrapper_mi; |
| logic intr_dma_smc_writer_done; |
| logic intr_dma_smc_reader_done; |
| logic intr_tlul_mailbox_smc_wtirq; |
| logic intr_tlul_mailbox_smc_rtirq; |
| logic intr_tlul_mailbox_smc_eirq; |
| logic intr_ml_top_host_req; |
| logic intr_ml_top_finish; |
| logic intr_ml_top_fault; |
| logic intr_spi_host2_error; |
| logic intr_spi_host2_spi_event; |
| logic intr_rv_timer_smc2_timer_expired_hart0_timer0; |
| logic intr_i2s0_tx_watermark; |
| logic intr_i2s0_rx_watermark; |
| logic intr_i2s0_tx_empty; |
| logic intr_i2s0_rx_overflow; |
| |
| |
| // Alert list |
| prim_alert_pkg::alert_tx_t [alert_pkg::NAlerts-1:0] alert_tx; |
| prim_alert_pkg::alert_rx_t [alert_pkg::NAlerts-1:0] alert_rx; |
| |
| |
| // define inter-module signals |
| ast_pkg::ast_obs_ctrl_t ast_obs_ctrl; |
| prim_ram_1p_pkg::ram_1p_cfg_t ast_ram_1p_cfg; |
| prim_ram_2p_pkg::ram_2p_cfg_t ast_ram_2p_cfg; |
| prim_rom_pkg::rom_cfg_t ast_rom_cfg; |
| alert_pkg::alert_crashdump_t alert_handler_crashdump; |
| prim_esc_pkg::esc_rx_t [3:0] alert_handler_esc_rx; |
| prim_esc_pkg::esc_tx_t [3:0] alert_handler_esc_tx; |
| logic aon_timer_aon_nmi_wdog_timer_bark; |
| csrng_pkg::csrng_req_t [1:0] csrng_csrng_cmd_req; |
| csrng_pkg::csrng_rsp_t [1:0] csrng_csrng_cmd_rsp; |
| entropy_src_pkg::entropy_src_hw_if_req_t csrng_entropy_src_hw_if_req; |
| entropy_src_pkg::entropy_src_hw_if_rsp_t csrng_entropy_src_hw_if_rsp; |
| entropy_src_pkg::cs_aes_halt_req_t csrng_cs_aes_halt_req; |
| entropy_src_pkg::cs_aes_halt_rsp_t csrng_cs_aes_halt_rsp; |
| flash_ctrl_pkg::keymgr_flash_t flash_ctrl_keymgr; |
| otp_ctrl_pkg::flash_otp_key_req_t flash_ctrl_otp_req; |
| otp_ctrl_pkg::flash_otp_key_rsp_t flash_ctrl_otp_rsp; |
| lc_ctrl_pkg::lc_flash_rma_seed_t flash_ctrl_rma_seed; |
| otp_ctrl_pkg::sram_otp_key_req_t [2:0] otp_ctrl_sram_otp_key_req; |
| otp_ctrl_pkg::sram_otp_key_rsp_t [2:0] otp_ctrl_sram_otp_key_rsp; |
| pwrmgr_pkg::pwr_flash_t pwrmgr_aon_pwr_flash; |
| pwrmgr_pkg::pwr_rst_req_t pwrmgr_aon_pwr_rst_req; |
| pwrmgr_pkg::pwr_rst_rsp_t pwrmgr_aon_pwr_rst_rsp; |
| pwrmgr_pkg::pwr_clk_req_t pwrmgr_aon_pwr_clk_req; |
| pwrmgr_pkg::pwr_clk_rsp_t pwrmgr_aon_pwr_clk_rsp; |
| pwrmgr_pkg::pwr_otp_req_t pwrmgr_aon_pwr_otp_req; |
| pwrmgr_pkg::pwr_otp_rsp_t pwrmgr_aon_pwr_otp_rsp; |
| pwrmgr_pkg::pwr_lc_req_t pwrmgr_aon_pwr_lc_req; |
| pwrmgr_pkg::pwr_lc_rsp_t pwrmgr_aon_pwr_lc_rsp; |
| logic pwrmgr_aon_strap; |
| logic pwrmgr_aon_low_power; |
| lc_ctrl_pkg::lc_tx_t pwrmgr_aon_fetch_en; |
| rom_ctrl_pkg::pwrmgr_data_t rom_ctrl_pwrmgr_data; |
| rom_ctrl_pkg::keymgr_data_t rom_ctrl_keymgr_data; |
| lc_ctrl_pkg::lc_tx_t lc_ctrl_lc_flash_rma_req; |
| lc_ctrl_pkg::lc_tx_t flash_ctrl_rma_ack; |
| lc_ctrl_pkg::lc_tx_t otbn_lc_rma_ack; |
| logic usbdev_usb_dp_pullup; |
| logic usbdev_usb_dn_pullup; |
| logic usbdev_usb_aon_suspend_req; |
| logic usbdev_usb_aon_wake_ack; |
| logic usbdev_usb_aon_bus_reset; |
| logic usbdev_usb_aon_sense_lost; |
| logic pinmux_aon_usbdev_wake_detect_active; |
| logic isp_wrapper_isp_cvalid; |
| logic isp_wrapper_isp_cready; |
| logic isp_wrapper_isp_cwrite; |
| logic [21:0] isp_wrapper_isp_caddr; |
| logic [255:0] isp_wrapper_isp_wdata; |
| logic [31:0] isp_wrapper_isp_wmask; |
| edn_pkg::edn_req_t [7:0] edn0_edn_req; |
| edn_pkg::edn_rsp_t [7:0] edn0_edn_rsp; |
| edn_pkg::edn_req_t [7:0] edn1_edn_req; |
| edn_pkg::edn_rsp_t [7:0] edn1_edn_rsp; |
| otp_ctrl_pkg::otbn_otp_key_req_t otp_ctrl_otbn_otp_key_req; |
| otp_ctrl_pkg::otbn_otp_key_rsp_t otp_ctrl_otbn_otp_key_rsp; |
| otp_ctrl_pkg::otp_keymgr_key_t otp_ctrl_otp_keymgr_key; |
| keymgr_pkg::hw_key_req_t keymgr_aes_key; |
| keymgr_pkg::hw_key_req_t keymgr_kmac_key; |
| keymgr_pkg::otbn_key_req_t keymgr_otbn_key; |
| kmac_pkg::app_req_t [2:0] kmac_app_req; |
| kmac_pkg::app_rsp_t [2:0] kmac_app_rsp; |
| logic kmac_en_masking; |
| prim_mubi_pkg::mubi4_t [3:0] clkmgr_aon_idle; |
| jtag_pkg::jtag_req_t pinmux_aon_lc_jtag_req; |
| jtag_pkg::jtag_rsp_t pinmux_aon_lc_jtag_rsp; |
| jtag_pkg::jtag_req_t pinmux_aon_rv_jtag_req; |
| jtag_pkg::jtag_rsp_t pinmux_aon_rv_jtag_rsp; |
| lc_ctrl_pkg::lc_tx_t pinmux_aon_pinmux_hw_debug_en; |
| otp_ctrl_pkg::otp_lc_data_t otp_ctrl_otp_lc_data; |
| otp_ctrl_pkg::lc_otp_program_req_t lc_ctrl_lc_otp_program_req; |
| otp_ctrl_pkg::lc_otp_program_rsp_t lc_ctrl_lc_otp_program_rsp; |
| otp_ctrl_pkg::lc_otp_vendor_test_req_t lc_ctrl_lc_otp_vendor_test_req; |
| otp_ctrl_pkg::lc_otp_vendor_test_rsp_t lc_ctrl_lc_otp_vendor_test_rsp; |
| lc_ctrl_pkg::lc_keymgr_div_t lc_ctrl_lc_keymgr_div; |
| lc_ctrl_pkg::lc_tx_t lc_ctrl_lc_dft_en; |
| lc_ctrl_pkg::lc_tx_t lc_ctrl_lc_nvm_debug_en; |
| lc_ctrl_pkg::lc_tx_t lc_ctrl_lc_hw_debug_en; |
| lc_ctrl_pkg::lc_tx_t lc_ctrl_lc_cpu_en; |
| lc_ctrl_pkg::lc_tx_t lc_ctrl_lc_keymgr_en; |
| lc_ctrl_pkg::lc_tx_t lc_ctrl_lc_escalate_en; |
| lc_ctrl_pkg::lc_tx_t lc_ctrl_lc_check_byp_en; |
| lc_ctrl_pkg::lc_tx_t lc_ctrl_lc_clk_byp_req; |
| lc_ctrl_pkg::lc_tx_t lc_ctrl_lc_clk_byp_ack; |
| lc_ctrl_pkg::lc_tx_t lc_ctrl_lc_creator_seed_sw_rw_en; |
| lc_ctrl_pkg::lc_tx_t lc_ctrl_lc_owner_seed_sw_rw_en; |
| lc_ctrl_pkg::lc_tx_t lc_ctrl_lc_iso_part_sw_rd_en; |
| lc_ctrl_pkg::lc_tx_t lc_ctrl_lc_iso_part_sw_wr_en; |
| lc_ctrl_pkg::lc_tx_t lc_ctrl_lc_seed_hw_rd_en; |
| logic [1:0] rv_plic_msip; |
| logic [1:0] rv_plic_irq; |
| logic rv_plic_smc_msip; |
| logic rv_plic_smc_irq; |
| logic [1:0] rv_dm_debug_req; |
| rv_core_ibex_pkg::cpu_crash_dump_t rv_core_ibex_sec_crash_dump; |
| pwrmgr_pkg::pwr_cpu_t rv_core_ibex_sec_pwrmgr; |
| lc_ctrl_pkg::lc_tx_t rv_core_ibex_smc_pwrmgr_cpu_en; |
| spi_device_pkg::passthrough_req_t spi_device_passthrough_req; |
| spi_device_pkg::passthrough_rsp_t spi_device_passthrough_rsp; |
| logic rv_dm_ndmreset_req; |
| prim_mubi_pkg::mubi4_t rstmgr_aon_sw_rst_req; |
| logic [5:0] pwrmgr_aon_wakeups; |
| logic [1:0] pwrmgr_aon_rstreqs; |
| tlul_pkg::tl_h2d_t main_tl_rv_core_ibex_sec__corei_req; |
| tlul_pkg::tl_d2h_t main_tl_rv_core_ibex_sec__corei_rsp; |
| tlul_pkg::tl_h2d_t main_tl_rv_core_ibex_sec__cored_req; |
| tlul_pkg::tl_d2h_t main_tl_rv_core_ibex_sec__cored_rsp; |
| tlul_pkg::tl_h2d_t main_tl_rv_dm__sba_req; |
| tlul_pkg::tl_d2h_t main_tl_rv_dm__sba_rsp; |
| tlul_pkg::tl_h2d_t main_tl_dma0__reader_req; |
| tlul_pkg::tl_d2h_t main_tl_dma0__reader_rsp; |
| tlul_pkg::tl_h2d_t main_tl_dma0__writer_req; |
| tlul_pkg::tl_d2h_t main_tl_dma0__writer_rsp; |
| tlul_pkg::tl_h2d_t dma0_tl_d_req; |
| tlul_pkg::tl_d2h_t dma0_tl_d_rsp; |
| tlul_pkg::tl_h2d_t rom_ctrl_rom_tl_req; |
| tlul_pkg::tl_d2h_t rom_ctrl_rom_tl_rsp; |
| tlul_pkg::tl_h2d_t rom_ctrl_regs_tl_req; |
| tlul_pkg::tl_d2h_t rom_ctrl_regs_tl_rsp; |
| tlul_pkg::tl_h2d_t main_tl_peri_req; |
| tlul_pkg::tl_d2h_t main_tl_peri_rsp; |
| tlul_pkg::tl_h2d_t spi_host0_tl_req; |
| tlul_pkg::tl_d2h_t spi_host0_tl_rsp; |
| tlul_pkg::tl_h2d_t spi_host1_tl_req; |
| tlul_pkg::tl_d2h_t spi_host1_tl_rsp; |
| tlul_pkg::tl_h2d_t usbdev_tl_req; |
| tlul_pkg::tl_d2h_t usbdev_tl_rsp; |
| tlul_pkg::tl_h2d_t flash_ctrl_core_tl_req; |
| tlul_pkg::tl_d2h_t flash_ctrl_core_tl_rsp; |
| tlul_pkg::tl_h2d_t flash_ctrl_prim_tl_req; |
| tlul_pkg::tl_d2h_t flash_ctrl_prim_tl_rsp; |
| tlul_pkg::tl_h2d_t flash_ctrl_mem_tl_req; |
| tlul_pkg::tl_d2h_t flash_ctrl_mem_tl_rsp; |
| tlul_pkg::tl_h2d_t hmac_tl_req; |
| tlul_pkg::tl_d2h_t hmac_tl_rsp; |
| tlul_pkg::tl_h2d_t kmac_tl_req; |
| tlul_pkg::tl_d2h_t kmac_tl_rsp; |
| tlul_pkg::tl_h2d_t aes_tl_req; |
| tlul_pkg::tl_d2h_t aes_tl_rsp; |
| tlul_pkg::tl_h2d_t entropy_src_tl_req; |
| tlul_pkg::tl_d2h_t entropy_src_tl_rsp; |
| tlul_pkg::tl_h2d_t csrng_tl_req; |
| tlul_pkg::tl_d2h_t csrng_tl_rsp; |
| tlul_pkg::tl_h2d_t edn0_tl_req; |
| tlul_pkg::tl_d2h_t edn0_tl_rsp; |
| tlul_pkg::tl_h2d_t edn1_tl_req; |
| tlul_pkg::tl_d2h_t edn1_tl_rsp; |
| tlul_pkg::tl_h2d_t rv_plic_tl_req; |
| tlul_pkg::tl_d2h_t rv_plic_tl_rsp; |
| tlul_pkg::tl_h2d_t otbn_tl_req; |
| tlul_pkg::tl_d2h_t otbn_tl_rsp; |
| tlul_pkg::tl_h2d_t keymgr_tl_req; |
| tlul_pkg::tl_d2h_t keymgr_tl_rsp; |
| tlul_pkg::tl_h2d_t rv_core_ibex_sec_cfg_tl_d_req; |
| tlul_pkg::tl_d2h_t rv_core_ibex_sec_cfg_tl_d_rsp; |
| tlul_pkg::tl_h2d_t sram_ctrl_main_regs_tl_req; |
| tlul_pkg::tl_d2h_t sram_ctrl_main_regs_tl_rsp; |
| tlul_pkg::tl_h2d_t sram_ctrl_main_ram_tl_req; |
| tlul_pkg::tl_d2h_t sram_ctrl_main_ram_tl_rsp; |
| tlul_pkg::tl_h2d_t tlul_mailbox_sec_tl_req; |
| tlul_pkg::tl_d2h_t tlul_mailbox_sec_tl_rsp; |
| tlul_pkg::tl_h2d_t main_tl_smc_req; |
| tlul_pkg::tl_d2h_t main_tl_smc_rsp; |
| tlul_pkg::tl_h2d_t main_tl_dbg_req; |
| tlul_pkg::tl_d2h_t main_tl_dbg_rsp; |
| tlul_pkg::tl_h2d_t uart0_tl_req; |
| tlul_pkg::tl_d2h_t uart0_tl_rsp; |
| tlul_pkg::tl_h2d_t uart1_tl_req; |
| tlul_pkg::tl_d2h_t uart1_tl_rsp; |
| tlul_pkg::tl_h2d_t uart2_tl_req; |
| tlul_pkg::tl_d2h_t uart2_tl_rsp; |
| tlul_pkg::tl_h2d_t uart3_tl_req; |
| tlul_pkg::tl_d2h_t uart3_tl_rsp; |
| tlul_pkg::tl_h2d_t i2c0_tl_req; |
| tlul_pkg::tl_d2h_t i2c0_tl_rsp; |
| tlul_pkg::tl_h2d_t i2c1_tl_req; |
| tlul_pkg::tl_d2h_t i2c1_tl_rsp; |
| tlul_pkg::tl_h2d_t i2c2_tl_req; |
| tlul_pkg::tl_d2h_t i2c2_tl_rsp; |
| tlul_pkg::tl_h2d_t pattgen_tl_req; |
| tlul_pkg::tl_d2h_t pattgen_tl_rsp; |
| tlul_pkg::tl_h2d_t pwm_aon_tl_req; |
| tlul_pkg::tl_d2h_t pwm_aon_tl_rsp; |
| tlul_pkg::tl_h2d_t gpio_tl_req; |
| tlul_pkg::tl_d2h_t gpio_tl_rsp; |
| tlul_pkg::tl_h2d_t spi_device_tl_req; |
| tlul_pkg::tl_d2h_t spi_device_tl_rsp; |
| tlul_pkg::tl_h2d_t rv_timer_tl_req; |
| tlul_pkg::tl_d2h_t rv_timer_tl_rsp; |
| tlul_pkg::tl_h2d_t pwrmgr_aon_tl_req; |
| tlul_pkg::tl_d2h_t pwrmgr_aon_tl_rsp; |
| tlul_pkg::tl_h2d_t rstmgr_aon_tl_req; |
| tlul_pkg::tl_d2h_t rstmgr_aon_tl_rsp; |
| tlul_pkg::tl_h2d_t clkmgr_aon_tl_req; |
| tlul_pkg::tl_d2h_t clkmgr_aon_tl_rsp; |
| tlul_pkg::tl_h2d_t pinmux_aon_tl_req; |
| tlul_pkg::tl_d2h_t pinmux_aon_tl_rsp; |
| tlul_pkg::tl_h2d_t otp_ctrl_core_tl_req; |
| tlul_pkg::tl_d2h_t otp_ctrl_core_tl_rsp; |
| tlul_pkg::tl_h2d_t otp_ctrl_prim_tl_req; |
| tlul_pkg::tl_d2h_t otp_ctrl_prim_tl_rsp; |
| tlul_pkg::tl_h2d_t lc_ctrl_tl_req; |
| tlul_pkg::tl_d2h_t lc_ctrl_tl_rsp; |
| tlul_pkg::tl_h2d_t sensor_ctrl_tl_req; |
| tlul_pkg::tl_d2h_t sensor_ctrl_tl_rsp; |
| tlul_pkg::tl_h2d_t alert_handler_tl_req; |
| tlul_pkg::tl_d2h_t alert_handler_tl_rsp; |
| tlul_pkg::tl_h2d_t sram_ctrl_ret_aon_regs_tl_req; |
| tlul_pkg::tl_d2h_t sram_ctrl_ret_aon_regs_tl_rsp; |
| tlul_pkg::tl_h2d_t sram_ctrl_ret_aon_ram_tl_req; |
| tlul_pkg::tl_d2h_t sram_ctrl_ret_aon_ram_tl_rsp; |
| tlul_pkg::tl_h2d_t aon_timer_aon_tl_req; |
| tlul_pkg::tl_d2h_t aon_timer_aon_tl_rsp; |
| tlul_pkg::tl_h2d_t sysrst_ctrl_aon_tl_req; |
| tlul_pkg::tl_d2h_t sysrst_ctrl_aon_tl_rsp; |
| tlul_pkg::tl_h2d_t adc_ctrl_aon_tl_req; |
| tlul_pkg::tl_d2h_t adc_ctrl_aon_tl_rsp; |
| tlul_pkg::tl_h2d_t smc_tl_rv_core_ibex_smc__corei_req; |
| tlul_pkg::tl_d2h_t smc_tl_rv_core_ibex_smc__corei_rsp; |
| tlul_pkg::tl_h2d_t smc_tl_rv_core_ibex_smc__cored_req; |
| tlul_pkg::tl_d2h_t smc_tl_rv_core_ibex_smc__cored_rsp; |
| tlul_pkg::tl_h2d_t smc_tl_dma_smc__reader_req; |
| tlul_pkg::tl_d2h_t smc_tl_dma_smc__reader_rsp; |
| tlul_pkg::tl_h2d_t smc_tl_dma_smc__writer_req; |
| tlul_pkg::tl_d2h_t smc_tl_dma_smc__writer_rsp; |
| tlul_pkg::tl_h2d_t rv_plic_smc_tl_req; |
| tlul_pkg::tl_d2h_t rv_plic_smc_tl_rsp; |
| tlul_pkg::tl_h2d_t rv_core_ibex_smc_cfg_tl_d_req; |
| tlul_pkg::tl_d2h_t rv_core_ibex_smc_cfg_tl_d_rsp; |
| tlul_pkg::tl_h2d_t ram_smc_tl_req; |
| tlul_pkg::tl_d2h_t ram_smc_tl_rsp; |
| tlul_pkg::tl_h2d_t smc_uart_tl_req; |
| tlul_pkg::tl_d2h_t smc_uart_tl_rsp; |
| tlul_pkg::tl_h2d_t rv_timer_smc_tl_req; |
| tlul_pkg::tl_d2h_t rv_timer_smc_tl_rsp; |
| tlul_pkg::tl_h2d_t tlul_mailbox_smc_tl_req; |
| tlul_pkg::tl_d2h_t tlul_mailbox_smc_tl_rsp; |
| tlul_pkg::tl_h2d_t smc_ctrl_tl_req; |
| tlul_pkg::tl_d2h_t smc_ctrl_tl_rsp; |
| tlul_pkg::tl_h2d_t cam_i2c_tl_req; |
| tlul_pkg::tl_d2h_t cam_i2c_tl_rsp; |
| tlul_pkg::tl_h2d_t cam_ctrl_tl_req; |
| tlul_pkg::tl_d2h_t cam_ctrl_tl_rsp; |
| tlul_pkg::tl_h2d_t ml_top_dmem_tl_req; |
| tlul_pkg::tl_d2h_t ml_top_dmem_tl_rsp; |
| tlul_pkg::tl_h2d_t ml_top_core_tl_req; |
| tlul_pkg::tl_d2h_t ml_top_core_tl_rsp; |
| tlul_pkg::tl_h2d_t isp_wrapper_tl_req; |
| tlul_pkg::tl_d2h_t isp_wrapper_tl_rsp; |
| tlul_pkg::tl_h2d_t dma_smc_tl_d_req; |
| tlul_pkg::tl_d2h_t dma_smc_tl_d_rsp; |
| tlul_pkg::tl_h2d_t spi_host2_tl_req; |
| tlul_pkg::tl_d2h_t spi_host2_tl_rsp; |
| tlul_pkg::tl_h2d_t smc_tl_dbg_req; |
| tlul_pkg::tl_d2h_t smc_tl_dbg_rsp; |
| tlul_pkg::tl_h2d_t rv_timer_smc2_tl_req; |
| tlul_pkg::tl_d2h_t rv_timer_smc2_tl_rsp; |
| tlul_pkg::tl_h2d_t i2s0_tl_req; |
| tlul_pkg::tl_d2h_t i2s0_tl_rsp; |
| tlul_pkg::tl_h2d_t rv_dm_regs_tl_d_req; |
| tlul_pkg::tl_d2h_t rv_dm_regs_tl_d_rsp; |
| tlul_pkg::tl_h2d_t rv_dm_mem_tl_d_req; |
| tlul_pkg::tl_d2h_t rv_dm_mem_tl_d_rsp; |
| clkmgr_pkg::clkmgr_out_t clkmgr_aon_clocks; |
| clkmgr_pkg::clkmgr_cg_en_t clkmgr_aon_cg_en; |
| rstmgr_pkg::rstmgr_out_t rstmgr_aon_resets; |
| rstmgr_pkg::rstmgr_rst_en_t rstmgr_aon_rst_en; |
| logic rv_core_ibex_sec_irq_timer; |
| logic rv_core_ibex_smc_irq_timer; |
| logic [31:0] rv_core_ibex_sec_hart_id; |
| logic [31:0] rv_core_ibex_sec_boot_addr; |
| logic [31:0] rv_core_ibex_smc_hart_id; |
| logic [31:0] rv_core_ibex_smc_boot_addr; |
| jtag_pkg::jtag_req_t pinmux_aon_dft_jtag_req; |
| jtag_pkg::jtag_rsp_t pinmux_aon_dft_jtag_rsp; |
| otp_ctrl_part_pkg::otp_hw_cfg_t otp_ctrl_otp_hw_cfg; |
| prim_mubi_pkg::mubi8_t csrng_otp_en_csrng_sw_app_read; |
| prim_mubi_pkg::mubi8_t entropy_src_otp_en_entropy_src_fw_read; |
| prim_mubi_pkg::mubi8_t entropy_src_otp_en_entropy_src_fw_over; |
| otp_ctrl_pkg::otp_device_id_t lc_ctrl_otp_device_id; |
| otp_ctrl_pkg::otp_manuf_state_t lc_ctrl_otp_manuf_state; |
| otp_ctrl_pkg::otp_device_id_t keymgr_otp_device_id; |
| prim_mubi_pkg::mubi8_t sram_ctrl_main_otp_en_sram_ifetch; |
| |
| // define mixed connection to port |
| assign edn0_edn_req[2] = ast_edn_req_i; |
| assign ast_edn_rsp_o = edn0_edn_rsp[2]; |
| assign ast_lc_dft_en_o = lc_ctrl_lc_dft_en; |
| assign ast_obs_ctrl = obs_ctrl_i; |
| assign ast_ram_1p_cfg = ram_1p_cfg_i; |
| assign ast_ram_2p_cfg = ram_2p_cfg_i; |
| assign ast_rom_cfg = rom_cfg_i; |
| |
| // define partial inter-module tie-off |
| edn_pkg::edn_rsp_t unused_edn1_edn_rsp1; |
| edn_pkg::edn_rsp_t unused_edn1_edn_rsp2; |
| edn_pkg::edn_rsp_t unused_edn1_edn_rsp3; |
| edn_pkg::edn_rsp_t unused_edn1_edn_rsp4; |
| edn_pkg::edn_rsp_t unused_edn1_edn_rsp5; |
| edn_pkg::edn_rsp_t unused_edn1_edn_rsp6; |
| edn_pkg::edn_rsp_t unused_edn1_edn_rsp7; |
| |
| // assign partial inter-module tie-off |
| assign unused_edn1_edn_rsp1 = edn1_edn_rsp[1]; |
| assign unused_edn1_edn_rsp2 = edn1_edn_rsp[2]; |
| assign unused_edn1_edn_rsp3 = edn1_edn_rsp[3]; |
| assign unused_edn1_edn_rsp4 = edn1_edn_rsp[4]; |
| assign unused_edn1_edn_rsp5 = edn1_edn_rsp[5]; |
| assign unused_edn1_edn_rsp6 = edn1_edn_rsp[6]; |
| assign unused_edn1_edn_rsp7 = edn1_edn_rsp[7]; |
| assign edn1_edn_req[1] = '0; |
| assign edn1_edn_req[2] = '0; |
| assign edn1_edn_req[3] = '0; |
| assign edn1_edn_req[4] = '0; |
| assign edn1_edn_req[5] = '0; |
| assign edn1_edn_req[6] = '0; |
| assign edn1_edn_req[7] = '0; |
| |
| |
| // OTP HW_CFG Broadcast signals. |
| // TODO(#6713): The actual struct breakout and mapping currently needs to |
| // be performed by hand. |
| assign csrng_otp_en_csrng_sw_app_read = otp_ctrl_otp_hw_cfg.data.en_csrng_sw_app_read; |
| assign entropy_src_otp_en_entropy_src_fw_read = otp_ctrl_otp_hw_cfg.data.en_entropy_src_fw_read; |
| assign entropy_src_otp_en_entropy_src_fw_over = otp_ctrl_otp_hw_cfg.data.en_entropy_src_fw_over; |
| assign sram_ctrl_main_otp_en_sram_ifetch = otp_ctrl_otp_hw_cfg.data.en_sram_ifetch; |
| assign lc_ctrl_otp_device_id = otp_ctrl_otp_hw_cfg.data.device_id; |
| assign lc_ctrl_otp_manuf_state = otp_ctrl_otp_hw_cfg.data.manuf_state; |
| assign keymgr_otp_device_id = otp_ctrl_otp_hw_cfg.data.device_id; |
| |
| logic unused_otp_hw_cfg_bits; |
| assign unused_otp_hw_cfg_bits = ^{ |
| otp_ctrl_otp_hw_cfg.valid, |
| otp_ctrl_otp_hw_cfg.data.hw_cfg_digest, |
| otp_ctrl_otp_hw_cfg.data.unallocated |
| }; |
| |
| // See #7978 This below is a hack. |
| // This is because ast is a comportable-like module that sits outside |
| // of top_matcha's boundary. |
| assign clks_ast_o = clkmgr_aon_clocks; |
| assign rsts_ast_o = rstmgr_aon_resets; |
| |
| // ibex specific assignments |
| // TODO(b/271173103). |
| assign rv_core_ibex_sec_irq_timer = intr_rv_timer_timer_expired_hart0_timer0; |
| assign rv_core_ibex_sec_hart_id = 0; |
| |
| assign rv_core_ibex_smc_irq_timer = intr_rv_timer_smc_timer_expired_hart0_timer0; |
| assign rv_core_ibex_smc_hart_id = 1; |
| |
| assign rv_core_ibex_sec_boot_addr = ADDR_SPACE_ROM_CTRL__ROM; |
| assign rv_core_ibex_smc_boot_addr = ADDR_SPACE_RAM_SMC; |
| |
| |
| // Struct breakout module tool-inserted DFT TAP signals |
| pinmux_jtag_breakout u_dft_tap_breakout ( |
| .req_i (pinmux_aon_dft_jtag_req), |
| .rsp_o (pinmux_aon_dft_jtag_rsp), |
| .tck_o (), |
| .trst_no (), |
| .tms_o (), |
| .tdi_o (), |
| .tdo_i (1'b0), |
| .tdo_oe_i (1'b0) |
| ); |
| |
| // sram device |
| logic ram_smc_req; |
| logic ram_smc_we; |
| logic [19:0] ram_smc_addr; |
| logic [31:0] ram_smc_wdata; |
| logic [31:0] ram_smc_wmask; |
| logic [31:0] ram_smc_rdata; |
| logic ram_smc_rvalid; |
| logic [1:0] ram_smc_rerror; |
| |
| tluh_adapter_sram #( |
| .MemLatency(1), |
| .MaxBurstSize(2) |
| ) u_tl_adapter_ram_smc ( |
| .clk_i (clkmgr_aon_clocks.clk_smc_infra), |
| .rst_ni (rstmgr_aon_resets.rst_smc_n[rstmgr_pkg::Domain0Sel]), |
| .tl_i (ram_smc_tl_req), |
| .tl_o (ram_smc_tl_rsp), |
| |
| .req_o (ram_smc_req), |
| .gnt_i (ram_smc_req), // Grant when requests occur |
| .we_o (ram_smc_we), |
| .addr_o (ram_smc_addr), |
| .wdata_o (ram_smc_wdata), |
| .wmask_o (ram_smc_wmask), |
| .rdata_i (ram_smc_rdata), |
| .rvalid_i (ram_smc_rvalid), |
| .err_i (ram_smc_rerror[0]) |
| ); |
| |
| prim_ram_1p_adv #( |
| .Width(32), |
| .Depth(1048576), |
| .DataBitsPerMask(8), |
| // TODO: enable parity once supported by the simulation infrastructure |
| .EnableParity(0) |
| ) u_ram1p_ram_smc ( |
| .clk_i (clkmgr_aon_clocks.clk_smc_infra), |
| .rst_ni (rstmgr_aon_resets.rst_smc_n[rstmgr_pkg::Domain0Sel]), |
| .req_i (ram_smc_req), |
| .write_i (ram_smc_we), |
| .addr_i (ram_smc_addr), |
| .wdata_i (ram_smc_wdata), |
| .wmask_i (ram_smc_wmask), |
| .rdata_o (ram_smc_rdata), |
| .rvalid_o (ram_smc_rvalid), |
| .rerror_o (ram_smc_rerror), |
| .cfg_i ('0) |
| ); |
| |
| // Wire up alert handler LPGs |
| prim_mubi_pkg::mubi4_t [alert_pkg::NLpg-1:0] lpg_cg_en; |
| prim_mubi_pkg::mubi4_t [alert_pkg::NLpg-1:0] lpg_rst_en; |
| |
| |
| // peri_lc_io_div4_0 |
| assign lpg_cg_en[0] = clkmgr_aon_cg_en.io_div4_peri; |
| assign lpg_rst_en[0] = rstmgr_aon_rst_en.lc_io_div4[rstmgr_pkg::Domain0Sel]; |
| // peri_spi_device_0 |
| assign lpg_cg_en[1] = clkmgr_aon_cg_en.io_div4_peri; |
| assign lpg_rst_en[1] = rstmgr_aon_rst_en.spi_device[rstmgr_pkg::Domain0Sel]; |
| // peri_i2c0_0 |
| assign lpg_cg_en[2] = clkmgr_aon_cg_en.io_div4_peri; |
| assign lpg_rst_en[2] = rstmgr_aon_rst_en.i2c0[rstmgr_pkg::Domain0Sel]; |
| // peri_i2c1_0 |
| assign lpg_cg_en[3] = clkmgr_aon_cg_en.io_div4_peri; |
| assign lpg_rst_en[3] = rstmgr_aon_rst_en.i2c1[rstmgr_pkg::Domain0Sel]; |
| // peri_i2c2_0 |
| assign lpg_cg_en[4] = clkmgr_aon_cg_en.io_div4_peri; |
| assign lpg_rst_en[4] = rstmgr_aon_rst_en.i2c2[rstmgr_pkg::Domain0Sel]; |
| // timers_lc_io_div4_0 |
| assign lpg_cg_en[5] = clkmgr_aon_cg_en.io_div4_timers; |
| assign lpg_rst_en[5] = rstmgr_aon_rst_en.lc_io_div4[rstmgr_pkg::Domain0Sel]; |
| // secure_lc_io_div4_0 |
| assign lpg_cg_en[6] = clkmgr_aon_cg_en.io_div4_secure; |
| assign lpg_rst_en[6] = rstmgr_aon_rst_en.lc_io_div4[rstmgr_pkg::Domain0Sel]; |
| // peri_spi_host0_0 |
| assign lpg_cg_en[7] = clkmgr_aon_cg_en.io_peri; |
| assign lpg_rst_en[7] = rstmgr_aon_rst_en.spi_host0[rstmgr_pkg::Domain0Sel]; |
| // peri_spi_host1_0 |
| assign lpg_cg_en[8] = clkmgr_aon_cg_en.io_peri; |
| assign lpg_rst_en[8] = rstmgr_aon_rst_en.spi_host1[rstmgr_pkg::Domain0Sel]; |
| // peri_usb_0 |
| assign lpg_cg_en[9] = clkmgr_aon_cg_en.usb_peri; |
| assign lpg_rst_en[9] = rstmgr_aon_rst_en.usb[rstmgr_pkg::Domain0Sel]; |
| // powerup_por_io_div4_Aon |
| assign lpg_cg_en[10] = clkmgr_aon_cg_en.io_div4_powerup; |
| assign lpg_rst_en[10] = rstmgr_aon_rst_en.por_io_div4[rstmgr_pkg::DomainAonSel]; |
| // powerup_lc_io_div4_Aon |
| assign lpg_cg_en[11] = clkmgr_aon_cg_en.io_div4_powerup; |
| assign lpg_rst_en[11] = rstmgr_aon_rst_en.lc_io_div4[rstmgr_pkg::DomainAonSel]; |
| // secure_lc_io_div4_Aon |
| assign lpg_cg_en[12] = clkmgr_aon_cg_en.io_div4_secure; |
| assign lpg_rst_en[12] = rstmgr_aon_rst_en.lc_io_div4[rstmgr_pkg::DomainAonSel]; |
| // peri_lc_io_div4_Aon |
| assign lpg_cg_en[13] = clkmgr_aon_cg_en.io_div4_peri; |
| assign lpg_rst_en[13] = rstmgr_aon_rst_en.lc_io_div4[rstmgr_pkg::DomainAonSel]; |
| // timers_lc_io_div4_Aon |
| assign lpg_cg_en[14] = clkmgr_aon_cg_en.io_div4_timers; |
| assign lpg_rst_en[14] = rstmgr_aon_rst_en.lc_io_div4[rstmgr_pkg::DomainAonSel]; |
| // infra_lc_io_div4_0 |
| assign lpg_cg_en[15] = clkmgr_aon_cg_en.io_div4_infra; |
| assign lpg_rst_en[15] = rstmgr_aon_rst_en.lc_io_div4[rstmgr_pkg::Domain0Sel]; |
| // infra_lc_io_div4_Aon |
| assign lpg_cg_en[16] = clkmgr_aon_cg_en.io_div4_infra; |
| assign lpg_rst_en[16] = rstmgr_aon_rst_en.lc_io_div4[rstmgr_pkg::DomainAonSel]; |
| // infra_lc_0 |
| assign lpg_cg_en[17] = clkmgr_aon_cg_en.main_infra; |
| assign lpg_rst_en[17] = rstmgr_aon_rst_en.lc[rstmgr_pkg::Domain0Sel]; |
| // infra_sys_0 |
| assign lpg_cg_en[18] = clkmgr_aon_cg_en.main_infra; |
| assign lpg_rst_en[18] = rstmgr_aon_rst_en.sys[rstmgr_pkg::Domain0Sel]; |
| // secure_lc_0 |
| assign lpg_cg_en[19] = clkmgr_aon_cg_en.main_secure; |
| assign lpg_rst_en[19] = rstmgr_aon_rst_en.lc[rstmgr_pkg::Domain0Sel]; |
| // aes_trans_lc_0 |
| assign lpg_cg_en[20] = clkmgr_aon_cg_en.main_aes; |
| assign lpg_rst_en[20] = rstmgr_aon_rst_en.lc[rstmgr_pkg::Domain0Sel]; |
| // hmac_trans_lc_0 |
| assign lpg_cg_en[21] = clkmgr_aon_cg_en.main_hmac; |
| assign lpg_rst_en[21] = rstmgr_aon_rst_en.lc[rstmgr_pkg::Domain0Sel]; |
| // kmac_trans_lc_0 |
| assign lpg_cg_en[22] = clkmgr_aon_cg_en.main_kmac; |
| assign lpg_rst_en[22] = rstmgr_aon_rst_en.lc[rstmgr_pkg::Domain0Sel]; |
| // otbn_trans_lc_0 |
| assign lpg_cg_en[23] = clkmgr_aon_cg_en.main_otbn; |
| assign lpg_rst_en[23] = rstmgr_aon_rst_en.lc[rstmgr_pkg::Domain0Sel]; |
| // secure_smc_0 |
| assign lpg_cg_en[24] = clkmgr_aon_cg_en.smc_secure; |
| assign lpg_rst_en[24] = rstmgr_aon_rst_en.smc[rstmgr_pkg::Domain0Sel]; |
| // peri_cam_i2c_0 |
| assign lpg_cg_en[25] = clkmgr_aon_cg_en.io_div4_peri; |
| assign lpg_rst_en[25] = rstmgr_aon_rst_en.cam_i2c[rstmgr_pkg::Domain0Sel]; |
| // peri_smc_0 |
| assign lpg_cg_en[26] = clkmgr_aon_cg_en.video_peri; |
| assign lpg_rst_en[26] = rstmgr_aon_rst_en.smc[rstmgr_pkg::Domain0Sel]; |
| // infra_smc_0 |
| assign lpg_cg_en[27] = clkmgr_aon_cg_en.smc_infra; |
| assign lpg_rst_en[27] = rstmgr_aon_rst_en.smc[rstmgr_pkg::Domain0Sel]; |
| // peri_ml_0 |
| assign lpg_cg_en[28] = clkmgr_aon_cg_en.ml_peri; |
| assign lpg_rst_en[28] = rstmgr_aon_rst_en.ml[rstmgr_pkg::Domain0Sel]; |
| // peri_spi_host2_0 |
| assign lpg_cg_en[29] = clkmgr_aon_cg_en.io_peri; |
| assign lpg_rst_en[29] = rstmgr_aon_rst_en.spi_host2[rstmgr_pkg::Domain0Sel]; |
| // timers_sys_io_div4_0 |
| assign lpg_cg_en[30] = clkmgr_aon_cg_en.io_div4_timers; |
| assign lpg_rst_en[30] = rstmgr_aon_rst_en.sys_io_div4[rstmgr_pkg::Domain0Sel]; |
| // peri_sys_io_div4_0 |
| assign lpg_cg_en[31] = clkmgr_aon_cg_en.io_div4_peri; |
| assign lpg_rst_en[31] = rstmgr_aon_rst_en.sys_io_div4[rstmgr_pkg::Domain0Sel]; |
| |
| // tie-off unused connections |
| //VCS coverage off |
| // pragma coverage off |
| prim_mubi_pkg::mubi4_t unused_cg_en_0; |
| assign unused_cg_en_0 = clkmgr_aon_cg_en.aon_powerup; |
| prim_mubi_pkg::mubi4_t unused_cg_en_1; |
| assign unused_cg_en_1 = clkmgr_aon_cg_en.main_powerup; |
| prim_mubi_pkg::mubi4_t unused_cg_en_2; |
| assign unused_cg_en_2 = clkmgr_aon_cg_en.io_powerup; |
| prim_mubi_pkg::mubi4_t unused_cg_en_3; |
| assign unused_cg_en_3 = clkmgr_aon_cg_en.usb_powerup; |
| prim_mubi_pkg::mubi4_t unused_cg_en_4; |
| assign unused_cg_en_4 = clkmgr_aon_cg_en.io_div2_powerup; |
| prim_mubi_pkg::mubi4_t unused_cg_en_5; |
| assign unused_cg_en_5 = clkmgr_aon_cg_en.smc_powerup; |
| prim_mubi_pkg::mubi4_t unused_cg_en_6; |
| assign unused_cg_en_6 = clkmgr_aon_cg_en.ml_powerup; |
| prim_mubi_pkg::mubi4_t unused_cg_en_7; |
| assign unused_cg_en_7 = clkmgr_aon_cg_en.video_powerup; |
| prim_mubi_pkg::mubi4_t unused_cg_en_8; |
| assign unused_cg_en_8 = clkmgr_aon_cg_en.audio_powerup; |
| prim_mubi_pkg::mubi4_t unused_cg_en_9; |
| assign unused_cg_en_9 = clkmgr_aon_cg_en.aon_secure; |
| prim_mubi_pkg::mubi4_t unused_cg_en_10; |
| assign unused_cg_en_10 = clkmgr_aon_cg_en.aon_peri; |
| prim_mubi_pkg::mubi4_t unused_cg_en_11; |
| assign unused_cg_en_11 = clkmgr_aon_cg_en.aon_timers; |
| prim_mubi_pkg::mubi4_t unused_cg_en_12; |
| assign unused_cg_en_12 = clkmgr_aon_cg_en.usb_infra; |
| prim_mubi_pkg::mubi4_t unused_cg_en_13; |
| assign unused_cg_en_13 = clkmgr_aon_cg_en.io_infra; |
| prim_mubi_pkg::mubi4_t unused_cg_en_14; |
| assign unused_cg_en_14 = clkmgr_aon_cg_en.ml_infra; |
| prim_mubi_pkg::mubi4_t unused_cg_en_15; |
| assign unused_cg_en_15 = clkmgr_aon_cg_en.video_infra; |
| prim_mubi_pkg::mubi4_t unused_cg_en_16; |
| assign unused_cg_en_16 = clkmgr_aon_cg_en.audio_infra; |
| prim_mubi_pkg::mubi4_t unused_cg_en_17; |
| assign unused_cg_en_17 = clkmgr_aon_cg_en.io_div2_peri; |
| prim_mubi_pkg::mubi4_t unused_cg_en_18; |
| assign unused_cg_en_18 = clkmgr_aon_cg_en.audio_peri; |
| prim_mubi_pkg::mubi4_t unused_cg_en_19; |
| assign unused_cg_en_19 = clkmgr_aon_cg_en.smc_peri; |
| prim_mubi_pkg::mubi4_t unused_rst_en_0; |
| assign unused_rst_en_0 = rstmgr_aon_rst_en.por_aon[rstmgr_pkg::DomainAonSel]; |
| prim_mubi_pkg::mubi4_t unused_rst_en_1; |
| assign unused_rst_en_1 = rstmgr_aon_rst_en.por_aon[rstmgr_pkg::Domain0Sel]; |
| prim_mubi_pkg::mubi4_t unused_rst_en_2; |
| assign unused_rst_en_2 = rstmgr_aon_rst_en.por[rstmgr_pkg::DomainAonSel]; |
| prim_mubi_pkg::mubi4_t unused_rst_en_3; |
| assign unused_rst_en_3 = rstmgr_aon_rst_en.por[rstmgr_pkg::Domain0Sel]; |
| prim_mubi_pkg::mubi4_t unused_rst_en_4; |
| assign unused_rst_en_4 = rstmgr_aon_rst_en.por_io[rstmgr_pkg::DomainAonSel]; |
| prim_mubi_pkg::mubi4_t unused_rst_en_5; |
| assign unused_rst_en_5 = rstmgr_aon_rst_en.por_io[rstmgr_pkg::Domain0Sel]; |
| prim_mubi_pkg::mubi4_t unused_rst_en_6; |
| assign unused_rst_en_6 = rstmgr_aon_rst_en.por_io_div2[rstmgr_pkg::DomainAonSel]; |
| prim_mubi_pkg::mubi4_t unused_rst_en_7; |
| assign unused_rst_en_7 = rstmgr_aon_rst_en.por_io_div2[rstmgr_pkg::Domain0Sel]; |
| prim_mubi_pkg::mubi4_t unused_rst_en_8; |
| assign unused_rst_en_8 = rstmgr_aon_rst_en.por_io_div4[rstmgr_pkg::Domain0Sel]; |
| prim_mubi_pkg::mubi4_t unused_rst_en_9; |
| assign unused_rst_en_9 = rstmgr_aon_rst_en.por_usb[rstmgr_pkg::DomainAonSel]; |
| prim_mubi_pkg::mubi4_t unused_rst_en_10; |
| assign unused_rst_en_10 = rstmgr_aon_rst_en.por_usb[rstmgr_pkg::Domain0Sel]; |
| prim_mubi_pkg::mubi4_t unused_rst_en_11; |
| assign unused_rst_en_11 = rstmgr_aon_rst_en.por_smc[rstmgr_pkg::DomainAonSel]; |
| prim_mubi_pkg::mubi4_t unused_rst_en_12; |
| assign unused_rst_en_12 = rstmgr_aon_rst_en.por_smc[rstmgr_pkg::Domain0Sel]; |
| prim_mubi_pkg::mubi4_t unused_rst_en_13; |
| assign unused_rst_en_13 = rstmgr_aon_rst_en.por_ml[rstmgr_pkg::DomainAonSel]; |
| prim_mubi_pkg::mubi4_t unused_rst_en_14; |
| assign unused_rst_en_14 = rstmgr_aon_rst_en.por_ml[rstmgr_pkg::Domain0Sel]; |
| prim_mubi_pkg::mubi4_t unused_rst_en_15; |
| assign unused_rst_en_15 = rstmgr_aon_rst_en.por_video[rstmgr_pkg::DomainAonSel]; |
| prim_mubi_pkg::mubi4_t unused_rst_en_16; |
| assign unused_rst_en_16 = rstmgr_aon_rst_en.por_video[rstmgr_pkg::Domain0Sel]; |
| prim_mubi_pkg::mubi4_t unused_rst_en_17; |
| assign unused_rst_en_17 = rstmgr_aon_rst_en.por_audio[rstmgr_pkg::DomainAonSel]; |
| prim_mubi_pkg::mubi4_t unused_rst_en_18; |
| assign unused_rst_en_18 = rstmgr_aon_rst_en.por_audio[rstmgr_pkg::Domain0Sel]; |
| prim_mubi_pkg::mubi4_t unused_rst_en_19; |
| assign unused_rst_en_19 = rstmgr_aon_rst_en.lc_shadowed[rstmgr_pkg::DomainAonSel]; |
| prim_mubi_pkg::mubi4_t unused_rst_en_20; |
| assign unused_rst_en_20 = rstmgr_aon_rst_en.lc[rstmgr_pkg::DomainAonSel]; |
| prim_mubi_pkg::mubi4_t unused_rst_en_21; |
| assign unused_rst_en_21 = rstmgr_aon_rst_en.lc_shadowed[rstmgr_pkg::Domain0Sel]; |
| prim_mubi_pkg::mubi4_t unused_rst_en_22; |
| assign unused_rst_en_22 = rstmgr_aon_rst_en.lc_aon[rstmgr_pkg::DomainAonSel]; |
| prim_mubi_pkg::mubi4_t unused_rst_en_23; |
| assign unused_rst_en_23 = rstmgr_aon_rst_en.lc_aon[rstmgr_pkg::Domain0Sel]; |
| prim_mubi_pkg::mubi4_t unused_rst_en_24; |
| assign unused_rst_en_24 = rstmgr_aon_rst_en.lc_io[rstmgr_pkg::DomainAonSel]; |
| prim_mubi_pkg::mubi4_t unused_rst_en_25; |
| assign unused_rst_en_25 = rstmgr_aon_rst_en.lc_io[rstmgr_pkg::Domain0Sel]; |
| prim_mubi_pkg::mubi4_t unused_rst_en_26; |
| assign unused_rst_en_26 = rstmgr_aon_rst_en.lc_io_div2[rstmgr_pkg::DomainAonSel]; |
| prim_mubi_pkg::mubi4_t unused_rst_en_27; |
| assign unused_rst_en_27 = rstmgr_aon_rst_en.lc_io_div2[rstmgr_pkg::Domain0Sel]; |
| prim_mubi_pkg::mubi4_t unused_rst_en_28; |
| assign unused_rst_en_28 = rstmgr_aon_rst_en.lc_io_div4_shadowed[rstmgr_pkg::DomainAonSel]; |
| prim_mubi_pkg::mubi4_t unused_rst_en_29; |
| assign unused_rst_en_29 = rstmgr_aon_rst_en.lc_io_div4_shadowed[rstmgr_pkg::Domain0Sel]; |
| prim_mubi_pkg::mubi4_t unused_rst_en_30; |
| assign unused_rst_en_30 = rstmgr_aon_rst_en.lc_usb[rstmgr_pkg::DomainAonSel]; |
| prim_mubi_pkg::mubi4_t unused_rst_en_31; |
| assign unused_rst_en_31 = rstmgr_aon_rst_en.lc_usb[rstmgr_pkg::Domain0Sel]; |
| prim_mubi_pkg::mubi4_t unused_rst_en_32; |
| assign unused_rst_en_32 = rstmgr_aon_rst_en.lc_smc[rstmgr_pkg::DomainAonSel]; |
| prim_mubi_pkg::mubi4_t unused_rst_en_33; |
| assign unused_rst_en_33 = rstmgr_aon_rst_en.lc_smc[rstmgr_pkg::Domain0Sel]; |
| prim_mubi_pkg::mubi4_t unused_rst_en_34; |
| assign unused_rst_en_34 = rstmgr_aon_rst_en.lc_ml[rstmgr_pkg::DomainAonSel]; |
| prim_mubi_pkg::mubi4_t unused_rst_en_35; |
| assign unused_rst_en_35 = rstmgr_aon_rst_en.lc_ml[rstmgr_pkg::Domain0Sel]; |
| prim_mubi_pkg::mubi4_t unused_rst_en_36; |
| assign unused_rst_en_36 = rstmgr_aon_rst_en.lc_video[rstmgr_pkg::DomainAonSel]; |
| prim_mubi_pkg::mubi4_t unused_rst_en_37; |
| assign unused_rst_en_37 = rstmgr_aon_rst_en.lc_video[rstmgr_pkg::Domain0Sel]; |
| prim_mubi_pkg::mubi4_t unused_rst_en_38; |
| assign unused_rst_en_38 = rstmgr_aon_rst_en.lc_audio[rstmgr_pkg::DomainAonSel]; |
| prim_mubi_pkg::mubi4_t unused_rst_en_39; |
| assign unused_rst_en_39 = rstmgr_aon_rst_en.lc_audio[rstmgr_pkg::Domain0Sel]; |
| prim_mubi_pkg::mubi4_t unused_rst_en_40; |
| assign unused_rst_en_40 = rstmgr_aon_rst_en.sys[rstmgr_pkg::DomainAonSel]; |
| prim_mubi_pkg::mubi4_t unused_rst_en_41; |
| assign unused_rst_en_41 = rstmgr_aon_rst_en.sys_io_div4[rstmgr_pkg::DomainAonSel]; |
| prim_mubi_pkg::mubi4_t unused_rst_en_42; |
| assign unused_rst_en_42 = rstmgr_aon_rst_en.spi_device[rstmgr_pkg::DomainAonSel]; |
| prim_mubi_pkg::mubi4_t unused_rst_en_43; |
| assign unused_rst_en_43 = rstmgr_aon_rst_en.spi_host0[rstmgr_pkg::DomainAonSel]; |
| prim_mubi_pkg::mubi4_t unused_rst_en_44; |
| assign unused_rst_en_44 = rstmgr_aon_rst_en.spi_host1[rstmgr_pkg::DomainAonSel]; |
| prim_mubi_pkg::mubi4_t unused_rst_en_45; |
| assign unused_rst_en_45 = rstmgr_aon_rst_en.spi_host2[rstmgr_pkg::DomainAonSel]; |
| prim_mubi_pkg::mubi4_t unused_rst_en_46; |
| assign unused_rst_en_46 = rstmgr_aon_rst_en.usb[rstmgr_pkg::DomainAonSel]; |
| prim_mubi_pkg::mubi4_t unused_rst_en_47; |
| assign unused_rst_en_47 = rstmgr_aon_rst_en.usb_aon[rstmgr_pkg::DomainAonSel]; |
| prim_mubi_pkg::mubi4_t unused_rst_en_48; |
| assign unused_rst_en_48 = rstmgr_aon_rst_en.usb_aon[rstmgr_pkg::Domain0Sel]; |
| prim_mubi_pkg::mubi4_t unused_rst_en_49; |
| assign unused_rst_en_49 = rstmgr_aon_rst_en.i2c0[rstmgr_pkg::DomainAonSel]; |
| prim_mubi_pkg::mubi4_t unused_rst_en_50; |
| assign unused_rst_en_50 = rstmgr_aon_rst_en.i2c1[rstmgr_pkg::DomainAonSel]; |
| prim_mubi_pkg::mubi4_t unused_rst_en_51; |
| assign unused_rst_en_51 = rstmgr_aon_rst_en.i2c2[rstmgr_pkg::DomainAonSel]; |
| prim_mubi_pkg::mubi4_t unused_rst_en_52; |
| assign unused_rst_en_52 = rstmgr_aon_rst_en.smc[rstmgr_pkg::DomainAonSel]; |
| prim_mubi_pkg::mubi4_t unused_rst_en_53; |
| assign unused_rst_en_53 = rstmgr_aon_rst_en.ml[rstmgr_pkg::DomainAonSel]; |
| prim_mubi_pkg::mubi4_t unused_rst_en_54; |
| assign unused_rst_en_54 = rstmgr_aon_rst_en.cam_i2c[rstmgr_pkg::DomainAonSel]; |
| prim_mubi_pkg::mubi4_t unused_rst_en_55; |
| assign unused_rst_en_55 = rstmgr_aon_rst_en.video[rstmgr_pkg::DomainAonSel]; |
| prim_mubi_pkg::mubi4_t unused_rst_en_56; |
| assign unused_rst_en_56 = rstmgr_aon_rst_en.video[rstmgr_pkg::Domain0Sel]; |
| prim_mubi_pkg::mubi4_t unused_rst_en_57; |
| assign unused_rst_en_57 = rstmgr_aon_rst_en.audio[rstmgr_pkg::DomainAonSel]; |
| prim_mubi_pkg::mubi4_t unused_rst_en_58; |
| assign unused_rst_en_58 = rstmgr_aon_rst_en.audio[rstmgr_pkg::Domain0Sel]; |
| //VCS coverage on |
| // pragma coverage on |
| |
| // Peripheral Instantiation |
| |
| uart #( |
| .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[0:0]) |
| ) u_uart0 ( |
| |
| // Input |
| .cio_rx_i (cio_uart0_rx_p2d), |
| |
| // Output |
| .cio_tx_o (cio_uart0_tx_d2p), |
| .cio_tx_en_o (cio_uart0_tx_en_d2p), |
| |
| // Interrupt |
| .intr_tx_watermark_o (intr_uart0_tx_watermark), |
| .intr_rx_watermark_o (intr_uart0_rx_watermark), |
| .intr_tx_empty_o (intr_uart0_tx_empty), |
| .intr_rx_overflow_o (intr_uart0_rx_overflow), |
| .intr_rx_frame_err_o (intr_uart0_rx_frame_err), |
| .intr_rx_break_err_o (intr_uart0_rx_break_err), |
| .intr_rx_timeout_o (intr_uart0_rx_timeout), |
| .intr_rx_parity_err_o (intr_uart0_rx_parity_err), |
| // [0]: fatal_fault |
| .alert_tx_o ( alert_tx[0:0] ), |
| .alert_rx_i ( alert_rx[0:0] ), |
| |
| // Inter-module signals |
| .tl_i(uart0_tl_req), |
| .tl_o(uart0_tl_rsp), |
| |
| // Clock and reset connections |
| .clk_i (clkmgr_aon_clocks.clk_io_div4_peri), |
| .rst_ni (rstmgr_aon_resets.rst_lc_io_div4_n[rstmgr_pkg::Domain0Sel]) |
| ); |
| uart #( |
| .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[1:1]) |
| ) u_uart1 ( |
| |
| // Input |
| .cio_rx_i (cio_uart1_rx_p2d), |
| |
| // Output |
| .cio_tx_o (cio_uart1_tx_d2p), |
| .cio_tx_en_o (cio_uart1_tx_en_d2p), |
| |
| // Interrupt |
| .intr_tx_watermark_o (intr_uart1_tx_watermark), |
| .intr_rx_watermark_o (intr_uart1_rx_watermark), |
| .intr_tx_empty_o (intr_uart1_tx_empty), |
| .intr_rx_overflow_o (intr_uart1_rx_overflow), |
| .intr_rx_frame_err_o (intr_uart1_rx_frame_err), |
| .intr_rx_break_err_o (intr_uart1_rx_break_err), |
| .intr_rx_timeout_o (intr_uart1_rx_timeout), |
| .intr_rx_parity_err_o (intr_uart1_rx_parity_err), |
| // [1]: fatal_fault |
| .alert_tx_o ( alert_tx[1:1] ), |
| .alert_rx_i ( alert_rx[1:1] ), |
| |
| // Inter-module signals |
| .tl_i(uart1_tl_req), |
| .tl_o(uart1_tl_rsp), |
| |
| // Clock and reset connections |
| .clk_i (clkmgr_aon_clocks.clk_io_div4_peri), |
| .rst_ni (rstmgr_aon_resets.rst_lc_io_div4_n[rstmgr_pkg::Domain0Sel]) |
| ); |
| uart #( |
| .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[2:2]) |
| ) u_uart2 ( |
| |
| // Input |
| .cio_rx_i (cio_uart2_rx_p2d), |
| |
| // Output |
| .cio_tx_o (cio_uart2_tx_d2p), |
| .cio_tx_en_o (cio_uart2_tx_en_d2p), |
| |
| // Interrupt |
| .intr_tx_watermark_o (intr_uart2_tx_watermark), |
| .intr_rx_watermark_o (intr_uart2_rx_watermark), |
| .intr_tx_empty_o (intr_uart2_tx_empty), |
| .intr_rx_overflow_o (intr_uart2_rx_overflow), |
| .intr_rx_frame_err_o (intr_uart2_rx_frame_err), |
| .intr_rx_break_err_o (intr_uart2_rx_break_err), |
| .intr_rx_timeout_o (intr_uart2_rx_timeout), |
| .intr_rx_parity_err_o (intr_uart2_rx_parity_err), |
| // [2]: fatal_fault |
| .alert_tx_o ( alert_tx[2:2] ), |
| .alert_rx_i ( alert_rx[2:2] ), |
| |
| // Inter-module signals |
| .tl_i(uart2_tl_req), |
| .tl_o(uart2_tl_rsp), |
| |
| // Clock and reset connections |
| .clk_i (clkmgr_aon_clocks.clk_io_div4_peri), |
| .rst_ni (rstmgr_aon_resets.rst_lc_io_div4_n[rstmgr_pkg::Domain0Sel]) |
| ); |
| uart #( |
| .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[3:3]) |
| ) u_uart3 ( |
| |
| // Input |
| .cio_rx_i (cio_uart3_rx_p2d), |
| |
| // Output |
| .cio_tx_o (cio_uart3_tx_d2p), |
| .cio_tx_en_o (cio_uart3_tx_en_d2p), |
| |
| // Interrupt |
| .intr_tx_watermark_o (intr_uart3_tx_watermark), |
| .intr_rx_watermark_o (intr_uart3_rx_watermark), |
| .intr_tx_empty_o (intr_uart3_tx_empty), |
| .intr_rx_overflow_o (intr_uart3_rx_overflow), |
| .intr_rx_frame_err_o (intr_uart3_rx_frame_err), |
| .intr_rx_break_err_o (intr_uart3_rx_break_err), |
| .intr_rx_timeout_o (intr_uart3_rx_timeout), |
| .intr_rx_parity_err_o (intr_uart3_rx_parity_err), |
| // [3]: fatal_fault |
| .alert_tx_o ( alert_tx[3:3] ), |
| .alert_rx_i ( alert_rx[3:3] ), |
| |
| // Inter-module signals |
| .tl_i(uart3_tl_req), |
| .tl_o(uart3_tl_rsp), |
| |
| // Clock and reset connections |
| .clk_i (clkmgr_aon_clocks.clk_io_div4_peri), |
| .rst_ni (rstmgr_aon_resets.rst_lc_io_div4_n[rstmgr_pkg::Domain0Sel]) |
| ); |
| gpio #( |
| .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[4:4]), |
| .GpioAsyncOn(GpioGpioAsyncOn) |
| ) u_gpio ( |
| |
| // Input |
| .cio_gpio_i (cio_gpio_gpio_p2d), |
| |
| // Output |
| .cio_gpio_o (cio_gpio_gpio_d2p), |
| .cio_gpio_en_o (cio_gpio_gpio_en_d2p), |
| |
| // Interrupt |
| .intr_gpio_o (intr_gpio_gpio), |
| // [4]: fatal_fault |
| .alert_tx_o ( alert_tx[4:4] ), |
| .alert_rx_i ( alert_rx[4:4] ), |
| |
| // Inter-module signals |
| .tl_i(gpio_tl_req), |
| .tl_o(gpio_tl_rsp), |
| |
| // Clock and reset connections |
| .clk_i (clkmgr_aon_clocks.clk_io_div4_peri), |
| .rst_ni (rstmgr_aon_resets.rst_lc_io_div4_n[rstmgr_pkg::Domain0Sel]) |
| ); |
| spi_device #( |
| .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[5:5]) |
| ) u_spi_device ( |
| |
| // Input |
| .cio_sck_i (cio_spi_device_sck_p2d), |
| .cio_csb_i (cio_spi_device_csb_p2d), |
| .cio_tpm_csb_i (cio_spi_device_tpm_csb_p2d), |
| .cio_sd_i (cio_spi_device_sd_p2d), |
| |
| // Output |
| .cio_sd_o (cio_spi_device_sd_d2p), |
| .cio_sd_en_o (cio_spi_device_sd_en_d2p), |
| |
| // Interrupt |
| .intr_generic_rx_full_o (intr_spi_device_generic_rx_full), |
| .intr_generic_rx_watermark_o (intr_spi_device_generic_rx_watermark), |
| .intr_generic_tx_watermark_o (intr_spi_device_generic_tx_watermark), |
| .intr_generic_rx_error_o (intr_spi_device_generic_rx_error), |
| .intr_generic_rx_overflow_o (intr_spi_device_generic_rx_overflow), |
| .intr_generic_tx_underflow_o (intr_spi_device_generic_tx_underflow), |
| .intr_upload_cmdfifo_not_empty_o (intr_spi_device_upload_cmdfifo_not_empty), |
| .intr_upload_payload_not_empty_o (intr_spi_device_upload_payload_not_empty), |
| .intr_upload_payload_overflow_o (intr_spi_device_upload_payload_overflow), |
| .intr_readbuf_watermark_o (intr_spi_device_readbuf_watermark), |
| .intr_readbuf_flip_o (intr_spi_device_readbuf_flip), |
| .intr_tpm_header_not_empty_o (intr_spi_device_tpm_header_not_empty), |
| // [5]: fatal_fault |
| .alert_tx_o ( alert_tx[5:5] ), |
| .alert_rx_i ( alert_rx[5:5] ), |
| |
| // Inter-module signals |
| .ram_cfg_i(ast_ram_2p_cfg), |
| .passthrough_o(spi_device_passthrough_req), |
| .passthrough_i(spi_device_passthrough_rsp), |
| .mbist_en_i('0), |
| .sck_monitor_o(sck_monitor_o), |
| .tl_i(spi_device_tl_req), |
| .tl_o(spi_device_tl_rsp), |
| .scanmode_i, |
| .scan_rst_ni, |
| |
| // Clock and reset connections |
| .clk_i (clkmgr_aon_clocks.clk_io_div4_peri), |
| .scan_clk_i (clkmgr_aon_clocks.clk_io_div2_peri), |
| .rst_ni (rstmgr_aon_resets.rst_spi_device_n[rstmgr_pkg::Domain0Sel]) |
| ); |
| i2c #( |
| .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[6:6]) |
| ) u_i2c0 ( |
| |
| // Input |
| .cio_sda_i (cio_i2c0_sda_p2d), |
| .cio_scl_i (cio_i2c0_scl_p2d), |
| |
| // Output |
| .cio_sda_o (cio_i2c0_sda_d2p), |
| .cio_sda_en_o (cio_i2c0_sda_en_d2p), |
| .cio_scl_o (cio_i2c0_scl_d2p), |
| .cio_scl_en_o (cio_i2c0_scl_en_d2p), |
| |
| // Interrupt |
| .intr_fmt_threshold_o (intr_i2c0_fmt_threshold), |
| .intr_rx_threshold_o (intr_i2c0_rx_threshold), |
| .intr_fmt_overflow_o (intr_i2c0_fmt_overflow), |
| .intr_rx_overflow_o (intr_i2c0_rx_overflow), |
| .intr_nak_o (intr_i2c0_nak), |
| .intr_scl_interference_o (intr_i2c0_scl_interference), |
| .intr_sda_interference_o (intr_i2c0_sda_interference), |
| .intr_stretch_timeout_o (intr_i2c0_stretch_timeout), |
| .intr_sda_unstable_o (intr_i2c0_sda_unstable), |
| .intr_cmd_complete_o (intr_i2c0_cmd_complete), |
| .intr_tx_stretch_o (intr_i2c0_tx_stretch), |
| .intr_tx_overflow_o (intr_i2c0_tx_overflow), |
| .intr_acq_full_o (intr_i2c0_acq_full), |
| .intr_unexp_stop_o (intr_i2c0_unexp_stop), |
| .intr_host_timeout_o (intr_i2c0_host_timeout), |
| // [6]: fatal_fault |
| .alert_tx_o ( alert_tx[6:6] ), |
| .alert_rx_i ( alert_rx[6:6] ), |
| |
| // Inter-module signals |
| .tl_i(i2c0_tl_req), |
| .tl_o(i2c0_tl_rsp), |
| |
| // Clock and reset connections |
| .clk_i (clkmgr_aon_clocks.clk_io_div4_peri), |
| .rst_ni (rstmgr_aon_resets.rst_i2c0_n[rstmgr_pkg::Domain0Sel]) |
| ); |
| i2c #( |
| .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[7:7]) |
| ) u_i2c1 ( |
| |
| // Input |
| .cio_sda_i (cio_i2c1_sda_p2d), |
| .cio_scl_i (cio_i2c1_scl_p2d), |
| |
| // Output |
| .cio_sda_o (cio_i2c1_sda_d2p), |
| .cio_sda_en_o (cio_i2c1_sda_en_d2p), |
| .cio_scl_o (cio_i2c1_scl_d2p), |
| .cio_scl_en_o (cio_i2c1_scl_en_d2p), |
| |
| // Interrupt |
| .intr_fmt_threshold_o (intr_i2c1_fmt_threshold), |
| .intr_rx_threshold_o (intr_i2c1_rx_threshold), |
| .intr_fmt_overflow_o (intr_i2c1_fmt_overflow), |
| .intr_rx_overflow_o (intr_i2c1_rx_overflow), |
| .intr_nak_o (intr_i2c1_nak), |
| .intr_scl_interference_o (intr_i2c1_scl_interference), |
| .intr_sda_interference_o (intr_i2c1_sda_interference), |
| .intr_stretch_timeout_o (intr_i2c1_stretch_timeout), |
| .intr_sda_unstable_o (intr_i2c1_sda_unstable), |
| .intr_cmd_complete_o (intr_i2c1_cmd_complete), |
| .intr_tx_stretch_o (intr_i2c1_tx_stretch), |
| .intr_tx_overflow_o (intr_i2c1_tx_overflow), |
| .intr_acq_full_o (intr_i2c1_acq_full), |
| .intr_unexp_stop_o (intr_i2c1_unexp_stop), |
| .intr_host_timeout_o (intr_i2c1_host_timeout), |
| // [7]: fatal_fault |
| .alert_tx_o ( alert_tx[7:7] ), |
| .alert_rx_i ( alert_rx[7:7] ), |
| |
| // Inter-module signals |
| .tl_i(i2c1_tl_req), |
| .tl_o(i2c1_tl_rsp), |
| |
| // Clock and reset connections |
| .clk_i (clkmgr_aon_clocks.clk_io_div4_peri), |
| .rst_ni (rstmgr_aon_resets.rst_i2c1_n[rstmgr_pkg::Domain0Sel]) |
| ); |
| i2c #( |
| .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[8:8]) |
| ) u_i2c2 ( |
| |
| // Input |
| .cio_sda_i (cio_i2c2_sda_p2d), |
| .cio_scl_i (cio_i2c2_scl_p2d), |
| |
| // Output |
| .cio_sda_o (cio_i2c2_sda_d2p), |
| .cio_sda_en_o (cio_i2c2_sda_en_d2p), |
| .cio_scl_o (cio_i2c2_scl_d2p), |
| .cio_scl_en_o (cio_i2c2_scl_en_d2p), |
| |
| // Interrupt |
| .intr_fmt_threshold_o (intr_i2c2_fmt_threshold), |
| .intr_rx_threshold_o (intr_i2c2_rx_threshold), |
| .intr_fmt_overflow_o (intr_i2c2_fmt_overflow), |
| .intr_rx_overflow_o (intr_i2c2_rx_overflow), |
| .intr_nak_o (intr_i2c2_nak), |
| .intr_scl_interference_o (intr_i2c2_scl_interference), |
| .intr_sda_interference_o (intr_i2c2_sda_interference), |
| .intr_stretch_timeout_o (intr_i2c2_stretch_timeout), |
| .intr_sda_unstable_o (intr_i2c2_sda_unstable), |
| .intr_cmd_complete_o (intr_i2c2_cmd_complete), |
| .intr_tx_stretch_o (intr_i2c2_tx_stretch), |
| .intr_tx_overflow_o (intr_i2c2_tx_overflow), |
| .intr_acq_full_o (intr_i2c2_acq_full), |
| .intr_unexp_stop_o (intr_i2c2_unexp_stop), |
| .intr_host_timeout_o (intr_i2c2_host_timeout), |
| // [8]: fatal_fault |
| .alert_tx_o ( alert_tx[8:8] ), |
| .alert_rx_i ( alert_rx[8:8] ), |
| |
| // Inter-module signals |
| .tl_i(i2c2_tl_req), |
| .tl_o(i2c2_tl_rsp), |
| |
| // Clock and reset connections |
| .clk_i (clkmgr_aon_clocks.clk_io_div4_peri), |
| .rst_ni (rstmgr_aon_resets.rst_i2c2_n[rstmgr_pkg::Domain0Sel]) |
| ); |
| pattgen #( |
| .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[9:9]) |
| ) u_pattgen ( |
| |
| // Output |
| .cio_pda0_tx_o (cio_pattgen_pda0_tx_d2p), |
| .cio_pda0_tx_en_o (cio_pattgen_pda0_tx_en_d2p), |
| .cio_pcl0_tx_o (cio_pattgen_pcl0_tx_d2p), |
| .cio_pcl0_tx_en_o (cio_pattgen_pcl0_tx_en_d2p), |
| .cio_pda1_tx_o (cio_pattgen_pda1_tx_d2p), |
| .cio_pda1_tx_en_o (cio_pattgen_pda1_tx_en_d2p), |
| .cio_pcl1_tx_o (cio_pattgen_pcl1_tx_d2p), |
| .cio_pcl1_tx_en_o (cio_pattgen_pcl1_tx_en_d2p), |
| |
| // Interrupt |
| .intr_done_ch0_o (intr_pattgen_done_ch0), |
| .intr_done_ch1_o (intr_pattgen_done_ch1), |
| // [9]: fatal_fault |
| .alert_tx_o ( alert_tx[9:9] ), |
| .alert_rx_i ( alert_rx[9:9] ), |
| |
| // Inter-module signals |
| .tl_i(pattgen_tl_req), |
| .tl_o(pattgen_tl_rsp), |
| |
| // Clock and reset connections |
| .clk_i (clkmgr_aon_clocks.clk_io_div4_peri), |
| .rst_ni (rstmgr_aon_resets.rst_lc_io_div4_n[rstmgr_pkg::Domain0Sel]) |
| ); |
| rv_timer #( |
| .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[10:10]) |
| ) u_rv_timer ( |
| |
| // Interrupt |
| .intr_timer_expired_hart0_timer0_o (intr_rv_timer_timer_expired_hart0_timer0), |
| // [10]: fatal_fault |
| .alert_tx_o ( alert_tx[10:10] ), |
| .alert_rx_i ( alert_rx[10:10] ), |
| |
| // Inter-module signals |
| .tl_i(rv_timer_tl_req), |
| .tl_o(rv_timer_tl_rsp), |
| |
| // Clock and reset connections |
| .clk_i (clkmgr_aon_clocks.clk_io_div4_timers), |
| .rst_ni (rstmgr_aon_resets.rst_lc_io_div4_n[rstmgr_pkg::Domain0Sel]) |
| ); |
| otp_ctrl #( |
| .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[15:11]), |
| .MemInitFile(OtpCtrlMemInitFile), |
| .RndCnstLfsrSeed(RndCnstOtpCtrlLfsrSeed), |
| .RndCnstLfsrPerm(RndCnstOtpCtrlLfsrPerm), |
| .RndCnstScrmblKeyInit(RndCnstOtpCtrlScrmblKeyInit) |
| ) u_otp_ctrl ( |
| |
| // Output |
| .cio_test_o (cio_otp_ctrl_test_d2p), |
| .cio_test_en_o (cio_otp_ctrl_test_en_d2p), |
| |
| // Interrupt |
| .intr_otp_operation_done_o (intr_otp_ctrl_otp_operation_done), |
| .intr_otp_error_o (intr_otp_ctrl_otp_error), |
| // [11]: fatal_macro_error |
| // [12]: fatal_check_error |
| // [13]: fatal_bus_integ_error |
| // [14]: fatal_prim_otp_alert |
| // [15]: recov_prim_otp_alert |
| .alert_tx_o ( alert_tx[15:11] ), |
| .alert_rx_i ( alert_rx[15:11] ), |
| |
| // Inter-module signals |
| .otp_ext_voltage_h_io(otp_ext_voltage_h_io), |
| .otp_ast_pwr_seq_o(otp_ctrl_otp_ast_pwr_seq_o), |
| .otp_ast_pwr_seq_h_i(otp_ctrl_otp_ast_pwr_seq_h_i), |
| .edn_o(edn0_edn_req[1]), |
| .edn_i(edn0_edn_rsp[1]), |
| .pwr_otp_i(pwrmgr_aon_pwr_otp_req), |
| .pwr_otp_o(pwrmgr_aon_pwr_otp_rsp), |
| .lc_otp_vendor_test_i(lc_ctrl_lc_otp_vendor_test_req), |
| .lc_otp_vendor_test_o(lc_ctrl_lc_otp_vendor_test_rsp), |
| .lc_otp_program_i(lc_ctrl_lc_otp_program_req), |
| .lc_otp_program_o(lc_ctrl_lc_otp_program_rsp), |
| .otp_lc_data_o(otp_ctrl_otp_lc_data), |
| .lc_escalate_en_i(lc_ctrl_lc_escalate_en), |
| .lc_creator_seed_sw_rw_en_i(lc_ctrl_lc_creator_seed_sw_rw_en), |
| .lc_seed_hw_rd_en_i(lc_ctrl_lc_seed_hw_rd_en), |
| .lc_dft_en_i(lc_ctrl_lc_dft_en), |
| .lc_check_byp_en_i(lc_ctrl_lc_check_byp_en), |
| .otp_keymgr_key_o(otp_ctrl_otp_keymgr_key), |
| .flash_otp_key_i(flash_ctrl_otp_req), |
| .flash_otp_key_o(flash_ctrl_otp_rsp), |
| .sram_otp_key_i(otp_ctrl_sram_otp_key_req), |
| .sram_otp_key_o(otp_ctrl_sram_otp_key_rsp), |
| .otbn_otp_key_i(otp_ctrl_otbn_otp_key_req), |
| .otbn_otp_key_o(otp_ctrl_otbn_otp_key_rsp), |
| .otp_hw_cfg_o(otp_ctrl_otp_hw_cfg), |
| .obs_ctrl_i(ast_obs_ctrl), |
| .otp_obs_o(otp_obs_o), |
| .core_tl_i(otp_ctrl_core_tl_req), |
| .core_tl_o(otp_ctrl_core_tl_rsp), |
| .prim_tl_i(otp_ctrl_prim_tl_req), |
| .prim_tl_o(otp_ctrl_prim_tl_rsp), |
| .scanmode_i, |
| .scan_rst_ni, |
| .scan_en_i, |
| |
| // Clock and reset connections |
| .clk_i (clkmgr_aon_clocks.clk_io_div4_secure), |
| .clk_edn_i (clkmgr_aon_clocks.clk_main_secure), |
| .rst_ni (rstmgr_aon_resets.rst_lc_io_div4_n[rstmgr_pkg::Domain0Sel]), |
| .rst_edn_ni (rstmgr_aon_resets.rst_lc_n[rstmgr_pkg::Domain0Sel]) |
| ); |
| lc_ctrl #( |
| .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[18:16]), |
| .RndCnstLcKeymgrDivInvalid(RndCnstLcCtrlLcKeymgrDivInvalid), |
| .RndCnstLcKeymgrDivTestDevRma(RndCnstLcCtrlLcKeymgrDivTestDevRma), |
| .RndCnstLcKeymgrDivProduction(RndCnstLcCtrlLcKeymgrDivProduction), |
| .RndCnstInvalidTokens(RndCnstLcCtrlInvalidTokens), |
| .ChipGen(LcCtrlChipGen), |
| .ChipRev(LcCtrlChipRev), |
| .IdcodeValue(LcCtrlIdcodeValue) |
| ) u_lc_ctrl ( |
| // [16]: fatal_prog_error |
| // [17]: fatal_state_error |
| // [18]: fatal_bus_integ_error |
| .alert_tx_o ( alert_tx[18:16] ), |
| .alert_rx_i ( alert_rx[18:16] ), |
| |
| // Inter-module signals |
| .jtag_i(pinmux_aon_lc_jtag_req), |
| .jtag_o(pinmux_aon_lc_jtag_rsp), |
| .esc_scrap_state0_tx_i(alert_handler_esc_tx[1]), |
| .esc_scrap_state0_rx_o(alert_handler_esc_rx[1]), |
| .esc_scrap_state1_tx_i(alert_handler_esc_tx[2]), |
| .esc_scrap_state1_rx_o(alert_handler_esc_rx[2]), |
| .pwr_lc_i(pwrmgr_aon_pwr_lc_req), |
| .pwr_lc_o(pwrmgr_aon_pwr_lc_rsp), |
| .lc_otp_vendor_test_o(lc_ctrl_lc_otp_vendor_test_req), |
| .lc_otp_vendor_test_i(lc_ctrl_lc_otp_vendor_test_rsp), |
| .otp_lc_data_i(otp_ctrl_otp_lc_data), |
| .lc_otp_program_o(lc_ctrl_lc_otp_program_req), |
| .lc_otp_program_i(lc_ctrl_lc_otp_program_rsp), |
| .kmac_data_o(kmac_app_req[1]), |
| .kmac_data_i(kmac_app_rsp[1]), |
| .lc_dft_en_o(lc_ctrl_lc_dft_en), |
| .lc_nvm_debug_en_o(lc_ctrl_lc_nvm_debug_en), |
| .lc_hw_debug_en_o(lc_ctrl_lc_hw_debug_en), |
| .lc_cpu_en_o(lc_ctrl_lc_cpu_en), |
| .lc_keymgr_en_o(lc_ctrl_lc_keymgr_en), |
| .lc_escalate_en_o(lc_ctrl_lc_escalate_en), |
| .lc_clk_byp_req_o(lc_ctrl_lc_clk_byp_req), |
| .lc_clk_byp_ack_i(lc_ctrl_lc_clk_byp_ack), |
| .lc_flash_rma_req_o(lc_ctrl_lc_flash_rma_req), |
| .lc_flash_rma_seed_o(flash_ctrl_rma_seed), |
| .lc_flash_rma_ack_i(otbn_lc_rma_ack), |
| .lc_check_byp_en_o(lc_ctrl_lc_check_byp_en), |
| .lc_creator_seed_sw_rw_en_o(lc_ctrl_lc_creator_seed_sw_rw_en), |
| .lc_owner_seed_sw_rw_en_o(lc_ctrl_lc_owner_seed_sw_rw_en), |
| .lc_iso_part_sw_rd_en_o(lc_ctrl_lc_iso_part_sw_rd_en), |
| .lc_iso_part_sw_wr_en_o(lc_ctrl_lc_iso_part_sw_wr_en), |
| .lc_seed_hw_rd_en_o(lc_ctrl_lc_seed_hw_rd_en), |
| .lc_keymgr_div_o(lc_ctrl_lc_keymgr_div), |
| .otp_device_id_i(lc_ctrl_otp_device_id), |
| .otp_manuf_state_i(lc_ctrl_otp_manuf_state), |
| .hw_rev_o(), |
| .tl_i(lc_ctrl_tl_req), |
| .tl_o(lc_ctrl_tl_rsp), |
| .scanmode_i, |
| .scan_rst_ni, |
| |
| // Clock and reset connections |
| .clk_i (clkmgr_aon_clocks.clk_io_div4_secure), |
| .clk_kmac_i (clkmgr_aon_clocks.clk_main_secure), |
| .rst_ni (rstmgr_aon_resets.rst_lc_io_div4_n[rstmgr_pkg::Domain0Sel]), |
| .rst_kmac_ni (rstmgr_aon_resets.rst_lc_n[rstmgr_pkg::Domain0Sel]) |
| ); |
| alert_handler #( |
| .RndCnstLfsrSeed(RndCnstAlertHandlerLfsrSeed), |
| .RndCnstLfsrPerm(RndCnstAlertHandlerLfsrPerm) |
| ) u_alert_handler ( |
| |
| // Interrupt |
| .intr_classa_o (intr_alert_handler_classa), |
| .intr_classb_o (intr_alert_handler_classb), |
| .intr_classc_o (intr_alert_handler_classc), |
| .intr_classd_o (intr_alert_handler_classd), |
| |
| // Inter-module signals |
| .crashdump_o(alert_handler_crashdump), |
| .edn_o(edn0_edn_req[4]), |
| .edn_i(edn0_edn_rsp[4]), |
| .esc_rx_i(alert_handler_esc_rx), |
| .esc_tx_o(alert_handler_esc_tx), |
| .tl_i(alert_handler_tl_req), |
| .tl_o(alert_handler_tl_rsp), |
| // alert signals |
| .alert_rx_o ( alert_rx ), |
| .alert_tx_i ( alert_tx ), |
| // synchronized clock gated / reset asserted |
| // indications for each alert |
| .lpg_cg_en_i ( lpg_cg_en ), |
| .lpg_rst_en_i ( lpg_rst_en ), |
| |
| // Clock and reset connections |
| .clk_i (clkmgr_aon_clocks.clk_io_div4_secure), |
| .clk_edn_i (clkmgr_aon_clocks.clk_main_secure), |
| .rst_shadowed_ni (rstmgr_aon_resets.rst_lc_io_div4_shadowed_n[rstmgr_pkg::Domain0Sel]), |
| .rst_ni (rstmgr_aon_resets.rst_lc_io_div4_n[rstmgr_pkg::Domain0Sel]), |
| .rst_edn_ni (rstmgr_aon_resets.rst_lc_n[rstmgr_pkg::Domain0Sel]) |
| ); |
| spi_host #( |
| .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[19:19]) |
| ) u_spi_host0 ( |
| |
| // Input |
| .cio_sd_i (cio_spi_host0_sd_p2d), |
| |
| // Output |
| .cio_sck_o (cio_spi_host0_sck_d2p), |
| .cio_sck_en_o (cio_spi_host0_sck_en_d2p), |
| .cio_csb_o (cio_spi_host0_csb_d2p), |
| .cio_csb_en_o (cio_spi_host0_csb_en_d2p), |
| .cio_sd_o (cio_spi_host0_sd_d2p), |
| .cio_sd_en_o (cio_spi_host0_sd_en_d2p), |
| |
| // Interrupt |
| .intr_error_o (intr_spi_host0_error), |
| .intr_spi_event_o (intr_spi_host0_spi_event), |
| // [19]: fatal_fault |
| .alert_tx_o ( alert_tx[19:19] ), |
| .alert_rx_i ( alert_rx[19:19] ), |
| |
| // Inter-module signals |
| .passthrough_i(spi_device_passthrough_req), |
| .passthrough_o(spi_device_passthrough_rsp), |
| .tl_i(spi_host0_tl_req), |
| .tl_o(spi_host0_tl_rsp), |
| |
| // Clock and reset connections |
| .clk_i (clkmgr_aon_clocks.clk_io_peri), |
| .rst_ni (rstmgr_aon_resets.rst_spi_host0_n[rstmgr_pkg::Domain0Sel]) |
| ); |
| spi_host #( |
| .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[20:20]) |
| ) u_spi_host1 ( |
| |
| // Input |
| .cio_sd_i (cio_spi_host1_sd_p2d), |
| |
| // Output |
| .cio_sck_o (cio_spi_host1_sck_d2p), |
| .cio_sck_en_o (cio_spi_host1_sck_en_d2p), |
| .cio_csb_o (cio_spi_host1_csb_d2p), |
| .cio_csb_en_o (cio_spi_host1_csb_en_d2p), |
| .cio_sd_o (cio_spi_host1_sd_d2p), |
| .cio_sd_en_o (cio_spi_host1_sd_en_d2p), |
| |
| // Interrupt |
| .intr_error_o (intr_spi_host1_error), |
| .intr_spi_event_o (intr_spi_host1_spi_event), |
| // [20]: fatal_fault |
| .alert_tx_o ( alert_tx[20:20] ), |
| .alert_rx_i ( alert_rx[20:20] ), |
| |
| // Inter-module signals |
| .passthrough_i(spi_device_pkg::PASSTHROUGH_REQ_DEFAULT), |
| .passthrough_o(), |
| .tl_i(spi_host1_tl_req), |
| .tl_o(spi_host1_tl_rsp), |
| |
| // Clock and reset connections |
| .clk_i (clkmgr_aon_clocks.clk_io_peri), |
| .rst_ni (rstmgr_aon_resets.rst_spi_host1_n[rstmgr_pkg::Domain0Sel]) |
| ); |
| usbdev #( |
| .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[21:21]), |
| .Stub(UsbdevStub), |
| .RcvrWakeTimeUs(UsbdevRcvrWakeTimeUs) |
| ) u_usbdev ( |
| |
| // Input |
| .cio_sense_i (cio_usbdev_sense_p2d), |
| .cio_usb_dp_i (cio_usbdev_usb_dp_p2d), |
| .cio_usb_dn_i (cio_usbdev_usb_dn_p2d), |
| |
| // Output |
| .cio_usb_dp_o (cio_usbdev_usb_dp_d2p), |
| .cio_usb_dp_en_o (cio_usbdev_usb_dp_en_d2p), |
| .cio_usb_dn_o (cio_usbdev_usb_dn_d2p), |
| .cio_usb_dn_en_o (cio_usbdev_usb_dn_en_d2p), |
| |
| // Interrupt |
| .intr_pkt_received_o (intr_usbdev_pkt_received), |
| .intr_pkt_sent_o (intr_usbdev_pkt_sent), |
| .intr_disconnected_o (intr_usbdev_disconnected), |
| .intr_host_lost_o (intr_usbdev_host_lost), |
| .intr_link_reset_o (intr_usbdev_link_reset), |
| .intr_link_suspend_o (intr_usbdev_link_suspend), |
| .intr_link_resume_o (intr_usbdev_link_resume), |
| .intr_av_empty_o (intr_usbdev_av_empty), |
| .intr_rx_full_o (intr_usbdev_rx_full), |
| .intr_av_overflow_o (intr_usbdev_av_overflow), |
| .intr_link_in_err_o (intr_usbdev_link_in_err), |
| .intr_rx_crc_err_o (intr_usbdev_rx_crc_err), |
| .intr_rx_pid_err_o (intr_usbdev_rx_pid_err), |
| .intr_rx_bitstuff_err_o (intr_usbdev_rx_bitstuff_err), |
| .intr_frame_o (intr_usbdev_frame), |
| .intr_powered_o (intr_usbdev_powered), |
| .intr_link_out_err_o (intr_usbdev_link_out_err), |
| // [21]: fatal_fault |
| .alert_tx_o ( alert_tx[21:21] ), |
| .alert_rx_i ( alert_rx[21:21] ), |
| |
| // Inter-module signals |
| .usb_rx_d_i(usbdev_usb_rx_d_i), |
| .usb_tx_d_o(usbdev_usb_tx_d_o), |
| .usb_tx_se0_o(usbdev_usb_tx_se0_o), |
| .usb_tx_use_d_se0_o(usbdev_usb_tx_use_d_se0_o), |
| .usb_dp_pullup_o(usbdev_usb_dp_pullup), |
| .usb_dn_pullup_o(usbdev_usb_dn_pullup), |
| .usb_rx_enable_o(usbdev_usb_rx_enable_o), |
| .usb_ref_val_o(usbdev_usb_ref_val_o), |
| .usb_ref_pulse_o(usbdev_usb_ref_pulse_o), |
| .usb_aon_suspend_req_o(usbdev_usb_aon_suspend_req), |
| .usb_aon_wake_ack_o(usbdev_usb_aon_wake_ack), |
| .usb_aon_bus_reset_i(usbdev_usb_aon_bus_reset), |
| .usb_aon_sense_lost_i(usbdev_usb_aon_sense_lost), |
| .usb_aon_wake_detect_active_i(pinmux_aon_usbdev_wake_detect_active), |
| .ram_cfg_i(ast_ram_2p_cfg), |
| .tl_i(usbdev_tl_req), |
| .tl_o(usbdev_tl_rsp), |
| |
| // Clock and reset connections |
| .clk_i (clkmgr_aon_clocks.clk_usb_peri), |
| .clk_aon_i (clkmgr_aon_clocks.clk_aon_peri), |
| .rst_ni (rstmgr_aon_resets.rst_usb_n[rstmgr_pkg::Domain0Sel]), |
| .rst_aon_ni (rstmgr_aon_resets.rst_usb_aon_n[rstmgr_pkg::Domain0Sel]) |
| ); |
| pwrmgr #( |
| .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[22:22]) |
| ) u_pwrmgr_aon ( |
| |
| // Interrupt |
| .intr_wakeup_o (intr_pwrmgr_aon_wakeup), |
| // [22]: fatal_fault |
| .alert_tx_o ( alert_tx[22:22] ), |
| .alert_rx_i ( alert_rx[22:22] ), |
| |
| // Inter-module signals |
| .pwr_ast_o(pwrmgr_ast_req_o), |
| .pwr_ast_i(pwrmgr_ast_rsp_i), |
| .pwr_rst_o(pwrmgr_aon_pwr_rst_req), |
| .pwr_rst_i(pwrmgr_aon_pwr_rst_rsp), |
| .pwr_clk_o(pwrmgr_aon_pwr_clk_req), |
| .pwr_clk_i(pwrmgr_aon_pwr_clk_rsp), |
| .pwr_otp_o(pwrmgr_aon_pwr_otp_req), |
| .pwr_otp_i(pwrmgr_aon_pwr_otp_rsp), |
| .pwr_lc_o(pwrmgr_aon_pwr_lc_req), |
| .pwr_lc_i(pwrmgr_aon_pwr_lc_rsp), |
| .pwr_flash_i(pwrmgr_aon_pwr_flash), |
| .esc_rst_tx_i(alert_handler_esc_tx[3]), |
| .esc_rst_rx_o(alert_handler_esc_rx[3]), |
| .pwr_cpu_i(rv_core_ibex_sec_pwrmgr), |
| .wakeups_i(pwrmgr_aon_wakeups), |
| .rstreqs_i(pwrmgr_aon_rstreqs), |
| .ndmreset_req_i(rv_dm_ndmreset_req), |
| .strap_o(pwrmgr_aon_strap), |
| .low_power_o(pwrmgr_aon_low_power), |
| .rom_ctrl_i(rom_ctrl_pwrmgr_data), |
| .fetch_en_o(pwrmgr_aon_fetch_en), |
| .lc_dft_en_i(lc_ctrl_lc_dft_en), |
| .lc_hw_debug_en_i(lc_ctrl_lc_hw_debug_en), |
| .sw_rst_req_i(rstmgr_aon_sw_rst_req), |
| .tl_i(pwrmgr_aon_tl_req), |
| .tl_o(pwrmgr_aon_tl_rsp), |
| |
| // Clock and reset connections |
| .clk_i (clkmgr_aon_clocks.clk_io_div4_powerup), |
| .clk_slow_i (clkmgr_aon_clocks.clk_aon_powerup), |
| .clk_lc_i (clkmgr_aon_clocks.clk_io_div4_powerup), |
| .clk_esc_i (clkmgr_aon_clocks.clk_io_div4_secure), |
| .rst_ni (rstmgr_aon_resets.rst_por_io_div4_n[rstmgr_pkg::DomainAonSel]), |
| .rst_main_ni (rstmgr_aon_resets.rst_por_aon_n[rstmgr_pkg::Domain0Sel]), |
| .rst_lc_ni (rstmgr_aon_resets.rst_lc_io_div4_n[rstmgr_pkg::DomainAonSel]), |
| .rst_esc_ni (rstmgr_aon_resets.rst_lc_io_div4_n[rstmgr_pkg::DomainAonSel]), |
| .rst_slow_ni (rstmgr_aon_resets.rst_por_aon_n[rstmgr_pkg::DomainAonSel]) |
| ); |
| rstmgr #( |
| .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[24:23]), |
| .SecCheck(SecRstmgrAonCheck), |
| .SecMaxSyncDelay(SecRstmgrAonMaxSyncDelay) |
| ) u_rstmgr_aon ( |
| // [23]: fatal_fault |
| // [24]: fatal_cnsty_fault |
| .alert_tx_o ( alert_tx[24:23] ), |
| .alert_rx_i ( alert_rx[24:23] ), |
| |
| // Inter-module signals |
| .por_n_i(por_n_i), |
| .pwr_i(pwrmgr_aon_pwr_rst_req), |
| .pwr_o(pwrmgr_aon_pwr_rst_rsp), |
| .resets_o(rstmgr_aon_resets), |
| .rst_en_o(rstmgr_aon_rst_en), |
| .alert_dump_i(alert_handler_crashdump), |
| .cpu_dump_i(rv_core_ibex_sec_crash_dump), |
| .sw_rst_req_o(rstmgr_aon_sw_rst_req), |
| .tl_i(rstmgr_aon_tl_req), |
| .tl_o(rstmgr_aon_tl_rsp), |
| .scanmode_i, |
| .scan_rst_ni, |
| |
| // Clock and reset connections |
| .clk_i (clkmgr_aon_clocks.clk_io_div4_powerup), |
| .clk_por_i (clkmgr_aon_clocks.clk_io_div4_powerup), |
| .clk_aon_i (clkmgr_aon_clocks.clk_aon_powerup), |
| .clk_main_i (clkmgr_aon_clocks.clk_main_powerup), |
| .clk_io_i (clkmgr_aon_clocks.clk_io_powerup), |
| .clk_usb_i (clkmgr_aon_clocks.clk_usb_powerup), |
| .clk_io_div2_i (clkmgr_aon_clocks.clk_io_div2_powerup), |
| .clk_io_div4_i (clkmgr_aon_clocks.clk_io_div4_powerup), |
| .clk_smc_i (clkmgr_aon_clocks.clk_smc_powerup), |
| .clk_ml_i (clkmgr_aon_clocks.clk_ml_powerup), |
| .clk_video_i (clkmgr_aon_clocks.clk_video_powerup), |
| .clk_audio_i (clkmgr_aon_clocks.clk_audio_powerup), |
| .rst_ni (rstmgr_aon_resets.rst_lc_io_div4_n[rstmgr_pkg::DomainAonSel]), |
| .rst_por_ni (rstmgr_aon_resets.rst_por_io_div4_n[rstmgr_pkg::DomainAonSel]) |
| ); |
| clkmgr #( |
| .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[26:25]) |
| ) u_clkmgr_aon ( |
| // [25]: recov_fault |
| // [26]: fatal_fault |
| .alert_tx_o ( alert_tx[26:25] ), |
| .alert_rx_i ( alert_rx[26:25] ), |
| |
| // Inter-module signals |
| .clocks_o(clkmgr_aon_clocks), |
| .cg_en_o(clkmgr_aon_cg_en), |
| .lc_hw_debug_en_i(lc_ctrl_lc_hw_debug_en), |
| .io_clk_byp_req_o(io_clk_byp_req_o), |
| .io_clk_byp_ack_i(io_clk_byp_ack_i), |
| .all_clk_byp_req_o(all_clk_byp_req_o), |
| .all_clk_byp_ack_i(all_clk_byp_ack_i), |
| .hi_speed_sel_o(hi_speed_sel_o), |
| .div_step_down_req_i(div_step_down_req_i), |
| .lc_clk_byp_req_i(lc_ctrl_lc_clk_byp_req), |
| .lc_clk_byp_ack_o(lc_ctrl_lc_clk_byp_ack), |
| .jitter_en_o(clk_main_jitter_en_o), |
| .pwr_i(pwrmgr_aon_pwr_clk_req), |
| .pwr_o(pwrmgr_aon_pwr_clk_rsp), |
| .idle_i(clkmgr_aon_idle), |
| .calib_rdy_i(calib_rdy_i), |
| .tl_i(clkmgr_aon_tl_req), |
| .tl_o(clkmgr_aon_tl_rsp), |
| .scanmode_i, |
| |
| // Clock and reset connections |
| .clk_i (clkmgr_aon_clocks.clk_io_div4_powerup), |
| .clk_main_i (clk_main_i), |
| .clk_io_i (clk_io_i), |
| .clk_usb_i (clk_usb_i), |
| .clk_aon_i (clk_aon_i), |
| .clk_ml_i (clk_ml_i), |
| .clk_smc_i (clk_smc_i), |
| .clk_video_i (clk_video_i), |
| .clk_audio_i (clk_audio_i), |
| .rst_shadowed_ni (rstmgr_aon_resets.rst_lc_io_div4_shadowed_n[rstmgr_pkg::DomainAonSel]), |
| .rst_ni (rstmgr_aon_resets.rst_lc_io_div4_n[rstmgr_pkg::DomainAonSel]), |
| .rst_aon_ni (rstmgr_aon_resets.rst_lc_aon_n[rstmgr_pkg::DomainAonSel]), |
| .rst_io_ni (rstmgr_aon_resets.rst_lc_io_n[rstmgr_pkg::DomainAonSel]), |
| .rst_io_div2_ni (rstmgr_aon_resets.rst_lc_io_div2_n[rstmgr_pkg::DomainAonSel]), |
| .rst_io_div4_ni (rstmgr_aon_resets.rst_lc_io_div4_n[rstmgr_pkg::DomainAonSel]), |
| .rst_main_ni (rstmgr_aon_resets.rst_lc_n[rstmgr_pkg::DomainAonSel]), |
| .rst_usb_ni (rstmgr_aon_resets.rst_lc_usb_n[rstmgr_pkg::DomainAonSel]), |
| .rst_smc_ni (rstmgr_aon_resets.rst_lc_smc_n[rstmgr_pkg::DomainAonSel]), |
| .rst_ml_ni (rstmgr_aon_resets.rst_lc_ml_n[rstmgr_pkg::DomainAonSel]), |
| .rst_video_ni (rstmgr_aon_resets.rst_lc_video_n[rstmgr_pkg::DomainAonSel]), |
| .rst_audio_ni (rstmgr_aon_resets.rst_lc_audio_n[rstmgr_pkg::DomainAonSel]), |
| .rst_root_ni (rstmgr_aon_resets.rst_por_io_div4_n[rstmgr_pkg::DomainAonSel]), |
| .rst_root_io_ni (rstmgr_aon_resets.rst_por_io_n[rstmgr_pkg::DomainAonSel]), |
| .rst_root_io_div2_ni (rstmgr_aon_resets.rst_por_io_div2_n[rstmgr_pkg::DomainAonSel]), |
| .rst_root_io_div4_ni (rstmgr_aon_resets.rst_por_io_div4_n[rstmgr_pkg::DomainAonSel]), |
| .rst_root_main_ni (rstmgr_aon_resets.rst_por_n[rstmgr_pkg::DomainAonSel]), |
| .rst_root_usb_ni (rstmgr_aon_resets.rst_por_usb_n[rstmgr_pkg::DomainAonSel]), |
| .rst_root_smc_ni (rstmgr_aon_resets.rst_por_smc_n[rstmgr_pkg::DomainAonSel]), |
| .rst_root_ml_ni (rstmgr_aon_resets.rst_por_ml_n[rstmgr_pkg::DomainAonSel]), |
| .rst_root_video_ni (rstmgr_aon_resets.rst_por_video_n[rstmgr_pkg::DomainAonSel]), |
| .rst_root_audio_ni (rstmgr_aon_resets.rst_por_audio_n[rstmgr_pkg::DomainAonSel]) |
| ); |
| sysrst_ctrl #( |
| .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[27:27]) |
| ) u_sysrst_ctrl_aon ( |
| |
| // Input |
| .cio_ac_present_i (cio_sysrst_ctrl_aon_ac_present_p2d), |
| .cio_key0_in_i (cio_sysrst_ctrl_aon_key0_in_p2d), |
| .cio_key1_in_i (cio_sysrst_ctrl_aon_key1_in_p2d), |
| .cio_key2_in_i (cio_sysrst_ctrl_aon_key2_in_p2d), |
| .cio_pwrb_in_i (cio_sysrst_ctrl_aon_pwrb_in_p2d), |
| .cio_lid_open_i (cio_sysrst_ctrl_aon_lid_open_p2d), |
| .cio_ec_rst_l_i (cio_sysrst_ctrl_aon_ec_rst_l_p2d), |
| .cio_flash_wp_l_i (cio_sysrst_ctrl_aon_flash_wp_l_p2d), |
| |
| // Output |
| .cio_bat_disable_o (cio_sysrst_ctrl_aon_bat_disable_d2p), |
| .cio_bat_disable_en_o (cio_sysrst_ctrl_aon_bat_disable_en_d2p), |
| .cio_key0_out_o (cio_sysrst_ctrl_aon_key0_out_d2p), |
| .cio_key0_out_en_o (cio_sysrst_ctrl_aon_key0_out_en_d2p), |
| .cio_key1_out_o (cio_sysrst_ctrl_aon_key1_out_d2p), |
| .cio_key1_out_en_o (cio_sysrst_ctrl_aon_key1_out_en_d2p), |
| .cio_key2_out_o (cio_sysrst_ctrl_aon_key2_out_d2p), |
| .cio_key2_out_en_o (cio_sysrst_ctrl_aon_key2_out_en_d2p), |
| .cio_pwrb_out_o (cio_sysrst_ctrl_aon_pwrb_out_d2p), |
| .cio_pwrb_out_en_o (cio_sysrst_ctrl_aon_pwrb_out_en_d2p), |
| .cio_z3_wakeup_o (cio_sysrst_ctrl_aon_z3_wakeup_d2p), |
| .cio_z3_wakeup_en_o (cio_sysrst_ctrl_aon_z3_wakeup_en_d2p), |
| .cio_ec_rst_l_o (cio_sysrst_ctrl_aon_ec_rst_l_d2p), |
| .cio_ec_rst_l_en_o (cio_sysrst_ctrl_aon_ec_rst_l_en_d2p), |
| .cio_flash_wp_l_o (cio_sysrst_ctrl_aon_flash_wp_l_d2p), |
| .cio_flash_wp_l_en_o (cio_sysrst_ctrl_aon_flash_wp_l_en_d2p), |
| |
| // Interrupt |
| .intr_event_detected_o (intr_sysrst_ctrl_aon_event_detected), |
| // [27]: fatal_fault |
| .alert_tx_o ( alert_tx[27:27] ), |
| .alert_rx_i ( alert_rx[27:27] ), |
| |
| // Inter-module signals |
| .wkup_req_o(pwrmgr_aon_wakeups[0]), |
| .rst_req_o(pwrmgr_aon_rstreqs[0]), |
| .tl_i(sysrst_ctrl_aon_tl_req), |
| .tl_o(sysrst_ctrl_aon_tl_rsp), |
| |
| // Clock and reset connections |
| .clk_i (clkmgr_aon_clocks.clk_io_div4_secure), |
| .clk_aon_i (clkmgr_aon_clocks.clk_aon_secure), |
| .rst_ni (rstmgr_aon_resets.rst_lc_io_div4_n[rstmgr_pkg::DomainAonSel]), |
| .rst_aon_ni (rstmgr_aon_resets.rst_lc_aon_n[rstmgr_pkg::DomainAonSel]) |
| ); |
| adc_ctrl #( |
| .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[28:28]) |
| ) u_adc_ctrl_aon ( |
| |
| // Interrupt |
| .intr_match_done_o (intr_adc_ctrl_aon_match_done), |
| // [28]: fatal_fault |
| .alert_tx_o ( alert_tx[28:28] ), |
| .alert_rx_i ( alert_rx[28:28] ), |
| |
| // Inter-module signals |
| .adc_o(adc_req_o), |
| .adc_i(adc_rsp_i), |
| .wkup_req_o(pwrmgr_aon_wakeups[1]), |
| .tl_i(adc_ctrl_aon_tl_req), |
| .tl_o(adc_ctrl_aon_tl_rsp), |
| |
| // Clock and reset connections |
| .clk_i (clkmgr_aon_clocks.clk_io_div4_peri), |
| .clk_aon_i (clkmgr_aon_clocks.clk_aon_peri), |
| .rst_ni (rstmgr_aon_resets.rst_lc_io_div4_n[rstmgr_pkg::DomainAonSel]), |
| .rst_aon_ni (rstmgr_aon_resets.rst_lc_aon_n[rstmgr_pkg::DomainAonSel]) |
| ); |
| pwm #( |
| .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[29:29]) |
| ) u_pwm_aon ( |
| |
| // Output |
| .cio_pwm_o (cio_pwm_aon_pwm_d2p), |
| .cio_pwm_en_o (cio_pwm_aon_pwm_en_d2p), |
| // [29]: fatal_fault |
| .alert_tx_o ( alert_tx[29:29] ), |
| .alert_rx_i ( alert_rx[29:29] ), |
| |
| // Inter-module signals |
| .tl_i(pwm_aon_tl_req), |
| .tl_o(pwm_aon_tl_rsp), |
| |
| // Clock and reset connections |
| .clk_i (clkmgr_aon_clocks.clk_io_div4_peri), |
| .clk_core_i (clkmgr_aon_clocks.clk_aon_peri), |
| .rst_ni (rstmgr_aon_resets.rst_lc_io_div4_n[rstmgr_pkg::DomainAonSel]), |
| .rst_core_ni (rstmgr_aon_resets.rst_lc_aon_n[rstmgr_pkg::DomainAonSel]) |
| ); |
| pinmux #( |
| .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[30:30]), |
| .TargetCfg(PinmuxAonTargetCfg) |
| ) u_pinmux_aon ( |
| // [30]: fatal_fault |
| .alert_tx_o ( alert_tx[30:30] ), |
| .alert_rx_i ( alert_rx[30:30] ), |
| |
| // Inter-module signals |
| .lc_hw_debug_en_i(lc_ctrl_lc_hw_debug_en), |
| .lc_dft_en_i(lc_ctrl_lc_dft_en), |
| .lc_escalate_en_i(lc_ctrl_lc_escalate_en), |
| .lc_check_byp_en_i(lc_ctrl_lc_check_byp_en), |
| .pinmux_hw_debug_en_o(pinmux_aon_pinmux_hw_debug_en), |
| .lc_jtag_o(pinmux_aon_lc_jtag_req), |
| .lc_jtag_i(pinmux_aon_lc_jtag_rsp), |
| .rv_jtag_o(pinmux_aon_rv_jtag_req), |
| .rv_jtag_i(pinmux_aon_rv_jtag_rsp), |
| .dft_jtag_o(pinmux_aon_dft_jtag_req), |
| .dft_jtag_i(pinmux_aon_dft_jtag_rsp), |
| .dft_strap_test_o(dft_strap_test_o), |
| .dft_hold_tap_sel_i(dft_hold_tap_sel_i), |
| .sleep_en_i(pwrmgr_aon_low_power), |
| .strap_en_i(pwrmgr_aon_strap), |
| .pin_wkup_req_o(pwrmgr_aon_wakeups[2]), |
| .usbdev_dppullup_en_i(usbdev_usb_dp_pullup), |
| .usbdev_dnpullup_en_i(usbdev_usb_dn_pullup), |
| .usb_dppullup_en_o(usb_dp_pullup_en_o), |
| .usb_dnpullup_en_o(usb_dn_pullup_en_o), |
| .usb_wkup_req_o(pwrmgr_aon_wakeups[3]), |
| .usbdev_suspend_req_i(usbdev_usb_aon_suspend_req), |
| .usbdev_wake_ack_i(usbdev_usb_aon_wake_ack), |
| .usbdev_bus_reset_o(usbdev_usb_aon_bus_reset), |
| .usbdev_sense_lost_o(usbdev_usb_aon_sense_lost), |
| .usbdev_wake_detect_active_o(pinmux_aon_usbdev_wake_detect_active), |
| .tl_i(pinmux_aon_tl_req), |
| .tl_o(pinmux_aon_tl_rsp), |
| |
| .periph_to_mio_i (mio_d2p ), |
| .periph_to_mio_oe_i (mio_en_d2p ), |
| .mio_to_periph_o (mio_p2d ), |
| |
| .mio_attr_o, |
| .mio_out_o, |
| .mio_oe_o, |
| .mio_in_i, |
| |
| .periph_to_dio_i (dio_d2p ), |
| .periph_to_dio_oe_i (dio_en_d2p ), |
| .dio_to_periph_o (dio_p2d ), |
| |
| .dio_attr_o, |
| .dio_out_o, |
| .dio_oe_o, |
| .dio_in_i, |
| |
| .scanmode_i, |
| |
| // Clock and reset connections |
| .clk_i (clkmgr_aon_clocks.clk_io_div4_powerup), |
| .clk_aon_i (clkmgr_aon_clocks.clk_aon_powerup), |
| .rst_ni (rstmgr_aon_resets.rst_lc_io_div4_n[rstmgr_pkg::DomainAonSel]), |
| .rst_aon_ni (rstmgr_aon_resets.rst_lc_aon_n[rstmgr_pkg::DomainAonSel]), |
| .rst_sys_ni (rstmgr_aon_resets.rst_sys_io_div4_n[rstmgr_pkg::DomainAonSel]) |
| ); |
| aon_timer #( |
| .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[31:31]) |
| ) u_aon_timer_aon ( |
| |
| // Interrupt |
| .intr_wkup_timer_expired_o (intr_aon_timer_aon_wkup_timer_expired), |
| .intr_wdog_timer_bark_o (intr_aon_timer_aon_wdog_timer_bark), |
| // [31]: fatal_fault |
| .alert_tx_o ( alert_tx[31:31] ), |
| .alert_rx_i ( alert_rx[31:31] ), |
| |
| // Inter-module signals |
| .nmi_wdog_timer_bark_o(aon_timer_aon_nmi_wdog_timer_bark), |
| .wkup_req_o(pwrmgr_aon_wakeups[4]), |
| .aon_timer_rst_req_o(pwrmgr_aon_rstreqs[1]), |
| .lc_escalate_en_i(lc_ctrl_lc_escalate_en), |
| .sleep_mode_i(pwrmgr_aon_low_power), |
| .tl_i(aon_timer_aon_tl_req), |
| .tl_o(aon_timer_aon_tl_rsp), |
| |
| // Clock and reset connections |
| .clk_i (clkmgr_aon_clocks.clk_io_div4_timers), |
| .clk_aon_i (clkmgr_aon_clocks.clk_aon_timers), |
| .rst_ni (rstmgr_aon_resets.rst_lc_io_div4_n[rstmgr_pkg::DomainAonSel]), |
| .rst_aon_ni (rstmgr_aon_resets.rst_lc_aon_n[rstmgr_pkg::DomainAonSel]) |
| ); |
| sensor_ctrl #( |
| .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[33:32]) |
| ) u_sensor_ctrl ( |
| |
| // Output |
| .cio_ast_debug_out_o (cio_sensor_ctrl_ast_debug_out_d2p), |
| .cio_ast_debug_out_en_o (cio_sensor_ctrl_ast_debug_out_en_d2p), |
| |
| // Interrupt |
| .intr_io_status_change_o (intr_sensor_ctrl_io_status_change), |
| .intr_init_status_change_o (intr_sensor_ctrl_init_status_change), |
| // [32]: recov_alert |
| // [33]: fatal_alert |
| .alert_tx_o ( alert_tx[33:32] ), |
| .alert_rx_i ( alert_rx[33:32] ), |
| |
| // Inter-module signals |
| .ast_alert_i(sensor_ctrl_ast_alert_req_i), |
| .ast_alert_o(sensor_ctrl_ast_alert_rsp_o), |
| .ast_status_i(sensor_ctrl_ast_status_i), |
| .ast_init_done_i(ast_init_done_i), |
| .ast2pinmux_i(ast2pinmux_i), |
| .wkup_req_o(pwrmgr_aon_wakeups[5]), |
| .tl_i(sensor_ctrl_tl_req), |
| .tl_o(sensor_ctrl_tl_rsp), |
| |
| // Clock and reset connections |
| .clk_i (clkmgr_aon_clocks.clk_io_div4_secure), |
| .clk_aon_i (clkmgr_aon_clocks.clk_aon_secure), |
| .rst_ni (rstmgr_aon_resets.rst_lc_io_div4_n[rstmgr_pkg::DomainAonSel]), |
| .rst_aon_ni (rstmgr_aon_resets.rst_lc_aon_n[rstmgr_pkg::DomainAonSel]) |
| ); |
| sram_ctrl #( |
| .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[34:34]), |
| .RndCnstSramKey(RndCnstSramCtrlRetAonSramKey), |
| .RndCnstSramNonce(RndCnstSramCtrlRetAonSramNonce), |
| .RndCnstLfsrSeed(RndCnstSramCtrlRetAonLfsrSeed), |
| .RndCnstLfsrPerm(RndCnstSramCtrlRetAonLfsrPerm), |
| .MemSizeRam(4096), |
| .InstrExec(SramCtrlRetAonInstrExec) |
| ) u_sram_ctrl_ret_aon ( |
| // [34]: fatal_error |
| .alert_tx_o ( alert_tx[34:34] ), |
| .alert_rx_i ( alert_rx[34:34] ), |
| |
| // Inter-module signals |
| .sram_otp_key_o(otp_ctrl_sram_otp_key_req[1]), |
| .sram_otp_key_i(otp_ctrl_sram_otp_key_rsp[1]), |
| .cfg_i(ast_ram_1p_cfg), |
| .lc_escalate_en_i(lc_ctrl_lc_escalate_en), |
| .lc_hw_debug_en_i(lc_ctrl_pkg::Off), |
| .otp_en_sram_ifetch_i(prim_mubi_pkg::MuBi8False), |
| .regs_tl_i(sram_ctrl_ret_aon_regs_tl_req), |
| .regs_tl_o(sram_ctrl_ret_aon_regs_tl_rsp), |
| .ram_tl_i(sram_ctrl_ret_aon_ram_tl_req), |
| .ram_tl_o(sram_ctrl_ret_aon_ram_tl_rsp), |
| |
| // Clock and reset connections |
| .clk_i (clkmgr_aon_clocks.clk_io_div4_infra), |
| .clk_otp_i (clkmgr_aon_clocks.clk_io_div4_infra), |
| .rst_ni (rstmgr_aon_resets.rst_lc_io_div4_n[rstmgr_pkg::DomainAonSel]), |
| .rst_otp_ni (rstmgr_aon_resets.rst_lc_io_div4_n[rstmgr_pkg::DomainAonSel]) |
| ); |
| flash_ctrl #( |
| .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[39:35]), |
| .RndCnstAddrKey(RndCnstFlashCtrlAddrKey), |
| .RndCnstDataKey(RndCnstFlashCtrlDataKey), |
| .RndCnstAllSeeds(RndCnstFlashCtrlAllSeeds), |
| .RndCnstLfsrSeed(RndCnstFlashCtrlLfsrSeed), |
| .RndCnstLfsrPerm(RndCnstFlashCtrlLfsrPerm), |
| .SecScrambleEn(SecFlashCtrlScrambleEn), |
| .ProgFifoDepth(FlashCtrlProgFifoDepth), |
| .RdFifoDepth(FlashCtrlRdFifoDepth) |
| ) u_flash_ctrl ( |
| |
| // Input |
| .cio_tck_i (cio_flash_ctrl_tck_p2d), |
| .cio_tms_i (cio_flash_ctrl_tms_p2d), |
| .cio_tdi_i (cio_flash_ctrl_tdi_p2d), |
| |
| // Output |
| .cio_tdo_o (cio_flash_ctrl_tdo_d2p), |
| .cio_tdo_en_o (cio_flash_ctrl_tdo_en_d2p), |
| |
| // Interrupt |
| .intr_prog_empty_o (intr_flash_ctrl_prog_empty), |
| .intr_prog_lvl_o (intr_flash_ctrl_prog_lvl), |
| .intr_rd_full_o (intr_flash_ctrl_rd_full), |
| .intr_rd_lvl_o (intr_flash_ctrl_rd_lvl), |
| .intr_op_done_o (intr_flash_ctrl_op_done), |
| .intr_corr_err_o (intr_flash_ctrl_corr_err), |
| // [35]: recov_err |
| // [36]: fatal_std_err |
| // [37]: fatal_err |
| // [38]: fatal_prim_flash_alert |
| // [39]: recov_prim_flash_alert |
| .alert_tx_o ( alert_tx[39:35] ), |
| .alert_rx_i ( alert_rx[39:35] ), |
| |
| // Inter-module signals |
| .otp_o(flash_ctrl_otp_req), |
| .otp_i(flash_ctrl_otp_rsp), |
| .lc_nvm_debug_en_i(lc_ctrl_lc_nvm_debug_en), |
| .flash_bist_enable_i(flash_bist_enable_i), |
| .flash_power_down_h_i(flash_power_down_h_i), |
| .flash_power_ready_h_i(flash_power_ready_h_i), |
| .flash_test_mode_a_io(flash_test_mode_a_io), |
| .flash_test_voltage_h_io(flash_test_voltage_h_io), |
| .lc_creator_seed_sw_rw_en_i(lc_ctrl_lc_creator_seed_sw_rw_en), |
| .lc_owner_seed_sw_rw_en_i(lc_ctrl_lc_owner_seed_sw_rw_en), |
| .lc_iso_part_sw_rd_en_i(lc_ctrl_lc_iso_part_sw_rd_en), |
| .lc_iso_part_sw_wr_en_i(lc_ctrl_lc_iso_part_sw_wr_en), |
| .lc_seed_hw_rd_en_i(lc_ctrl_lc_seed_hw_rd_en), |
| .lc_escalate_en_i(lc_ctrl_lc_escalate_en), |
| .rma_req_i(lc_ctrl_lc_flash_rma_req), |
| .rma_ack_o(flash_ctrl_rma_ack), |
| .rma_seed_i(flash_ctrl_rma_seed), |
| .pwrmgr_o(pwrmgr_aon_pwr_flash), |
| .keymgr_o(flash_ctrl_keymgr), |
| .obs_ctrl_i(ast_obs_ctrl), |
| .fla_obs_o(flash_obs_o), |
| .core_tl_i(flash_ctrl_core_tl_req), |
| .core_tl_o(flash_ctrl_core_tl_rsp), |
| .prim_tl_i(flash_ctrl_prim_tl_req), |
| .prim_tl_o(flash_ctrl_prim_tl_rsp), |
| .mem_tl_i(flash_ctrl_mem_tl_req), |
| .mem_tl_o(flash_ctrl_mem_tl_rsp), |
| .scanmode_i, |
| .scan_rst_ni, |
| .scan_en_i, |
| |
| // Clock and reset connections |
| .clk_i (clkmgr_aon_clocks.clk_main_infra), |
| .clk_otp_i (clkmgr_aon_clocks.clk_io_div4_infra), |
| .rst_shadowed_ni (rstmgr_aon_resets.rst_lc_shadowed_n[rstmgr_pkg::Domain0Sel]), |
| .rst_ni (rstmgr_aon_resets.rst_lc_n[rstmgr_pkg::Domain0Sel]), |
| .rst_otp_ni (rstmgr_aon_resets.rst_lc_io_div4_n[rstmgr_pkg::Domain0Sel]) |
| ); |
| rv_dm #( |
| .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[40:40]), |
| .IdcodeValue(RvDmIdcodeValue) |
| ) u_rv_dm ( |
| // [40]: fatal_fault |
| .alert_tx_o ( alert_tx[40:40] ), |
| .alert_rx_i ( alert_rx[40:40] ), |
| |
| // Inter-module signals |
| .jtag_i(pinmux_aon_rv_jtag_req), |
| .jtag_o(pinmux_aon_rv_jtag_rsp), |
| .lc_hw_debug_en_i(lc_ctrl_lc_hw_debug_en), |
| .pinmux_hw_debug_en_i(pinmux_aon_pinmux_hw_debug_en), |
| .unavailable_i(2'b0), |
| .ndmreset_req_o(rv_dm_ndmreset_req), |
| .dmactive_o(), |
| .debug_req_o(rv_dm_debug_req), |
| .sba_tl_h_o(main_tl_rv_dm__sba_req), |
| .sba_tl_h_i(main_tl_rv_dm__sba_rsp), |
| .regs_tl_d_i(rv_dm_regs_tl_d_req), |
| .regs_tl_d_o(rv_dm_regs_tl_d_rsp), |
| .mem_tl_d_i(rv_dm_mem_tl_d_req), |
| .mem_tl_d_o(rv_dm_mem_tl_d_rsp), |
| .scanmode_i, |
| .scan_rst_ni, |
| |
| // Clock and reset connections |
| .clk_i (clkmgr_aon_clocks.clk_main_infra), |
| .rst_ni (rstmgr_aon_resets.rst_sys_n[rstmgr_pkg::Domain0Sel]) |
| ); |
| rv_plic #( |
| .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[41:41]) |
| ) u_rv_plic ( |
| // [41]: fatal_fault |
| .alert_tx_o ( alert_tx[41:41] ), |
| .alert_rx_i ( alert_rx[41:41] ), |
| |
| // Inter-module signals |
| .irq_o(rv_plic_irq), |
| .irq_id_o(), |
| .msip_o(rv_plic_msip), |
| .tl_i(rv_plic_tl_req), |
| .tl_o(rv_plic_tl_rsp), |
| .intr_src_i (sec_intr_vector), |
| |
| // Clock and reset connections |
| .clk_i (clkmgr_aon_clocks.clk_main_secure), |
| .rst_ni (rstmgr_aon_resets.rst_lc_n[rstmgr_pkg::Domain0Sel]) |
| ); |
| aes #( |
| .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[43:42]), |
| .AES192Enable(1'b1), |
| .SecMasking(SecAesMasking), |
| .SecSBoxImpl(SecAesSBoxImpl), |
| .SecStartTriggerDelay(SecAesStartTriggerDelay), |
| .SecAllowForcingMasks(SecAesAllowForcingMasks), |
| .SecSkipPRNGReseeding(SecAesSkipPRNGReseeding), |
| .RndCnstClearingLfsrSeed(RndCnstAesClearingLfsrSeed), |
| .RndCnstClearingLfsrPerm(RndCnstAesClearingLfsrPerm), |
| .RndCnstClearingSharePerm(RndCnstAesClearingSharePerm), |
| .RndCnstMaskingLfsrSeed(RndCnstAesMaskingLfsrSeed), |
| .RndCnstMaskingLfsrPerm(RndCnstAesMaskingLfsrPerm) |
| ) u_aes ( |
| // [42]: recov_ctrl_update_err |
| // [43]: fatal_fault |
| .alert_tx_o ( alert_tx[43:42] ), |
| .alert_rx_i ( alert_rx[43:42] ), |
| |
| // Inter-module signals |
| .idle_o(clkmgr_aon_idle[0]), |
| .lc_escalate_en_i(lc_ctrl_lc_escalate_en), |
| .edn_o(edn0_edn_req[5]), |
| .edn_i(edn0_edn_rsp[5]), |
| .keymgr_key_i(keymgr_aes_key), |
| .tl_i(aes_tl_req), |
| .tl_o(aes_tl_rsp), |
| |
| // Clock and reset connections |
| .clk_i (clkmgr_aon_clocks.clk_main_aes), |
| .clk_edn_i (clkmgr_aon_clocks.clk_main_aes), |
| .rst_shadowed_ni (rstmgr_aon_resets.rst_lc_shadowed_n[rstmgr_pkg::Domain0Sel]), |
| .rst_ni (rstmgr_aon_resets.rst_lc_n[rstmgr_pkg::Domain0Sel]), |
| .rst_edn_ni (rstmgr_aon_resets.rst_lc_n[rstmgr_pkg::Domain0Sel]) |
| ); |
| hmac #( |
| .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[44:44]) |
| ) u_hmac ( |
| |
| // Interrupt |
| .intr_hmac_done_o (intr_hmac_hmac_done), |
| .intr_fifo_empty_o (intr_hmac_fifo_empty), |
| .intr_hmac_err_o (intr_hmac_hmac_err), |
| // [44]: fatal_fault |
| .alert_tx_o ( alert_tx[44:44] ), |
| .alert_rx_i ( alert_rx[44:44] ), |
| |
| // Inter-module signals |
| .idle_o(clkmgr_aon_idle[1]), |
| .tl_i(hmac_tl_req), |
| .tl_o(hmac_tl_rsp), |
| |
| // Clock and reset connections |
| .clk_i (clkmgr_aon_clocks.clk_main_hmac), |
| .rst_ni (rstmgr_aon_resets.rst_lc_n[rstmgr_pkg::Domain0Sel]) |
| ); |
| kmac #( |
| .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[46:45]), |
| .EnMasking(KmacEnMasking), |
| .SwKeyMasked(KmacSwKeyMasked), |
| .SecCmdDelay(SecKmacCmdDelay), |
| .SecIdleAcceptSwMsg(SecKmacIdleAcceptSwMsg), |
| .RndCnstLfsrSeed(RndCnstKmacLfsrSeed), |
| .RndCnstLfsrPerm(RndCnstKmacLfsrPerm), |
| .RndCnstLfsrFwdPerm(RndCnstKmacLfsrFwdPerm), |
| .RndCnstMsgPerm(RndCnstKmacMsgPerm) |
| ) u_kmac ( |
| |
| // Interrupt |
| .intr_kmac_done_o (intr_kmac_kmac_done), |
| .intr_fifo_empty_o (intr_kmac_fifo_empty), |
| .intr_kmac_err_o (intr_kmac_kmac_err), |
| // [45]: recov_operation_err |
| // [46]: fatal_fault_err |
| .alert_tx_o ( alert_tx[46:45] ), |
| .alert_rx_i ( alert_rx[46:45] ), |
| |
| // Inter-module signals |
| .keymgr_key_i(keymgr_kmac_key), |
| .app_i(kmac_app_req), |
| .app_o(kmac_app_rsp), |
| .entropy_o(edn0_edn_req[3]), |
| .entropy_i(edn0_edn_rsp[3]), |
| .idle_o(clkmgr_aon_idle[2]), |
| .en_masking_o(kmac_en_masking), |
| .lc_escalate_en_i(lc_ctrl_lc_escalate_en), |
| .tl_i(kmac_tl_req), |
| .tl_o(kmac_tl_rsp), |
| |
| // Clock and reset connections |
| .clk_i (clkmgr_aon_clocks.clk_main_kmac), |
| .clk_edn_i (clkmgr_aon_clocks.clk_main_kmac), |
| .rst_shadowed_ni (rstmgr_aon_resets.rst_lc_shadowed_n[rstmgr_pkg::Domain0Sel]), |
| .rst_ni (rstmgr_aon_resets.rst_lc_n[rstmgr_pkg::Domain0Sel]), |
| .rst_edn_ni (rstmgr_aon_resets.rst_lc_n[rstmgr_pkg::Domain0Sel]) |
| ); |
| otbn #( |
| .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[48:47]), |
| .Stub(OtbnStub), |
| .RegFile(OtbnRegFile), |
| .RndCnstUrndPrngSeed(RndCnstOtbnUrndPrngSeed), |
| .SecMuteUrnd(SecOtbnMuteUrnd), |
| .SecSkipUrndReseedAtStart(SecOtbnSkipUrndReseedAtStart), |
| .RndCnstOtbnKey(RndCnstOtbnOtbnKey), |
| .RndCnstOtbnNonce(RndCnstOtbnOtbnNonce) |
| ) u_otbn ( |
| |
| // Interrupt |
| .intr_done_o (intr_otbn_done), |
| // [47]: fatal |
| // [48]: recov |
| .alert_tx_o ( alert_tx[48:47] ), |
| .alert_rx_i ( alert_rx[48:47] ), |
| |
| // Inter-module signals |
| .otbn_otp_key_o(otp_ctrl_otbn_otp_key_req), |
| .otbn_otp_key_i(otp_ctrl_otbn_otp_key_rsp), |
| .edn_rnd_o(edn1_edn_req[0]), |
| .edn_rnd_i(edn1_edn_rsp[0]), |
| .edn_urnd_o(edn0_edn_req[6]), |
| .edn_urnd_i(edn0_edn_rsp[6]), |
| .idle_o(clkmgr_aon_idle[3]), |
| .ram_cfg_i(ast_ram_1p_cfg), |
| .lc_escalate_en_i(lc_ctrl_lc_escalate_en), |
| .lc_rma_req_i(flash_ctrl_rma_ack), |
| .lc_rma_ack_o(otbn_lc_rma_ack), |
| .keymgr_key_i(keymgr_otbn_key), |
| .tl_i(otbn_tl_req), |
| .tl_o(otbn_tl_rsp), |
| |
| // Clock and reset connections |
| .clk_i (clkmgr_aon_clocks.clk_main_otbn), |
| .clk_edn_i (clkmgr_aon_clocks.clk_main_secure), |
| .clk_otp_i (clkmgr_aon_clocks.clk_io_div4_secure), |
| .rst_ni (rstmgr_aon_resets.rst_lc_n[rstmgr_pkg::Domain0Sel]), |
| .rst_edn_ni (rstmgr_aon_resets.rst_lc_n[rstmgr_pkg::Domain0Sel]), |
| .rst_otp_ni (rstmgr_aon_resets.rst_lc_io_div4_n[rstmgr_pkg::Domain0Sel]) |
| ); |
| keymgr #( |
| .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[50:49]), |
| .KmacEnMasking(KeymgrKmacEnMasking), |
| .RndCnstLfsrSeed(RndCnstKeymgrLfsrSeed), |
| .RndCnstLfsrPerm(RndCnstKeymgrLfsrPerm), |
| .RndCnstRandPerm(RndCnstKeymgrRandPerm), |
| .RndCnstRevisionSeed(RndCnstKeymgrRevisionSeed), |
| .RndCnstCreatorIdentitySeed(RndCnstKeymgrCreatorIdentitySeed), |
| .RndCnstOwnerIntIdentitySeed(RndCnstKeymgrOwnerIntIdentitySeed), |
| .RndCnstOwnerIdentitySeed(RndCnstKeymgrOwnerIdentitySeed), |
| .RndCnstSoftOutputSeed(RndCnstKeymgrSoftOutputSeed), |
| .RndCnstHardOutputSeed(RndCnstKeymgrHardOutputSeed), |
| .RndCnstAesSeed(RndCnstKeymgrAesSeed), |
| .RndCnstKmacSeed(RndCnstKeymgrKmacSeed), |
| .RndCnstOtbnSeed(RndCnstKeymgrOtbnSeed), |
| .RndCnstCdi(RndCnstKeymgrCdi), |
| .RndCnstNoneSeed(RndCnstKeymgrNoneSeed) |
| ) u_keymgr ( |
| |
| // Interrupt |
| .intr_op_done_o (intr_keymgr_op_done), |
| // [49]: recov_operation_err |
| // [50]: fatal_fault_err |
| .alert_tx_o ( alert_tx[50:49] ), |
| .alert_rx_i ( alert_rx[50:49] ), |
| |
| // Inter-module signals |
| .edn_o(edn0_edn_req[0]), |
| .edn_i(edn0_edn_rsp[0]), |
| .aes_key_o(keymgr_aes_key), |
| .kmac_key_o(keymgr_kmac_key), |
| .otbn_key_o(keymgr_otbn_key), |
| .kmac_data_o(kmac_app_req[0]), |
| .kmac_data_i(kmac_app_rsp[0]), |
| .otp_key_i(otp_ctrl_otp_keymgr_key), |
| .otp_device_id_i(keymgr_otp_device_id), |
| .flash_i(flash_ctrl_keymgr), |
| .lc_keymgr_en_i(lc_ctrl_lc_keymgr_en), |
| .lc_keymgr_div_i(lc_ctrl_lc_keymgr_div), |
| .rom_digest_i(rom_ctrl_keymgr_data), |
| .kmac_en_masking_i(kmac_en_masking), |
| .tl_i(keymgr_tl_req), |
| .tl_o(keymgr_tl_rsp), |
| |
| // Clock and reset connections |
| .clk_i (clkmgr_aon_clocks.clk_main_secure), |
| .clk_edn_i (clkmgr_aon_clocks.clk_main_secure), |
| .rst_shadowed_ni (rstmgr_aon_resets.rst_lc_shadowed_n[rstmgr_pkg::Domain0Sel]), |
| .rst_ni (rstmgr_aon_resets.rst_lc_n[rstmgr_pkg::Domain0Sel]), |
| .rst_edn_ni (rstmgr_aon_resets.rst_lc_n[rstmgr_pkg::Domain0Sel]) |
| ); |
| csrng #( |
| .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[52:51]), |
| .RndCnstCsKeymgrDivNonProduction(RndCnstCsrngCsKeymgrDivNonProduction), |
| .RndCnstCsKeymgrDivProduction(RndCnstCsrngCsKeymgrDivProduction), |
| .SBoxImpl(CsrngSBoxImpl) |
| ) u_csrng ( |
| |
| // Interrupt |
| .intr_cs_cmd_req_done_o (intr_csrng_cs_cmd_req_done), |
| .intr_cs_entropy_req_o (intr_csrng_cs_entropy_req), |
| .intr_cs_hw_inst_exc_o (intr_csrng_cs_hw_inst_exc), |
| .intr_cs_fatal_err_o (intr_csrng_cs_fatal_err), |
| // [51]: recov_alert |
| // [52]: fatal_alert |
| .alert_tx_o ( alert_tx[52:51] ), |
| .alert_rx_i ( alert_rx[52:51] ), |
| |
| // Inter-module signals |
| .csrng_cmd_i(csrng_csrng_cmd_req), |
| .csrng_cmd_o(csrng_csrng_cmd_rsp), |
| .entropy_src_hw_if_o(csrng_entropy_src_hw_if_req), |
| .entropy_src_hw_if_i(csrng_entropy_src_hw_if_rsp), |
| .cs_aes_halt_i(csrng_cs_aes_halt_req), |
| .cs_aes_halt_o(csrng_cs_aes_halt_rsp), |
| .otp_en_csrng_sw_app_read_i(csrng_otp_en_csrng_sw_app_read), |
| .lc_hw_debug_en_i(lc_ctrl_lc_hw_debug_en), |
| .tl_i(csrng_tl_req), |
| .tl_o(csrng_tl_rsp), |
| |
| // Clock and reset connections |
| .clk_i (clkmgr_aon_clocks.clk_main_secure), |
| .rst_ni (rstmgr_aon_resets.rst_lc_n[rstmgr_pkg::Domain0Sel]) |
| ); |
| entropy_src #( |
| .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[54:53]), |
| .Stub(EntropySrcStub) |
| ) u_entropy_src ( |
| |
| // Interrupt |
| .intr_es_entropy_valid_o (intr_entropy_src_es_entropy_valid), |
| .intr_es_health_test_failed_o (intr_entropy_src_es_health_test_failed), |
| .intr_es_observe_fifo_ready_o (intr_entropy_src_es_observe_fifo_ready), |
| .intr_es_fatal_err_o (intr_entropy_src_es_fatal_err), |
| // [53]: recov_alert |
| // [54]: fatal_alert |
| .alert_tx_o ( alert_tx[54:53] ), |
| .alert_rx_i ( alert_rx[54:53] ), |
| |
| // Inter-module signals |
| .entropy_src_hw_if_i(csrng_entropy_src_hw_if_req), |
| .entropy_src_hw_if_o(csrng_entropy_src_hw_if_rsp), |
| .cs_aes_halt_o(csrng_cs_aes_halt_req), |
| .cs_aes_halt_i(csrng_cs_aes_halt_rsp), |
| .entropy_src_rng_o(es_rng_req_o), |
| .entropy_src_rng_i(es_rng_rsp_i), |
| .entropy_src_xht_o(), |
| .entropy_src_xht_i(entropy_src_pkg::ENTROPY_SRC_XHT_RSP_DEFAULT), |
| .otp_en_entropy_src_fw_read_i(entropy_src_otp_en_entropy_src_fw_read), |
| .otp_en_entropy_src_fw_over_i(entropy_src_otp_en_entropy_src_fw_over), |
| .rng_fips_o(es_rng_fips_o), |
| .tl_i(entropy_src_tl_req), |
| .tl_o(entropy_src_tl_rsp), |
| |
| // Clock and reset connections |
| .clk_i (clkmgr_aon_clocks.clk_main_secure), |
| .rst_ni (rstmgr_aon_resets.rst_lc_n[rstmgr_pkg::Domain0Sel]) |
| ); |
| edn #( |
| .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[56:55]) |
| ) u_edn0 ( |
| |
| // Interrupt |
| .intr_edn_cmd_req_done_o (intr_edn0_edn_cmd_req_done), |
| .intr_edn_fatal_err_o (intr_edn0_edn_fatal_err), |
| // [55]: recov_alert |
| // [56]: fatal_alert |
| .alert_tx_o ( alert_tx[56:55] ), |
| .alert_rx_i ( alert_rx[56:55] ), |
| |
| // Inter-module signals |
| .csrng_cmd_o(csrng_csrng_cmd_req[0]), |
| .csrng_cmd_i(csrng_csrng_cmd_rsp[0]), |
| .edn_i(edn0_edn_req), |
| .edn_o(edn0_edn_rsp), |
| .tl_i(edn0_tl_req), |
| .tl_o(edn0_tl_rsp), |
| |
| // Clock and reset connections |
| .clk_i (clkmgr_aon_clocks.clk_main_secure), |
| .rst_ni (rstmgr_aon_resets.rst_lc_n[rstmgr_pkg::Domain0Sel]) |
| ); |
| edn #( |
| .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[58:57]) |
| ) u_edn1 ( |
| |
| // Interrupt |
| .intr_edn_cmd_req_done_o (intr_edn1_edn_cmd_req_done), |
| .intr_edn_fatal_err_o (intr_edn1_edn_fatal_err), |
| // [57]: recov_alert |
| // [58]: fatal_alert |
| .alert_tx_o ( alert_tx[58:57] ), |
| .alert_rx_i ( alert_rx[58:57] ), |
| |
| // Inter-module signals |
| .csrng_cmd_o(csrng_csrng_cmd_req[1]), |
| .csrng_cmd_i(csrng_csrng_cmd_rsp[1]), |
| .edn_i(edn1_edn_req), |
| .edn_o(edn1_edn_rsp), |
| .tl_i(edn1_tl_req), |
| .tl_o(edn1_tl_rsp), |
| |
| // Clock and reset connections |
| .clk_i (clkmgr_aon_clocks.clk_main_secure), |
| .rst_ni (rstmgr_aon_resets.rst_lc_n[rstmgr_pkg::Domain0Sel]) |
| ); |
| sram_ctrl #( |
| .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[59:59]), |
| .RndCnstSramKey(RndCnstSramCtrlMainSramKey), |
| .RndCnstSramNonce(RndCnstSramCtrlMainSramNonce), |
| .RndCnstLfsrSeed(RndCnstSramCtrlMainLfsrSeed), |
| .RndCnstLfsrPerm(RndCnstSramCtrlMainLfsrPerm), |
| .MemSizeRam(131072), |
| .InstrExec(SramCtrlMainInstrExec) |
| ) u_sram_ctrl_main ( |
| // [59]: fatal_error |
| .alert_tx_o ( alert_tx[59:59] ), |
| .alert_rx_i ( alert_rx[59:59] ), |
| |
| // Inter-module signals |
| .sram_otp_key_o(otp_ctrl_sram_otp_key_req[0]), |
| .sram_otp_key_i(otp_ctrl_sram_otp_key_rsp[0]), |
| .cfg_i(ast_ram_1p_cfg), |
| .lc_escalate_en_i(lc_ctrl_lc_escalate_en), |
| .lc_hw_debug_en_i(lc_ctrl_lc_hw_debug_en), |
| .otp_en_sram_ifetch_i(sram_ctrl_main_otp_en_sram_ifetch), |
| .regs_tl_i(sram_ctrl_main_regs_tl_req), |
| .regs_tl_o(sram_ctrl_main_regs_tl_rsp), |
| .ram_tl_i(sram_ctrl_main_ram_tl_req), |
| .ram_tl_o(sram_ctrl_main_ram_tl_rsp), |
| |
| // Clock and reset connections |
| .clk_i (clkmgr_aon_clocks.clk_main_infra), |
| .clk_otp_i (clkmgr_aon_clocks.clk_io_div4_infra), |
| .rst_ni (rstmgr_aon_resets.rst_lc_n[rstmgr_pkg::Domain0Sel]), |
| .rst_otp_ni (rstmgr_aon_resets.rst_lc_io_div4_n[rstmgr_pkg::Domain0Sel]) |
| ); |
| rom_ctrl #( |
| .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[60:60]), |
| .BootRomInitFile(RomCtrlBootRomInitFile), |
| .RndCnstScrNonce(RndCnstRomCtrlScrNonce), |
| .RndCnstScrKey(RndCnstRomCtrlScrKey), |
| .SecDisableScrambling(SecRomCtrlDisableScrambling) |
| ) u_rom_ctrl ( |
| // [60]: fatal |
| .alert_tx_o ( alert_tx[60:60] ), |
| .alert_rx_i ( alert_rx[60:60] ), |
| |
| // Inter-module signals |
| .rom_cfg_i(ast_rom_cfg), |
| .pwrmgr_data_o(rom_ctrl_pwrmgr_data), |
| .keymgr_data_o(rom_ctrl_keymgr_data), |
| .kmac_data_o(kmac_app_req[2]), |
| .kmac_data_i(kmac_app_rsp[2]), |
| .regs_tl_i(rom_ctrl_regs_tl_req), |
| .regs_tl_o(rom_ctrl_regs_tl_rsp), |
| .rom_tl_i(rom_ctrl_rom_tl_req), |
| .rom_tl_o(rom_ctrl_rom_tl_rsp), |
| |
| // Clock and reset connections |
| .clk_i (clkmgr_aon_clocks.clk_main_infra), |
| .rst_ni (rstmgr_aon_resets.rst_lc_n[rstmgr_pkg::Domain0Sel]) |
| ); |
| rv_core_ibex #( |
| .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[64:61]), |
| .RndCnstLfsrSeed(RndCnstRvCoreIbexSecLfsrSeed), |
| .RndCnstLfsrPerm(RndCnstRvCoreIbexSecLfsrPerm), |
| .RndCnstIbexKeyDefault(RndCnstRvCoreIbexSecIbexKeyDefault), |
| .RndCnstIbexNonceDefault(RndCnstRvCoreIbexSecIbexNonceDefault), |
| .PMPEnable(RvCoreIbexSecPMPEnable), |
| .PMPGranularity(RvCoreIbexSecPMPGranularity), |
| .PMPNumRegions(RvCoreIbexSecPMPNumRegions), |
| .MHPMCounterNum(RvCoreIbexSecMHPMCounterNum), |
| .MHPMCounterWidth(RvCoreIbexSecMHPMCounterWidth), |
| .RV32E(RvCoreIbexSecRV32E), |
| .RV32M(RvCoreIbexSecRV32M), |
| .RV32B(RvCoreIbexSecRV32B), |
| .RegFile(RvCoreIbexSecRegFile), |
| .BranchTargetALU(RvCoreIbexSecBranchTargetALU), |
| .WritebackStage(RvCoreIbexSecWritebackStage), |
| .ICache(RvCoreIbexSecICache), |
| .ICacheECC(RvCoreIbexSecICacheECC), |
| .ICacheScramble(RvCoreIbexSecICacheScramble), |
| .BranchPredictor(RvCoreIbexSecBranchPredictor), |
| .DbgTriggerEn(RvCoreIbexSecDbgTriggerEn), |
| .DbgHwBreakNum(RvCoreIbexSecDbgHwBreakNum), |
| .SecureIbex(RvCoreIbexSecSecureIbex), |
| .DmHaltAddr(RvCoreIbexSecDmHaltAddr), |
| .DmExceptionAddr(RvCoreIbexSecDmExceptionAddr), |
| .PipeLine(RvCoreIbexSecPipeLine) |
| ) u_rv_core_ibex_sec ( |
| // [61]: fatal_sw_err |
| // [62]: recov_sw_err |
| // [63]: fatal_hw_err |
| // [64]: recov_hw_err |
| .alert_tx_o ( alert_tx[64:61] ), |
| .alert_rx_i ( alert_rx[64:61] ), |
| |
| // Inter-module signals |
| .rst_cpu_n_o(), |
| .ram_cfg_i(ast_ram_1p_cfg), |
| .hart_id_i(rv_core_ibex_sec_hart_id), |
| .boot_addr_i(rv_core_ibex_sec_boot_addr), |
| .irq_software_i(rv_plic_msip[0]), |
| .irq_timer_i(rv_core_ibex_sec_irq_timer), |
| .irq_external_i(rv_plic_irq[0]), |
| .esc_tx_i(alert_handler_esc_tx[0]), |
| .esc_rx_o(alert_handler_esc_rx[0]), |
| .debug_req_i(rv_dm_debug_req[0]), |
| .crash_dump_o(rv_core_ibex_sec_crash_dump), |
| .lc_cpu_en_i(lc_ctrl_lc_cpu_en), |
| .pwrmgr_cpu_en_i(pwrmgr_aon_fetch_en), |
| .pwrmgr_o(rv_core_ibex_sec_pwrmgr), |
| .nmi_wdog_i(aon_timer_aon_nmi_wdog_timer_bark), |
| .edn_o(edn0_edn_req[7]), |
| .edn_i(edn0_edn_rsp[7]), |
| .icache_otp_key_o(otp_ctrl_sram_otp_key_req[2]), |
| .icache_otp_key_i(otp_ctrl_sram_otp_key_rsp[2]), |
| .fpga_info_i(fpga_info_i), |
| .corei_tl_h_o(main_tl_rv_core_ibex_sec__corei_req), |
| .corei_tl_h_i(main_tl_rv_core_ibex_sec__corei_rsp), |
| .cored_tl_h_o(main_tl_rv_core_ibex_sec__cored_req), |
| .cored_tl_h_i(main_tl_rv_core_ibex_sec__cored_rsp), |
| .cfg_tl_d_i(rv_core_ibex_sec_cfg_tl_d_req), |
| .cfg_tl_d_o(rv_core_ibex_sec_cfg_tl_d_rsp), |
| .scanmode_i, |
| .scan_rst_ni, |
| |
| // Clock and reset connections |
| .clk_i (clkmgr_aon_clocks.clk_main_infra), |
| .clk_edn_i (clkmgr_aon_clocks.clk_main_infra), |
| .clk_esc_i (clkmgr_aon_clocks.clk_io_div4_secure), |
| .clk_otp_i (clkmgr_aon_clocks.clk_io_div4_secure), |
| .rst_ni (rstmgr_aon_resets.rst_lc_n[rstmgr_pkg::Domain0Sel]), |
| .rst_edn_ni (rstmgr_aon_resets.rst_lc_n[rstmgr_pkg::Domain0Sel]), |
| .rst_esc_ni (rstmgr_aon_resets.rst_lc_io_div4_n[rstmgr_pkg::Domain0Sel]), |
| .rst_otp_ni (rstmgr_aon_resets.rst_lc_io_div4_n[rstmgr_pkg::Domain0Sel]) |
| ); |
| dma u_dma0 ( |
| |
| // Interrupt |
| .intr_writer_done_o (intr_dma0_writer_done), |
| .intr_reader_done_o (intr_dma0_reader_done), |
| |
| // Inter-module signals |
| .writer_tl_h_o(main_tl_dma0__writer_req), |
| .writer_tl_h_i(main_tl_dma0__writer_rsp), |
| .reader_tl_h_o(main_tl_dma0__reader_req), |
| .reader_tl_h_i(main_tl_dma0__reader_rsp), |
| .tl_d_i(dma0_tl_d_req), |
| .tl_d_o(dma0_tl_d_rsp), |
| |
| // Clock and reset connections |
| .clk_i (clkmgr_aon_clocks.clk_main_infra), |
| .rst_ni (rstmgr_aon_resets.rst_lc_n[rstmgr_pkg::Domain0Sel]) |
| ); |
| uart #( |
| .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[65:65]) |
| ) u_smc_uart ( |
| |
| // Input |
| .cio_rx_i (cio_smc_uart_rx_p2d), |
| |
| // Output |
| .cio_tx_o (cio_smc_uart_tx_d2p), |
| .cio_tx_en_o (cio_smc_uart_tx_en_d2p), |
| |
| // Interrupt |
| .intr_tx_watermark_o (intr_smc_uart_tx_watermark), |
| .intr_rx_watermark_o (intr_smc_uart_rx_watermark), |
| .intr_tx_empty_o (intr_smc_uart_tx_empty), |
| .intr_rx_overflow_o (intr_smc_uart_rx_overflow), |
| .intr_rx_frame_err_o (intr_smc_uart_rx_frame_err), |
| .intr_rx_break_err_o (intr_smc_uart_rx_break_err), |
| .intr_rx_timeout_o (intr_smc_uart_rx_timeout), |
| .intr_rx_parity_err_o (intr_smc_uart_rx_parity_err), |
| // [65]: fatal_fault |
| .alert_tx_o ( alert_tx[65:65] ), |
| .alert_rx_i ( alert_rx[65:65] ), |
| |
| // Inter-module signals |
| .tl_i(smc_uart_tl_req), |
| .tl_o(smc_uart_tl_rsp), |
| |
| // Clock and reset connections |
| .clk_i (clkmgr_aon_clocks.clk_io_div4_peri), |
| .rst_ni (rstmgr_aon_resets.rst_lc_io_div4_n[rstmgr_pkg::Domain0Sel]) |
| ); |
| rv_timer #( |
| .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[66:66]) |
| ) u_rv_timer_smc ( |
| |
| // Interrupt |
| .intr_timer_expired_hart0_timer0_o (intr_rv_timer_smc_timer_expired_hart0_timer0), |
| // [66]: fatal_fault |
| .alert_tx_o ( alert_tx[66:66] ), |
| .alert_rx_i ( alert_rx[66:66] ), |
| |
| // Inter-module signals |
| .tl_i(rv_timer_smc_tl_req), |
| .tl_o(rv_timer_smc_tl_rsp), |
| |
| // Clock and reset connections |
| .clk_i (clkmgr_aon_clocks.clk_io_div4_timers), |
| .rst_ni (rstmgr_aon_resets.rst_lc_io_div4_n[rstmgr_pkg::Domain0Sel]) |
| ); |
| logic smc_ctrl_boot_en_o; |
| assign rv_core_ibex_smc_pwrmgr_cpu_en = lc_ctrl_pkg::lc_tx_t'(smc_ctrl_boot_en_o); |
| smc_ctrl u_smc_ctrl ( |
| |
| // Inter-module signals |
| .smc_boot_en_o(smc_ctrl_boot_en_o), |
| .tl_i(smc_ctrl_tl_req), |
| .tl_o(smc_ctrl_tl_rsp), |
| |
| // Clock and reset connections |
| .clk_i (clkmgr_aon_clocks.clk_smc_secure), |
| .rst_ni (rstmgr_aon_resets.rst_smc_n[rstmgr_pkg::Domain0Sel]) |
| ); |
| i2c #( |
| .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[67:67]) |
| ) u_cam_i2c ( |
| |
| // Input |
| .cio_sda_i (cio_cam_i2c_sda_p2d), |
| .cio_scl_i (cio_cam_i2c_scl_p2d), |
| |
| // Output |
| .cio_sda_o (cio_cam_i2c_sda_d2p), |
| .cio_sda_en_o (cio_cam_i2c_sda_en_d2p), |
| .cio_scl_o (cio_cam_i2c_scl_d2p), |
| .cio_scl_en_o (cio_cam_i2c_scl_en_d2p), |
| |
| // Interrupt |
| .intr_fmt_threshold_o (intr_cam_i2c_fmt_threshold), |
| .intr_rx_threshold_o (intr_cam_i2c_rx_threshold), |
| .intr_fmt_overflow_o (intr_cam_i2c_fmt_overflow), |
| .intr_rx_overflow_o (intr_cam_i2c_rx_overflow), |
| .intr_nak_o (intr_cam_i2c_nak), |
| .intr_scl_interference_o (intr_cam_i2c_scl_interference), |
| .intr_sda_interference_o (intr_cam_i2c_sda_interference), |
| .intr_stretch_timeout_o (intr_cam_i2c_stretch_timeout), |
| .intr_sda_unstable_o (intr_cam_i2c_sda_unstable), |
| .intr_cmd_complete_o (intr_cam_i2c_cmd_complete), |
| .intr_tx_stretch_o (intr_cam_i2c_tx_stretch), |
| .intr_tx_overflow_o (intr_cam_i2c_tx_overflow), |
| .intr_acq_full_o (intr_cam_i2c_acq_full), |
| .intr_unexp_stop_o (intr_cam_i2c_unexp_stop), |
| .intr_host_timeout_o (intr_cam_i2c_host_timeout), |
| // [67]: fatal_fault |
| .alert_tx_o ( alert_tx[67:67] ), |
| .alert_rx_i ( alert_rx[67:67] ), |
| |
| // Inter-module signals |
| .tl_i(cam_i2c_tl_req), |
| .tl_o(cam_i2c_tl_rsp), |
| |
| // Clock and reset connections |
| .clk_i (clkmgr_aon_clocks.clk_io_div4_peri), |
| .rst_ni (rstmgr_aon_resets.rst_cam_i2c_n[rstmgr_pkg::Domain0Sel]) |
| ); |
| cam_ctrl u_cam_ctrl ( |
| |
| // Input |
| .cio_cam_int_i (cio_cam_ctrl_cam_int_p2d), |
| |
| // Output |
| .cio_cam_trig_o (cio_cam_ctrl_cam_trig_d2p), |
| .cio_cam_trig_en_o (cio_cam_ctrl_cam_trig_en_d2p), |
| |
| // Interrupt |
| .intr_cam_motion_detect_o (intr_cam_ctrl_cam_motion_detect), |
| |
| // Inter-module signals |
| .tl_i(cam_ctrl_tl_req), |
| .tl_o(cam_ctrl_tl_rsp), |
| |
| // Clock and reset connections |
| .clk_i (clkmgr_aon_clocks.clk_io_div4_peri), |
| .rst_ni (rstmgr_aon_resets.rst_lc_io_div4_n[rstmgr_pkg::Domain0Sel]) |
| ); |
| isp_wrapper #( |
| .AhbLiteDataWidth(IspWrapperAhbLiteDataWidth), |
| .TimeoutLimit(IspWrapperTimeoutLimit) |
| ) u_isp_wrapper ( |
| |
| // Input |
| .cio_s_pclk_i (cio_isp_wrapper_s_pclk_p2d), |
| .cio_s_data_i (cio_isp_wrapper_s_data_p2d), |
| .cio_s_hsync_i (cio_isp_wrapper_s_hsync_p2d), |
| .cio_s_vsync_i (cio_isp_wrapper_s_vsync_p2d), |
| |
| // Interrupt |
| .intr_isp_o (intr_isp_wrapper_isp), |
| .intr_mi_o (intr_isp_wrapper_mi), |
| |
| // Inter-module signals |
| .disable_isp_i('0), |
| .scanmode_i('0), |
| .out_y_r_frame_start_o(), |
| .out_y_r_frame_end_o(), |
| .out_y_r_line_start_o(), |
| .out_y_r_line_end_o(), |
| .out_cb_g_frame_start_o(), |
| .out_cb_g_frame_end_o(), |
| .out_cb_g_line_start_o(), |
| .out_cb_g_line_end_o(), |
| .out_cr_b_frame_start_o(), |
| .out_cr_b_frame_end_o(), |
| .out_cr_b_line_start_o(), |
| .out_cr_b_line_end_o(), |
| .out_y_r_val_stream_o(), |
| .out_y_r_data_stream_o(), |
| .out_cb_g_val_stream_o(), |
| .out_cb_g_data_stream_o(), |
| .out_cr_b_val_stream_o(), |
| .out_cr_b_data_stream_o(), |
| .isp_cvalid_o(isp_wrapper_isp_cvalid), |
| .isp_cready_i(isp_wrapper_isp_cready), |
| .isp_cwrite_o(isp_wrapper_isp_cwrite), |
| .isp_caddr_o(isp_wrapper_isp_caddr), |
| .isp_wdata_o(isp_wrapper_isp_wdata), |
| .isp_wmask_o(isp_wrapper_isp_wmask), |
| .tl_i(isp_wrapper_tl_req), |
| .tl_o(isp_wrapper_tl_rsp), |
| |
| // Clock and reset connections |
| .clk_i (clkmgr_aon_clocks.clk_video_peri), |
| .clk_core_i (clkmgr_aon_clocks.clk_video_peri), |
| .clk_axi_i (clkmgr_aon_clocks.clk_video_peri), |
| .rst_ni (rstmgr_aon_resets.rst_smc_n[rstmgr_pkg::Domain0Sel]) |
| ); |
| dma u_dma_smc ( |
| |
| // Interrupt |
| .intr_writer_done_o (intr_dma_smc_writer_done), |
| .intr_reader_done_o (intr_dma_smc_reader_done), |
| |
| // Inter-module signals |
| .writer_tl_h_o(smc_tl_dma_smc__writer_req), |
| .writer_tl_h_i(smc_tl_dma_smc__writer_rsp), |
| .reader_tl_h_o(smc_tl_dma_smc__reader_req), |
| .reader_tl_h_i(smc_tl_dma_smc__reader_rsp), |
| .tl_d_i(dma_smc_tl_d_req), |
| .tl_d_o(dma_smc_tl_d_rsp), |
| |
| // Clock and reset connections |
| .clk_i (clkmgr_aon_clocks.clk_smc_infra), |
| .rst_ni (rstmgr_aon_resets.rst_smc_n[rstmgr_pkg::Domain0Sel]) |
| ); |
| rv_plic_smc #( |
| .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[68:68]) |
| ) u_rv_plic_smc ( |
| // [68]: fatal_fault |
| .alert_tx_o ( alert_tx[68:68] ), |
| .alert_rx_i ( alert_rx[68:68] ), |
| |
| // Inter-module signals |
| .irq_o(rv_plic_smc_irq), |
| .irq_id_o(), |
| .msip_o(rv_plic_smc_msip), |
| .tl_i(rv_plic_smc_tl_req), |
| .tl_o(rv_plic_smc_tl_rsp), |
| .intr_src_i (smc_intr_vector), |
| |
| // Clock and reset connections |
| .clk_i (clkmgr_aon_clocks.clk_smc_infra), |
| .rst_ni (rstmgr_aon_resets.rst_smc_n[rstmgr_pkg::Domain0Sel]) |
| ); |
| tlul_mailbox #( |
| .MailboxDepth(TlulMailboxSecMailboxDepth) |
| ) u_tlul_mailbox_sec ( |
| |
| // Interrupt |
| .intr_core0_wtirq_o (intr_tlul_mailbox_sec_wtirq), |
| .intr_core1_wtirq_o (intr_tlul_mailbox_smc_wtirq), |
| .intr_core0_rtirq_o (intr_tlul_mailbox_sec_rtirq), |
| .intr_core1_rtirq_o (intr_tlul_mailbox_smc_rtirq), |
| .intr_core0_eirq_o (intr_tlul_mailbox_sec_eirq), |
| .intr_core1_eirq_o (intr_tlul_mailbox_smc_eirq), |
| |
| // Inter-module signals |
| .core0_tl_i(tlul_mailbox_sec_tl_req), |
| .core0_tl_o(tlul_mailbox_sec_tl_rsp), |
| |
| .core1_tl_i(tlul_mailbox_smc_tl_req), |
| .core1_tl_o(tlul_mailbox_smc_tl_rsp), |
| |
| .test_i (1'b0), |
| |
| // Clock and reset connections |
| .clk_i (clkmgr_aon_clocks.clk_main_infra), |
| .rst_ni (rstmgr_aon_resets.rst_lc_n[rstmgr_pkg::Domain0Sel]) |
| ); |
| ml_top u_ml_top ( |
| |
| // Interrupt |
| .intr_host_req_o (intr_ml_top_host_req), |
| .intr_finish_o (intr_ml_top_finish), |
| .intr_fault_o (intr_ml_top_fault), |
| |
| // Inter-module signals |
| .isp_cvalid_i(isp_wrapper_isp_cvalid), |
| .isp_cready_o(isp_wrapper_isp_cready), |
| .isp_cwrite_i(isp_wrapper_isp_cwrite), |
| .isp_caddr_i(isp_wrapper_isp_caddr), |
| .isp_wdata_i(isp_wrapper_isp_wdata), |
| .isp_wmask_i(isp_wrapper_isp_wmask), |
| .core_tl_i(ml_top_core_tl_req), |
| .core_tl_o(ml_top_core_tl_rsp), |
| .dmem_tl_i(ml_top_dmem_tl_req), |
| .dmem_tl_o(ml_top_dmem_tl_rsp), |
| |
| // Clock and reset connections |
| .clk_i (clkmgr_aon_clocks.clk_ml_peri), |
| .rst_ni (rstmgr_aon_resets.rst_ml_n[rstmgr_pkg::Domain0Sel]) |
| ); |
| spi_host #( |
| .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[69:69]) |
| ) u_spi_host2 ( |
| |
| // Input |
| .cio_sd_i (cio_spi_host2_sd_p2d), |
| |
| // Output |
| .cio_sck_o (cio_spi_host2_sck_d2p), |
| .cio_sck_en_o (cio_spi_host2_sck_en_d2p), |
| .cio_csb_o (cio_spi_host2_csb_d2p), |
| .cio_csb_en_o (cio_spi_host2_csb_en_d2p), |
| .cio_sd_o (cio_spi_host2_sd_d2p), |
| .cio_sd_en_o (cio_spi_host2_sd_en_d2p), |
| |
| // Interrupt |
| .intr_error_o (intr_spi_host2_error), |
| .intr_spi_event_o (intr_spi_host2_spi_event), |
| // [69]: fatal_fault |
| .alert_tx_o ( alert_tx[69:69] ), |
| .alert_rx_i ( alert_rx[69:69] ), |
| |
| // Inter-module signals |
| .passthrough_i(spi_device_pkg::PASSTHROUGH_REQ_DEFAULT), |
| .passthrough_o(), |
| .tl_i(spi_host2_tl_req), |
| .tl_o(spi_host2_tl_rsp), |
| |
| // Clock and reset connections |
| .clk_i (clkmgr_aon_clocks.clk_io_peri), |
| .rst_ni (rstmgr_aon_resets.rst_spi_host2_n[rstmgr_pkg::Domain0Sel]) |
| ); |
| rv_timer #( |
| .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[70:70]) |
| ) u_rv_timer_smc2 ( |
| |
| // Interrupt |
| .intr_timer_expired_hart0_timer0_o (intr_rv_timer_smc2_timer_expired_hart0_timer0), |
| // [70]: fatal_fault |
| .alert_tx_o ( alert_tx[70:70] ), |
| .alert_rx_i ( alert_rx[70:70] ), |
| |
| // Inter-module signals |
| .tl_i(rv_timer_smc2_tl_req), |
| .tl_o(rv_timer_smc2_tl_rsp), |
| |
| // Clock and reset connections |
| .clk_i (clkmgr_aon_clocks.clk_io_div4_timers), |
| .rst_ni (rstmgr_aon_resets.rst_sys_io_div4_n[rstmgr_pkg::Domain0Sel]) |
| ); |
| i2s u_i2s0 ( |
| |
| // Input |
| .cio_rx_sd_i (cio_i2s0_rx_sd_p2d), |
| |
| // Output |
| .cio_rx_sclk_o (cio_i2s0_rx_sclk_d2p), |
| .cio_rx_sclk_en_o (cio_i2s0_rx_sclk_en_d2p), |
| .cio_rx_ws_o (cio_i2s0_rx_ws_d2p), |
| .cio_rx_ws_en_o (cio_i2s0_rx_ws_en_d2p), |
| .cio_tx_sclk_o (cio_i2s0_tx_sclk_d2p), |
| .cio_tx_sclk_en_o (cio_i2s0_tx_sclk_en_d2p), |
| .cio_tx_ws_o (cio_i2s0_tx_ws_d2p), |
| .cio_tx_ws_en_o (cio_i2s0_tx_ws_en_d2p), |
| .cio_tx_sd_o (cio_i2s0_tx_sd_d2p), |
| .cio_tx_sd_en_o (cio_i2s0_tx_sd_en_d2p), |
| |
| // Interrupt |
| .intr_tx_watermark_o (intr_i2s0_tx_watermark), |
| .intr_rx_watermark_o (intr_i2s0_rx_watermark), |
| .intr_tx_empty_o (intr_i2s0_tx_empty), |
| .intr_rx_overflow_o (intr_i2s0_rx_overflow), |
| |
| // Inter-module signals |
| .tl_i(i2s0_tl_req), |
| .tl_o(i2s0_tl_rsp), |
| |
| // Clock and reset connections |
| .clk_i (clkmgr_aon_clocks.clk_io_div4_peri), |
| .clk_audio_i (clkmgr_aon_clocks.clk_audio_peri), |
| .rst_ni (rstmgr_aon_resets.rst_sys_io_div4_n[rstmgr_pkg::Domain0Sel]) |
| ); |
| rv_core_smc #( |
| .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[74:71]), |
| .RndCnstLfsrSeed(RndCnstRvCoreIbexSmcLfsrSeed), |
| .RndCnstLfsrPerm(RndCnstRvCoreIbexSmcLfsrPerm), |
| .RndCnstSmcKeyDefault(RndCnstRvCoreIbexSmcSmcKeyDefault), |
| .RndCnstSmcNonceDefault(RndCnstRvCoreIbexSmcSmcNonceDefault), |
| .PMPEnable(RvCoreIbexSmcPMPEnable), |
| .PMPGranularity(RvCoreIbexSmcPMPGranularity), |
| .PMPNumRegions(RvCoreIbexSmcPMPNumRegions), |
| .MHPMCounterNum(RvCoreIbexSmcMHPMCounterNum), |
| .MHPMCounterWidth(RvCoreIbexSmcMHPMCounterWidth), |
| .RV32E(RvCoreIbexSmcRV32E), |
| .RV32M(RvCoreIbexSmcRV32M), |
| .RV32B(RvCoreIbexSmcRV32B), |
| .RV32A(RvCoreIbexSmcRV32A), |
| .RegFile(RvCoreIbexSmcRegFile), |
| .BranchTargetALU(RvCoreIbexSmcBranchTargetALU), |
| .WritebackStage(RvCoreIbexSmcWritebackStage), |
| .ICache(RvCoreIbexSmcICache), |
| .ICacheECC(RvCoreIbexSmcICacheECC), |
| .ICacheScramble(RvCoreIbexSmcICacheScramble), |
| .BranchPredictor(RvCoreIbexSmcBranchPredictor), |
| .DbgTriggerEn(RvCoreIbexSmcDbgTriggerEn), |
| .DbgHwBreakNum(RvCoreIbexSmcDbgHwBreakNum), |
| .SecureSmc(RvCoreIbexSmcSecureSmc), |
| .DmHaltAddr(RvCoreIbexSmcDmHaltAddr), |
| .DmExceptionAddr(RvCoreIbexSmcDmExceptionAddr), |
| .PipeLine(RvCoreIbexSmcPipeLine), |
| .ITLBEntries(RvCoreIbexSmcITLBEntries), |
| .DTLBEntries(RvCoreIbexSmcDTLBEntries), |
| .ASIDWidth(RvCoreIbexSmcASIDWidth) |
| ) u_rv_core_ibex_smc ( |
| // [71]: fatal_sw_err |
| // [72]: recov_sw_err |
| // [73]: fatal_hw_err |
| // [74]: recov_hw_err |
| .alert_tx_o ( alert_tx[74:71] ), |
| .alert_rx_i ( alert_rx[74:71] ), |
| |
| // Inter-module signals |
| .rst_cpu_n_o(), |
| .ram_cfg_i(ast_ram_1p_cfg), |
| .hart_id_i(rv_core_ibex_smc_hart_id), |
| .boot_addr_i(rv_core_ibex_smc_boot_addr), |
| .irq_software_i(rv_plic_smc_msip), |
| .irq_timer_i(rv_core_ibex_smc_irq_timer), |
| .irq_external_i(rv_plic_smc_irq), |
| .esc_tx_i(prim_esc_pkg::ESC_TX_DEFAULT), |
| .esc_rx_o(), |
| .debug_req_i(rv_dm_debug_req[1]), |
| .crash_dump_o(), |
| .lc_cpu_en_i(lc_ctrl_lc_cpu_en), |
| .pwrmgr_cpu_en_i(rv_core_ibex_smc_pwrmgr_cpu_en), |
| .pwrmgr_o(), |
| .nmi_wdog_i('0), |
| .edn_o(), |
| .edn_i(edn_pkg::EDN_RSP_DEFAULT), |
| .icache_otp_key_o(), |
| .icache_otp_key_i(otp_ctrl_pkg::SRAM_OTP_KEY_RSP_DEFAULT), |
| .fpga_info_i('0), |
| .corei_tl_h_o(smc_tl_rv_core_ibex_smc__corei_req), |
| .corei_tl_h_i(smc_tl_rv_core_ibex_smc__corei_rsp), |
| .cored_tl_h_o(smc_tl_rv_core_ibex_smc__cored_req), |
| .cored_tl_h_i(smc_tl_rv_core_ibex_smc__cored_rsp), |
| .cfg_tl_d_i(rv_core_ibex_smc_cfg_tl_d_req), |
| .cfg_tl_d_o(rv_core_ibex_smc_cfg_tl_d_rsp), |
| .scanmode_i, |
| .scan_rst_ni, |
| |
| // Clock and reset connections |
| .clk_i (clkmgr_aon_clocks.clk_smc_peri), |
| .clk_esc_i (clkmgr_aon_clocks.clk_io_div4_peri), |
| .rst_ni (rstmgr_aon_resets.rst_smc_n[rstmgr_pkg::Domain0Sel]), |
| .rst_esc_ni (rstmgr_aon_resets.rst_lc_io_div4_n[rstmgr_pkg::Domain0Sel]) |
| ); |
| |
| // security core interrupt assignments |
| assign sec_intr_vector = { |
| intr_tlul_mailbox_sec_eirq, // IDs [189 +: 1] |
| intr_tlul_mailbox_sec_rtirq, // IDs [188 +: 1] |
| intr_tlul_mailbox_sec_wtirq, // IDs [187 +: 1] |
| intr_dma0_reader_done, // IDs [186 +: 1] |
| intr_dma0_writer_done, // IDs [185 +: 1] |
| intr_edn1_edn_fatal_err, // IDs [184 +: 1] |
| intr_edn1_edn_cmd_req_done, // IDs [183 +: 1] |
| intr_edn0_edn_fatal_err, // IDs [182 +: 1] |
| intr_edn0_edn_cmd_req_done, // IDs [181 +: 1] |
| intr_entropy_src_es_fatal_err, // IDs [180 +: 1] |
| intr_entropy_src_es_observe_fifo_ready, // IDs [179 +: 1] |
| intr_entropy_src_es_health_test_failed, // IDs [178 +: 1] |
| intr_entropy_src_es_entropy_valid, // IDs [177 +: 1] |
| intr_csrng_cs_fatal_err, // IDs [176 +: 1] |
| intr_csrng_cs_hw_inst_exc, // IDs [175 +: 1] |
| intr_csrng_cs_entropy_req, // IDs [174 +: 1] |
| intr_csrng_cs_cmd_req_done, // IDs [173 +: 1] |
| intr_keymgr_op_done, // IDs [172 +: 1] |
| intr_otbn_done, // IDs [171 +: 1] |
| intr_kmac_kmac_err, // IDs [170 +: 1] |
| intr_kmac_fifo_empty, // IDs [169 +: 1] |
| intr_kmac_kmac_done, // IDs [168 +: 1] |
| intr_hmac_hmac_err, // IDs [167 +: 1] |
| intr_hmac_fifo_empty, // IDs [166 +: 1] |
| intr_hmac_hmac_done, // IDs [165 +: 1] |
| intr_flash_ctrl_corr_err, // IDs [164 +: 1] |
| intr_flash_ctrl_op_done, // IDs [163 +: 1] |
| intr_flash_ctrl_rd_lvl, // IDs [162 +: 1] |
| intr_flash_ctrl_rd_full, // IDs [161 +: 1] |
| intr_flash_ctrl_prog_lvl, // IDs [160 +: 1] |
| intr_flash_ctrl_prog_empty, // IDs [159 +: 1] |
| intr_sensor_ctrl_init_status_change, // IDs [158 +: 1] |
| intr_sensor_ctrl_io_status_change, // IDs [157 +: 1] |
| intr_aon_timer_aon_wdog_timer_bark, // IDs [156 +: 1] |
| intr_aon_timer_aon_wkup_timer_expired, // IDs [155 +: 1] |
| intr_adc_ctrl_aon_match_done, // IDs [154 +: 1] |
| intr_sysrst_ctrl_aon_event_detected, // IDs [153 +: 1] |
| intr_pwrmgr_aon_wakeup, // IDs [152 +: 1] |
| intr_usbdev_link_out_err, // IDs [151 +: 1] |
| intr_usbdev_powered, // IDs [150 +: 1] |
| intr_usbdev_frame, // IDs [149 +: 1] |
| intr_usbdev_rx_bitstuff_err, // IDs [148 +: 1] |
| intr_usbdev_rx_pid_err, // IDs [147 +: 1] |
| intr_usbdev_rx_crc_err, // IDs [146 +: 1] |
| intr_usbdev_link_in_err, // IDs [145 +: 1] |
| intr_usbdev_av_overflow, // IDs [144 +: 1] |
| intr_usbdev_rx_full, // IDs [143 +: 1] |
| intr_usbdev_av_empty, // IDs [142 +: 1] |
| intr_usbdev_link_resume, // IDs [141 +: 1] |
| intr_usbdev_link_suspend, // IDs [140 +: 1] |
| intr_usbdev_link_reset, // IDs [139 +: 1] |
| intr_usbdev_host_lost, // IDs [138 +: 1] |
| intr_usbdev_disconnected, // IDs [137 +: 1] |
| intr_usbdev_pkt_sent, // IDs [136 +: 1] |
| intr_usbdev_pkt_received, // IDs [135 +: 1] |
| intr_spi_host1_spi_event, // IDs [134 +: 1] |
| intr_spi_host1_error, // IDs [133 +: 1] |
| intr_spi_host0_spi_event, // IDs [132 +: 1] |
| intr_spi_host0_error, // IDs [131 +: 1] |
| intr_alert_handler_classd, // IDs [130 +: 1] |
| intr_alert_handler_classc, // IDs [129 +: 1] |
| intr_alert_handler_classb, // IDs [128 +: 1] |
| intr_alert_handler_classa, // IDs [127 +: 1] |
| intr_otp_ctrl_otp_error, // IDs [126 +: 1] |
| intr_otp_ctrl_otp_operation_done, // IDs [125 +: 1] |
| intr_rv_timer_timer_expired_hart0_timer0, // IDs [124 +: 1] |
| intr_pattgen_done_ch1, // IDs [123 +: 1] |
| intr_pattgen_done_ch0, // IDs [122 +: 1] |
| intr_i2c2_host_timeout, // IDs [121 +: 1] |
| intr_i2c2_unexp_stop, // IDs [120 +: 1] |
| intr_i2c2_acq_full, // IDs [119 +: 1] |
| intr_i2c2_tx_overflow, // IDs [118 +: 1] |
| intr_i2c2_tx_stretch, // IDs [117 +: 1] |
| intr_i2c2_cmd_complete, // IDs [116 +: 1] |
| intr_i2c2_sda_unstable, // IDs [115 +: 1] |
| intr_i2c2_stretch_timeout, // IDs [114 +: 1] |
| intr_i2c2_sda_interference, // IDs [113 +: 1] |
| intr_i2c2_scl_interference, // IDs [112 +: 1] |
| intr_i2c2_nak, // IDs [111 +: 1] |
| intr_i2c2_rx_overflow, // IDs [110 +: 1] |
| intr_i2c2_fmt_overflow, // IDs [109 +: 1] |
| intr_i2c2_rx_threshold, // IDs [108 +: 1] |
| intr_i2c2_fmt_threshold, // IDs [107 +: 1] |
| intr_i2c1_host_timeout, // IDs [106 +: 1] |
| intr_i2c1_unexp_stop, // IDs [105 +: 1] |
| intr_i2c1_acq_full, // IDs [104 +: 1] |
| intr_i2c1_tx_overflow, // IDs [103 +: 1] |
| intr_i2c1_tx_stretch, // IDs [102 +: 1] |
| intr_i2c1_cmd_complete, // IDs [101 +: 1] |
| intr_i2c1_sda_unstable, // IDs [100 +: 1] |
| intr_i2c1_stretch_timeout, // IDs [99 +: 1] |
| intr_i2c1_sda_interference, // IDs [98 +: 1] |
| intr_i2c1_scl_interference, // IDs [97 +: 1] |
| intr_i2c1_nak, // IDs [96 +: 1] |
| intr_i2c1_rx_overflow, // IDs [95 +: 1] |
| intr_i2c1_fmt_overflow, // IDs [94 +: 1] |
| intr_i2c1_rx_threshold, // IDs [93 +: 1] |
| intr_i2c1_fmt_threshold, // IDs [92 +: 1] |
| intr_i2c0_host_timeout, // IDs [91 +: 1] |
| intr_i2c0_unexp_stop, // IDs [90 +: 1] |
| intr_i2c0_acq_full, // IDs [89 +: 1] |
| intr_i2c0_tx_overflow, // IDs [88 +: 1] |
| intr_i2c0_tx_stretch, // IDs [87 +: 1] |
| intr_i2c0_cmd_complete, // IDs [86 +: 1] |
| intr_i2c0_sda_unstable, // IDs [85 +: 1] |
| intr_i2c0_stretch_timeout, // IDs [84 +: 1] |
| intr_i2c0_sda_interference, // IDs [83 +: 1] |
| intr_i2c0_scl_interference, // IDs [82 +: 1] |
| intr_i2c0_nak, // IDs [81 +: 1] |
| intr_i2c0_rx_overflow, // IDs [80 +: 1] |
| intr_i2c0_fmt_overflow, // IDs [79 +: 1] |
| intr_i2c0_rx_threshold, // IDs [78 +: 1] |
| intr_i2c0_fmt_threshold, // IDs [77 +: 1] |
| intr_spi_device_tpm_header_not_empty, // IDs [76 +: 1] |
| intr_spi_device_readbuf_flip, // IDs [75 +: 1] |
| intr_spi_device_readbuf_watermark, // IDs [74 +: 1] |
| intr_spi_device_upload_payload_overflow, // IDs [73 +: 1] |
| intr_spi_device_upload_payload_not_empty, // IDs [72 +: 1] |
| intr_spi_device_upload_cmdfifo_not_empty, // IDs [71 +: 1] |
| intr_spi_device_generic_tx_underflow, // IDs [70 +: 1] |
| intr_spi_device_generic_rx_overflow, // IDs [69 +: 1] |
| intr_spi_device_generic_rx_error, // IDs [68 +: 1] |
| intr_spi_device_generic_tx_watermark, // IDs [67 +: 1] |
| intr_spi_device_generic_rx_watermark, // IDs [66 +: 1] |
| intr_spi_device_generic_rx_full, // IDs [65 +: 1] |
| intr_gpio_gpio, // IDs [33 +: 32] |
| intr_uart3_rx_parity_err, // IDs [32 +: 1] |
| intr_uart3_rx_timeout, // IDs [31 +: 1] |
| intr_uart3_rx_break_err, // IDs [30 +: 1] |
| intr_uart3_rx_frame_err, // IDs [29 +: 1] |
| intr_uart3_rx_overflow, // IDs [28 +: 1] |
| intr_uart3_tx_empty, // IDs [27 +: 1] |
| intr_uart3_rx_watermark, // IDs [26 +: 1] |
| intr_uart3_tx_watermark, // IDs [25 +: 1] |
| intr_uart2_rx_parity_err, // IDs [24 +: 1] |
| intr_uart2_rx_timeout, // IDs [23 +: 1] |
| intr_uart2_rx_break_err, // IDs [22 +: 1] |
| intr_uart2_rx_frame_err, // IDs [21 +: 1] |
| intr_uart2_rx_overflow, // IDs [20 +: 1] |
| intr_uart2_tx_empty, // IDs [19 +: 1] |
| intr_uart2_rx_watermark, // IDs [18 +: 1] |
| intr_uart2_tx_watermark, // IDs [17 +: 1] |
| intr_uart1_rx_parity_err, // IDs [16 +: 1] |
| intr_uart1_rx_timeout, // IDs [15 +: 1] |
| intr_uart1_rx_break_err, // IDs [14 +: 1] |
| intr_uart1_rx_frame_err, // IDs [13 +: 1] |
| intr_uart1_rx_overflow, // IDs [12 +: 1] |
| intr_uart1_tx_empty, // IDs [11 +: 1] |
| intr_uart1_rx_watermark, // IDs [10 +: 1] |
| intr_uart1_tx_watermark, // IDs [9 +: 1] |
| intr_uart0_rx_parity_err, // IDs [8 +: 1] |
| intr_uart0_rx_timeout, // IDs [7 +: 1] |
| intr_uart0_rx_break_err, // IDs [6 +: 1] |
| intr_uart0_rx_frame_err, // IDs [5 +: 1] |
| intr_uart0_rx_overflow, // IDs [4 +: 1] |
| intr_uart0_tx_empty, // IDs [3 +: 1] |
| intr_uart0_rx_watermark, // IDs [2 +: 1] |
| intr_uart0_tx_watermark, // IDs [1 +: 1] |
| 1'b 0 // ID [0 +: 1] is a special case and tied to zero. |
| }; |
| |
| // smc core interrupt assignments |
| assign smc_intr_vector = { |
| intr_i2s0_rx_overflow, // IDs [42 +: 1] |
| intr_i2s0_tx_empty, // IDs [41 +: 1] |
| intr_i2s0_rx_watermark, // IDs [40 +: 1] |
| intr_i2s0_tx_watermark, // IDs [39 +: 1] |
| intr_rv_timer_smc2_timer_expired_hart0_timer0, // IDs [38 +: 1] |
| intr_spi_host2_spi_event, // IDs [37 +: 1] |
| intr_spi_host2_error, // IDs [36 +: 1] |
| intr_ml_top_fault, // IDs [35 +: 1] |
| intr_ml_top_finish, // IDs [34 +: 1] |
| intr_ml_top_host_req, // IDs [33 +: 1] |
| intr_tlul_mailbox_smc_eirq, // IDs [32 +: 1] |
| intr_tlul_mailbox_smc_rtirq, // IDs [31 +: 1] |
| intr_tlul_mailbox_smc_wtirq, // IDs [30 +: 1] |
| intr_dma_smc_reader_done, // IDs [29 +: 1] |
| intr_dma_smc_writer_done, // IDs [28 +: 1] |
| intr_isp_wrapper_mi, // IDs [27 +: 1] |
| intr_isp_wrapper_isp, // IDs [26 +: 1] |
| intr_cam_ctrl_cam_motion_detect, // IDs [25 +: 1] |
| intr_cam_i2c_host_timeout, // IDs [24 +: 1] |
| intr_cam_i2c_unexp_stop, // IDs [23 +: 1] |
| intr_cam_i2c_acq_full, // IDs [22 +: 1] |
| intr_cam_i2c_tx_overflow, // IDs [21 +: 1] |
| intr_cam_i2c_tx_stretch, // IDs [20 +: 1] |
| intr_cam_i2c_cmd_complete, // IDs [19 +: 1] |
| intr_cam_i2c_sda_unstable, // IDs [18 +: 1] |
| intr_cam_i2c_stretch_timeout, // IDs [17 +: 1] |
| intr_cam_i2c_sda_interference, // IDs [16 +: 1] |
| intr_cam_i2c_scl_interference, // IDs [15 +: 1] |
| intr_cam_i2c_nak, // IDs [14 +: 1] |
| intr_cam_i2c_rx_overflow, // IDs [13 +: 1] |
| intr_cam_i2c_fmt_overflow, // IDs [12 +: 1] |
| intr_cam_i2c_rx_threshold, // IDs [11 +: 1] |
| intr_cam_i2c_fmt_threshold, // IDs [10 +: 1] |
| intr_rv_timer_smc_timer_expired_hart0_timer0, // IDs [9 +: 1] |
| intr_smc_uart_rx_parity_err, // IDs [8 +: 1] |
| intr_smc_uart_rx_timeout, // IDs [7 +: 1] |
| intr_smc_uart_rx_break_err, // IDs [6 +: 1] |
| intr_smc_uart_rx_frame_err, // IDs [5 +: 1] |
| intr_smc_uart_rx_overflow, // IDs [4 +: 1] |
| intr_smc_uart_tx_empty, // IDs [3 +: 1] |
| intr_smc_uart_rx_watermark, // IDs [2 +: 1] |
| intr_smc_uart_tx_watermark, // IDs [1 +: 1] |
| 1'b 0 // ID [0 +: 1] is a special case and tied to zero. |
| }; |
| |
| |
| // TL-UL Crossbar |
| xbar_main u_xbar_main ( |
| .clk_main_i (clkmgr_aon_clocks.clk_main_infra), |
| .clk_fixed_i (clkmgr_aon_clocks.clk_io_div4_infra), |
| .clk_usb_i (clkmgr_aon_clocks.clk_usb_infra), |
| .clk_spi_host0_i (clkmgr_aon_clocks.clk_io_infra), |
| .clk_spi_host1_i (clkmgr_aon_clocks.clk_io_infra), |
| .clk_smc_i (clkmgr_aon_clocks.clk_smc_infra), |
| .rst_main_ni (rstmgr_aon_resets.rst_lc_n[rstmgr_pkg::Domain0Sel]), |
| .rst_fixed_ni (rstmgr_aon_resets.rst_lc_io_div4_n[rstmgr_pkg::Domain0Sel]), |
| .rst_usb_ni (rstmgr_aon_resets.rst_lc_usb_n[rstmgr_pkg::Domain0Sel]), |
| .rst_spi_host0_ni (rstmgr_aon_resets.rst_lc_io_n[rstmgr_pkg::Domain0Sel]), |
| .rst_spi_host1_ni (rstmgr_aon_resets.rst_lc_io_n[rstmgr_pkg::Domain0Sel]), |
| .rst_smc_ni (rstmgr_aon_resets.rst_smc_n[rstmgr_pkg::Domain0Sel]), |
| |
| // port: tl_rv_core_ibex_sec__corei |
| .tl_rv_core_ibex_sec__corei_i(main_tl_rv_core_ibex_sec__corei_req), |
| .tl_rv_core_ibex_sec__corei_o(main_tl_rv_core_ibex_sec__corei_rsp), |
| |
| // port: tl_rv_core_ibex_sec__cored |
| .tl_rv_core_ibex_sec__cored_i(main_tl_rv_core_ibex_sec__cored_req), |
| .tl_rv_core_ibex_sec__cored_o(main_tl_rv_core_ibex_sec__cored_rsp), |
| |
| // port: tl_rv_dm__sba |
| .tl_rv_dm__sba_i(main_tl_rv_dm__sba_req), |
| .tl_rv_dm__sba_o(main_tl_rv_dm__sba_rsp), |
| |
| // port: tl_dma0__reader |
| .tl_dma0__reader_i(main_tl_dma0__reader_req), |
| .tl_dma0__reader_o(main_tl_dma0__reader_rsp), |
| |
| // port: tl_dma0__writer |
| .tl_dma0__writer_i(main_tl_dma0__writer_req), |
| .tl_dma0__writer_o(main_tl_dma0__writer_rsp), |
| |
| // port: tl_dma0 |
| .tl_dma0_o(dma0_tl_d_req), |
| .tl_dma0_i(dma0_tl_d_rsp), |
| |
| // port: tl_rom_ctrl__rom |
| .tl_rom_ctrl__rom_o(rom_ctrl_rom_tl_req), |
| .tl_rom_ctrl__rom_i(rom_ctrl_rom_tl_rsp), |
| |
| // port: tl_rom_ctrl__regs |
| .tl_rom_ctrl__regs_o(rom_ctrl_regs_tl_req), |
| .tl_rom_ctrl__regs_i(rom_ctrl_regs_tl_rsp), |
| |
| // port: tl_peri |
| .tl_peri_o(main_tl_peri_req), |
| .tl_peri_i(main_tl_peri_rsp), |
| |
| // port: tl_spi_host0 |
| .tl_spi_host0_o(spi_host0_tl_req), |
| .tl_spi_host0_i(spi_host0_tl_rsp), |
| |
| // port: tl_spi_host1 |
| .tl_spi_host1_o(spi_host1_tl_req), |
| .tl_spi_host1_i(spi_host1_tl_rsp), |
| |
| // port: tl_usbdev |
| .tl_usbdev_o(usbdev_tl_req), |
| .tl_usbdev_i(usbdev_tl_rsp), |
| |
| // port: tl_flash_ctrl__core |
| .tl_flash_ctrl__core_o(flash_ctrl_core_tl_req), |
| .tl_flash_ctrl__core_i(flash_ctrl_core_tl_rsp), |
| |
| // port: tl_flash_ctrl__prim |
| .tl_flash_ctrl__prim_o(flash_ctrl_prim_tl_req), |
| .tl_flash_ctrl__prim_i(flash_ctrl_prim_tl_rsp), |
| |
| // port: tl_flash_ctrl__mem |
| .tl_flash_ctrl__mem_o(flash_ctrl_mem_tl_req), |
| .tl_flash_ctrl__mem_i(flash_ctrl_mem_tl_rsp), |
| |
| // port: tl_hmac |
| .tl_hmac_o(hmac_tl_req), |
| .tl_hmac_i(hmac_tl_rsp), |
| |
| // port: tl_kmac |
| .tl_kmac_o(kmac_tl_req), |
| .tl_kmac_i(kmac_tl_rsp), |
| |
| // port: tl_aes |
| .tl_aes_o(aes_tl_req), |
| .tl_aes_i(aes_tl_rsp), |
| |
| // port: tl_entropy_src |
| .tl_entropy_src_o(entropy_src_tl_req), |
| .tl_entropy_src_i(entropy_src_tl_rsp), |
| |
| // port: tl_csrng |
| .tl_csrng_o(csrng_tl_req), |
| .tl_csrng_i(csrng_tl_rsp), |
| |
| // port: tl_edn0 |
| .tl_edn0_o(edn0_tl_req), |
| .tl_edn0_i(edn0_tl_rsp), |
| |
| // port: tl_edn1 |
| .tl_edn1_o(edn1_tl_req), |
| .tl_edn1_i(edn1_tl_rsp), |
| |
| // port: tl_rv_plic |
| .tl_rv_plic_o(rv_plic_tl_req), |
| .tl_rv_plic_i(rv_plic_tl_rsp), |
| |
| // port: tl_otbn |
| .tl_otbn_o(otbn_tl_req), |
| .tl_otbn_i(otbn_tl_rsp), |
| |
| // port: tl_keymgr |
| .tl_keymgr_o(keymgr_tl_req), |
| .tl_keymgr_i(keymgr_tl_rsp), |
| |
| // port: tl_rv_core_ibex_sec__cfg |
| .tl_rv_core_ibex_sec__cfg_o(rv_core_ibex_sec_cfg_tl_d_req), |
| .tl_rv_core_ibex_sec__cfg_i(rv_core_ibex_sec_cfg_tl_d_rsp), |
| |
| // port: tl_sram_ctrl_main__regs |
| .tl_sram_ctrl_main__regs_o(sram_ctrl_main_regs_tl_req), |
| .tl_sram_ctrl_main__regs_i(sram_ctrl_main_regs_tl_rsp), |
| |
| // port: tl_sram_ctrl_main__ram |
| .tl_sram_ctrl_main__ram_o(sram_ctrl_main_ram_tl_req), |
| .tl_sram_ctrl_main__ram_i(sram_ctrl_main_ram_tl_rsp), |
| |
| // port: tl_tlul_mailbox_sec |
| .tl_tlul_mailbox_sec_o(tlul_mailbox_sec_tl_req), |
| .tl_tlul_mailbox_sec_i(tlul_mailbox_sec_tl_rsp), |
| |
| // port: tl_smc |
| .tl_smc_o(main_tl_smc_req), |
| .tl_smc_i(main_tl_smc_rsp), |
| |
| // port: tl_dbg |
| .tl_dbg_o(main_tl_dbg_req), |
| .tl_dbg_i(main_tl_dbg_rsp), |
| |
| |
| .scanmode_i |
| ); |
| xbar_peri u_xbar_peri ( |
| .clk_peri_i (clkmgr_aon_clocks.clk_io_div4_infra), |
| .rst_peri_ni (rstmgr_aon_resets.rst_lc_io_div4_n[rstmgr_pkg::Domain0Sel]), |
| |
| // port: tl_main |
| .tl_main_i(main_tl_peri_req), |
| .tl_main_o(main_tl_peri_rsp), |
| |
| // port: tl_uart0 |
| .tl_uart0_o(uart0_tl_req), |
| .tl_uart0_i(uart0_tl_rsp), |
| |
| // port: tl_uart1 |
| .tl_uart1_o(uart1_tl_req), |
| .tl_uart1_i(uart1_tl_rsp), |
| |
| // port: tl_uart2 |
| .tl_uart2_o(uart2_tl_req), |
| .tl_uart2_i(uart2_tl_rsp), |
| |
| // port: tl_uart3 |
| .tl_uart3_o(uart3_tl_req), |
| .tl_uart3_i(uart3_tl_rsp), |
| |
| // port: tl_i2c0 |
| .tl_i2c0_o(i2c0_tl_req), |
| .tl_i2c0_i(i2c0_tl_rsp), |
| |
| // port: tl_i2c1 |
| .tl_i2c1_o(i2c1_tl_req), |
| .tl_i2c1_i(i2c1_tl_rsp), |
| |
| // port: tl_i2c2 |
| .tl_i2c2_o(i2c2_tl_req), |
| .tl_i2c2_i(i2c2_tl_rsp), |
| |
| // port: tl_pattgen |
| .tl_pattgen_o(pattgen_tl_req), |
| .tl_pattgen_i(pattgen_tl_rsp), |
| |
| // port: tl_pwm_aon |
| .tl_pwm_aon_o(pwm_aon_tl_req), |
| .tl_pwm_aon_i(pwm_aon_tl_rsp), |
| |
| // port: tl_gpio |
| .tl_gpio_o(gpio_tl_req), |
| .tl_gpio_i(gpio_tl_rsp), |
| |
| // port: tl_spi_device |
| .tl_spi_device_o(spi_device_tl_req), |
| .tl_spi_device_i(spi_device_tl_rsp), |
| |
| // port: tl_rv_timer |
| .tl_rv_timer_o(rv_timer_tl_req), |
| .tl_rv_timer_i(rv_timer_tl_rsp), |
| |
| // port: tl_pwrmgr_aon |
| .tl_pwrmgr_aon_o(pwrmgr_aon_tl_req), |
| .tl_pwrmgr_aon_i(pwrmgr_aon_tl_rsp), |
| |
| // port: tl_rstmgr_aon |
| .tl_rstmgr_aon_o(rstmgr_aon_tl_req), |
| .tl_rstmgr_aon_i(rstmgr_aon_tl_rsp), |
| |
| // port: tl_clkmgr_aon |
| .tl_clkmgr_aon_o(clkmgr_aon_tl_req), |
| .tl_clkmgr_aon_i(clkmgr_aon_tl_rsp), |
| |
| // port: tl_pinmux_aon |
| .tl_pinmux_aon_o(pinmux_aon_tl_req), |
| .tl_pinmux_aon_i(pinmux_aon_tl_rsp), |
| |
| // port: tl_otp_ctrl__core |
| .tl_otp_ctrl__core_o(otp_ctrl_core_tl_req), |
| .tl_otp_ctrl__core_i(otp_ctrl_core_tl_rsp), |
| |
| // port: tl_otp_ctrl__prim |
| .tl_otp_ctrl__prim_o(otp_ctrl_prim_tl_req), |
| .tl_otp_ctrl__prim_i(otp_ctrl_prim_tl_rsp), |
| |
| // port: tl_lc_ctrl |
| .tl_lc_ctrl_o(lc_ctrl_tl_req), |
| .tl_lc_ctrl_i(lc_ctrl_tl_rsp), |
| |
| // port: tl_sensor_ctrl |
| .tl_sensor_ctrl_o(sensor_ctrl_tl_req), |
| .tl_sensor_ctrl_i(sensor_ctrl_tl_rsp), |
| |
| // port: tl_alert_handler |
| .tl_alert_handler_o(alert_handler_tl_req), |
| .tl_alert_handler_i(alert_handler_tl_rsp), |
| |
| // port: tl_sram_ctrl_ret_aon__regs |
| .tl_sram_ctrl_ret_aon__regs_o(sram_ctrl_ret_aon_regs_tl_req), |
| .tl_sram_ctrl_ret_aon__regs_i(sram_ctrl_ret_aon_regs_tl_rsp), |
| |
| // port: tl_sram_ctrl_ret_aon__ram |
| .tl_sram_ctrl_ret_aon__ram_o(sram_ctrl_ret_aon_ram_tl_req), |
| .tl_sram_ctrl_ret_aon__ram_i(sram_ctrl_ret_aon_ram_tl_rsp), |
| |
| // port: tl_aon_timer_aon |
| .tl_aon_timer_aon_o(aon_timer_aon_tl_req), |
| .tl_aon_timer_aon_i(aon_timer_aon_tl_rsp), |
| |
| // port: tl_sysrst_ctrl_aon |
| .tl_sysrst_ctrl_aon_o(sysrst_ctrl_aon_tl_req), |
| .tl_sysrst_ctrl_aon_i(sysrst_ctrl_aon_tl_rsp), |
| |
| // port: tl_adc_ctrl_aon |
| .tl_adc_ctrl_aon_o(adc_ctrl_aon_tl_req), |
| .tl_adc_ctrl_aon_i(adc_ctrl_aon_tl_rsp), |
| |
| // port: tl_ast |
| .tl_ast_o(ast_tl_req_o), |
| .tl_ast_i(ast_tl_rsp_i), |
| |
| |
| .scanmode_i |
| ); |
| xbar_smc u_xbar_smc ( |
| .clk_smc_i (clkmgr_aon_clocks.clk_smc_infra), |
| .clk_peri_i (clkmgr_aon_clocks.clk_io_div4_infra), |
| .clk_spi_host2_i (clkmgr_aon_clocks.clk_io_infra), |
| .clk_ml_i (clkmgr_aon_clocks.clk_ml_infra), |
| .clk_video_i (clkmgr_aon_clocks.clk_video_infra), |
| .clk_audio_i (clkmgr_aon_clocks.clk_audio_infra), |
| .clk_main_i (clkmgr_aon_clocks.clk_main_infra), |
| .rst_smc_ni (rstmgr_aon_resets.rst_smc_n[rstmgr_pkg::Domain0Sel]), |
| .rst_peri_ni (rstmgr_aon_resets.rst_lc_io_div4_n[rstmgr_pkg::Domain0Sel]), |
| .rst_spi_host2_ni (rstmgr_aon_resets.rst_lc_io_n[rstmgr_pkg::Domain0Sel]), |
| .rst_ml_ni (rstmgr_aon_resets.rst_ml_n[rstmgr_pkg::Domain0Sel]), |
| .rst_video_ni (rstmgr_aon_resets.rst_video_n[rstmgr_pkg::Domain0Sel]), |
| .rst_audio_ni (rstmgr_aon_resets.rst_audio_n[rstmgr_pkg::Domain0Sel]), |
| .rst_main_ni (rstmgr_aon_resets.rst_lc_n[rstmgr_pkg::Domain0Sel]), |
| |
| // port: tl_main |
| .tl_main_i(main_tl_smc_req), |
| .tl_main_o(main_tl_smc_rsp), |
| |
| // port: tl_rv_core_ibex_smc__corei |
| .tl_rv_core_ibex_smc__corei_i(smc_tl_rv_core_ibex_smc__corei_req), |
| .tl_rv_core_ibex_smc__corei_o(smc_tl_rv_core_ibex_smc__corei_rsp), |
| |
| // port: tl_rv_core_ibex_smc__cored |
| .tl_rv_core_ibex_smc__cored_i(smc_tl_rv_core_ibex_smc__cored_req), |
| .tl_rv_core_ibex_smc__cored_o(smc_tl_rv_core_ibex_smc__cored_rsp), |
| |
| // port: tl_dma_smc__reader |
| .tl_dma_smc__reader_i(smc_tl_dma_smc__reader_req), |
| .tl_dma_smc__reader_o(smc_tl_dma_smc__reader_rsp), |
| |
| // port: tl_dma_smc__writer |
| .tl_dma_smc__writer_i(smc_tl_dma_smc__writer_req), |
| .tl_dma_smc__writer_o(smc_tl_dma_smc__writer_rsp), |
| |
| // port: tl_rv_plic_smc |
| .tl_rv_plic_smc_o(rv_plic_smc_tl_req), |
| .tl_rv_plic_smc_i(rv_plic_smc_tl_rsp), |
| |
| // port: tl_rv_core_ibex_smc__cfg |
| .tl_rv_core_ibex_smc__cfg_o(rv_core_ibex_smc_cfg_tl_d_req), |
| .tl_rv_core_ibex_smc__cfg_i(rv_core_ibex_smc_cfg_tl_d_rsp), |
| |
| // port: tl_ram_smc |
| .tl_ram_smc_o(ram_smc_tl_req), |
| .tl_ram_smc_i(ram_smc_tl_rsp), |
| |
| // port: tl_smc_uart |
| .tl_smc_uart_o(smc_uart_tl_req), |
| .tl_smc_uart_i(smc_uart_tl_rsp), |
| |
| // port: tl_rv_timer_smc |
| .tl_rv_timer_smc_o(rv_timer_smc_tl_req), |
| .tl_rv_timer_smc_i(rv_timer_smc_tl_rsp), |
| |
| // port: tl_tlul_mailbox_smc |
| .tl_tlul_mailbox_smc_o(tlul_mailbox_smc_tl_req), |
| .tl_tlul_mailbox_smc_i(tlul_mailbox_smc_tl_rsp), |
| |
| // port: tl_smc_ctrl |
| .tl_smc_ctrl_o(smc_ctrl_tl_req), |
| .tl_smc_ctrl_i(smc_ctrl_tl_rsp), |
| |
| // port: tl_cam_i2c |
| .tl_cam_i2c_o(cam_i2c_tl_req), |
| .tl_cam_i2c_i(cam_i2c_tl_rsp), |
| |
| // port: tl_cam_ctrl |
| .tl_cam_ctrl_o(cam_ctrl_tl_req), |
| .tl_cam_ctrl_i(cam_ctrl_tl_rsp), |
| |
| // port: tl_ml_top__dmem |
| .tl_ml_top__dmem_o(ml_top_dmem_tl_req), |
| .tl_ml_top__dmem_i(ml_top_dmem_tl_rsp), |
| |
| // port: tl_ml_top__core |
| .tl_ml_top__core_o(ml_top_core_tl_req), |
| .tl_ml_top__core_i(ml_top_core_tl_rsp), |
| |
| // port: tl_isp_wrapper |
| .tl_isp_wrapper_o(isp_wrapper_tl_req), |
| .tl_isp_wrapper_i(isp_wrapper_tl_rsp), |
| |
| // port: tl_dma_smc |
| .tl_dma_smc_o(dma_smc_tl_d_req), |
| .tl_dma_smc_i(dma_smc_tl_d_rsp), |
| |
| // port: tl_spi_host2 |
| .tl_spi_host2_o(spi_host2_tl_req), |
| .tl_spi_host2_i(spi_host2_tl_rsp), |
| |
| // port: tl_dbg |
| .tl_dbg_o(smc_tl_dbg_req), |
| .tl_dbg_i(smc_tl_dbg_rsp), |
| |
| // port: tl_rv_timer_smc2 |
| .tl_rv_timer_smc2_o(rv_timer_smc2_tl_req), |
| .tl_rv_timer_smc2_i(rv_timer_smc2_tl_rsp), |
| |
| // port: tl_i2s0 |
| .tl_i2s0_o(i2s0_tl_req), |
| .tl_i2s0_i(i2s0_tl_rsp), |
| |
| |
| .scanmode_i |
| ); |
| xbar_dbg u_xbar_dbg ( |
| .clk_main_i (clkmgr_aon_clocks.clk_main_infra), |
| .rst_main_ni (rstmgr_aon_resets.rst_lc_n[rstmgr_pkg::Domain0Sel]), |
| |
| // port: tl_main |
| .tl_main_i(main_tl_dbg_req), |
| .tl_main_o(main_tl_dbg_rsp), |
| |
| // port: tl_smc |
| .tl_smc_i(smc_tl_dbg_req), |
| .tl_smc_o(smc_tl_dbg_rsp), |
| |
| // port: tl_rv_dm__regs |
| .tl_rv_dm__regs_o(rv_dm_regs_tl_d_req), |
| .tl_rv_dm__regs_i(rv_dm_regs_tl_d_rsp), |
| |
| // port: tl_rv_dm__mem |
| .tl_rv_dm__mem_o(rv_dm_mem_tl_d_req), |
| .tl_rv_dm__mem_i(rv_dm_mem_tl_d_rsp), |
| |
| |
| .scanmode_i |
| ); |
| |
| // Pinmux connections |
| // All muxed inputs |
| assign cio_gpio_gpio_p2d[0] = mio_p2d[MioInGpioGpio0]; |
| assign cio_gpio_gpio_p2d[1] = mio_p2d[MioInGpioGpio1]; |
| assign cio_gpio_gpio_p2d[2] = mio_p2d[MioInGpioGpio2]; |
| assign cio_gpio_gpio_p2d[3] = mio_p2d[MioInGpioGpio3]; |
| assign cio_gpio_gpio_p2d[4] = mio_p2d[MioInGpioGpio4]; |
| assign cio_gpio_gpio_p2d[5] = mio_p2d[MioInGpioGpio5]; |
| assign cio_gpio_gpio_p2d[6] = mio_p2d[MioInGpioGpio6]; |
| assign cio_gpio_gpio_p2d[7] = mio_p2d[MioInGpioGpio7]; |
| assign cio_gpio_gpio_p2d[8] = mio_p2d[MioInGpioGpio8]; |
| assign cio_gpio_gpio_p2d[9] = mio_p2d[MioInGpioGpio9]; |
| assign cio_gpio_gpio_p2d[10] = mio_p2d[MioInGpioGpio10]; |
| assign cio_gpio_gpio_p2d[11] = mio_p2d[MioInGpioGpio11]; |
| assign cio_gpio_gpio_p2d[12] = mio_p2d[MioInGpioGpio12]; |
| assign cio_gpio_gpio_p2d[13] = mio_p2d[MioInGpioGpio13]; |
| assign cio_gpio_gpio_p2d[14] = mio_p2d[MioInGpioGpio14]; |
| assign cio_gpio_gpio_p2d[15] = mio_p2d[MioInGpioGpio15]; |
| assign cio_gpio_gpio_p2d[16] = mio_p2d[MioInGpioGpio16]; |
| assign cio_gpio_gpio_p2d[17] = mio_p2d[MioInGpioGpio17]; |
| assign cio_gpio_gpio_p2d[18] = mio_p2d[MioInGpioGpio18]; |
| assign cio_gpio_gpio_p2d[19] = mio_p2d[MioInGpioGpio19]; |
| assign cio_gpio_gpio_p2d[20] = mio_p2d[MioInGpioGpio20]; |
| assign cio_gpio_gpio_p2d[21] = mio_p2d[MioInGpioGpio21]; |
| assign cio_gpio_gpio_p2d[22] = mio_p2d[MioInGpioGpio22]; |
| assign cio_gpio_gpio_p2d[23] = mio_p2d[MioInGpioGpio23]; |
| assign cio_gpio_gpio_p2d[24] = mio_p2d[MioInGpioGpio24]; |
| assign cio_gpio_gpio_p2d[25] = mio_p2d[MioInGpioGpio25]; |
| assign cio_gpio_gpio_p2d[26] = mio_p2d[MioInGpioGpio26]; |
| assign cio_gpio_gpio_p2d[27] = mio_p2d[MioInGpioGpio27]; |
| assign cio_gpio_gpio_p2d[28] = mio_p2d[MioInGpioGpio28]; |
| assign cio_gpio_gpio_p2d[29] = mio_p2d[MioInGpioGpio29]; |
| assign cio_gpio_gpio_p2d[30] = mio_p2d[MioInGpioGpio30]; |
| assign cio_gpio_gpio_p2d[31] = mio_p2d[MioInGpioGpio31]; |
| assign cio_i2c0_sda_p2d = mio_p2d[MioInI2c0Sda]; |
| assign cio_i2c0_scl_p2d = mio_p2d[MioInI2c0Scl]; |
| assign cio_i2c1_sda_p2d = mio_p2d[MioInI2c1Sda]; |
| assign cio_i2c1_scl_p2d = mio_p2d[MioInI2c1Scl]; |
| assign cio_i2c2_sda_p2d = mio_p2d[MioInI2c2Sda]; |
| assign cio_i2c2_scl_p2d = mio_p2d[MioInI2c2Scl]; |
| assign cio_cam_i2c_sda_p2d = mio_p2d[MioInCamI2cSda]; |
| assign cio_cam_i2c_scl_p2d = mio_p2d[MioInCamI2cScl]; |
| assign cio_spi_host1_sd_p2d[0] = mio_p2d[MioInSpiHost1Sd0]; |
| assign cio_spi_host1_sd_p2d[1] = mio_p2d[MioInSpiHost1Sd1]; |
| assign cio_spi_host1_sd_p2d[2] = mio_p2d[MioInSpiHost1Sd2]; |
| assign cio_spi_host1_sd_p2d[3] = mio_p2d[MioInSpiHost1Sd3]; |
| assign cio_spi_host2_sd_p2d[0] = mio_p2d[MioInSpiHost2Sd0]; |
| assign cio_spi_host2_sd_p2d[1] = mio_p2d[MioInSpiHost2Sd1]; |
| assign cio_spi_host2_sd_p2d[2] = mio_p2d[MioInSpiHost2Sd2]; |
| assign cio_spi_host2_sd_p2d[3] = mio_p2d[MioInSpiHost2Sd3]; |
| assign cio_uart0_rx_p2d = mio_p2d[MioInUart0Rx]; |
| assign cio_uart1_rx_p2d = mio_p2d[MioInUart1Rx]; |
| assign cio_uart2_rx_p2d = mio_p2d[MioInUart2Rx]; |
| assign cio_smc_uart_rx_p2d = mio_p2d[MioInSmcUartRx]; |
| assign cio_cam_ctrl_cam_int_p2d = mio_p2d[MioInCamCtrlCamInt]; |
| assign cio_isp_wrapper_s_pclk_p2d = mio_p2d[MioInIspWrapperSPclk]; |
| assign cio_isp_wrapper_s_data_p2d[0] = mio_p2d[MioInIspWrapperSData0]; |
| assign cio_isp_wrapper_s_data_p2d[1] = mio_p2d[MioInIspWrapperSData1]; |
| assign cio_isp_wrapper_s_data_p2d[2] = mio_p2d[MioInIspWrapperSData2]; |
| assign cio_isp_wrapper_s_data_p2d[3] = mio_p2d[MioInIspWrapperSData3]; |
| assign cio_isp_wrapper_s_data_p2d[4] = mio_p2d[MioInIspWrapperSData4]; |
| assign cio_isp_wrapper_s_data_p2d[5] = mio_p2d[MioInIspWrapperSData5]; |
| assign cio_isp_wrapper_s_data_p2d[6] = mio_p2d[MioInIspWrapperSData6]; |
| assign cio_isp_wrapper_s_data_p2d[7] = mio_p2d[MioInIspWrapperSData7]; |
| assign cio_isp_wrapper_s_hsync_p2d = mio_p2d[MioInIspWrapperSHsync]; |
| assign cio_isp_wrapper_s_vsync_p2d = mio_p2d[MioInIspWrapperSVsync]; |
| assign cio_i2s0_rx_sd_p2d = mio_p2d[MioInI2s0RxSd]; |
| assign cio_spi_device_tpm_csb_p2d = mio_p2d[MioInSpiDeviceTpmCsb]; |
| assign cio_flash_ctrl_tck_p2d = mio_p2d[MioInFlashCtrlTck]; |
| assign cio_flash_ctrl_tms_p2d = mio_p2d[MioInFlashCtrlTms]; |
| assign cio_flash_ctrl_tdi_p2d = mio_p2d[MioInFlashCtrlTdi]; |
| assign cio_sysrst_ctrl_aon_ac_present_p2d = mio_p2d[MioInSysrstCtrlAonAcPresent]; |
| assign cio_sysrst_ctrl_aon_key0_in_p2d = mio_p2d[MioInSysrstCtrlAonKey0In]; |
| assign cio_sysrst_ctrl_aon_key1_in_p2d = mio_p2d[MioInSysrstCtrlAonKey1In]; |
| assign cio_sysrst_ctrl_aon_key2_in_p2d = mio_p2d[MioInSysrstCtrlAonKey2In]; |
| assign cio_sysrst_ctrl_aon_pwrb_in_p2d = mio_p2d[MioInSysrstCtrlAonPwrbIn]; |
| assign cio_sysrst_ctrl_aon_lid_open_p2d = mio_p2d[MioInSysrstCtrlAonLidOpen]; |
| assign cio_usbdev_sense_p2d = mio_p2d[MioInUsbdevSense]; |
| |
| // All muxed outputs |
| assign mio_d2p[MioOutGpioGpio0] = cio_gpio_gpio_d2p[0]; |
| assign mio_d2p[MioOutGpioGpio1] = cio_gpio_gpio_d2p[1]; |
| assign mio_d2p[MioOutGpioGpio2] = cio_gpio_gpio_d2p[2]; |
| assign mio_d2p[MioOutGpioGpio3] = cio_gpio_gpio_d2p[3]; |
| assign mio_d2p[MioOutGpioGpio4] = cio_gpio_gpio_d2p[4]; |
| assign mio_d2p[MioOutGpioGpio5] = cio_gpio_gpio_d2p[5]; |
| assign mio_d2p[MioOutGpioGpio6] = cio_gpio_gpio_d2p[6]; |
| assign mio_d2p[MioOutGpioGpio7] = cio_gpio_gpio_d2p[7]; |
| assign mio_d2p[MioOutGpioGpio8] = cio_gpio_gpio_d2p[8]; |
| assign mio_d2p[MioOutGpioGpio9] = cio_gpio_gpio_d2p[9]; |
| assign mio_d2p[MioOutGpioGpio10] = cio_gpio_gpio_d2p[10]; |
| assign mio_d2p[MioOutGpioGpio11] = cio_gpio_gpio_d2p[11]; |
| assign mio_d2p[MioOutGpioGpio12] = cio_gpio_gpio_d2p[12]; |
| assign mio_d2p[MioOutGpioGpio13] = cio_gpio_gpio_d2p[13]; |
| assign mio_d2p[MioOutGpioGpio14] = cio_gpio_gpio_d2p[14]; |
| assign mio_d2p[MioOutGpioGpio15] = cio_gpio_gpio_d2p[15]; |
| assign mio_d2p[MioOutGpioGpio16] = cio_gpio_gpio_d2p[16]; |
| assign mio_d2p[MioOutGpioGpio17] = cio_gpio_gpio_d2p[17]; |
| assign mio_d2p[MioOutGpioGpio18] = cio_gpio_gpio_d2p[18]; |
| assign mio_d2p[MioOutGpioGpio19] = cio_gpio_gpio_d2p[19]; |
| assign mio_d2p[MioOutGpioGpio20] = cio_gpio_gpio_d2p[20]; |
| assign mio_d2p[MioOutGpioGpio21] = cio_gpio_gpio_d2p[21]; |
| assign mio_d2p[MioOutGpioGpio22] = cio_gpio_gpio_d2p[22]; |
| assign mio_d2p[MioOutGpioGpio23] = cio_gpio_gpio_d2p[23]; |
| assign mio_d2p[MioOutGpioGpio24] = cio_gpio_gpio_d2p[24]; |
| assign mio_d2p[MioOutGpioGpio25] = cio_gpio_gpio_d2p[25]; |
| assign mio_d2p[MioOutGpioGpio26] = cio_gpio_gpio_d2p[26]; |
| assign mio_d2p[MioOutGpioGpio27] = cio_gpio_gpio_d2p[27]; |
| assign mio_d2p[MioOutGpioGpio28] = cio_gpio_gpio_d2p[28]; |
| assign mio_d2p[MioOutGpioGpio29] = cio_gpio_gpio_d2p[29]; |
| assign mio_d2p[MioOutGpioGpio30] = cio_gpio_gpio_d2p[30]; |
| assign mio_d2p[MioOutGpioGpio31] = cio_gpio_gpio_d2p[31]; |
| assign mio_d2p[MioOutI2c0Sda] = cio_i2c0_sda_d2p; |
| assign mio_d2p[MioOutI2c0Scl] = cio_i2c0_scl_d2p; |
| assign mio_d2p[MioOutI2c1Sda] = cio_i2c1_sda_d2p; |
| assign mio_d2p[MioOutI2c1Scl] = cio_i2c1_scl_d2p; |
| assign mio_d2p[MioOutI2c2Sda] = cio_i2c2_sda_d2p; |
| assign mio_d2p[MioOutI2c2Scl] = cio_i2c2_scl_d2p; |
| assign mio_d2p[MioOutCamI2cSda] = cio_cam_i2c_sda_d2p; |
| assign mio_d2p[MioOutCamI2cScl] = cio_cam_i2c_scl_d2p; |
| assign mio_d2p[MioOutSpiHost1Sd0] = cio_spi_host1_sd_d2p[0]; |
| assign mio_d2p[MioOutSpiHost1Sd1] = cio_spi_host1_sd_d2p[1]; |
| assign mio_d2p[MioOutSpiHost1Sd2] = cio_spi_host1_sd_d2p[2]; |
| assign mio_d2p[MioOutSpiHost1Sd3] = cio_spi_host1_sd_d2p[3]; |
| assign mio_d2p[MioOutSpiHost2Sd0] = cio_spi_host2_sd_d2p[0]; |
| assign mio_d2p[MioOutSpiHost2Sd1] = cio_spi_host2_sd_d2p[1]; |
| assign mio_d2p[MioOutSpiHost2Sd2] = cio_spi_host2_sd_d2p[2]; |
| assign mio_d2p[MioOutSpiHost2Sd3] = cio_spi_host2_sd_d2p[3]; |
| assign mio_d2p[MioOutUart0Tx] = cio_uart0_tx_d2p; |
| assign mio_d2p[MioOutUart1Tx] = cio_uart1_tx_d2p; |
| assign mio_d2p[MioOutUart2Tx] = cio_uart2_tx_d2p; |
| assign mio_d2p[MioOutSmcUartTx] = cio_smc_uart_tx_d2p; |
| assign mio_d2p[MioOutCamCtrlCamTrig] = cio_cam_ctrl_cam_trig_d2p; |
| assign mio_d2p[MioOutI2s0RxSclk] = cio_i2s0_rx_sclk_d2p; |
| assign mio_d2p[MioOutI2s0RxWs] = cio_i2s0_rx_ws_d2p; |
| assign mio_d2p[MioOutI2s0TxSclk] = cio_i2s0_tx_sclk_d2p; |
| assign mio_d2p[MioOutI2s0TxWs] = cio_i2s0_tx_ws_d2p; |
| assign mio_d2p[MioOutI2s0TxSd] = cio_i2s0_tx_sd_d2p; |
| assign mio_d2p[MioOutPattgenPda0Tx] = cio_pattgen_pda0_tx_d2p; |
| assign mio_d2p[MioOutPattgenPcl0Tx] = cio_pattgen_pcl0_tx_d2p; |
| assign mio_d2p[MioOutPattgenPda1Tx] = cio_pattgen_pda1_tx_d2p; |
| assign mio_d2p[MioOutPattgenPcl1Tx] = cio_pattgen_pcl1_tx_d2p; |
| assign mio_d2p[MioOutSpiHost1Sck] = cio_spi_host1_sck_d2p; |
| assign mio_d2p[MioOutSpiHost1Csb] = cio_spi_host1_csb_d2p; |
| assign mio_d2p[MioOutSpiHost2Sck] = cio_spi_host2_sck_d2p; |
| assign mio_d2p[MioOutSpiHost2Csb] = cio_spi_host2_csb_d2p; |
| assign mio_d2p[MioOutFlashCtrlTdo] = cio_flash_ctrl_tdo_d2p; |
| assign mio_d2p[MioOutSensorCtrlAstDebugOut0] = cio_sensor_ctrl_ast_debug_out_d2p[0]; |
| assign mio_d2p[MioOutSensorCtrlAstDebugOut1] = cio_sensor_ctrl_ast_debug_out_d2p[1]; |
| assign mio_d2p[MioOutSensorCtrlAstDebugOut2] = cio_sensor_ctrl_ast_debug_out_d2p[2]; |
| assign mio_d2p[MioOutSensorCtrlAstDebugOut3] = cio_sensor_ctrl_ast_debug_out_d2p[3]; |
| assign mio_d2p[MioOutSensorCtrlAstDebugOut4] = cio_sensor_ctrl_ast_debug_out_d2p[4]; |
| assign mio_d2p[MioOutSensorCtrlAstDebugOut5] = cio_sensor_ctrl_ast_debug_out_d2p[5]; |
| assign mio_d2p[MioOutSensorCtrlAstDebugOut6] = cio_sensor_ctrl_ast_debug_out_d2p[6]; |
| |
