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opensecura / hw / matcha / 998b2e8729b962d1ff3eef75a3ac878d2e4e25cc / . / hw / top_matcha / ip_autogen / rv_plic_smc / rtl / rv_plic_smc_reg_top.sv
blob: 711efb7edc2a6aec6e0b8272a496da0af4c93754 [file] [log] [blame]
// Copyright lowRISC contributors.
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0
//
// Register Top module auto-generated by `reggen`
`include "prim_assert.sv"
module rv_plic_smc_reg_top (
input clk_i,
input rst_ni,
input tlul_pkg::tl_h2d_t tl_i,
output tlul_pkg::tl_d2h_t tl_o,
// To HW
output rv_plic_smc_reg_pkg::rv_plic_smc_reg2hw_t reg2hw, // Write
input rv_plic_smc_reg_pkg::rv_plic_smc_hw2reg_t hw2reg, // Read
// Integrity check errors
output logic intg_err_o,
// Config
input devmode_i // If 1, explicit error return for unmapped register access
);
import rv_plic_smc_reg_pkg::* ;
localparam int AW = 27;
localparam int DW = 32;
localparam int DBW = DW/8; // Byte Width
// register signals
logic reg_we;
logic reg_re;
logic [AW-1:0] reg_addr;
logic [DW-1:0] reg_wdata;
logic [DBW-1:0] reg_be;
logic [DW-1:0] reg_rdata;
logic reg_error;
logic addrmiss, wr_err;
logic [DW-1:0] reg_rdata_next;
logic reg_busy;
tlul_pkg::tl_h2d_t tl_reg_h2d;
tlul_pkg::tl_d2h_t tl_reg_d2h;
// incoming payload check
logic intg_err;
tlul_cmd_intg_chk u_chk (
.tl_i(tl_i),
.err_o(intg_err)
);
// also check for spurious write enables
logic reg_we_err;
logic [50:0] reg_we_check;
prim_reg_we_check #(
.OneHotWidth(51)
) u_prim_reg_we_check (
.clk_i(clk_i),
.rst_ni(rst_ni),
.oh_i (reg_we_check),
.en_i (reg_we && !addrmiss),
.err_o (reg_we_err)
);
logic err_q;
always_ff @(posedge clk_i or negedge rst_ni) begin
if (!rst_ni) begin
err_q <= '0;
end else if (intg_err || reg_we_err) begin
err_q <= 1'b1;
end
end
// integrity error output is permanent and should be used for alert generation
// register errors are transactional
assign intg_err_o = err_q | intg_err | reg_we_err;
// outgoing integrity generation
tlul_pkg::tl_d2h_t tl_o_pre;
tlul_rsp_intg_gen #(
.EnableRspIntgGen(1),
.EnableDataIntgGen(1)
) u_rsp_intg_gen (
.tl_i(tl_o_pre),
.tl_o(tl_o)
);
assign tl_reg_h2d = tl_i;
assign tl_o_pre = tl_reg_d2h;
tlul_adapter_reg #(
.RegAw(AW),
.RegDw(DW),
.EnableDataIntgGen(0)
) u_reg_if (
.clk_i (clk_i),
.rst_ni (rst_ni),
.tl_i (tl_reg_h2d),
.tl_o (tl_reg_d2h),
.en_ifetch_i(prim_mubi_pkg::MuBi4False),
.intg_error_o(),
.we_o (reg_we),
.re_o (reg_re),
.addr_o (reg_addr),
.wdata_o (reg_wdata),
.be_o (reg_be),
.busy_i (reg_busy),
.rdata_i (reg_rdata),
.error_i (reg_error)
);
// cdc oversampling signals
assign reg_rdata = reg_rdata_next ;
assign reg_error = (devmode_i & addrmiss) | wr_err | intg_err;
// Define SW related signals
// Format: <reg>_<field>_{wd|we|qs}
// or <reg>_{wd|we|qs} if field == 1 or 0
logic prio0_we;
logic [1:0] prio0_qs;
logic [1:0] prio0_wd;
logic prio1_we;
logic [1:0] prio1_qs;
logic [1:0] prio1_wd;
logic prio2_we;
logic [1:0] prio2_qs;
logic [1:0] prio2_wd;
logic prio3_we;
logic [1:0] prio3_qs;
logic [1:0] prio3_wd;
logic prio4_we;
logic [1:0] prio4_qs;
logic [1:0] prio4_wd;
logic prio5_we;
logic [1:0] prio5_qs;
logic [1:0] prio5_wd;
logic prio6_we;
logic [1:0] prio6_qs;
logic [1:0] prio6_wd;
logic prio7_we;
logic [1:0] prio7_qs;
logic [1:0] prio7_wd;
logic prio8_we;
logic [1:0] prio8_qs;
logic [1:0] prio8_wd;
logic prio9_we;
logic [1:0] prio9_qs;
logic [1:0] prio9_wd;
logic prio10_we;
logic [1:0] prio10_qs;
logic [1:0] prio10_wd;
logic prio11_we;
logic [1:0] prio11_qs;
logic [1:0] prio11_wd;
logic prio12_we;
logic [1:0] prio12_qs;
logic [1:0] prio12_wd;
logic prio13_we;
logic [1:0] prio13_qs;
logic [1:0] prio13_wd;
logic prio14_we;
logic [1:0] prio14_qs;
logic [1:0] prio14_wd;
logic prio15_we;
logic [1:0] prio15_qs;
logic [1:0] prio15_wd;
logic prio16_we;
logic [1:0] prio16_qs;
logic [1:0] prio16_wd;
logic prio17_we;
logic [1:0] prio17_qs;
logic [1:0] prio17_wd;
logic prio18_we;
logic [1:0] prio18_qs;
logic [1:0] prio18_wd;
logic prio19_we;
logic [1:0] prio19_qs;
logic [1:0] prio19_wd;
logic prio20_we;
logic [1:0] prio20_qs;
logic [1:0] prio20_wd;
logic prio21_we;
logic [1:0] prio21_qs;
logic [1:0] prio21_wd;
logic prio22_we;
logic [1:0] prio22_qs;
logic [1:0] prio22_wd;
logic prio23_we;
logic [1:0] prio23_qs;
logic [1:0] prio23_wd;
logic prio24_we;
logic [1:0] prio24_qs;
logic [1:0] prio24_wd;
logic prio25_we;
logic [1:0] prio25_qs;
logic [1:0] prio25_wd;
logic prio26_we;
logic [1:0] prio26_qs;
logic [1:0] prio26_wd;
logic prio27_we;
logic [1:0] prio27_qs;
logic [1:0] prio27_wd;
logic prio28_we;
logic [1:0] prio28_qs;
logic [1:0] prio28_wd;
logic prio29_we;
logic [1:0] prio29_qs;
logic [1:0] prio29_wd;
logic prio30_we;
logic [1:0] prio30_qs;
logic [1:0] prio30_wd;
logic prio31_we;
logic [1:0] prio31_qs;
logic [1:0] prio31_wd;
logic prio32_we;
logic [1:0] prio32_qs;
logic [1:0] prio32_wd;
logic prio33_we;
logic [1:0] prio33_qs;
logic [1:0] prio33_wd;
logic prio34_we;
logic [1:0] prio34_qs;
logic [1:0] prio34_wd;
logic prio35_we;
logic [1:0] prio35_qs;
logic [1:0] prio35_wd;
logic prio36_we;
logic [1:0] prio36_qs;
logic [1:0] prio36_wd;
logic prio37_we;
logic [1:0] prio37_qs;
logic [1:0] prio37_wd;
logic prio38_we;
logic [1:0] prio38_qs;
logic [1:0] prio38_wd;
logic prio39_we;
logic [1:0] prio39_qs;
logic [1:0] prio39_wd;
logic prio40_we;
logic [1:0] prio40_qs;
logic [1:0] prio40_wd;
logic prio41_we;
logic [1:0] prio41_qs;
logic [1:0] prio41_wd;
logic prio42_we;
logic [1:0] prio42_qs;
logic [1:0] prio42_wd;
logic ip_0_p_0_qs;
logic ip_0_p_1_qs;
logic ip_0_p_2_qs;
logic ip_0_p_3_qs;
logic ip_0_p_4_qs;
logic ip_0_p_5_qs;
logic ip_0_p_6_qs;
logic ip_0_p_7_qs;
logic ip_0_p_8_qs;
logic ip_0_p_9_qs;
logic ip_0_p_10_qs;
logic ip_0_p_11_qs;
logic ip_0_p_12_qs;
logic ip_0_p_13_qs;
logic ip_0_p_14_qs;
logic ip_0_p_15_qs;
logic ip_0_p_16_qs;
logic ip_0_p_17_qs;
logic ip_0_p_18_qs;
logic ip_0_p_19_qs;
logic ip_0_p_20_qs;
logic ip_0_p_21_qs;
logic ip_0_p_22_qs;
logic ip_0_p_23_qs;
logic ip_0_p_24_qs;
logic ip_0_p_25_qs;
logic ip_0_p_26_qs;
logic ip_0_p_27_qs;
logic ip_0_p_28_qs;
logic ip_0_p_29_qs;
logic ip_0_p_30_qs;
logic ip_0_p_31_qs;
logic ip_1_p_32_qs;
logic ip_1_p_33_qs;
logic ip_1_p_34_qs;
logic ip_1_p_35_qs;
logic ip_1_p_36_qs;
logic ip_1_p_37_qs;
logic ip_1_p_38_qs;
logic ip_1_p_39_qs;
logic ip_1_p_40_qs;
logic ip_1_p_41_qs;
logic ip_1_p_42_qs;
logic ie0_0_we;
logic ie0_0_e_0_qs;
logic ie0_0_e_0_wd;
logic ie0_0_e_1_qs;
logic ie0_0_e_1_wd;
logic ie0_0_e_2_qs;
logic ie0_0_e_2_wd;
logic ie0_0_e_3_qs;
logic ie0_0_e_3_wd;
logic ie0_0_e_4_qs;
logic ie0_0_e_4_wd;
logic ie0_0_e_5_qs;
logic ie0_0_e_5_wd;
logic ie0_0_e_6_qs;
logic ie0_0_e_6_wd;
logic ie0_0_e_7_qs;
logic ie0_0_e_7_wd;
logic ie0_0_e_8_qs;
logic ie0_0_e_8_wd;
logic ie0_0_e_9_qs;
logic ie0_0_e_9_wd;
logic ie0_0_e_10_qs;
logic ie0_0_e_10_wd;
logic ie0_0_e_11_qs;
logic ie0_0_e_11_wd;
logic ie0_0_e_12_qs;
logic ie0_0_e_12_wd;
logic ie0_0_e_13_qs;
logic ie0_0_e_13_wd;
logic ie0_0_e_14_qs;
logic ie0_0_e_14_wd;
logic ie0_0_e_15_qs;
logic ie0_0_e_15_wd;
logic ie0_0_e_16_qs;
logic ie0_0_e_16_wd;
logic ie0_0_e_17_qs;
logic ie0_0_e_17_wd;
logic ie0_0_e_18_qs;
logic ie0_0_e_18_wd;
logic ie0_0_e_19_qs;
logic ie0_0_e_19_wd;
logic ie0_0_e_20_qs;
logic ie0_0_e_20_wd;
logic ie0_0_e_21_qs;
logic ie0_0_e_21_wd;
logic ie0_0_e_22_qs;
logic ie0_0_e_22_wd;
logic ie0_0_e_23_qs;
logic ie0_0_e_23_wd;
logic ie0_0_e_24_qs;
logic ie0_0_e_24_wd;
logic ie0_0_e_25_qs;
logic ie0_0_e_25_wd;
logic ie0_0_e_26_qs;
logic ie0_0_e_26_wd;
logic ie0_0_e_27_qs;
logic ie0_0_e_27_wd;
logic ie0_0_e_28_qs;
logic ie0_0_e_28_wd;
logic ie0_0_e_29_qs;
logic ie0_0_e_29_wd;
logic ie0_0_e_30_qs;
logic ie0_0_e_30_wd;
logic ie0_0_e_31_qs;
logic ie0_0_e_31_wd;
logic ie0_1_we;
logic ie0_1_e_32_qs;
logic ie0_1_e_32_wd;
logic ie0_1_e_33_qs;
logic ie0_1_e_33_wd;
logic ie0_1_e_34_qs;
logic ie0_1_e_34_wd;
logic ie0_1_e_35_qs;
logic ie0_1_e_35_wd;
logic ie0_1_e_36_qs;
logic ie0_1_e_36_wd;
logic ie0_1_e_37_qs;
logic ie0_1_e_37_wd;
logic ie0_1_e_38_qs;
logic ie0_1_e_38_wd;
logic ie0_1_e_39_qs;
logic ie0_1_e_39_wd;
logic ie0_1_e_40_qs;
logic ie0_1_e_40_wd;
logic ie0_1_e_41_qs;
logic ie0_1_e_41_wd;
logic ie0_1_e_42_qs;
logic ie0_1_e_42_wd;
logic threshold0_we;
logic [1:0] threshold0_qs;
logic [1:0] threshold0_wd;
logic cc0_re;
logic cc0_we;
logic [5:0] cc0_qs;
logic [5:0] cc0_wd;
logic msip0_we;
logic msip0_qs;
logic msip0_wd;
logic alert_test_we;
logic alert_test_wd;
// Register instances
// R[prio0]: V(False)
prim_subreg #(
.DW (2),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (2'h0)
) u_prio0 (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (prio0_we),
.wd (prio0_wd),
// from internal hardware
.de (1'b0),
.d ('0),
// to internal hardware
.qe (),
.q (reg2hw.prio0.q),
.ds (),
// to register interface (read)
.qs (prio0_qs)
);
// R[prio1]: V(False)
prim_subreg #(
.DW (2),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (2'h0)
) u_prio1 (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (prio1_we),
.wd (prio1_wd),
// from internal hardware
.de (1'b0),
.d ('0),
// to internal hardware
.qe (),
.q (reg2hw.prio1.q),
.ds (),
// to register interface (read)
.qs (prio1_qs)
);
// R[prio2]: V(False)
prim_subreg #(
.DW (2),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (2'h0)
) u_prio2 (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (prio2_we),
.wd (prio2_wd),
// from internal hardware
.de (1'b0),
.d ('0),
// to internal hardware
.qe (),
.q (reg2hw.prio2.q),
.ds (),
// to register interface (read)
.qs (prio2_qs)
);
// R[prio3]: V(False)
prim_subreg #(
.DW (2),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (2'h0)
) u_prio3 (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (prio3_we),
.wd (prio3_wd),
// from internal hardware
.de (1'b0),
.d ('0),
// to internal hardware
.qe (),
.q (reg2hw.prio3.q),
.ds (),
// to register interface (read)
.qs (prio3_qs)
);
// R[prio4]: V(False)
prim_subreg #(
.DW (2),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (2'h0)
) u_prio4 (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (prio4_we),
.wd (prio4_wd),
// from internal hardware
.de (1'b0),
.d ('0),
// to internal hardware
.qe (),
.q (reg2hw.prio4.q),
.ds (),
// to register interface (read)
.qs (prio4_qs)
);
// R[prio5]: V(False)
prim_subreg #(
.DW (2),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (2'h0)
) u_prio5 (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (prio5_we),
.wd (prio5_wd),
// from internal hardware
.de (1'b0),
.d ('0),
// to internal hardware
.qe (),
.q (reg2hw.prio5.q),
.ds (),
// to register interface (read)
.qs (prio5_qs)
);
// R[prio6]: V(False)
prim_subreg #(
.DW (2),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (2'h0)
) u_prio6 (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (prio6_we),
.wd (prio6_wd),
// from internal hardware
.de (1'b0),
.d ('0),
// to internal hardware
.qe (),
.q (reg2hw.prio6.q),
.ds (),
// to register interface (read)
.qs (prio6_qs)
);
// R[prio7]: V(False)
prim_subreg #(
.DW (2),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (2'h0)
) u_prio7 (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (prio7_we),
.wd (prio7_wd),
// from internal hardware
.de (1'b0),
.d ('0),
// to internal hardware
.qe (),
.q (reg2hw.prio7.q),
.ds (),
// to register interface (read)
.qs (prio7_qs)
);
// R[prio8]: V(False)
prim_subreg #(
.DW (2),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (2'h0)
) u_prio8 (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (prio8_we),
.wd (prio8_wd),
// from internal hardware
.de (1'b0),
.d ('0),
// to internal hardware
.qe (),
.q (reg2hw.prio8.q),
.ds (),
// to register interface (read)
.qs (prio8_qs)
);
// R[prio9]: V(False)
prim_subreg #(
.DW (2),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (2'h0)
) u_prio9 (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (prio9_we),
.wd (prio9_wd),
// from internal hardware
.de (1'b0),
.d ('0),
// to internal hardware
.qe (),
.q (reg2hw.prio9.q),
.ds (),
// to register interface (read)
.qs (prio9_qs)
);
// R[prio10]: V(False)
prim_subreg #(
.DW (2),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (2'h0)
) u_prio10 (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (prio10_we),
.wd (prio10_wd),
// from internal hardware
.de (1'b0),
.d ('0),
// to internal hardware
.qe (),
.q (reg2hw.prio10.q),
.ds (),
// to register interface (read)
.qs (prio10_qs)
);
// R[prio11]: V(False)
prim_subreg #(
.DW (2),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (2'h0)
) u_prio11 (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (prio11_we),
.wd (prio11_wd),
// from internal hardware
.de (1'b0),
.d ('0),
// to internal hardware
.qe (),
.q (reg2hw.prio11.q),
.ds (),
// to register interface (read)
.qs (prio11_qs)
);
// R[prio12]: V(False)
prim_subreg #(
.DW (2),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (2'h0)
) u_prio12 (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (prio12_we),
.wd (prio12_wd),
// from internal hardware
.de (1'b0),
.d ('0),
// to internal hardware
.qe (),
.q (reg2hw.prio12.q),
.ds (),
// to register interface (read)
.qs (prio12_qs)
);
// R[prio13]: V(False)
prim_subreg #(
.DW (2),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (2'h0)
) u_prio13 (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (prio13_we),
.wd (prio13_wd),
// from internal hardware
.de (1'b0),
.d ('0),
// to internal hardware
.qe (),
.q (reg2hw.prio13.q),
.ds (),
// to register interface (read)
.qs (prio13_qs)
);
// R[prio14]: V(False)
prim_subreg #(
.DW (2),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (2'h0)
) u_prio14 (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (prio14_we),
.wd (prio14_wd),
// from internal hardware
.de (1'b0),
.d ('0),
// to internal hardware
.qe (),
.q (reg2hw.prio14.q),
.ds (),
// to register interface (read)
.qs (prio14_qs)
);
// R[prio15]: V(False)
prim_subreg #(
.DW (2),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (2'h0)
) u_prio15 (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (prio15_we),
.wd (prio15_wd),
// from internal hardware
.de (1'b0),
.d ('0),
// to internal hardware
.qe (),
.q (reg2hw.prio15.q),
.ds (),
// to register interface (read)
.qs (prio15_qs)
);
// R[prio16]: V(False)
prim_subreg #(
.DW (2),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (2'h0)
) u_prio16 (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (prio16_we),
.wd (prio16_wd),
// from internal hardware
.de (1'b0),
.d ('0),
// to internal hardware
.qe (),
.q (reg2hw.prio16.q),
.ds (),
// to register interface (read)
.qs (prio16_qs)
);
// R[prio17]: V(False)
prim_subreg #(
.DW (2),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (2'h0)
) u_prio17 (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (prio17_we),
.wd (prio17_wd),
// from internal hardware
.de (1'b0),
.d ('0),
// to internal hardware
.qe (),
.q (reg2hw.prio17.q),
.ds (),
// to register interface (read)
.qs (prio17_qs)
);
// R[prio18]: V(False)
prim_subreg #(
.DW (2),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (2'h0)
) u_prio18 (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (prio18_we),
.wd (prio18_wd),
// from internal hardware
.de (1'b0),
.d ('0),
// to internal hardware
.qe (),
.q (reg2hw.prio18.q),
.ds (),
// to register interface (read)
.qs (prio18_qs)
);
// R[prio19]: V(False)
prim_subreg #(
.DW (2),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (2'h0)
) u_prio19 (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (prio19_we),
.wd (prio19_wd),
// from internal hardware
.de (1'b0),
.d ('0),
// to internal hardware
.qe (),
.q (reg2hw.prio19.q),
.ds (),
// to register interface (read)
.qs (prio19_qs)
);
// R[prio20]: V(False)
prim_subreg #(
.DW (2),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (2'h0)
) u_prio20 (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (prio20_we),
.wd (prio20_wd),
// from internal hardware
.de (1'b0),
.d ('0),
// to internal hardware
.qe (),
.q (reg2hw.prio20.q),
.ds (),
// to register interface (read)
.qs (prio20_qs)
);
// R[prio21]: V(False)
prim_subreg #(
.DW (2),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (2'h0)
) u_prio21 (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (prio21_we),
.wd (prio21_wd),
// from internal hardware
.de (1'b0),
.d ('0),
// to internal hardware
.qe (),
.q (reg2hw.prio21.q),
.ds (),
// to register interface (read)
.qs (prio21_qs)
);
// R[prio22]: V(False)
prim_subreg #(
.DW (2),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (2'h0)
) u_prio22 (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (prio22_we),
.wd (prio22_wd),
// from internal hardware
.de (1'b0),
.d ('0),
// to internal hardware
.qe (),
.q (reg2hw.prio22.q),
.ds (),
// to register interface (read)
.qs (prio22_qs)
);
// R[prio23]: V(False)
prim_subreg #(
.DW (2),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (2'h0)
) u_prio23 (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (prio23_we),
.wd (prio23_wd),
// from internal hardware
.de (1'b0),
.d ('0),
// to internal hardware
.qe (),
.q (reg2hw.prio23.q),
.ds (),
// to register interface (read)
.qs (prio23_qs)
);
// R[prio24]: V(False)
prim_subreg #(
.DW (2),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (2'h0)
) u_prio24 (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (prio24_we),
.wd (prio24_wd),
// from internal hardware
.de (1'b0),
.d ('0),
// to internal hardware
.qe (),
.q (reg2hw.prio24.q),
.ds (),
// to register interface (read)
.qs (prio24_qs)
);
// R[prio25]: V(False)
prim_subreg #(
.DW (2),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (2'h0)
) u_prio25 (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (prio25_we),
.wd (prio25_wd),
// from internal hardware
.de (1'b0),
.d ('0),
// to internal hardware
.qe (),
.q (reg2hw.prio25.q),
.ds (),
// to register interface (read)
.qs (prio25_qs)
);
// R[prio26]: V(False)
prim_subreg #(
.DW (2),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (2'h0)
) u_prio26 (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (prio26_we),
.wd (prio26_wd),
// from internal hardware
.de (1'b0),
.d ('0),
// to internal hardware
.qe (),
.q (reg2hw.prio26.q),
.ds (),
// to register interface (read)
.qs (prio26_qs)
);
// R[prio27]: V(False)
prim_subreg #(
.DW (2),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (2'h0)
) u_prio27 (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (prio27_we),
.wd (prio27_wd),
// from internal hardware
.de (1'b0),
.d ('0),
// to internal hardware
.qe (),
.q (reg2hw.prio27.q),
.ds (),
// to register interface (read)
.qs (prio27_qs)
);
// R[prio28]: V(False)
prim_subreg #(
.DW (2),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (2'h0)
) u_prio28 (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (prio28_we),
.wd (prio28_wd),
// from internal hardware
.de (1'b0),
.d ('0),
// to internal hardware
.qe (),
.q (reg2hw.prio28.q),
.ds (),
// to register interface (read)
.qs (prio28_qs)
);
// R[prio29]: V(False)
prim_subreg #(
.DW (2),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (2'h0)
) u_prio29 (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (prio29_we),
.wd (prio29_wd),
// from internal hardware
.de (1'b0),
.d ('0),
// to internal hardware
.qe (),
.q (reg2hw.prio29.q),
.ds (),
// to register interface (read)
.qs (prio29_qs)
);
// R[prio30]: V(False)
prim_subreg #(
.DW (2),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (2'h0)
) u_prio30 (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (prio30_we),
.wd (prio30_wd),
// from internal hardware
.de (1'b0),
.d ('0),
// to internal hardware
.qe (),
.q (reg2hw.prio30.q),
.ds (),
// to register interface (read)
.qs (prio30_qs)
);
// R[prio31]: V(False)
prim_subreg #(
.DW (2),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (2'h0)
) u_prio31 (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (prio31_we),
.wd (prio31_wd),
// from internal hardware
.de (1'b0),
.d ('0),
// to internal hardware
.qe (),
.q (reg2hw.prio31.q),
.ds (),
// to register interface (read)
.qs (prio31_qs)
);
// R[prio32]: V(False)
prim_subreg #(
.DW (2),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (2'h0)
) u_prio32 (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (prio32_we),
.wd (prio32_wd),
// from internal hardware
.de (1'b0),
.d ('0),
// to internal hardware
.qe (),
.q (reg2hw.prio32.q),
.ds (),
// to register interface (read)
.qs (prio32_qs)
);
// R[prio33]: V(False)
prim_subreg #(
.DW (2),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (2'h0)
) u_prio33 (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (prio33_we),
.wd (prio33_wd),
// from internal hardware
.de (1'b0),
.d ('0),
// to internal hardware
.qe (),
.q (reg2hw.prio33.q),
.ds (),
// to register interface (read)
.qs (prio33_qs)
);
// R[prio34]: V(False)
prim_subreg #(
.DW (2),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (2'h0)
) u_prio34 (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (prio34_we),
.wd (prio34_wd),
// from internal hardware
.de (1'b0),
.d ('0),
// to internal hardware
.qe (),
.q (reg2hw.prio34.q),
.ds (),
// to register interface (read)
.qs (prio34_qs)
);
// R[prio35]: V(False)
prim_subreg #(
.DW (2),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (2'h0)
) u_prio35 (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (prio35_we),
.wd (prio35_wd),
// from internal hardware
.de (1'b0),
.d ('0),
// to internal hardware
.qe (),
.q (reg2hw.prio35.q),
.ds (),
// to register interface (read)
.qs (prio35_qs)
);
// R[prio36]: V(False)
prim_subreg #(
.DW (2),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (2'h0)
) u_prio36 (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (prio36_we),
.wd (prio36_wd),
// from internal hardware
.de (1'b0),
.d ('0),
// to internal hardware
.qe (),
.q (reg2hw.prio36.q),
.ds (),
// to register interface (read)
.qs (prio36_qs)
);
// R[prio37]: V(False)
prim_subreg #(
.DW (2),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (2'h0)
) u_prio37 (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (prio37_we),
.wd (prio37_wd),
// from internal hardware
.de (1'b0),
.d ('0),
// to internal hardware
.qe (),
.q (reg2hw.prio37.q),
.ds (),
// to register interface (read)
.qs (prio37_qs)
);
// R[prio38]: V(False)
prim_subreg #(
.DW (2),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (2'h0)
) u_prio38 (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (prio38_we),
.wd (prio38_wd),
// from internal hardware
.de (1'b0),
.d ('0),
// to internal hardware
.qe (),
.q (reg2hw.prio38.q),
.ds (),
// to register interface (read)
.qs (prio38_qs)
);
// R[prio39]: V(False)
prim_subreg #(
.DW (2),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (2'h0)
) u_prio39 (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (prio39_we),
.wd (prio39_wd),
// from internal hardware
.de (1'b0),
.d ('0),
// to internal hardware
.qe (),
.q (reg2hw.prio39.q),
.ds (),
// to register interface (read)
.qs (prio39_qs)
);
// R[prio40]: V(False)
prim_subreg #(
.DW (2),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (2'h0)
) u_prio40 (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (prio40_we),
.wd (prio40_wd),
// from internal hardware
.de (1'b0),
.d ('0),
// to internal hardware
.qe (),
.q (reg2hw.prio40.q),
.ds (),
// to register interface (read)
.qs (prio40_qs)
);
// R[prio41]: V(False)
prim_subreg #(
.DW (2),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (2'h0)
) u_prio41 (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (prio41_we),
.wd (prio41_wd),
// from internal hardware
.de (1'b0),
.d ('0),
// to internal hardware
.qe (),
.q (reg2hw.prio41.q),
.ds (),
// to register interface (read)
.qs (prio41_qs)
);
// R[prio42]: V(False)
prim_subreg #(
.DW (2),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (2'h0)
) u_prio42 (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (prio42_we),
.wd (prio42_wd),
// from internal hardware
.de (1'b0),
.d ('0),
// to internal hardware
.qe (),
.q (reg2hw.prio42.q),
.ds (),
// to register interface (read)
.qs (prio42_qs)
);
// Subregister 0 of Multireg ip
// R[ip_0]: V(False)
// F[p_0]: 0:0
prim_subreg #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessRO),
.RESVAL (1'h0)
) u_ip_0_p_0 (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (1'b0),
.wd ('0),
// from internal hardware
.de (hw2reg.ip[0].de),
.d (hw2reg.ip[0].d),
// to internal hardware
.qe (),
.q (),
.ds (),
// to register interface (read)
.qs (ip_0_p_0_qs)
);
// F[p_1]: 1:1
prim_subreg #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessRO),
.RESVAL (1'h0)
) u_ip_0_p_1 (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (1'b0),
.wd ('0),
// from internal hardware
.de (hw2reg.ip[1].de),
.d (hw2reg.ip[1].d),
// to internal hardware
.qe (),
.q (),
.ds (),
// to register interface (read)
.qs (ip_0_p_1_qs)
);
// F[p_2]: 2:2
prim_subreg #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessRO),
.RESVAL (1'h0)
) u_ip_0_p_2 (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (1'b0),
.wd ('0),
// from internal hardware
.de (hw2reg.ip[2].de),
.d (hw2reg.ip[2].d),
// to internal hardware
.qe (),
.q (),
.ds (),
// to register interface (read)
.qs (ip_0_p_2_qs)
);
// F[p_3]: 3:3
prim_subreg #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessRO),
.RESVAL (1'h0)
) u_ip_0_p_3 (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (1'b0),
.wd ('0),
// from internal hardware
.de (hw2reg.ip[3].de),
.d (hw2reg.ip[3].d),
// to internal hardware
.qe (),
.q (),
.ds (),
// to register interface (read)
.qs (ip_0_p_3_qs)
);
// F[p_4]: 4:4
prim_subreg #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessRO),
.RESVAL (1'h0)
) u_ip_0_p_4 (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (1'b0),
.wd ('0),
// from internal hardware
.de (hw2reg.ip[4].de),
.d (hw2reg.ip[4].d),
// to internal hardware
.qe (),
.q (),
.ds (),
// to register interface (read)
.qs (ip_0_p_4_qs)
);
// F[p_5]: 5:5
prim_subreg #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessRO),
.RESVAL (1'h0)
) u_ip_0_p_5 (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (1'b0),
.wd ('0),
// from internal hardware
.de (hw2reg.ip[5].de),
.d (hw2reg.ip[5].d),
// to internal hardware
.qe (),
.q (),
.ds (),
// to register interface (read)
.qs (ip_0_p_5_qs)
);
// F[p_6]: 6:6
prim_subreg #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessRO),
.RESVAL (1'h0)
) u_ip_0_p_6 (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (1'b0),
.wd ('0),
// from internal hardware
.de (hw2reg.ip[6].de),
.d (hw2reg.ip[6].d),
// to internal hardware
.qe (),
.q (),
.ds (),
// to register interface (read)
.qs (ip_0_p_6_qs)
);
// F[p_7]: 7:7
prim_subreg #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessRO),
.RESVAL (1'h0)
) u_ip_0_p_7 (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (1'b0),
.wd ('0),
// from internal hardware
.de (hw2reg.ip[7].de),
.d (hw2reg.ip[7].d),
// to internal hardware
.qe (),
.q (),
.ds (),
// to register interface (read)
.qs (ip_0_p_7_qs)
);
// F[p_8]: 8:8
prim_subreg #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessRO),
.RESVAL (1'h0)
) u_ip_0_p_8 (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (1'b0),
.wd ('0),
// from internal hardware
.de (hw2reg.ip[8].de),
.d (hw2reg.ip[8].d),
// to internal hardware
.qe (),
.q (),
.ds (),
// to register interface (read)
.qs (ip_0_p_8_qs)
);
// F[p_9]: 9:9
prim_subreg #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessRO),
.RESVAL (1'h0)
) u_ip_0_p_9 (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (1'b0),
.wd ('0),
// from internal hardware
.de (hw2reg.ip[9].de),
.d (hw2reg.ip[9].d),
// to internal hardware
.qe (),
.q (),
.ds (),
// to register interface (read)
.qs (ip_0_p_9_qs)
);
// F[p_10]: 10:10
prim_subreg #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessRO),
.RESVAL (1'h0)
) u_ip_0_p_10 (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (1'b0),
.wd ('0),
// from internal hardware
.de (hw2reg.ip[10].de),
.d (hw2reg.ip[10].d),
// to internal hardware
.qe (),
.q (),
.ds (),
// to register interface (read)
.qs (ip_0_p_10_qs)
);
// F[p_11]: 11:11
prim_subreg #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessRO),
.RESVAL (1'h0)
) u_ip_0_p_11 (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (1'b0),
.wd ('0),
// from internal hardware
.de (hw2reg.ip[11].de),
.d (hw2reg.ip[11].d),
// to internal hardware
.qe (),
.q (),
.ds (),
// to register interface (read)
.qs (ip_0_p_11_qs)
);
// F[p_12]: 12:12
prim_subreg #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessRO),
.RESVAL (1'h0)
) u_ip_0_p_12 (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (1'b0),
.wd ('0),
// from internal hardware
.de (hw2reg.ip[12].de),
.d (hw2reg.ip[12].d),
// to internal hardware
.qe (),
.q (),
.ds (),
// to register interface (read)
.qs (ip_0_p_12_qs)
);
// F[p_13]: 13:13
prim_subreg #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessRO),
.RESVAL (1'h0)
) u_ip_0_p_13 (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (1'b0),
.wd ('0),
// from internal hardware
.de (hw2reg.ip[13].de),
.d (hw2reg.ip[13].d),
// to internal hardware
.qe (),
.q (),
.ds (),
// to register interface (read)
.qs (ip_0_p_13_qs)
);
// F[p_14]: 14:14
prim_subreg #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessRO),
.RESVAL (1'h0)
) u_ip_0_p_14 (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (1'b0),
.wd ('0),
// from internal hardware
.de (hw2reg.ip[14].de),
.d (hw2reg.ip[14].d),
// to internal hardware
.qe (),
.q (),
.ds (),
// to register interface (read)
.qs (ip_0_p_14_qs)
);
// F[p_15]: 15:15
prim_subreg #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessRO),
.RESVAL (1'h0)
) u_ip_0_p_15 (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (1'b0),
.wd ('0),
// from internal hardware
.de (hw2reg.ip[15].de),
.d (hw2reg.ip[15].d),
// to internal hardware
.qe (),
.q (),
.ds (),
// to register interface (read)
.qs (ip_0_p_15_qs)
);
// F[p_16]: 16:16
prim_subreg #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessRO),
.RESVAL (1'h0)
) u_ip_0_p_16 (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (1'b0),
.wd ('0),
// from internal hardware
.de (hw2reg.ip[16].de),
.d (hw2reg.ip[16].d),
// to internal hardware
.qe (),
.q (),
.ds (),
// to register interface (read)
.qs (ip_0_p_16_qs)
);
// F[p_17]: 17:17
prim_subreg #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessRO),
.RESVAL (1'h0)
) u_ip_0_p_17 (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (1'b0),
.wd ('0),
// from internal hardware
.de (hw2reg.ip[17].de),
.d (hw2reg.ip[17].d),
// to internal hardware
.qe (),
.q (),
.ds (),
// to register interface (read)
.qs (ip_0_p_17_qs)
);
// F[p_18]: 18:18
prim_subreg #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessRO),
.RESVAL (1'h0)
) u_ip_0_p_18 (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (1'b0),
.wd ('0),
// from internal hardware
.de (hw2reg.ip[18].de),
.d (hw2reg.ip[18].d),
// to internal hardware
.qe (),
.q (),
.ds (),
// to register interface (read)
.qs (ip_0_p_18_qs)
);
// F[p_19]: 19:19
prim_subreg #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessRO),
.RESVAL (1'h0)
) u_ip_0_p_19 (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (1'b0),
.wd ('0),
// from internal hardware
.de (hw2reg.ip[19].de),
.d (hw2reg.ip[19].d),
// to internal hardware
.qe (),
.q (),
.ds (),
// to register interface (read)
.qs (ip_0_p_19_qs)
);
// F[p_20]: 20:20
prim_subreg #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessRO),
.RESVAL (1'h0)
) u_ip_0_p_20 (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (1'b0),
.wd ('0),
// from internal hardware
.de (hw2reg.ip[20].de),
.d (hw2reg.ip[20].d),
// to internal hardware
.qe (),
.q (),
.ds (),
// to register interface (read)
.qs (ip_0_p_20_qs)
);
// F[p_21]: 21:21
prim_subreg #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessRO),
.RESVAL (1'h0)
) u_ip_0_p_21 (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (1'b0),
.wd ('0),
// from internal hardware
.de (hw2reg.ip[21].de),
.d (hw2reg.ip[21].d),
// to internal hardware
.qe (),
.q (),
.ds (),
// to register interface (read)
.qs (ip_0_p_21_qs)
);
// F[p_22]: 22:22
prim_subreg #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessRO),
.RESVAL (1'h0)
) u_ip_0_p_22 (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (1'b0),
.wd ('0),
// from internal hardware
.de (hw2reg.ip[22].de),
.d (hw2reg.ip[22].d),
// to internal hardware
.qe (),
.q (),
.ds (),
// to register interface (read)
.qs (ip_0_p_22_qs)
);
// F[p_23]: 23:23
prim_subreg #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessRO),
.RESVAL (1'h0)
) u_ip_0_p_23 (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (1'b0),
.wd ('0),
// from internal hardware
.de (hw2reg.ip[23].de),
.d (hw2reg.ip[23].d),
// to internal hardware
.qe (),
.q (),
.ds (),
// to register interface (read)
.qs (ip_0_p_23_qs)
);
// F[p_24]: 24:24
prim_subreg #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessRO),
.RESVAL (1'h0)
) u_ip_0_p_24 (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (1'b0),
.wd ('0),
// from internal hardware
.de (hw2reg.ip[24].de),
.d (hw2reg.ip[24].d),
// to internal hardware
.qe (),
.q (),
.ds (),
// to register interface (read)
.qs (ip_0_p_24_qs)
);
// F[p_25]: 25:25
prim_subreg #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessRO),
.RESVAL (1'h0)
) u_ip_0_p_25 (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (1'b0),
.wd ('0),
// from internal hardware
.de (hw2reg.ip[25].de),
.d (hw2reg.ip[25].d),
// to internal hardware
.qe (),
.q (),
.ds (),
// to register interface (read)
.qs (ip_0_p_25_qs)
);
// F[p_26]: 26:26
prim_subreg #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessRO),
.RESVAL (1'h0)
) u_ip_0_p_26 (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (1'b0),
.wd ('0),
// from internal hardware
.de (hw2reg.ip[26].de),
.d (hw2reg.ip[26].d),
// to internal hardware
.qe (),
.q (),
.ds (),
// to register interface (read)
.qs (ip_0_p_26_qs)
);
// F[p_27]: 27:27
prim_subreg #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessRO),
.RESVAL (1'h0)
) u_ip_0_p_27 (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (1'b0),
.wd ('0),
// from internal hardware
.de (hw2reg.ip[27].de),
.d (hw2reg.ip[27].d),
// to internal hardware
.qe (),
.q (),
.ds (),
// to register interface (read)
.qs (ip_0_p_27_qs)
);
// F[p_28]: 28:28
prim_subreg #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessRO),
.RESVAL (1'h0)
) u_ip_0_p_28 (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (1'b0),
.wd ('0),
// from internal hardware
.de (hw2reg.ip[28].de),
.d (hw2reg.ip[28].d),
// to internal hardware
.qe (),
.q (),
.ds (),
// to register interface (read)
.qs (ip_0_p_28_qs)
);
// F[p_29]: 29:29
prim_subreg #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessRO),
.RESVAL (1'h0)
) u_ip_0_p_29 (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (1'b0),
.wd ('0),
// from internal hardware
.de (hw2reg.ip[29].de),
.d (hw2reg.ip[29].d),
// to internal hardware
.qe (),
.q (),
.ds (),
// to register interface (read)
.qs (ip_0_p_29_qs)
);
// F[p_30]: 30:30
prim_subreg #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessRO),
.RESVAL (1'h0)
) u_ip_0_p_30 (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (1'b0),
.wd ('0),
// from internal hardware
.de (hw2reg.ip[30].de),
.d (hw2reg.ip[30].d),
// to internal hardware
.qe (),
.q (),
.ds (),
// to register interface (read)
.qs (ip_0_p_30_qs)
);
// F[p_31]: 31:31
prim_subreg #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessRO),
.RESVAL (1'h0)
) u_ip_0_p_31 (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (1'b0),
.wd ('0),
// from internal hardware
.de (hw2reg.ip[31].de),
.d (hw2reg.ip[31].d),
// to internal hardware
.qe (),
.q (),
.ds (),
// to register interface (read)
.qs (ip_0_p_31_qs)
);
// Subregister 1 of Multireg ip
// R[ip_1]: V(False)
// F[p_32]: 0:0
prim_subreg #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessRO),
.RESVAL (1'h0)
) u_ip_1_p_32 (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (1'b0),
.wd ('0),
// from internal hardware
.de (hw2reg.ip[32].de),
.d (hw2reg.ip[32].d),
// to internal hardware
.qe (),
.q (),
.ds (),
// to register interface (read)
.qs (ip_1_p_32_qs)
);
// F[p_33]: 1:1
prim_subreg #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessRO),
.RESVAL (1'h0)
) u_ip_1_p_33 (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (1'b0),
.wd ('0),
// from internal hardware
.de (hw2reg.ip[33].de),
.d (hw2reg.ip[33].d),
// to internal hardware
.qe (),
.q (),
.ds (),
// to register interface (read)
.qs (ip_1_p_33_qs)
);
// F[p_34]: 2:2
prim_subreg #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessRO),
.RESVAL (1'h0)
) u_ip_1_p_34 (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (1'b0),
.wd ('0),
// from internal hardware
.de (hw2reg.ip[34].de),
.d (hw2reg.ip[34].d),
// to internal hardware
.qe (),
.q (),
.ds (),
// to register interface (read)
.qs (ip_1_p_34_qs)
);
// F[p_35]: 3:3
prim_subreg #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessRO),
.RESVAL (1'h0)
) u_ip_1_p_35 (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (1'b0),
.wd ('0),
// from internal hardware
.de (hw2reg.ip[35].de),
.d (hw2reg.ip[35].d),
// to internal hardware
.qe (),
.q (),
.ds (),
// to register interface (read)
.qs (ip_1_p_35_qs)
);
// F[p_36]: 4:4
prim_subreg #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessRO),
.RESVAL (1'h0)
) u_ip_1_p_36 (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (1'b0),
.wd ('0),
// from internal hardware
.de (hw2reg.ip[36].de),
.d (hw2reg.ip[36].d),
// to internal hardware
.qe (),
.q (),
.ds (),
// to register interface (read)
.qs (ip_1_p_36_qs)
);
// F[p_37]: 5:5
prim_subreg #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessRO),
.RESVAL (1'h0)
) u_ip_1_p_37 (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (1'b0),
.wd ('0),
// from internal hardware
.de (hw2reg.ip[37].de),
.d (hw2reg.ip[37].d),
// to internal hardware
.qe (),
.q (),
.ds (),
// to register interface (read)
.qs (ip_1_p_37_qs)
);
// F[p_38]: 6:6
prim_subreg #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessRO),
.RESVAL (1'h0)
) u_ip_1_p_38 (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (1'b0),
.wd ('0),
// from internal hardware
.de (hw2reg.ip[38].de),
.d (hw2reg.ip[38].d),
// to internal hardware
.qe (),
.q (),
.ds (),
// to register interface (read)
.qs (ip_1_p_38_qs)
);
// F[p_39]: 7:7
prim_subreg #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessRO),
.RESVAL (1'h0)
) u_ip_1_p_39 (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (1'b0),
.wd ('0),
// from internal hardware
.de (hw2reg.ip[39].de),
.d (hw2reg.ip[39].d),
// to internal hardware
.qe (),
.q (),
.ds (),
// to register interface (read)
.qs (ip_1_p_39_qs)
);
// F[p_40]: 8:8
prim_subreg #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessRO),
.RESVAL (1'h0)
) u_ip_1_p_40 (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (1'b0),
.wd ('0),
// from internal hardware
.de (hw2reg.ip[40].de),
.d (hw2reg.ip[40].d),
// to internal hardware
.qe (),
.q (),
.ds (),
// to register interface (read)
.qs (ip_1_p_40_qs)
);
// F[p_41]: 9:9
prim_subreg #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessRO),
.RESVAL (1'h0)
) u_ip_1_p_41 (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (1'b0),
.wd ('0),
// from internal hardware
.de (hw2reg.ip[41].de),
.d (hw2reg.ip[41].d),
// to internal hardware
.qe (),
.q (),
.ds (),
// to register interface (read)
.qs (ip_1_p_41_qs)
);
// F[p_42]: 10:10
prim_subreg #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessRO),
.RESVAL (1'h0)
) u_ip_1_p_42 (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (1'b0),
.wd ('0),
// from internal hardware
.de (hw2reg.ip[42].de),
.d (hw2reg.ip[42].d),
// to internal hardware
.qe (),
.q (),
.ds (),
// to register interface (read)
.qs (ip_1_p_42_qs)
);
// Subregister 0 of Multireg ie0
// R[ie0_0]: V(False)
// F[e_0]: 0:0
prim_subreg #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (1'h0)
) u_ie0_0_e_0 (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (ie0_0_we),
.wd (ie0_0_e_0_wd),
// from internal hardware
.de (1'b0),
.d ('0),
// to internal hardware
.qe (),
.q (reg2hw.ie0[0].q),
.ds (),
// to register interface (read)
.qs (ie0_0_e_0_qs)
);
// F[e_1]: 1:1
prim_subreg #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (1'h0)
) u_ie0_0_e_1 (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (ie0_0_we),
.wd (ie0_0_e_1_wd),
// from internal hardware
.de (1'b0),
.d ('0),
// to internal hardware
.qe (),
.q (reg2hw.ie0[1].q),
.ds (),
// to register interface (read)
.qs (ie0_0_e_1_qs)
);
// F[e_2]: 2:2
prim_subreg #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (1'h0)
) u_ie0_0_e_2 (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (ie0_0_we),
.wd (ie0_0_e_2_wd),
// from internal hardware
.de (1'b0),
.d ('0),
// to internal hardware
.qe (),
.q (reg2hw.ie0[2].q),
.ds (),
// to register interface (read)
.qs (ie0_0_e_2_qs)
);
// F[e_3]: 3:3
prim_subreg #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (1'h0)
) u_ie0_0_e_3 (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (ie0_0_we),
.wd (ie0_0_e_3_wd),
// from internal hardware
.de (1'b0),
.d ('0),
// to internal hardware
.qe (),
.q (reg2hw.ie0[3].q),
.ds (),
// to register interface (read)
.qs (ie0_0_e_3_qs)
);
// F[e_4]: 4:4
prim_subreg #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (1'h0)
) u_ie0_0_e_4 (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (ie0_0_we),
.wd (ie0_0_e_4_wd),
// from internal hardware
.de (1'b0),
.d ('0),
// to internal hardware
.qe (),
.q (reg2hw.ie0[4].q),
.ds (),
// to register interface (read)
.qs (ie0_0_e_4_qs)
);
// F[e_5]: 5:5
prim_subreg #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (1'h0)
) u_ie0_0_e_5 (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (ie0_0_we),
.wd (ie0_0_e_5_wd),
// from internal hardware
.de (1'b0),
.d ('0),
// to internal hardware
.qe (),
.q (reg2hw.ie0[5].q),
.ds (),
// to register interface (read)
.qs (ie0_0_e_5_qs)
);
// F[e_6]: 6:6
prim_subreg #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (1'h0)
) u_ie0_0_e_6 (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (ie0_0_we),
.wd (ie0_0_e_6_wd),
// from internal hardware
.de (1'b0),
.d ('0),
// to internal hardware
.qe (),
.q (reg2hw.ie0[6].q),
.ds (),
// to register interface (read)
.qs (ie0_0_e_6_qs)
);
// F[e_7]: 7:7
prim_subreg #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (1'h0)
) u_ie0_0_e_7 (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (ie0_0_we),
.wd (ie0_0_e_7_wd),
// from internal hardware
.de (1'b0),
.d ('0),
// to internal hardware
.qe (),
.q (reg2hw.ie0[7].q),
.ds (),
// to register interface (read)
.qs (ie0_0_e_7_qs)
);
// F[e_8]: 8:8
prim_subreg #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (1'h0)
) u_ie0_0_e_8 (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (ie0_0_we),
.wd (ie0_0_e_8_wd),
// from internal hardware
.de (1'b0),
.d ('0),
// to internal hardware
.qe (),
.q (reg2hw.ie0[8].q),
.ds (),
// to register interface (read)
.qs (ie0_0_e_8_qs)
);
// F[e_9]: 9:9
prim_subreg #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (1'h0)
) u_ie0_0_e_9 (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (ie0_0_we),
.wd (ie0_0_e_9_wd),
// from internal hardware
.de (1'b0),
.d ('0),
// to internal hardware
.qe (),
.q (reg2hw.ie0[9].q),
.ds (),
// to register interface (read)
.qs (ie0_0_e_9_qs)
);
// F[e_10]: 10:10
prim_subreg #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (1'h0)
) u_ie0_0_e_10 (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (ie0_0_we),
.wd (ie0_0_e_10_wd),
// from internal hardware
.de (1'b0),
.d ('0),
// to internal hardware
.qe (),
.q (reg2hw.ie0[10].q),
.ds (),
// to register interface (read)
.qs (ie0_0_e_10_qs)
);
// F[e_11]: 11:11
prim_subreg #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (1'h0)
) u_ie0_0_e_11 (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (ie0_0_we),
.wd (ie0_0_e_11_wd),
// from internal hardware
.de (1'b0),
.d ('0),
// to internal hardware
.qe (),
.q (reg2hw.ie0[11].q),
.ds (),
// to register interface (read)
.qs (ie0_0_e_11_qs)
);
// F[e_12]: 12:12
prim_subreg #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (1'h0)
) u_ie0_0_e_12 (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (ie0_0_we),
.wd (ie0_0_e_12_wd),
// from internal hardware
.de (1'b0),
.d ('0),
// to internal hardware
.qe (),
.q (reg2hw.ie0[12].q),
.ds (),
// to register interface (read)
.qs (ie0_0_e_12_qs)
);
// F[e_13]: 13:13
prim_subreg #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (1'h0)
) u_ie0_0_e_13 (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (ie0_0_we),
.wd (ie0_0_e_13_wd),
// from internal hardware
.de (1'b0),
.d ('0),
// to internal hardware
.qe (),
.q (reg2hw.ie0[13].q),
.ds (),
// to register interface (read)
.qs (ie0_0_e_13_qs)
);
// F[e_14]: 14:14
prim_subreg #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (1'h0)
) u_ie0_0_e_14 (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (ie0_0_we),
.wd (ie0_0_e_14_wd),
// from internal hardware
.de (1'b0),
.d ('0),
// to internal hardware
.qe (),
.q (reg2hw.ie0[14].q),
.ds (),
// to register interface (read)
.qs (ie0_0_e_14_qs)
);
// F[e_15]: 15:15
prim_subreg #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (1'h0)
) u_ie0_0_e_15 (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (ie0_0_we),
.wd (ie0_0_e_15_wd),
// from internal hardware
.de (1'b0),
.d ('0),
// to internal hardware
.qe (),
.q (reg2hw.ie0[15].q),
.ds (),
// to register interface (read)
.qs (ie0_0_e_15_qs)
);
// F[e_16]: 16:16
prim_subreg #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (1'h0)
) u_ie0_0_e_16 (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (ie0_0_we),
.wd (ie0_0_e_16_wd),
// from internal hardware
.de (1'b0),
.d ('0),
// to internal hardware
.qe (),
.q (reg2hw.ie0[16].q),
.ds (),
// to register interface (read)
.qs (ie0_0_e_16_qs)
);
// F[e_17]: 17:17
prim_subreg #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (1'h0)
) u_ie0_0_e_17 (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (ie0_0_we),
.wd (ie0_0_e_17_wd),
// from internal hardware
.de (1'b0),
.d ('0),
// to internal hardware
.qe (),
.q (reg2hw.ie0[17].q),
.ds (),
// to register interface (read)
.qs (ie0_0_e_17_qs)
);
// F[e_18]: 18:18
prim_subreg #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (1'h0)
) u_ie0_0_e_18 (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (ie0_0_we),
.wd (ie0_0_e_18_wd),
// from internal hardware
.de (1'b0),
.d ('0),
// to internal hardware
.qe (),
.q (reg2hw.ie0[18].q),
.ds (),
// to register interface (read)
.qs (ie0_0_e_18_qs)
);
// F[e_19]: 19:19
prim_subreg #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (1'h0)
) u_ie0_0_e_19 (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (ie0_0_we),
.wd (ie0_0_e_19_wd),
// from internal hardware
.de (1'b0),
.d ('0),
// to internal hardware
.qe (),
.q (reg2hw.ie0[19].q),
.ds (),
// to register interface (read)
.qs (ie0_0_e_19_qs)
);
// F[e_20]: 20:20
prim_subreg #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (1'h0)
) u_ie0_0_e_20 (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (ie0_0_we),
.wd (ie0_0_e_20_wd),
// from internal hardware
.de (1'b0),
.d ('0),
// to internal hardware
.qe (),
.q (reg2hw.ie0[20].q),
.ds (),
// to register interface (read)
.qs (ie0_0_e_20_qs)
);
// F[e_21]: 21:21
prim_subreg #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (1'h0)
) u_ie0_0_e_21 (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (ie0_0_we),
.wd (ie0_0_e_21_wd),
// from internal hardware
.de (1'b0),
.d ('0),
// to internal hardware
.qe (),
.q (reg2hw.ie0[21].q),
.ds (),
// to register interface (read)
.qs (ie0_0_e_21_qs)
);
// F[e_22]: 22:22
prim_subreg #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (1'h0)
) u_ie0_0_e_22 (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (ie0_0_we),
.wd (ie0_0_e_22_wd),
// from internal hardware
.de (1'b0),
.d ('0),
// to internal hardware
.qe (),
.q (reg2hw.ie0[22].q),
.ds (),
// to register interface (read)
.qs (ie0_0_e_22_qs)
);
// F[e_23]: 23:23
prim_subreg #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (1'h0)
) u_ie0_0_e_23 (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (ie0_0_we),
.wd (ie0_0_e_23_wd),
// from internal hardware
.de (1'b0),
.d ('0),
// to internal hardware
.qe (),
.q (reg2hw.ie0[23].q),
.ds (),
// to register interface (read)
.qs (ie0_0_e_23_qs)
);
// F[e_24]: 24:24
prim_subreg #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (1'h0)
) u_ie0_0_e_24 (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (ie0_0_we),
.wd (ie0_0_e_24_wd),
// from internal hardware
.de (1'b0),
.d ('0),
// to internal hardware
.qe (),
.q (reg2hw.ie0[24].q),
.ds (),
// to register interface (read)
.qs (ie0_0_e_24_qs)
);
// F[e_25]: 25:25
prim_subreg #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (1'h0)
) u_ie0_0_e_25 (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (ie0_0_we),
.wd (ie0_0_e_25_wd),
// from internal hardware
.de (1'b0),
.d ('0),
// to internal hardware
.qe (),
.q (reg2hw.ie0[25].q),
.ds (),
// to register interface (read)
.qs (ie0_0_e_25_qs)
);
// F[e_26]: 26:26
prim_subreg #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (1'h0)
) u_ie0_0_e_26 (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (ie0_0_we),
.wd (ie0_0_e_26_wd),
// from internal hardware
.de (1'b0),
.d ('0),
// to internal hardware
.qe (),
.q (reg2hw.ie0[26].q),
.ds (),
// to register interface (read)
.qs (ie0_0_e_26_qs)
);
// F[e_27]: 27:27
prim_subreg #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (1'h0)
) u_ie0_0_e_27 (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (ie0_0_we),
.wd (ie0_0_e_27_wd),
// from internal hardware
.de (1'b0),
.d ('0),
// to internal hardware
.qe (),
.q (reg2hw.ie0[27].q),
.ds (),
// to register interface (read)
.qs (ie0_0_e_27_qs)
);
// F[e_28]: 28:28
prim_subreg #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (1'h0)
) u_ie0_0_e_28 (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (ie0_0_we),
.wd (ie0_0_e_28_wd),
// from internal hardware
.de (1'b0),
.d ('0),
// to internal hardware
.qe (),
.q (reg2hw.ie0[28].q),
.ds (),
// to register interface (read)
.qs (ie0_0_e_28_qs)
);
// F[e_29]: 29:29
prim_subreg #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (1'h0)
) u_ie0_0_e_29 (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (ie0_0_we),
.wd (ie0_0_e_29_wd),
// from internal hardware
.de (1'b0),
.d ('0),
// to internal hardware
.qe (),
.q (reg2hw.ie0[29].q),
.ds (),
// to register interface (read)
.qs (ie0_0_e_29_qs)
);
// F[e_30]: 30:30
prim_subreg #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (1'h0)
) u_ie0_0_e_30 (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (ie0_0_we),
.wd (ie0_0_e_30_wd),
// from internal hardware
.de (1'b0),
.d ('0),
// to internal hardware
.qe (),
.q (reg2hw.ie0[30].q),
.ds (),
// to register interface (read)
.qs (ie0_0_e_30_qs)
);
// F[e_31]: 31:31
prim_subreg #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (1'h0)
) u_ie0_0_e_31 (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (ie0_0_we),
.wd (ie0_0_e_31_wd),
// from internal hardware
.de (1'b0),
.d ('0),
// to internal hardware
.qe (),
.q (reg2hw.ie0[31].q),
.ds (),
// to register interface (read)
.qs (ie0_0_e_31_qs)
);
// Subregister 1 of Multireg ie0
// R[ie0_1]: V(False)
// F[e_32]: 0:0
prim_subreg #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (1'h0)
) u_ie0_1_e_32 (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (ie0_1_we),
.wd (ie0_1_e_32_wd),
// from internal hardware
.de (1'b0),
.d ('0),
// to internal hardware
.qe (),
.q (reg2hw.ie0[32].q),
.ds (),
// to register interface (read)
.qs (ie0_1_e_32_qs)
);
// F[e_33]: 1:1
prim_subreg #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (1'h0)
) u_ie0_1_e_33 (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (ie0_1_we),
.wd (ie0_1_e_33_wd),
// from internal hardware
.de (1'b0),
.d ('0),
// to internal hardware
.qe (),
.q (reg2hw.ie0[33].q),
.ds (),
// to register interface (read)
.qs (ie0_1_e_33_qs)
);
// F[e_34]: 2:2
prim_subreg #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (1'h0)
) u_ie0_1_e_34 (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (ie0_1_we),
.wd (ie0_1_e_34_wd),
// from internal hardware
.de (1'b0),
.d ('0),
// to internal hardware
.qe (),
.q (reg2hw.ie0[34].q),
.ds (),
// to register interface (read)
.qs (ie0_1_e_34_qs)
);
// F[e_35]: 3:3
prim_subreg #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (1'h0)
) u_ie0_1_e_35 (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (ie0_1_we),
.wd (ie0_1_e_35_wd),
// from internal hardware
.de (1'b0),
.d ('0),
// to internal hardware
.qe (),
.q (reg2hw.ie0[35].q),
.ds (),
// to register interface (read)
.qs (ie0_1_e_35_qs)
);
// F[e_36]: 4:4
prim_subreg #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (1'h0)
) u_ie0_1_e_36 (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (ie0_1_we),
.wd (ie0_1_e_36_wd),
// from internal hardware
.de (1'b0),
.d ('0),
// to internal hardware
.qe (),
.q (reg2hw.ie0[36].q),
.ds (),
// to register interface (read)
.qs (ie0_1_e_36_qs)
);
// F[e_37]: 5:5
prim_subreg #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (1'h0)
) u_ie0_1_e_37 (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (ie0_1_we),
.wd (ie0_1_e_37_wd),
// from internal hardware
.de (1'b0),
.d ('0),
// to internal hardware
.qe (),
.q (reg2hw.ie0[37].q),
.ds (),
// to register interface (read)
.qs (ie0_1_e_37_qs)
);
// F[e_38]: 6:6
prim_subreg #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (1'h0)
) u_ie0_1_e_38 (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (ie0_1_we),
.wd (ie0_1_e_38_wd),
// from internal hardware
.de (1'b0),
.d ('0),
// to internal hardware
.qe (),
.q (reg2hw.ie0[38].q),
.ds (),
// to register interface (read)
.qs (ie0_1_e_38_qs)
);
// F[e_39]: 7:7
prim_subreg #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (1'h0)
) u_ie0_1_e_39 (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (ie0_1_we),
.wd (ie0_1_e_39_wd),
// from internal hardware
.de (1'b0),
.d ('0),
// to internal hardware
.qe (),
.q (reg2hw.ie0[39].q),
.ds (),
// to register interface (read)
.qs (ie0_1_e_39_qs)
);
// F[e_40]: 8:8
prim_subreg #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (1'h0)
) u_ie0_1_e_40 (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (ie0_1_we),
.wd (ie0_1_e_40_wd),
// from internal hardware
.de (1'b0),
.d ('0),
// to internal hardware
.qe (),
.q (reg2hw.ie0[40].q),
.ds (),
// to register interface (read)
.qs (ie0_1_e_40_qs)
);
// F[e_41]: 9:9
prim_subreg #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (1'h0)
) u_ie0_1_e_41 (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (ie0_1_we),
.wd (ie0_1_e_41_wd),
// from internal hardware
.de (1'b0),
.d ('0),
// to internal hardware
.qe (),
.q (reg2hw.ie0[41].q),
.ds (),
// to register interface (read)
.qs (ie0_1_e_41_qs)
);
// F[e_42]: 10:10
prim_subreg #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (1'h0)
) u_ie0_1_e_42 (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (ie0_1_we),
.wd (ie0_1_e_42_wd),
// from internal hardware
.de (1'b0),
.d ('0),
// to internal hardware
.qe (),
.q (reg2hw.ie0[42].q),
.ds (),
// to register interface (read)
.qs (ie0_1_e_42_qs)
);
// R[threshold0]: V(False)
prim_subreg #(
.DW (2),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (2'h0)
) u_threshold0 (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (threshold0_we),
.wd (threshold0_wd),
// from internal hardware
.de (1'b0),
.d ('0),
// to internal hardware
.qe (),
.q (reg2hw.threshold0.q),
.ds (),
// to register interface (read)
.qs (threshold0_qs)
);
// R[cc0]: V(True)
logic cc0_qe;
logic [0:0] cc0_flds_we;
assign cc0_qe = &cc0_flds_we;
prim_subreg_ext #(
.DW (6)
) u_cc0 (
.re (cc0_re),
.we (cc0_we),
.wd (cc0_wd),
.d (hw2reg.cc0.d),
.qre (reg2hw.cc0.re),
.qe (cc0_flds_we[0]),
.q (reg2hw.cc0.q),
.ds (),
.qs (cc0_qs)
);
assign reg2hw.cc0.qe = cc0_qe;
// R[msip0]: V(False)
prim_subreg #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (1'h0)
) u_msip0 (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (msip0_we),
.wd (msip0_wd),
// from internal hardware
.de (1'b0),
.d ('0),
// to internal hardware
.qe (),
.q (reg2hw.msip0.q),
.ds (),
// to register interface (read)
.qs (msip0_qs)
);
// R[alert_test]: V(True)
logic alert_test_qe;
logic [0:0] alert_test_flds_we;
assign alert_test_qe = &alert_test_flds_we;
prim_subreg_ext #(
.DW (1)
) u_alert_test (
.re (1'b0),
.we (alert_test_we),
.wd (alert_test_wd),
.d ('0),
.qre (),
.qe (alert_test_flds_we[0]),
.q (reg2hw.alert_test.q),
.ds (),
.qs ()
);
assign reg2hw.alert_test.qe = alert_test_qe;
logic [50:0] addr_hit;
always_comb begin
addr_hit = '0;
addr_hit[ 0] = (reg_addr == RV_PLIC_SMC_PRIO0_OFFSET);
addr_hit[ 1] = (reg_addr == RV_PLIC_SMC_PRIO1_OFFSET);
addr_hit[ 2] = (reg_addr == RV_PLIC_SMC_PRIO2_OFFSET);
addr_hit[ 3] = (reg_addr == RV_PLIC_SMC_PRIO3_OFFSET);
addr_hit[ 4] = (reg_addr == RV_PLIC_SMC_PRIO4_OFFSET);
addr_hit[ 5] = (reg_addr == RV_PLIC_SMC_PRIO5_OFFSET);
addr_hit[ 6] = (reg_addr == RV_PLIC_SMC_PRIO6_OFFSET);
addr_hit[ 7] = (reg_addr == RV_PLIC_SMC_PRIO7_OFFSET);
addr_hit[ 8] = (reg_addr == RV_PLIC_SMC_PRIO8_OFFSET);
addr_hit[ 9] = (reg_addr == RV_PLIC_SMC_PRIO9_OFFSET);
addr_hit[10] = (reg_addr == RV_PLIC_SMC_PRIO10_OFFSET);
addr_hit[11] = (reg_addr == RV_PLIC_SMC_PRIO11_OFFSET);
addr_hit[12] = (reg_addr == RV_PLIC_SMC_PRIO12_OFFSET);
addr_hit[13] = (reg_addr == RV_PLIC_SMC_PRIO13_OFFSET);
addr_hit[14] = (reg_addr == RV_PLIC_SMC_PRIO14_OFFSET);
addr_hit[15] = (reg_addr == RV_PLIC_SMC_PRIO15_OFFSET);
addr_hit[16] = (reg_addr == RV_PLIC_SMC_PRIO16_OFFSET);
addr_hit[17] = (reg_addr == RV_PLIC_SMC_PRIO17_OFFSET);
addr_hit[18] = (reg_addr == RV_PLIC_SMC_PRIO18_OFFSET);
addr_hit[19] = (reg_addr == RV_PLIC_SMC_PRIO19_OFFSET);
addr_hit[20] = (reg_addr == RV_PLIC_SMC_PRIO20_OFFSET);
addr_hit[21] = (reg_addr == RV_PLIC_SMC_PRIO21_OFFSET);
addr_hit[22] = (reg_addr == RV_PLIC_SMC_PRIO22_OFFSET);
addr_hit[23] = (reg_addr == RV_PLIC_SMC_PRIO23_OFFSET);
addr_hit[24] = (reg_addr == RV_PLIC_SMC_PRIO24_OFFSET);
addr_hit[25] = (reg_addr == RV_PLIC_SMC_PRIO25_OFFSET);
addr_hit[26] = (reg_addr == RV_PLIC_SMC_PRIO26_OFFSET);
addr_hit[27] = (reg_addr == RV_PLIC_SMC_PRIO27_OFFSET);
addr_hit[28] = (reg_addr == RV_PLIC_SMC_PRIO28_OFFSET);
addr_hit[29] = (reg_addr == RV_PLIC_SMC_PRIO29_OFFSET);
addr_hit[30] = (reg_addr == RV_PLIC_SMC_PRIO30_OFFSET);
addr_hit[31] = (reg_addr == RV_PLIC_SMC_PRIO31_OFFSET);
addr_hit[32] = (reg_addr == RV_PLIC_SMC_PRIO32_OFFSET);
addr_hit[33] = (reg_addr == RV_PLIC_SMC_PRIO33_OFFSET);
addr_hit[34] = (reg_addr == RV_PLIC_SMC_PRIO34_OFFSET);
addr_hit[35] = (reg_addr == RV_PLIC_SMC_PRIO35_OFFSET);
addr_hit[36] = (reg_addr == RV_PLIC_SMC_PRIO36_OFFSET);
addr_hit[37] = (reg_addr == RV_PLIC_SMC_PRIO37_OFFSET);
addr_hit[38] = (reg_addr == RV_PLIC_SMC_PRIO38_OFFSET);
addr_hit[39] = (reg_addr == RV_PLIC_SMC_PRIO39_OFFSET);
addr_hit[40] = (reg_addr == RV_PLIC_SMC_PRIO40_OFFSET);
addr_hit[41] = (reg_addr == RV_PLIC_SMC_PRIO41_OFFSET);
addr_hit[42] = (reg_addr == RV_PLIC_SMC_PRIO42_OFFSET);
addr_hit[43] = (reg_addr == RV_PLIC_SMC_IP_0_OFFSET);
addr_hit[44] = (reg_addr == RV_PLIC_SMC_IP_1_OFFSET);
addr_hit[45] = (reg_addr == RV_PLIC_SMC_IE0_0_OFFSET);
addr_hit[46] = (reg_addr == RV_PLIC_SMC_IE0_1_OFFSET);
addr_hit[47] = (reg_addr == RV_PLIC_SMC_THRESHOLD0_OFFSET);
addr_hit[48] = (reg_addr == RV_PLIC_SMC_CC0_OFFSET);
addr_hit[49] = (reg_addr == RV_PLIC_SMC_MSIP0_OFFSET);
addr_hit[50] = (reg_addr == RV_PLIC_SMC_ALERT_TEST_OFFSET);
end
assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ;
// Check sub-word write is permitted
always_comb begin
wr_err = (reg_we &
((addr_hit[ 0] & (|(RV_PLIC_SMC_PERMIT[ 0] & ~reg_be))) |
(addr_hit[ 1] & (|(RV_PLIC_SMC_PERMIT[ 1] & ~reg_be))) |
(addr_hit[ 2] & (|(RV_PLIC_SMC_PERMIT[ 2] & ~reg_be))) |
(addr_hit[ 3] & (|(RV_PLIC_SMC_PERMIT[ 3] & ~reg_be))) |
(addr_hit[ 4] & (|(RV_PLIC_SMC_PERMIT[ 4] & ~reg_be))) |
(addr_hit[ 5] & (|(RV_PLIC_SMC_PERMIT[ 5] & ~reg_be))) |
(addr_hit[ 6] & (|(RV_PLIC_SMC_PERMIT[ 6] & ~reg_be))) |
(addr_hit[ 7] & (|(RV_PLIC_SMC_PERMIT[ 7] & ~reg_be))) |
(addr_hit[ 8] & (|(RV_PLIC_SMC_PERMIT[ 8] & ~reg_be))) |
(addr_hit[ 9] & (|(RV_PLIC_SMC_PERMIT[ 9] & ~reg_be))) |
(addr_hit[10] & (|(RV_PLIC_SMC_PERMIT[10] & ~reg_be))) |
(addr_hit[11] & (|(RV_PLIC_SMC_PERMIT[11] & ~reg_be))) |
(addr_hit[12] & (|(RV_PLIC_SMC_PERMIT[12] & ~reg_be))) |
(addr_hit[13] & (|(RV_PLIC_SMC_PERMIT[13] & ~reg_be))) |
(addr_hit[14] & (|(RV_PLIC_SMC_PERMIT[14] & ~reg_be))) |
(addr_hit[15] & (|(RV_PLIC_SMC_PERMIT[15] & ~reg_be))) |
(addr_hit[16] & (|(RV_PLIC_SMC_PERMIT[16] & ~reg_be))) |
(addr_hit[17] & (|(RV_PLIC_SMC_PERMIT[17] & ~reg_be))) |
(addr_hit[18] & (|(RV_PLIC_SMC_PERMIT[18] & ~reg_be))) |
(addr_hit[19] & (|(RV_PLIC_SMC_PERMIT[19] & ~reg_be))) |
(addr_hit[20] & (|(RV_PLIC_SMC_PERMIT[20] & ~reg_be))) |
(addr_hit[21] & (|(RV_PLIC_SMC_PERMIT[21] & ~reg_be))) |
(addr_hit[22] & (|(RV_PLIC_SMC_PERMIT[22] & ~reg_be))) |
(addr_hit[23] & (|(RV_PLIC_SMC_PERMIT[23] & ~reg_be))) |
(addr_hit[24] & (|(RV_PLIC_SMC_PERMIT[24] & ~reg_be))) |
(addr_hit[25] & (|(RV_PLIC_SMC_PERMIT[25] & ~reg_be))) |
(addr_hit[26] & (|(RV_PLIC_SMC_PERMIT[26] & ~reg_be))) |
(addr_hit[27] & (|(RV_PLIC_SMC_PERMIT[27] & ~reg_be))) |
(addr_hit[28] & (|(RV_PLIC_SMC_PERMIT[28] & ~reg_be))) |
(addr_hit[29] & (|(RV_PLIC_SMC_PERMIT[29] & ~reg_be))) |
(addr_hit[30] & (|(RV_PLIC_SMC_PERMIT[30] & ~reg_be))) |
(addr_hit[31] & (|(RV_PLIC_SMC_PERMIT[31] & ~reg_be))) |
(addr_hit[32] & (|(RV_PLIC_SMC_PERMIT[32] & ~reg_be))) |
(addr_hit[33] & (|(RV_PLIC_SMC_PERMIT[33] & ~reg_be))) |
(addr_hit[34] & (|(RV_PLIC_SMC_PERMIT[34] & ~reg_be))) |
(addr_hit[35] & (|(RV_PLIC_SMC_PERMIT[35] & ~reg_be))) |
(addr_hit[36] & (|(RV_PLIC_SMC_PERMIT[36] & ~reg_be))) |
(addr_hit[37] & (|(RV_PLIC_SMC_PERMIT[37] & ~reg_be))) |
(addr_hit[38] & (|(RV_PLIC_SMC_PERMIT[38] & ~reg_be))) |
(addr_hit[39] & (|(RV_PLIC_SMC_PERMIT[39] & ~reg_be))) |
(addr_hit[40] & (|(RV_PLIC_SMC_PERMIT[40] & ~reg_be))) |
(addr_hit[41] & (|(RV_PLIC_SMC_PERMIT[41] & ~reg_be))) |
(addr_hit[42] & (|(RV_PLIC_SMC_PERMIT[42] & ~reg_be))) |
(addr_hit[43] & (|(RV_PLIC_SMC_PERMIT[43] & ~reg_be))) |
(addr_hit[44] & (|(RV_PLIC_SMC_PERMIT[44] & ~reg_be))) |
(addr_hit[45] & (|(RV_PLIC_SMC_PERMIT[45] & ~reg_be))) |
(addr_hit[46] & (|(RV_PLIC_SMC_PERMIT[46] & ~reg_be))) |
(addr_hit[47] & (|(RV_PLIC_SMC_PERMIT[47] & ~reg_be))) |
(addr_hit[48] & (|(RV_PLIC_SMC_PERMIT[48] & ~reg_be))) |
(addr_hit[49] & (|(RV_PLIC_SMC_PERMIT[49] & ~reg_be))) |
(addr_hit[50] & (|(RV_PLIC_SMC_PERMIT[50] & ~reg_be)))));
end
// Generate write-enables
assign prio0_we = addr_hit[0] & reg_we & !reg_error;
assign prio0_wd = reg_wdata[1:0];
assign prio1_we = addr_hit[1] & reg_we & !reg_error;
assign prio1_wd = reg_wdata[1:0];
assign prio2_we = addr_hit[2] & reg_we & !reg_error;
assign prio2_wd = reg_wdata[1:0];
assign prio3_we = addr_hit[3] & reg_we & !reg_error;
assign prio3_wd = reg_wdata[1:0];
assign prio4_we = addr_hit[4] & reg_we & !reg_error;
assign prio4_wd = reg_wdata[1:0];
assign prio5_we = addr_hit[5] & reg_we & !reg_error;
assign prio5_wd = reg_wdata[1:0];
assign prio6_we = addr_hit[6] & reg_we & !reg_error;
assign prio6_wd = reg_wdata[1:0];
assign prio7_we = addr_hit[7] & reg_we & !reg_error;
assign prio7_wd = reg_wdata[1:0];
assign prio8_we = addr_hit[8] & reg_we & !reg_error;
assign prio8_wd = reg_wdata[1:0];
assign prio9_we = addr_hit[9] & reg_we & !reg_error;
assign prio9_wd = reg_wdata[1:0];
assign prio10_we = addr_hit[10] & reg_we & !reg_error;
assign prio10_wd = reg_wdata[1:0];
assign prio11_we = addr_hit[11] & reg_we & !reg_error;
assign prio11_wd = reg_wdata[1:0];
assign prio12_we = addr_hit[12] & reg_we & !reg_error;
assign prio12_wd = reg_wdata[1:0];
assign prio13_we = addr_hit[13] & reg_we & !reg_error;
assign prio13_wd = reg_wdata[1:0];
assign prio14_we = addr_hit[14] & reg_we & !reg_error;
assign prio14_wd = reg_wdata[1:0];
assign prio15_we = addr_hit[15] & reg_we & !reg_error;
assign prio15_wd = reg_wdata[1:0];
assign prio16_we = addr_hit[16] & reg_we & !reg_error;
assign prio16_wd = reg_wdata[1:0];
assign prio17_we = addr_hit[17] & reg_we & !reg_error;
assign prio17_wd = reg_wdata[1:0];
assign prio18_we = addr_hit[18] & reg_we & !reg_error;
assign prio18_wd = reg_wdata[1:0];
assign prio19_we = addr_hit[19] & reg_we & !reg_error;
assign prio19_wd = reg_wdata[1:0];
assign prio20_we = addr_hit[20] & reg_we & !reg_error;
assign prio20_wd = reg_wdata[1:0];
assign prio21_we = addr_hit[21] & reg_we & !reg_error;
assign prio21_wd = reg_wdata[1:0];
assign prio22_we = addr_hit[22] & reg_we & !reg_error;
assign prio22_wd = reg_wdata[1:0];
assign prio23_we = addr_hit[23] & reg_we & !reg_error;
assign prio23_wd = reg_wdata[1:0];
assign prio24_we = addr_hit[24] & reg_we & !reg_error;
assign prio24_wd = reg_wdata[1:0];
assign prio25_we = addr_hit[25] & reg_we & !reg_error;
assign prio25_wd = reg_wdata[1:0];
assign prio26_we = addr_hit[26] & reg_we & !reg_error;
assign prio26_wd = reg_wdata[1:0];
assign prio27_we = addr_hit[27] & reg_we & !reg_error;
assign prio27_wd = reg_wdata[1:0];
assign prio28_we = addr_hit[28] & reg_we & !reg_error;
assign prio28_wd = reg_wdata[1:0];
assign prio29_we = addr_hit[29] & reg_we & !reg_error;
assign prio29_wd = reg_wdata[1:0];
assign prio30_we = addr_hit[30] & reg_we & !reg_error;
assign prio30_wd = reg_wdata[1:0];
assign prio31_we = addr_hit[31] & reg_we & !reg_error;
assign prio31_wd = reg_wdata[1:0];
assign prio32_we = addr_hit[32] & reg_we & !reg_error;
assign prio32_wd = reg_wdata[1:0];
assign prio33_we = addr_hit[33] & reg_we & !reg_error;
assign prio33_wd = reg_wdata[1:0];
assign prio34_we = addr_hit[34] & reg_we & !reg_error;
assign prio34_wd = reg_wdata[1:0];
assign prio35_we = addr_hit[35] & reg_we & !reg_error;
assign prio35_wd = reg_wdata[1:0];
assign prio36_we = addr_hit[36] & reg_we & !reg_error;
assign prio36_wd = reg_wdata[1:0];
assign prio37_we = addr_hit[37] & reg_we & !reg_error;
assign prio37_wd = reg_wdata[1:0];
assign prio38_we = addr_hit[38] & reg_we & !reg_error;
assign prio38_wd = reg_wdata[1:0];
assign prio39_we = addr_hit[39] & reg_we & !reg_error;
assign prio39_wd = reg_wdata[1:0];
assign prio40_we = addr_hit[40] & reg_we & !reg_error;
assign prio40_wd = reg_wdata[1:0];
assign prio41_we = addr_hit[41] & reg_we & !reg_error;
assign prio41_wd = reg_wdata[1:0];
assign prio42_we = addr_hit[42] & reg_we & !reg_error;
assign prio42_wd = reg_wdata[1:0];
assign ie0_0_we = addr_hit[45] & reg_we & !reg_error;
assign ie0_0_e_0_wd = reg_wdata[0];
assign ie0_0_e_1_wd = reg_wdata[1];
assign ie0_0_e_2_wd = reg_wdata[2];
assign ie0_0_e_3_wd = reg_wdata[3];
assign ie0_0_e_4_wd = reg_wdata[4];
assign ie0_0_e_5_wd = reg_wdata[5];
assign ie0_0_e_6_wd = reg_wdata[6];
assign ie0_0_e_7_wd = reg_wdata[7];
assign ie0_0_e_8_wd = reg_wdata[8];
assign ie0_0_e_9_wd = reg_wdata[9];
assign ie0_0_e_10_wd = reg_wdata[10];
assign ie0_0_e_11_wd = reg_wdata[11];
assign ie0_0_e_12_wd = reg_wdata[12];
assign ie0_0_e_13_wd = reg_wdata[13];
assign ie0_0_e_14_wd = reg_wdata[14];
assign ie0_0_e_15_wd = reg_wdata[15];
assign ie0_0_e_16_wd = reg_wdata[16];
assign ie0_0_e_17_wd = reg_wdata[17];
assign ie0_0_e_18_wd = reg_wdata[18];
assign ie0_0_e_19_wd = reg_wdata[19];
assign ie0_0_e_20_wd = reg_wdata[20];
assign ie0_0_e_21_wd = reg_wdata[21];
assign ie0_0_e_22_wd = reg_wdata[22];
assign ie0_0_e_23_wd = reg_wdata[23];
assign ie0_0_e_24_wd = reg_wdata[24];
assign ie0_0_e_25_wd = reg_wdata[25];
assign ie0_0_e_26_wd = reg_wdata[26];
assign ie0_0_e_27_wd = reg_wdata[27];
assign ie0_0_e_28_wd = reg_wdata[28];
assign ie0_0_e_29_wd = reg_wdata[29];
assign ie0_0_e_30_wd = reg_wdata[30];
assign ie0_0_e_31_wd = reg_wdata[31];
assign ie0_1_we = addr_hit[46] & reg_we & !reg_error;
assign ie0_1_e_32_wd = reg_wdata[0];
assign ie0_1_e_33_wd = reg_wdata[1];
assign ie0_1_e_34_wd = reg_wdata[2];
assign ie0_1_e_35_wd = reg_wdata[3];
assign ie0_1_e_36_wd = reg_wdata[4];
assign ie0_1_e_37_wd = reg_wdata[5];
assign ie0_1_e_38_wd = reg_wdata[6];
assign ie0_1_e_39_wd = reg_wdata[7];
assign ie0_1_e_40_wd = reg_wdata[8];
assign ie0_1_e_41_wd = reg_wdata[9];
assign ie0_1_e_42_wd = reg_wdata[10];
assign threshold0_we = addr_hit[47] & reg_we & !reg_error;
assign threshold0_wd = reg_wdata[1:0];
assign cc0_re = addr_hit[48] & reg_re & !reg_error;
assign cc0_we = addr_hit[48] & reg_we & !reg_error;
assign cc0_wd = reg_wdata[5:0];
assign msip0_we = addr_hit[49] & reg_we & !reg_error;
assign msip0_wd = reg_wdata[0];
assign alert_test_we = addr_hit[50] & reg_we & !reg_error;
assign alert_test_wd = reg_wdata[0];
// Assign write-enables to checker logic vector.
always_comb begin
reg_we_check = '0;
reg_we_check[0] = prio0_we;
reg_we_check[1] = prio1_we;
reg_we_check[2] = prio2_we;
reg_we_check[3] = prio3_we;
reg_we_check[4] = prio4_we;
reg_we_check[5] = prio5_we;
reg_we_check[6] = prio6_we;
reg_we_check[7] = prio7_we;
reg_we_check[8] = prio8_we;
reg_we_check[9] = prio9_we;
reg_we_check[10] = prio10_we;
reg_we_check[11] = prio11_we;
reg_we_check[12] = prio12_we;
reg_we_check[13] = prio13_we;
reg_we_check[14] = prio14_we;
reg_we_check[15] = prio15_we;
reg_we_check[16] = prio16_we;
reg_we_check[17] = prio17_we;
reg_we_check[18] = prio18_we;
reg_we_check[19] = prio19_we;
reg_we_check[20] = prio20_we;
reg_we_check[21] = prio21_we;
reg_we_check[22] = prio22_we;
reg_we_check[23] = prio23_we;
reg_we_check[24] = prio24_we;
reg_we_check[25] = prio25_we;
reg_we_check[26] = prio26_we;
reg_we_check[27] = prio27_we;
reg_we_check[28] = prio28_we;
reg_we_check[29] = prio29_we;
reg_we_check[30] = prio30_we;
reg_we_check[31] = prio31_we;
reg_we_check[32] = prio32_we;
reg_we_check[33] = prio33_we;
reg_we_check[34] = prio34_we;
reg_we_check[35] = prio35_we;
reg_we_check[36] = prio36_we;
reg_we_check[37] = prio37_we;
reg_we_check[38] = prio38_we;
reg_we_check[39] = prio39_we;
reg_we_check[40] = prio40_we;
reg_we_check[41] = prio41_we;
reg_we_check[42] = prio42_we;
reg_we_check[43] = 1'b0;
reg_we_check[44] = 1'b0;
reg_we_check[45] = ie0_0_we;
reg_we_check[46] = ie0_1_we;
reg_we_check[47] = threshold0_we;
reg_we_check[48] = cc0_we;
reg_we_check[49] = msip0_we;
reg_we_check[50] = alert_test_we;
end
// Read data return
always_comb begin
reg_rdata_next = '0;
unique case (1'b1)
addr_hit[0]: begin
reg_rdata_next[1:0] = prio0_qs;
end
addr_hit[1]: begin
reg_rdata_next[1:0] = prio1_qs;
end
addr_hit[2]: begin
reg_rdata_next[1:0] = prio2_qs;
end
addr_hit[3]: begin
reg_rdata_next[1:0] = prio3_qs;
end
addr_hit[4]: begin
reg_rdata_next[1:0] = prio4_qs;
end
addr_hit[5]: begin
reg_rdata_next[1:0] = prio5_qs;
end
addr_hit[6]: begin
reg_rdata_next[1:0] = prio6_qs;
end
addr_hit[7]: begin
reg_rdata_next[1:0] = prio7_qs;
end
addr_hit[8]: begin
reg_rdata_next[1:0] = prio8_qs;
end
addr_hit[9]: begin
reg_rdata_next[1:0] = prio9_qs;
end
addr_hit[10]: begin
reg_rdata_next[1:0] = prio10_qs;
end
addr_hit[11]: begin
reg_rdata_next[1:0] = prio11_qs;
end
addr_hit[12]: begin
reg_rdata_next[1:0] = prio12_qs;
end
addr_hit[13]: begin
reg_rdata_next[1:0] = prio13_qs;
end
addr_hit[14]: begin
reg_rdata_next[1:0] = prio14_qs;
end
addr_hit[15]: begin
reg_rdata_next[1:0] = prio15_qs;
end
addr_hit[16]: begin
reg_rdata_next[1:0] = prio16_qs;
end
addr_hit[17]: begin
reg_rdata_next[1:0] = prio17_qs;
end
addr_hit[18]: begin
reg_rdata_next[1:0] = prio18_qs;
end
addr_hit[19]: begin
reg_rdata_next[1:0] = prio19_qs;
end
addr_hit[20]: begin
reg_rdata_next[1:0] = prio20_qs;
end
addr_hit[21]: begin
reg_rdata_next[1:0] = prio21_qs;
end
addr_hit[22]: begin
reg_rdata_next[1:0] = prio22_qs;
end
addr_hit[23]: begin
reg_rdata_next[1:0] = prio23_qs;
end
addr_hit[24]: begin
reg_rdata_next[1:0] = prio24_qs;
end
addr_hit[25]: begin
reg_rdata_next[1:0] = prio25_qs;
end
addr_hit[26]: begin
reg_rdata_next[1:0] = prio26_qs;
end
addr_hit[27]: begin
reg_rdata_next[1:0] = prio27_qs;
end
addr_hit[28]: begin
reg_rdata_next[1:0] = prio28_qs;
end
addr_hit[29]: begin
reg_rdata_next[1:0] = prio29_qs;
end
addr_hit[30]: begin
reg_rdata_next[1:0] = prio30_qs;
end
addr_hit[31]: begin
reg_rdata_next[1:0] = prio31_qs;
end
addr_hit[32]: begin
reg_rdata_next[1:0] = prio32_qs;
end
addr_hit[33]: begin
reg_rdata_next[1:0] = prio33_qs;
end
addr_hit[34]: begin
reg_rdata_next[1:0] = prio34_qs;
end
addr_hit[35]: begin
reg_rdata_next[1:0] = prio35_qs;
end
addr_hit[36]: begin
reg_rdata_next[1:0] = prio36_qs;
end
addr_hit[37]: begin
reg_rdata_next[1:0] = prio37_qs;
end
addr_hit[38]: begin
reg_rdata_next[1:0] = prio38_qs;
end
addr_hit[39]: begin
reg_rdata_next[1:0] = prio39_qs;
end
addr_hit[40]: begin
reg_rdata_next[1:0] = prio40_qs;
end
addr_hit[41]: begin
reg_rdata_next[1:0] = prio41_qs;
end
addr_hit[42]: begin
reg_rdata_next[1:0] = prio42_qs;
end
addr_hit[43]: begin
reg_rdata_next[0] = ip_0_p_0_qs;
reg_rdata_next[1] = ip_0_p_1_qs;
reg_rdata_next[2] = ip_0_p_2_qs;
reg_rdata_next[3] = ip_0_p_3_qs;
reg_rdata_next[4] = ip_0_p_4_qs;
reg_rdata_next[5] = ip_0_p_5_qs;
reg_rdata_next[6] = ip_0_p_6_qs;
reg_rdata_next[7] = ip_0_p_7_qs;
reg_rdata_next[8] = ip_0_p_8_qs;
reg_rdata_next[9] = ip_0_p_9_qs;
reg_rdata_next[10] = ip_0_p_10_qs;
reg_rdata_next[11] = ip_0_p_11_qs;
reg_rdata_next[12] = ip_0_p_12_qs;
reg_rdata_next[13] = ip_0_p_13_qs;
reg_rdata_next[14] = ip_0_p_14_qs;
reg_rdata_next[15] = ip_0_p_15_qs;
reg_rdata_next[16] = ip_0_p_16_qs;
reg_rdata_next[17] = ip_0_p_17_qs;
reg_rdata_next[18] = ip_0_p_18_qs;
reg_rdata_next[19] = ip_0_p_19_qs;
reg_rdata_next[20] = ip_0_p_20_qs;
reg_rdata_next[21] = ip_0_p_21_qs;
reg_rdata_next[22] = ip_0_p_22_qs;
reg_rdata_next[23] = ip_0_p_23_qs;
reg_rdata_next[24] = ip_0_p_24_qs;
reg_rdata_next[25] = ip_0_p_25_qs;
reg_rdata_next[26] = ip_0_p_26_qs;
reg_rdata_next[27] = ip_0_p_27_qs;
reg_rdata_next[28] = ip_0_p_28_qs;
reg_rdata_next[29] = ip_0_p_29_qs;
reg_rdata_next[30] = ip_0_p_30_qs;
reg_rdata_next[31] = ip_0_p_31_qs;
end
addr_hit[44]: begin
reg_rdata_next[0] = ip_1_p_32_qs;
reg_rdata_next[1] = ip_1_p_33_qs;
reg_rdata_next[2] = ip_1_p_34_qs;
reg_rdata_next[3] = ip_1_p_35_qs;
reg_rdata_next[4] = ip_1_p_36_qs;
reg_rdata_next[5] = ip_1_p_37_qs;
reg_rdata_next[6] = ip_1_p_38_qs;
reg_rdata_next[7] = ip_1_p_39_qs;
reg_rdata_next[8] = ip_1_p_40_qs;
reg_rdata_next[9] = ip_1_p_41_qs;
reg_rdata_next[10] = ip_1_p_42_qs;
end
addr_hit[45]: begin
reg_rdata_next[0] = ie0_0_e_0_qs;
reg_rdata_next[1] = ie0_0_e_1_qs;
reg_rdata_next[2] = ie0_0_e_2_qs;
reg_rdata_next[3] = ie0_0_e_3_qs;
reg_rdata_next[4] = ie0_0_e_4_qs;
reg_rdata_next[5] = ie0_0_e_5_qs;
reg_rdata_next[6] = ie0_0_e_6_qs;
reg_rdata_next[7] = ie0_0_e_7_qs;
reg_rdata_next[8] = ie0_0_e_8_qs;
reg_rdata_next[9] = ie0_0_e_9_qs;
reg_rdata_next[10] = ie0_0_e_10_qs;
reg_rdata_next[11] = ie0_0_e_11_qs;
reg_rdata_next[12] = ie0_0_e_12_qs;
reg_rdata_next[13] = ie0_0_e_13_qs;
reg_rdata_next[14] = ie0_0_e_14_qs;
reg_rdata_next[15] = ie0_0_e_15_qs;
reg_rdata_next[16] = ie0_0_e_16_qs;
reg_rdata_next[17] = ie0_0_e_17_qs;
reg_rdata_next[18] = ie0_0_e_18_qs;
reg_rdata_next[19] = ie0_0_e_19_qs;
reg_rdata_next[20] = ie0_0_e_20_qs;
reg_rdata_next[21] = ie0_0_e_21_qs;
reg_rdata_next[22] = ie0_0_e_22_qs;
reg_rdata_next[23] = ie0_0_e_23_qs;
reg_rdata_next[24] = ie0_0_e_24_qs;
reg_rdata_next[25] = ie0_0_e_25_qs;
reg_rdata_next[26] = ie0_0_e_26_qs;
reg_rdata_next[27] = ie0_0_e_27_qs;
reg_rdata_next[28] = ie0_0_e_28_qs;
reg_rdata_next[29] = ie0_0_e_29_qs;
reg_rdata_next[30] = ie0_0_e_30_qs;
reg_rdata_next[31] = ie0_0_e_31_qs;
end
addr_hit[46]: begin
reg_rdata_next[0] = ie0_1_e_32_qs;
reg_rdata_next[1] = ie0_1_e_33_qs;
reg_rdata_next[2] = ie0_1_e_34_qs;
reg_rdata_next[3] = ie0_1_e_35_qs;
reg_rdata_next[4] = ie0_1_e_36_qs;
reg_rdata_next[5] = ie0_1_e_37_qs;
reg_rdata_next[6] = ie0_1_e_38_qs;
reg_rdata_next[7] = ie0_1_e_39_qs;
reg_rdata_next[8] = ie0_1_e_40_qs;
reg_rdata_next[9] = ie0_1_e_41_qs;
reg_rdata_next[10] = ie0_1_e_42_qs;
end
addr_hit[47]: begin
reg_rdata_next[1:0] = threshold0_qs;
end
addr_hit[48]: begin
reg_rdata_next[5:0] = cc0_qs;
end
addr_hit[49]: begin
reg_rdata_next[0] = msip0_qs;
end
addr_hit[50]: begin
reg_rdata_next[0] = '0;
end
default: begin
reg_rdata_next = '1;
end
endcase
end
// shadow busy
logic shadow_busy;
assign shadow_busy = 1'b0;
// register busy
assign reg_busy = shadow_busy;
// Unused signal tieoff
// wdata / byte enable are not always fully used
// add a blanket unused statement to handle lint waivers
logic unused_wdata;
logic unused_be;
assign unused_wdata = ^reg_wdata;
assign unused_be = ^reg_be;
// Assertions for Register Interface
`ASSERT_PULSE(wePulse, reg_we, clk_i, !rst_ni)
`ASSERT_PULSE(rePulse, reg_re, clk_i, !rst_ni)
`ASSERT(reAfterRv, $rose(reg_re || reg_we) |=> tl_o_pre.d_valid, clk_i, !rst_ni)
`ASSERT(en2addrHit, (reg_we || reg_re) |-> $onehot0(addr_hit), clk_i, !rst_ni)
// this is formulated as an assumption such that the FPV testbenches do disprove this
// property by mistake
//`ASSUME(reqParity, tl_reg_h2d.a_valid |-> tl_reg_h2d.a_user.chk_en == tlul_pkg::CheckDis)
endmodule