blob: 0a3227b4039e0378f4a59af4079051d12b2e2d6d [file] [log] [blame]
// Copyright lowRISC contributors.
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0
//
// Register Package auto-generated by `reggen` containing data structure
package rv_plic_smc_reg_pkg;
// Param list
parameter int NumSrc = 43;
parameter int NumTarget = 1;
parameter int PrioWidth = 2;
parameter int NumAlerts = 1;
// Address widths within the block
parameter int BlockAw = 27;
////////////////////////////
// Typedefs for registers //
////////////////////////////
typedef struct packed {
logic [1:0] q;
} rv_plic_smc_reg2hw_prio0_reg_t;
typedef struct packed {
logic [1:0] q;
} rv_plic_smc_reg2hw_prio1_reg_t;
typedef struct packed {
logic [1:0] q;
} rv_plic_smc_reg2hw_prio2_reg_t;
typedef struct packed {
logic [1:0] q;
} rv_plic_smc_reg2hw_prio3_reg_t;
typedef struct packed {
logic [1:0] q;
} rv_plic_smc_reg2hw_prio4_reg_t;
typedef struct packed {
logic [1:0] q;
} rv_plic_smc_reg2hw_prio5_reg_t;
typedef struct packed {
logic [1:0] q;
} rv_plic_smc_reg2hw_prio6_reg_t;
typedef struct packed {
logic [1:0] q;
} rv_plic_smc_reg2hw_prio7_reg_t;
typedef struct packed {
logic [1:0] q;
} rv_plic_smc_reg2hw_prio8_reg_t;
typedef struct packed {
logic [1:0] q;
} rv_plic_smc_reg2hw_prio9_reg_t;
typedef struct packed {
logic [1:0] q;
} rv_plic_smc_reg2hw_prio10_reg_t;
typedef struct packed {
logic [1:0] q;
} rv_plic_smc_reg2hw_prio11_reg_t;
typedef struct packed {
logic [1:0] q;
} rv_plic_smc_reg2hw_prio12_reg_t;
typedef struct packed {
logic [1:0] q;
} rv_plic_smc_reg2hw_prio13_reg_t;
typedef struct packed {
logic [1:0] q;
} rv_plic_smc_reg2hw_prio14_reg_t;
typedef struct packed {
logic [1:0] q;
} rv_plic_smc_reg2hw_prio15_reg_t;
typedef struct packed {
logic [1:0] q;
} rv_plic_smc_reg2hw_prio16_reg_t;
typedef struct packed {
logic [1:0] q;
} rv_plic_smc_reg2hw_prio17_reg_t;
typedef struct packed {
logic [1:0] q;
} rv_plic_smc_reg2hw_prio18_reg_t;
typedef struct packed {
logic [1:0] q;
} rv_plic_smc_reg2hw_prio19_reg_t;
typedef struct packed {
logic [1:0] q;
} rv_plic_smc_reg2hw_prio20_reg_t;
typedef struct packed {
logic [1:0] q;
} rv_plic_smc_reg2hw_prio21_reg_t;
typedef struct packed {
logic [1:0] q;
} rv_plic_smc_reg2hw_prio22_reg_t;
typedef struct packed {
logic [1:0] q;
} rv_plic_smc_reg2hw_prio23_reg_t;
typedef struct packed {
logic [1:0] q;
} rv_plic_smc_reg2hw_prio24_reg_t;
typedef struct packed {
logic [1:0] q;
} rv_plic_smc_reg2hw_prio25_reg_t;
typedef struct packed {
logic [1:0] q;
} rv_plic_smc_reg2hw_prio26_reg_t;
typedef struct packed {
logic [1:0] q;
} rv_plic_smc_reg2hw_prio27_reg_t;
typedef struct packed {
logic [1:0] q;
} rv_plic_smc_reg2hw_prio28_reg_t;
typedef struct packed {
logic [1:0] q;
} rv_plic_smc_reg2hw_prio29_reg_t;
typedef struct packed {
logic [1:0] q;
} rv_plic_smc_reg2hw_prio30_reg_t;
typedef struct packed {
logic [1:0] q;
} rv_plic_smc_reg2hw_prio31_reg_t;
typedef struct packed {
logic [1:0] q;
} rv_plic_smc_reg2hw_prio32_reg_t;
typedef struct packed {
logic [1:0] q;
} rv_plic_smc_reg2hw_prio33_reg_t;
typedef struct packed {
logic [1:0] q;
} rv_plic_smc_reg2hw_prio34_reg_t;
typedef struct packed {
logic [1:0] q;
} rv_plic_smc_reg2hw_prio35_reg_t;
typedef struct packed {
logic [1:0] q;
} rv_plic_smc_reg2hw_prio36_reg_t;
typedef struct packed {
logic [1:0] q;
} rv_plic_smc_reg2hw_prio37_reg_t;
typedef struct packed {
logic [1:0] q;
} rv_plic_smc_reg2hw_prio38_reg_t;
typedef struct packed {
logic [1:0] q;
} rv_plic_smc_reg2hw_prio39_reg_t;
typedef struct packed {
logic [1:0] q;
} rv_plic_smc_reg2hw_prio40_reg_t;
typedef struct packed {
logic [1:0] q;
} rv_plic_smc_reg2hw_prio41_reg_t;
typedef struct packed {
logic [1:0] q;
} rv_plic_smc_reg2hw_prio42_reg_t;
typedef struct packed {
logic q;
} rv_plic_smc_reg2hw_ie0_mreg_t;
typedef struct packed {
logic [1:0] q;
} rv_plic_smc_reg2hw_threshold0_reg_t;
typedef struct packed {
logic [5:0] q;
logic qe;
logic re;
} rv_plic_smc_reg2hw_cc0_reg_t;
typedef struct packed {
logic q;
} rv_plic_smc_reg2hw_msip0_reg_t;
typedef struct packed {
logic q;
logic qe;
} rv_plic_smc_reg2hw_alert_test_reg_t;
typedef struct packed {
logic d;
logic de;
} rv_plic_smc_hw2reg_ip_mreg_t;
typedef struct packed {
logic [5:0] d;
} rv_plic_smc_hw2reg_cc0_reg_t;
// Register -> HW type
typedef struct packed {
rv_plic_smc_reg2hw_prio0_reg_t prio0; // [141:140]
rv_plic_smc_reg2hw_prio1_reg_t prio1; // [139:138]
rv_plic_smc_reg2hw_prio2_reg_t prio2; // [137:136]
rv_plic_smc_reg2hw_prio3_reg_t prio3; // [135:134]
rv_plic_smc_reg2hw_prio4_reg_t prio4; // [133:132]
rv_plic_smc_reg2hw_prio5_reg_t prio5; // [131:130]
rv_plic_smc_reg2hw_prio6_reg_t prio6; // [129:128]
rv_plic_smc_reg2hw_prio7_reg_t prio7; // [127:126]
rv_plic_smc_reg2hw_prio8_reg_t prio8; // [125:124]
rv_plic_smc_reg2hw_prio9_reg_t prio9; // [123:122]
rv_plic_smc_reg2hw_prio10_reg_t prio10; // [121:120]
rv_plic_smc_reg2hw_prio11_reg_t prio11; // [119:118]
rv_plic_smc_reg2hw_prio12_reg_t prio12; // [117:116]
rv_plic_smc_reg2hw_prio13_reg_t prio13; // [115:114]
rv_plic_smc_reg2hw_prio14_reg_t prio14; // [113:112]
rv_plic_smc_reg2hw_prio15_reg_t prio15; // [111:110]
rv_plic_smc_reg2hw_prio16_reg_t prio16; // [109:108]
rv_plic_smc_reg2hw_prio17_reg_t prio17; // [107:106]
rv_plic_smc_reg2hw_prio18_reg_t prio18; // [105:104]
rv_plic_smc_reg2hw_prio19_reg_t prio19; // [103:102]
rv_plic_smc_reg2hw_prio20_reg_t prio20; // [101:100]
rv_plic_smc_reg2hw_prio21_reg_t prio21; // [99:98]
rv_plic_smc_reg2hw_prio22_reg_t prio22; // [97:96]
rv_plic_smc_reg2hw_prio23_reg_t prio23; // [95:94]
rv_plic_smc_reg2hw_prio24_reg_t prio24; // [93:92]
rv_plic_smc_reg2hw_prio25_reg_t prio25; // [91:90]
rv_plic_smc_reg2hw_prio26_reg_t prio26; // [89:88]
rv_plic_smc_reg2hw_prio27_reg_t prio27; // [87:86]
rv_plic_smc_reg2hw_prio28_reg_t prio28; // [85:84]
rv_plic_smc_reg2hw_prio29_reg_t prio29; // [83:82]
rv_plic_smc_reg2hw_prio30_reg_t prio30; // [81:80]
rv_plic_smc_reg2hw_prio31_reg_t prio31; // [79:78]
rv_plic_smc_reg2hw_prio32_reg_t prio32; // [77:76]
rv_plic_smc_reg2hw_prio33_reg_t prio33; // [75:74]
rv_plic_smc_reg2hw_prio34_reg_t prio34; // [73:72]
rv_plic_smc_reg2hw_prio35_reg_t prio35; // [71:70]
rv_plic_smc_reg2hw_prio36_reg_t prio36; // [69:68]
rv_plic_smc_reg2hw_prio37_reg_t prio37; // [67:66]
rv_plic_smc_reg2hw_prio38_reg_t prio38; // [65:64]
rv_plic_smc_reg2hw_prio39_reg_t prio39; // [63:62]
rv_plic_smc_reg2hw_prio40_reg_t prio40; // [61:60]
rv_plic_smc_reg2hw_prio41_reg_t prio41; // [59:58]
rv_plic_smc_reg2hw_prio42_reg_t prio42; // [57:56]
rv_plic_smc_reg2hw_ie0_mreg_t [42:0] ie0; // [55:13]
rv_plic_smc_reg2hw_threshold0_reg_t threshold0; // [12:11]
rv_plic_smc_reg2hw_cc0_reg_t cc0; // [10:3]
rv_plic_smc_reg2hw_msip0_reg_t msip0; // [2:2]
rv_plic_smc_reg2hw_alert_test_reg_t alert_test; // [1:0]
} rv_plic_smc_reg2hw_t;
// HW -> register type
typedef struct packed {
rv_plic_smc_hw2reg_ip_mreg_t [42:0] ip; // [91:6]
rv_plic_smc_hw2reg_cc0_reg_t cc0; // [5:0]
} rv_plic_smc_hw2reg_t;
// Register offsets
parameter logic [BlockAw-1:0] RV_PLIC_SMC_PRIO0_OFFSET = 27'h 0;
parameter logic [BlockAw-1:0] RV_PLIC_SMC_PRIO1_OFFSET = 27'h 4;
parameter logic [BlockAw-1:0] RV_PLIC_SMC_PRIO2_OFFSET = 27'h 8;
parameter logic [BlockAw-1:0] RV_PLIC_SMC_PRIO3_OFFSET = 27'h c;
parameter logic [BlockAw-1:0] RV_PLIC_SMC_PRIO4_OFFSET = 27'h 10;
parameter logic [BlockAw-1:0] RV_PLIC_SMC_PRIO5_OFFSET = 27'h 14;
parameter logic [BlockAw-1:0] RV_PLIC_SMC_PRIO6_OFFSET = 27'h 18;
parameter logic [BlockAw-1:0] RV_PLIC_SMC_PRIO7_OFFSET = 27'h 1c;
parameter logic [BlockAw-1:0] RV_PLIC_SMC_PRIO8_OFFSET = 27'h 20;
parameter logic [BlockAw-1:0] RV_PLIC_SMC_PRIO9_OFFSET = 27'h 24;
parameter logic [BlockAw-1:0] RV_PLIC_SMC_PRIO10_OFFSET = 27'h 28;
parameter logic [BlockAw-1:0] RV_PLIC_SMC_PRIO11_OFFSET = 27'h 2c;
parameter logic [BlockAw-1:0] RV_PLIC_SMC_PRIO12_OFFSET = 27'h 30;
parameter logic [BlockAw-1:0] RV_PLIC_SMC_PRIO13_OFFSET = 27'h 34;
parameter logic [BlockAw-1:0] RV_PLIC_SMC_PRIO14_OFFSET = 27'h 38;
parameter logic [BlockAw-1:0] RV_PLIC_SMC_PRIO15_OFFSET = 27'h 3c;
parameter logic [BlockAw-1:0] RV_PLIC_SMC_PRIO16_OFFSET = 27'h 40;
parameter logic [BlockAw-1:0] RV_PLIC_SMC_PRIO17_OFFSET = 27'h 44;
parameter logic [BlockAw-1:0] RV_PLIC_SMC_PRIO18_OFFSET = 27'h 48;
parameter logic [BlockAw-1:0] RV_PLIC_SMC_PRIO19_OFFSET = 27'h 4c;
parameter logic [BlockAw-1:0] RV_PLIC_SMC_PRIO20_OFFSET = 27'h 50;
parameter logic [BlockAw-1:0] RV_PLIC_SMC_PRIO21_OFFSET = 27'h 54;
parameter logic [BlockAw-1:0] RV_PLIC_SMC_PRIO22_OFFSET = 27'h 58;
parameter logic [BlockAw-1:0] RV_PLIC_SMC_PRIO23_OFFSET = 27'h 5c;
parameter logic [BlockAw-1:0] RV_PLIC_SMC_PRIO24_OFFSET = 27'h 60;
parameter logic [BlockAw-1:0] RV_PLIC_SMC_PRIO25_OFFSET = 27'h 64;
parameter logic [BlockAw-1:0] RV_PLIC_SMC_PRIO26_OFFSET = 27'h 68;
parameter logic [BlockAw-1:0] RV_PLIC_SMC_PRIO27_OFFSET = 27'h 6c;
parameter logic [BlockAw-1:0] RV_PLIC_SMC_PRIO28_OFFSET = 27'h 70;
parameter logic [BlockAw-1:0] RV_PLIC_SMC_PRIO29_OFFSET = 27'h 74;
parameter logic [BlockAw-1:0] RV_PLIC_SMC_PRIO30_OFFSET = 27'h 78;
parameter logic [BlockAw-1:0] RV_PLIC_SMC_PRIO31_OFFSET = 27'h 7c;
parameter logic [BlockAw-1:0] RV_PLIC_SMC_PRIO32_OFFSET = 27'h 80;
parameter logic [BlockAw-1:0] RV_PLIC_SMC_PRIO33_OFFSET = 27'h 84;
parameter logic [BlockAw-1:0] RV_PLIC_SMC_PRIO34_OFFSET = 27'h 88;
parameter logic [BlockAw-1:0] RV_PLIC_SMC_PRIO35_OFFSET = 27'h 8c;
parameter logic [BlockAw-1:0] RV_PLIC_SMC_PRIO36_OFFSET = 27'h 90;
parameter logic [BlockAw-1:0] RV_PLIC_SMC_PRIO37_OFFSET = 27'h 94;
parameter logic [BlockAw-1:0] RV_PLIC_SMC_PRIO38_OFFSET = 27'h 98;
parameter logic [BlockAw-1:0] RV_PLIC_SMC_PRIO39_OFFSET = 27'h 9c;
parameter logic [BlockAw-1:0] RV_PLIC_SMC_PRIO40_OFFSET = 27'h a0;
parameter logic [BlockAw-1:0] RV_PLIC_SMC_PRIO41_OFFSET = 27'h a4;
parameter logic [BlockAw-1:0] RV_PLIC_SMC_PRIO42_OFFSET = 27'h a8;
parameter logic [BlockAw-1:0] RV_PLIC_SMC_IP_0_OFFSET = 27'h 1000;
parameter logic [BlockAw-1:0] RV_PLIC_SMC_IP_1_OFFSET = 27'h 1004;
parameter logic [BlockAw-1:0] RV_PLIC_SMC_IE0_0_OFFSET = 27'h 2000;
parameter logic [BlockAw-1:0] RV_PLIC_SMC_IE0_1_OFFSET = 27'h 2004;
parameter logic [BlockAw-1:0] RV_PLIC_SMC_THRESHOLD0_OFFSET = 27'h 200000;
parameter logic [BlockAw-1:0] RV_PLIC_SMC_CC0_OFFSET = 27'h 200004;
parameter logic [BlockAw-1:0] RV_PLIC_SMC_MSIP0_OFFSET = 27'h 4000000;
parameter logic [BlockAw-1:0] RV_PLIC_SMC_ALERT_TEST_OFFSET = 27'h 4004000;
// Reset values for hwext registers and their fields
parameter logic [5:0] RV_PLIC_SMC_CC0_RESVAL = 6'h 0;
parameter logic [0:0] RV_PLIC_SMC_ALERT_TEST_RESVAL = 1'h 0;
// Register index
typedef enum int {
RV_PLIC_SMC_PRIO0,
RV_PLIC_SMC_PRIO1,
RV_PLIC_SMC_PRIO2,
RV_PLIC_SMC_PRIO3,
RV_PLIC_SMC_PRIO4,
RV_PLIC_SMC_PRIO5,
RV_PLIC_SMC_PRIO6,
RV_PLIC_SMC_PRIO7,
RV_PLIC_SMC_PRIO8,
RV_PLIC_SMC_PRIO9,
RV_PLIC_SMC_PRIO10,
RV_PLIC_SMC_PRIO11,
RV_PLIC_SMC_PRIO12,
RV_PLIC_SMC_PRIO13,
RV_PLIC_SMC_PRIO14,
RV_PLIC_SMC_PRIO15,
RV_PLIC_SMC_PRIO16,
RV_PLIC_SMC_PRIO17,
RV_PLIC_SMC_PRIO18,
RV_PLIC_SMC_PRIO19,
RV_PLIC_SMC_PRIO20,
RV_PLIC_SMC_PRIO21,
RV_PLIC_SMC_PRIO22,
RV_PLIC_SMC_PRIO23,
RV_PLIC_SMC_PRIO24,
RV_PLIC_SMC_PRIO25,
RV_PLIC_SMC_PRIO26,
RV_PLIC_SMC_PRIO27,
RV_PLIC_SMC_PRIO28,
RV_PLIC_SMC_PRIO29,
RV_PLIC_SMC_PRIO30,
RV_PLIC_SMC_PRIO31,
RV_PLIC_SMC_PRIO32,
RV_PLIC_SMC_PRIO33,
RV_PLIC_SMC_PRIO34,
RV_PLIC_SMC_PRIO35,
RV_PLIC_SMC_PRIO36,
RV_PLIC_SMC_PRIO37,
RV_PLIC_SMC_PRIO38,
RV_PLIC_SMC_PRIO39,
RV_PLIC_SMC_PRIO40,
RV_PLIC_SMC_PRIO41,
RV_PLIC_SMC_PRIO42,
RV_PLIC_SMC_IP_0,
RV_PLIC_SMC_IP_1,
RV_PLIC_SMC_IE0_0,
RV_PLIC_SMC_IE0_1,
RV_PLIC_SMC_THRESHOLD0,
RV_PLIC_SMC_CC0,
RV_PLIC_SMC_MSIP0,
RV_PLIC_SMC_ALERT_TEST
} rv_plic_smc_id_e;
// Register width information to check illegal writes
parameter logic [3:0] RV_PLIC_SMC_PERMIT [51] = '{
4'b 0001, // index[ 0] RV_PLIC_SMC_PRIO0
4'b 0001, // index[ 1] RV_PLIC_SMC_PRIO1
4'b 0001, // index[ 2] RV_PLIC_SMC_PRIO2
4'b 0001, // index[ 3] RV_PLIC_SMC_PRIO3
4'b 0001, // index[ 4] RV_PLIC_SMC_PRIO4
4'b 0001, // index[ 5] RV_PLIC_SMC_PRIO5
4'b 0001, // index[ 6] RV_PLIC_SMC_PRIO6
4'b 0001, // index[ 7] RV_PLIC_SMC_PRIO7
4'b 0001, // index[ 8] RV_PLIC_SMC_PRIO8
4'b 0001, // index[ 9] RV_PLIC_SMC_PRIO9
4'b 0001, // index[10] RV_PLIC_SMC_PRIO10
4'b 0001, // index[11] RV_PLIC_SMC_PRIO11
4'b 0001, // index[12] RV_PLIC_SMC_PRIO12
4'b 0001, // index[13] RV_PLIC_SMC_PRIO13
4'b 0001, // index[14] RV_PLIC_SMC_PRIO14
4'b 0001, // index[15] RV_PLIC_SMC_PRIO15
4'b 0001, // index[16] RV_PLIC_SMC_PRIO16
4'b 0001, // index[17] RV_PLIC_SMC_PRIO17
4'b 0001, // index[18] RV_PLIC_SMC_PRIO18
4'b 0001, // index[19] RV_PLIC_SMC_PRIO19
4'b 0001, // index[20] RV_PLIC_SMC_PRIO20
4'b 0001, // index[21] RV_PLIC_SMC_PRIO21
4'b 0001, // index[22] RV_PLIC_SMC_PRIO22
4'b 0001, // index[23] RV_PLIC_SMC_PRIO23
4'b 0001, // index[24] RV_PLIC_SMC_PRIO24
4'b 0001, // index[25] RV_PLIC_SMC_PRIO25
4'b 0001, // index[26] RV_PLIC_SMC_PRIO26
4'b 0001, // index[27] RV_PLIC_SMC_PRIO27
4'b 0001, // index[28] RV_PLIC_SMC_PRIO28
4'b 0001, // index[29] RV_PLIC_SMC_PRIO29
4'b 0001, // index[30] RV_PLIC_SMC_PRIO30
4'b 0001, // index[31] RV_PLIC_SMC_PRIO31
4'b 0001, // index[32] RV_PLIC_SMC_PRIO32
4'b 0001, // index[33] RV_PLIC_SMC_PRIO33
4'b 0001, // index[34] RV_PLIC_SMC_PRIO34
4'b 0001, // index[35] RV_PLIC_SMC_PRIO35
4'b 0001, // index[36] RV_PLIC_SMC_PRIO36
4'b 0001, // index[37] RV_PLIC_SMC_PRIO37
4'b 0001, // index[38] RV_PLIC_SMC_PRIO38
4'b 0001, // index[39] RV_PLIC_SMC_PRIO39
4'b 0001, // index[40] RV_PLIC_SMC_PRIO40
4'b 0001, // index[41] RV_PLIC_SMC_PRIO41
4'b 0001, // index[42] RV_PLIC_SMC_PRIO42
4'b 1111, // index[43] RV_PLIC_SMC_IP_0
4'b 0011, // index[44] RV_PLIC_SMC_IP_1
4'b 1111, // index[45] RV_PLIC_SMC_IE0_0
4'b 0011, // index[46] RV_PLIC_SMC_IE0_1
4'b 0001, // index[47] RV_PLIC_SMC_THRESHOLD0
4'b 0001, // index[48] RV_PLIC_SMC_CC0
4'b 0001, // index[49] RV_PLIC_SMC_MSIP0
4'b 0001 // index[50] RV_PLIC_SMC_ALERT_TEST
};
endpackage