| // Copyright lowRISC contributors. |
| // Licensed under the Apache License, Version 2.0, see LICENSE for details. |
| // SPDX-License-Identifier: Apache-2.0 |
| // |
| # RV_PLIC_SMC register template |
| # |
| # Parameter (given by Python tool) |
| # - src: Number of Interrupt Sources |
| # - target: Number of Targets that handle interrupt requests |
| # - prio: Max value of interrupt priorities |
| # - module_instance_name: Module instance name. |
| { |
| name: "rv_plic_smc", |
| design_spec: "../doc", |
| dv_doc: "../doc/dv", |
| hw_checklist: "../doc/checklist", |
| sw_checklist: "/sw/device/lib/dif/dif_rv_plic_smc", |
| revisions: [ |
| { |
| version: "1.0", |
| life_stage: "L1", |
| design_stage: "D3", |
| verification_stage: "V2", |
| dif_stage: "S2", |
| commit_id: "", |
| notes: "Use FPV to perform block level verification.", |
| } |
| ], |
| clocking: [{clock: "clk_i", reset: "rst_ni"}], |
| bus_interfaces: [ |
| { protocol: "tlul", direction: "device" } |
| ], |
| |
| param_list: [ |
| { name: "NumSrc", |
| desc: "Number of interrupt sources", |
| type: "int", |
| default: "43", |
| local: "true" |
| }, |
| { name: "NumTarget", |
| desc: "Number of Targets (Harts)", |
| type: "int", |
| default: "1", |
| local: "true", |
| }, |
| { name: "PrioWidth", |
| desc: "Width of priority signals", |
| type: "int", |
| default: "2", |
| local: "true", |
| }, |
| ], |
| |
| // In order to not disturb the PLIC address map, we place the alert test |
| // register manually at a safe offset after the main CSRs. |
| no_auto_alert_regs: "True", |
| alert_list: [ |
| { name: "fatal_fault", |
| desc: ''' |
| This fatal alert is triggered when a fatal TL-UL bus integrity fault is detected. |
| ''' |
| } |
| ], |
| |
| inter_signal_list: [ |
| { struct: "logic", |
| type: "uni", |
| name: "irq", |
| act: "req", |
| package: "", |
| width: "1" |
| }, |
| |
| { struct: "logic", |
| type: "uni", |
| name: "irq_id", |
| act: "req", |
| package: "", |
| }, |
| |
| { struct: "logic", |
| type: "uni", |
| name: "msip", |
| act: "req", |
| package: "", |
| width: "1" |
| }, |
| ] |
| |
| countermeasures: [ |
| { name: "BUS.INTEGRITY", |
| desc: "End-to-end bus integrity scheme." |
| } |
| ] |
| |
| regwidth: "32", |
| registers: [ |
| { name: "PRIO0", |
| desc: "Interrupt Source 0 Priority", |
| swaccess: "rw", |
| hwaccess: "hro", |
| fields: [ |
| { bits: "1:0" } |
| ], |
| } |
| { name: "PRIO1", |
| desc: "Interrupt Source 1 Priority", |
| swaccess: "rw", |
| hwaccess: "hro", |
| fields: [ |
| { bits: "1:0" } |
| ], |
| } |
| { name: "PRIO2", |
| desc: "Interrupt Source 2 Priority", |
| swaccess: "rw", |
| hwaccess: "hro", |
| fields: [ |
| { bits: "1:0" } |
| ], |
| } |
| { name: "PRIO3", |
| desc: "Interrupt Source 3 Priority", |
| swaccess: "rw", |
| hwaccess: "hro", |
| fields: [ |
| { bits: "1:0" } |
| ], |
| } |
| { name: "PRIO4", |
| desc: "Interrupt Source 4 Priority", |
| swaccess: "rw", |
| hwaccess: "hro", |
| fields: [ |
| { bits: "1:0" } |
| ], |
| } |
| { name: "PRIO5", |
| desc: "Interrupt Source 5 Priority", |
| swaccess: "rw", |
| hwaccess: "hro", |
| fields: [ |
| { bits: "1:0" } |
| ], |
| } |
| { name: "PRIO6", |
| desc: "Interrupt Source 6 Priority", |
| swaccess: "rw", |
| hwaccess: "hro", |
| fields: [ |
| { bits: "1:0" } |
| ], |
| } |
| { name: "PRIO7", |
| desc: "Interrupt Source 7 Priority", |
| swaccess: "rw", |
| hwaccess: "hro", |
| fields: [ |
| { bits: "1:0" } |
| ], |
| } |
| { name: "PRIO8", |
| desc: "Interrupt Source 8 Priority", |
| swaccess: "rw", |
| hwaccess: "hro", |
| fields: [ |
| { bits: "1:0" } |
| ], |
| } |
| { name: "PRIO9", |
| desc: "Interrupt Source 9 Priority", |
| swaccess: "rw", |
| hwaccess: "hro", |
| fields: [ |
| { bits: "1:0" } |
| ], |
| } |
| { name: "PRIO10", |
| desc: "Interrupt Source 10 Priority", |
| swaccess: "rw", |
| hwaccess: "hro", |
| fields: [ |
| { bits: "1:0" } |
| ], |
| } |
| { name: "PRIO11", |
| desc: "Interrupt Source 11 Priority", |
| swaccess: "rw", |
| hwaccess: "hro", |
| fields: [ |
| { bits: "1:0" } |
| ], |
| } |
| { name: "PRIO12", |
| desc: "Interrupt Source 12 Priority", |
| swaccess: "rw", |
| hwaccess: "hro", |
| fields: [ |
| { bits: "1:0" } |
| ], |
| } |
| { name: "PRIO13", |
| desc: "Interrupt Source 13 Priority", |
| swaccess: "rw", |
| hwaccess: "hro", |
| fields: [ |
| { bits: "1:0" } |
| ], |
| } |
| { name: "PRIO14", |
| desc: "Interrupt Source 14 Priority", |
| swaccess: "rw", |
| hwaccess: "hro", |
| fields: [ |
| { bits: "1:0" } |
| ], |
| } |
| { name: "PRIO15", |
| desc: "Interrupt Source 15 Priority", |
| swaccess: "rw", |
| hwaccess: "hro", |
| fields: [ |
| { bits: "1:0" } |
| ], |
| } |
| { name: "PRIO16", |
| desc: "Interrupt Source 16 Priority", |
| swaccess: "rw", |
| hwaccess: "hro", |
| fields: [ |
| { bits: "1:0" } |
| ], |
| } |
| { name: "PRIO17", |
| desc: "Interrupt Source 17 Priority", |
| swaccess: "rw", |
| hwaccess: "hro", |
| fields: [ |
| { bits: "1:0" } |
| ], |
| } |
| { name: "PRIO18", |
| desc: "Interrupt Source 18 Priority", |
| swaccess: "rw", |
| hwaccess: "hro", |
| fields: [ |
| { bits: "1:0" } |
| ], |
| } |
| { name: "PRIO19", |
| desc: "Interrupt Source 19 Priority", |
| swaccess: "rw", |
| hwaccess: "hro", |
| fields: [ |
| { bits: "1:0" } |
| ], |
| } |
| { name: "PRIO20", |
| desc: "Interrupt Source 20 Priority", |
| swaccess: "rw", |
| hwaccess: "hro", |
| fields: [ |
| { bits: "1:0" } |
| ], |
| } |
| { name: "PRIO21", |
| desc: "Interrupt Source 21 Priority", |
| swaccess: "rw", |
| hwaccess: "hro", |
| fields: [ |
| { bits: "1:0" } |
| ], |
| } |
| { name: "PRIO22", |
| desc: "Interrupt Source 22 Priority", |
| swaccess: "rw", |
| hwaccess: "hro", |
| fields: [ |
| { bits: "1:0" } |
| ], |
| } |
| { name: "PRIO23", |
| desc: "Interrupt Source 23 Priority", |
| swaccess: "rw", |
| hwaccess: "hro", |
| fields: [ |
| { bits: "1:0" } |
| ], |
| } |
| { name: "PRIO24", |
| desc: "Interrupt Source 24 Priority", |
| swaccess: "rw", |
| hwaccess: "hro", |
| fields: [ |
| { bits: "1:0" } |
| ], |
| } |
| { name: "PRIO25", |
| desc: "Interrupt Source 25 Priority", |
| swaccess: "rw", |
| hwaccess: "hro", |
| fields: [ |
| { bits: "1:0" } |
| ], |
| } |
| { name: "PRIO26", |
| desc: "Interrupt Source 26 Priority", |
| swaccess: "rw", |
| hwaccess: "hro", |
| fields: [ |
| { bits: "1:0" } |
| ], |
| } |
| { name: "PRIO27", |
| desc: "Interrupt Source 27 Priority", |
| swaccess: "rw", |
| hwaccess: "hro", |
| fields: [ |
| { bits: "1:0" } |
| ], |
| } |
| { name: "PRIO28", |
| desc: "Interrupt Source 28 Priority", |
| swaccess: "rw", |
| hwaccess: "hro", |
| fields: [ |
| { bits: "1:0" } |
| ], |
| } |
| { name: "PRIO29", |
| desc: "Interrupt Source 29 Priority", |
| swaccess: "rw", |
| hwaccess: "hro", |
| fields: [ |
| { bits: "1:0" } |
| ], |
| } |
| { name: "PRIO30", |
| desc: "Interrupt Source 30 Priority", |
| swaccess: "rw", |
| hwaccess: "hro", |
| fields: [ |
| { bits: "1:0" } |
| ], |
| } |
| { name: "PRIO31", |
| desc: "Interrupt Source 31 Priority", |
| swaccess: "rw", |
| hwaccess: "hro", |
| fields: [ |
| { bits: "1:0" } |
| ], |
| } |
| { name: "PRIO32", |
| desc: "Interrupt Source 32 Priority", |
| swaccess: "rw", |
| hwaccess: "hro", |
| fields: [ |
| { bits: "1:0" } |
| ], |
| } |
| { name: "PRIO33", |
| desc: "Interrupt Source 33 Priority", |
| swaccess: "rw", |
| hwaccess: "hro", |
| fields: [ |
| { bits: "1:0" } |
| ], |
| } |
| { name: "PRIO34", |
| desc: "Interrupt Source 34 Priority", |
| swaccess: "rw", |
| hwaccess: "hro", |
| fields: [ |
| { bits: "1:0" } |
| ], |
| } |
| { name: "PRIO35", |
| desc: "Interrupt Source 35 Priority", |
| swaccess: "rw", |
| hwaccess: "hro", |
| fields: [ |
| { bits: "1:0" } |
| ], |
| } |
| { name: "PRIO36", |
| desc: "Interrupt Source 36 Priority", |
| swaccess: "rw", |
| hwaccess: "hro", |
| fields: [ |
| { bits: "1:0" } |
| ], |
| } |
| { name: "PRIO37", |
| desc: "Interrupt Source 37 Priority", |
| swaccess: "rw", |
| hwaccess: "hro", |
| fields: [ |
| { bits: "1:0" } |
| ], |
| } |
| { name: "PRIO38", |
| desc: "Interrupt Source 38 Priority", |
| swaccess: "rw", |
| hwaccess: "hro", |
| fields: [ |
| { bits: "1:0" } |
| ], |
| } |
| { name: "PRIO39", |
| desc: "Interrupt Source 39 Priority", |
| swaccess: "rw", |
| hwaccess: "hro", |
| fields: [ |
| { bits: "1:0" } |
| ], |
| } |
| { name: "PRIO40", |
| desc: "Interrupt Source 40 Priority", |
| swaccess: "rw", |
| hwaccess: "hro", |
| fields: [ |
| { bits: "1:0" } |
| ], |
| } |
| { name: "PRIO41", |
| desc: "Interrupt Source 41 Priority", |
| swaccess: "rw", |
| hwaccess: "hro", |
| fields: [ |
| { bits: "1:0" } |
| ], |
| } |
| { name: "PRIO42", |
| desc: "Interrupt Source 42 Priority", |
| swaccess: "rw", |
| hwaccess: "hro", |
| fields: [ |
| { bits: "1:0" } |
| ], |
| } |
| { skipto: "0x00001000" } |
| { multireg: { |
| name: "IP", |
| desc: "Interrupt Pending", |
| count: "NumSrc", |
| cname: "RV_PLIC_SMC", |
| swaccess: "ro", |
| hwaccess: "hwo", |
| fields: [ |
| { bits: "0", name: "P", desc: "Interrupt Pending of Source" } |
| ], |
| tags: [// IP is driven by intr_src, cannot auto-predict |
| "excl:CsrNonInitTests:CsrExclCheck"], |
| } |
| }, |
| { skipto: "0x2000" } |
| { multireg: { |
| name: "IE0", |
| desc: "Interrupt Enable for Target 0", |
| count: "NumSrc", |
| cname: "RV_PLIC_SMC", |
| swaccess: "rw", |
| hwaccess: "hro", |
| fields: [ |
| { bits: "0", name: "E", desc: "Interrupt Enable of Source" } |
| ], |
| } |
| } |
| { skipto: "0x200000" } |
| { name: "THRESHOLD0", |
| desc: "Threshold of priority for Target 0", |
| swaccess: "rw", |
| hwaccess: "hro", |
| fields: [ |
| { bits: "1:0" } |
| ], |
| } |
| { name: "CC0", |
| desc: '''Claim interrupt by read, complete interrupt by write for Target 0. |
| Value read/written is interrupt ID. Reading a value of 0 means no pending interrupts.''', |
| swaccess: "rw", |
| hwaccess: "hrw", |
| hwext: "true", |
| hwqe: "true", |
| hwre: "true", |
| fields: [ |
| { bits: "5:0" } |
| ], |
| tags: [// CC register value is related to IP |
| "excl:CsrNonInitTests:CsrExclCheck"], |
| } |
| { skipto: "0x4000000" } |
| { name: "MSIP0", |
| desc: '''msip for Hart 0. |
| Write 1 to here asserts software interrupt for Hart msip_o[0], write 0 to clear.''', |
| swaccess: "rw", |
| hwaccess: "hro", |
| fields: [ |
| { bits: "0", |
| desc: "Software Interrupt Pending register", |
| } |
| ], |
| } |
| { skipto: "0x4004000" } |
| { name: "ALERT_TEST", |
| desc: '''Alert Test Register.''', |
| swaccess: "wo", |
| hwaccess: "hro", |
| hwqe: "True", |
| hwext: "True", |
| fields: [ |
| { bits: "0", |
| name: "fatal_fault", |
| desc: "'Write 1 to trigger one alert event of this kind.'", |
| } |
| ], |
| } |
| ], |
| } |
