hw/top_matcha/ip/ml_top/rtl/ml_top_reg_pkg.sv

// Copyright lowRISC contributors.
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0
//
// Register Package auto-generated by `reggen` containing data structure

package ml_top_reg_pkg;

  // Address widths within the block
  parameter int CoreAw = 6;
  parameter int DmemAw = 1;

  ///////////////////////////////////////////////
  // Typedefs for registers for core interface //
  ///////////////////////////////////////////////

  typedef struct packed {
    struct packed {
      logic        q;
    } host_req;
    struct packed {
      logic        q;
    } finish;
    struct packed {
      logic        q;
    } fault;
  } ml_top_reg2hw_intr_state_reg_t;

  typedef struct packed {
    struct packed {
      logic        q;
    } host_req;
    struct packed {
      logic        q;
    } finish;
    struct packed {
      logic        q;
    } fault;
  } ml_top_reg2hw_intr_enable_reg_t;

  typedef struct packed {
    struct packed {
      logic        q;
      logic        qe;
    } host_req;
    struct packed {
      logic        q;
      logic        qe;
    } finish;
    struct packed {
      logic        q;
      logic        qe;
    } fault;
  } ml_top_reg2hw_intr_test_reg_t;

  typedef struct packed {
    struct packed {
      logic        q;
    } freeze;
    struct packed {
      logic        q;
    } ml_reset;
    struct packed {
      logic [21:0] q;
    } pc_start;
    struct packed {
      logic        q;
    } volt_sel;
    struct packed {
      logic [6:0]  q;
    } reserv;
  } ml_top_reg2hw_ctrl_reg_t;

  typedef struct packed {
    struct packed {
      logic [15:0] q;
    } d_mem_enable;
    struct packed {
      logic [15:0] q;
    } reserv;
  } ml_top_reg2hw_memory_bank_ctrl_reg_t;

  typedef struct packed {
    struct packed {
      logic        q;
    } d_mem_out_of_range;
    struct packed {
      logic [7:0]  q;
    } d_mem_disable_access;
  } ml_top_reg2hw_error_status_reg_t;

  typedef struct packed {
    logic [21:0] q;
  } ml_top_reg2hw_init_start_reg_t;

  typedef struct packed {
    struct packed {
      logic [21:0] q;
    } address;
    struct packed {
      logic        q;
    } valid;
  } ml_top_reg2hw_init_end_reg_t;

  typedef struct packed {
    struct packed {
      logic        d;
      logic        de;
    } host_req;
    struct packed {
      logic        d;
      logic        de;
    } finish;
    struct packed {
      logic        d;
      logic        de;
    } fault;
  } ml_top_hw2reg_intr_state_reg_t;

  typedef struct packed {
    struct packed {
      logic        d;
      logic        de;
    } d_mem_out_of_range;
    struct packed {
      logic [7:0]  d;
      logic        de;
    } d_mem_disable_access;
  } ml_top_hw2reg_error_status_reg_t;

  typedef struct packed {
    struct packed {
      logic [21:0] d;
      logic        de;
    } address;
    struct packed {
      logic        d;
      logic        de;
    } valid;
  } ml_top_hw2reg_init_end_reg_t;

  typedef struct packed {
    struct packed {
      logic        d;
      logic        de;
    } init_pending;
    struct packed {
      logic        d;
      logic        de;
    } init_done;
  } ml_top_hw2reg_init_status_reg_t;

  // Register -> HW type for core interface
  typedef struct packed {
    ml_top_reg2hw_intr_state_reg_t intr_state; // [129:127]
    ml_top_reg2hw_intr_enable_reg_t intr_enable; // [126:124]
    ml_top_reg2hw_intr_test_reg_t intr_test; // [123:118]
    ml_top_reg2hw_ctrl_reg_t ctrl; // [117:86]
    ml_top_reg2hw_memory_bank_ctrl_reg_t memory_bank_ctrl; // [85:54]
    ml_top_reg2hw_error_status_reg_t error_status; // [53:45]
    ml_top_reg2hw_init_start_reg_t init_start; // [44:23]
    ml_top_reg2hw_init_end_reg_t init_end; // [22:0]
  } ml_top_core_reg2hw_t;

  // HW -> register type for core interface
  typedef struct packed {
    ml_top_hw2reg_intr_state_reg_t intr_state; // [45:40]
    ml_top_hw2reg_error_status_reg_t error_status; // [39:29]
    ml_top_hw2reg_init_end_reg_t init_end; // [28:4]
    ml_top_hw2reg_init_status_reg_t init_status; // [3:0]
  } ml_top_core_hw2reg_t;

  // Register offsets for core interface
  parameter logic [CoreAw-1:0] ML_TOP_INTR_STATE_OFFSET = 6'h 0;
  parameter logic [CoreAw-1:0] ML_TOP_INTR_ENABLE_OFFSET = 6'h 4;
  parameter logic [CoreAw-1:0] ML_TOP_INTR_TEST_OFFSET = 6'h 8;
  parameter logic [CoreAw-1:0] ML_TOP_CTRL_OFFSET = 6'h c;
  parameter logic [CoreAw-1:0] ML_TOP_MEMORY_BANK_CTRL_OFFSET = 6'h 10;
  parameter logic [CoreAw-1:0] ML_TOP_ERROR_STATUS_OFFSET = 6'h 14;
  parameter logic [CoreAw-1:0] ML_TOP_INIT_START_OFFSET = 6'h 18;
  parameter logic [CoreAw-1:0] ML_TOP_INIT_END_OFFSET = 6'h 1c;
  parameter logic [CoreAw-1:0] ML_TOP_INIT_STATUS_OFFSET = 6'h 20;

  // Reset values for hwext registers and their fields for core interface
  parameter logic [2:0] ML_TOP_INTR_TEST_RESVAL = 3'h 0;
  parameter logic [0:0] ML_TOP_INTR_TEST_HOST_REQ_RESVAL = 1'h 0;
  parameter logic [0:0] ML_TOP_INTR_TEST_FINISH_RESVAL = 1'h 0;
  parameter logic [0:0] ML_TOP_INTR_TEST_FAULT_RESVAL = 1'h 0;

  // Register index for core interface
  typedef enum int {
    ML_TOP_INTR_STATE,
    ML_TOP_INTR_ENABLE,
    ML_TOP_INTR_TEST,
    ML_TOP_CTRL,
    ML_TOP_MEMORY_BANK_CTRL,
    ML_TOP_ERROR_STATUS,
    ML_TOP_INIT_START,
    ML_TOP_INIT_END,
    ML_TOP_INIT_STATUS
  } ml_top_core_id_e;

  // Register width information to check illegal writes for core interface
  parameter logic [3:0] ML_TOP_CORE_PERMIT [9] = '{
    4'b 0001, // index[0] ML_TOP_INTR_STATE
    4'b 0001, // index[1] ML_TOP_INTR_ENABLE
    4'b 0001, // index[2] ML_TOP_INTR_TEST
    4'b 1111, // index[3] ML_TOP_CTRL
    4'b 1111, // index[4] ML_TOP_MEMORY_BANK_CTRL
    4'b 0011, // index[5] ML_TOP_ERROR_STATUS
    4'b 0111, // index[6] ML_TOP_INIT_START
    4'b 0111, // index[7] ML_TOP_INIT_END
    4'b 0001  // index[8] ML_TOP_INIT_STATUS
  };

endpackage