hw/top_matcha/ip/ml_top/rtl/ml_top_core_reg_top.sv

// Copyright lowRISC contributors.
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0
//
// Register Top module auto-generated by `reggen`

`include "prim_assert.sv"

module ml_top_core_reg_top (
  input clk_i,
  input rst_ni,
  input  tlul_pkg::tl_h2d_t tl_i,
  output tlul_pkg::tl_d2h_t tl_o,
  // To HW
  output ml_top_reg_pkg::ml_top_core_reg2hw_t reg2hw, // Write
  input  ml_top_reg_pkg::ml_top_core_hw2reg_t hw2reg, // Read

  // Integrity check errors
  output logic intg_err_o,

  // Config
  input devmode_i // If 1, explicit error return for unmapped register access
);

  import ml_top_reg_pkg::* ;

  localparam int AW = 6;
  localparam int DW = 32;
  localparam int DBW = DW/8;                    // Byte Width

  // register signals
  logic           reg_we;
  logic           reg_re;
  logic [AW-1:0]  reg_addr;
  logic [DW-1:0]  reg_wdata;
  logic [DBW-1:0] reg_be;
  logic [DW-1:0]  reg_rdata;
  logic           reg_error;

  logic          addrmiss, wr_err;

  logic [DW-1:0] reg_rdata_next;
  logic reg_busy;

  tlul_pkg::tl_h2d_t tl_reg_h2d;
  tlul_pkg::tl_d2h_t tl_reg_d2h;


  // incoming payload check
  logic intg_err;
  tlul_cmd_intg_chk u_chk (
    .tl_i(tl_i),
    .err_o(intg_err)
  );

  // also check for spurious write enables
  logic reg_we_err;
  logic [8:0] reg_we_check;
  prim_reg_we_check #(
    .OneHotWidth(9)
  ) u_prim_reg_we_check (
    .clk_i(clk_i),
    .rst_ni(rst_ni),
    .oh_i  (reg_we_check),
    .en_i  (reg_we && !addrmiss),
    .err_o (reg_we_err)
  );

  logic err_q;
  always_ff @(posedge clk_i or negedge rst_ni) begin
    if (!rst_ni) begin
      err_q <= '0;
    end else if (intg_err || reg_we_err) begin
      err_q <= 1'b1;
    end
  end

  // integrity error output is permanent and should be used for alert generation
  // register errors are transactional
  assign intg_err_o = err_q | intg_err | reg_we_err;

  // outgoing integrity generation
  tlul_pkg::tl_d2h_t tl_o_pre;
  tlul_rsp_intg_gen #(
    .EnableRspIntgGen(1),
    .EnableDataIntgGen(1)
  ) u_rsp_intg_gen (
    .tl_i(tl_o_pre),
    .tl_o(tl_o)
  );

  assign tl_reg_h2d = tl_i;
  assign tl_o_pre   = tl_reg_d2h;

  tlul_adapter_reg #(
    .RegAw(AW),
    .RegDw(DW),
    .EnableDataIntgGen(0)
  ) u_reg_if (
    .clk_i  (clk_i),
    .rst_ni (rst_ni),

    .tl_i (tl_reg_h2d),
    .tl_o (tl_reg_d2h),

    .en_ifetch_i(prim_mubi_pkg::MuBi4False),
    .intg_error_o(),

    .we_o    (reg_we),
    .re_o    (reg_re),
    .addr_o  (reg_addr),
    .wdata_o (reg_wdata),
    .be_o    (reg_be),
    .busy_i  (reg_busy),
    .rdata_i (reg_rdata),
    .error_i (reg_error)
  );

  // cdc oversampling signals

  assign reg_rdata = reg_rdata_next ;
  assign reg_error = (devmode_i & addrmiss) | wr_err | intg_err;

  // Define SW related signals
  // Format: <reg>_<field>_{wd|we|qs}
  //        or <reg>_{wd|we|qs} if field == 1 or 0
  logic intr_state_we;
  logic intr_state_host_req_qs;
  logic intr_state_host_req_wd;
  logic intr_state_finish_qs;
  logic intr_state_finish_wd;
  logic intr_state_fault_qs;
  logic intr_state_fault_wd;
  logic intr_enable_we;
  logic intr_enable_host_req_qs;
  logic intr_enable_host_req_wd;
  logic intr_enable_finish_qs;
  logic intr_enable_finish_wd;
  logic intr_enable_fault_qs;
  logic intr_enable_fault_wd;
  logic intr_test_we;
  logic intr_test_host_req_wd;
  logic intr_test_finish_wd;
  logic intr_test_fault_wd;
  logic ctrl_we;
  logic ctrl_freeze_qs;
  logic ctrl_freeze_wd;
  logic ctrl_ml_reset_qs;
  logic ctrl_ml_reset_wd;
  logic [21:0] ctrl_pc_start_qs;
  logic [21:0] ctrl_pc_start_wd;
  logic ctrl_volt_sel_qs;
  logic ctrl_volt_sel_wd;
  logic [6:0] ctrl_reserv_qs;
  logic [6:0] ctrl_reserv_wd;
  logic [15:0] memory_bank_ctrl_d_mem_enable_qs;
  logic [15:0] memory_bank_ctrl_reserv_qs;
  logic error_status_re;
  logic error_status_d_mem_out_of_range_qs;
  logic error_status_d_mem_out_of_range_wd;
  logic [7:0] error_status_d_mem_disable_access_qs;
  logic [7:0] error_status_d_mem_disable_access_wd;
  logic init_start_we;
  logic [21:0] init_start_qs;
  logic [21:0] init_start_wd;
  logic init_end_we;
  logic [21:0] init_end_address_qs;
  logic [21:0] init_end_address_wd;
  logic init_end_valid_qs;
  logic init_end_valid_wd;
  logic init_status_re;
  logic init_status_init_pending_qs;
  logic init_status_init_pending_wd;
  logic init_status_init_done_qs;
  logic init_status_init_done_wd;

  // Register instances
  // R[intr_state]: V(False)
  //   F[host_req]: 0:0
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessW1C),
    .RESVAL  (1'h0)
  ) u_intr_state_host_req (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (intr_state_we),
    .wd     (intr_state_host_req_wd),

    // from internal hardware
    .de     (hw2reg.intr_state.host_req.de),
    .d      (hw2reg.intr_state.host_req.d),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intr_state.host_req.q),
    .ds     (),

    // to register interface (read)
    .qs     (intr_state_host_req_qs)
  );

  //   F[finish]: 1:1
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessW1C),
    .RESVAL  (1'h0)
  ) u_intr_state_finish (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (intr_state_we),
    .wd     (intr_state_finish_wd),

    // from internal hardware
    .de     (hw2reg.intr_state.finish.de),
    .d      (hw2reg.intr_state.finish.d),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intr_state.finish.q),
    .ds     (),

    // to register interface (read)
    .qs     (intr_state_finish_qs)
  );

  //   F[fault]: 2:2
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessW1C),
    .RESVAL  (1'h0)
  ) u_intr_state_fault (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (intr_state_we),
    .wd     (intr_state_fault_wd),

    // from internal hardware
    .de     (hw2reg.intr_state.fault.de),
    .d      (hw2reg.intr_state.fault.d),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intr_state.fault.q),
    .ds     (),

    // to register interface (read)
    .qs     (intr_state_fault_qs)
  );


  // R[intr_enable]: V(False)
  //   F[host_req]: 0:0
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0)
  ) u_intr_enable_host_req (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (intr_enable_we),
    .wd     (intr_enable_host_req_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intr_enable.host_req.q),
    .ds     (),

    // to register interface (read)
    .qs     (intr_enable_host_req_qs)
  );

  //   F[finish]: 1:1
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0)
  ) u_intr_enable_finish (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (intr_enable_we),
    .wd     (intr_enable_finish_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intr_enable.finish.q),
    .ds     (),

    // to register interface (read)
    .qs     (intr_enable_finish_qs)
  );

  //   F[fault]: 2:2
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0)
  ) u_intr_enable_fault (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (intr_enable_we),
    .wd     (intr_enable_fault_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intr_enable.fault.q),
    .ds     (),

    // to register interface (read)
    .qs     (intr_enable_fault_qs)
  );


  // R[intr_test]: V(True)
  logic intr_test_qe;
  logic [2:0] intr_test_flds_we;
  assign intr_test_qe = &intr_test_flds_we;
  //   F[host_req]: 0:0
  prim_subreg_ext #(
    .DW    (1)
  ) u_intr_test_host_req (
    .re     (1'b0),
    .we     (intr_test_we),
    .wd     (intr_test_host_req_wd),
    .d      ('0),
    .qre    (),
    .qe     (intr_test_flds_we[0]),
    .q      (reg2hw.intr_test.host_req.q),
    .ds     (),
    .qs     ()
  );
  assign reg2hw.intr_test.host_req.qe = intr_test_qe;

  //   F[finish]: 1:1
  prim_subreg_ext #(
    .DW    (1)
  ) u_intr_test_finish (
    .re     (1'b0),
    .we     (intr_test_we),
    .wd     (intr_test_finish_wd),
    .d      ('0),
    .qre    (),
    .qe     (intr_test_flds_we[1]),
    .q      (reg2hw.intr_test.finish.q),
    .ds     (),
    .qs     ()
  );
  assign reg2hw.intr_test.finish.qe = intr_test_qe;

  //   F[fault]: 2:2
  prim_subreg_ext #(
    .DW    (1)
  ) u_intr_test_fault (
    .re     (1'b0),
    .we     (intr_test_we),
    .wd     (intr_test_fault_wd),
    .d      ('0),
    .qre    (),
    .qe     (intr_test_flds_we[2]),
    .q      (reg2hw.intr_test.fault.q),
    .ds     (),
    .qs     ()
  );
  assign reg2hw.intr_test.fault.qe = intr_test_qe;


  // R[ctrl]: V(False)
  //   F[freeze]: 0:0
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0)
  ) u_ctrl_freeze (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (ctrl_we),
    .wd     (ctrl_freeze_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.ctrl.freeze.q),
    .ds     (),

    // to register interface (read)
    .qs     (ctrl_freeze_qs)
  );

  //   F[ml_reset]: 1:1
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h1)
  ) u_ctrl_ml_reset (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (ctrl_we),
    .wd     (ctrl_ml_reset_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.ctrl.ml_reset.q),
    .ds     (),

    // to register interface (read)
    .qs     (ctrl_ml_reset_qs)
  );

  //   F[pc_start]: 23:2
  prim_subreg #(
    .DW      (22),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (22'h0)
  ) u_ctrl_pc_start (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (ctrl_we),
    .wd     (ctrl_pc_start_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.ctrl.pc_start.q),
    .ds     (),

    // to register interface (read)
    .qs     (ctrl_pc_start_qs)
  );

  //   F[volt_sel]: 24:24
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0)
  ) u_ctrl_volt_sel (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (ctrl_we),
    .wd     (ctrl_volt_sel_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.ctrl.volt_sel.q),
    .ds     (),

    // to register interface (read)
    .qs     (ctrl_volt_sel_qs)
  );

  //   F[reserv]: 31:25
  prim_subreg #(
    .DW      (7),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (7'h0)
  ) u_ctrl_reserv (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (ctrl_we),
    .wd     (ctrl_reserv_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.ctrl.reserv.q),
    .ds     (),

    // to register interface (read)
    .qs     (ctrl_reserv_qs)
  );


  // R[memory_bank_ctrl]: V(False)
  //   F[d_mem_enable]: 15:0
  prim_subreg #(
    .DW      (16),
    .SwAccess(prim_subreg_pkg::SwAccessRO),
    .RESVAL  (16'hf)
  ) u_memory_bank_ctrl_d_mem_enable (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (1'b0),
    .wd     ('0),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.memory_bank_ctrl.d_mem_enable.q),
    .ds     (),

    // to register interface (read)
    .qs     (memory_bank_ctrl_d_mem_enable_qs)
  );

  //   F[reserv]: 31:16
  prim_subreg #(
    .DW      (16),
    .SwAccess(prim_subreg_pkg::SwAccessRO),
    .RESVAL  (16'h0)
  ) u_memory_bank_ctrl_reserv (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (1'b0),
    .wd     ('0),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.memory_bank_ctrl.reserv.q),
    .ds     (),

    // to register interface (read)
    .qs     (memory_bank_ctrl_reserv_qs)
  );


  // R[error_status]: V(False)
  //   F[d_mem_out_of_range]: 0:0
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRC),
    .RESVAL  (1'h0)
  ) u_error_status_d_mem_out_of_range (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (error_status_re),
    .wd     (error_status_d_mem_out_of_range_wd),

    // from internal hardware
    .de     (hw2reg.error_status.d_mem_out_of_range.de),
    .d      (hw2reg.error_status.d_mem_out_of_range.d),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.error_status.d_mem_out_of_range.q),
    .ds     (),

    // to register interface (read)
    .qs     (error_status_d_mem_out_of_range_qs)
  );

  //   F[d_mem_disable_access]: 8:1
  prim_subreg #(
    .DW      (8),
    .SwAccess(prim_subreg_pkg::SwAccessRC),
    .RESVAL  (8'h0)
  ) u_error_status_d_mem_disable_access (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (error_status_re),
    .wd     (error_status_d_mem_disable_access_wd),

    // from internal hardware
    .de     (hw2reg.error_status.d_mem_disable_access.de),
    .d      (hw2reg.error_status.d_mem_disable_access.d),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.error_status.d_mem_disable_access.q),
    .ds     (),

    // to register interface (read)
    .qs     (error_status_d_mem_disable_access_qs)
  );


  // R[init_start]: V(False)
  prim_subreg #(
    .DW      (22),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (22'h0)
  ) u_init_start (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (init_start_we),
    .wd     (init_start_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.init_start.q),
    .ds     (),

    // to register interface (read)
    .qs     (init_start_qs)
  );


  // R[init_end]: V(False)
  //   F[address]: 21:0
  prim_subreg #(
    .DW      (22),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (22'h0)
  ) u_init_end_address (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (init_end_we),
    .wd     (init_end_address_wd),

    // from internal hardware
    .de     (hw2reg.init_end.address.de),
    .d      (hw2reg.init_end.address.d),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.init_end.address.q),
    .ds     (),

    // to register interface (read)
    .qs     (init_end_address_qs)
  );

  //   F[valid]: 22:22
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0)
  ) u_init_end_valid (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (init_end_we),
    .wd     (init_end_valid_wd),

    // from internal hardware
    .de     (hw2reg.init_end.valid.de),
    .d      (hw2reg.init_end.valid.d),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.init_end.valid.q),
    .ds     (),

    // to register interface (read)
    .qs     (init_end_valid_qs)
  );


  // R[init_status]: V(False)
  //   F[init_pending]: 0:0
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRC),
    .RESVAL  (1'h0)
  ) u_init_status_init_pending (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (init_status_re),
    .wd     (init_status_init_pending_wd),

    // from internal hardware
    .de     (hw2reg.init_status.init_pending.de),
    .d      (hw2reg.init_status.init_pending.d),

    // to internal hardware
    .qe     (),
    .q      (),
    .ds     (),

    // to register interface (read)
    .qs     (init_status_init_pending_qs)
  );

  //   F[init_done]: 1:1
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRC),
    .RESVAL  (1'h0)
  ) u_init_status_init_done (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (init_status_re),
    .wd     (init_status_init_done_wd),

    // from internal hardware
    .de     (hw2reg.init_status.init_done.de),
    .d      (hw2reg.init_status.init_done.d),

    // to internal hardware
    .qe     (),
    .q      (),
    .ds     (),

    // to register interface (read)
    .qs     (init_status_init_done_qs)
  );



  logic [8:0] addr_hit;
  always_comb begin
    addr_hit = '0;
    addr_hit[0] = (reg_addr == ML_TOP_INTR_STATE_OFFSET);
    addr_hit[1] = (reg_addr == ML_TOP_INTR_ENABLE_OFFSET);
    addr_hit[2] = (reg_addr == ML_TOP_INTR_TEST_OFFSET);
    addr_hit[3] = (reg_addr == ML_TOP_CTRL_OFFSET);
    addr_hit[4] = (reg_addr == ML_TOP_MEMORY_BANK_CTRL_OFFSET);
    addr_hit[5] = (reg_addr == ML_TOP_ERROR_STATUS_OFFSET);
    addr_hit[6] = (reg_addr == ML_TOP_INIT_START_OFFSET);
    addr_hit[7] = (reg_addr == ML_TOP_INIT_END_OFFSET);
    addr_hit[8] = (reg_addr == ML_TOP_INIT_STATUS_OFFSET);
  end

  assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ;

  // Check sub-word write is permitted
  always_comb begin
    wr_err = (reg_we &
              ((addr_hit[0] & (|(ML_TOP_CORE_PERMIT[0] & ~reg_be))) |
               (addr_hit[1] & (|(ML_TOP_CORE_PERMIT[1] & ~reg_be))) |
               (addr_hit[2] & (|(ML_TOP_CORE_PERMIT[2] & ~reg_be))) |
               (addr_hit[3] & (|(ML_TOP_CORE_PERMIT[3] & ~reg_be))) |
               (addr_hit[4] & (|(ML_TOP_CORE_PERMIT[4] & ~reg_be))) |
               (addr_hit[5] & (|(ML_TOP_CORE_PERMIT[5] & ~reg_be))) |
               (addr_hit[6] & (|(ML_TOP_CORE_PERMIT[6] & ~reg_be))) |
               (addr_hit[7] & (|(ML_TOP_CORE_PERMIT[7] & ~reg_be))) |
               (addr_hit[8] & (|(ML_TOP_CORE_PERMIT[8] & ~reg_be)))));
  end

  // Generate write-enables
  assign intr_state_we = addr_hit[0] & reg_we & !reg_error;

  assign intr_state_host_req_wd = reg_wdata[0];

  assign intr_state_finish_wd = reg_wdata[1];

  assign intr_state_fault_wd = reg_wdata[2];
  assign intr_enable_we = addr_hit[1] & reg_we & !reg_error;

  assign intr_enable_host_req_wd = reg_wdata[0];

  assign intr_enable_finish_wd = reg_wdata[1];

  assign intr_enable_fault_wd = reg_wdata[2];
  assign intr_test_we = addr_hit[2] & reg_we & !reg_error;

  assign intr_test_host_req_wd = reg_wdata[0];

  assign intr_test_finish_wd = reg_wdata[1];

  assign intr_test_fault_wd = reg_wdata[2];
  assign ctrl_we = addr_hit[3] & reg_we & !reg_error;

  assign ctrl_freeze_wd = reg_wdata[0];

  assign ctrl_ml_reset_wd = reg_wdata[1];

  assign ctrl_pc_start_wd = reg_wdata[23:2];

  assign ctrl_volt_sel_wd = reg_wdata[24];

  assign ctrl_reserv_wd = reg_wdata[31:25];
  assign error_status_re = addr_hit[5] & reg_re & !reg_error;

  assign error_status_d_mem_out_of_range_wd = '1;

  assign error_status_d_mem_disable_access_wd = '1;
  assign init_start_we = addr_hit[6] & reg_we & !reg_error;

  assign init_start_wd = reg_wdata[21:0];
  assign init_end_we = addr_hit[7] & reg_we & !reg_error;

  assign init_end_address_wd = reg_wdata[21:0];

  assign init_end_valid_wd = reg_wdata[22];
  assign init_status_re = addr_hit[8] & reg_re & !reg_error;

  assign init_status_init_pending_wd = '1;

  assign init_status_init_done_wd = '1;

  // Assign write-enables to checker logic vector.
  always_comb begin
    reg_we_check = '0;
    reg_we_check[0] = intr_state_we;
    reg_we_check[1] = intr_enable_we;
    reg_we_check[2] = intr_test_we;
    reg_we_check[3] = ctrl_we;
    reg_we_check[4] = 1'b0;
    reg_we_check[5] = 1'b0;
    reg_we_check[6] = init_start_we;
    reg_we_check[7] = init_end_we;
    reg_we_check[8] = 1'b0;
  end

  // Read data return
  always_comb begin
    reg_rdata_next = '0;
    unique case (1'b1)
      addr_hit[0]: begin
        reg_rdata_next[0] = intr_state_host_req_qs;
        reg_rdata_next[1] = intr_state_finish_qs;
        reg_rdata_next[2] = intr_state_fault_qs;
      end

      addr_hit[1]: begin
        reg_rdata_next[0] = intr_enable_host_req_qs;
        reg_rdata_next[1] = intr_enable_finish_qs;
        reg_rdata_next[2] = intr_enable_fault_qs;
      end

      addr_hit[2]: begin
        reg_rdata_next[0] = '0;
        reg_rdata_next[1] = '0;
        reg_rdata_next[2] = '0;
      end

      addr_hit[3]: begin
        reg_rdata_next[0] = ctrl_freeze_qs;
        reg_rdata_next[1] = ctrl_ml_reset_qs;
        reg_rdata_next[23:2] = ctrl_pc_start_qs;
        reg_rdata_next[24] = ctrl_volt_sel_qs;
        reg_rdata_next[31:25] = ctrl_reserv_qs;
      end

      addr_hit[4]: begin
        reg_rdata_next[15:0] = memory_bank_ctrl_d_mem_enable_qs;
        reg_rdata_next[31:16] = memory_bank_ctrl_reserv_qs;
      end

      addr_hit[5]: begin
        reg_rdata_next[0] = error_status_d_mem_out_of_range_qs;
        reg_rdata_next[8:1] = error_status_d_mem_disable_access_qs;
      end

      addr_hit[6]: begin
        reg_rdata_next[21:0] = init_start_qs;
      end

      addr_hit[7]: begin
        reg_rdata_next[21:0] = init_end_address_qs;
        reg_rdata_next[22] = init_end_valid_qs;
      end

      addr_hit[8]: begin
        reg_rdata_next[0] = init_status_init_pending_qs;
        reg_rdata_next[1] = init_status_init_done_qs;
      end

      default: begin
        reg_rdata_next = '1;
      end
    endcase
  end

  // shadow busy
  logic shadow_busy;
  assign shadow_busy = 1'b0;

  // register busy
  assign reg_busy = shadow_busy;

  // Unused signal tieoff

  // wdata / byte enable are not always fully used
  // add a blanket unused statement to handle lint waivers
  logic unused_wdata;
  logic unused_be;
  assign unused_wdata = ^reg_wdata;
  assign unused_be = ^reg_be;

  // Assertions for Register Interface
  `ASSERT_PULSE(wePulse, reg_we, clk_i, !rst_ni)
  `ASSERT_PULSE(rePulse, reg_re, clk_i, !rst_ni)

  `ASSERT(reAfterRv, $rose(reg_re || reg_we) |=> tl_o_pre.d_valid, clk_i, !rst_ni)

  `ASSERT(en2addrHit, (reg_we || reg_re) |-> $onehot0(addr_hit), clk_i, !rst_ni)

  // this is formulated as an assumption such that the FPV testbenches do disprove this
  // property by mistake
  //`ASSUME(reqParity, tl_reg_h2d.a_valid |-> tl_reg_h2d.a_user.chk_en == tlul_pkg::CheckDis)

endmodule