hw/top_matcha/ip/ml_top/rtl/ml_top.sv

// Copyright 2022 Google LLC.
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0
//
// This file is the top level for the AI/ML Core. It instantiates the
// following units:
//   TLUL:      2 independent TLUL target ports to access core_crtl and D-Mem
//   AXI4:      AXI2_SRAM_Adapter for ISP interface
//   XBAR_SRAM: SRAM Corssbar (To-be-added)
//   Kelvin :   RISC-V Vector Core Implementation (To-be-added)
//   D-Mem:     Data memory
//   CORE_CTRL: Control/Status registers for controlling this design. This is not the same
//              as CSR implemented inside RV32IV as part of the RISC-V
//              definitions
//
module ml_top #(
) (
  input logic       rst_ni,
  input logic       clk_i,

  // TLUL Interfaces

  // DMEM
  input  tlul_pkg::tl_h2d_t  dmem_tl_i,
  output tlul_pkg::tl_d2h_t  dmem_tl_o,

  // CSR
  input  tlul_pkg::tl_h2d_t  core_tl_i,
  output tlul_pkg::tl_d2h_t  core_tl_o,

  // ISP Memory Interfaces (Only reserve write channel)
    input                      isp_cvalid_i,
    output logic               isp_cready_o,
    input                      isp_cwrite_i,
    input        [21:0]        isp_caddr_i,
    input        [255:0]       isp_wdata_i,
    input        [31:0]        isp_wmask_i,

  // Interrupts
  output logic  intr_host_req_o,
  output logic  intr_finish_o,
  output logic  intr_fault_o

);

  import ml_pkg::*;

  // Signal declaration

  logic              core0_cvalid;
  logic              core0_cready;
  logic              core0_cwrite;
  logic   [31:0]     core0_caddr;
  logic   [7:0]      core0_cid;
  logic   [255:0]    core0_wdata;
  logic   [31:0]     core0_wmask;
  logic              core0_rvalid;
  logic   [7:0]      core0_rid;
  logic   [255:0]    core0_rdata;

  logic              core0_host_req, core0_finish, core0_fault;

  // CSR Registers
  ml_top_reg_pkg::ml_top_core_reg2hw_t                      reg2hw;
  ml_top_reg_pkg::ml_top_core_hw2reg_t                      hw2reg;
  ml_top_reg_pkg::ml_top_reg2hw_ctrl_reg_t                  ctrl;

  // Interrupt event, to be wired to correct source
  logic event_host_req;
  logic event_finish;
  logic event_fault;
  logic event_data_fault;


  assign ctrl             = reg2hw.ctrl;

  always_comb begin
    hw2reg.error_status.d_mem_out_of_range.d = 1'b0;
    hw2reg.error_status.d_mem_out_of_range.de = 1'b0;
    hw2reg.error_status.d_mem_disable_access.d = reg2hw.error_status.d_mem_disable_access;
    hw2reg.error_status.d_mem_disable_access.de = 1'b0;
  end

  // ML_top Control
  ml_top_core_reg_top u_reg (
    .clk_i,
    .rst_ni,

    .tl_i       ( core_tl_i ),
    .tl_o       ( core_tl_o ),

    .reg2hw,
    .hw2reg,
    .devmode_i  ( 1'b0 )
  );

  // Kelvin core
  Kelvin u_kelvin (
    .clk_i,
    .rst_ni,

    // CSR control
    .clk_freeze   (ctrl.freeze),    // Default 0, writing 1 will freeze the kelvin's clock. (Clock gate inside)
    .ml_reset     (ctrl.ml_reset),  // default 1, writing 1 will reset the ml core.
                                    //            Writing 0 will take it out of reset.

    // Kelvin core execution start address {PC[21:0]}, 4MB address space. See register definition for bitfield lsb.
    .pc_start     (ctrl.pc_start),
    .volt_sel     (ctrl.volt_sel), // Default 0 for 0.8V memory macros, write 1 for 0.65V.

    // SRAM Interface
    .cvalid       (core0_cvalid),
    .cready       (core0_cready),
    .cwrite       (core0_cwrite),
    .caddr        (core0_caddr),
    .cid          (core0_cid[6:0]),
    .wdata        (core0_wdata),
    .wmask        (core0_wmask),
    .rvalid       (core0_rvalid),
    .rid          (core0_rid[6:0]),
    .rdata        (core0_rdata),

    .slog_valid   (),
    .slog_addr    (),
    .slog_data    (),

    // Interrupt
    .fault        (core0_fault),
    .host_req     (core0_host_req), // raised if the kelvin core need to interrupt the host
    .finish       (core0_finish)    // raised if the kelvin finish the task
  );


  // Memory Block (inlcude xbar_sram and SRAM banks)
  ml_dmem  u_ml_dmem (
    .rst_ni        ( rst_ni ),
    .clk_i         ( clk_i ),

    .volt_sel_i    ( ctrl.volt_sel ),

    // TLUL Interface
    .tl_mem_i   ( dmem_tl_i ),
    .tl_mem_o   ( dmem_tl_o ),

    // In Port 1 -- ISP
    .isp_cvalid_i   (isp_cvalid_i),
    .isp_cready_o   (isp_cready_o),
    .isp_cwrite_i   (isp_cwrite_i),
    .isp_caddr_i    (isp_caddr_i),
    .isp_cid_i      (8'b0),
    .isp_wdata_i    (isp_wdata_i),
    .isp_wmask_i    (isp_wmask_i),
    .isp_rvalid_o   (),
    .isp_rid_o      (),
    .isp_rdata_o    (),
    // In Port 2 -- Kelvin
    .core0_cvalid_i   (core0_cvalid),
    .core0_cready_o   (core0_cready),
    .core0_cwrite_i   (core0_cwrite),
    .core0_caddr_i    (core0_caddr[21:0]),
    .core0_cid_i      (core0_cid),
    .core0_wdata_i    (core0_wdata),
    .core0_wmask_i    (core0_wmask),
    .core0_rvalid_o   (core0_rvalid),
    .core0_rid_o      (core0_rid),
    .core0_rdata_o    (core0_rdata),
    // In Port 3 -- Unused
    .core1_cvalid_i   (1'b0),
    .core1_cready_o   (),
    .core1_cwrite_i   (1'b0),
    .core1_caddr_i    (22'b0),
    .core1_cid_i      (8'b0),
    .core1_wdata_i    (256'b0),
    .core1_wmask_i    (32'b0),
    .core1_rvalid_o   (),
    .core1_rid_o      (),
    .core1_rdata_o    ()
  );


  ///////////////
  // Interrupt //
  ///////////////


  assign event_host_req = core0_host_req;
  assign event_finish = core0_finish;
  assign event_fault = core0_fault;

  // Host Request interrupt
  prim_intr_hw #(.Width(1)) intr_host_req (
    .clk_i,
    .rst_ni,
    .event_intr_i           (event_host_req),
    .reg2hw_intr_enable_q_i (reg2hw.intr_enable.host_req.q),
    .reg2hw_intr_test_q_i   (reg2hw.intr_test.host_req.q),
    .reg2hw_intr_test_qe_i  (reg2hw.intr_test.host_req.qe),
    .reg2hw_intr_state_q_i  (reg2hw.intr_state.host_req.q),
    .hw2reg_intr_state_de_o (hw2reg.intr_state.host_req.de),
    .hw2reg_intr_state_d_o  (hw2reg.intr_state.host_req.d),
    .intr_o                 (intr_host_req_o)
  );


  // Finish interrupt
  prim_intr_hw #(.Width(1)) intr_finish (
    .clk_i,
    .rst_ni,
    .event_intr_i           (event_finish),
    .reg2hw_intr_enable_q_i (reg2hw.intr_enable.finish.q),
    .reg2hw_intr_test_q_i   (reg2hw.intr_test.finish.q),
    .reg2hw_intr_test_qe_i  (reg2hw.intr_test.finish.qe),
    .reg2hw_intr_state_q_i  (reg2hw.intr_state.finish.q),
    .hw2reg_intr_state_de_o (hw2reg.intr_state.finish.de),
    .hw2reg_intr_state_d_o  (hw2reg.intr_state.finish.d),
    .intr_o                 (intr_finish_o)
  );

  // Fault interrupt
  prim_intr_hw #(.Width(1)) intr_fault (
    .clk_i,
    .rst_ni,
    .event_intr_i           (event_fault),
    .reg2hw_intr_enable_q_i (reg2hw.intr_enable.fault.q),
    .reg2hw_intr_test_q_i   (reg2hw.intr_test.fault.q),
    .reg2hw_intr_test_qe_i  (reg2hw.intr_test.fault.qe),
    .reg2hw_intr_state_q_i  (reg2hw.intr_state.fault.q),
    .hw2reg_intr_state_de_o (hw2reg.intr_state.fault.de),
    .hw2reg_intr_state_d_o  (hw2reg.intr_state.fault.d),
    .intr_o                 (intr_fault_o)
  );

endmodule