| // Copyright 2022 Google LLC. |
| // Licensed under the Apache License, Version 2.0, see LICENSE for details. |
| // SPDX-License-Identifier: Apache-2.0 |
| //---------------------------------------------- |
| |
| // This module implements the D-Mem inside the Vector Core Top Level |
| // |
| // This memory can be accessed either by TLUL or ML cores through xbar_sram |
| |
| module ml_dmem |
| import ml_pkg::*; |
| import ml_top_reg_pkg::*; |
| import prim_ram_1p_pkg::ram_1p_cfg_t; |
| ( |
| input logic rst_ni, |
| input logic clk_i, |
| |
| // CSR for memory voltage control |
| input logic volt_sel_i, |
| |
| // TLUL Interfaces |
| input tlul_pkg::tl_h2d_t tl_mem_i, |
| output tlul_pkg::tl_d2h_t tl_mem_o, |
| |
| // ISP Memory Interfaces |
| input isp_cvalid_i, |
| output logic isp_cready_o, |
| input isp_cwrite_i, |
| input [21:0] isp_caddr_i, |
| input [7:0] isp_cid_i, |
| input [255:0] isp_wdata_i, |
| input [31:0] isp_wmask_i, |
| output logic [255:0] isp_rdata_o, |
| output logic isp_rvalid_o, |
| output logic [7:0] isp_rid_o, |
| |
| |
| // ML Core0 (Kelvin) Memory Interfaces |
| input core0_cvalid_i, |
| output logic core0_cready_o, |
| input core0_cwrite_i, |
| input [21:0] core0_caddr_i, |
| input [7:0] core0_cid_i, |
| input [255:0] core0_wdata_i, |
| input [31:0] core0_wmask_i, |
| output logic [255:0] core0_rdata_o, |
| output logic core0_rvalid_o, |
| output logic [7:0] core0_rid_o, |
| |
| // ML Core1 (Malamute) Memory Interfaces |
| input core1_cvalid_i, |
| output logic core1_cready_o, |
| input core1_cwrite_i, |
| input [21:0] core1_caddr_i, |
| input [7:0] core1_cid_i, |
| input [255:0] core1_wdata_i, |
| input [31:0] core1_wmask_i, |
| output logic [255:0] core1_rdata_o, |
| output logic core1_rvalid_o, |
| output logic [7:0] core1_rid_o |
| |
| ); |
| |
| // outgoing integrity generation |
| tlul_pkg::tl_d2h_t tl_o_pre; |
| tlul_rsp_intg_gen #( |
| ) u_ml_dmem_rsp_gen ( |
| .tl_i(tl_o_pre), |
| .tl_o(tl_mem_o) |
| ); |
| |
| logic dmem_req, xbar_req; |
| logic dmem_we, xbar_we; |
| logic xbar_gnt; |
| logic [21:0] dmem_addr; |
| logic [16:0] xbar_addr; |
| logic [255:0] dmem_wdata, xbar_wdata; |
| logic [255:0] dmem_wmask, xbar_wmask; |
| logic [31:0] dmem_wmask_b, xbar_wmask_b; |
| logic [255:0] dmem_rdata, xbar_rdata; |
| logic dmem_rvalid, xbar_rvalid; |
| logic [1:0] dmem_rerror, xbar_rerror; |
| ram_1p_cfg_t ram_cfg; |
| |
| // cfg_en (LSB) is unused in memory module and does not qualify volt_sel |
| assign ram_cfg.ram_cfg = { 3'b0, volt_sel_i, 1'b0 }; |
| |
| // xbar_sram only support Byte-Mask for now. i.e 8 data bits per mask bit. |
| assign xbar_wmask_b = {xbar_wmask[248], xbar_wmask[240], xbar_wmask[232], xbar_wmask[224], |
| xbar_wmask[216], xbar_wmask[208], xbar_wmask[200], xbar_wmask[192], |
| xbar_wmask[184], xbar_wmask[176], xbar_wmask[168], xbar_wmask[160], |
| xbar_wmask[152], xbar_wmask[144], xbar_wmask[136], xbar_wmask[128], |
| xbar_wmask[120], xbar_wmask[112], xbar_wmask[104], xbar_wmask[96], |
| xbar_wmask[88], xbar_wmask[80], xbar_wmask[72], xbar_wmask[64], |
| xbar_wmask[56], xbar_wmask[48], xbar_wmask[40], xbar_wmask[32], |
| xbar_wmask[24], xbar_wmask[16], xbar_wmask[8], xbar_wmask[0]}; |
| |
| assign dmem_wmask = {dmem_wmask_b[31] ? 8'hff : 8'h00, |
| dmem_wmask_b[30] ? 8'hff : 8'h00, |
| dmem_wmask_b[29] ? 8'hff : 8'h00, |
| dmem_wmask_b[28] ? 8'hff : 8'h00, |
| dmem_wmask_b[27] ? 8'hff : 8'h00, |
| dmem_wmask_b[26] ? 8'hff : 8'h00, |
| dmem_wmask_b[25] ? 8'hff : 8'h00, |
| dmem_wmask_b[24] ? 8'hff : 8'h00, |
| dmem_wmask_b[23] ? 8'hff : 8'h00, |
| dmem_wmask_b[22] ? 8'hff : 8'h00, |
| dmem_wmask_b[21] ? 8'hff : 8'h00, |
| dmem_wmask_b[20] ? 8'hff : 8'h00, |
| dmem_wmask_b[19] ? 8'hff : 8'h00, |
| dmem_wmask_b[18] ? 8'hff : 8'h00, |
| dmem_wmask_b[17] ? 8'hff : 8'h00, |
| dmem_wmask_b[16] ? 8'hff : 8'h00, |
| dmem_wmask_b[15] ? 8'hff : 8'h00, |
| dmem_wmask_b[14] ? 8'hff : 8'h00, |
| dmem_wmask_b[13] ? 8'hff : 8'h00, |
| dmem_wmask_b[12] ? 8'hff : 8'h00, |
| dmem_wmask_b[11] ? 8'hff : 8'h00, |
| dmem_wmask_b[10] ? 8'hff : 8'h00, |
| dmem_wmask_b[9] ? 8'hff : 8'h00, |
| dmem_wmask_b[8] ? 8'hff : 8'h00, |
| dmem_wmask_b[7] ? 8'hff : 8'h00, |
| dmem_wmask_b[6] ? 8'hff : 8'h00, |
| dmem_wmask_b[5] ? 8'hff : 8'h00, |
| dmem_wmask_b[4] ? 8'hff : 8'h00, |
| dmem_wmask_b[3] ? 8'hff : 8'h00, |
| dmem_wmask_b[2] ? 8'hff : 8'h00, |
| dmem_wmask_b[1] ? 8'hff : 8'h00, |
| dmem_wmask_b[0] ? 8'hff : 8'h00}; |
| |
| tlul_adapter_sram #( |
| .SramAw (17), // TO-DO(pbf): 4MB size, use DMemAw late |
| .SramDw (256), |
| .Outstanding (1), |
| .ByteAccess (1), |
| .ErrOnRead (0), |
| .EnableDataIntgPt(0) |
| ) u_tlul_adapter_sram_dmem ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| .tl_i (tl_mem_i), |
| .tl_o (tl_o_pre), |
| .en_ifetch_i (prim_mubi_pkg::MuBi4False), |
| .req_o (xbar_req), |
| .req_type_o (), |
| .gnt_i (xbar_gnt), // Grant when requests occur |
| .we_o (xbar_we), |
| .addr_o (xbar_addr), |
| .wdata_o (xbar_wdata), |
| .wmask_o (xbar_wmask), |
| .intg_error_o(), |
| .rdata_i (xbar_rdata), |
| .rvalid_i (xbar_rvalid), |
| .rerror_i (2'b0) |
| ); |
| |
| |
| // crossbar |
| xbar_sram u_xbar_sram( |
| .clock (clk_i), |
| .reset (~rst_ni), |
| // In Port 0 -- TLUL-SRAM Adatper |
| .io_in_0_cvalid (xbar_req), |
| .io_in_0_cready (xbar_gnt) , |
| .io_in_0_cwrite (xbar_we), |
| .io_in_0_caddr ({xbar_addr, 5'b0}), |
| .io_in_0_cid (8'b0), |
| .io_in_0_wdata (xbar_wdata), |
| .io_in_0_wmask (xbar_wmask_b), |
| .io_in_0_rvalid (xbar_rvalid), |
| .io_in_0_rid (), |
| .io_in_0_rdata (xbar_rdata), |
| // In Port 1 -- ISP |
| .io_in_1_cvalid (isp_cvalid_i), |
| .io_in_1_cready (isp_cready_o), |
| .io_in_1_cwrite (isp_cwrite_i), |
| .io_in_1_caddr (isp_caddr_i), |
| .io_in_1_cid (isp_cid_i), |
| .io_in_1_wdata (isp_wdata_i), |
| .io_in_1_wmask (isp_wmask_i), |
| .io_in_1_rvalid (isp_rvalid_o), |
| .io_in_1_rid (isp_rid_o), |
| .io_in_1_rdata (isp_rdata_o), |
| // In Port 2 -- Kelvin |
| .io_in_2_cvalid (core0_cvalid_i), |
| .io_in_2_cready (core0_cready_o), |
| .io_in_2_cwrite (core0_cwrite_i), |
| .io_in_2_caddr (core0_caddr_i), |
| .io_in_2_cid (core0_cid_i), |
| .io_in_2_wdata (core0_wdata_i), |
| .io_in_2_wmask (core0_wmask_i), |
| .io_in_2_rvalid (core0_rvalid_o), |
| .io_in_2_rid (core0_rid_o), |
| .io_in_2_rdata (core0_rdata_o), |
| // In Port 3 -- Malamute |
| .io_in_3_cvalid (core1_cvalid_i), |
| .io_in_3_cready (core1_cready_o), |
| .io_in_3_cwrite (core1_cwrite_i), |
| .io_in_3_caddr (core1_caddr_i), |
| .io_in_3_cid (core1_cid_i), |
| .io_in_3_wdata (core1_wdata_i), |
| .io_in_3_wmask (core1_wmask_i), |
| .io_in_3_rvalid (core1_rvalid_o), |
| .io_in_3_rid (core1_rid_o), |
| .io_in_3_rdata (core1_rdata_o), |
| // Output |
| .io_out_valid (dmem_req), |
| .io_out_write (dmem_we), |
| .io_out_addr (dmem_addr), |
| .io_out_wdata (dmem_wdata), |
| .io_out_wmask (dmem_wmask_b), |
| .io_out_rdata (dmem_rdata) |
| ); |
| |
| // TODO(pbf): Currently is just for FPGA utilization exercise, will change |
| // the Width/Depth after adding xbar_sram. |
| prim_ram_1p_adv #( |
| .Width(256), |
| .Depth(131072), |
| .DataBitsPerMask(8), |
| // TODO: enable parity once supported by the simulation infrastructure |
| .EnableParity(0) |
| ) u_ram1p_dmem ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| .req_i (dmem_req), |
| .write_i (dmem_we), |
| .addr_i (dmem_addr[21:5]), |
| .wdata_i (dmem_wdata), |
| .wmask_i (dmem_wmask), |
| .rdata_o (dmem_rdata), |
| .rvalid_o (dmem_rvalid), |
| .rerror_o (dmem_rerror), |
| .cfg_i (ram_cfg) |
| ); |
| |
| endmodule |
| |
