hw/top_matcha/ip/ml_top/rtl/ClockGate.v

module ClockGate(
  input         clk_i,
  input         enable,  // '1' passthrough, '0' disable.
  output        clk_o
);
// TO-DO(pbf): Bypass clock gate for now. It cause FPGA build failure and
// simulation issue
assign clk_o = clk_i;
/*
reg clk_en;
`ifdef FPGA
    assign clk_o = clk_i;
`else
    // Capture 'enable' during low phase of the clock.
    always @(clk_i or enable)
    begin
      if (~clk_i)
      clk_en = enable;
    end

  assign clk_o = clk_i & clk_en;
`endif
*/
endmodule  // ClockGate