hw/top_matcha/ip/ml_top/data/ml_top.hjson

// Copyright 2022 Google LLC.
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0

{ name: "ml_top",

  // To-do: add other clocks
  clocking: [
    {clock: "clk_i", reset: "rst_ni", primary: true},
  ],
  bus_interfaces: [

    { protocol: "tlul", direction: "device", name: "core" }, // rename csr to core due to new check.
    { protocol: "tlul", direction: "device", name: "dmem" }
  ],

  // As current opentitan build script, the registers set (state/enable/test) for each of interrupt
  // added in below interrupt_list will only be added in the first tlul device defined in
  // above bus_interface, i.e., "core".

  interrupt_list: [
    {
      name: "host_req"
      desc: "raised if the ml_top need to interrupt host(reserved)."
    }
    {
      name: "finish"
      desc: "raised if the ml_top finishes task."
    }
    {
      name: "fault"
      desc: "raised if kelvin report fault."
    }
  ],

  inter_signal_list: [
     { name:  "isp_cvalid",
        package: "",
        struct:  "logic",
        act:     "rcv",
        type:    "uni",
        width:   "1"
     },
     { name:  "isp_cready",
        package: "",
        struct:  "logic",
        act:     "req",
        type:    "uni",
        width:   "1"
     },
     { name:  "isp_cwrite",
        package: "",
        struct:  "logic",
        act:     "rcv",
        type:    "uni",
        width:   "1"
     },
     { name:  "isp_caddr",
        package: "",
        struct:  "logic",
        act:     "rcv",
        type:    "uni",
        width:   "22"
     },
     { name:  "isp_wdata",
        package: "",
        struct:  "logic",
        act:     "rcv",
        type:    "uni",
        width:   "256"
     },
     { name:  "isp_wmask",
        package: "",
        struct:  "logic",
        act:     "rcv",
        type:    "uni",
        width:   "32"
     },
  ],


  regwidth: "32",

  registers: {

    core: [
      { name: "CTRL",
        desc: "ML_Top Control register",
        swaccess: "rw",
        hwaccess: "hro",
        fields: [
          { bits: "0",
            name: "freeze",
            resval: 0x0
            desc: "Writing a 1 will freeze the vector core clock (reserved), clock gating is implemented at chip root level instead now."
          }
          { bits: "1",
            name: "ml_reset",
            resval: 0x1
            desc: "Writing a 1 will reset the vector core. Writing a 0 will take it out of reset"
          }
          { bits: "23:2",
            name: "pc_start",
            resval: 0x0
            desc: "Starting address (22 bits for 4MB) for the PC when RV32IV is taken out of reset"
          }
          { bits: "24",
            name: "volt_sel",
            resval: 0x0
            desc: "SRAM Macro voltage control. Default 0 for 0.8V, set to 1 for 0.65v"
          }
          { bits: "31:25",
            name: "reserv",
            resval: 0x0
            desc: "Reserved bits"
          }
        ]
      },

      { name:     "MEMORY_BANK_CTRL"
        desc:     "Control register for the memory banks (reserved)"
        swaccess: "ro"
        hwaccess: "hro"
        fields: [
          { bits: "15:0",
            name: "d_mem_enable",
            resval: 0xf
            desc: "A value of 1 enables the specified dmem bank"
          }
          { bits: "31:16",
            name: "reserv",
            resval: 0x0
            desc: "Reserved bits"
          }
        ]
      },

      { name: "ERROR_STATUS",
        desc: "ML_Top Error Status register",
        swaccess: "rc",
        hwaccess: "hrw",
        fields: [
          { bits: "0",
            name: "d_mem_out_of_range",
            resval: 0x0
            desc: "A value of 1 indicates an out of DMEM range access (reserved)"
          }
          { bits: "8:1",
            name: "d_mem_disable_access",
            resval: 0x0
            desc: "A value of 1 indicates an access to a disabled DMEM bank (reserved)"
          }
        ]
      }

      { name: "INIT_START",
        desc: "Memory Initialization Start Address (reserved), HW implmentation TBD",
        swaccess: "rw",
        hwaccess: "hro",
        fields: [
          { bits: "21:0",
            name: "address",
            desc: "Starting Address for initialization."
            resval: 0x0
          }
        ]
      }

      { name: "INIT_END",
        desc: "Memory Initialization End Address (reserved), HW implementation TBD",
        swaccess: "rw",
        hwaccess: "hrw",
        fields: [
          { bits: "21:0",
            name: "address",
            desc: "Ending Address for initialization."
          }
          { bits: "22",
            name: "valid"
            desc: Writing a 1 triggers the initialization to start. HW clears this bit on completion
          }
        ],
        tags: [// Exclude from Csr tests
               "excl:CsrAllTests:CsrExclAll"],
      }

      { name: "INIT_STATUS",
        desc: "Memory Initialization Status (reserved), HW implementation TBD",
        swaccess: "rc",
        hwaccess: "hwo",
        fields: [
          { bits: "0",
            name: "init_pending",
            desc: "A value of 1 indicates an ongoing initialization operation"
          }
          { bits: "1",
            name: "init_done"
            //swaccess: rc
            desc: Indicates init operation has completed
          }
        ],
        tags: [// Exclude from Csr tests
               "excl:CsrAllTests:CsrExclAll"],
      }
    ]

    dmem: []
  }
}