| // Copyright lowRISC contributors. |
| // Licensed under the Apache License, Version 2.0, see LICENSE for details. |
| // SPDX-License-Identifier: Apache-2.0 |
| { name: "main", |
| type: "xbar", |
| clock_primary: "clk_main_i", // Main clock, used in sockets |
| other_clock_list: [ "clk_fixed_i", "clk_spi_host0_i", "clk_spi_host1_i", "clk_usb_i", "clk_smc_i"] |
| reset_primary: "rst_main_ni", // Main reset, used in sockets |
| other_reset_list: [ "rst_fixed_ni", "rst_spi_host0_ni", "rst_spi_host1_ni", "rst_usb_ni", "rst_smc_ni"] |
| |
| // Rationale for pipeline and req/rsp_fifo_pass: |
| // For host interfaces that are used during production state (corei/cored), |
| // minimize the amount of host introduced latency. This is accomplished |
| // by setting pipeline to false. |
| // For host interfaces that are only used for debug, relax the timing by |
| // inserting a register slice and not allowing passthrough (more access |
| // latency. This is accomplished by setting `req/rsp_fifo_pass` to false, |
| // and implicitly using the default of pipeline true. |
| // |
| // For device interfaces, especially configuration registers, latency is |
| // not generally a concern, thus use `req/rsp_fifo_pass` false and pipeline |
| // true. |
| // For device accesses to memories (ram / rom / flash), performance is a concern, |
| // so use pipeline false where permissible by timing. If not, find a combination |
| // that works. |
| |
| nodes: [ |
| { name: "rv_core_ibex_sec.corei", |
| type: "host", |
| clock: "clk_main_i", |
| reset: "rst_main_ni", |
| pipeline: false |
| |
| }, |
| { name: "rv_core_ibex_sec.cored", |
| type: "host", |
| clock: "clk_main_i", |
| reset: "rst_main_ni", |
| pipeline: false |
| }, |
| { name: "rv_dm.sba", |
| type: "host", |
| clock: "clk_main_i", |
| reset: "rst_main_ni", |
| req_fifo_pass: false, |
| rsp_fifo_pass: false, |
| }, |
| { name: "dma0.reader", |
| type: "host", |
| clock: "clk_main_i", |
| reset: "rst_main_ni", |
| pipeline: false |
| }, |
| { name: "dma0.writer", |
| type: "host", |
| clock: "clk_main_i", |
| reset: "rst_main_ni", |
| pipeline: false |
| }, |
| { name: "dma0", |
| type: "device", |
| clock: "clk_main_i", |
| reset: "rst_main_ni", |
| req_fifo_pass: false, |
| rsp_fifo_pass: false, |
| }, |
| { name: "rom_ctrl.rom", |
| type: "device", |
| clock: "clk_main_i", |
| reset: "rst_main_ni", |
| req_fifo_pass: true, |
| rsp_fifo_pass: false, |
| }, |
| { name: "rom_ctrl.regs", |
| type: "device", |
| clock: "clk_main_i", |
| reset: "rst_main_ni", |
| req_fifo_pass: false, |
| rsp_fifo_pass: false, |
| }, |
| { name: "peri", |
| type: "device", |
| clock: "clk_fixed_i", |
| reset: "rst_fixed_ni", |
| req_fifo_pass: false, |
| rsp_fifo_pass: false, |
| }, |
| { name: "spi_host0", |
| type: "device", |
| clock: "clk_spi_host0_i", |
| reset: "rst_spi_host0_ni", |
| req_fifo_pass: false, |
| rsp_fifo_pass: false, |
| }, |
| { name: "spi_host1", |
| type: "device", |
| clock: "clk_spi_host1_i", |
| reset: "rst_spi_host1_ni", |
| req_fifo_pass: false, |
| rsp_fifo_pass: false, |
| }, |
| { name: "usbdev", |
| type: "device", |
| clock: "clk_usb_i", |
| reset: "rst_usb_ni", |
| req_fifo_pass: false, |
| rsp_fifo_pass: false, |
| }, |
| { name: "flash_ctrl.core", |
| type: "device", |
| clock: "clk_main_i", |
| reset: "rst_main_ni", |
| req_fifo_pass: false, |
| rsp_fifo_pass: false, |
| }, |
| { name: "flash_ctrl.prim", |
| type: "device", |
| clock: "clk_main_i", |
| reset: "rst_main_ni", |
| req_fifo_pass: false, |
| rsp_fifo_pass: false, |
| }, |
| { name: "flash_ctrl.mem", |
| type: "device", |
| clock: "clk_main_i", |
| reset: "rst_main_ni", |
| req_fifo_pass: false, |
| rsp_fifo_pass: false, |
| }, |
| { name: "hmac", |
| type: "device", |
| clock: "clk_main_i", |
| reset: "rst_main_ni", |
| req_fifo_pass: false, |
| rsp_fifo_pass: false, |
| }, |
| { name: "kmac" |
| type: "device" |
| clock: "clk_main_i" |
| reset: "rst_main_ni" |
| req_fifo_pass: false, |
| rsp_fifo_pass: false, |
| } |
| { name: "aes", |
| type: "device", |
| clock: "clk_main_i" |
| reset: "rst_main_ni" |
| req_fifo_pass: false, |
| rsp_fifo_pass: false, |
| }, |
| { name: "entropy_src", |
| type: "device", |
| clock: "clk_main_i" |
| reset: "rst_main_ni" |
| req_fifo_pass: false, |
| rsp_fifo_pass: false, |
| }, |
| { name: "csrng", |
| type: "device", |
| clock: "clk_main_i" |
| reset: "rst_main_ni" |
| req_fifo_pass: false, |
| rsp_fifo_pass: false, |
| }, |
| { name: "edn0", |
| type: "device", |
| clock: "clk_main_i" |
| reset: "rst_main_ni" |
| req_fifo_pass: false, |
| rsp_fifo_pass: false, |
| }, |
| { name: "edn1", |
| type: "device", |
| clock: "clk_main_i" |
| reset: "rst_main_ni" |
| req_fifo_pass: false, |
| rsp_fifo_pass: false, |
| }, |
| { name: "rv_plic", |
| type: "device", |
| clock: "clk_main_i", |
| reset: "rst_main_ni", |
| inst_type: "rv_plic", |
| req_fifo_pass: false, |
| rsp_fifo_pass: false, |
| }, |
| { name: "otbn", |
| type: "device", |
| clock: "clk_main_i" |
| reset: "rst_main_ni" |
| req_fifo_pass: false, |
| rsp_fifo_pass: false, |
| }, |
| { name: "keymgr", |
| type: "device", |
| clock: "clk_main_i" |
| reset: "rst_main_ni" |
| req_fifo_pass: false, |
| rsp_fifo_pass: false, |
| }, |
| { name: "rv_core_ibex_sec.cfg", |
| type: "device", |
| clock: "clk_main_i" |
| reset: "rst_main_ni" |
| req_fifo_pass: false, |
| rsp_fifo_pass: false, |
| }, |
| { name: "sram_ctrl_main.regs", |
| type: "device", |
| clock: "clk_main_i", |
| reset: "rst_main_ni", |
| req_fifo_pass: false, |
| rsp_fifo_pass: false, |
| }, |
| { name: "sram_ctrl_main.ram", |
| type: "device", |
| clock: "clk_main_i", |
| reset: "rst_main_ni", |
| pipeline: false |
| }, |
| { name: "tlul_mailbox_sec", |
| type: "device", |
| clock: "clk_main_i", |
| reset: "rst_main_ni", |
| pipeline_byp: false, |
| }, |
| { name: "smc", |
| type: "device", |
| clock: "clk_smc_i", |
| reset: "rst_smc_ni", |
| pipeline_byp: false, |
| xbar: "true" |
| }, |
| { name: "dbg", |
| type: "device", |
| clock: "clk_main_i", |
| reset: "rst_main_ni", |
| pipeline_byp: false, |
| xbar: "true" |
| }, |
| ], |
| connections: { |
| rv_core_ibex_sec.corei: ["rom_ctrl.rom", "dbg", "sram_ctrl_main.ram", "flash_ctrl.mem"], |
| rv_core_ibex_sec.cored: [ |
| "rom_ctrl.rom", "rom_ctrl.regs", "dbg", |
| "sram_ctrl_main.ram", "peri", "spi_host0", "spi_host1", "usbdev", |
| "flash_ctrl.core", "flash_ctrl.prim", "flash_ctrl.mem", |
| "aes", "entropy_src", "csrng", "edn0", "edn1", "hmac", |
| "rv_plic", "otbn", "keymgr", "kmac", "sram_ctrl_main.regs", |
| "rv_core_ibex_sec.cfg", "smc", "tlul_mailbox_sec", dma0 |
| ], |
| rv_dm.sba: [ |
| "dbg", "rom_ctrl.rom", "rom_ctrl.regs", "peri", "spi_host0", "spi_host1", "usbdev", |
| "flash_ctrl.core", "flash_ctrl.prim", "flash_ctrl.mem", "hmac", "kmac", |
| "aes", "entropy_src", "csrng", "edn0", "edn1", "rv_plic", "otbn", |
| "keymgr", "rv_core_ibex_sec.cfg", "sram_ctrl_main.regs", "sram_ctrl_main.ram", "smc", "tlul_mailbox_sec" |
| ], |
| dma0.reader: ["rom_ctrl.rom", "sram_ctrl_main.ram", "flash_ctrl.mem", "smc"], |
| dma0.writer: ["rom_ctrl.rom", "sram_ctrl_main.ram", "flash_ctrl.mem", "smc"], |
| }, |
| } |
