| ## Copyright lowRISC contributors. |
| ## Licensed under the Apache License, Version 2.0, see LICENSE for details. |
| ## SPDX-License-Identifier: Apache-2.0 |
| |
| ## Nexus FPGA Board. |
| |
| ## Clock Signal: 100Mhz REFCLK (Pin U13 and T13 at Bank 72) |
| ## TODO(pbf): Nexus board routed as diff-pair. Use LVDS or DIFF-SSTL18? |
| set_property -dict { PACKAGE_PIN U13 IOSTANDARD DIFF_SSTL18_I } [get_ports { IO_CLK }]; # CK_100M00_FPGA_1_P |
| set_property -dict { PACKAGE_PIN T13 IOSTANDARD DIFF_SSTL18_I } [get_ports { IO_CLK_N }]; # CK_100M00_FPGA_1_N |
| |
| ## Clock constraints |
| ## set via clocks.xdc |
| |
| ## Preserve prim_prince modules and setup multi-cycle paths |
| ## These are no longer required, but kept here as a reference |
| ## set_property KEEP_HIERARCHY TRUE [get_cells top_matcha/u_flash_eflash/gen_flash_banks[*].i_core/u_scramble/u_cipher] |
| ## set_multicycle_path -setup 2 -through [get_pins -of_objects [get_cells top_matcha/u_flash_eflash/gen_flash_banks[*].i_core/u_scramble/u_cipher]] |
| ## set_multicycle_path -hold 1 -through [get_pins -of_objects [get_cells top_matcha/u_flash_eflash/gen_flash_banks[*].i_core/u_scramble/u_cipher]] |
| |
| #set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets IO_SDCK_IBUF]; # SDCK clock to be ignored |
| |
| ## LEDs in Bank 68 LVCMOS12 |
| set_property -dict { PACKAGE_PIN R36 DRIVE 8 IOSTANDARD LVCMOS12 } [get_ports { IOA8 }]; #LED_B_0 |
| # 6/23/23. pbf comment out following LEDs pins, re-cycled IOB0-6 for Camera interface |
| #set_property -dict { PACKAGE_PIN T31 DRIVE 8 IOSTANDARD LVCMOS12 } [get_ports { IOB0 }]; #LED_B_1 |
| #set_property -dict { PACKAGE_PIN P31 DRIVE 8 IOSTANDARD LVCMOS12 } [get_ports { IOB1 }]; #LED_B_2 |
| #set_property -dict { PACKAGE_PIN N37 DRIVE 8 IOSTANDARD LVCMOS12 } [get_ports { IOB2 }]; #LED_B_3 |
| #set_property -dict { PACKAGE_PIN M38 DRIVE 8 IOSTANDARD LVCMOS12 } [get_ports { IOB3 }]; #LED_B_4 |
| #set_property -dict { PACKAGE_PIN L38 DRIVE 8 IOSTANDARD LVCMOS12 } [get_ports { IOB4 }]; #LED_B_5 |
| #set_property -dict { PACKAGE_PIN L36 DRIVE 8 IOSTANDARD LVCMOS12 } [get_ports { IOB5 }]; #LED_B_6 |
| #set_property -dict { PACKAGE_PIN K36 DRIVE 8 IOSTANDARD LVCMOS12 } [get_ports { IOB6 }]; #LED_B_7 |
| |
| ### Buttons in Bank 68 LVCMOS12 #TEMPORARILY REMOVED - should add in addition to FTDI reset |
| #set_property -dict { PACKAGE_PIN W31 IOSTANDARD LVCMOS12 } [get_ports { POR_N }]; #pushbutton PBA1 |
| |
| ## Switches (4 in Bank60 for Nexus: FPGA_SW[0-3] LVCMOS18, to DIP Switch SW03) |
| set_property -dict { PACKAGE_PIN AT30 IOSTANDARD LVCMOS18 } [get_ports { IOC8 }]; #FPGA_SW0 #tap0 |
| set_property -dict { PACKAGE_PIN AT31 IOSTANDARD LVCMOS18 } [get_ports { IOC5 }]; #FPGA_SW1 #tap1 |
| |
| # 6/23/23. pbf comment out following SW pins, re-cycled IOA2-7 for Camera interface |
| #set_property -dict { PACKAGE_PIN AR32 IOSTANDARD LVCMOS18 } [get_ports { IOA2 }]; #FPGA_SW2 |
| #set_property -dict { PACKAGE_PIN AR33 IOSTANDARD LVCMOS18 } [get_ports { IOA3 }]; #FPGA_SW3 |
| ## Switches (another 4 in Bank66 for Nexus: FPGA_SW[4-7] LVCMOS18, to both DIP switch SW47 and debug header J259) |
| #set_property -dict { PACKAGE_PIN BF9 IOSTANDARD LVCMOS18 } [get_ports { IOA4 }]; #FPGA_SW4 |
| #set_property -dict { PACKAGE_PIN BE9 IOSTANDARD LVCMOS18 } [get_ports { IOA5 }]; #FPGA_SW5 |
| #set_property -dict { PACKAGE_PIN BF10 IOSTANDARD LVCMOS18 } [get_ports { IOA6 }]; #FPGA_SW6 |
| #set_property -dict { PACKAGE_PIN BE10 IOSTANDARD LVCMOS18 } [get_ports { IOA7 }]; #FPGA_SW7 |
| |
| #SIGNALS REMOVED FROM SWITCHES TO MAKE WAY FOR OTHER SIGNALS |
| #IOA0 removed from FPGA_SW0 to make way for IOC8 (tap0) |
| #IOA1 removed from FPGA_SW0 to make way for IOC5 (tap1) |
| |
| ## SPI_Device Option 1: (SPI Device connect to SPI1 to MCU through 1v8<->3V3 level shifter, Bank60 LVCMOS18) |
| #set_property -dict { PACKAGE_PIN AT32 IOSTANDARD LVCMOS18 } [get_ports { SPI_DEV_CLK }]; #SCK (SPI1_SCK/FPGA_MCU_1P8_5) |
| #set_property -dict { PACKAGE_PIN AU33 IOSTANDARD LVCMOS18 } [get_ports { SPI_DEV_D0 }]; #SDI (SPI1_MOSI/FPGA_MCU_1P8_3) |
| #set_property -dict { PACKAGE_PIN AV34 IOSTANDARD LVCMOS18 } [get_ports { SPI_DEV_D1 }]; #SDO (SPI1_MISO/FPGA_MCU_1P8_4) |
| #set_property -dict { PACKAGE_PIN AU32 IOSTANDARD LVCMOS18 } [get_ports { SPI_DEV_CS_L }];#CSB (SPI1_NSS/FPGA_MCU_1P8_6) |
| |
| ## SPI_Device Option 2: (SPI Device connect to FTDI ADBUS through 1v8<->3V3 level shifter, Bank65 LVCMOS18) |
| set_property -dict { PACKAGE_PIN AV19 IOSTANDARD LVCMOS18 } [get_ports { SPI_DEV_CLK }]; #SCK (FT_AD0_SCK) |
| set_property -dict { PACKAGE_PIN AV20 IOSTANDARD LVCMOS18 } [get_ports { SPI_DEV_D0 }]; #SDI (FT_AD1_MOSI) |
| set_property -dict { PACKAGE_PIN AV18 IOSTANDARD LVCMOS18 } [get_ports { SPI_DEV_D1 }]; #SDO (FT_AD2_MISO) |
| set_property -dict { PACKAGE_PIN BA17 IOSTANDARD LVCMOS18 } [get_ports { SPI_DEV_D2 }]; #SDI (FT_AD4)-placeholder |
| set_property -dict { PACKAGE_PIN BB17 IOSTANDARD LVCMOS18 } [get_ports { SPI_DEV_D3 }]; #SDO (FT_AD5)-placeholder |
| set_property -dict { PACKAGE_PIN AW20 IOSTANDARD LVCMOS18 } [get_ports { SPI_DEV_CS_L }];#CSB (FT_AD3_SS) |
| |
| ## JTAG (Dedicate JTAG pin header for ARM/RISC-V, connected to header J291 through level shifter U291) |
| ## in bank 65 and 66 LVCMOS18 |
| ## This is different from CW310 in which JTAG and SPI_Device are overlaid. |
| ## TODO(pbf): Check PULLUP/DN for JTAG signals |
| set_property -dict { PACKAGE_PIN BE18 IOSTANDARD LVCMOS18 PULLTYPE PULLDOWN } [get_ports { IOR0 }]; #JTAG TMS (FPGA_ARM_TMS) |
| set_property -dict { PACKAGE_PIN BE17 IOSTANDARD LVCMOS18 PULLTYPE PULLDOWN } [get_ports { IOR1 }]; #JTAG TDO (FPGA_ARM_TDO) |
| set_property -dict { PACKAGE_PIN BB19 IOSTANDARD LVCMOS18 PULLTYPE PULLDOWN } [get_ports { IOR2 }]; #JTAG TDI (FPGA_ARM_TDI) |
| set_property -dict { PACKAGE_PIN AW18 IOSTANDARD LVCMOS18 PULLTYPE PULLDOWN } [get_ports { IOR3 }]; #JTAG TCK (FPGA_ARM_TCLK) |
| set_property -dict { PACKAGE_PIN BC19 IOSTANDARD LVCMOS18 } [get_ports { IOR4 }]; #JTAG_TRST (FPGA_ARAM_TRSTN) |
| set_property -dict { PACKAGE_PIN BC16 IOSTANDARD LVCMOS18 PULLTYPE PULLUP } [get_ports { JTAG_SRST_N }]; #JTAG SRST (FPGA_ARM_NSRST) |
| |
| ## SPI HOST (connected to FLASH1 U6 on Nexus, FPGA Bank 73, LVCMOS18) |
| set_property -dict { PACKAGE_PIN A16 IOSTANDARD LVCMOS18 } [get_ports { SPI_HOST_CLK }]; #SCK (FLASH1_SCK) |
| set_property -dict { PACKAGE_PIN B16 IOSTANDARD LVCMOS18 PULLTYPE PULLUP } [get_ports { SPI_HOST_D0 }]; #SDO (FLASH1_D0) |
| set_property -dict { PACKAGE_PIN C13 IOSTANDARD LVCMOS18 PULLTYPE PULLUP } [get_ports { SPI_HOST_D1 }]; #SD1 (FLASH1_D1) |
| set_property -dict { PACKAGE_PIN C12 IOSTANDARD LVCMOS18 PULLTYPE PULLUP } [get_ports { SPI_HOST_D2 }]; #SD2 (FLASH1_D2) |
| set_property -dict { PACKAGE_PIN H15 IOSTANDARD LVCMOS18 PULLTYPE PULLUP } [get_ports { SPI_HOST_D3 }]; #SD3 (FLASH1_D3) |
| set_property -dict { PACKAGE_PIN A14 IOSTANDARD LVCMOS18 } [get_ports { SPI_HOST_CS_L }]; #CSB (FLASH1_CSB) |
| ## TODO(pbf): assign reset pin for external Flash. |
| set_property -dict { PACKAGE_PIN C15 IOSTANDARD LVCMOS18 PULLTYPE PULLUP } [ get_ports { IOC12 }]; #RSTB (FLASH1_RSTB) |
| |
| ## Nexus PMOD3 connect to interace Connector (J263, 3.3V through level shifter), Bank62 LVCMOS18 |
| #set_property -dict { PACKAGE_PIN AU40 IOSTANDARD LVCMOS18 } [get_ports { IOC2 }]; #PMOD3_1_FPGA |
| #set_property -dict { PACKAGE_PIN AV40 IOSTANDARD LVCMOS18 } [get_ports { IOC3 }]; #PMOD3_2_FPGA USED FOR UART to match nexus |
| #set_property -dict { PACKAGE_PIN AW40 IOSTANDARD LVCMOS18 } [get_ports { IOC4 }]; #PMOD3_3_FPGA USED FOR UART to match nexus |
| set_property -dict { PACKAGE_PIN AY39 IOSTANDARD LVCMOS18 } [get_ports { IOA0 }]; #PMOD3_4_FPGA IOA0 moved for IOC8 TAP0 |
| set_property -dict { PACKAGE_PIN AU39 IOSTANDARD LVCMOS18 } [get_ports { IOC6 }]; #PMOD3_7_FPGA |
| set_property -dict { PACKAGE_PIN AV39 IOSTANDARD LVCMOS18 } [get_ports { IOC7 }]; #PMOD3_8_FPGA |
| set_property -dict { PACKAGE_PIN AW37 IOSTANDARD LVCMOS18 } [get_ports { IOA1 }]; #PMOD3_9_FPGA IOA1 moved for IOC5 TAP1 |
| set_property -dict { PACKAGE_PIN AW38 IOSTANDARD LVCMOS18 } [get_ports { IOC9 }]; #PMOD3_10_FPGA |
| |
| |
| ## Parallel Camera Nexus SMC J14 pins for HPS |
| #FORMAT: ASSIGNMENT #SIGNAL_DESCRIPTION #NEXUS_SIGNAL_NAME |
| #set_property -dict { PACKAGE_PIN BE35 IOSTANDARD LVCMOS18 } [get_ports { ISP_DVP_D0 }]; #PCAM_D0 #FMC_LA021_P |
| #set_property -dict { PACKAGE_PIN BD30 IOSTANDARD LVCMOS18 } [get_ports { ISP_DVP_D1 }]; #PCAM_D1 #FMC_LA12_P |
| #set_property -dict { PACKAGE_PIN BB36 IOSTANDARD LVCMOS18 } [get_ports { ISP_DVP_D2 }]; #PCAM_D2 #FMC_LA26_P |
| #set_property -dict { PACKAGE_PIN BF30 IOSTANDARD LVCMOS18 } [get_ports { ISP_DVP_D3 }]; #PCAM_D3 #FMC_LA011_P |
| #set_property -dict { PACKAGE_PIN BA35 IOSTANDARD LVCMOS18 } [get_ports { ISP_DVP_D4 }]; #PCAM_D4 #FMC_LA27_P |
| #set_property -dict { PACKAGE_PIN BD32 IOSTANDARD LVCMOS18 } [get_ports { ISP_DVP_D5 }]; #PCAM_D5 #FMC_LA16_P |
| #set_property -dict { PACKAGE_PIN BC35 IOSTANDARD LVCMOS18 } [get_ports { ISP_DVP_D6 }]; #PCAM_D6 #FMC_LA25_P |
| #set_property -dict { PACKAGE_PIN BE32 IOSTANDARD LVCMOS18 } [get_ports { ISP_DVP_D7 }]; #PCAM_D7 #FMC_LA015_P |
| #set_property -dict { PACKAGE_PIN AY32 IOSTANDARD LVCMOS18 } [get_ports { ISP_DVP_PCLK}]; #PCAM_PCLK #FMC_LA18_CC_P |
| ##set_property -dict { PACKAGE_PIN AW31 IOSTANDARD LVCMOS18 } [get_ports { ISP_DVP_MCLK }]; #PCAM_MCLK #FMC_LA17_CC_P |
| #set_property -dict { PACKAGE_PIN BF26 IOSTANDARD LVCMOS18 } [get_ports { ISP_DVP_VSYNC }]; #PCAM_FVLD #FMC_LA04_P |
| #set_property -dict { PACKAGE_PIN BE29 IOSTANDARD LVCMOS18 } [get_ports { ISP_DVP_HSYNC }]; #PCAM_LVLD #FMC_LA07_P |
| #set_property -dict { PACKAGE_PIN BE34 IOSTANDARD LVCMOS18 } [get_ports { CAM_SCL }]; #PCAM_SCL #FMC_LA019_P |
| #set_property -dict { PACKAGE_PIN BC33 IOSTANDARD LVCMOS18 } [get_ports { CAM_SDA }]; #PCAM_SDA #FMC_LA20_P |
| #set_property -dict { PACKAGE_PIN BD28 IOSTANDARD LVCMOS18 } [get_ports { CAM_INT }]; # #FMC_LA08_P |
| #set_property -dict { PACKAGE_PIN AT37 IOSTANDARD LVCMOS18 } [get_ports { CAM_TRIG }]; #PMOD2_10_FPGA #NOT USED IN HPS > left at pmod |
| |
| |
| ### Nexus PMOD1 and 2 for Valiant camera parallel interace Connector (J255), Bank63 LVCMOS18 |
| ### 6/23/23. pbf changed Cam interface (ISP_DVP_*, CAM_SCL, CAM_SDA CAM_INT, CAM_TRIG) from DIO to MIO. |
| set_property -dict { PACKAGE_PIN AK29 IOSTANDARD LVCMOS18 } [get_ports { IOB0 }]; #PMOD1_7_FPGA -ISP_DVP_D0 |
| set_property -dict { PACKAGE_PIN AL29 IOSTANDARD LVCMOS18 } [get_ports { IOB1 }]; #PMOD1_1_FPGA -ISP_DVP_D1 |
| set_property -dict { PACKAGE_PIN AL31 IOSTANDARD LVCMOS18 } [get_ports { IOB2 }]; #PMOD1_8_FPGA -ISP_DVP_D2 |
| set_property -dict { PACKAGE_PIN AL32 IOSTANDARD LVCMOS18 } [get_ports { IOB3 }]; #PMOD1_2_FPGA -ISP_DVP_D3 |
| set_property -dict { PACKAGE_PIN AL30 IOSTANDARD LVCMOS18 } [get_ports { IOB4 }]; #PMOD1_9_FPGA -ISP_DVP_D4 |
| set_property -dict { PACKAGE_PIN AM29 IOSTANDARD LVCMOS18 } [get_ports { IOB5 }]; #PMOD1_3_FPGA -ISP_DVP_D5 |
| set_property -dict { PACKAGE_PIN AM33 IOSTANDARD LVCMOS18 } [get_ports { IOB6 }]; #PMOD1_10_FPGA -ISP_DVP_D6 |
| set_property -dict { PACKAGE_PIN AM32 IOSTANDARD LVCMOS18 } [get_ports { IOB7 }]; #PMOD1_4_FPGA -ISP_DVP_D7 |
| set_property -dict { PACKAGE_PIN AN33 IOSTANDARD LVCMOS18 } [get_ports { IOB8 }]; #PMOD2_1_FPGA -ISP_DVP_PCLK |
| #set_property -dict { PACKAGE_PIN AN34 IOSTANDARD LVCMOS18 } [get_ports { ISP_DVP_MCLK }]; #PMOD2_7_FPGA -ISP_DVP_MCLK |
| set_property -dict { PACKAGE_PIN AM31 IOSTANDARD LVCMOS18 } [get_ports { IOA2 }]; #PMOD2_2_FPGA -ISP_DVP_VSYNC |
| set_property -dict { PACKAGE_PIN AP33 IOSTANDARD LVCMOS18 } [get_ports { IOA3 }]; #PMOD2_8_FPGA -ISP_DVP_HSYNC |
| set_property -dict { PACKAGE_PIN AR35 IOSTANDARD LVCMOS18 } [get_ports { IOA4 }]; #PCAM_SCL/PMOD2_9_FPGA -CAM_SCL |
| set_property -dict { PACKAGE_PIN AT35 IOSTANDARD LVCMOS18 } [get_ports { IOA5 }]; #PCAM_SDA/PMOD2_3_FPGA -CAM_SDA |
| set_property -dict { PACKAGE_PIN AT36 IOSTANDARD LVCMOS18 } [get_ports { IOA6 }]; #PMOD2_4_FPGA -CAM_INT |
| set_property -dict { PACKAGE_PIN AT37 IOSTANDARD LVCMOS18 } [get_ports { IOA7 }]; #PMOD2_10_FPGA -CAM_TRIG |
| |
| |
| |
| # PMOD4: (Bank62) Temporarily repurposed for demo display. SPI + 2x (incl CS) + 2x GPIO Required. |
| # 6/23/23. pbf changed SPI_HOST2 interface from DIO to MIO. |
| set_property -dict { PACKAGE_PIN AY38 IOSTANDARD LVCMOS18 } [get_ports { IOB10 }]; #PMOD4_1_FPGA -SPI_HOST2_D0 |
| set_property -dict { PACKAGE_PIN BA39 IOSTANDARD LVCMOS18 } [get_ports { IOB11 }]; #PMOD4_2_FPGA -SPI_HOST2_D1 |
| set_property -dict { PACKAGE_PIN AW35 IOSTANDARD LVCMOS18 } [get_ports { IOB12 }]; #PMOD4_3_FPGA -SPI_HOST2_D2 |
| set_property -dict { PACKAGE_PIN AY35 IOSTANDARD LVCMOS18 } [get_ports { IOR11 }]; #PMOD4_4_FPGA -SPI_HOST2_D3 |
| set_property -dict { PACKAGE_PIN AY40 IOSTANDARD LVCMOS18 } [get_ports { IOR12 }]; #PMOD4_7_FPGA -SPI_HOST2_CLK |
| set_property -dict { PACKAGE_PIN BA40 IOSTANDARD LVCMOS18 } [get_ports { IOR13 }]; #PMOD4_8_FPGA -SPI_HOST2_CS_L |
| #set_property -dict { PACKAGE_PIN AW36 IOSTANDARD LVCMOS18 } [get_ports { IOB7 }]; #PMOD4_9_FPGA |
| #set_property -dict { PACKAGE_PIN BC40 IOSTANDARD LVCMOS18 } [get_ports { IOB8 }]; #PMOD4_10_FPGA |
| |
| ##OLD## J271 pins for prototyping. Bank 63 -- IOB7/8 previously for display control moved. IOD0/1 will be used for display control signals for demo. |
| set_property -dict { PACKAGE_PIN AK30 IOSTANDARD LVCMOS18 } [get_ports { IOD0 }]; #EXP1x10_J271_P1 |
| set_property -dict { PACKAGE_PIN AJ30 IOSTANDARD LVCMOS18 } [get_ports { IOD1 }]; #EXP1x10_J271_P3 |
| set_property -dict { PACKAGE_PIN AH30 IOSTANDARD LVCMOS18 } [get_ports { IOD2 }]; #EXP1x10_J271_P5 |
| set_property -dict { PACKAGE_PIN AJ31 IOSTANDARD LVCMOS18 } [get_ports { IOD3 }]; #EXP1x10_J271_P7 |
| set_property -dict { PACKAGE_PIN AG31 IOSTANDARD LVCMOS18 } [get_ports { IOD4 }]; #EXP1x10_J271_P9 |
| set_property -dict { PACKAGE_PIN AH31 IOSTANDARD LVCMOS18 } [get_ports { IOD5 }]; #EXP1x10_J271_P11 |
| # set_property -dict { PACKAGE_PIN AG32 IOSTANDARD LVCMOS18 } [get_ports { xx }]; #EXP1x10_J271_P13 |
| #EXP1x10_J271_P19 held by IO_UPHY_DPPULLUP |
| #EXP1x10_J271_P17 unused |
| # set_property -dict { PACKAGE_PIN AG33 IOSTANDARD LVCMOS18 } [get_ports { xx }]; #EXP1x10_J271_P19 |
| |
| ###2## IO_TRIGGER, IO_CLKOUT and USB signals moved to FMC_HA pins for now. Skipping FMC_HA00_CC, FMC_HA01_CC as they are clocks |
| set_property -dict { PACKAGE_PIN BD13 IOSTANDARD LVCMOS18 } [get_ports { IO_TRIGGER }]; #FMC_HA02_P |
| set_property -dict { PACKAGE_PIN BE13 IOSTANDARD LVCMOS18 } [get_ports { IO_CLKOUT }]; #FMC_HA02_N |
| set_property -dict { PACKAGE_PIN BD12 IOSTANDARD LVCMOS18 } [get_ports { USB_P }]; #FMC_HA03_P |
| set_property -dict { PACKAGE_PIN BE12 IOSTANDARD LVCMOS18 } [get_ports { USB_N }]; #FMC_HA03_N |
| set_property -dict { PACKAGE_PIN BB13 IOSTANDARD LVCMOS18 } [get_ports { IO_USB_SENSE0 }]; #FMC_HA04_P |
| set_property -dict { PACKAGE_PIN BB12 IOSTANDARD LVCMOS18 } [get_ports { IO_USB_DNPULLUP0 }]; #FMC_HA04_N |
| set_property -dict { PACKAGE_PIN BC11 IOSTANDARD LVCMOS18 } [get_ports { IO_USB_DPPULLUP0 }]; #FMC_HA05_P |
| set_property -dict { PACKAGE_PIN BD11 IOSTANDARD LVCMOS18 } [get_ports { IOB9 }]; #FMC_HA05_N |
| |
| |
| ## TI TUSB1T1105AMHX USB Transceiver "usbdev" testing, Bank 64 LVCMOS18 |
| #set_property -dict { PACKAGE_PIN AW23 IOSTANDARD LVCMOS18 } [get_ports { IO_UPHY_DP_TX }]; #USB0_VPO |
| #set_property -dict { PACKAGE_PIN AW22 IOSTANDARD LVCMOS18 } [get_ports { IO_UPHY_DN_TX }]; #USB0_VMO |
| #set_property -dict { PACKAGE_PIN AY22 IOSTANDARD LVCMOS18 } [get_ports { IO_UPHY_DP_RX }]; #USB0_VP |
| #set_property -dict { PACKAGE_PIN BA22 IOSTANDARD LVCMOS18 } [get_ports { IO_UPHY_DN_RX }]; #USB0_VM |
| ## USRUSB_SOFTCONN(not used, conneted to xxxxx as placeholder) |
| #set_property -dict { PACKAGE_PIN AH33 IOSTANDARD LVCMOS18 } [get_ports { IO_UPHY_DPPULLUP }]; ## MOVED TO EXP1x10_J271_P15 to clear up PMOD4 |
| ## Roman added USB voltage sense pin to AY17 of Bank65 of Nexus FPGA in the latest revision board. |
| #set_property -dict { PACKAGE_PIN AY17 IOSTANDARD LVCMOS18 } [get_ports { IO_UPHY_SENSE }]; #USB0_VBUS_SENSEB |
| #set_property -dict { PACKAGE_PIN AU21 IOSTANDARD LVCMOS18 } [get_ports { IO_UPHY_OE_N }]; #USB0_OEB |
| #set_property -dict { PACKAGE_PIN AV21 IOSTANDARD LVCMOS18 } [get_ports { IO_UPHY_D_RX }]; #USB0_RCV |
| ## TODO(pbf): Re-use port IO_UPHY_SPD/SUS for MODE/CFG of TI USB1T1105A tranciver. Need to tie either high or low with logic. |
| #set_property -dict { PACKAGE_PIN BA21 IOSTANDARD LVCMOS18 PULLTYPE PULLUP} [get_ports { IO_UPHY_SPD }]; #USB0_MODE |
| #set_property -dict { PACKAGE_PIN AT21 IOSTANDARD LVCMOS18 PULLTYPE PULLUP} [get_ports { IO_UPHY_SUS }]; #USB0_CFG |
| |
| ## UART0 (Security Core UART0, default connect to FTDI CDBUS, late may map to SOM_FPGA_GPIO for in-system monitor) |
| ## Bank 65, LVCMOS18 |
| set_property -dict { PACKAGE_PIN BF20 IOSTANDARD LVCMOS18 } [get_ports { IOC4 }]; #FTDI_RX_FPGA_TX_1P8 - Matcha UART0 TX FTDI |
| set_property -dict { PACKAGE_PIN BD20 IOSTANDARD LVCMOS18 } [get_ports { IOC3 }]; #FTDI_TX_FPGA_RX_1P8 - Matcha UART0 RX FTDI |
| #set_property -dict { PACKAGE_PIN BC20 IOSTANDARD LVCMOS18 } [get_ports { xx }]; #FTDI_FPGA_CTS - not used in Matcha |
| #set_property -dict { PACKAGE_PIN BE20 IOSTANDARD LVCMOS18 } [get_ports { xx }]; #FTDI_FPGA_RTS - not used in Matcha |
| |
| ## UART1 (Security Core UART1 or SMC core UART, default connect to CP2103 U250, Bank 74, LVCMOS18 |
| ## late may map to SOM_FPGA_GPIO for in-system monitor) |
| set_property -dict { PACKAGE_PIN R23 IOSTANDARD LVCMOS18 } [get_ports { IOC11 }]; #FPGA_UART_TX - Matcha UART1 TX CP210 USB |
| set_property -dict { PACKAGE_PIN T23 IOSTANDARD LVCMOS18 } [get_ports { IOC10 }]; #FPGA_UART_RX - Matcha UART1 RX CP210 USB |
| #set_property -dict { PACKAGE_PIN P22 IOSTANDARD LVCMOS18 } [get_ports { xx }]; #FPGA_UART_CTS - not used in Matcha |
| #set_property -dict { PACKAGE_PIN R22 IOSTANDARD LVCMOS18 } [get_ports { xx }]; #FPGA_UART_RTS - not used in Matcha |
| |
| ## Configuration options, can be used for all designs |
| set_property CONFIG_VOLTAGE 1.8 [current_design] |
| ## Different from 7 Series or UltraScale, no CFGBVS pin in UltraScal+ device, |
| ## Became RSVGND pin and need to be connected to GND (as Nexus schematic pin AB11) |
| #set_property CFGBVS GND [current_design] |
| |
| # Bootstrap pins |
| set_property -dict { PACKAGE_PIN AU18 IOSTANDARD LVCMOS18 } [get_ports { IOC0 }]; # Bootstrap0 |
| set_property -dict { PACKAGE_PIN AU19 IOSTANDARD LVCMOS18 } [get_ports { IOC1 }]; # Bootstrap1 |
| set_property -dict { PACKAGE_PIN AR20 IOSTANDARD LVCMOS18 } [get_ports { IOC2 }]; # Bootstrap2 |
| set_property -dict { PACKAGE_PIN AR19 IOSTANDARD LVCMOS18 } [get_ports { POR_N }]; |
| |
| # Pushbuttons and LEDs on 1.2V Bank 68 |
| set_property -dict { PACKAGE_PIN U32 DRIVE 8 IOSTANDARD LVCMOS12 } [get_ports { POR_BUTTON_N }]; #PBC3 BUTTON |
| |
| set_property -dict { PACKAGE_PIN W31 DRIVE 8 IOSTANDARD LVCMOS12 } [get_ports { IOR5 }]; #PBA1 BUTTON |
| set_property -dict { PACKAGE_PIN U33 DRIVE 8 IOSTANDARD LVCMOS12 } [get_ports { IOR6 }]; #PBA2 BUTTON |
| set_property -dict { PACKAGE_PIN T35 DRIVE 8 IOSTANDARD LVCMOS12 } [get_ports { IOR7 }]; #PBA3 BUTTON |
| # IOR8, IOR9 are direct connect pins |
| set_property -dict { PACKAGE_PIN W32 DRIVE 8 IOSTANDARD LVCMOS12 } [get_ports { IOR10 }]; #PBB1 BUTTON |
| #set_property -dict { PACKAGE_PIN V30 DRIVE 8 IOSTANDARD LVCMOS12 } [get_ports { IOR11 }]; #PBB2 BUTTON MOVED TO SPI |
| #set_property -dict { PACKAGE_PIN T36 DRIVE 8 IOSTANDARD LVCMOS12 } [get_ports { IOR12 }]; #PBB3 BUTTON MOVED TO SPI |
| |
| ## # 6/23/23. pbf comment out following two placeholder bank assignment and reuse the IOB/IORs for SPI_host2 |
| # Placeholder 1.8V BANK63 GPIO J2611 |
| #set_property -dict { PACKAGE_PIN AL36 IOSTANDARD LVCMOS18 } [get_ports { IOB10 }]; #FPGA_EXP6X1_1_P2 |
| #set_property -dict { PACKAGE_PIN AM34 IOSTANDARD LVCMOS18 } [get_ports { IOB11 }]; #FPGA_EXP6X1_1_P3 |
| #set_property -dict { PACKAGE_PIN AM36 IOSTANDARD LVCMOS18 } [get_ports { IOB12 }]; #FPGA_EXP6X1_1_P4 |
| # Placeholder 1.8V BANK63 GPIO J2612 |
| set_property -dict { PACKAGE_PIN AJ33 IOSTANDARD LVCMOS18 } [get_ports { IOR8 }]; #FPGA_EXP6X1_2_P4 DIRECT ec_rst_l |
| set_property -dict { PACKAGE_PIN AJ32 IOSTANDARD LVCMOS18 } [get_ports { IOR9 }]; #FPGA_EXP6X1_2_P5 DIRECT flash_wp_l |
| # Placeholder 1.8V BANK63 GPIO J2613 |
| #set_property -dict { PACKAGE_PIN AP38 IOSTANDARD LVCMOS18 } [get_ports { IOR13 }]; #FPGA_EXP6X1_3_P5 |
