Migrate fastvdma and build in hw/matcha
Change-Id: I50179f9f39279d58f73a57fc2c13a5883170f917
diff --git a/BUILD.bazel b/BUILD.bazel
index ee42854..0f0a46b 100644
--- a/BUILD.bazel
+++ b/BUILD.bazel
@@ -12,6 +12,7 @@
"@lowrisc_opentitan//hw/dv:BUILD",
"@lowrisc_opentitan//hw/ip:BUILD",
"@kelvin_hw//hdl/chisel:kelvin.core",
+ "//hw/top_matcha/ip/dma/chisel:fastvdma.core",
"@lowrisc_opentitan//hw/lint:BUILD",
"@lowrisc_opentitan//hw/vendor:BUILD",
# Place the following file to make compilation works
diff --git a/hw/dv/tools/dvsim/fusesoc.hjson b/hw/dv/tools/dvsim/fusesoc.hjson
index db7c762..522e5a6 100644
--- a/hw/dv/tools/dvsim/fusesoc.hjson
+++ b/hw/dv/tools/dvsim/fusesoc.hjson
@@ -13,6 +13,7 @@
"--setup {fusesoc_core}"]
fusesoc_cores_root_dirs: ["--cores-root {titan_root}/hw/ip",
"--cores-root {proj_root}/bazel-bin/external/kelvin_hw/hdl/chisel",
+ "--cores-root {proj_root}/bazel-bin/hw/top_matcha/ip/dma/chisel",
"--cores-root {titan_root}/hw/dv/sv",
"--cores-root {titan_root}/hw/dv/verilator",
"--cores-root {titan_root}/hw/formal",
diff --git a/hw/top_matcha/ip/dma/chisel/BUILD b/hw/top_matcha/ip/dma/chisel/BUILD
new file mode 100644
index 0000000..2a102ea
--- /dev/null
+++ b/hw/top_matcha/ip/dma/chisel/BUILD
@@ -0,0 +1,45 @@
+# Copyright 2023 Google LLC
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+genrule(
+ name = "fastvdma_verilog",
+ srcs = [
+ "//hw/top_matcha/ip/dma/chisel/src:DMATop.sv"
+ ],
+ outs = [
+ "fastvdma.sv",
+ ],
+
+ cmd = """
+ cat $(location //hw/top_matcha/ip/dma/chisel/src:DMATop.sv) >> $(location fastvdma.sv)
+ """,
+ visibility = ["//visibility:public"],
+)
+
+# Generate fastvdma.core from this template so it can sit at the same GenDir as
+# the RTL file.
+genrule(
+ name = "fastvdma_core",
+ srcs = [
+ "fastvdma.core.in",
+ "fastvdma_verilog",
+ ],
+ outs = [
+ "fastvdma.core",
+ ],
+ cmd = """
+ cp -f $(location fastvdma.core.in) $(location fastvdma.core)
+ """,
+ visibility = ["//visibility:public"],
+)
diff --git a/hw/top_matcha/ip/dma/chisel/fastvdma.core.in b/hw/top_matcha/ip/dma/chisel/fastvdma.core.in
new file mode 100644
index 0000000..6131837
--- /dev/null
+++ b/hw/top_matcha/ip/dma/chisel/fastvdma.core.in
@@ -0,0 +1,34 @@
+CAPI=2:
+# Copyright 2023 Google LLC
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+name: "google:ip:fastvdma:0.1"
+description: "Generated fastvdma originally from Antmicro"
+filesets:
+ files_rtl:
+ files:
+ - fastvdma.sv
+ file_type: systemVerilogSource
+
+parameters:
+ SYNTHESIS:
+ datatype: bool
+ paramtype: vlogdefine
+
+
+targets:
+ default: &default_target
+ filesets:
+ - files_rtl
+ toplevel: fastvdma
+
+ lint:
+ <<: *default_target
+ default_tool: verilator
+ parameters:
+ - SYNTHESIS=true
+ tools:
+ verilator:
+ mode: lint-only
+ verilator_options:
+ - "-Wall"
diff --git a/hw/top_matcha/ip/dma/chisel/src/BUILD b/hw/top_matcha/ip/dma/chisel/src/BUILD
new file mode 100644
index 0000000..745cb3f
--- /dev/null
+++ b/hw/top_matcha/ip/dma/chisel/src/BUILD
@@ -0,0 +1,54 @@
+# Copyright 2024 Google LLC
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+load("@kelvin_hw//rules:chisel.bzl", "chisel_cc_library", "chisel_library")
+
+package(default_visibility = ["//visibility:public"])
+
+chisel_library(
+ name = "fastvdma_tlul",
+ srcs = [
+ "DMAConfig.scala",
+ "DMATop.scala",
+ "bus/TLUL.scala",
+ "csr/CSR.scala",
+ "csr/CSRBusBundle.scala",
+ "csr/CSRRegBundle.scala",
+ "csr/ClearCSR.scala",
+ "csr/SetCSR.scala",
+ "csr/SimpleCSR.scala",
+ "csr/StatusCSR.scala",
+ "frontend/BusBase.scala",
+ "frontend/TLULCSR.scala",
+ "frontend/TLULReader.scala",
+ "frontend/TLULWriter.scala",
+ "worker/AddressGenerator.scala",
+ "worker/AddressGeneratorCtlBundle.scala",
+ "worker/InterruptBundle.scala",
+ "worker/InterruptController.scala",
+ "worker/SyncBundle.scala",
+ "worker/TransferSplitter.scala",
+ "worker/WorkerCSRWrapper.scala",
+ "worker/XferDescBundle.scala",
+ ],
+ deps = [
+ ],
+)
+
+chisel_cc_library(
+ name = "fastvdma_cc_library",
+ chisel_lib = ":fastvdma_tlul",
+ emit_class = "DMAController.EmitDMA",
+ module_name = "DMATop",
+)
diff --git a/hw/top_matcha/ip/dma/chisel/src/DMAConfig.scala b/hw/top_matcha/ip/dma/chisel/src/DMAConfig.scala
new file mode 100644
index 0000000..6d16c81
--- /dev/null
+++ b/hw/top_matcha/ip/dma/chisel/src/DMAConfig.scala
@@ -0,0 +1,35 @@
+/*
+Copyright 2024 Google LLC
+Copyright (C) 2019-2022 Antmicro
+
+http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS,
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
+
+SPDX-License-Identifier: Apache-2.0
+*/
+
+package DMAController.DMAConfig
+
+import chisel3._
+
+object DMAConfig {
+ val addrWidth = 32
+ val readDataWidth = 32
+ val writeDataWidth = 32
+ val readMaxBurst = 0
+ val writeMaxBurst = 256
+ val reader4KBarrier = false
+ val writer4KBarrier = true
+
+ val controlDataWidth = 32
+ val controlAddrWidth = 32
+ val controlRegCount = 16
+
+ val fifoDepth = 512
+
+}
diff --git a/hw/top_matcha/ip/dma/chisel/src/DMATop.scala b/hw/top_matcha/ip/dma/chisel/src/DMATop.scala
new file mode 100644
index 0000000..564e7e3
--- /dev/null
+++ b/hw/top_matcha/ip/dma/chisel/src/DMATop.scala
@@ -0,0 +1,68 @@
+/*
+Copyright 2024 Google LLC
+Copyright (C) 2019-2022 Antmicro
+
+http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS,
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
+
+SPDX-License-Identifier: Apache-2.0
+*/
+
+package DMAController
+
+import chisel3._
+import chisel3.util._
+import DMAController.Bus._
+import DMAController.CSR.CSR
+import DMAController.Frontend._
+import DMAController.Worker.{InterruptBundle, WorkerCSRWrapper, SyncBundle}
+import DMAController.DMAConfig._
+import _root_.circt.stage.ChiselStage
+
+class DMATop extends Module {
+
+ val io = IO(new Bundle{
+ val control = new TLULDevice(DMAConfig.addrWidth, DMAConfig.readDataWidth)
+ val read = new TLULHost(DMAConfig.addrWidth, DMAConfig.readDataWidth)
+ val write = new TLULHost(DMAConfig.addrWidth, DMAConfig.readDataWidth)
+ val irq = new InterruptBundle
+ val sync = new SyncBundle
+ })
+
+ val csrFrontend = Module(new TLULCSR(DMAConfig.addrWidth, DMAConfig.readDataWidth))
+
+ val readerFrontend = Module(new TLULReader(DMAConfig.addrWidth, DMAConfig.readDataWidth))
+
+ val writerFrontend = Module(new TLULWriter(DMAConfig.addrWidth, DMAConfig.readDataWidth))
+
+ val csr = Module(new CSR(DMAConfig.addrWidth))
+
+ val ctl = Module(new WorkerCSRWrapper(DMAConfig.addrWidth, DMAConfig.readDataWidth, DMAConfig.writeDataWidth,
+ DMAConfig.readMaxBurst, DMAConfig.writeMaxBurst, DMAConfig.reader4KBarrier, DMAConfig.writer4KBarrier))
+
+ val queue = Queue(readerFrontend.io.dataIO, DMAConfig.fifoDepth)
+ queue <> writerFrontend.io.dataIO
+
+ csrFrontend.io.ctl <> io.control
+ csr.io.bus <> csrFrontend.io.bus
+ ctl.io.csr <> csr.io.csr
+ readerFrontend.io.xfer <> ctl.io.xferRead
+ writerFrontend.io.xfer <> ctl.io.xferWrite
+
+ io.read <> readerFrontend.io.bus
+ io.write <> writerFrontend.io.bus
+
+ io.irq <> ctl.io.irq
+ io.sync <> ctl.io.sync
+
+ assert(DMAConfig.readDataWidth == DMAConfig.writeDataWidth)
+}
+
+object EmitDMA extends App{
+ ChiselStage.emitSystemVerilogFile(new DMATop, args)
+}
diff --git a/hw/top_matcha/ip/dma/chisel/src/bus/TLUL.scala b/hw/top_matcha/ip/dma/chisel/src/bus/TLUL.scala
new file mode 100644
index 0000000..470877a
--- /dev/null
+++ b/hw/top_matcha/ip/dma/chisel/src/bus/TLUL.scala
@@ -0,0 +1,138 @@
+/*
+Copyright 2024 Google LLC
+Copyright (C) 2019-2022 Antmicro
+
+http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS,
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
+
+SPDX-License-Identifier: Apache-2.0
+*/
+
+package DMAController.Bus
+
+import chisel3._
+
+class TLULA(val addrWidth : Int, val dataWidth: Int) extends Bundle{
+ val opcode = Output(UInt(TLUL.codeWidth.W))
+ val param = Output(UInt(TLUL.aparamWidth.W))
+ val size = Output(UInt(TLUL.size.W))
+ val source = Output(UInt(TLUL.sourceWidth.W))
+ val address = Output(UInt(addrWidth.W))
+ val mask = Output(UInt((dataWidth/8).W))
+ val data = Output(UInt(dataWidth.W))
+ val corrupt = Output(Bool())
+ val valid = Output(Bool())
+ val ready = Input(Bool())
+}
+
+object TLULA {
+ def apply(addr : UInt, data : UInt, valid : UInt) : TLULA = {
+ val a = Wire(new TLULA(addr.getWidth, data.getWidth))
+ a.opcode := 0.U
+ a.param := 0.U
+ a.size := 0.U
+ a.source := 0.U
+ a.address := addr
+ a.mask := 0.U
+ a.data := data
+ a.corrupt := 0.U
+ a.valid := valid
+ a.ready := 0.U
+ a
+ }
+ def tieOff(addrWidth : Int, dataWidth: Int): TLULA = {
+ val a = Wire(new TLULA(addrWidth, dataWidth))
+ a.opcode := 0.U
+ a.param := 0.U
+ a.size := 0.U
+ a.source := 0.U
+ a.address := 0.U
+ a.mask := 0.U
+ a.data := 0.U
+ a.corrupt := 0.U
+ a.valid := 0.U
+ a.ready := 0.U
+ a
+ }
+}
+
+class TLULD(val addrWidth : Int, val dataWidth: Int) extends Bundle{
+ val opcode = Output(UInt(TLUL.codeWidth.W))
+ val param = Output(UInt(TLUL.dparamWidth.W))
+ val size = Output(UInt(TLUL.size.W))
+ val source = Output(UInt(TLUL.sourceWidth.W))
+ val sink = Output(UInt(TLUL.sinkWidth.W))
+ val denied = Output(Bool())
+ val data = Output(UInt(dataWidth.W))
+ val corrupt = Output(Bool())
+ val valid = Output(Bool())
+ val ready = Input(Bool())
+}
+
+object TLULD {
+ def apply(addr : UInt, data : UInt, valid : UInt) : TLULD = {
+ val d = Wire(new TLULD(addr.getWidth, data.getWidth))
+ d.opcode := 0.U
+ d.param := 0.U
+ d.size := 0.U
+ d.source := 0.U
+ d.sink := 0.U
+ d.denied := 0.U
+ d.data := data
+ d.corrupt := 0.U
+ d.valid := valid
+ d.ready := 0.U
+ d
+ }
+ def tieOff(addrWidth : Int, dataWidth : Int): TLULD = {
+ val d = Wire(new TLULD(addrWidth, dataWidth))
+ d.opcode := 0.U
+ d.param := 0.U
+ d.size := 0.U
+ d.source := 0.U
+ d.sink := 0.U
+ d.denied := 0.U
+ d.data := 0.U
+ d.corrupt := 0.U
+ d.valid := 0.U
+ d.ready := 0.U
+ d
+ }
+}
+
+class TLULHost (val addrWidth : Int, val dataWidth: Int) extends Bundle{
+ val a = new TLULA(addrWidth, dataWidth);
+ val d = Flipped(new TLULD(addrWidth, dataWidth));
+}
+
+class TLULDevice (val addrWidth : Int, val dataWidth: Int) extends Bundle{
+ val a = Flipped(new TLULA(addrWidth, dataWidth));
+ val d = new TLULD(addrWidth, dataWidth);
+}
+
+object TLUL {
+ // Bus constants
+ val codeWidth = 3
+ val aparamWidth = 3
+ val dparamWidth = 3
+ val sourceWidth = 10
+ val sinkWidth = 1
+ val size = 2 // 2^size bytes
+
+}
+
+object TLOp {
+ val PutFull = 0.U
+ val PutPartial = 1.U
+ val Get = 4.U
+}
+
+object TLResp {
+ val AccessAck = 0.U
+ val AccessAckData = 1.U
+}
diff --git a/hw/top_matcha/ip/dma/chisel/src/csr/CSR.scala b/hw/top_matcha/ip/dma/chisel/src/csr/CSR.scala
new file mode 100644
index 0000000..8099948
--- /dev/null
+++ b/hw/top_matcha/ip/dma/chisel/src/csr/CSR.scala
@@ -0,0 +1,47 @@
+/*
+Copyright 2024 Google LLC
+Copyright (C) 2019-2022 Antmicro
+
+http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS,
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
+
+SPDX-License-Identifier: Apache-2.0
+*/
+
+package DMAController.CSR
+
+import chisel3._
+import DMAController.DMAConfig._
+
+class CSR(val addrWidth : Int) extends Module{
+ val io = IO(new Bundle{
+ val csr: Vec[CSRRegBundle] = Vec(DMAConfig.controlRegCount, new CSRRegBundle())
+ val bus = Flipped(new CSRBusBundle)
+ })
+
+ val data = WireInit(0.U(DMAConfig.controlDataWidth.W))
+
+ io.bus.dataIn := data
+
+ for(i <- 0 until DMAConfig.controlRegCount){
+ when(io.bus.addr === i.U && io.bus.read){
+ data := io.csr(i).dataIn
+ io.csr(i).dataRead := true.B
+ }.otherwise{
+ io.csr(i).dataRead := false.B
+ }
+
+ when(io.bus.addr === i.U && io.bus.write){
+ io.csr(i).dataOut := io.bus.dataOut
+ io.csr(i).dataWrite := true.B
+ }.otherwise{
+ io.csr(i).dataWrite := false.B
+ io.csr(i).dataOut := 0.U
+ }
+ }
+}
diff --git a/hw/top_matcha/ip/dma/chisel/src/csr/CSRBusBundle.scala b/hw/top_matcha/ip/dma/chisel/src/csr/CSRBusBundle.scala
new file mode 100644
index 0000000..cb460aa
--- /dev/null
+++ b/hw/top_matcha/ip/dma/chisel/src/csr/CSRBusBundle.scala
@@ -0,0 +1,28 @@
+/*
+Copyright 2024 Google LLC
+Copyright (C) 2019-2022 Antmicro
+
+http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS,
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
+
+SPDX-License-Identifier: Apache-2.0
+*/
+
+package DMAController.CSR
+
+import DMAController.DMAConfig._
+import chisel3._
+import chisel3.util.log2Ceil
+
+class CSRBusBundle extends Bundle {
+ val addr = Output(UInt(log2Ceil(DMAConfig.controlRegCount).W))
+ val dataOut = Output(UInt(DMAConfig.controlDataWidth.W))
+ val dataIn = Input(UInt(DMAConfig.controlDataWidth.W))
+ val write = Output(Bool())
+ val read = Output(Bool())
+}
diff --git a/hw/top_matcha/ip/dma/chisel/src/csr/CSRRegBundle.scala b/hw/top_matcha/ip/dma/chisel/src/csr/CSRRegBundle.scala
new file mode 100644
index 0000000..06303e8
--- /dev/null
+++ b/hw/top_matcha/ip/dma/chisel/src/csr/CSRRegBundle.scala
@@ -0,0 +1,26 @@
+/*
+Copyright 2024 Google LLC
+Copyright (C) 2019-2022 Antmicro
+
+http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS,
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
+
+SPDX-License-Identifier: Apache-2.0
+*/
+
+package DMAController.CSR
+
+import DMAController.DMAConfig._
+import chisel3._
+
+class CSRRegBundle() extends Bundle{
+ val dataRead = Output(Bool())
+ val dataOut = Output(UInt(DMAConfig.controlDataWidth.W))
+ val dataWrite = Output(Bool())
+ val dataIn = Input(UInt(DMAConfig.controlDataWidth.W))
+}
diff --git a/hw/top_matcha/ip/dma/chisel/src/csr/ClearCSR.scala b/hw/top_matcha/ip/dma/chisel/src/csr/ClearCSR.scala
new file mode 100644
index 0000000..22a3d65
--- /dev/null
+++ b/hw/top_matcha/ip/dma/chisel/src/csr/ClearCSR.scala
@@ -0,0 +1,50 @@
+/*
+Copyright 2024 Google LLC
+Copyright (C) 2019-2022 Antmicro
+
+http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS,
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
+
+SPDX-License-Identifier: Apache-2.0
+*/
+
+package DMAController.CSR
+
+import DMAController.DMAConfig._
+import chisel3._
+
+class ClearCSR extends Module{
+ val io = IO(new Bundle{
+ val csr = Flipped(new CSRRegBundle())
+ val value = Output(UInt(DMAConfig.controlDataWidth.W))
+ val clear = Input(UInt(DMAConfig.controlDataWidth.W))
+ })
+
+ val reg = RegInit(0.U(DMAConfig.controlDataWidth.W))
+
+ io.csr.dataIn := reg
+ io.value := reg
+
+ when(io.csr.dataWrite){
+ reg := io.csr.dataOut
+ }.otherwise{
+ reg := reg & (~io.clear).asUInt
+ }
+}
+
+object ClearCSR {
+ def apply(clear : UInt, csrCtl : CSRRegBundle): UInt = {
+ val csr = Module(new ClearCSR())
+
+ csr.io.clear := clear
+
+ csr.io.csr <> csrCtl
+
+ csr.io.value
+ }
+}
diff --git a/hw/top_matcha/ip/dma/chisel/src/csr/SetCSR.scala b/hw/top_matcha/ip/dma/chisel/src/csr/SetCSR.scala
new file mode 100644
index 0000000..2d1376c
--- /dev/null
+++ b/hw/top_matcha/ip/dma/chisel/src/csr/SetCSR.scala
@@ -0,0 +1,52 @@
+/*
+Copyright 2024 Google LLC
+Copyright (C) 2019-2022 Antmicro
+
+http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS,
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
+
+SPDX-License-Identifier: Apache-2.0
+*/
+
+package DMAController.CSR
+
+import chisel3._
+import DMAController.DMAConfig.DMAConfig
+
+class SetCSR extends Module{
+ val io = IO(new Bundle{
+ val csr = Flipped(new CSRRegBundle())
+ val value = Output(UInt(DMAConfig.controlDataWidth.W))
+ val set = Input(UInt(DMAConfig.controlDataWidth.W))
+ })
+
+ val reg = RegInit(0.U(DMAConfig.controlDataWidth.W))
+
+ io.csr.dataIn := reg
+ io.value := reg
+
+ when(io.csr.dataWrite){
+ reg := (reg & (~io.csr.dataOut).asUInt) | io.set
+ }.otherwise{
+ reg := reg | io.set
+ }
+
+}
+
+object SetCSR {
+ def apply(set : UInt, csrCtl : CSRRegBundle): UInt = {
+ val csr = Module(new SetCSR())
+
+ csr.io.set := set
+
+ csr.io.csr <> csrCtl
+
+ csr.io.value
+ }
+}
+
diff --git a/hw/top_matcha/ip/dma/chisel/src/csr/SimpleCSR.scala b/hw/top_matcha/ip/dma/chisel/src/csr/SimpleCSR.scala
new file mode 100644
index 0000000..8c99906
--- /dev/null
+++ b/hw/top_matcha/ip/dma/chisel/src/csr/SimpleCSR.scala
@@ -0,0 +1,46 @@
+/*
+Copyright 2024 Google LLC
+Copyright (C) 2019-2022 Antmicro
+
+http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS,
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
+
+SPDX-License-Identifier: Apache-2.0
+*/
+
+package DMAController.CSR
+
+import chisel3._
+import DMAController.DMAConfig.DMAConfig
+
+class SimpleCSR extends Module{
+ val io = IO(new Bundle{
+ val csr = Flipped(new CSRRegBundle())
+ val value = Output(UInt(DMAConfig.controlDataWidth.W))
+ })
+
+ val reg = RegInit(0.U(DMAConfig.controlDataWidth.W))
+
+ io.csr.dataIn := reg
+ io.value := reg
+
+ when(io.csr.dataWrite){
+ reg := io.csr.dataOut
+ }
+
+}
+
+object SimpleCSR {
+ def apply(csrCtl : CSRRegBundle): UInt = {
+ val csr = Module(new SimpleCSR())
+
+ csr.io.csr <> csrCtl
+
+ csr.io.value
+ }
+}
diff --git a/hw/top_matcha/ip/dma/chisel/src/csr/StatusCSR.scala b/hw/top_matcha/ip/dma/chisel/src/csr/StatusCSR.scala
new file mode 100644
index 0000000..af33eb1
--- /dev/null
+++ b/hw/top_matcha/ip/dma/chisel/src/csr/StatusCSR.scala
@@ -0,0 +1,40 @@
+/*
+Copyright 2024 Google LLC
+Copyright (C) 2019-2022 Antmicro
+
+http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS,
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
+
+SPDX-License-Identifier: Apache-2.0
+*/
+
+package DMAController.CSR
+
+import DMAController.DMAConfig._
+import chisel3._
+
+class StatusCSR extends Module{
+ val io = IO(new Bundle{
+ val csr = Flipped(new CSRRegBundle())
+ val value = Input(UInt(DMAConfig.controlDataWidth.W))
+ })
+
+ val reg = RegNext(io.value)
+
+ io.csr.dataIn := reg
+}
+
+object StatusCSR{
+ def apply(status : UInt, csrCtl : CSRRegBundle): Unit = {
+ val csr = Module(new StatusCSR())
+
+ csr.io.csr <> csrCtl
+
+ csr.io.value := status
+ }
+}
diff --git a/hw/top_matcha/ip/dma/chisel/src/frontend/BusBase.scala b/hw/top_matcha/ip/dma/chisel/src/frontend/BusBase.scala
new file mode 100644
index 0000000..c679fd0
--- /dev/null
+++ b/hw/top_matcha/ip/dma/chisel/src/frontend/BusBase.scala
@@ -0,0 +1,39 @@
+/*
+Copyright 2024 Google LLC
+Copyright (C) 2019-2022 Antmicro
+
+http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS,
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
+
+SPDX-License-Identifier: Apache-2.0
+*/
+
+package DMAController.Frontend
+
+import chisel3._
+import chisel3.util._
+
+import DMAController.Bus._
+import DMAController.CSR.{CSR, CSRBusBundle}
+import DMAController.Worker.{WorkerCSRWrapper, XferDescBundle}
+import DMAController.DMAConfig.DMAConfig
+
+abstract class IOBus[+T] extends Module {
+ val io : Bundle {
+ val bus : T
+ val dataIO : DecoupledIO[UInt]
+ val xfer : XferDescBundle
+ }
+}
+
+abstract class CSRBus [+T] extends Module {
+ val io : Bundle {
+ val bus : CSRBusBundle
+ val ctl : T
+ }
+}
diff --git a/hw/top_matcha/ip/dma/chisel/src/frontend/TLULCSR.scala b/hw/top_matcha/ip/dma/chisel/src/frontend/TLULCSR.scala
new file mode 100644
index 0000000..370e73a
--- /dev/null
+++ b/hw/top_matcha/ip/dma/chisel/src/frontend/TLULCSR.scala
@@ -0,0 +1,104 @@
+/*
+Copyright 2024 Google LLC
+
+http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS,
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
+
+SPDX-License-Identifier: Apache-2.0
+*/
+
+package DMAController.Frontend
+
+import DMAController.Bus._
+import DMAController.CSR.{CSR, CSRBusBundle}
+import DMAController.DMAConfig._
+import DMAController.Worker.{WorkerCSRWrapper}
+import chisel3._
+import chisel3.util._
+
+class TLULCSR(addrWidth : Int, dataWidth : Int) extends CSRBus[TLULDevice]{
+ val io = IO(new Bundle{
+ val ctl = new TLULDevice(addrWidth, dataWidth)
+ val bus = new CSRBusBundle
+ })
+
+ val sIdle :: sGet :: sPut :: Nil = Enum(3)
+ val state = RegInit(sIdle)
+
+ val rsp = WireInit(TLResp.AccessAck)
+ val valid = WireInit(false.B)
+
+ val addr = RegInit(0.U(addrWidth.W))
+ val wdata = RegInit(0.U(dataWidth.W))
+ val sourceId = RegInit(0.U)
+ val size = RegInit(0.U)
+
+ val write = WireInit(false.B)
+
+ io.ctl.a <> TLULA.tieOff(addrWidth, dataWidth)
+
+ // TLUL response
+ io.ctl.d.data := io.bus.dataIn
+ io.ctl.d.opcode := rsp
+ io.ctl.d.valid := valid
+ io.ctl.d.param := 0.U
+ io.ctl.d.size := size
+ io.ctl.d.corrupt := 0.U
+ io.ctl.d.sink := 0.U
+ io.ctl.d.source := sourceId
+ io.ctl.d.denied := 0.U
+
+ // CSR Interface
+ io.bus.addr := addr
+ io.bus.dataOut := wdata
+
+ io.bus.write := write
+ io.bus.read := (state === sGet)
+
+ switch(state) {
+ is(sIdle) {
+ io.ctl.a.ready := true.B
+ valid := false.B
+ write := false.B
+ addr := io.ctl.a.address(5, 2)
+ when(io.ctl.a.valid) {
+ size := io.ctl.a.size
+ sourceId := io.ctl.a.source
+
+ when(io.ctl.a.opcode === TLOp.Get) {
+ state := sGet
+ addr := io.ctl.a.address(5, 2)
+ }.elsewhen(io.ctl.a.opcode === TLOp.PutFull ||
+ io.ctl.a.opcode === TLOp.PutPartial) {
+ addr := io.ctl.a.address(5, 2)
+ wdata := io.ctl.a.data
+ state := sPut
+ }
+ }
+ }
+ is(sGet) {
+ state := sGet
+ rsp := TLResp.AccessAckData
+ valid := true.B
+ when(io.ctl.d.ready) {
+ state := sIdle
+ }
+ }
+ is(sPut) {
+ state := sPut
+ rsp := TLResp.AccessAck
+ valid := true.B
+ when(io.ctl.d.ready) {
+ write := true.B
+ state := sIdle
+ }
+ }
+ }
+
+
+}
diff --git a/hw/top_matcha/ip/dma/chisel/src/frontend/TLULReader.scala b/hw/top_matcha/ip/dma/chisel/src/frontend/TLULReader.scala
new file mode 100644
index 0000000..1230b10
--- /dev/null
+++ b/hw/top_matcha/ip/dma/chisel/src/frontend/TLULReader.scala
@@ -0,0 +1,116 @@
+/*
+Copyright 2024 Google LLC
+
+http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS,
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
+
+SPDX-License-Identifier: Apache-2.0
+*/
+
+package DMAController.Frontend
+
+import DMAController.Bus._
+import DMAController.Worker.{XferDescBundle, WorkerCSRWrapper}
+import DMAController.CSR.CSR
+import chisel3._
+import chisel3.util._
+
+class TLULReader(val addrWidth : Int, val dataWidth : Int) extends IOBus[TLULHost]{
+ val io = IO(new Bundle{
+ val bus = new TLULHost(addrWidth, dataWidth)
+ val dataIO = EnqIO(UInt(dataWidth.W))
+ val xfer = Flipped(new XferDescBundle(addrWidth))
+ })
+
+ val sIdle :: sTransfer :: sWait :: Nil = Enum(3)
+
+ val state = RegInit(sIdle)
+
+ val xferCnt = RegInit(0.U(addrWidth.W))
+ val addr = RegInit(0.U(addrWidth.W))
+ val valid = RegInit(false.B)
+
+ val done = WireInit(false.B)
+ val xferValid = WireInit(false.B)
+ val xfer = WireInit(io.dataIO.ready && io.xfer.valid)
+
+ io.bus.d <> TLULD.tieOff(addrWidth, dataWidth)
+
+ // Producer to fifo
+ io.dataIO.bits := io.bus.d.data
+ io.dataIO.valid := xferValid
+
+ io.bus.a.valid := valid
+ io.bus.a.data := 0.U
+
+ io.bus.a.opcode := TLOp.Get
+ io.bus.a.param := 0.U
+ io.bus.a.size := 2.U
+ io.bus.a.source := 0.U
+ io.bus.a.address := addr
+ io.bus.a.corrupt := 0.U
+ io.bus.a.mask := 0xF.U
+
+ io.xfer.done := done
+
+ switch(state){
+ is(sIdle){
+ valid := false.B
+ io.bus.d.ready := false.B
+ done := false.B
+ xferValid := false.B
+ when(xfer) {
+ valid := true.B
+ state := sTransfer
+ xferCnt := io.xfer.length
+ addr := io.xfer.address
+ }
+ }
+ is(sTransfer){
+ io.bus.d.ready := true.B
+ xferValid := false.B
+ when(io.bus.a.ready) {
+ valid := false.B
+ state := sWait
+
+ when(xferCnt =/= 0.U) {
+ addr := addr + (dataWidth / 8).U
+ xferCnt := xferCnt - 1.U
+ }
+
+ // Don't stall if we receive same cycle d_valid
+ when(io.bus.d.valid) {
+ xferValid := true.B
+
+ when(xferCnt === 1.U) {
+ state := sIdle
+ done := true.B
+ }.otherwise {
+ valid := true.B
+ state := sTransfer
+ }
+ }
+ }
+ }
+ is(sWait){
+ valid := false.B
+ xferValid := false.B
+ io.bus.d.ready := true.B
+ when(io.bus.d.valid) {
+ xferValid := true.B
+ when(xferCnt === 0.U) {
+ state := sIdle
+ done := true.B
+ }.otherwise {
+ valid := true.B
+ state := sTransfer
+ }
+ }
+ }
+ }
+}
diff --git a/hw/top_matcha/ip/dma/chisel/src/frontend/TLULWriter.scala b/hw/top_matcha/ip/dma/chisel/src/frontend/TLULWriter.scala
new file mode 100644
index 0000000..d025d94
--- /dev/null
+++ b/hw/top_matcha/ip/dma/chisel/src/frontend/TLULWriter.scala
@@ -0,0 +1,124 @@
+/*
+Copyright 2024 Google LLC
+
+http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS,
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
+
+SPDX-License-Identifier: Apache-2.0
+*/
+
+package DMAController.Frontend
+
+import DMAController.Bus._
+import DMAController.Worker.{XferDescBundle, WorkerCSRWrapper}
+import DMAController.CSR.CSR
+import chisel3._
+import chisel3.util._
+
+class TLULWriter(val addrWidth : Int, val dataWidth : Int) extends IOBus[TLULHost]{
+ val io = IO(new Bundle{
+ val bus = new TLULHost(addrWidth, dataWidth)
+ val dataIO = DeqIO(UInt(dataWidth.W))
+ val xfer = Flipped(new XferDescBundle(addrWidth))
+ })
+
+ val sIdle :: sTransfer :: sWait :: Nil = Enum(3)
+
+ val state = RegInit(sIdle)
+
+ val xferCnt = RegInit(0.U(addrWidth.W))
+ val addr = RegInit(0.U(addrWidth.W))
+ val addrValid = RegInit(false.B)
+ val valid = RegInit(false.B)
+
+ val done = WireInit(false.B)
+ val xferValid = WireInit(false.B)
+
+ io.bus.d <> TLULD.tieOff(addrWidth, dataWidth)
+
+ // Consumer of fifo
+ io.dataIO.ready := xferValid
+
+ io.bus.a.valid := valid
+ io.bus.a.data := io.dataIO.bits
+
+ // Note: Write port does not support TLUL partial put op
+ io.bus.a.opcode := TLOp.PutFull
+ io.bus.a.param := 0.U
+ io.bus.a.size := 2.U
+ io.bus.a.source := 0.U
+ io.bus.a.address := addr
+ io.bus.a.corrupt := 0.U
+ io.bus.a.mask := 0xF.U
+
+ io.xfer.done := done
+
+ switch(state){
+ is(sIdle){
+ valid := false.B
+ io.bus.d.ready := false.B
+ done := false.B
+ xferValid := false.B
+
+ // Sync valid signals from the data queue and
+ // address generator here.
+ when(io.xfer.valid) {
+ addrValid := true.B
+ }
+
+ when(io.dataIO.valid && addrValid) {
+ valid := true.B
+ state := sTransfer
+ xferCnt := io.xfer.length
+ addr := io.xfer.address
+ addrValid := false.B
+ }
+ }
+ is(sTransfer){
+ io.bus.d.ready := true.B
+ xferValid := false.B
+ when(io.bus.a.ready) {
+ valid := false.B
+ state := sWait
+
+ when(xferCnt =/= 0.U) {
+ addr := addr + (dataWidth / 8).U
+ xferCnt := xferCnt - 1.U
+ }
+
+ // Don't stall if we receive same cycle d_valid
+ when(io.bus.d.valid) {
+ xferValid := true.B
+
+ when(xferCnt === 1.U) {
+ state := sIdle
+ done := true.B
+ }.otherwise {
+ valid := true.B
+ state := sTransfer
+ }
+ }
+ }
+ }
+ is(sWait){
+ valid := false.B
+ xferValid := false.B
+ io.bus.d.ready := true.B
+ when(io.bus.d.valid) {
+ xferValid := true.B
+ when(xferCnt === 0.U) {
+ state := sIdle
+ done := true.B
+ }.otherwise {
+ valid := true.B
+ state := sTransfer
+ }
+ }
+ }
+ }
+}
diff --git a/hw/top_matcha/ip/dma/chisel/src/worker/AddressGenerator.scala b/hw/top_matcha/ip/dma/chisel/src/worker/AddressGenerator.scala
new file mode 100644
index 0000000..a439c1c
--- /dev/null
+++ b/hw/top_matcha/ip/dma/chisel/src/worker/AddressGenerator.scala
@@ -0,0 +1,88 @@
+/*
+Copyright (C) 2019-2022 Antmicro
+
+http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS,
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
+
+SPDX-License-Identifier: Apache-2.0
+*/
+
+package DMAController.Worker
+
+import chisel3._
+import chisel3.util._
+
+class AddressGenerator(val addrWidth : Int, val dataWidth : Int) extends Module{
+ val io = IO(new Bundle{
+ val ctl = new AddressGeneratorCtlBundle(addrWidth)
+ val xfer = new XferDescBundle(addrWidth)
+ })
+
+ val sIdle :: sLine :: sLineWait :: sDone :: Nil = Enum(4)
+
+ val state = RegInit(sIdle)
+
+ val lineCount = RegInit(0.U(addrWidth.W))
+ val lineGap = RegInit(0.U(addrWidth.W))
+
+ val address_o = RegInit(0.U(addrWidth.W))
+ val address_i = RegInit(0.U(addrWidth.W))
+ val length_o = RegInit(0.U(addrWidth.W))
+ val length_i = RegInit(0.U(addrWidth.W))
+ val valid = RegInit(false.B)
+ val first = RegInit(false.B)
+ val busy = RegInit(false.B)
+
+ io.xfer.address := address_o
+ io.xfer.length := length_o
+ io.xfer.valid := valid
+ io.xfer.first := first
+ io.ctl.busy := busy
+
+ when(state === sIdle){
+ busy := false.B
+ }.otherwise{
+ busy := true.B
+ }
+
+ switch(state){
+ is(sIdle){
+ when(io.ctl.start){
+ state := sLine
+
+ address_i := io.ctl.startAddress
+ length_i := io.ctl.lineLength
+ lineCount := io.ctl.lineCount
+ lineGap := io.ctl.lineGap
+ first := true.B
+ }
+ }
+ is(sLine){
+
+ valid := true.B
+ address_o := address_i
+ length_o := length_i
+ address_i := address_i + (length_i * (dataWidth / 8).U) + (lineGap * (dataWidth / 8).U)
+
+ lineCount := lineCount - 1.U
+ state := sLineWait
+ }
+ is(sLineWait){
+ valid := false.B
+ first := false.B
+ when(io.xfer.done){
+ when(lineCount > 0.U){
+ state := sLine
+ }.otherwise{
+ state := sIdle
+ }
+ }
+ }
+ }
+
+}
diff --git a/hw/top_matcha/ip/dma/chisel/src/worker/AddressGeneratorCtlBundle.scala b/hw/top_matcha/ip/dma/chisel/src/worker/AddressGeneratorCtlBundle.scala
new file mode 100644
index 0000000..035623f
--- /dev/null
+++ b/hw/top_matcha/ip/dma/chisel/src/worker/AddressGeneratorCtlBundle.scala
@@ -0,0 +1,26 @@
+/*
+Copyright (C) 2019-2022 Antmicro
+
+http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS,
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
+
+SPDX-License-Identifier: Apache-2.0
+*/
+
+package DMAController.Worker
+
+import chisel3._
+
+class AddressGeneratorCtlBundle(val addrWidth : Int) extends Bundle{
+ val start = Input(Bool())
+ val busy = Output(Bool())
+ val startAddress = Input(UInt(addrWidth.W))
+ val lineLength = Input(UInt(addrWidth.W))
+ val lineCount = Input(UInt(addrWidth.W))
+ val lineGap = Input(UInt(addrWidth.W))
+}
diff --git a/hw/top_matcha/ip/dma/chisel/src/worker/InterruptBundle.scala b/hw/top_matcha/ip/dma/chisel/src/worker/InterruptBundle.scala
new file mode 100644
index 0000000..96aeac2
--- /dev/null
+++ b/hw/top_matcha/ip/dma/chisel/src/worker/InterruptBundle.scala
@@ -0,0 +1,22 @@
+/*
+Copyright (C) 2019-2022 Antmicro
+
+http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS,
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
+
+SPDX-License-Identifier: Apache-2.0
+*/
+
+package DMAController.Worker
+
+import chisel3._
+
+class InterruptBundle extends Bundle{
+ val readerDone = Output(Bool())
+ val writerDone = Output(Bool())
+}
diff --git a/hw/top_matcha/ip/dma/chisel/src/worker/InterruptController.scala b/hw/top_matcha/ip/dma/chisel/src/worker/InterruptController.scala
new file mode 100644
index 0000000..054b06e
--- /dev/null
+++ b/hw/top_matcha/ip/dma/chisel/src/worker/InterruptController.scala
@@ -0,0 +1,64 @@
+/*
+Copyright (C) 2019-2022 Antmicro
+
+http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS,
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
+
+SPDX-License-Identifier: Apache-2.0
+*/
+
+package DMAController.Worker
+
+import DMAController.CSR.{CSRRegBundle, SetCSR, SimpleCSR}
+import chisel3._
+import chisel3.util.Cat
+
+class InterruptController extends Module{
+ val io = IO(new Bundle {
+ val irq = new InterruptBundle
+ val readBusy = Input(Bool())
+ val writeBusy = Input(Bool())
+ val imr = Flipped(new CSRRegBundle())
+ val isr = Flipped(new CSRRegBundle())
+ })
+
+ val mask = WireInit(SimpleCSR(io.imr))
+
+ val readBusy = RegNext(io.readBusy)
+ val readBusyOld = RegNext(readBusy)
+
+ val writeBusy = RegNext(io.writeBusy)
+ val writeBusyOld = RegNext(writeBusy)
+
+ val writeBusyIrq = RegInit(false.B)
+ val readBusyIrq = RegInit(false.B)
+
+ writeBusyIrq := writeBusyOld && !writeBusy && mask(0)
+ readBusyIrq := readBusyOld && !readBusy && mask(1)
+
+ val irq = WireInit(Cat(readBusyIrq, writeBusyIrq))
+
+ val isr = WireInit(SetCSR(irq, io.isr))
+
+ io.irq.writerDone := isr(0)
+ io.irq.readerDone := isr(1)
+}
+
+object InterruptController {
+ def apply(readBusy : Bool, writeBusy : Bool, imr : CSRRegBundle, isr : CSRRegBundle): InterruptBundle = {
+ val irqc = Module(new InterruptController)
+
+ irqc.io.readBusy := readBusy
+ irqc.io.writeBusy := writeBusy
+
+ irqc.io.imr <> imr
+ irqc.io.isr <> isr
+
+ irqc.io.irq
+ }
+}
\ No newline at end of file
diff --git a/hw/top_matcha/ip/dma/chisel/src/worker/SyncBundle.scala b/hw/top_matcha/ip/dma/chisel/src/worker/SyncBundle.scala
new file mode 100644
index 0000000..69612a0
--- /dev/null
+++ b/hw/top_matcha/ip/dma/chisel/src/worker/SyncBundle.scala
@@ -0,0 +1,22 @@
+/*
+Copyright (C) 2019-2022 Antmicro
+
+http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS,
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
+
+SPDX-License-Identifier: Apache-2.0
+*/
+
+package DMAController.Worker
+
+import chisel3._
+
+class SyncBundle extends Bundle{
+ val readerSync = Input(Bool())
+ val writerSync = Input(Bool())
+}
diff --git a/hw/top_matcha/ip/dma/chisel/src/worker/TransferSplitter.scala b/hw/top_matcha/ip/dma/chisel/src/worker/TransferSplitter.scala
new file mode 100644
index 0000000..0c68ae1
--- /dev/null
+++ b/hw/top_matcha/ip/dma/chisel/src/worker/TransferSplitter.scala
@@ -0,0 +1,125 @@
+/*
+Copyright (C) 2019-2022 Antmicro
+
+http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS,
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
+
+SPDX-License-Identifier: Apache-2.0
+*/
+
+package DMAController.Worker
+
+import chisel3._
+import chisel3.util._
+
+class TransferSplitter(val addressWidth : Int, val dataWidth : Int,
+ val maxLength : Int, val canCrossBarrier : Boolean) extends Module{
+ val io = IO(new Bundle{
+ val xferIn = Flipped(new XferDescBundle(addressWidth))
+ val xferOut = new XferDescBundle(addressWidth)
+ })
+
+ if(maxLength != 0) {
+ val sIdle :: sSplit :: sSplitWait :: Nil = Enum(3)
+
+ val dataBytes: Int = dataWidth / 8
+
+ val barrierBytes: Int = 4096
+
+ val address_i = RegInit(0.U(addressWidth.W))
+ val length_i = RegInit(0.U(addressWidth.W))
+
+ val address_o = RegInit(0.U(addressWidth.W))
+ val length_o = RegInit(0.U(addressWidth.W))
+
+ val first_i = RegInit(false.B)
+ val first_o = RegInit(false.B)
+
+ val done = RegInit(false.B)
+ val valid = RegInit(false.B)
+
+ val state = RegInit(sIdle)
+
+ io.xferIn.done := done
+ io.xferOut.valid := valid
+
+ io.xferOut.first := first_o
+ io.xferOut.address := address_o
+ io.xferOut.length := length_o
+
+ switch(state) {
+ is(sIdle) {
+ done := false.B
+
+ when(io.xferIn.valid) {
+ address_i := io.xferIn.address
+ length_i := io.xferIn.length
+ first_i := io.xferIn.first
+ state := sSplit
+ }
+ }
+ is(sSplit) {
+ address_o := address_i
+ first_o := first_i
+ valid := true.B
+ state := sSplitWait
+
+ when(length_i > maxLength.U) {
+ if (canCrossBarrier) {
+ length_o := maxLength.U
+ length_i := length_i - maxLength.U
+ address_i := address_i + maxLength.U * dataBytes.U
+ } else {
+ val bytesToBarrier = barrierBytes.U - address_i % barrierBytes.U
+ when(bytesToBarrier < maxLength.U * dataBytes.U) {
+ length_o := bytesToBarrier / dataBytes.U
+ length_i := length_i - bytesToBarrier / dataBytes.U
+ address_i := address_i + bytesToBarrier
+ }.otherwise {
+ length_o := maxLength.U
+ length_i := length_i - maxLength.U
+ address_i := address_i + maxLength.U * dataBytes.U
+ }
+ }
+
+ }.otherwise {
+ if (canCrossBarrier) {
+ length_o := length_i
+ length_i := 0.U
+ address_i := address_i + length_i * dataBytes.U
+ } else {
+ val bytesToBarrier = barrierBytes.U - address_i % barrierBytes.U
+ when(bytesToBarrier < length_i * dataBytes.U) {
+ length_o := bytesToBarrier / dataBytes.U
+ length_i := length_i - bytesToBarrier / dataBytes.U
+ address_i := address_i + bytesToBarrier
+ }.otherwise {
+ length_o := length_i
+ length_i := 0.U
+ address_i := address_i + length_i * dataBytes.U
+ }
+ }
+ }
+ }
+ is(sSplitWait) {
+ valid := false.B
+ first_i := false.B
+ when(io.xferOut.done) {
+ when(length_i > 0.U) {
+ state := sSplit
+ }.otherwise {
+ state := sIdle
+ done := true.B
+ }
+ }
+ }
+ }
+ } else {
+ io.xferOut <> io.xferIn
+ }
+}
diff --git a/hw/top_matcha/ip/dma/chisel/src/worker/WorkerCSRWrapper.scala b/hw/top_matcha/ip/dma/chisel/src/worker/WorkerCSRWrapper.scala
new file mode 100644
index 0000000..8c05120
--- /dev/null
+++ b/hw/top_matcha/ip/dma/chisel/src/worker/WorkerCSRWrapper.scala
@@ -0,0 +1,96 @@
+/*
+Copyright 2024 Google LLC
+Copyright (C) 2019-2022 Antmicro
+
+http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS,
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
+
+SPDX-License-Identifier: Apache-2.0
+*/
+
+package DMAController.Worker
+
+import DMAController.CSR._
+import DMAController.DMAConfig._
+import chisel3._
+import chisel3.util.Cat
+
+class WorkerCSRWrapper(addrWidth : Int, readerDataWidth : Int, writerDataWidth : Int, readerMaxBurst : Int,
+ writerMaxBurst : Int, reader4KBarrier : Boolean, writer4KBarrier : Boolean) extends Module{
+ val io = IO(new Bundle{
+ val csr: Vec[CSRRegBundle] = Vec(DMAConfig.controlRegCount, Flipped(new CSRRegBundle()))
+ val irq = new InterruptBundle
+ val sync = new SyncBundle
+ val xferRead = new XferDescBundle(addrWidth)
+ val xferWrite = new XferDescBundle(addrWidth)
+ })
+
+ val addressGeneratorRead = Module(new AddressGenerator(addrWidth, readerDataWidth))
+ val transferSplitterRead = Module(new TransferSplitter(addrWidth, readerDataWidth, readerMaxBurst, reader4KBarrier))
+
+ val addressGeneratorWrite = Module(new AddressGenerator(addrWidth, writerDataWidth))
+ val transferSplitterWrite = Module(new TransferSplitter(addrWidth, writerDataWidth, writerMaxBurst, writer4KBarrier))
+
+ val status = RegNext(Cat(addressGeneratorRead.io.ctl.busy, addressGeneratorWrite.io.ctl.busy))
+
+ val readerSync = RegNext(io.sync.readerSync)
+ val readerSyncOld = RegNext(readerSync)
+
+ val writerSync = RegNext(io.sync.writerSync)
+ val writerSyncOld = RegNext(writerSync)
+
+ val readerStart = RegInit(false.B)
+ val writerStart = RegInit(false.B)
+
+ val control = Wire(UInt())
+ val clear = Wire(UInt())
+
+ // TODO(hoangm): Consider versioning for future revisions of DMA.
+ val version = RegInit(0.U)
+ // 0x555 value does not conflict with prior bus configs.
+ val (in, csr, out) = (5,5,5)
+ val config = RegInit((in << 8 | csr << 4 | out).U(addrWidth.W))
+
+ control := ClearCSR(clear, io.csr(0))
+
+ StatusCSR(status, io.csr(1))
+
+ io.irq <> InterruptController(addressGeneratorRead.io.ctl.busy, addressGeneratorWrite.io.ctl.busy,
+ io.csr(2), io.csr(3))
+
+ clear := Cat(readerStart, writerStart) & ~Cat(control(5), control(4))
+
+ readerStart := ((!readerSyncOld && readerSync) || control(3)) && control(1)
+ writerStart := ((!writerSyncOld && writerSync) || control(2)) && control(0)
+
+ addressGeneratorRead.io.ctl.start := readerStart
+ addressGeneratorRead.io.ctl.startAddress := SimpleCSR(io.csr(4))
+ addressGeneratorRead.io.ctl.lineLength := SimpleCSR(io.csr(5))
+ addressGeneratorRead.io.ctl.lineCount := SimpleCSR(io.csr(6))
+ addressGeneratorRead.io.ctl.lineGap := SimpleCSR(io.csr(7))
+
+ addressGeneratorWrite.io.ctl.start := writerStart
+ addressGeneratorWrite.io.ctl.startAddress := SimpleCSR(io.csr(8))
+ addressGeneratorWrite.io.ctl.lineLength := SimpleCSR(io.csr(9))
+ addressGeneratorWrite.io.ctl.lineCount := SimpleCSR(io.csr(10))
+ addressGeneratorWrite.io.ctl.lineGap := SimpleCSR(io.csr(11))
+
+ StatusCSR(version, io.csr(12))
+ StatusCSR(config, io.csr(13))
+
+ for(i <- 14 until DMAConfig.controlRegCount){
+ SimpleCSR(io.csr(i))
+ }
+
+ transferSplitterRead.io.xferIn <> addressGeneratorRead.io.xfer
+ io.xferRead <> transferSplitterRead.io.xferOut
+
+ transferSplitterWrite.io.xferIn <> addressGeneratorWrite.io.xfer
+ io.xferWrite <> transferSplitterWrite.io.xferOut
+
+}
diff --git a/hw/top_matcha/ip/dma/chisel/src/worker/XferDescBundle.scala b/hw/top_matcha/ip/dma/chisel/src/worker/XferDescBundle.scala
new file mode 100644
index 0000000..1e2762f
--- /dev/null
+++ b/hw/top_matcha/ip/dma/chisel/src/worker/XferDescBundle.scala
@@ -0,0 +1,25 @@
+/*
+Copyright (C) 2019-2022 Antmicro
+
+http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS,
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
+
+SPDX-License-Identifier: Apache-2.0
+*/
+
+package DMAController.Worker
+
+import chisel3._
+
+class XferDescBundle(val addrWidth : Int) extends Bundle{
+ val done = Input(Bool())
+ val address = Output(UInt(addrWidth.W))
+ val length = Output(UInt(addrWidth.W))
+ val valid = Output(Bool())
+ val first = Output(Bool())
+}
diff --git a/hw/top_matcha/ip/dma/dma.core b/hw/top_matcha/ip/dma/dma.core
index 27ab4b6..a293642 100644
--- a/hw/top_matcha/ip/dma/dma.core
+++ b/hw/top_matcha/ip/dma/dma.core
@@ -9,10 +9,10 @@
depend:
- lowrisc:ip:tlul
- lowrisc:prim:all
+ - google:ip:fastvdma
files:
- rtl/dma.sv
- - rtl/DMATopTL_TL_TL.v
file_type: systemVerilogSource
files_verilator_waiver:
diff --git a/hw/top_matcha/ip/dma/rtl/DMATopTL_TL_TL.v b/hw/top_matcha/ip/dma/rtl/DMATopTL_TL_TL.v
deleted file mode 100644
index ee09b09..0000000
--- a/hw/top_matcha/ip/dma/rtl/DMATopTL_TL_TL.v
+++ /dev/null
@@ -1,3188 +0,0 @@
-// Copyright 2023 Google LLC
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-// http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-// SHA: f52a857f6167581412199b2fde43a4cb307cdada
-module TLULCSRTL_TL_TL( // @[:@3.2]
- input clock, // @[:@4.4]
- input reset, // @[:@5.4]
- input [2:0] io_ctl_a_opcode, // @[:@6.4]
- input [1:0] io_ctl_a_size, // @[:@6.4]
- input [9:0] io_ctl_a_source, // @[:@6.4]
- input [31:0] io_ctl_a_address, // @[:@6.4]
- input [31:0] io_ctl_a_data, // @[:@6.4]
- input io_ctl_a_valid, // @[:@6.4]
- output io_ctl_a_ready, // @[:@6.4]
- output [2:0] io_ctl_d_opcode, // @[:@6.4]
- output [1:0] io_ctl_d_size, // @[:@6.4]
- output [9:0] io_ctl_d_source, // @[:@6.4]
- output [31:0] io_ctl_d_data, // @[:@6.4]
- output io_ctl_d_valid, // @[:@6.4]
- input io_ctl_d_ready, // @[:@6.4]
- output [3:0] io_bus_addr, // @[:@6.4]
- output [31:0] io_bus_dataOut, // @[:@6.4]
- input [31:0] io_bus_dataIn, // @[:@6.4]
- output io_bus_write, // @[:@6.4]
- output io_bus_read // @[:@6.4]
-);
- reg [1:0] state; // @[TLULCSR.scala 31:22:@8.4]
- reg [31:0] _RAND_0;
- reg [31:0] addr; // @[TLULCSR.scala 36:21:@13.4]
- reg [31:0] _RAND_1;
- reg [31:0] wdata; // @[TLULCSR.scala 37:22:@14.4]
- reg [31:0] _RAND_2;
- reg [9:0] sourceId; // @[TLULCSR.scala 38:25:@15.4]
- reg [31:0] _RAND_3;
- reg [1:0] size; // @[TLULCSR.scala 39:21:@16.4]
- reg [31:0] _RAND_4;
- wire _T_130; // @[Conditional.scala 37:30:@54.4]
- wire [3:0] _T_134; // @[TLULCSR.scala 68:31:@59.6]
- wire _T_138; // @[TLULCSR.scala 73:30:@64.8]
- wire _T_140; // @[TLULCSR.scala 76:36:@71.10]
- wire _T_141; // @[TLULCSR.scala 77:36:@72.10]
- wire _T_142; // @[TLULCSR.scala 76:53:@73.10]
- wire [3:0] _GEN_0; // @[TLULCSR.scala 77:57:@74.10]
- wire [31:0] _GEN_1; // @[TLULCSR.scala 77:57:@74.10]
- wire [1:0] _GEN_2; // @[TLULCSR.scala 77:57:@74.10]
- wire [1:0] _GEN_3; // @[TLULCSR.scala 73:44:@65.8]
- wire [3:0] _GEN_4; // @[TLULCSR.scala 73:44:@65.8]
- wire [31:0] _GEN_5; // @[TLULCSR.scala 73:44:@65.8]
- wire [1:0] _GEN_6; // @[TLULCSR.scala 69:28:@61.6]
- wire [9:0] _GEN_7; // @[TLULCSR.scala 69:28:@61.6]
- wire [1:0] _GEN_8; // @[TLULCSR.scala 69:28:@61.6]
- wire [3:0] _GEN_9; // @[TLULCSR.scala 69:28:@61.6]
- wire [31:0] _GEN_10; // @[TLULCSR.scala 69:28:@61.6]
- wire _T_144; // @[Conditional.scala 37:30:@83.6]
- wire [1:0] _GEN_11; // @[TLULCSR.scala 88:28:@88.8]
- wire _T_146; // @[Conditional.scala 37:30:@93.8]
- wire [1:0] _GEN_13; // @[TLULCSR.scala 96:28:@98.10]
- wire [1:0] _GEN_14; // @[Conditional.scala 39:67:@94.8]
- wire _GEN_17; // @[Conditional.scala 39:67:@94.8]
- wire [1:0] _GEN_18; // @[Conditional.scala 39:67:@84.6]
- wire _GEN_20; // @[Conditional.scala 39:67:@84.6]
- wire _GEN_21; // @[Conditional.scala 39:67:@84.6]
- wire [31:0] _GEN_25; // @[Conditional.scala 40:58:@55.4]
- wire [1:0] _GEN_26; // @[Conditional.scala 40:58:@55.4]
- wire [9:0] _GEN_27; // @[Conditional.scala 40:58:@55.4]
- wire [1:0] _GEN_28; // @[Conditional.scala 40:58:@55.4]
- wire [31:0] _GEN_29; // @[Conditional.scala 40:58:@55.4]
- wire rsp; // @[Conditional.scala 40:58:@55.4]
- assign _T_130 = 2'h0 == state; // @[Conditional.scala 37:30:@54.4]
- assign _T_134 = io_ctl_a_address[5:2]; // @[TLULCSR.scala 68:31:@59.6]
- assign _T_138 = io_ctl_a_opcode == 3'h4; // @[TLULCSR.scala 73:30:@64.8]
- assign _T_140 = io_ctl_a_opcode == 3'h0; // @[TLULCSR.scala 76:36:@71.10]
- assign _T_141 = io_ctl_a_opcode == 3'h1; // @[TLULCSR.scala 77:36:@72.10]
- assign _T_142 = _T_140 | _T_141; // @[TLULCSR.scala 76:53:@73.10]
- assign _GEN_0 = _T_142 ? _T_134 : _T_134; // @[TLULCSR.scala 77:57:@74.10]
- assign _GEN_1 = _T_142 ? io_ctl_a_data : wdata; // @[TLULCSR.scala 77:57:@74.10]
- assign _GEN_2 = _T_142 ? 2'h2 : state; // @[TLULCSR.scala 77:57:@74.10]
- assign _GEN_3 = _T_138 ? 2'h1 : _GEN_2; // @[TLULCSR.scala 73:44:@65.8]
- assign _GEN_4 = _T_138 ? _T_134 : _GEN_0; // @[TLULCSR.scala 73:44:@65.8]
- assign _GEN_5 = _T_138 ? wdata : _GEN_1; // @[TLULCSR.scala 73:44:@65.8]
- assign _GEN_6 = io_ctl_a_valid ? io_ctl_a_size : size; // @[TLULCSR.scala 69:28:@61.6]
- assign _GEN_7 = io_ctl_a_valid ? io_ctl_a_source : sourceId; // @[TLULCSR.scala 69:28:@61.6]
- assign _GEN_8 = io_ctl_a_valid ? _GEN_3 : state; // @[TLULCSR.scala 69:28:@61.6]
- assign _GEN_9 = io_ctl_a_valid ? _GEN_4 : _T_134; // @[TLULCSR.scala 69:28:@61.6]
- assign _GEN_10 = io_ctl_a_valid ? _GEN_5 : wdata; // @[TLULCSR.scala 69:28:@61.6]
- assign _T_144 = 2'h1 == state; // @[Conditional.scala 37:30:@83.6]
- assign _GEN_11 = io_ctl_d_ready ? 2'h0 : 2'h1; // @[TLULCSR.scala 88:28:@88.8]
- assign _T_146 = 2'h2 == state; // @[Conditional.scala 37:30:@93.8]
- assign _GEN_13 = io_ctl_d_ready ? 2'h0 : 2'h2; // @[TLULCSR.scala 96:28:@98.10]
- assign _GEN_14 = _T_146 ? _GEN_13 : state; // @[Conditional.scala 39:67:@94.8]
- assign _GEN_17 = _T_146 ? io_ctl_d_ready : 1'h0; // @[Conditional.scala 39:67:@94.8]
- assign _GEN_18 = _T_144 ? _GEN_11 : _GEN_14; // @[Conditional.scala 39:67:@84.6]
- assign _GEN_20 = _T_144 ? 1'h1 : _T_146; // @[Conditional.scala 39:67:@84.6]
- assign _GEN_21 = _T_144 ? 1'h0 : _GEN_17; // @[Conditional.scala 39:67:@84.6]
- assign _GEN_25 = _T_130 ? {{28'd0}, _GEN_9} : addr; // @[Conditional.scala 40:58:@55.4]
- assign _GEN_26 = _T_130 ? _GEN_6 : size; // @[Conditional.scala 40:58:@55.4]
- assign _GEN_27 = _T_130 ? _GEN_7 : sourceId; // @[Conditional.scala 40:58:@55.4]
- assign _GEN_28 = _T_130 ? _GEN_8 : _GEN_18; // @[Conditional.scala 40:58:@55.4]
- assign _GEN_29 = _T_130 ? _GEN_10 : wdata; // @[Conditional.scala 40:58:@55.4]
- assign rsp = _T_130 ? 1'h0 : _T_144; // @[Conditional.scala 40:58:@55.4]
- assign io_ctl_a_ready = 2'h0 == state; // @[TLULCSR.scala 43:12:@30.4 TLULCSR.scala 65:22:@56.6]
- assign io_ctl_d_opcode = {{2'd0}, rsp}; // @[TLULCSR.scala 47:19:@41.4]
- assign io_ctl_d_size = size; // @[TLULCSR.scala 50:17:@44.4]
- assign io_ctl_d_source = sourceId; // @[TLULCSR.scala 53:19:@47.4]
- assign io_ctl_d_data = io_bus_dataIn; // @[TLULCSR.scala 46:17:@40.4]
- assign io_ctl_d_valid = _T_130 ? 1'h0 : _GEN_20; // @[TLULCSR.scala 48:18:@42.4]
- assign io_bus_addr = addr[3:0]; // @[TLULCSR.scala 57:15:@49.4]
- assign io_bus_dataOut = wdata; // @[TLULCSR.scala 58:18:@50.4]
- assign io_bus_write = _T_130 ? 1'h0 : _GEN_21; // @[TLULCSR.scala 60:16:@51.4]
- assign io_bus_read = state == 2'h1; // @[TLULCSR.scala 61:15:@53.4]
-`ifdef RANDOMIZE_GARBAGE_ASSIGN
-`define RANDOMIZE
-`endif
-`ifdef RANDOMIZE_INVALID_ASSIGN
-`define RANDOMIZE
-`endif
-`ifdef RANDOMIZE_REG_INIT
-`define RANDOMIZE
-`endif
-`ifdef RANDOMIZE_MEM_INIT
-`define RANDOMIZE
-`endif
-`ifndef RANDOM
-`define RANDOM $random
-`endif
-`ifdef RANDOMIZE
- integer initvar;
- initial begin
- `ifdef INIT_RANDOM
- `INIT_RANDOM
- `endif
- `ifndef VERILATOR
- #0.002 begin end
- `endif
- `ifdef RANDOMIZE_REG_INIT
- _RAND_0 = {1{`RANDOM}};
- state = _RAND_0[1:0];
- `endif // RANDOMIZE_REG_INIT
- `ifdef RANDOMIZE_REG_INIT
- _RAND_1 = {1{`RANDOM}};
- addr = _RAND_1[31:0];
- `endif // RANDOMIZE_REG_INIT
- `ifdef RANDOMIZE_REG_INIT
- _RAND_2 = {1{`RANDOM}};
- wdata = _RAND_2[31:0];
- `endif // RANDOMIZE_REG_INIT
- `ifdef RANDOMIZE_REG_INIT
- _RAND_3 = {1{`RANDOM}};
- sourceId = _RAND_3[9:0];
- `endif // RANDOMIZE_REG_INIT
- `ifdef RANDOMIZE_REG_INIT
- _RAND_4 = {1{`RANDOM}};
- size = _RAND_4[1:0];
- `endif // RANDOMIZE_REG_INIT
- end
-`endif // RANDOMIZE
- always @(posedge clock) begin
- if (reset) begin
- state <= 2'h0;
- end else begin
- if (_T_130) begin
- if (io_ctl_a_valid) begin
- if (_T_138) begin
- state <= 2'h1;
- end else begin
- if (_T_142) begin
- state <= 2'h2;
- end
- end
- end
- end else begin
- if (_T_144) begin
- if (io_ctl_d_ready) begin
- state <= 2'h0;
- end else begin
- state <= 2'h1;
- end
- end else begin
- if (_T_146) begin
- if (io_ctl_d_ready) begin
- state <= 2'h0;
- end else begin
- state <= 2'h2;
- end
- end
- end
- end
- end
- if (reset) begin
- addr <= 32'h0;
- end else begin
- if (_T_130) begin
- addr <= {{28'd0}, _GEN_9};
- end
- end
- if (reset) begin
- wdata <= 32'h0;
- end else begin
- if (_T_130) begin
- if (io_ctl_a_valid) begin
- if (!(_T_138)) begin
- if (_T_142) begin
- wdata <= io_ctl_a_data;
- end
- end
- end
- end
- end
- if (reset) begin
- sourceId <= 10'h0;
- end else begin
- if (_T_130) begin
- if (io_ctl_a_valid) begin
- sourceId <= io_ctl_a_source;
- end
- end
- end
- if (reset) begin
- size <= 2'h0;
- end else begin
- if (_T_130) begin
- if (io_ctl_a_valid) begin
- size <= io_ctl_a_size;
- end
- end
- end
- end
-endmodule
-module TLULReaderTL_TL_TL( // @[:@104.2]
- input clock, // @[:@105.4]
- input reset, // @[:@106.4]
- output [31:0] io_bus_a_address, // @[:@107.4]
- output io_bus_a_valid, // @[:@107.4]
- input io_bus_a_ready, // @[:@107.4]
- input [31:0] io_bus_d_data, // @[:@107.4]
- input io_bus_d_valid, // @[:@107.4]
- output io_bus_d_ready, // @[:@107.4]
- input io_dataIO_ready, // @[:@107.4]
- output io_dataIO_valid, // @[:@107.4]
- output [31:0] io_dataIO_bits, // @[:@107.4]
- output io_xfer_done, // @[:@107.4]
- input [31:0] io_xfer_address, // @[:@107.4]
- input [31:0] io_xfer_length, // @[:@107.4]
- input io_xfer_valid // @[:@107.4]
-);
- reg [1:0] state; // @[TLULReader.scala 32:22:@109.4]
- reg [31:0] _RAND_0;
- reg [31:0] xferCnt; // @[TLULReader.scala 34:24:@110.4]
- reg [31:0] _RAND_1;
- reg [31:0] addr; // @[TLULReader.scala 35:21:@111.4]
- reg [31:0] _RAND_2;
- reg valid; // @[TLULReader.scala 36:22:@112.4]
- reg [31:0] _RAND_3;
- wire xfer; // @[TLULReader.scala 40:39:@117.4]
- wire _T_146; // @[Conditional.scala 37:30:@153.4]
- wire [1:0] _GEN_1; // @[TLULReader.scala 67:18:@159.6]
- wire [31:0] _GEN_2; // @[TLULReader.scala 67:18:@159.6]
- wire [31:0] _GEN_3; // @[TLULReader.scala 67:18:@159.6]
- wire _T_152; // @[Conditional.scala 37:30:@167.6]
- wire _T_157; // @[TLULReader.scala 81:22:@174.10]
- wire [32:0] _T_159; // @[TLULReader.scala 82:24:@176.12]
- wire [31:0] _T_160; // @[TLULReader.scala 82:24:@177.12]
- wire [32:0] _T_162; // @[TLULReader.scala 83:30:@179.12]
- wire [32:0] _T_163; // @[TLULReader.scala 83:30:@180.12]
- wire [31:0] _T_164; // @[TLULReader.scala 83:30:@181.12]
- wire [31:0] _GEN_4; // @[TLULReader.scala 81:31:@175.10]
- wire [31:0] _GEN_5; // @[TLULReader.scala 81:31:@175.10]
- wire _T_167; // @[TLULReader.scala 90:24:@186.12]
- wire [1:0] _GEN_6; // @[TLULReader.scala 90:33:@187.12]
- wire _GEN_8; // @[TLULReader.scala 90:33:@187.12]
- wire [1:0] _GEN_10; // @[TLULReader.scala 87:30:@184.10]
- wire _GEN_11; // @[TLULReader.scala 87:30:@184.10]
- wire _GEN_12; // @[TLULReader.scala 87:30:@184.10]
- wire _GEN_13; // @[TLULReader.scala 77:28:@171.8]
- wire [1:0] _GEN_14; // @[TLULReader.scala 77:28:@171.8]
- wire [31:0] _GEN_15; // @[TLULReader.scala 77:28:@171.8]
- wire [31:0] _GEN_16; // @[TLULReader.scala 77:28:@171.8]
- wire _GEN_17; // @[TLULReader.scala 77:28:@171.8]
- wire _GEN_18; // @[TLULReader.scala 77:28:@171.8]
- wire _T_170; // @[Conditional.scala 37:30:@199.8]
- wire _T_176; // @[TLULReader.scala 106:22:@206.12]
- wire [1:0] _GEN_19; // @[TLULReader.scala 106:31:@207.12]
- wire _GEN_21; // @[TLULReader.scala 106:31:@207.12]
- wire [1:0] _GEN_22; // @[TLULReader.scala 104:28:@204.10]
- wire _GEN_23; // @[TLULReader.scala 104:28:@204.10]
- wire _GEN_24; // @[TLULReader.scala 104:28:@204.10]
- wire _GEN_25; // @[Conditional.scala 39:67:@200.8]
- wire _GEN_26; // @[Conditional.scala 39:67:@200.8]
- wire [1:0] _GEN_28; // @[Conditional.scala 39:67:@200.8]
- wire _GEN_29; // @[Conditional.scala 39:67:@200.8]
- wire _GEN_30; // @[Conditional.scala 39:67:@168.6]
- wire _GEN_31; // @[Conditional.scala 39:67:@168.6]
- wire _GEN_32; // @[Conditional.scala 39:67:@168.6]
- wire [1:0] _GEN_33; // @[Conditional.scala 39:67:@168.6]
- wire [31:0] _GEN_34; // @[Conditional.scala 39:67:@168.6]
- wire [31:0] _GEN_35; // @[Conditional.scala 39:67:@168.6]
- wire _GEN_36; // @[Conditional.scala 39:67:@168.6]
- wire _GEN_37; // @[Conditional.scala 40:58:@154.4]
- wire [1:0] _GEN_41; // @[Conditional.scala 40:58:@154.4]
- wire [31:0] _GEN_42; // @[Conditional.scala 40:58:@154.4]
- wire [31:0] _GEN_43; // @[Conditional.scala 40:58:@154.4]
- assign xfer = io_dataIO_ready & io_xfer_valid; // @[TLULReader.scala 40:39:@117.4]
- assign _T_146 = 2'h0 == state; // @[Conditional.scala 37:30:@153.4]
- assign _GEN_1 = xfer ? 2'h1 : state; // @[TLULReader.scala 67:18:@159.6]
- assign _GEN_2 = xfer ? io_xfer_length : xferCnt; // @[TLULReader.scala 67:18:@159.6]
- assign _GEN_3 = xfer ? io_xfer_address : addr; // @[TLULReader.scala 67:18:@159.6]
- assign _T_152 = 2'h1 == state; // @[Conditional.scala 37:30:@167.6]
- assign _T_157 = xferCnt != 32'h0; // @[TLULReader.scala 81:22:@174.10]
- assign _T_159 = addr + 32'h4; // @[TLULReader.scala 82:24:@176.12]
- assign _T_160 = addr + 32'h4; // @[TLULReader.scala 82:24:@177.12]
- assign _T_162 = xferCnt - 32'h1; // @[TLULReader.scala 83:30:@179.12]
- assign _T_163 = $unsigned(_T_162); // @[TLULReader.scala 83:30:@180.12]
- assign _T_164 = _T_163[31:0]; // @[TLULReader.scala 83:30:@181.12]
- assign _GEN_4 = _T_157 ? _T_160 : addr; // @[TLULReader.scala 81:31:@175.10]
- assign _GEN_5 = _T_157 ? _T_164 : xferCnt; // @[TLULReader.scala 81:31:@175.10]
- assign _T_167 = xferCnt == 32'h1; // @[TLULReader.scala 90:24:@186.12]
- assign _GEN_6 = _T_167 ? 2'h0 : 2'h1; // @[TLULReader.scala 90:33:@187.12]
- assign _GEN_8 = _T_167 ? 1'h0 : 1'h1; // @[TLULReader.scala 90:33:@187.12]
- assign _GEN_10 = io_bus_d_valid ? _GEN_6 : 2'h2; // @[TLULReader.scala 87:30:@184.10]
- assign _GEN_11 = io_bus_d_valid ? _T_167 : 1'h0; // @[TLULReader.scala 87:30:@184.10]
- assign _GEN_12 = io_bus_d_valid ? _GEN_8 : 1'h0; // @[TLULReader.scala 87:30:@184.10]
- assign _GEN_13 = io_bus_a_ready ? _GEN_12 : valid; // @[TLULReader.scala 77:28:@171.8]
- assign _GEN_14 = io_bus_a_ready ? _GEN_10 : state; // @[TLULReader.scala 77:28:@171.8]
- assign _GEN_15 = io_bus_a_ready ? _GEN_4 : addr; // @[TLULReader.scala 77:28:@171.8]
- assign _GEN_16 = io_bus_a_ready ? _GEN_5 : xferCnt; // @[TLULReader.scala 77:28:@171.8]
- assign _GEN_17 = io_bus_a_ready ? io_bus_d_valid : 1'h0; // @[TLULReader.scala 77:28:@171.8]
- assign _GEN_18 = io_bus_a_ready ? _GEN_11 : 1'h0; // @[TLULReader.scala 77:28:@171.8]
- assign _T_170 = 2'h2 == state; // @[Conditional.scala 37:30:@199.8]
- assign _T_176 = xferCnt == 32'h0; // @[TLULReader.scala 106:22:@206.12]
- assign _GEN_19 = _T_176 ? 2'h0 : 2'h1; // @[TLULReader.scala 106:31:@207.12]
- assign _GEN_21 = _T_176 ? 1'h0 : 1'h1; // @[TLULReader.scala 106:31:@207.12]
- assign _GEN_22 = io_bus_d_valid ? _GEN_19 : state; // @[TLULReader.scala 104:28:@204.10]
- assign _GEN_23 = io_bus_d_valid ? _T_176 : 1'h0; // @[TLULReader.scala 104:28:@204.10]
- assign _GEN_24 = io_bus_d_valid ? _GEN_21 : 1'h0; // @[TLULReader.scala 104:28:@204.10]
- assign _GEN_25 = _T_170 ? _GEN_24 : valid; // @[Conditional.scala 39:67:@200.8]
- assign _GEN_26 = _T_170 ? io_bus_d_valid : 1'h0; // @[Conditional.scala 39:67:@200.8]
- assign _GEN_28 = _T_170 ? _GEN_22 : state; // @[Conditional.scala 39:67:@200.8]
- assign _GEN_29 = _T_170 ? _GEN_23 : 1'h0; // @[Conditional.scala 39:67:@200.8]
- assign _GEN_30 = _T_152 ? 1'h1 : _T_170; // @[Conditional.scala 39:67:@168.6]
- assign _GEN_31 = _T_152 ? _GEN_17 : _GEN_26; // @[Conditional.scala 39:67:@168.6]
- assign _GEN_32 = _T_152 ? _GEN_13 : _GEN_25; // @[Conditional.scala 39:67:@168.6]
- assign _GEN_33 = _T_152 ? _GEN_14 : _GEN_28; // @[Conditional.scala 39:67:@168.6]
- assign _GEN_34 = _T_152 ? _GEN_15 : addr; // @[Conditional.scala 39:67:@168.6]
- assign _GEN_35 = _T_152 ? _GEN_16 : xferCnt; // @[Conditional.scala 39:67:@168.6]
- assign _GEN_36 = _T_152 ? _GEN_18 : _GEN_29; // @[Conditional.scala 39:67:@168.6]
- assign _GEN_37 = _T_146 ? xfer : _GEN_32; // @[Conditional.scala 40:58:@154.4]
- assign _GEN_41 = _T_146 ? _GEN_1 : _GEN_33; // @[Conditional.scala 40:58:@154.4]
- assign _GEN_42 = _T_146 ? _GEN_2 : _GEN_35; // @[Conditional.scala 40:58:@154.4]
- assign _GEN_43 = _T_146 ? _GEN_3 : _GEN_34; // @[Conditional.scala 40:58:@154.4]
- assign io_bus_a_address = addr; // @[TLULReader.scala 55:20:@149.4]
- assign io_bus_a_valid = valid; // @[TLULReader.scala 48:18:@143.4]
- assign io_bus_d_ready = _T_146 ? 1'h0 : _GEN_30; // @[TLULReader.scala 42:12:@131.4 TLULReader.scala 64:22:@156.6 TLULReader.scala 75:22:@169.8 TLULReader.scala 103:22:@203.10]
- assign io_dataIO_valid = _T_146 ? 1'h0 : _GEN_31; // @[TLULReader.scala 46:19:@142.4]
- assign io_dataIO_bits = io_bus_d_data; // @[TLULReader.scala 45:18:@141.4]
- assign io_xfer_done = _T_146 ? 1'h0 : _GEN_36; // @[TLULReader.scala 59:16:@152.4]
-`ifdef RANDOMIZE_GARBAGE_ASSIGN
-`define RANDOMIZE
-`endif
-`ifdef RANDOMIZE_INVALID_ASSIGN
-`define RANDOMIZE
-`endif
-`ifdef RANDOMIZE_REG_INIT
-`define RANDOMIZE
-`endif
-`ifdef RANDOMIZE_MEM_INIT
-`define RANDOMIZE
-`endif
-`ifndef RANDOM
-`define RANDOM $random
-`endif
-`ifdef RANDOMIZE
- integer initvar;
- initial begin
- `ifdef INIT_RANDOM
- `INIT_RANDOM
- `endif
- `ifndef VERILATOR
- #0.002 begin end
- `endif
- `ifdef RANDOMIZE_REG_INIT
- _RAND_0 = {1{`RANDOM}};
- state = _RAND_0[1:0];
- `endif // RANDOMIZE_REG_INIT
- `ifdef RANDOMIZE_REG_INIT
- _RAND_1 = {1{`RANDOM}};
- xferCnt = _RAND_1[31:0];
- `endif // RANDOMIZE_REG_INIT
- `ifdef RANDOMIZE_REG_INIT
- _RAND_2 = {1{`RANDOM}};
- addr = _RAND_2[31:0];
- `endif // RANDOMIZE_REG_INIT
- `ifdef RANDOMIZE_REG_INIT
- _RAND_3 = {1{`RANDOM}};
- valid = _RAND_3[0:0];
- `endif // RANDOMIZE_REG_INIT
- end
-`endif // RANDOMIZE
- always @(posedge clock) begin
- if (reset) begin
- state <= 2'h0;
- end else begin
- if (_T_146) begin
- if (xfer) begin
- state <= 2'h1;
- end
- end else begin
- if (_T_152) begin
- if (io_bus_a_ready) begin
- if (io_bus_d_valid) begin
- if (_T_167) begin
- state <= 2'h0;
- end else begin
- state <= 2'h1;
- end
- end else begin
- state <= 2'h2;
- end
- end
- end else begin
- if (_T_170) begin
- if (io_bus_d_valid) begin
- if (_T_176) begin
- state <= 2'h0;
- end else begin
- state <= 2'h1;
- end
- end
- end
- end
- end
- end
- if (reset) begin
- xferCnt <= 32'h0;
- end else begin
- if (_T_146) begin
- if (xfer) begin
- xferCnt <= io_xfer_length;
- end
- end else begin
- if (_T_152) begin
- if (io_bus_a_ready) begin
- if (_T_157) begin
- xferCnt <= _T_164;
- end
- end
- end
- end
- end
- if (reset) begin
- addr <= 32'h0;
- end else begin
- if (_T_146) begin
- if (xfer) begin
- addr <= io_xfer_address;
- end
- end else begin
- if (_T_152) begin
- if (io_bus_a_ready) begin
- if (_T_157) begin
- addr <= _T_160;
- end
- end
- end
- end
- end
- if (reset) begin
- valid <= 1'h0;
- end else begin
- if (_T_146) begin
- valid <= xfer;
- end else begin
- if (_T_152) begin
- if (io_bus_a_ready) begin
- if (io_bus_d_valid) begin
- if (_T_167) begin
- valid <= 1'h0;
- end else begin
- valid <= 1'h1;
- end
- end else begin
- valid <= 1'h0;
- end
- end
- end else begin
- if (_T_170) begin
- if (io_bus_d_valid) begin
- if (_T_176) begin
- valid <= 1'h0;
- end else begin
- valid <= 1'h1;
- end
- end else begin
- valid <= 1'h0;
- end
- end
- end
- end
- end
- end
-endmodule
-module TLULWriterTL_TL_TL( // @[:@218.2]
- input clock, // @[:@219.4]
- input reset, // @[:@220.4]
- output [31:0] io_bus_a_address, // @[:@221.4]
- output [31:0] io_bus_a_data, // @[:@221.4]
- output io_bus_a_valid, // @[:@221.4]
- input io_bus_a_ready, // @[:@221.4]
- input io_bus_d_valid, // @[:@221.4]
- output io_bus_d_ready, // @[:@221.4]
- output io_dataIO_ready, // @[:@221.4]
- input io_dataIO_valid, // @[:@221.4]
- input [31:0] io_dataIO_bits, // @[:@221.4]
- output io_xfer_done, // @[:@221.4]
- input [31:0] io_xfer_address, // @[:@221.4]
- input [31:0] io_xfer_length, // @[:@221.4]
- input io_xfer_valid // @[:@221.4]
-);
- reg [1:0] state; // @[TLULWriter.scala 32:22:@223.4]
- reg [31:0] _RAND_0;
- reg [31:0] xferCnt; // @[TLULWriter.scala 34:24:@224.4]
- reg [31:0] _RAND_1;
- reg [31:0] addr; // @[TLULWriter.scala 35:21:@225.4]
- reg [31:0] _RAND_2;
- reg addrValid; // @[TLULWriter.scala 36:26:@226.4]
- reg [31:0] _RAND_3;
- reg valid; // @[TLULWriter.scala 37:22:@227.4]
- reg [31:0] _RAND_4;
- wire _T_151; // @[Conditional.scala 37:30:@264.4]
- wire _GEN_0; // @[TLULWriter.scala 70:27:@270.6]
- wire _T_157; // @[TLULWriter.scala 74:28:@273.6]
- wire [1:0] _GEN_2; // @[TLULWriter.scala 74:42:@274.6]
- wire [31:0] _GEN_3; // @[TLULWriter.scala 74:42:@274.6]
- wire [31:0] _GEN_4; // @[TLULWriter.scala 74:42:@274.6]
- wire _GEN_5; // @[TLULWriter.scala 74:42:@274.6]
- wire _T_160; // @[Conditional.scala 37:30:@283.6]
- wire _T_165; // @[TLULWriter.scala 89:22:@290.10]
- wire [32:0] _T_167; // @[TLULWriter.scala 90:24:@292.12]
- wire [31:0] _T_168; // @[TLULWriter.scala 90:24:@293.12]
- wire [32:0] _T_170; // @[TLULWriter.scala 91:30:@295.12]
- wire [32:0] _T_171; // @[TLULWriter.scala 91:30:@296.12]
- wire [31:0] _T_172; // @[TLULWriter.scala 91:30:@297.12]
- wire [31:0] _GEN_6; // @[TLULWriter.scala 89:31:@291.10]
- wire [31:0] _GEN_7; // @[TLULWriter.scala 89:31:@291.10]
- wire _T_175; // @[TLULWriter.scala 98:24:@302.12]
- wire [1:0] _GEN_8; // @[TLULWriter.scala 98:33:@303.12]
- wire _GEN_10; // @[TLULWriter.scala 98:33:@303.12]
- wire [1:0] _GEN_12; // @[TLULWriter.scala 95:30:@300.10]
- wire _GEN_13; // @[TLULWriter.scala 95:30:@300.10]
- wire _GEN_14; // @[TLULWriter.scala 95:30:@300.10]
- wire _GEN_15; // @[TLULWriter.scala 85:28:@287.8]
- wire [1:0] _GEN_16; // @[TLULWriter.scala 85:28:@287.8]
- wire [31:0] _GEN_17; // @[TLULWriter.scala 85:28:@287.8]
- wire [31:0] _GEN_18; // @[TLULWriter.scala 85:28:@287.8]
- wire _GEN_19; // @[TLULWriter.scala 85:28:@287.8]
- wire _GEN_20; // @[TLULWriter.scala 85:28:@287.8]
- wire _T_178; // @[Conditional.scala 37:30:@315.8]
- wire _T_184; // @[TLULWriter.scala 114:22:@322.12]
- wire [1:0] _GEN_21; // @[TLULWriter.scala 114:31:@323.12]
- wire _GEN_23; // @[TLULWriter.scala 114:31:@323.12]
- wire [1:0] _GEN_24; // @[TLULWriter.scala 112:28:@320.10]
- wire _GEN_25; // @[TLULWriter.scala 112:28:@320.10]
- wire _GEN_26; // @[TLULWriter.scala 112:28:@320.10]
- wire _GEN_27; // @[Conditional.scala 39:67:@316.8]
- wire _GEN_28; // @[Conditional.scala 39:67:@316.8]
- wire [1:0] _GEN_30; // @[Conditional.scala 39:67:@316.8]
- wire _GEN_31; // @[Conditional.scala 39:67:@316.8]
- wire _GEN_32; // @[Conditional.scala 39:67:@284.6]
- wire _GEN_33; // @[Conditional.scala 39:67:@284.6]
- wire _GEN_34; // @[Conditional.scala 39:67:@284.6]
- wire [1:0] _GEN_35; // @[Conditional.scala 39:67:@284.6]
- wire [31:0] _GEN_36; // @[Conditional.scala 39:67:@284.6]
- wire [31:0] _GEN_37; // @[Conditional.scala 39:67:@284.6]
- wire _GEN_38; // @[Conditional.scala 39:67:@284.6]
- wire _GEN_39; // @[Conditional.scala 40:58:@265.4]
- wire _GEN_43; // @[Conditional.scala 40:58:@265.4]
- wire [1:0] _GEN_44; // @[Conditional.scala 40:58:@265.4]
- wire [31:0] _GEN_45; // @[Conditional.scala 40:58:@265.4]
- wire [31:0] _GEN_46; // @[Conditional.scala 40:58:@265.4]
- assign _T_151 = 2'h0 == state; // @[Conditional.scala 37:30:@264.4]
- assign _GEN_0 = io_xfer_valid ? 1'h1 : addrValid; // @[TLULWriter.scala 70:27:@270.6]
- assign _T_157 = io_dataIO_valid & addrValid; // @[TLULWriter.scala 74:28:@273.6]
- assign _GEN_2 = _T_157 ? 2'h1 : state; // @[TLULWriter.scala 74:42:@274.6]
- assign _GEN_3 = _T_157 ? io_xfer_length : xferCnt; // @[TLULWriter.scala 74:42:@274.6]
- assign _GEN_4 = _T_157 ? io_xfer_address : addr; // @[TLULWriter.scala 74:42:@274.6]
- assign _GEN_5 = _T_157 ? 1'h0 : _GEN_0; // @[TLULWriter.scala 74:42:@274.6]
- assign _T_160 = 2'h1 == state; // @[Conditional.scala 37:30:@283.6]
- assign _T_165 = xferCnt != 32'h0; // @[TLULWriter.scala 89:22:@290.10]
- assign _T_167 = addr + 32'h4; // @[TLULWriter.scala 90:24:@292.12]
- assign _T_168 = addr + 32'h4; // @[TLULWriter.scala 90:24:@293.12]
- assign _T_170 = xferCnt - 32'h1; // @[TLULWriter.scala 91:30:@295.12]
- assign _T_171 = $unsigned(_T_170); // @[TLULWriter.scala 91:30:@296.12]
- assign _T_172 = _T_171[31:0]; // @[TLULWriter.scala 91:30:@297.12]
- assign _GEN_6 = _T_165 ? _T_168 : addr; // @[TLULWriter.scala 89:31:@291.10]
- assign _GEN_7 = _T_165 ? _T_172 : xferCnt; // @[TLULWriter.scala 89:31:@291.10]
- assign _T_175 = xferCnt == 32'h1; // @[TLULWriter.scala 98:24:@302.12]
- assign _GEN_8 = _T_175 ? 2'h0 : 2'h1; // @[TLULWriter.scala 98:33:@303.12]
- assign _GEN_10 = _T_175 ? 1'h0 : 1'h1; // @[TLULWriter.scala 98:33:@303.12]
- assign _GEN_12 = io_bus_d_valid ? _GEN_8 : 2'h2; // @[TLULWriter.scala 95:30:@300.10]
- assign _GEN_13 = io_bus_d_valid ? _T_175 : 1'h0; // @[TLULWriter.scala 95:30:@300.10]
- assign _GEN_14 = io_bus_d_valid ? _GEN_10 : 1'h0; // @[TLULWriter.scala 95:30:@300.10]
- assign _GEN_15 = io_bus_a_ready ? _GEN_14 : valid; // @[TLULWriter.scala 85:28:@287.8]
- assign _GEN_16 = io_bus_a_ready ? _GEN_12 : state; // @[TLULWriter.scala 85:28:@287.8]
- assign _GEN_17 = io_bus_a_ready ? _GEN_6 : addr; // @[TLULWriter.scala 85:28:@287.8]
- assign _GEN_18 = io_bus_a_ready ? _GEN_7 : xferCnt; // @[TLULWriter.scala 85:28:@287.8]
- assign _GEN_19 = io_bus_a_ready ? io_bus_d_valid : 1'h0; // @[TLULWriter.scala 85:28:@287.8]
- assign _GEN_20 = io_bus_a_ready ? _GEN_13 : 1'h0; // @[TLULWriter.scala 85:28:@287.8]
- assign _T_178 = 2'h2 == state; // @[Conditional.scala 37:30:@315.8]
- assign _T_184 = xferCnt == 32'h0; // @[TLULWriter.scala 114:22:@322.12]
- assign _GEN_21 = _T_184 ? 2'h0 : 2'h1; // @[TLULWriter.scala 114:31:@323.12]
- assign _GEN_23 = _T_184 ? 1'h0 : 1'h1; // @[TLULWriter.scala 114:31:@323.12]
- assign _GEN_24 = io_bus_d_valid ? _GEN_21 : state; // @[TLULWriter.scala 112:28:@320.10]
- assign _GEN_25 = io_bus_d_valid ? _T_184 : 1'h0; // @[TLULWriter.scala 112:28:@320.10]
- assign _GEN_26 = io_bus_d_valid ? _GEN_23 : 1'h0; // @[TLULWriter.scala 112:28:@320.10]
- assign _GEN_27 = _T_178 ? _GEN_26 : valid; // @[Conditional.scala 39:67:@316.8]
- assign _GEN_28 = _T_178 ? io_bus_d_valid : 1'h0; // @[Conditional.scala 39:67:@316.8]
- assign _GEN_30 = _T_178 ? _GEN_24 : state; // @[Conditional.scala 39:67:@316.8]
- assign _GEN_31 = _T_178 ? _GEN_25 : 1'h0; // @[Conditional.scala 39:67:@316.8]
- assign _GEN_32 = _T_160 ? 1'h1 : _T_178; // @[Conditional.scala 39:67:@284.6]
- assign _GEN_33 = _T_160 ? _GEN_19 : _GEN_28; // @[Conditional.scala 39:67:@284.6]
- assign _GEN_34 = _T_160 ? _GEN_15 : _GEN_27; // @[Conditional.scala 39:67:@284.6]
- assign _GEN_35 = _T_160 ? _GEN_16 : _GEN_30; // @[Conditional.scala 39:67:@284.6]
- assign _GEN_36 = _T_160 ? _GEN_17 : addr; // @[Conditional.scala 39:67:@284.6]
- assign _GEN_37 = _T_160 ? _GEN_18 : xferCnt; // @[Conditional.scala 39:67:@284.6]
- assign _GEN_38 = _T_160 ? _GEN_20 : _GEN_31; // @[Conditional.scala 39:67:@284.6]
- assign _GEN_39 = _T_151 ? _T_157 : _GEN_34; // @[Conditional.scala 40:58:@265.4]
- assign _GEN_43 = _T_151 ? _GEN_5 : addrValid; // @[Conditional.scala 40:58:@265.4]
- assign _GEN_44 = _T_151 ? _GEN_2 : _GEN_35; // @[Conditional.scala 40:58:@265.4]
- assign _GEN_45 = _T_151 ? _GEN_3 : _GEN_37; // @[Conditional.scala 40:58:@265.4]
- assign _GEN_46 = _T_151 ? _GEN_4 : _GEN_36; // @[Conditional.scala 40:58:@265.4]
- assign io_bus_a_address = addr; // @[TLULWriter.scala 55:20:@260.4]
- assign io_bus_a_data = io_dataIO_bits; // @[TLULWriter.scala 48:17:@255.4]
- assign io_bus_a_valid = valid; // @[TLULWriter.scala 47:18:@254.4]
- assign io_bus_d_ready = _T_151 ? 1'h0 : _GEN_32; // @[TLULWriter.scala 42:12:@243.4 TLULWriter.scala 64:22:@267.6 TLULWriter.scala 83:22:@285.8 TLULWriter.scala 111:22:@319.10]
- assign io_dataIO_ready = _T_151 ? 1'h0 : _GEN_33; // @[TLULWriter.scala 45:19:@253.4]
- assign io_xfer_done = _T_151 ? 1'h0 : _GEN_38; // @[TLULWriter.scala 59:16:@263.4]
-`ifdef RANDOMIZE_GARBAGE_ASSIGN
-`define RANDOMIZE
-`endif
-`ifdef RANDOMIZE_INVALID_ASSIGN
-`define RANDOMIZE
-`endif
-`ifdef RANDOMIZE_REG_INIT
-`define RANDOMIZE
-`endif
-`ifdef RANDOMIZE_MEM_INIT
-`define RANDOMIZE
-`endif
-`ifndef RANDOM
-`define RANDOM $random
-`endif
-`ifdef RANDOMIZE
- integer initvar;
- initial begin
- `ifdef INIT_RANDOM
- `INIT_RANDOM
- `endif
- `ifndef VERILATOR
- #0.002 begin end
- `endif
- `ifdef RANDOMIZE_REG_INIT
- _RAND_0 = {1{`RANDOM}};
- state = _RAND_0[1:0];
- `endif // RANDOMIZE_REG_INIT
- `ifdef RANDOMIZE_REG_INIT
- _RAND_1 = {1{`RANDOM}};
- xferCnt = _RAND_1[31:0];
- `endif // RANDOMIZE_REG_INIT
- `ifdef RANDOMIZE_REG_INIT
- _RAND_2 = {1{`RANDOM}};
- addr = _RAND_2[31:0];
- `endif // RANDOMIZE_REG_INIT
- `ifdef RANDOMIZE_REG_INIT
- _RAND_3 = {1{`RANDOM}};
- addrValid = _RAND_3[0:0];
- `endif // RANDOMIZE_REG_INIT
- `ifdef RANDOMIZE_REG_INIT
- _RAND_4 = {1{`RANDOM}};
- valid = _RAND_4[0:0];
- `endif // RANDOMIZE_REG_INIT
- end
-`endif // RANDOMIZE
- always @(posedge clock) begin
- if (reset) begin
- state <= 2'h0;
- end else begin
- if (_T_151) begin
- if (_T_157) begin
- state <= 2'h1;
- end
- end else begin
- if (_T_160) begin
- if (io_bus_a_ready) begin
- if (io_bus_d_valid) begin
- if (_T_175) begin
- state <= 2'h0;
- end else begin
- state <= 2'h1;
- end
- end else begin
- state <= 2'h2;
- end
- end
- end else begin
- if (_T_178) begin
- if (io_bus_d_valid) begin
- if (_T_184) begin
- state <= 2'h0;
- end else begin
- state <= 2'h1;
- end
- end
- end
- end
- end
- end
- if (reset) begin
- xferCnt <= 32'h0;
- end else begin
- if (_T_151) begin
- if (_T_157) begin
- xferCnt <= io_xfer_length;
- end
- end else begin
- if (_T_160) begin
- if (io_bus_a_ready) begin
- if (_T_165) begin
- xferCnt <= _T_172;
- end
- end
- end
- end
- end
- if (reset) begin
- addr <= 32'h0;
- end else begin
- if (_T_151) begin
- if (_T_157) begin
- addr <= io_xfer_address;
- end
- end else begin
- if (_T_160) begin
- if (io_bus_a_ready) begin
- if (_T_165) begin
- addr <= _T_168;
- end
- end
- end
- end
- end
- if (reset) begin
- addrValid <= 1'h0;
- end else begin
- if (_T_151) begin
- if (_T_157) begin
- addrValid <= 1'h0;
- end else begin
- if (io_xfer_valid) begin
- addrValid <= 1'h1;
- end
- end
- end
- end
- if (reset) begin
- valid <= 1'h0;
- end else begin
- if (_T_151) begin
- valid <= _T_157;
- end else begin
- if (_T_160) begin
- if (io_bus_a_ready) begin
- if (io_bus_d_valid) begin
- if (_T_175) begin
- valid <= 1'h0;
- end else begin
- valid <= 1'h1;
- end
- end else begin
- valid <= 1'h0;
- end
- end
- end else begin
- if (_T_178) begin
- if (io_bus_d_valid) begin
- if (_T_184) begin
- valid <= 1'h0;
- end else begin
- valid <= 1'h1;
- end
- end else begin
- valid <= 1'h0;
- end
- end
- end
- end
- end
- end
-endmodule
-module CSRTL_TL_TL( // @[:@334.2]
- output [31:0] io_csr_0_dataOut, // @[:@337.4]
- output io_csr_0_dataWrite, // @[:@337.4]
- input [31:0] io_csr_0_dataIn, // @[:@337.4]
- input [31:0] io_csr_1_dataIn, // @[:@337.4]
- output [31:0] io_csr_2_dataOut, // @[:@337.4]
- output io_csr_2_dataWrite, // @[:@337.4]
- input [31:0] io_csr_2_dataIn, // @[:@337.4]
- output [31:0] io_csr_3_dataOut, // @[:@337.4]
- output io_csr_3_dataWrite, // @[:@337.4]
- input [31:0] io_csr_3_dataIn, // @[:@337.4]
- output [31:0] io_csr_4_dataOut, // @[:@337.4]
- output io_csr_4_dataWrite, // @[:@337.4]
- input [31:0] io_csr_4_dataIn, // @[:@337.4]
- output [31:0] io_csr_5_dataOut, // @[:@337.4]
- output io_csr_5_dataWrite, // @[:@337.4]
- input [31:0] io_csr_5_dataIn, // @[:@337.4]
- output [31:0] io_csr_6_dataOut, // @[:@337.4]
- output io_csr_6_dataWrite, // @[:@337.4]
- input [31:0] io_csr_6_dataIn, // @[:@337.4]
- output [31:0] io_csr_7_dataOut, // @[:@337.4]
- output io_csr_7_dataWrite, // @[:@337.4]
- input [31:0] io_csr_7_dataIn, // @[:@337.4]
- output [31:0] io_csr_8_dataOut, // @[:@337.4]
- output io_csr_8_dataWrite, // @[:@337.4]
- input [31:0] io_csr_8_dataIn, // @[:@337.4]
- output [31:0] io_csr_9_dataOut, // @[:@337.4]
- output io_csr_9_dataWrite, // @[:@337.4]
- input [31:0] io_csr_9_dataIn, // @[:@337.4]
- output [31:0] io_csr_10_dataOut, // @[:@337.4]
- output io_csr_10_dataWrite, // @[:@337.4]
- input [31:0] io_csr_10_dataIn, // @[:@337.4]
- output [31:0] io_csr_11_dataOut, // @[:@337.4]
- output io_csr_11_dataWrite, // @[:@337.4]
- input [31:0] io_csr_11_dataIn, // @[:@337.4]
- input [31:0] io_csr_12_dataIn, // @[:@337.4]
- input [31:0] io_csr_13_dataIn, // @[:@337.4]
- output [31:0] io_csr_14_dataOut, // @[:@337.4]
- output io_csr_14_dataWrite, // @[:@337.4]
- input [31:0] io_csr_14_dataIn, // @[:@337.4]
- output [31:0] io_csr_15_dataOut, // @[:@337.4]
- output io_csr_15_dataWrite, // @[:@337.4]
- input [31:0] io_csr_15_dataIn, // @[:@337.4]
- input [3:0] io_bus_addr, // @[:@337.4]
- input [31:0] io_bus_dataOut, // @[:@337.4]
- output [31:0] io_bus_dataIn, // @[:@337.4]
- input io_bus_write, // @[:@337.4]
- input io_bus_read // @[:@337.4]
-);
- wire _T_178; // @[CSR.scala 32:22:@342.4]
- wire _T_179; // @[CSR.scala 32:30:@343.4]
- wire [31:0] _GEN_0; // @[CSR.scala 32:45:@344.4]
- wire _T_184; // @[CSR.scala 39:30:@352.4]
- wire _T_189; // @[CSR.scala 32:22:@361.4]
- wire _T_190; // @[CSR.scala 32:30:@362.4]
- wire [31:0] _GEN_4; // @[CSR.scala 32:45:@363.4]
- wire _T_200; // @[CSR.scala 32:22:@380.4]
- wire _T_201; // @[CSR.scala 32:30:@381.4]
- wire [31:0] _GEN_8; // @[CSR.scala 32:45:@382.4]
- wire _T_206; // @[CSR.scala 39:30:@390.4]
- wire _T_211; // @[CSR.scala 32:22:@399.4]
- wire _T_212; // @[CSR.scala 32:30:@400.4]
- wire [31:0] _GEN_12; // @[CSR.scala 32:45:@401.4]
- wire _T_217; // @[CSR.scala 39:30:@409.4]
- wire _T_222; // @[CSR.scala 32:22:@418.4]
- wire _T_223; // @[CSR.scala 32:30:@419.4]
- wire [31:0] _GEN_16; // @[CSR.scala 32:45:@420.4]
- wire _T_228; // @[CSR.scala 39:30:@428.4]
- wire _T_233; // @[CSR.scala 32:22:@437.4]
- wire _T_234; // @[CSR.scala 32:30:@438.4]
- wire [31:0] _GEN_20; // @[CSR.scala 32:45:@439.4]
- wire _T_239; // @[CSR.scala 39:30:@447.4]
- wire _T_244; // @[CSR.scala 32:22:@456.4]
- wire _T_245; // @[CSR.scala 32:30:@457.4]
- wire [31:0] _GEN_24; // @[CSR.scala 32:45:@458.4]
- wire _T_250; // @[CSR.scala 39:30:@466.4]
- wire _T_255; // @[CSR.scala 32:22:@475.4]
- wire _T_256; // @[CSR.scala 32:30:@476.4]
- wire [31:0] _GEN_28; // @[CSR.scala 32:45:@477.4]
- wire _T_261; // @[CSR.scala 39:30:@485.4]
- wire _T_266; // @[CSR.scala 32:22:@494.4]
- wire _T_267; // @[CSR.scala 32:30:@495.4]
- wire [31:0] _GEN_32; // @[CSR.scala 32:45:@496.4]
- wire _T_272; // @[CSR.scala 39:30:@504.4]
- wire _T_277; // @[CSR.scala 32:22:@513.4]
- wire _T_278; // @[CSR.scala 32:30:@514.4]
- wire [31:0] _GEN_36; // @[CSR.scala 32:45:@515.4]
- wire _T_283; // @[CSR.scala 39:30:@523.4]
- wire _T_288; // @[CSR.scala 32:22:@532.4]
- wire _T_289; // @[CSR.scala 32:30:@533.4]
- wire [31:0] _GEN_40; // @[CSR.scala 32:45:@534.4]
- wire _T_294; // @[CSR.scala 39:30:@542.4]
- wire _T_299; // @[CSR.scala 32:22:@551.4]
- wire _T_300; // @[CSR.scala 32:30:@552.4]
- wire [31:0] _GEN_44; // @[CSR.scala 32:45:@553.4]
- wire _T_305; // @[CSR.scala 39:30:@561.4]
- wire _T_310; // @[CSR.scala 32:22:@570.4]
- wire _T_311; // @[CSR.scala 32:30:@571.4]
- wire [31:0] _GEN_48; // @[CSR.scala 32:45:@572.4]
- wire _T_321; // @[CSR.scala 32:22:@589.4]
- wire _T_322; // @[CSR.scala 32:30:@590.4]
- wire [31:0] _GEN_52; // @[CSR.scala 32:45:@591.4]
- wire _T_332; // @[CSR.scala 32:22:@608.4]
- wire _T_333; // @[CSR.scala 32:30:@609.4]
- wire [31:0] _GEN_56; // @[CSR.scala 32:45:@610.4]
- wire _T_338; // @[CSR.scala 39:30:@618.4]
- wire _T_343; // @[CSR.scala 32:22:@627.4]
- wire _T_344; // @[CSR.scala 32:30:@628.4]
- wire _T_349; // @[CSR.scala 39:30:@637.4]
- assign _T_178 = io_bus_addr == 4'h0; // @[CSR.scala 32:22:@342.4]
- assign _T_179 = _T_178 & io_bus_read; // @[CSR.scala 32:30:@343.4]
- assign _GEN_0 = _T_179 ? io_csr_0_dataIn : 32'h0; // @[CSR.scala 32:45:@344.4]
- assign _T_184 = _T_178 & io_bus_write; // @[CSR.scala 39:30:@352.4]
- assign _T_189 = io_bus_addr == 4'h1; // @[CSR.scala 32:22:@361.4]
- assign _T_190 = _T_189 & io_bus_read; // @[CSR.scala 32:30:@362.4]
- assign _GEN_4 = _T_190 ? io_csr_1_dataIn : _GEN_0; // @[CSR.scala 32:45:@363.4]
- assign _T_200 = io_bus_addr == 4'h2; // @[CSR.scala 32:22:@380.4]
- assign _T_201 = _T_200 & io_bus_read; // @[CSR.scala 32:30:@381.4]
- assign _GEN_8 = _T_201 ? io_csr_2_dataIn : _GEN_4; // @[CSR.scala 32:45:@382.4]
- assign _T_206 = _T_200 & io_bus_write; // @[CSR.scala 39:30:@390.4]
- assign _T_211 = io_bus_addr == 4'h3; // @[CSR.scala 32:22:@399.4]
- assign _T_212 = _T_211 & io_bus_read; // @[CSR.scala 32:30:@400.4]
- assign _GEN_12 = _T_212 ? io_csr_3_dataIn : _GEN_8; // @[CSR.scala 32:45:@401.4]
- assign _T_217 = _T_211 & io_bus_write; // @[CSR.scala 39:30:@409.4]
- assign _T_222 = io_bus_addr == 4'h4; // @[CSR.scala 32:22:@418.4]
- assign _T_223 = _T_222 & io_bus_read; // @[CSR.scala 32:30:@419.4]
- assign _GEN_16 = _T_223 ? io_csr_4_dataIn : _GEN_12; // @[CSR.scala 32:45:@420.4]
- assign _T_228 = _T_222 & io_bus_write; // @[CSR.scala 39:30:@428.4]
- assign _T_233 = io_bus_addr == 4'h5; // @[CSR.scala 32:22:@437.4]
- assign _T_234 = _T_233 & io_bus_read; // @[CSR.scala 32:30:@438.4]
- assign _GEN_20 = _T_234 ? io_csr_5_dataIn : _GEN_16; // @[CSR.scala 32:45:@439.4]
- assign _T_239 = _T_233 & io_bus_write; // @[CSR.scala 39:30:@447.4]
- assign _T_244 = io_bus_addr == 4'h6; // @[CSR.scala 32:22:@456.4]
- assign _T_245 = _T_244 & io_bus_read; // @[CSR.scala 32:30:@457.4]
- assign _GEN_24 = _T_245 ? io_csr_6_dataIn : _GEN_20; // @[CSR.scala 32:45:@458.4]
- assign _T_250 = _T_244 & io_bus_write; // @[CSR.scala 39:30:@466.4]
- assign _T_255 = io_bus_addr == 4'h7; // @[CSR.scala 32:22:@475.4]
- assign _T_256 = _T_255 & io_bus_read; // @[CSR.scala 32:30:@476.4]
- assign _GEN_28 = _T_256 ? io_csr_7_dataIn : _GEN_24; // @[CSR.scala 32:45:@477.4]
- assign _T_261 = _T_255 & io_bus_write; // @[CSR.scala 39:30:@485.4]
- assign _T_266 = io_bus_addr == 4'h8; // @[CSR.scala 32:22:@494.4]
- assign _T_267 = _T_266 & io_bus_read; // @[CSR.scala 32:30:@495.4]
- assign _GEN_32 = _T_267 ? io_csr_8_dataIn : _GEN_28; // @[CSR.scala 32:45:@496.4]
- assign _T_272 = _T_266 & io_bus_write; // @[CSR.scala 39:30:@504.4]
- assign _T_277 = io_bus_addr == 4'h9; // @[CSR.scala 32:22:@513.4]
- assign _T_278 = _T_277 & io_bus_read; // @[CSR.scala 32:30:@514.4]
- assign _GEN_36 = _T_278 ? io_csr_9_dataIn : _GEN_32; // @[CSR.scala 32:45:@515.4]
- assign _T_283 = _T_277 & io_bus_write; // @[CSR.scala 39:30:@523.4]
- assign _T_288 = io_bus_addr == 4'ha; // @[CSR.scala 32:22:@532.4]
- assign _T_289 = _T_288 & io_bus_read; // @[CSR.scala 32:30:@533.4]
- assign _GEN_40 = _T_289 ? io_csr_10_dataIn : _GEN_36; // @[CSR.scala 32:45:@534.4]
- assign _T_294 = _T_288 & io_bus_write; // @[CSR.scala 39:30:@542.4]
- assign _T_299 = io_bus_addr == 4'hb; // @[CSR.scala 32:22:@551.4]
- assign _T_300 = _T_299 & io_bus_read; // @[CSR.scala 32:30:@552.4]
- assign _GEN_44 = _T_300 ? io_csr_11_dataIn : _GEN_40; // @[CSR.scala 32:45:@553.4]
- assign _T_305 = _T_299 & io_bus_write; // @[CSR.scala 39:30:@561.4]
- assign _T_310 = io_bus_addr == 4'hc; // @[CSR.scala 32:22:@570.4]
- assign _T_311 = _T_310 & io_bus_read; // @[CSR.scala 32:30:@571.4]
- assign _GEN_48 = _T_311 ? io_csr_12_dataIn : _GEN_44; // @[CSR.scala 32:45:@572.4]
- assign _T_321 = io_bus_addr == 4'hd; // @[CSR.scala 32:22:@589.4]
- assign _T_322 = _T_321 & io_bus_read; // @[CSR.scala 32:30:@590.4]
- assign _GEN_52 = _T_322 ? io_csr_13_dataIn : _GEN_48; // @[CSR.scala 32:45:@591.4]
- assign _T_332 = io_bus_addr == 4'he; // @[CSR.scala 32:22:@608.4]
- assign _T_333 = _T_332 & io_bus_read; // @[CSR.scala 32:30:@609.4]
- assign _GEN_56 = _T_333 ? io_csr_14_dataIn : _GEN_52; // @[CSR.scala 32:45:@610.4]
- assign _T_338 = _T_332 & io_bus_write; // @[CSR.scala 39:30:@618.4]
- assign _T_343 = io_bus_addr == 4'hf; // @[CSR.scala 32:22:@627.4]
- assign _T_344 = _T_343 & io_bus_read; // @[CSR.scala 32:30:@628.4]
- assign _T_349 = _T_343 & io_bus_write; // @[CSR.scala 39:30:@637.4]
- assign io_csr_0_dataOut = _T_184 ? io_bus_dataOut : 32'h0; // @[CSR.scala 40:25:@354.6 CSR.scala 44:25:@359.6]
- assign io_csr_0_dataWrite = _T_178 & io_bus_write; // @[CSR.scala 41:27:@355.6 CSR.scala 43:27:@358.6]
- assign io_csr_2_dataOut = _T_206 ? io_bus_dataOut : 32'h0; // @[CSR.scala 40:25:@392.6 CSR.scala 44:25:@397.6]
- assign io_csr_2_dataWrite = _T_200 & io_bus_write; // @[CSR.scala 41:27:@393.6 CSR.scala 43:27:@396.6]
- assign io_csr_3_dataOut = _T_217 ? io_bus_dataOut : 32'h0; // @[CSR.scala 40:25:@411.6 CSR.scala 44:25:@416.6]
- assign io_csr_3_dataWrite = _T_211 & io_bus_write; // @[CSR.scala 41:27:@412.6 CSR.scala 43:27:@415.6]
- assign io_csr_4_dataOut = _T_228 ? io_bus_dataOut : 32'h0; // @[CSR.scala 40:25:@430.6 CSR.scala 44:25:@435.6]
- assign io_csr_4_dataWrite = _T_222 & io_bus_write; // @[CSR.scala 41:27:@431.6 CSR.scala 43:27:@434.6]
- assign io_csr_5_dataOut = _T_239 ? io_bus_dataOut : 32'h0; // @[CSR.scala 40:25:@449.6 CSR.scala 44:25:@454.6]
- assign io_csr_5_dataWrite = _T_233 & io_bus_write; // @[CSR.scala 41:27:@450.6 CSR.scala 43:27:@453.6]
- assign io_csr_6_dataOut = _T_250 ? io_bus_dataOut : 32'h0; // @[CSR.scala 40:25:@468.6 CSR.scala 44:25:@473.6]
- assign io_csr_6_dataWrite = _T_244 & io_bus_write; // @[CSR.scala 41:27:@469.6 CSR.scala 43:27:@472.6]
- assign io_csr_7_dataOut = _T_261 ? io_bus_dataOut : 32'h0; // @[CSR.scala 40:25:@487.6 CSR.scala 44:25:@492.6]
- assign io_csr_7_dataWrite = _T_255 & io_bus_write; // @[CSR.scala 41:27:@488.6 CSR.scala 43:27:@491.6]
- assign io_csr_8_dataOut = _T_272 ? io_bus_dataOut : 32'h0; // @[CSR.scala 40:25:@506.6 CSR.scala 44:25:@511.6]
- assign io_csr_8_dataWrite = _T_266 & io_bus_write; // @[CSR.scala 41:27:@507.6 CSR.scala 43:27:@510.6]
- assign io_csr_9_dataOut = _T_283 ? io_bus_dataOut : 32'h0; // @[CSR.scala 40:25:@525.6 CSR.scala 44:25:@530.6]
- assign io_csr_9_dataWrite = _T_277 & io_bus_write; // @[CSR.scala 41:27:@526.6 CSR.scala 43:27:@529.6]
- assign io_csr_10_dataOut = _T_294 ? io_bus_dataOut : 32'h0; // @[CSR.scala 40:25:@544.6 CSR.scala 44:25:@549.6]
- assign io_csr_10_dataWrite = _T_288 & io_bus_write; // @[CSR.scala 41:27:@545.6 CSR.scala 43:27:@548.6]
- assign io_csr_11_dataOut = _T_305 ? io_bus_dataOut : 32'h0; // @[CSR.scala 40:25:@563.6 CSR.scala 44:25:@568.6]
- assign io_csr_11_dataWrite = _T_299 & io_bus_write; // @[CSR.scala 41:27:@564.6 CSR.scala 43:27:@567.6]
- assign io_csr_14_dataOut = _T_338 ? io_bus_dataOut : 32'h0; // @[CSR.scala 40:25:@620.6 CSR.scala 44:25:@625.6]
- assign io_csr_14_dataWrite = _T_332 & io_bus_write; // @[CSR.scala 41:27:@621.6 CSR.scala 43:27:@624.6]
- assign io_csr_15_dataOut = _T_349 ? io_bus_dataOut : 32'h0; // @[CSR.scala 40:25:@639.6 CSR.scala 44:25:@644.6]
- assign io_csr_15_dataWrite = _T_343 & io_bus_write; // @[CSR.scala 41:27:@640.6 CSR.scala 43:27:@643.6]
- assign io_bus_dataIn = _T_344 ? io_csr_15_dataIn : _GEN_56; // @[CSR.scala 29:17:@341.4]
-endmodule
-module AddressGeneratorTL_TL_TL( // @[:@647.2]
- input clock, // @[:@648.4]
- input reset, // @[:@649.4]
- input io_ctl_start, // @[:@650.4]
- output io_ctl_busy, // @[:@650.4]
- input [31:0] io_ctl_startAddress, // @[:@650.4]
- input [31:0] io_ctl_lineLength, // @[:@650.4]
- input [31:0] io_ctl_lineCount, // @[:@650.4]
- input [31:0] io_ctl_lineGap, // @[:@650.4]
- input io_xfer_done, // @[:@650.4]
- output [31:0] io_xfer_address, // @[:@650.4]
- output [31:0] io_xfer_length, // @[:@650.4]
- output io_xfer_valid // @[:@650.4]
-);
- reg [1:0] state; // @[AddressGenerator.scala 29:22:@652.4]
- reg [31:0] _RAND_0;
- reg [31:0] lineCount; // @[AddressGenerator.scala 31:26:@653.4]
- reg [31:0] _RAND_1;
- reg [31:0] lineGap; // @[AddressGenerator.scala 32:24:@654.4]
- reg [31:0] _RAND_2;
- reg [31:0] address_o; // @[AddressGenerator.scala 34:26:@655.4]
- reg [31:0] _RAND_3;
- reg [31:0] address_i; // @[AddressGenerator.scala 35:26:@656.4]
- reg [31:0] _RAND_4;
- reg [31:0] length_o; // @[AddressGenerator.scala 36:25:@657.4]
- reg [31:0] _RAND_5;
- reg [31:0] length_i; // @[AddressGenerator.scala 37:25:@658.4]
- reg [31:0] _RAND_6;
- reg valid; // @[AddressGenerator.scala 38:22:@659.4]
- reg [31:0] _RAND_7;
- reg busy; // @[AddressGenerator.scala 40:21:@661.4]
- reg [31:0] _RAND_8;
- wire _T_46; // @[AddressGenerator.scala 48:14:@667.4]
- wire _GEN_0; // @[AddressGenerator.scala 48:24:@668.4]
- wire _T_49; // @[Conditional.scala 37:30:@674.4]
- wire [1:0] _GEN_1; // @[AddressGenerator.scala 56:25:@676.6]
- wire [31:0] _GEN_2; // @[AddressGenerator.scala 56:25:@676.6]
- wire [31:0] _GEN_3; // @[AddressGenerator.scala 56:25:@676.6]
- wire [31:0] _GEN_4; // @[AddressGenerator.scala 56:25:@676.6]
- wire [31:0] _GEN_5; // @[AddressGenerator.scala 56:25:@676.6]
- wire _T_51; // @[Conditional.scala 37:30:@686.6]
- wire [34:0] _T_54; // @[AddressGenerator.scala 71:42:@691.8]
- wire [34:0] _GEN_28; // @[AddressGenerator.scala 71:30:@692.8]
- wire [35:0] _T_55; // @[AddressGenerator.scala 71:30:@692.8]
- wire [34:0] _T_56; // @[AddressGenerator.scala 71:30:@693.8]
- wire [34:0] _T_58; // @[AddressGenerator.scala 71:74:@694.8]
- wire [35:0] _T_59; // @[AddressGenerator.scala 71:63:@695.8]
- wire [34:0] _T_60; // @[AddressGenerator.scala 71:63:@696.8]
- wire [32:0] _T_62; // @[AddressGenerator.scala 73:30:@698.8]
- wire [32:0] _T_63; // @[AddressGenerator.scala 73:30:@699.8]
- wire [31:0] _T_64; // @[AddressGenerator.scala 73:30:@700.8]
- wire _T_65; // @[Conditional.scala 37:30:@705.8]
- wire _T_69; // @[AddressGenerator.scala 80:24:@710.12]
- wire [1:0] _GEN_7; // @[AddressGenerator.scala 80:30:@711.12]
- wire [1:0] _GEN_8; // @[AddressGenerator.scala 79:25:@709.10]
- wire _GEN_9; // @[Conditional.scala 39:67:@706.8]
- wire [1:0] _GEN_11; // @[Conditional.scala 39:67:@706.8]
- wire _GEN_12; // @[Conditional.scala 39:67:@687.6]
- wire [31:0] _GEN_13; // @[Conditional.scala 39:67:@687.6]
- wire [31:0] _GEN_14; // @[Conditional.scala 39:67:@687.6]
- wire [34:0] _GEN_15; // @[Conditional.scala 39:67:@687.6]
- wire [31:0] _GEN_16; // @[Conditional.scala 39:67:@687.6]
- wire [1:0] _GEN_17; // @[Conditional.scala 39:67:@687.6]
- wire [1:0] _GEN_19; // @[Conditional.scala 40:58:@675.4]
- wire [34:0] _GEN_20; // @[Conditional.scala 40:58:@675.4]
- wire [31:0] _GEN_21; // @[Conditional.scala 40:58:@675.4]
- wire [31:0] _GEN_22; // @[Conditional.scala 40:58:@675.4]
- wire [31:0] _GEN_23; // @[Conditional.scala 40:58:@675.4]
- wire _GEN_25; // @[Conditional.scala 40:58:@675.4]
- wire [31:0] _GEN_26; // @[Conditional.scala 40:58:@675.4]
- wire [31:0] _GEN_27; // @[Conditional.scala 40:58:@675.4]
- assign _T_46 = state == 2'h0; // @[AddressGenerator.scala 48:14:@667.4]
- assign _GEN_0 = _T_46 ? 1'h0 : 1'h1; // @[AddressGenerator.scala 48:24:@668.4]
- assign _T_49 = 2'h0 == state; // @[Conditional.scala 37:30:@674.4]
- assign _GEN_1 = io_ctl_start ? 2'h1 : state; // @[AddressGenerator.scala 56:25:@676.6]
- assign _GEN_2 = io_ctl_start ? io_ctl_startAddress : address_i; // @[AddressGenerator.scala 56:25:@676.6]
- assign _GEN_3 = io_ctl_start ? io_ctl_lineLength : length_i; // @[AddressGenerator.scala 56:25:@676.6]
- assign _GEN_4 = io_ctl_start ? io_ctl_lineCount : lineCount; // @[AddressGenerator.scala 56:25:@676.6]
- assign _GEN_5 = io_ctl_start ? io_ctl_lineGap : lineGap; // @[AddressGenerator.scala 56:25:@676.6]
- assign _T_51 = 2'h1 == state; // @[Conditional.scala 37:30:@686.6]
- assign _T_54 = length_i * 32'h4; // @[AddressGenerator.scala 71:42:@691.8]
- assign _GEN_28 = {{3'd0}, address_i}; // @[AddressGenerator.scala 71:30:@692.8]
- assign _T_55 = _GEN_28 + _T_54; // @[AddressGenerator.scala 71:30:@692.8]
- assign _T_56 = _GEN_28 + _T_54; // @[AddressGenerator.scala 71:30:@693.8]
- assign _T_58 = lineGap * 32'h4; // @[AddressGenerator.scala 71:74:@694.8]
- assign _T_59 = _T_56 + _T_58; // @[AddressGenerator.scala 71:63:@695.8]
- assign _T_60 = _T_56 + _T_58; // @[AddressGenerator.scala 71:63:@696.8]
- assign _T_62 = lineCount - 32'h1; // @[AddressGenerator.scala 73:30:@698.8]
- assign _T_63 = $unsigned(_T_62); // @[AddressGenerator.scala 73:30:@699.8]
- assign _T_64 = _T_63[31:0]; // @[AddressGenerator.scala 73:30:@700.8]
- assign _T_65 = 2'h2 == state; // @[Conditional.scala 37:30:@705.8]
- assign _T_69 = lineCount > 32'h0; // @[AddressGenerator.scala 80:24:@710.12]
- assign _GEN_7 = _T_69 ? 2'h1 : 2'h0; // @[AddressGenerator.scala 80:30:@711.12]
- assign _GEN_8 = io_xfer_done ? _GEN_7 : state; // @[AddressGenerator.scala 79:25:@709.10]
- assign _GEN_9 = _T_65 ? 1'h0 : valid; // @[Conditional.scala 39:67:@706.8]
- assign _GEN_11 = _T_65 ? _GEN_8 : state; // @[Conditional.scala 39:67:@706.8]
- assign _GEN_12 = _T_51 ? 1'h1 : _GEN_9; // @[Conditional.scala 39:67:@687.6]
- assign _GEN_13 = _T_51 ? address_i : address_o; // @[Conditional.scala 39:67:@687.6]
- assign _GEN_14 = _T_51 ? length_i : length_o; // @[Conditional.scala 39:67:@687.6]
- assign _GEN_15 = _T_51 ? _T_60 : {{3'd0}, address_i}; // @[Conditional.scala 39:67:@687.6]
- assign _GEN_16 = _T_51 ? _T_64 : lineCount; // @[Conditional.scala 39:67:@687.6]
- assign _GEN_17 = _T_51 ? 2'h2 : _GEN_11; // @[Conditional.scala 39:67:@687.6]
- assign _GEN_19 = _T_49 ? _GEN_1 : _GEN_17; // @[Conditional.scala 40:58:@675.4]
- assign _GEN_20 = _T_49 ? {{3'd0}, _GEN_2} : _GEN_15; // @[Conditional.scala 40:58:@675.4]
- assign _GEN_21 = _T_49 ? _GEN_3 : length_i; // @[Conditional.scala 40:58:@675.4]
- assign _GEN_22 = _T_49 ? _GEN_4 : _GEN_16; // @[Conditional.scala 40:58:@675.4]
- assign _GEN_23 = _T_49 ? _GEN_5 : lineGap; // @[Conditional.scala 40:58:@675.4]
- assign _GEN_25 = _T_49 ? valid : _GEN_12; // @[Conditional.scala 40:58:@675.4]
- assign _GEN_26 = _T_49 ? address_o : _GEN_13; // @[Conditional.scala 40:58:@675.4]
- assign _GEN_27 = _T_49 ? length_o : _GEN_14; // @[Conditional.scala 40:58:@675.4]
- assign io_ctl_busy = busy; // @[AddressGenerator.scala 46:15:@666.4]
- assign io_xfer_address = address_o; // @[AddressGenerator.scala 42:19:@662.4]
- assign io_xfer_length = length_o; // @[AddressGenerator.scala 43:18:@663.4]
- assign io_xfer_valid = valid; // @[AddressGenerator.scala 44:17:@664.4]
-`ifdef RANDOMIZE_GARBAGE_ASSIGN
-`define RANDOMIZE
-`endif
-`ifdef RANDOMIZE_INVALID_ASSIGN
-`define RANDOMIZE
-`endif
-`ifdef RANDOMIZE_REG_INIT
-`define RANDOMIZE
-`endif
-`ifdef RANDOMIZE_MEM_INIT
-`define RANDOMIZE
-`endif
-`ifndef RANDOM
-`define RANDOM $random
-`endif
-`ifdef RANDOMIZE
- integer initvar;
- initial begin
- `ifdef INIT_RANDOM
- `INIT_RANDOM
- `endif
- `ifndef VERILATOR
- #0.002 begin end
- `endif
- `ifdef RANDOMIZE_REG_INIT
- _RAND_0 = {1{`RANDOM}};
- state = _RAND_0[1:0];
- `endif // RANDOMIZE_REG_INIT
- `ifdef RANDOMIZE_REG_INIT
- _RAND_1 = {1{`RANDOM}};
- lineCount = _RAND_1[31:0];
- `endif // RANDOMIZE_REG_INIT
- `ifdef RANDOMIZE_REG_INIT
- _RAND_2 = {1{`RANDOM}};
- lineGap = _RAND_2[31:0];
- `endif // RANDOMIZE_REG_INIT
- `ifdef RANDOMIZE_REG_INIT
- _RAND_3 = {1{`RANDOM}};
- address_o = _RAND_3[31:0];
- `endif // RANDOMIZE_REG_INIT
- `ifdef RANDOMIZE_REG_INIT
- _RAND_4 = {1{`RANDOM}};
- address_i = _RAND_4[31:0];
- `endif // RANDOMIZE_REG_INIT
- `ifdef RANDOMIZE_REG_INIT
- _RAND_5 = {1{`RANDOM}};
- length_o = _RAND_5[31:0];
- `endif // RANDOMIZE_REG_INIT
- `ifdef RANDOMIZE_REG_INIT
- _RAND_6 = {1{`RANDOM}};
- length_i = _RAND_6[31:0];
- `endif // RANDOMIZE_REG_INIT
- `ifdef RANDOMIZE_REG_INIT
- _RAND_7 = {1{`RANDOM}};
- valid = _RAND_7[0:0];
- `endif // RANDOMIZE_REG_INIT
- `ifdef RANDOMIZE_REG_INIT
- _RAND_8 = {1{`RANDOM}};
- busy = _RAND_8[0:0];
- `endif // RANDOMIZE_REG_INIT
- end
-`endif // RANDOMIZE
- always @(posedge clock) begin
- if (reset) begin
- state <= 2'h0;
- end else begin
- if (_T_49) begin
- if (io_ctl_start) begin
- state <= 2'h1;
- end
- end else begin
- if (_T_51) begin
- state <= 2'h2;
- end else begin
- if (_T_65) begin
- if (io_xfer_done) begin
- if (_T_69) begin
- state <= 2'h1;
- end else begin
- state <= 2'h0;
- end
- end
- end
- end
- end
- end
- if (reset) begin
- lineCount <= 32'h0;
- end else begin
- if (_T_49) begin
- if (io_ctl_start) begin
- lineCount <= io_ctl_lineCount;
- end
- end else begin
- if (_T_51) begin
- lineCount <= _T_64;
- end
- end
- end
- if (reset) begin
- lineGap <= 32'h0;
- end else begin
- if (_T_49) begin
- if (io_ctl_start) begin
- lineGap <= io_ctl_lineGap;
- end
- end
- end
- if (reset) begin
- address_o <= 32'h0;
- end else begin
- if (!(_T_49)) begin
- if (_T_51) begin
- address_o <= address_i;
- end
- end
- end
- if (reset) begin
- address_i <= 32'h0;
- end else begin
- address_i <= _GEN_20[31:0];
- end
- if (reset) begin
- length_o <= 32'h0;
- end else begin
- if (!(_T_49)) begin
- if (_T_51) begin
- length_o <= length_i;
- end
- end
- end
- if (reset) begin
- length_i <= 32'h0;
- end else begin
- if (_T_49) begin
- if (io_ctl_start) begin
- length_i <= io_ctl_lineLength;
- end
- end
- end
- if (reset) begin
- valid <= 1'h0;
- end else begin
- if (!(_T_49)) begin
- if (_T_51) begin
- valid <= 1'h1;
- end else begin
- if (_T_65) begin
- valid <= 1'h0;
- end
- end
- end
- end
- if (reset) begin
- busy <= 1'h0;
- end else begin
- if (_T_46) begin
- busy <= 1'h0;
- end else begin
- busy <= 1'h1;
- end
- end
- end
-endmodule
-module TransferSplitterTL_TL_TL( // @[:@720.2]
- output io_xferIn_done, // @[:@723.4]
- input [31:0] io_xferIn_address, // @[:@723.4]
- input [31:0] io_xferIn_length, // @[:@723.4]
- input io_xferIn_valid, // @[:@723.4]
- input io_xferOut_done, // @[:@723.4]
- output [31:0] io_xferOut_address, // @[:@723.4]
- output [31:0] io_xferOut_length, // @[:@723.4]
- output io_xferOut_valid // @[:@723.4]
-);
- assign io_xferIn_done = io_xferOut_done; // @[TransferSplitter.scala 124:16:@729.4]
- assign io_xferOut_address = io_xferIn_address; // @[TransferSplitter.scala 124:16:@728.4]
- assign io_xferOut_length = io_xferIn_length; // @[TransferSplitter.scala 124:16:@727.4]
- assign io_xferOut_valid = io_xferIn_valid; // @[TransferSplitter.scala 124:16:@726.4]
-endmodule
-module TransferSplitterTL_TL_TL_1( // @[:@804.2]
- input clock, // @[:@805.4]
- input reset, // @[:@806.4]
- output io_xferIn_done, // @[:@807.4]
- input [31:0] io_xferIn_address, // @[:@807.4]
- input [31:0] io_xferIn_length, // @[:@807.4]
- input io_xferIn_valid, // @[:@807.4]
- input io_xferOut_done, // @[:@807.4]
- output [31:0] io_xferOut_address, // @[:@807.4]
- output [31:0] io_xferOut_length, // @[:@807.4]
- output io_xferOut_valid // @[:@807.4]
-);
- reg [31:0] _T_42; // @[TransferSplitter.scala 35:28:@809.4]
- reg [31:0] _RAND_0;
- reg [31:0] _T_45; // @[TransferSplitter.scala 36:27:@810.4]
- reg [31:0] _RAND_1;
- reg [31:0] _T_48; // @[TransferSplitter.scala 38:28:@811.4]
- reg [31:0] _RAND_2;
- reg [31:0] _T_51; // @[TransferSplitter.scala 39:27:@812.4]
- reg [31:0] _RAND_3;
- reg _T_60; // @[TransferSplitter.scala 44:23:@815.4]
- reg [31:0] _RAND_4;
- reg _T_63; // @[TransferSplitter.scala 45:24:@816.4]
- reg [31:0] _RAND_5;
- reg [1:0] _T_65; // @[TransferSplitter.scala 47:24:@817.4]
- reg [31:0] _RAND_6;
- wire _T_66; // @[Conditional.scala 37:30:@823.4]
- wire [31:0] _GEN_0; // @[TransferSplitter.scala 60:31:@826.6]
- wire [31:0] _GEN_1; // @[TransferSplitter.scala 60:31:@826.6]
- wire [1:0] _GEN_3; // @[TransferSplitter.scala 60:31:@826.6]
- wire _T_68; // @[Conditional.scala 37:30:@834.6]
- wire _T_71; // @[TransferSplitter.scala 73:23:@840.8]
- wire [32:0] _T_74; // @[TransferSplitter.scala 76:34:@843.10]
- wire [32:0] _T_75; // @[TransferSplitter.scala 76:34:@844.10]
- wire [31:0] _T_76; // @[TransferSplitter.scala 76:34:@845.10]
- wire [11:0] _T_79; // @[TransferSplitter.scala 77:50:@847.10]
- wire [31:0] _GEN_33; // @[TransferSplitter.scala 77:36:@848.10]
- wire [32:0] _T_80; // @[TransferSplitter.scala 77:36:@848.10]
- wire [31:0] _T_81; // @[TransferSplitter.scala 77:36:@849.10]
- wire [34:0] _T_84; // @[TransferSplitter.scala 95:47:@855.10]
- wire [34:0] _GEN_34; // @[TransferSplitter.scala 95:36:@856.10]
- wire [35:0] _T_85; // @[TransferSplitter.scala 95:36:@856.10]
- wire [34:0] _T_86; // @[TransferSplitter.scala 95:36:@857.10]
- wire [31:0] _GEN_4; // @[TransferSplitter.scala 73:38:@841.8]
- wire [31:0] _GEN_5; // @[TransferSplitter.scala 73:38:@841.8]
- wire [34:0] _GEN_6; // @[TransferSplitter.scala 73:38:@841.8]
- wire _T_87; // @[Conditional.scala 37:30:@862.8]
- wire _T_91; // @[TransferSplitter.scala 114:25:@867.12]
- wire [1:0] _GEN_7; // @[TransferSplitter.scala 114:32:@868.12]
- wire _GEN_8; // @[TransferSplitter.scala 114:32:@868.12]
- wire [1:0] _GEN_9; // @[TransferSplitter.scala 113:31:@866.10]
- wire _GEN_10; // @[TransferSplitter.scala 113:31:@866.10]
- wire _GEN_11; // @[Conditional.scala 39:67:@863.8]
- wire [1:0] _GEN_13; // @[Conditional.scala 39:67:@863.8]
- wire _GEN_14; // @[Conditional.scala 39:67:@863.8]
- wire [31:0] _GEN_15; // @[Conditional.scala 39:67:@835.6]
- wire _GEN_17; // @[Conditional.scala 39:67:@835.6]
- wire [1:0] _GEN_18; // @[Conditional.scala 39:67:@835.6]
- wire [31:0] _GEN_19; // @[Conditional.scala 39:67:@835.6]
- wire [31:0] _GEN_20; // @[Conditional.scala 39:67:@835.6]
- wire [34:0] _GEN_21; // @[Conditional.scala 39:67:@835.6]
- wire _GEN_23; // @[Conditional.scala 39:67:@835.6]
- wire _GEN_24; // @[Conditional.scala 40:58:@824.4]
- wire [34:0] _GEN_25; // @[Conditional.scala 40:58:@824.4]
- wire [31:0] _GEN_26; // @[Conditional.scala 40:58:@824.4]
- wire [1:0] _GEN_28; // @[Conditional.scala 40:58:@824.4]
- wire [31:0] _GEN_29; // @[Conditional.scala 40:58:@824.4]
- wire _GEN_31; // @[Conditional.scala 40:58:@824.4]
- wire [31:0] _GEN_32; // @[Conditional.scala 40:58:@824.4]
- assign _T_66 = 2'h0 == _T_65; // @[Conditional.scala 37:30:@823.4]
- assign _GEN_0 = io_xferIn_valid ? io_xferIn_address : _T_42; // @[TransferSplitter.scala 60:31:@826.6]
- assign _GEN_1 = io_xferIn_valid ? io_xferIn_length : _T_45; // @[TransferSplitter.scala 60:31:@826.6]
- assign _GEN_3 = io_xferIn_valid ? 2'h1 : _T_65; // @[TransferSplitter.scala 60:31:@826.6]
- assign _T_68 = 2'h1 == _T_65; // @[Conditional.scala 37:30:@834.6]
- assign _T_71 = _T_45 > 32'h100; // @[TransferSplitter.scala 73:23:@840.8]
- assign _T_74 = _T_45 - 32'h100; // @[TransferSplitter.scala 76:34:@843.10]
- assign _T_75 = $unsigned(_T_74); // @[TransferSplitter.scala 76:34:@844.10]
- assign _T_76 = _T_75[31:0]; // @[TransferSplitter.scala 76:34:@845.10]
- assign _T_79 = 9'h100 * 9'h4; // @[TransferSplitter.scala 77:50:@847.10]
- assign _GEN_33 = {{20'd0}, _T_79}; // @[TransferSplitter.scala 77:36:@848.10]
- assign _T_80 = _T_42 + _GEN_33; // @[TransferSplitter.scala 77:36:@848.10]
- assign _T_81 = _T_42 + _GEN_33; // @[TransferSplitter.scala 77:36:@849.10]
- assign _T_84 = _T_45 * 32'h4; // @[TransferSplitter.scala 95:47:@855.10]
- assign _GEN_34 = {{3'd0}, _T_42}; // @[TransferSplitter.scala 95:36:@856.10]
- assign _T_85 = _GEN_34 + _T_84; // @[TransferSplitter.scala 95:36:@856.10]
- assign _T_86 = _GEN_34 + _T_84; // @[TransferSplitter.scala 95:36:@857.10]
- assign _GEN_4 = _T_71 ? 32'h100 : _T_45; // @[TransferSplitter.scala 73:38:@841.8]
- assign _GEN_5 = _T_71 ? _T_76 : 32'h0; // @[TransferSplitter.scala 73:38:@841.8]
- assign _GEN_6 = _T_71 ? {{3'd0}, _T_81} : _T_86; // @[TransferSplitter.scala 73:38:@841.8]
- assign _T_87 = 2'h2 == _T_65; // @[Conditional.scala 37:30:@862.8]
- assign _T_91 = _T_45 > 32'h0; // @[TransferSplitter.scala 114:25:@867.12]
- assign _GEN_7 = _T_91 ? 2'h1 : 2'h0; // @[TransferSplitter.scala 114:32:@868.12]
- assign _GEN_8 = _T_91 ? _T_60 : 1'h1; // @[TransferSplitter.scala 114:32:@868.12]
- assign _GEN_9 = io_xferOut_done ? _GEN_7 : _T_65; // @[TransferSplitter.scala 113:31:@866.10]
- assign _GEN_10 = io_xferOut_done ? _GEN_8 : _T_60; // @[TransferSplitter.scala 113:31:@866.10]
- assign _GEN_11 = _T_87 ? 1'h0 : _T_63; // @[Conditional.scala 39:67:@863.8]
- assign _GEN_13 = _T_87 ? _GEN_9 : _T_65; // @[Conditional.scala 39:67:@863.8]
- assign _GEN_14 = _T_87 ? _GEN_10 : _T_60; // @[Conditional.scala 39:67:@863.8]
- assign _GEN_15 = _T_68 ? _T_42 : _T_48; // @[Conditional.scala 39:67:@835.6]
- assign _GEN_17 = _T_68 ? 1'h1 : _GEN_11; // @[Conditional.scala 39:67:@835.6]
- assign _GEN_18 = _T_68 ? 2'h2 : _GEN_13; // @[Conditional.scala 39:67:@835.6]
- assign _GEN_19 = _T_68 ? _GEN_4 : _T_51; // @[Conditional.scala 39:67:@835.6]
- assign _GEN_20 = _T_68 ? _GEN_5 : _T_45; // @[Conditional.scala 39:67:@835.6]
- assign _GEN_21 = _T_68 ? _GEN_6 : {{3'd0}, _T_42}; // @[Conditional.scala 39:67:@835.6]
- assign _GEN_23 = _T_68 ? _T_60 : _GEN_14; // @[Conditional.scala 39:67:@835.6]
- assign _GEN_24 = _T_66 ? 1'h0 : _GEN_23; // @[Conditional.scala 40:58:@824.4]
- assign _GEN_25 = _T_66 ? {{3'd0}, _GEN_0} : _GEN_21; // @[Conditional.scala 40:58:@824.4]
- assign _GEN_26 = _T_66 ? _GEN_1 : _GEN_20; // @[Conditional.scala 40:58:@824.4]
- assign _GEN_28 = _T_66 ? _GEN_3 : _GEN_18; // @[Conditional.scala 40:58:@824.4]
- assign _GEN_29 = _T_66 ? _T_48 : _GEN_15; // @[Conditional.scala 40:58:@824.4]
- assign _GEN_31 = _T_66 ? _T_63 : _GEN_17; // @[Conditional.scala 40:58:@824.4]
- assign _GEN_32 = _T_66 ? _T_51 : _GEN_19; // @[Conditional.scala 40:58:@824.4]
- assign io_xferIn_done = _T_60; // @[TransferSplitter.scala 49:20:@818.4]
- assign io_xferOut_address = _T_48; // @[TransferSplitter.scala 53:24:@821.4]
- assign io_xferOut_length = _T_51; // @[TransferSplitter.scala 54:23:@822.4]
- assign io_xferOut_valid = _T_63; // @[TransferSplitter.scala 50:22:@819.4]
-`ifdef RANDOMIZE_GARBAGE_ASSIGN
-`define RANDOMIZE
-`endif
-`ifdef RANDOMIZE_INVALID_ASSIGN
-`define RANDOMIZE
-`endif
-`ifdef RANDOMIZE_REG_INIT
-`define RANDOMIZE
-`endif
-`ifdef RANDOMIZE_MEM_INIT
-`define RANDOMIZE
-`endif
-`ifndef RANDOM
-`define RANDOM $random
-`endif
-`ifdef RANDOMIZE
- integer initvar;
- initial begin
- `ifdef INIT_RANDOM
- `INIT_RANDOM
- `endif
- `ifndef VERILATOR
- #0.002 begin end
- `endif
- `ifdef RANDOMIZE_REG_INIT
- _RAND_0 = {1{`RANDOM}};
- _T_42 = _RAND_0[31:0];
- `endif // RANDOMIZE_REG_INIT
- `ifdef RANDOMIZE_REG_INIT
- _RAND_1 = {1{`RANDOM}};
- _T_45 = _RAND_1[31:0];
- `endif // RANDOMIZE_REG_INIT
- `ifdef RANDOMIZE_REG_INIT
- _RAND_2 = {1{`RANDOM}};
- _T_48 = _RAND_2[31:0];
- `endif // RANDOMIZE_REG_INIT
- `ifdef RANDOMIZE_REG_INIT
- _RAND_3 = {1{`RANDOM}};
- _T_51 = _RAND_3[31:0];
- `endif // RANDOMIZE_REG_INIT
- `ifdef RANDOMIZE_REG_INIT
- _RAND_4 = {1{`RANDOM}};
- _T_60 = _RAND_4[0:0];
- `endif // RANDOMIZE_REG_INIT
- `ifdef RANDOMIZE_REG_INIT
- _RAND_5 = {1{`RANDOM}};
- _T_63 = _RAND_5[0:0];
- `endif // RANDOMIZE_REG_INIT
- `ifdef RANDOMIZE_REG_INIT
- _RAND_6 = {1{`RANDOM}};
- _T_65 = _RAND_6[1:0];
- `endif // RANDOMIZE_REG_INIT
- end
-`endif // RANDOMIZE
- always @(posedge clock) begin
- if (reset) begin
- _T_42 <= 32'h0;
- end else begin
- _T_42 <= _GEN_25[31:0];
- end
- if (reset) begin
- _T_45 <= 32'h0;
- end else begin
- if (_T_66) begin
- if (io_xferIn_valid) begin
- _T_45 <= io_xferIn_length;
- end
- end else begin
- if (_T_68) begin
- if (_T_71) begin
- _T_45 <= _T_76;
- end else begin
- _T_45 <= 32'h0;
- end
- end
- end
- end
- if (reset) begin
- _T_48 <= 32'h0;
- end else begin
- if (!(_T_66)) begin
- if (_T_68) begin
- _T_48 <= _T_42;
- end
- end
- end
- if (reset) begin
- _T_51 <= 32'h0;
- end else begin
- if (!(_T_66)) begin
- if (_T_68) begin
- if (_T_71) begin
- _T_51 <= 32'h100;
- end else begin
- _T_51 <= _T_45;
- end
- end
- end
- end
- if (reset) begin
- _T_60 <= 1'h0;
- end else begin
- if (_T_66) begin
- _T_60 <= 1'h0;
- end else begin
- if (!(_T_68)) begin
- if (_T_87) begin
- if (io_xferOut_done) begin
- if (!(_T_91)) begin
- _T_60 <= 1'h1;
- end
- end
- end
- end
- end
- end
- if (reset) begin
- _T_63 <= 1'h0;
- end else begin
- if (!(_T_66)) begin
- if (_T_68) begin
- _T_63 <= 1'h1;
- end else begin
- if (_T_87) begin
- _T_63 <= 1'h0;
- end
- end
- end
- end
- if (reset) begin
- _T_65 <= 2'h0;
- end else begin
- if (_T_66) begin
- if (io_xferIn_valid) begin
- _T_65 <= 2'h1;
- end
- end else begin
- if (_T_68) begin
- _T_65 <= 2'h2;
- end else begin
- if (_T_87) begin
- if (io_xferOut_done) begin
- if (_T_91) begin
- _T_65 <= 2'h1;
- end else begin
- _T_65 <= 2'h0;
- end
- end
- end
- end
- end
- end
- end
-endmodule
-module ClearCSRTL_TL_TL( // @[:@878.2]
- input clock, // @[:@879.4]
- input reset, // @[:@880.4]
- input [31:0] io_csr_dataOut, // @[:@881.4]
- input io_csr_dataWrite, // @[:@881.4]
- output [31:0] io_csr_dataIn, // @[:@881.4]
- output [31:0] io_value, // @[:@881.4]
- input [31:0] io_clear // @[:@881.4]
-);
- reg [31:0] reg$; // @[ClearCSR.scala 28:20:@883.4]
- reg [31:0] _RAND_0;
- wire [31:0] _T_29; // @[ClearCSR.scala 36:19:@890.6]
- wire [31:0] _T_30; // @[ClearCSR.scala 36:16:@891.6]
- wire [31:0] _GEN_0; // @[ClearCSR.scala 33:25:@886.4]
- assign _T_29 = ~ io_clear; // @[ClearCSR.scala 36:19:@890.6]
- assign _T_30 = reg$ & _T_29; // @[ClearCSR.scala 36:16:@891.6]
- assign _GEN_0 = io_csr_dataWrite ? io_csr_dataOut : _T_30; // @[ClearCSR.scala 33:25:@886.4]
- assign io_csr_dataIn = reg$; // @[ClearCSR.scala 30:17:@884.4]
- assign io_value = reg$; // @[ClearCSR.scala 31:12:@885.4]
-`ifdef RANDOMIZE_GARBAGE_ASSIGN
-`define RANDOMIZE
-`endif
-`ifdef RANDOMIZE_INVALID_ASSIGN
-`define RANDOMIZE
-`endif
-`ifdef RANDOMIZE_REG_INIT
-`define RANDOMIZE
-`endif
-`ifdef RANDOMIZE_MEM_INIT
-`define RANDOMIZE
-`endif
-`ifndef RANDOM
-`define RANDOM $random
-`endif
-`ifdef RANDOMIZE
- integer initvar;
- initial begin
- `ifdef INIT_RANDOM
- `INIT_RANDOM
- `endif
- `ifndef VERILATOR
- #0.002 begin end
- `endif
- `ifdef RANDOMIZE_REG_INIT
- _RAND_0 = {1{`RANDOM}};
- reg$ = _RAND_0[31:0];
- `endif // RANDOMIZE_REG_INIT
- end
-`endif // RANDOMIZE
- always @(posedge clock) begin
- if (reset) begin
- reg$ <= 32'h0;
- end else begin
- if (io_csr_dataWrite) begin
- reg$ <= io_csr_dataOut;
- end else begin
- reg$ <= _T_30;
- end
- end
- end
-endmodule
-module StatusCSRTL_TL_TL( // @[:@895.2]
- input clock, // @[:@896.4]
- output [31:0] io_csr_dataIn, // @[:@898.4]
- input [31:0] io_value // @[:@898.4]
-);
- reg [31:0] reg$; // @[StatusCSR.scala 27:20:@900.4]
- reg [31:0] _RAND_0;
- assign io_csr_dataIn = reg$; // @[StatusCSR.scala 29:17:@902.4]
-`ifdef RANDOMIZE_GARBAGE_ASSIGN
-`define RANDOMIZE
-`endif
-`ifdef RANDOMIZE_INVALID_ASSIGN
-`define RANDOMIZE
-`endif
-`ifdef RANDOMIZE_REG_INIT
-`define RANDOMIZE
-`endif
-`ifdef RANDOMIZE_MEM_INIT
-`define RANDOMIZE
-`endif
-`ifndef RANDOM
-`define RANDOM $random
-`endif
-`ifdef RANDOMIZE
- integer initvar;
- initial begin
- `ifdef INIT_RANDOM
- `INIT_RANDOM
- `endif
- `ifndef VERILATOR
- #0.002 begin end
- `endif
- `ifdef RANDOMIZE_REG_INIT
- _RAND_0 = {1{`RANDOM}};
- reg$ = _RAND_0[31:0];
- `endif // RANDOMIZE_REG_INIT
- end
-`endif // RANDOMIZE
- always @(posedge clock) begin
- reg$ <= io_value;
- end
-endmodule
-module SimpleCSRTL_TL_TL( // @[:@904.2]
- input clock, // @[:@905.4]
- input reset, // @[:@906.4]
- input [31:0] io_csr_dataOut, // @[:@907.4]
- input io_csr_dataWrite, // @[:@907.4]
- output [31:0] io_csr_dataIn, // @[:@907.4]
- output [31:0] io_value // @[:@907.4]
-);
- reg [31:0] reg$; // @[SimpleCSR.scala 27:20:@909.4]
- reg [31:0] _RAND_0;
- wire [31:0] _GEN_0; // @[SimpleCSR.scala 32:25:@912.4]
- assign _GEN_0 = io_csr_dataWrite ? io_csr_dataOut : reg$; // @[SimpleCSR.scala 32:25:@912.4]
- assign io_csr_dataIn = reg$; // @[SimpleCSR.scala 29:17:@910.4]
- assign io_value = reg$; // @[SimpleCSR.scala 30:12:@911.4]
-`ifdef RANDOMIZE_GARBAGE_ASSIGN
-`define RANDOMIZE
-`endif
-`ifdef RANDOMIZE_INVALID_ASSIGN
-`define RANDOMIZE
-`endif
-`ifdef RANDOMIZE_REG_INIT
-`define RANDOMIZE
-`endif
-`ifdef RANDOMIZE_MEM_INIT
-`define RANDOMIZE
-`endif
-`ifndef RANDOM
-`define RANDOM $random
-`endif
-`ifdef RANDOMIZE
- integer initvar;
- initial begin
- `ifdef INIT_RANDOM
- `INIT_RANDOM
- `endif
- `ifndef VERILATOR
- #0.002 begin end
- `endif
- `ifdef RANDOMIZE_REG_INIT
- _RAND_0 = {1{`RANDOM}};
- reg$ = _RAND_0[31:0];
- `endif // RANDOMIZE_REG_INIT
- end
-`endif // RANDOMIZE
- always @(posedge clock) begin
- if (reset) begin
- reg$ <= 32'h0;
- end else begin
- if (io_csr_dataWrite) begin
- reg$ <= io_csr_dataOut;
- end
- end
- end
-endmodule
-module SetCSRTL_TL_TL( // @[:@916.2]
- input clock, // @[:@917.4]
- input reset, // @[:@918.4]
- input [31:0] io_csr_dataOut, // @[:@919.4]
- input io_csr_dataWrite, // @[:@919.4]
- output [31:0] io_csr_dataIn, // @[:@919.4]
- output [31:0] io_value, // @[:@919.4]
- input [31:0] io_set // @[:@919.4]
-);
- reg [31:0] reg$; // @[SetCSR.scala 28:20:@921.4]
- reg [31:0] _RAND_0;
- wire [31:0] _T_29; // @[SetCSR.scala 34:20:@925.6]
- wire [31:0] _T_30; // @[SetCSR.scala 34:17:@926.6]
- wire [31:0] _T_31; // @[SetCSR.scala 34:45:@927.6]
- wire [31:0] _T_32; // @[SetCSR.scala 36:16:@931.6]
- wire [31:0] _GEN_0; // @[SetCSR.scala 33:25:@924.4]
- assign _T_29 = ~ io_csr_dataOut; // @[SetCSR.scala 34:20:@925.6]
- assign _T_30 = reg$ & _T_29; // @[SetCSR.scala 34:17:@926.6]
- assign _T_31 = _T_30 | io_set; // @[SetCSR.scala 34:45:@927.6]
- assign _T_32 = reg$ | io_set; // @[SetCSR.scala 36:16:@931.6]
- assign _GEN_0 = io_csr_dataWrite ? _T_31 : _T_32; // @[SetCSR.scala 33:25:@924.4]
- assign io_csr_dataIn = reg$; // @[SetCSR.scala 30:17:@922.4]
- assign io_value = reg$; // @[SetCSR.scala 31:12:@923.4]
-`ifdef RANDOMIZE_GARBAGE_ASSIGN
-`define RANDOMIZE
-`endif
-`ifdef RANDOMIZE_INVALID_ASSIGN
-`define RANDOMIZE
-`endif
-`ifdef RANDOMIZE_REG_INIT
-`define RANDOMIZE
-`endif
-`ifdef RANDOMIZE_MEM_INIT
-`define RANDOMIZE
-`endif
-`ifndef RANDOM
-`define RANDOM $random
-`endif
-`ifdef RANDOMIZE
- integer initvar;
- initial begin
- `ifdef INIT_RANDOM
- `INIT_RANDOM
- `endif
- `ifndef VERILATOR
- #0.002 begin end
- `endif
- `ifdef RANDOMIZE_REG_INIT
- _RAND_0 = {1{`RANDOM}};
- reg$ = _RAND_0[31:0];
- `endif // RANDOMIZE_REG_INIT
- end
-`endif // RANDOMIZE
- always @(posedge clock) begin
- if (reset) begin
- reg$ <= 32'h0;
- end else begin
- if (io_csr_dataWrite) begin
- reg$ <= _T_31;
- end else begin
- reg$ <= _T_32;
- end
- end
- end
-endmodule
-module InterruptControllerTL_TL_TL( // @[:@935.2]
- input clock, // @[:@936.4]
- input reset, // @[:@937.4]
- output io_irq_readerDone, // @[:@938.4]
- output io_irq_writerDone, // @[:@938.4]
- input io_readBusy, // @[:@938.4]
- input io_writeBusy, // @[:@938.4]
- input [31:0] io_imr_dataOut, // @[:@938.4]
- input io_imr_dataWrite, // @[:@938.4]
- output [31:0] io_imr_dataIn, // @[:@938.4]
- input [31:0] io_isr_dataOut, // @[:@938.4]
- input io_isr_dataWrite, // @[:@938.4]
- output [31:0] io_isr_dataIn // @[:@938.4]
-);
- wire SimpleCSRTL_TL_TL_clock; // @[SimpleCSR.scala 40:21:@940.4]
- wire SimpleCSRTL_TL_TL_reset; // @[SimpleCSR.scala 40:21:@940.4]
- wire [31:0] SimpleCSRTL_TL_TL_io_csr_dataOut; // @[SimpleCSR.scala 40:21:@940.4]
- wire SimpleCSRTL_TL_TL_io_csr_dataWrite; // @[SimpleCSR.scala 40:21:@940.4]
- wire [31:0] SimpleCSRTL_TL_TL_io_csr_dataIn; // @[SimpleCSR.scala 40:21:@940.4]
- wire [31:0] SimpleCSRTL_TL_TL_io_value; // @[SimpleCSR.scala 40:21:@940.4]
- wire SetCSRTL_TL_TL_clock; // @[SetCSR.scala 43:21:@972.4]
- wire SetCSRTL_TL_TL_reset; // @[SetCSR.scala 43:21:@972.4]
- wire [31:0] SetCSRTL_TL_TL_io_csr_dataOut; // @[SetCSR.scala 43:21:@972.4]
- wire SetCSRTL_TL_TL_io_csr_dataWrite; // @[SetCSR.scala 43:21:@972.4]
- wire [31:0] SetCSRTL_TL_TL_io_csr_dataIn; // @[SetCSR.scala 43:21:@972.4]
- wire [31:0] SetCSRTL_TL_TL_io_value; // @[SetCSR.scala 43:21:@972.4]
- wire [31:0] SetCSRTL_TL_TL_io_set; // @[SetCSR.scala 43:21:@972.4]
- reg readBusy; // @[InterruptController.scala 33:25:@949.4]
- reg [31:0] _RAND_0;
- reg readBusyOld; // @[InterruptController.scala 34:28:@951.4]
- reg [31:0] _RAND_1;
- reg writeBusy; // @[InterruptController.scala 36:26:@953.4]
- reg [31:0] _RAND_2;
- reg writeBusyOld; // @[InterruptController.scala 37:29:@955.4]
- reg [31:0] _RAND_3;
- reg writeBusyIrq; // @[InterruptController.scala 39:29:@957.4]
- reg [31:0] _RAND_4;
- reg readBusyIrq; // @[InterruptController.scala 40:28:@958.4]
- reg [31:0] _RAND_5;
- wire _T_59; // @[InterruptController.scala 42:35:@959.4]
- wire _T_60; // @[InterruptController.scala 42:32:@960.4]
- wire [31:0] mask; // @[:@947.4 :@948.4]
- wire _T_61; // @[InterruptController.scala 42:53:@961.4]
- wire _T_62; // @[InterruptController.scala 42:46:@962.4]
- wire _T_64; // @[InterruptController.scala 43:33:@964.4]
- wire _T_65; // @[InterruptController.scala 43:30:@965.4]
- wire _T_66; // @[InterruptController.scala 43:50:@966.4]
- wire _T_67; // @[InterruptController.scala 43:43:@967.4]
- wire [1:0] irq; // @[Cat.scala 30:58:@969.4]
- wire [31:0] isr; // @[:@980.4 :@981.4]
- SimpleCSRTL_TL_TL SimpleCSRTL_TL_TL ( // @[SimpleCSR.scala 40:21:@940.4]
- .clock(SimpleCSRTL_TL_TL_clock),
- .reset(SimpleCSRTL_TL_TL_reset),
- .io_csr_dataOut(SimpleCSRTL_TL_TL_io_csr_dataOut),
- .io_csr_dataWrite(SimpleCSRTL_TL_TL_io_csr_dataWrite),
- .io_csr_dataIn(SimpleCSRTL_TL_TL_io_csr_dataIn),
- .io_value(SimpleCSRTL_TL_TL_io_value)
- );
- SetCSRTL_TL_TL SetCSRTL_TL_TL ( // @[SetCSR.scala 43:21:@972.4]
- .clock(SetCSRTL_TL_TL_clock),
- .reset(SetCSRTL_TL_TL_reset),
- .io_csr_dataOut(SetCSRTL_TL_TL_io_csr_dataOut),
- .io_csr_dataWrite(SetCSRTL_TL_TL_io_csr_dataWrite),
- .io_csr_dataIn(SetCSRTL_TL_TL_io_csr_dataIn),
- .io_value(SetCSRTL_TL_TL_io_value),
- .io_set(SetCSRTL_TL_TL_io_set)
- );
- assign _T_59 = writeBusy == 1'h0; // @[InterruptController.scala 42:35:@959.4]
- assign _T_60 = writeBusyOld & _T_59; // @[InterruptController.scala 42:32:@960.4]
- assign mask = SimpleCSRTL_TL_TL_io_value; // @[:@947.4 :@948.4]
- assign _T_61 = mask[0]; // @[InterruptController.scala 42:53:@961.4]
- assign _T_62 = _T_60 & _T_61; // @[InterruptController.scala 42:46:@962.4]
- assign _T_64 = readBusy == 1'h0; // @[InterruptController.scala 43:33:@964.4]
- assign _T_65 = readBusyOld & _T_64; // @[InterruptController.scala 43:30:@965.4]
- assign _T_66 = mask[1]; // @[InterruptController.scala 43:50:@966.4]
- assign _T_67 = _T_65 & _T_66; // @[InterruptController.scala 43:43:@967.4]
- assign irq = {readBusyIrq,writeBusyIrq}; // @[Cat.scala 30:58:@969.4]
- assign isr = SetCSRTL_TL_TL_io_value; // @[:@980.4 :@981.4]
- assign io_irq_readerDone = isr[1]; // @[InterruptController.scala 50:21:@985.4]
- assign io_irq_writerDone = isr[0]; // @[InterruptController.scala 49:21:@983.4]
- assign io_imr_dataIn = SimpleCSRTL_TL_TL_io_csr_dataIn; // @[SimpleCSR.scala 42:16:@943.4]
- assign io_isr_dataIn = SetCSRTL_TL_TL_io_csr_dataIn; // @[SetCSR.scala 47:16:@976.4]
- assign SimpleCSRTL_TL_TL_clock = clock; // @[:@941.4]
- assign SimpleCSRTL_TL_TL_reset = reset; // @[:@942.4]
- assign SimpleCSRTL_TL_TL_io_csr_dataOut = io_imr_dataOut; // @[SimpleCSR.scala 42:16:@945.4]
- assign SimpleCSRTL_TL_TL_io_csr_dataWrite = io_imr_dataWrite; // @[SimpleCSR.scala 42:16:@944.4]
- assign SetCSRTL_TL_TL_clock = clock; // @[:@973.4]
- assign SetCSRTL_TL_TL_reset = reset; // @[:@974.4]
- assign SetCSRTL_TL_TL_io_csr_dataOut = io_isr_dataOut; // @[SetCSR.scala 47:16:@978.4]
- assign SetCSRTL_TL_TL_io_csr_dataWrite = io_isr_dataWrite; // @[SetCSR.scala 47:16:@977.4]
- assign SetCSRTL_TL_TL_io_set = {{30'd0}, irq}; // @[SetCSR.scala 45:16:@975.4]
-`ifdef RANDOMIZE_GARBAGE_ASSIGN
-`define RANDOMIZE
-`endif
-`ifdef RANDOMIZE_INVALID_ASSIGN
-`define RANDOMIZE
-`endif
-`ifdef RANDOMIZE_REG_INIT
-`define RANDOMIZE
-`endif
-`ifdef RANDOMIZE_MEM_INIT
-`define RANDOMIZE
-`endif
-`ifndef RANDOM
-`define RANDOM $random
-`endif
-`ifdef RANDOMIZE
- integer initvar;
- initial begin
- `ifdef INIT_RANDOM
- `INIT_RANDOM
- `endif
- `ifndef VERILATOR
- #0.002 begin end
- `endif
- `ifdef RANDOMIZE_REG_INIT
- _RAND_0 = {1{`RANDOM}};
- readBusy = _RAND_0[0:0];
- `endif // RANDOMIZE_REG_INIT
- `ifdef RANDOMIZE_REG_INIT
- _RAND_1 = {1{`RANDOM}};
- readBusyOld = _RAND_1[0:0];
- `endif // RANDOMIZE_REG_INIT
- `ifdef RANDOMIZE_REG_INIT
- _RAND_2 = {1{`RANDOM}};
- writeBusy = _RAND_2[0:0];
- `endif // RANDOMIZE_REG_INIT
- `ifdef RANDOMIZE_REG_INIT
- _RAND_3 = {1{`RANDOM}};
- writeBusyOld = _RAND_3[0:0];
- `endif // RANDOMIZE_REG_INIT
- `ifdef RANDOMIZE_REG_INIT
- _RAND_4 = {1{`RANDOM}};
- writeBusyIrq = _RAND_4[0:0];
- `endif // RANDOMIZE_REG_INIT
- `ifdef RANDOMIZE_REG_INIT
- _RAND_5 = {1{`RANDOM}};
- readBusyIrq = _RAND_5[0:0];
- `endif // RANDOMIZE_REG_INIT
- end
-`endif // RANDOMIZE
- always @(posedge clock) begin
- readBusy <= io_readBusy;
- readBusyOld <= readBusy;
- writeBusy <= io_writeBusy;
- writeBusyOld <= writeBusy;
- if (reset) begin
- writeBusyIrq <= 1'h0;
- end else begin
- writeBusyIrq <= _T_62;
- end
- if (reset) begin
- readBusyIrq <= 1'h0;
- end else begin
- readBusyIrq <= _T_67;
- end
- end
-endmodule
-module WorkerCSRWrapperTL_TL_TL( // @[:@1125.2]
- input clock, // @[:@1126.4]
- input reset, // @[:@1127.4]
- input [31:0] io_csr_0_dataOut, // @[:@1128.4]
- input io_csr_0_dataWrite, // @[:@1128.4]
- output [31:0] io_csr_0_dataIn, // @[:@1128.4]
- output [31:0] io_csr_1_dataIn, // @[:@1128.4]
- input [31:0] io_csr_2_dataOut, // @[:@1128.4]
- input io_csr_2_dataWrite, // @[:@1128.4]
- output [31:0] io_csr_2_dataIn, // @[:@1128.4]
- input [31:0] io_csr_3_dataOut, // @[:@1128.4]
- input io_csr_3_dataWrite, // @[:@1128.4]
- output [31:0] io_csr_3_dataIn, // @[:@1128.4]
- input [31:0] io_csr_4_dataOut, // @[:@1128.4]
- input io_csr_4_dataWrite, // @[:@1128.4]
- output [31:0] io_csr_4_dataIn, // @[:@1128.4]
- input [31:0] io_csr_5_dataOut, // @[:@1128.4]
- input io_csr_5_dataWrite, // @[:@1128.4]
- output [31:0] io_csr_5_dataIn, // @[:@1128.4]
- input [31:0] io_csr_6_dataOut, // @[:@1128.4]
- input io_csr_6_dataWrite, // @[:@1128.4]
- output [31:0] io_csr_6_dataIn, // @[:@1128.4]
- input [31:0] io_csr_7_dataOut, // @[:@1128.4]
- input io_csr_7_dataWrite, // @[:@1128.4]
- output [31:0] io_csr_7_dataIn, // @[:@1128.4]
- input [31:0] io_csr_8_dataOut, // @[:@1128.4]
- input io_csr_8_dataWrite, // @[:@1128.4]
- output [31:0] io_csr_8_dataIn, // @[:@1128.4]
- input [31:0] io_csr_9_dataOut, // @[:@1128.4]
- input io_csr_9_dataWrite, // @[:@1128.4]
- output [31:0] io_csr_9_dataIn, // @[:@1128.4]
- input [31:0] io_csr_10_dataOut, // @[:@1128.4]
- input io_csr_10_dataWrite, // @[:@1128.4]
- output [31:0] io_csr_10_dataIn, // @[:@1128.4]
- input [31:0] io_csr_11_dataOut, // @[:@1128.4]
- input io_csr_11_dataWrite, // @[:@1128.4]
- output [31:0] io_csr_11_dataIn, // @[:@1128.4]
- output [31:0] io_csr_12_dataIn, // @[:@1128.4]
- output [31:0] io_csr_13_dataIn, // @[:@1128.4]
- input [31:0] io_csr_14_dataOut, // @[:@1128.4]
- input io_csr_14_dataWrite, // @[:@1128.4]
- output [31:0] io_csr_14_dataIn, // @[:@1128.4]
- input [31:0] io_csr_15_dataOut, // @[:@1128.4]
- input io_csr_15_dataWrite, // @[:@1128.4]
- output [31:0] io_csr_15_dataIn, // @[:@1128.4]
- output io_irq_readerDone, // @[:@1128.4]
- output io_irq_writerDone, // @[:@1128.4]
- input io_sync_readerSync, // @[:@1128.4]
- input io_sync_writerSync, // @[:@1128.4]
- input io_xferRead_done, // @[:@1128.4]
- output [31:0] io_xferRead_address, // @[:@1128.4]
- output [31:0] io_xferRead_length, // @[:@1128.4]
- output io_xferRead_valid, // @[:@1128.4]
- input io_xferWrite_done, // @[:@1128.4]
- output [31:0] io_xferWrite_address, // @[:@1128.4]
- output [31:0] io_xferWrite_length, // @[:@1128.4]
- output io_xferWrite_valid // @[:@1128.4]
-);
- wire addressGeneratorRead_clock; // @[WorkerCSRWrapper.scala 33:36:@1130.4]
- wire addressGeneratorRead_reset; // @[WorkerCSRWrapper.scala 33:36:@1130.4]
- wire addressGeneratorRead_io_ctl_start; // @[WorkerCSRWrapper.scala 33:36:@1130.4]
- wire addressGeneratorRead_io_ctl_busy; // @[WorkerCSRWrapper.scala 33:36:@1130.4]
- wire [31:0] addressGeneratorRead_io_ctl_startAddress; // @[WorkerCSRWrapper.scala 33:36:@1130.4]
- wire [31:0] addressGeneratorRead_io_ctl_lineLength; // @[WorkerCSRWrapper.scala 33:36:@1130.4]
- wire [31:0] addressGeneratorRead_io_ctl_lineCount; // @[WorkerCSRWrapper.scala 33:36:@1130.4]
- wire [31:0] addressGeneratorRead_io_ctl_lineGap; // @[WorkerCSRWrapper.scala 33:36:@1130.4]
- wire addressGeneratorRead_io_xfer_done; // @[WorkerCSRWrapper.scala 33:36:@1130.4]
- wire [31:0] addressGeneratorRead_io_xfer_address; // @[WorkerCSRWrapper.scala 33:36:@1130.4]
- wire [31:0] addressGeneratorRead_io_xfer_length; // @[WorkerCSRWrapper.scala 33:36:@1130.4]
- wire addressGeneratorRead_io_xfer_valid; // @[WorkerCSRWrapper.scala 33:36:@1130.4]
- wire transferSplitterRead_io_xferIn_done; // @[WorkerCSRWrapper.scala 34:36:@1133.4]
- wire [31:0] transferSplitterRead_io_xferIn_address; // @[WorkerCSRWrapper.scala 34:36:@1133.4]
- wire [31:0] transferSplitterRead_io_xferIn_length; // @[WorkerCSRWrapper.scala 34:36:@1133.4]
- wire transferSplitterRead_io_xferIn_valid; // @[WorkerCSRWrapper.scala 34:36:@1133.4]
- wire transferSplitterRead_io_xferOut_done; // @[WorkerCSRWrapper.scala 34:36:@1133.4]
- wire [31:0] transferSplitterRead_io_xferOut_address; // @[WorkerCSRWrapper.scala 34:36:@1133.4]
- wire [31:0] transferSplitterRead_io_xferOut_length; // @[WorkerCSRWrapper.scala 34:36:@1133.4]
- wire transferSplitterRead_io_xferOut_valid; // @[WorkerCSRWrapper.scala 34:36:@1133.4]
- wire addressGeneratorWrite_clock; // @[WorkerCSRWrapper.scala 36:37:@1136.4]
- wire addressGeneratorWrite_reset; // @[WorkerCSRWrapper.scala 36:37:@1136.4]
- wire addressGeneratorWrite_io_ctl_start; // @[WorkerCSRWrapper.scala 36:37:@1136.4]
- wire addressGeneratorWrite_io_ctl_busy; // @[WorkerCSRWrapper.scala 36:37:@1136.4]
- wire [31:0] addressGeneratorWrite_io_ctl_startAddress; // @[WorkerCSRWrapper.scala 36:37:@1136.4]
- wire [31:0] addressGeneratorWrite_io_ctl_lineLength; // @[WorkerCSRWrapper.scala 36:37:@1136.4]
- wire [31:0] addressGeneratorWrite_io_ctl_lineCount; // @[WorkerCSRWrapper.scala 36:37:@1136.4]
- wire [31:0] addressGeneratorWrite_io_ctl_lineGap; // @[WorkerCSRWrapper.scala 36:37:@1136.4]
- wire addressGeneratorWrite_io_xfer_done; // @[WorkerCSRWrapper.scala 36:37:@1136.4]
- wire [31:0] addressGeneratorWrite_io_xfer_address; // @[WorkerCSRWrapper.scala 36:37:@1136.4]
- wire [31:0] addressGeneratorWrite_io_xfer_length; // @[WorkerCSRWrapper.scala 36:37:@1136.4]
- wire addressGeneratorWrite_io_xfer_valid; // @[WorkerCSRWrapper.scala 36:37:@1136.4]
- wire transferSplitterWrite_clock; // @[WorkerCSRWrapper.scala 37:37:@1139.4]
- wire transferSplitterWrite_reset; // @[WorkerCSRWrapper.scala 37:37:@1139.4]
- wire transferSplitterWrite_io_xferIn_done; // @[WorkerCSRWrapper.scala 37:37:@1139.4]
- wire [31:0] transferSplitterWrite_io_xferIn_address; // @[WorkerCSRWrapper.scala 37:37:@1139.4]
- wire [31:0] transferSplitterWrite_io_xferIn_length; // @[WorkerCSRWrapper.scala 37:37:@1139.4]
- wire transferSplitterWrite_io_xferIn_valid; // @[WorkerCSRWrapper.scala 37:37:@1139.4]
- wire transferSplitterWrite_io_xferOut_done; // @[WorkerCSRWrapper.scala 37:37:@1139.4]
- wire [31:0] transferSplitterWrite_io_xferOut_address; // @[WorkerCSRWrapper.scala 37:37:@1139.4]
- wire [31:0] transferSplitterWrite_io_xferOut_length; // @[WorkerCSRWrapper.scala 37:37:@1139.4]
- wire transferSplitterWrite_io_xferOut_valid; // @[WorkerCSRWrapper.scala 37:37:@1139.4]
- wire ClearCSRTL_TL_TL_clock; // @[ClearCSR.scala 42:21:@1159.4]
- wire ClearCSRTL_TL_TL_reset; // @[ClearCSR.scala 42:21:@1159.4]
- wire [31:0] ClearCSRTL_TL_TL_io_csr_dataOut; // @[ClearCSR.scala 42:21:@1159.4]
- wire ClearCSRTL_TL_TL_io_csr_dataWrite; // @[ClearCSR.scala 42:21:@1159.4]
- wire [31:0] ClearCSRTL_TL_TL_io_csr_dataIn; // @[ClearCSR.scala 42:21:@1159.4]
- wire [31:0] ClearCSRTL_TL_TL_io_value; // @[ClearCSR.scala 42:21:@1159.4]
- wire [31:0] ClearCSRTL_TL_TL_io_clear; // @[ClearCSR.scala 42:21:@1159.4]
- wire StatusCSRTL_TL_TL_clock; // @[StatusCSR.scala 34:21:@1168.4]
- wire [31:0] StatusCSRTL_TL_TL_io_csr_dataIn; // @[StatusCSR.scala 34:21:@1168.4]
- wire [31:0] StatusCSRTL_TL_TL_io_value; // @[StatusCSR.scala 34:21:@1168.4]
- wire InterruptControllerTL_TL_TL_clock; // @[InterruptController.scala 55:22:@1176.4]
- wire InterruptControllerTL_TL_TL_reset; // @[InterruptController.scala 55:22:@1176.4]
- wire InterruptControllerTL_TL_TL_io_irq_readerDone; // @[InterruptController.scala 55:22:@1176.4]
- wire InterruptControllerTL_TL_TL_io_irq_writerDone; // @[InterruptController.scala 55:22:@1176.4]
- wire InterruptControllerTL_TL_TL_io_readBusy; // @[InterruptController.scala 55:22:@1176.4]
- wire InterruptControllerTL_TL_TL_io_writeBusy; // @[InterruptController.scala 55:22:@1176.4]
- wire [31:0] InterruptControllerTL_TL_TL_io_imr_dataOut; // @[InterruptController.scala 55:22:@1176.4]
- wire InterruptControllerTL_TL_TL_io_imr_dataWrite; // @[InterruptController.scala 55:22:@1176.4]
- wire [31:0] InterruptControllerTL_TL_TL_io_imr_dataIn; // @[InterruptController.scala 55:22:@1176.4]
- wire [31:0] InterruptControllerTL_TL_TL_io_isr_dataOut; // @[InterruptController.scala 55:22:@1176.4]
- wire InterruptControllerTL_TL_TL_io_isr_dataWrite; // @[InterruptController.scala 55:22:@1176.4]
- wire [31:0] InterruptControllerTL_TL_TL_io_isr_dataIn; // @[InterruptController.scala 55:22:@1176.4]
- wire SimpleCSRTL_TL_TL_clock; // @[SimpleCSR.scala 40:21:@1213.4]
- wire SimpleCSRTL_TL_TL_reset; // @[SimpleCSR.scala 40:21:@1213.4]
- wire [31:0] SimpleCSRTL_TL_TL_io_csr_dataOut; // @[SimpleCSR.scala 40:21:@1213.4]
- wire SimpleCSRTL_TL_TL_io_csr_dataWrite; // @[SimpleCSR.scala 40:21:@1213.4]
- wire [31:0] SimpleCSRTL_TL_TL_io_csr_dataIn; // @[SimpleCSR.scala 40:21:@1213.4]
- wire [31:0] SimpleCSRTL_TL_TL_io_value; // @[SimpleCSR.scala 40:21:@1213.4]
- wire SimpleCSRTL_TL_TL_1_clock; // @[SimpleCSR.scala 40:21:@1221.4]
- wire SimpleCSRTL_TL_TL_1_reset; // @[SimpleCSR.scala 40:21:@1221.4]
- wire [31:0] SimpleCSRTL_TL_TL_1_io_csr_dataOut; // @[SimpleCSR.scala 40:21:@1221.4]
- wire SimpleCSRTL_TL_TL_1_io_csr_dataWrite; // @[SimpleCSR.scala 40:21:@1221.4]
- wire [31:0] SimpleCSRTL_TL_TL_1_io_csr_dataIn; // @[SimpleCSR.scala 40:21:@1221.4]
- wire [31:0] SimpleCSRTL_TL_TL_1_io_value; // @[SimpleCSR.scala 40:21:@1221.4]
- wire SimpleCSRTL_TL_TL_2_clock; // @[SimpleCSR.scala 40:21:@1229.4]
- wire SimpleCSRTL_TL_TL_2_reset; // @[SimpleCSR.scala 40:21:@1229.4]
- wire [31:0] SimpleCSRTL_TL_TL_2_io_csr_dataOut; // @[SimpleCSR.scala 40:21:@1229.4]
- wire SimpleCSRTL_TL_TL_2_io_csr_dataWrite; // @[SimpleCSR.scala 40:21:@1229.4]
- wire [31:0] SimpleCSRTL_TL_TL_2_io_csr_dataIn; // @[SimpleCSR.scala 40:21:@1229.4]
- wire [31:0] SimpleCSRTL_TL_TL_2_io_value; // @[SimpleCSR.scala 40:21:@1229.4]
- wire SimpleCSRTL_TL_TL_3_clock; // @[SimpleCSR.scala 40:21:@1237.4]
- wire SimpleCSRTL_TL_TL_3_reset; // @[SimpleCSR.scala 40:21:@1237.4]
- wire [31:0] SimpleCSRTL_TL_TL_3_io_csr_dataOut; // @[SimpleCSR.scala 40:21:@1237.4]
- wire SimpleCSRTL_TL_TL_3_io_csr_dataWrite; // @[SimpleCSR.scala 40:21:@1237.4]
- wire [31:0] SimpleCSRTL_TL_TL_3_io_csr_dataIn; // @[SimpleCSR.scala 40:21:@1237.4]
- wire [31:0] SimpleCSRTL_TL_TL_3_io_value; // @[SimpleCSR.scala 40:21:@1237.4]
- wire SimpleCSRTL_TL_TL_4_clock; // @[SimpleCSR.scala 40:21:@1246.4]
- wire SimpleCSRTL_TL_TL_4_reset; // @[SimpleCSR.scala 40:21:@1246.4]
- wire [31:0] SimpleCSRTL_TL_TL_4_io_csr_dataOut; // @[SimpleCSR.scala 40:21:@1246.4]
- wire SimpleCSRTL_TL_TL_4_io_csr_dataWrite; // @[SimpleCSR.scala 40:21:@1246.4]
- wire [31:0] SimpleCSRTL_TL_TL_4_io_csr_dataIn; // @[SimpleCSR.scala 40:21:@1246.4]
- wire [31:0] SimpleCSRTL_TL_TL_4_io_value; // @[SimpleCSR.scala 40:21:@1246.4]
- wire SimpleCSRTL_TL_TL_5_clock; // @[SimpleCSR.scala 40:21:@1254.4]
- wire SimpleCSRTL_TL_TL_5_reset; // @[SimpleCSR.scala 40:21:@1254.4]
- wire [31:0] SimpleCSRTL_TL_TL_5_io_csr_dataOut; // @[SimpleCSR.scala 40:21:@1254.4]
- wire SimpleCSRTL_TL_TL_5_io_csr_dataWrite; // @[SimpleCSR.scala 40:21:@1254.4]
- wire [31:0] SimpleCSRTL_TL_TL_5_io_csr_dataIn; // @[SimpleCSR.scala 40:21:@1254.4]
- wire [31:0] SimpleCSRTL_TL_TL_5_io_value; // @[SimpleCSR.scala 40:21:@1254.4]
- wire SimpleCSRTL_TL_TL_6_clock; // @[SimpleCSR.scala 40:21:@1262.4]
- wire SimpleCSRTL_TL_TL_6_reset; // @[SimpleCSR.scala 40:21:@1262.4]
- wire [31:0] SimpleCSRTL_TL_TL_6_io_csr_dataOut; // @[SimpleCSR.scala 40:21:@1262.4]
- wire SimpleCSRTL_TL_TL_6_io_csr_dataWrite; // @[SimpleCSR.scala 40:21:@1262.4]
- wire [31:0] SimpleCSRTL_TL_TL_6_io_csr_dataIn; // @[SimpleCSR.scala 40:21:@1262.4]
- wire [31:0] SimpleCSRTL_TL_TL_6_io_value; // @[SimpleCSR.scala 40:21:@1262.4]
- wire SimpleCSRTL_TL_TL_7_clock; // @[SimpleCSR.scala 40:21:@1270.4]
- wire SimpleCSRTL_TL_TL_7_reset; // @[SimpleCSR.scala 40:21:@1270.4]
- wire [31:0] SimpleCSRTL_TL_TL_7_io_csr_dataOut; // @[SimpleCSR.scala 40:21:@1270.4]
- wire SimpleCSRTL_TL_TL_7_io_csr_dataWrite; // @[SimpleCSR.scala 40:21:@1270.4]
- wire [31:0] SimpleCSRTL_TL_TL_7_io_csr_dataIn; // @[SimpleCSR.scala 40:21:@1270.4]
- wire [31:0] SimpleCSRTL_TL_TL_7_io_value; // @[SimpleCSR.scala 40:21:@1270.4]
- wire StatusCSRTL_TL_TL_1_clock; // @[StatusCSR.scala 34:21:@1278.4]
- wire [31:0] StatusCSRTL_TL_TL_1_io_csr_dataIn; // @[StatusCSR.scala 34:21:@1278.4]
- wire [31:0] StatusCSRTL_TL_TL_1_io_value; // @[StatusCSR.scala 34:21:@1278.4]
- wire StatusCSRTL_TL_TL_2_clock; // @[StatusCSR.scala 34:21:@1286.4]
- wire [31:0] StatusCSRTL_TL_TL_2_io_csr_dataIn; // @[StatusCSR.scala 34:21:@1286.4]
- wire [31:0] StatusCSRTL_TL_TL_2_io_value; // @[StatusCSR.scala 34:21:@1286.4]
- wire SimpleCSRTL_TL_TL_8_clock; // @[SimpleCSR.scala 40:21:@1294.4]
- wire SimpleCSRTL_TL_TL_8_reset; // @[SimpleCSR.scala 40:21:@1294.4]
- wire [31:0] SimpleCSRTL_TL_TL_8_io_csr_dataOut; // @[SimpleCSR.scala 40:21:@1294.4]
- wire SimpleCSRTL_TL_TL_8_io_csr_dataWrite; // @[SimpleCSR.scala 40:21:@1294.4]
- wire [31:0] SimpleCSRTL_TL_TL_8_io_csr_dataIn; // @[SimpleCSR.scala 40:21:@1294.4]
- wire [31:0] SimpleCSRTL_TL_TL_8_io_value; // @[SimpleCSR.scala 40:21:@1294.4]
- wire SimpleCSRTL_TL_TL_9_clock; // @[SimpleCSR.scala 40:21:@1301.4]
- wire SimpleCSRTL_TL_TL_9_reset; // @[SimpleCSR.scala 40:21:@1301.4]
- wire [31:0] SimpleCSRTL_TL_TL_9_io_csr_dataOut; // @[SimpleCSR.scala 40:21:@1301.4]
- wire SimpleCSRTL_TL_TL_9_io_csr_dataWrite; // @[SimpleCSR.scala 40:21:@1301.4]
- wire [31:0] SimpleCSRTL_TL_TL_9_io_csr_dataIn; // @[SimpleCSR.scala 40:21:@1301.4]
- wire [31:0] SimpleCSRTL_TL_TL_9_io_value; // @[SimpleCSR.scala 40:21:@1301.4]
- reg [1:0] status; // @[WorkerCSRWrapper.scala 39:23:@1143.4]
- reg [31:0] _RAND_0;
- reg readerSync; // @[WorkerCSRWrapper.scala 41:27:@1145.4]
- reg [31:0] _RAND_1;
- reg readerSyncOld; // @[WorkerCSRWrapper.scala 42:30:@1147.4]
- reg [31:0] _RAND_2;
- reg writerSync; // @[WorkerCSRWrapper.scala 44:27:@1149.4]
- reg [31:0] _RAND_3;
- reg writerSyncOld; // @[WorkerCSRWrapper.scala 45:30:@1151.4]
- reg [31:0] _RAND_4;
- reg readerStart; // @[WorkerCSRWrapper.scala 47:28:@1153.4]
- reg [31:0] _RAND_5;
- reg writerStart; // @[WorkerCSRWrapper.scala 48:28:@1154.4]
- reg [31:0] _RAND_6;
- wire [1:0] _T_207; // @[Cat.scala 30:58:@1191.4]
- wire [31:0] control; // @[WorkerCSRWrapper.scala 50:21:@1155.4 WorkerCSRWrapper.scala 59:11:@1167.4]
- wire _T_208; // @[WorkerCSRWrapper.scala 66:56:@1192.4]
- wire _T_209; // @[WorkerCSRWrapper.scala 66:68:@1193.4]
- wire [1:0] _T_210; // @[Cat.scala 30:58:@1194.4]
- wire [1:0] _T_211; // @[WorkerCSRWrapper.scala 66:44:@1195.4]
- wire [1:0] clear; // @[WorkerCSRWrapper.scala 66:42:@1196.4]
- wire _T_214; // @[WorkerCSRWrapper.scala 68:20:@1198.4]
- wire _T_215; // @[WorkerCSRWrapper.scala 68:35:@1199.4]
- wire _T_216; // @[WorkerCSRWrapper.scala 68:60:@1200.4]
- wire _T_217; // @[WorkerCSRWrapper.scala 68:50:@1201.4]
- wire _T_218; // @[WorkerCSRWrapper.scala 68:75:@1202.4]
- wire _T_219; // @[WorkerCSRWrapper.scala 68:65:@1203.4]
- wire _T_221; // @[WorkerCSRWrapper.scala 69:20:@1205.4]
- wire _T_222; // @[WorkerCSRWrapper.scala 69:35:@1206.4]
- wire _T_223; // @[WorkerCSRWrapper.scala 69:60:@1207.4]
- wire _T_224; // @[WorkerCSRWrapper.scala 69:50:@1208.4]
- wire _T_225; // @[WorkerCSRWrapper.scala 69:75:@1209.4]
- wire _T_226; // @[WorkerCSRWrapper.scala 69:65:@1210.4]
- AddressGeneratorTL_TL_TL addressGeneratorRead ( // @[WorkerCSRWrapper.scala 33:36:@1130.4]
- .clock(addressGeneratorRead_clock),
- .reset(addressGeneratorRead_reset),
- .io_ctl_start(addressGeneratorRead_io_ctl_start),
- .io_ctl_busy(addressGeneratorRead_io_ctl_busy),
- .io_ctl_startAddress(addressGeneratorRead_io_ctl_startAddress),
- .io_ctl_lineLength(addressGeneratorRead_io_ctl_lineLength),
- .io_ctl_lineCount(addressGeneratorRead_io_ctl_lineCount),
- .io_ctl_lineGap(addressGeneratorRead_io_ctl_lineGap),
- .io_xfer_done(addressGeneratorRead_io_xfer_done),
- .io_xfer_address(addressGeneratorRead_io_xfer_address),
- .io_xfer_length(addressGeneratorRead_io_xfer_length),
- .io_xfer_valid(addressGeneratorRead_io_xfer_valid)
- );
- TransferSplitterTL_TL_TL transferSplitterRead ( // @[WorkerCSRWrapper.scala 34:36:@1133.4]
- .io_xferIn_done(transferSplitterRead_io_xferIn_done),
- .io_xferIn_address(transferSplitterRead_io_xferIn_address),
- .io_xferIn_length(transferSplitterRead_io_xferIn_length),
- .io_xferIn_valid(transferSplitterRead_io_xferIn_valid),
- .io_xferOut_done(transferSplitterRead_io_xferOut_done),
- .io_xferOut_address(transferSplitterRead_io_xferOut_address),
- .io_xferOut_length(transferSplitterRead_io_xferOut_length),
- .io_xferOut_valid(transferSplitterRead_io_xferOut_valid)
- );
- AddressGeneratorTL_TL_TL addressGeneratorWrite ( // @[WorkerCSRWrapper.scala 36:37:@1136.4]
- .clock(addressGeneratorWrite_clock),
- .reset(addressGeneratorWrite_reset),
- .io_ctl_start(addressGeneratorWrite_io_ctl_start),
- .io_ctl_busy(addressGeneratorWrite_io_ctl_busy),
- .io_ctl_startAddress(addressGeneratorWrite_io_ctl_startAddress),
- .io_ctl_lineLength(addressGeneratorWrite_io_ctl_lineLength),
- .io_ctl_lineCount(addressGeneratorWrite_io_ctl_lineCount),
- .io_ctl_lineGap(addressGeneratorWrite_io_ctl_lineGap),
- .io_xfer_done(addressGeneratorWrite_io_xfer_done),
- .io_xfer_address(addressGeneratorWrite_io_xfer_address),
- .io_xfer_length(addressGeneratorWrite_io_xfer_length),
- .io_xfer_valid(addressGeneratorWrite_io_xfer_valid)
- );
- TransferSplitterTL_TL_TL_1 transferSplitterWrite ( // @[WorkerCSRWrapper.scala 37:37:@1139.4]
- .clock(transferSplitterWrite_clock),
- .reset(transferSplitterWrite_reset),
- .io_xferIn_done(transferSplitterWrite_io_xferIn_done),
- .io_xferIn_address(transferSplitterWrite_io_xferIn_address),
- .io_xferIn_length(transferSplitterWrite_io_xferIn_length),
- .io_xferIn_valid(transferSplitterWrite_io_xferIn_valid),
- .io_xferOut_done(transferSplitterWrite_io_xferOut_done),
- .io_xferOut_address(transferSplitterWrite_io_xferOut_address),
- .io_xferOut_length(transferSplitterWrite_io_xferOut_length),
- .io_xferOut_valid(transferSplitterWrite_io_xferOut_valid)
- );
- ClearCSRTL_TL_TL ClearCSRTL_TL_TL ( // @[ClearCSR.scala 42:21:@1159.4]
- .clock(ClearCSRTL_TL_TL_clock),
- .reset(ClearCSRTL_TL_TL_reset),
- .io_csr_dataOut(ClearCSRTL_TL_TL_io_csr_dataOut),
- .io_csr_dataWrite(ClearCSRTL_TL_TL_io_csr_dataWrite),
- .io_csr_dataIn(ClearCSRTL_TL_TL_io_csr_dataIn),
- .io_value(ClearCSRTL_TL_TL_io_value),
- .io_clear(ClearCSRTL_TL_TL_io_clear)
- );
- StatusCSRTL_TL_TL StatusCSRTL_TL_TL ( // @[StatusCSR.scala 34:21:@1168.4]
- .clock(StatusCSRTL_TL_TL_clock),
- .io_csr_dataIn(StatusCSRTL_TL_TL_io_csr_dataIn),
- .io_value(StatusCSRTL_TL_TL_io_value)
- );
- InterruptControllerTL_TL_TL InterruptControllerTL_TL_TL ( // @[InterruptController.scala 55:22:@1176.4]
- .clock(InterruptControllerTL_TL_TL_clock),
- .reset(InterruptControllerTL_TL_TL_reset),
- .io_irq_readerDone(InterruptControllerTL_TL_TL_io_irq_readerDone),
- .io_irq_writerDone(InterruptControllerTL_TL_TL_io_irq_writerDone),
- .io_readBusy(InterruptControllerTL_TL_TL_io_readBusy),
- .io_writeBusy(InterruptControllerTL_TL_TL_io_writeBusy),
- .io_imr_dataOut(InterruptControllerTL_TL_TL_io_imr_dataOut),
- .io_imr_dataWrite(InterruptControllerTL_TL_TL_io_imr_dataWrite),
- .io_imr_dataIn(InterruptControllerTL_TL_TL_io_imr_dataIn),
- .io_isr_dataOut(InterruptControllerTL_TL_TL_io_isr_dataOut),
- .io_isr_dataWrite(InterruptControllerTL_TL_TL_io_isr_dataWrite),
- .io_isr_dataIn(InterruptControllerTL_TL_TL_io_isr_dataIn)
- );
- SimpleCSRTL_TL_TL SimpleCSRTL_TL_TL ( // @[SimpleCSR.scala 40:21:@1213.4]
- .clock(SimpleCSRTL_TL_TL_clock),
- .reset(SimpleCSRTL_TL_TL_reset),
- .io_csr_dataOut(SimpleCSRTL_TL_TL_io_csr_dataOut),
- .io_csr_dataWrite(SimpleCSRTL_TL_TL_io_csr_dataWrite),
- .io_csr_dataIn(SimpleCSRTL_TL_TL_io_csr_dataIn),
- .io_value(SimpleCSRTL_TL_TL_io_value)
- );
- SimpleCSRTL_TL_TL SimpleCSRTL_TL_TL_1 ( // @[SimpleCSR.scala 40:21:@1221.4]
- .clock(SimpleCSRTL_TL_TL_1_clock),
- .reset(SimpleCSRTL_TL_TL_1_reset),
- .io_csr_dataOut(SimpleCSRTL_TL_TL_1_io_csr_dataOut),
- .io_csr_dataWrite(SimpleCSRTL_TL_TL_1_io_csr_dataWrite),
- .io_csr_dataIn(SimpleCSRTL_TL_TL_1_io_csr_dataIn),
- .io_value(SimpleCSRTL_TL_TL_1_io_value)
- );
- SimpleCSRTL_TL_TL SimpleCSRTL_TL_TL_2 ( // @[SimpleCSR.scala 40:21:@1229.4]
- .clock(SimpleCSRTL_TL_TL_2_clock),
- .reset(SimpleCSRTL_TL_TL_2_reset),
- .io_csr_dataOut(SimpleCSRTL_TL_TL_2_io_csr_dataOut),
- .io_csr_dataWrite(SimpleCSRTL_TL_TL_2_io_csr_dataWrite),
- .io_csr_dataIn(SimpleCSRTL_TL_TL_2_io_csr_dataIn),
- .io_value(SimpleCSRTL_TL_TL_2_io_value)
- );
- SimpleCSRTL_TL_TL SimpleCSRTL_TL_TL_3 ( // @[SimpleCSR.scala 40:21:@1237.4]
- .clock(SimpleCSRTL_TL_TL_3_clock),
- .reset(SimpleCSRTL_TL_TL_3_reset),
- .io_csr_dataOut(SimpleCSRTL_TL_TL_3_io_csr_dataOut),
- .io_csr_dataWrite(SimpleCSRTL_TL_TL_3_io_csr_dataWrite),
- .io_csr_dataIn(SimpleCSRTL_TL_TL_3_io_csr_dataIn),
- .io_value(SimpleCSRTL_TL_TL_3_io_value)
- );
- SimpleCSRTL_TL_TL SimpleCSRTL_TL_TL_4 ( // @[SimpleCSR.scala 40:21:@1246.4]
- .clock(SimpleCSRTL_TL_TL_4_clock),
- .reset(SimpleCSRTL_TL_TL_4_reset),
- .io_csr_dataOut(SimpleCSRTL_TL_TL_4_io_csr_dataOut),
- .io_csr_dataWrite(SimpleCSRTL_TL_TL_4_io_csr_dataWrite),
- .io_csr_dataIn(SimpleCSRTL_TL_TL_4_io_csr_dataIn),
- .io_value(SimpleCSRTL_TL_TL_4_io_value)
- );
- SimpleCSRTL_TL_TL SimpleCSRTL_TL_TL_5 ( // @[SimpleCSR.scala 40:21:@1254.4]
- .clock(SimpleCSRTL_TL_TL_5_clock),
- .reset(SimpleCSRTL_TL_TL_5_reset),
- .io_csr_dataOut(SimpleCSRTL_TL_TL_5_io_csr_dataOut),
- .io_csr_dataWrite(SimpleCSRTL_TL_TL_5_io_csr_dataWrite),
- .io_csr_dataIn(SimpleCSRTL_TL_TL_5_io_csr_dataIn),
- .io_value(SimpleCSRTL_TL_TL_5_io_value)
- );
- SimpleCSRTL_TL_TL SimpleCSRTL_TL_TL_6 ( // @[SimpleCSR.scala 40:21:@1262.4]
- .clock(SimpleCSRTL_TL_TL_6_clock),
- .reset(SimpleCSRTL_TL_TL_6_reset),
- .io_csr_dataOut(SimpleCSRTL_TL_TL_6_io_csr_dataOut),
- .io_csr_dataWrite(SimpleCSRTL_TL_TL_6_io_csr_dataWrite),
- .io_csr_dataIn(SimpleCSRTL_TL_TL_6_io_csr_dataIn),
- .io_value(SimpleCSRTL_TL_TL_6_io_value)
- );
- SimpleCSRTL_TL_TL SimpleCSRTL_TL_TL_7 ( // @[SimpleCSR.scala 40:21:@1270.4]
- .clock(SimpleCSRTL_TL_TL_7_clock),
- .reset(SimpleCSRTL_TL_TL_7_reset),
- .io_csr_dataOut(SimpleCSRTL_TL_TL_7_io_csr_dataOut),
- .io_csr_dataWrite(SimpleCSRTL_TL_TL_7_io_csr_dataWrite),
- .io_csr_dataIn(SimpleCSRTL_TL_TL_7_io_csr_dataIn),
- .io_value(SimpleCSRTL_TL_TL_7_io_value)
- );
- StatusCSRTL_TL_TL StatusCSRTL_TL_TL_1 ( // @[StatusCSR.scala 34:21:@1278.4]
- .clock(StatusCSRTL_TL_TL_1_clock),
- .io_csr_dataIn(StatusCSRTL_TL_TL_1_io_csr_dataIn),
- .io_value(StatusCSRTL_TL_TL_1_io_value)
- );
- StatusCSRTL_TL_TL StatusCSRTL_TL_TL_2 ( // @[StatusCSR.scala 34:21:@1286.4]
- .clock(StatusCSRTL_TL_TL_2_clock),
- .io_csr_dataIn(StatusCSRTL_TL_TL_2_io_csr_dataIn),
- .io_value(StatusCSRTL_TL_TL_2_io_value)
- );
- SimpleCSRTL_TL_TL SimpleCSRTL_TL_TL_8 ( // @[SimpleCSR.scala 40:21:@1294.4]
- .clock(SimpleCSRTL_TL_TL_8_clock),
- .reset(SimpleCSRTL_TL_TL_8_reset),
- .io_csr_dataOut(SimpleCSRTL_TL_TL_8_io_csr_dataOut),
- .io_csr_dataWrite(SimpleCSRTL_TL_TL_8_io_csr_dataWrite),
- .io_csr_dataIn(SimpleCSRTL_TL_TL_8_io_csr_dataIn),
- .io_value(SimpleCSRTL_TL_TL_8_io_value)
- );
- SimpleCSRTL_TL_TL SimpleCSRTL_TL_TL_9 ( // @[SimpleCSR.scala 40:21:@1301.4]
- .clock(SimpleCSRTL_TL_TL_9_clock),
- .reset(SimpleCSRTL_TL_TL_9_reset),
- .io_csr_dataOut(SimpleCSRTL_TL_TL_9_io_csr_dataOut),
- .io_csr_dataWrite(SimpleCSRTL_TL_TL_9_io_csr_dataWrite),
- .io_csr_dataIn(SimpleCSRTL_TL_TL_9_io_csr_dataIn),
- .io_value(SimpleCSRTL_TL_TL_9_io_value)
- );
- assign _T_207 = {readerStart,writerStart}; // @[Cat.scala 30:58:@1191.4]
- assign control = ClearCSRTL_TL_TL_io_value; // @[WorkerCSRWrapper.scala 50:21:@1155.4 WorkerCSRWrapper.scala 59:11:@1167.4]
- assign _T_208 = control[5]; // @[WorkerCSRWrapper.scala 66:56:@1192.4]
- assign _T_209 = control[4]; // @[WorkerCSRWrapper.scala 66:68:@1193.4]
- assign _T_210 = {_T_208,_T_209}; // @[Cat.scala 30:58:@1194.4]
- assign _T_211 = ~ _T_210; // @[WorkerCSRWrapper.scala 66:44:@1195.4]
- assign clear = _T_207 & _T_211; // @[WorkerCSRWrapper.scala 66:42:@1196.4]
- assign _T_214 = readerSyncOld == 1'h0; // @[WorkerCSRWrapper.scala 68:20:@1198.4]
- assign _T_215 = _T_214 & readerSync; // @[WorkerCSRWrapper.scala 68:35:@1199.4]
- assign _T_216 = control[3]; // @[WorkerCSRWrapper.scala 68:60:@1200.4]
- assign _T_217 = _T_215 | _T_216; // @[WorkerCSRWrapper.scala 68:50:@1201.4]
- assign _T_218 = control[1]; // @[WorkerCSRWrapper.scala 68:75:@1202.4]
- assign _T_219 = _T_217 & _T_218; // @[WorkerCSRWrapper.scala 68:65:@1203.4]
- assign _T_221 = writerSyncOld == 1'h0; // @[WorkerCSRWrapper.scala 69:20:@1205.4]
- assign _T_222 = _T_221 & writerSync; // @[WorkerCSRWrapper.scala 69:35:@1206.4]
- assign _T_223 = control[2]; // @[WorkerCSRWrapper.scala 69:60:@1207.4]
- assign _T_224 = _T_222 | _T_223; // @[WorkerCSRWrapper.scala 69:50:@1208.4]
- assign _T_225 = control[0]; // @[WorkerCSRWrapper.scala 69:75:@1209.4]
- assign _T_226 = _T_224 & _T_225; // @[WorkerCSRWrapper.scala 69:65:@1210.4]
- assign io_csr_0_dataIn = ClearCSRTL_TL_TL_io_csr_dataIn; // @[ClearCSR.scala 46:16:@1163.4]
- assign io_csr_1_dataIn = StatusCSRTL_TL_TL_io_csr_dataIn; // @[StatusCSR.scala 36:16:@1171.4]
- assign io_csr_2_dataIn = InterruptControllerTL_TL_TL_io_imr_dataIn; // @[InterruptController.scala 60:17:@1181.4]
- assign io_csr_3_dataIn = InterruptControllerTL_TL_TL_io_isr_dataIn; // @[InterruptController.scala 61:17:@1185.4]
- assign io_csr_4_dataIn = SimpleCSRTL_TL_TL_io_csr_dataIn; // @[SimpleCSR.scala 42:16:@1216.4]
- assign io_csr_5_dataIn = SimpleCSRTL_TL_TL_1_io_csr_dataIn; // @[SimpleCSR.scala 42:16:@1224.4]
- assign io_csr_6_dataIn = SimpleCSRTL_TL_TL_2_io_csr_dataIn; // @[SimpleCSR.scala 42:16:@1232.4]
- assign io_csr_7_dataIn = SimpleCSRTL_TL_TL_3_io_csr_dataIn; // @[SimpleCSR.scala 42:16:@1240.4]
- assign io_csr_8_dataIn = SimpleCSRTL_TL_TL_4_io_csr_dataIn; // @[SimpleCSR.scala 42:16:@1249.4]
- assign io_csr_9_dataIn = SimpleCSRTL_TL_TL_5_io_csr_dataIn; // @[SimpleCSR.scala 42:16:@1257.4]
- assign io_csr_10_dataIn = SimpleCSRTL_TL_TL_6_io_csr_dataIn; // @[SimpleCSR.scala 42:16:@1265.4]
- assign io_csr_11_dataIn = SimpleCSRTL_TL_TL_7_io_csr_dataIn; // @[SimpleCSR.scala 42:16:@1273.4]
- assign io_csr_12_dataIn = StatusCSRTL_TL_TL_1_io_csr_dataIn; // @[StatusCSR.scala 36:16:@1281.4]
- assign io_csr_13_dataIn = StatusCSRTL_TL_TL_2_io_csr_dataIn; // @[StatusCSR.scala 36:16:@1289.4]
- assign io_csr_14_dataIn = SimpleCSRTL_TL_TL_8_io_csr_dataIn; // @[SimpleCSR.scala 42:16:@1297.4]
- assign io_csr_15_dataIn = SimpleCSRTL_TL_TL_9_io_csr_dataIn; // @[SimpleCSR.scala 42:16:@1304.4]
- assign io_irq_readerDone = InterruptControllerTL_TL_TL_io_irq_readerDone; // @[WorkerCSRWrapper.scala 63:10:@1190.4]
- assign io_irq_writerDone = InterruptControllerTL_TL_TL_io_irq_writerDone; // @[WorkerCSRWrapper.scala 63:10:@1189.4]
- assign io_xferRead_address = transferSplitterRead_io_xferOut_address; // @[WorkerCSRWrapper.scala 91:15:@1316.4]
- assign io_xferRead_length = transferSplitterRead_io_xferOut_length; // @[WorkerCSRWrapper.scala 91:15:@1315.4]
- assign io_xferRead_valid = transferSplitterRead_io_xferOut_valid; // @[WorkerCSRWrapper.scala 91:15:@1314.4]
- assign io_xferWrite_address = transferSplitterWrite_io_xferOut_address; // @[WorkerCSRWrapper.scala 94:16:@1326.4]
- assign io_xferWrite_length = transferSplitterWrite_io_xferOut_length; // @[WorkerCSRWrapper.scala 94:16:@1325.4]
- assign io_xferWrite_valid = transferSplitterWrite_io_xferOut_valid; // @[WorkerCSRWrapper.scala 94:16:@1324.4]
- assign addressGeneratorRead_clock = clock; // @[:@1131.4]
- assign addressGeneratorRead_reset = reset; // @[:@1132.4]
- assign addressGeneratorRead_io_ctl_start = readerStart; // @[WorkerCSRWrapper.scala 71:37:@1212.4]
- assign addressGeneratorRead_io_ctl_startAddress = SimpleCSRTL_TL_TL_io_value; // @[WorkerCSRWrapper.scala 72:44:@1220.4]
- assign addressGeneratorRead_io_ctl_lineLength = SimpleCSRTL_TL_TL_1_io_value; // @[WorkerCSRWrapper.scala 73:42:@1228.4]
- assign addressGeneratorRead_io_ctl_lineCount = SimpleCSRTL_TL_TL_2_io_value; // @[WorkerCSRWrapper.scala 74:41:@1236.4]
- assign addressGeneratorRead_io_ctl_lineGap = SimpleCSRTL_TL_TL_3_io_value; // @[WorkerCSRWrapper.scala 75:39:@1244.4]
- assign addressGeneratorRead_io_xfer_done = transferSplitterRead_io_xferIn_done; // @[WorkerCSRWrapper.scala 90:34:@1312.4]
- assign transferSplitterRead_io_xferIn_address = addressGeneratorRead_io_xfer_address; // @[WorkerCSRWrapper.scala 90:34:@1311.4]
- assign transferSplitterRead_io_xferIn_length = addressGeneratorRead_io_xfer_length; // @[WorkerCSRWrapper.scala 90:34:@1310.4]
- assign transferSplitterRead_io_xferIn_valid = addressGeneratorRead_io_xfer_valid; // @[WorkerCSRWrapper.scala 90:34:@1309.4]
- assign transferSplitterRead_io_xferOut_done = io_xferRead_done; // @[WorkerCSRWrapper.scala 91:15:@1317.4]
- assign addressGeneratorWrite_clock = clock; // @[:@1137.4]
- assign addressGeneratorWrite_reset = reset; // @[:@1138.4]
- assign addressGeneratorWrite_io_ctl_start = writerStart; // @[WorkerCSRWrapper.scala 77:38:@1245.4]
- assign addressGeneratorWrite_io_ctl_startAddress = SimpleCSRTL_TL_TL_4_io_value; // @[WorkerCSRWrapper.scala 78:45:@1253.4]
- assign addressGeneratorWrite_io_ctl_lineLength = SimpleCSRTL_TL_TL_5_io_value; // @[WorkerCSRWrapper.scala 79:43:@1261.4]
- assign addressGeneratorWrite_io_ctl_lineCount = SimpleCSRTL_TL_TL_6_io_value; // @[WorkerCSRWrapper.scala 80:42:@1269.4]
- assign addressGeneratorWrite_io_ctl_lineGap = SimpleCSRTL_TL_TL_7_io_value; // @[WorkerCSRWrapper.scala 81:40:@1277.4]
- assign addressGeneratorWrite_io_xfer_done = transferSplitterWrite_io_xferIn_done; // @[WorkerCSRWrapper.scala 93:35:@1322.4]
- assign transferSplitterWrite_clock = clock; // @[:@1140.4]
- assign transferSplitterWrite_reset = reset; // @[:@1141.4]
- assign transferSplitterWrite_io_xferIn_address = addressGeneratorWrite_io_xfer_address; // @[WorkerCSRWrapper.scala 93:35:@1321.4]
- assign transferSplitterWrite_io_xferIn_length = addressGeneratorWrite_io_xfer_length; // @[WorkerCSRWrapper.scala 93:35:@1320.4]
- assign transferSplitterWrite_io_xferIn_valid = addressGeneratorWrite_io_xfer_valid; // @[WorkerCSRWrapper.scala 93:35:@1319.4]
- assign transferSplitterWrite_io_xferOut_done = io_xferWrite_done; // @[WorkerCSRWrapper.scala 94:16:@1327.4]
- assign ClearCSRTL_TL_TL_clock = clock; // @[:@1160.4]
- assign ClearCSRTL_TL_TL_reset = reset; // @[:@1161.4]
- assign ClearCSRTL_TL_TL_io_csr_dataOut = io_csr_0_dataOut; // @[ClearCSR.scala 46:16:@1165.4]
- assign ClearCSRTL_TL_TL_io_csr_dataWrite = io_csr_0_dataWrite; // @[ClearCSR.scala 46:16:@1164.4]
- assign ClearCSRTL_TL_TL_io_clear = {{30'd0}, clear}; // @[ClearCSR.scala 44:18:@1162.4]
- assign StatusCSRTL_TL_TL_clock = clock; // @[:@1169.4]
- assign StatusCSRTL_TL_TL_io_value = {{30'd0}, status}; // @[StatusCSR.scala 38:18:@1175.4]
- assign InterruptControllerTL_TL_TL_clock = clock; // @[:@1177.4]
- assign InterruptControllerTL_TL_TL_reset = reset; // @[:@1178.4]
- assign InterruptControllerTL_TL_TL_io_readBusy = addressGeneratorRead_io_ctl_busy; // @[InterruptController.scala 57:22:@1179.4]
- assign InterruptControllerTL_TL_TL_io_writeBusy = addressGeneratorWrite_io_ctl_busy; // @[InterruptController.scala 58:23:@1180.4]
- assign InterruptControllerTL_TL_TL_io_imr_dataOut = io_csr_2_dataOut; // @[InterruptController.scala 60:17:@1183.4]
- assign InterruptControllerTL_TL_TL_io_imr_dataWrite = io_csr_2_dataWrite; // @[InterruptController.scala 60:17:@1182.4]
- assign InterruptControllerTL_TL_TL_io_isr_dataOut = io_csr_3_dataOut; // @[InterruptController.scala 61:17:@1187.4]
- assign InterruptControllerTL_TL_TL_io_isr_dataWrite = io_csr_3_dataWrite; // @[InterruptController.scala 61:17:@1186.4]
- assign SimpleCSRTL_TL_TL_clock = clock; // @[:@1214.4]
- assign SimpleCSRTL_TL_TL_reset = reset; // @[:@1215.4]
- assign SimpleCSRTL_TL_TL_io_csr_dataOut = io_csr_4_dataOut; // @[SimpleCSR.scala 42:16:@1218.4]
- assign SimpleCSRTL_TL_TL_io_csr_dataWrite = io_csr_4_dataWrite; // @[SimpleCSR.scala 42:16:@1217.4]
- assign SimpleCSRTL_TL_TL_1_clock = clock; // @[:@1222.4]
- assign SimpleCSRTL_TL_TL_1_reset = reset; // @[:@1223.4]
- assign SimpleCSRTL_TL_TL_1_io_csr_dataOut = io_csr_5_dataOut; // @[SimpleCSR.scala 42:16:@1226.4]
- assign SimpleCSRTL_TL_TL_1_io_csr_dataWrite = io_csr_5_dataWrite; // @[SimpleCSR.scala 42:16:@1225.4]
- assign SimpleCSRTL_TL_TL_2_clock = clock; // @[:@1230.4]
- assign SimpleCSRTL_TL_TL_2_reset = reset; // @[:@1231.4]
- assign SimpleCSRTL_TL_TL_2_io_csr_dataOut = io_csr_6_dataOut; // @[SimpleCSR.scala 42:16:@1234.4]
- assign SimpleCSRTL_TL_TL_2_io_csr_dataWrite = io_csr_6_dataWrite; // @[SimpleCSR.scala 42:16:@1233.4]
- assign SimpleCSRTL_TL_TL_3_clock = clock; // @[:@1238.4]
- assign SimpleCSRTL_TL_TL_3_reset = reset; // @[:@1239.4]
- assign SimpleCSRTL_TL_TL_3_io_csr_dataOut = io_csr_7_dataOut; // @[SimpleCSR.scala 42:16:@1242.4]
- assign SimpleCSRTL_TL_TL_3_io_csr_dataWrite = io_csr_7_dataWrite; // @[SimpleCSR.scala 42:16:@1241.4]
- assign SimpleCSRTL_TL_TL_4_clock = clock; // @[:@1247.4]
- assign SimpleCSRTL_TL_TL_4_reset = reset; // @[:@1248.4]
- assign SimpleCSRTL_TL_TL_4_io_csr_dataOut = io_csr_8_dataOut; // @[SimpleCSR.scala 42:16:@1251.4]
- assign SimpleCSRTL_TL_TL_4_io_csr_dataWrite = io_csr_8_dataWrite; // @[SimpleCSR.scala 42:16:@1250.4]
- assign SimpleCSRTL_TL_TL_5_clock = clock; // @[:@1255.4]
- assign SimpleCSRTL_TL_TL_5_reset = reset; // @[:@1256.4]
- assign SimpleCSRTL_TL_TL_5_io_csr_dataOut = io_csr_9_dataOut; // @[SimpleCSR.scala 42:16:@1259.4]
- assign SimpleCSRTL_TL_TL_5_io_csr_dataWrite = io_csr_9_dataWrite; // @[SimpleCSR.scala 42:16:@1258.4]
- assign SimpleCSRTL_TL_TL_6_clock = clock; // @[:@1263.4]
- assign SimpleCSRTL_TL_TL_6_reset = reset; // @[:@1264.4]
- assign SimpleCSRTL_TL_TL_6_io_csr_dataOut = io_csr_10_dataOut; // @[SimpleCSR.scala 42:16:@1267.4]
- assign SimpleCSRTL_TL_TL_6_io_csr_dataWrite = io_csr_10_dataWrite; // @[SimpleCSR.scala 42:16:@1266.4]
- assign SimpleCSRTL_TL_TL_7_clock = clock; // @[:@1271.4]
- assign SimpleCSRTL_TL_TL_7_reset = reset; // @[:@1272.4]
- assign SimpleCSRTL_TL_TL_7_io_csr_dataOut = io_csr_11_dataOut; // @[SimpleCSR.scala 42:16:@1275.4]
- assign SimpleCSRTL_TL_TL_7_io_csr_dataWrite = io_csr_11_dataWrite; // @[SimpleCSR.scala 42:16:@1274.4]
- assign StatusCSRTL_TL_TL_1_clock = clock; // @[:@1279.4]
- assign StatusCSRTL_TL_TL_1_io_value = 32'h0; // @[StatusCSR.scala 38:18:@1285.4]
- assign StatusCSRTL_TL_TL_2_clock = clock; // @[:@1287.4]
- assign StatusCSRTL_TL_TL_2_io_value = 32'h555; // @[StatusCSR.scala 38:18:@1293.4]
- assign SimpleCSRTL_TL_TL_8_clock = clock; // @[:@1295.4]
- assign SimpleCSRTL_TL_TL_8_reset = reset; // @[:@1296.4]
- assign SimpleCSRTL_TL_TL_8_io_csr_dataOut = io_csr_14_dataOut; // @[SimpleCSR.scala 42:16:@1299.4]
- assign SimpleCSRTL_TL_TL_8_io_csr_dataWrite = io_csr_14_dataWrite; // @[SimpleCSR.scala 42:16:@1298.4]
- assign SimpleCSRTL_TL_TL_9_clock = clock; // @[:@1302.4]
- assign SimpleCSRTL_TL_TL_9_reset = reset; // @[:@1303.4]
- assign SimpleCSRTL_TL_TL_9_io_csr_dataOut = io_csr_15_dataOut; // @[SimpleCSR.scala 42:16:@1306.4]
- assign SimpleCSRTL_TL_TL_9_io_csr_dataWrite = io_csr_15_dataWrite; // @[SimpleCSR.scala 42:16:@1305.4]
-`ifdef RANDOMIZE_GARBAGE_ASSIGN
-`define RANDOMIZE
-`endif
-`ifdef RANDOMIZE_INVALID_ASSIGN
-`define RANDOMIZE
-`endif
-`ifdef RANDOMIZE_REG_INIT
-`define RANDOMIZE
-`endif
-`ifdef RANDOMIZE_MEM_INIT
-`define RANDOMIZE
-`endif
-`ifndef RANDOM
-`define RANDOM $random
-`endif
-`ifdef RANDOMIZE
- integer initvar;
- initial begin
- `ifdef INIT_RANDOM
- `INIT_RANDOM
- `endif
- `ifndef VERILATOR
- #0.002 begin end
- `endif
- `ifdef RANDOMIZE_REG_INIT
- _RAND_0 = {1{`RANDOM}};
- status = _RAND_0[1:0];
- `endif // RANDOMIZE_REG_INIT
- `ifdef RANDOMIZE_REG_INIT
- _RAND_1 = {1{`RANDOM}};
- readerSync = _RAND_1[0:0];
- `endif // RANDOMIZE_REG_INIT
- `ifdef RANDOMIZE_REG_INIT
- _RAND_2 = {1{`RANDOM}};
- readerSyncOld = _RAND_2[0:0];
- `endif // RANDOMIZE_REG_INIT
- `ifdef RANDOMIZE_REG_INIT
- _RAND_3 = {1{`RANDOM}};
- writerSync = _RAND_3[0:0];
- `endif // RANDOMIZE_REG_INIT
- `ifdef RANDOMIZE_REG_INIT
- _RAND_4 = {1{`RANDOM}};
- writerSyncOld = _RAND_4[0:0];
- `endif // RANDOMIZE_REG_INIT
- `ifdef RANDOMIZE_REG_INIT
- _RAND_5 = {1{`RANDOM}};
- readerStart = _RAND_5[0:0];
- `endif // RANDOMIZE_REG_INIT
- `ifdef RANDOMIZE_REG_INIT
- _RAND_6 = {1{`RANDOM}};
- writerStart = _RAND_6[0:0];
- `endif // RANDOMIZE_REG_INIT
- end
-`endif // RANDOMIZE
- always @(posedge clock) begin
- status <= {addressGeneratorRead_io_ctl_busy,addressGeneratorWrite_io_ctl_busy};
- readerSync <= io_sync_readerSync;
- readerSyncOld <= readerSync;
- writerSync <= io_sync_writerSync;
- writerSyncOld <= writerSync;
- if (reset) begin
- readerStart <= 1'h0;
- end else begin
- readerStart <= _T_219;
- end
- if (reset) begin
- writerStart <= 1'h0;
- end else begin
- writerStart <= _T_226;
- end
- end
-endmodule
-module Queue( // @[:@1329.2]
- input clock, // @[:@1330.4]
- input reset, // @[:@1331.4]
- output io_enq_ready, // @[:@1332.4]
- input io_enq_valid, // @[:@1332.4]
- input [31:0] io_enq_bits, // @[:@1332.4]
- input io_deq_ready, // @[:@1332.4]
- output io_deq_valid, // @[:@1332.4]
- output [31:0] io_deq_bits // @[:@1332.4]
-);
- reg [31:0] ram [0:511]; // @[Decoupled.scala 215:24:@1334.4]
- reg [31:0] _RAND_0;
- wire [31:0] ram__T_63_data; // @[Decoupled.scala 215:24:@1334.4]
- wire [8:0] ram__T_63_addr; // @[Decoupled.scala 215:24:@1334.4]
- wire [31:0] ram__T_49_data; // @[Decoupled.scala 215:24:@1334.4]
- wire [8:0] ram__T_49_addr; // @[Decoupled.scala 215:24:@1334.4]
- wire ram__T_49_mask; // @[Decoupled.scala 215:24:@1334.4]
- wire ram__T_49_en; // @[Decoupled.scala 215:24:@1334.4]
- reg [8:0] value; // @[Counter.scala 26:33:@1335.4]
- reg [31:0] _RAND_1;
- reg [8:0] value_1; // @[Counter.scala 26:33:@1336.4]
- reg [31:0] _RAND_2;
- reg maybe_full; // @[Decoupled.scala 218:35:@1337.4]
- reg [31:0] _RAND_3;
- wire _T_41; // @[Decoupled.scala 220:41:@1338.4]
- wire _T_43; // @[Decoupled.scala 221:36:@1339.4]
- wire empty; // @[Decoupled.scala 221:33:@1340.4]
- wire _T_44; // @[Decoupled.scala 222:32:@1341.4]
- wire do_enq; // @[Decoupled.scala 37:37:@1342.4]
- wire do_deq; // @[Decoupled.scala 37:37:@1345.4]
- wire [9:0] _T_52; // @[Counter.scala 35:22:@1352.6]
- wire [8:0] _T_53; // @[Counter.scala 35:22:@1353.6]
- wire [8:0] _GEN_5; // @[Decoupled.scala 226:17:@1348.4]
- wire [9:0] _T_56; // @[Counter.scala 35:22:@1358.6]
- wire [8:0] _T_57; // @[Counter.scala 35:22:@1359.6]
- wire [8:0] _GEN_6; // @[Decoupled.scala 230:17:@1356.4]
- wire _T_58; // @[Decoupled.scala 233:16:@1362.4]
- wire _GEN_7; // @[Decoupled.scala 233:28:@1363.4]
- assign ram__T_63_addr = value_1;
- assign ram__T_63_data = ram[ram__T_63_addr]; // @[Decoupled.scala 215:24:@1334.4]
- assign ram__T_49_data = io_enq_bits;
- assign ram__T_49_addr = value;
- assign ram__T_49_mask = 1'h1;
- assign ram__T_49_en = io_enq_ready & io_enq_valid;
- assign _T_41 = value == value_1; // @[Decoupled.scala 220:41:@1338.4]
- assign _T_43 = maybe_full == 1'h0; // @[Decoupled.scala 221:36:@1339.4]
- assign empty = _T_41 & _T_43; // @[Decoupled.scala 221:33:@1340.4]
- assign _T_44 = _T_41 & maybe_full; // @[Decoupled.scala 222:32:@1341.4]
- assign do_enq = io_enq_ready & io_enq_valid; // @[Decoupled.scala 37:37:@1342.4]
- assign do_deq = io_deq_ready & io_deq_valid; // @[Decoupled.scala 37:37:@1345.4]
- assign _T_52 = value + 9'h1; // @[Counter.scala 35:22:@1352.6]
- assign _T_53 = value + 9'h1; // @[Counter.scala 35:22:@1353.6]
- assign _GEN_5 = do_enq ? _T_53 : value; // @[Decoupled.scala 226:17:@1348.4]
- assign _T_56 = value_1 + 9'h1; // @[Counter.scala 35:22:@1358.6]
- assign _T_57 = value_1 + 9'h1; // @[Counter.scala 35:22:@1359.6]
- assign _GEN_6 = do_deq ? _T_57 : value_1; // @[Decoupled.scala 230:17:@1356.4]
- assign _T_58 = do_enq != do_deq; // @[Decoupled.scala 233:16:@1362.4]
- assign _GEN_7 = _T_58 ? do_enq : maybe_full; // @[Decoupled.scala 233:28:@1363.4]
- assign io_enq_ready = _T_44 == 1'h0; // @[Decoupled.scala 238:16:@1369.4]
- assign io_deq_valid = empty == 1'h0; // @[Decoupled.scala 237:16:@1367.4]
- assign io_deq_bits = ram__T_63_data; // @[Decoupled.scala 239:15:@1371.4]
-`ifdef RANDOMIZE_GARBAGE_ASSIGN
-`define RANDOMIZE
-`endif
-`ifdef RANDOMIZE_INVALID_ASSIGN
-`define RANDOMIZE
-`endif
-`ifdef RANDOMIZE_REG_INIT
-`define RANDOMIZE
-`endif
-`ifdef RANDOMIZE_MEM_INIT
-`define RANDOMIZE
-`endif
-`ifndef RANDOM
-`define RANDOM $random
-`endif
-`ifdef RANDOMIZE
- integer initvar;
- initial begin
- `ifdef INIT_RANDOM
- `INIT_RANDOM
- `endif
- `ifndef VERILATOR
- #0.002 begin end
- `endif
- _RAND_0 = {1{`RANDOM}};
- `ifdef RANDOMIZE_MEM_INIT
- for (initvar = 0; initvar < 512; initvar = initvar+1)
- ram[initvar] = _RAND_0[31:0];
- `endif // RANDOMIZE_MEM_INIT
- `ifdef RANDOMIZE_REG_INIT
- _RAND_1 = {1{`RANDOM}};
- value = _RAND_1[8:0];
- `endif // RANDOMIZE_REG_INIT
- `ifdef RANDOMIZE_REG_INIT
- _RAND_2 = {1{`RANDOM}};
- value_1 = _RAND_2[8:0];
- `endif // RANDOMIZE_REG_INIT
- `ifdef RANDOMIZE_REG_INIT
- _RAND_3 = {1{`RANDOM}};
- maybe_full = _RAND_3[0:0];
- `endif // RANDOMIZE_REG_INIT
- end
-`endif // RANDOMIZE
- always @(posedge clock) begin
- if(ram__T_49_en & ram__T_49_mask) begin
- ram[ram__T_49_addr] <= ram__T_49_data; // @[Decoupled.scala 215:24:@1334.4]
- end
- if (reset) begin
- value <= 9'h0;
- end else begin
- if (do_enq) begin
- value <= _T_53;
- end
- end
- if (reset) begin
- value_1 <= 9'h0;
- end else begin
- if (do_deq) begin
- value_1 <= _T_57;
- end
- end
- if (reset) begin
- maybe_full <= 1'h0;
- end else begin
- if (_T_58) begin
- maybe_full <= do_enq;
- end
- end
- end
-endmodule
-module DMATopTL_TL_TL( // @[:@1380.2]
- input clock, // @[:@1381.4]
- input reset, // @[:@1382.4]
- input [2:0] io_control_a_opcode, // @[:@1383.4]
- input [2:0] io_control_a_param, // @[:@1383.4]
- input [1:0] io_control_a_size, // @[:@1383.4]
- input [9:0] io_control_a_source, // @[:@1383.4]
- input [31:0] io_control_a_address, // @[:@1383.4]
- input [3:0] io_control_a_mask, // @[:@1383.4]
- input [31:0] io_control_a_data, // @[:@1383.4]
- input io_control_a_corrupt, // @[:@1383.4]
- input io_control_a_valid, // @[:@1383.4]
- output io_control_a_ready, // @[:@1383.4]
- output [2:0] io_control_d_opcode, // @[:@1383.4]
- output [2:0] io_control_d_param, // @[:@1383.4]
- output [1:0] io_control_d_size, // @[:@1383.4]
- output [9:0] io_control_d_source, // @[:@1383.4]
- output io_control_d_sink, // @[:@1383.4]
- output io_control_d_denied, // @[:@1383.4]
- output [31:0] io_control_d_data, // @[:@1383.4]
- output io_control_d_corrupt, // @[:@1383.4]
- output io_control_d_valid, // @[:@1383.4]
- input io_control_d_ready, // @[:@1383.4]
- output [2:0] io_read_a_opcode, // @[:@1383.4]
- output [2:0] io_read_a_param, // @[:@1383.4]
- output [1:0] io_read_a_size, // @[:@1383.4]
- output [9:0] io_read_a_source, // @[:@1383.4]
- output [31:0] io_read_a_address, // @[:@1383.4]
- output [3:0] io_read_a_mask, // @[:@1383.4]
- output [31:0] io_read_a_data, // @[:@1383.4]
- output io_read_a_corrupt, // @[:@1383.4]
- output io_read_a_valid, // @[:@1383.4]
- input io_read_a_ready, // @[:@1383.4]
- input [2:0] io_read_d_opcode, // @[:@1383.4]
- input [2:0] io_read_d_param, // @[:@1383.4]
- input [1:0] io_read_d_size, // @[:@1383.4]
- input [9:0] io_read_d_source, // @[:@1383.4]
- input io_read_d_sink, // @[:@1383.4]
- input io_read_d_denied, // @[:@1383.4]
- input [31:0] io_read_d_data, // @[:@1383.4]
- input io_read_d_corrupt, // @[:@1383.4]
- input io_read_d_valid, // @[:@1383.4]
- output io_read_d_ready, // @[:@1383.4]
- output [2:0] io_write_a_opcode, // @[:@1383.4]
- output [2:0] io_write_a_param, // @[:@1383.4]
- output [1:0] io_write_a_size, // @[:@1383.4]
- output [9:0] io_write_a_source, // @[:@1383.4]
- output [31:0] io_write_a_address, // @[:@1383.4]
- output [3:0] io_write_a_mask, // @[:@1383.4]
- output [31:0] io_write_a_data, // @[:@1383.4]
- output io_write_a_corrupt, // @[:@1383.4]
- output io_write_a_valid, // @[:@1383.4]
- input io_write_a_ready, // @[:@1383.4]
- input [2:0] io_write_d_opcode, // @[:@1383.4]
- input [2:0] io_write_d_param, // @[:@1383.4]
- input [1:0] io_write_d_size, // @[:@1383.4]
- input [9:0] io_write_d_source, // @[:@1383.4]
- input io_write_d_sink, // @[:@1383.4]
- input io_write_d_denied, // @[:@1383.4]
- input [31:0] io_write_d_data, // @[:@1383.4]
- input io_write_d_corrupt, // @[:@1383.4]
- input io_write_d_valid, // @[:@1383.4]
- output io_write_d_ready, // @[:@1383.4]
- output io_irq_readerDone, // @[:@1383.4]
- output io_irq_writerDone, // @[:@1383.4]
- input io_sync_readerSync, // @[:@1383.4]
- input io_sync_writerSync // @[:@1383.4]
-);
- wire csrFrontend_clock; // @[DMATop.scala 38:27:@1385.4]
- wire csrFrontend_reset; // @[DMATop.scala 38:27:@1385.4]
- wire [2:0] csrFrontend_io_ctl_a_opcode; // @[DMATop.scala 38:27:@1385.4]
- wire [1:0] csrFrontend_io_ctl_a_size; // @[DMATop.scala 38:27:@1385.4]
- wire [9:0] csrFrontend_io_ctl_a_source; // @[DMATop.scala 38:27:@1385.4]
- wire [31:0] csrFrontend_io_ctl_a_address; // @[DMATop.scala 38:27:@1385.4]
- wire [31:0] csrFrontend_io_ctl_a_data; // @[DMATop.scala 38:27:@1385.4]
- wire csrFrontend_io_ctl_a_valid; // @[DMATop.scala 38:27:@1385.4]
- wire csrFrontend_io_ctl_a_ready; // @[DMATop.scala 38:27:@1385.4]
- wire [2:0] csrFrontend_io_ctl_d_opcode; // @[DMATop.scala 38:27:@1385.4]
- wire [1:0] csrFrontend_io_ctl_d_size; // @[DMATop.scala 38:27:@1385.4]
- wire [9:0] csrFrontend_io_ctl_d_source; // @[DMATop.scala 38:27:@1385.4]
- wire [31:0] csrFrontend_io_ctl_d_data; // @[DMATop.scala 38:27:@1385.4]
- wire csrFrontend_io_ctl_d_valid; // @[DMATop.scala 38:27:@1385.4]
- wire csrFrontend_io_ctl_d_ready; // @[DMATop.scala 38:27:@1385.4]
- wire [3:0] csrFrontend_io_bus_addr; // @[DMATop.scala 38:27:@1385.4]
- wire [31:0] csrFrontend_io_bus_dataOut; // @[DMATop.scala 38:27:@1385.4]
- wire [31:0] csrFrontend_io_bus_dataIn; // @[DMATop.scala 38:27:@1385.4]
- wire csrFrontend_io_bus_write; // @[DMATop.scala 38:27:@1385.4]
- wire csrFrontend_io_bus_read; // @[DMATop.scala 38:27:@1385.4]
- wire readerFrontend_clock; // @[DMATop.scala 40:30:@1388.4]
- wire readerFrontend_reset; // @[DMATop.scala 40:30:@1388.4]
- wire [31:0] readerFrontend_io_bus_a_address; // @[DMATop.scala 40:30:@1388.4]
- wire readerFrontend_io_bus_a_valid; // @[DMATop.scala 40:30:@1388.4]
- wire readerFrontend_io_bus_a_ready; // @[DMATop.scala 40:30:@1388.4]
- wire [31:0] readerFrontend_io_bus_d_data; // @[DMATop.scala 40:30:@1388.4]
- wire readerFrontend_io_bus_d_valid; // @[DMATop.scala 40:30:@1388.4]
- wire readerFrontend_io_bus_d_ready; // @[DMATop.scala 40:30:@1388.4]
- wire readerFrontend_io_dataIO_ready; // @[DMATop.scala 40:30:@1388.4]
- wire readerFrontend_io_dataIO_valid; // @[DMATop.scala 40:30:@1388.4]
- wire [31:0] readerFrontend_io_dataIO_bits; // @[DMATop.scala 40:30:@1388.4]
- wire readerFrontend_io_xfer_done; // @[DMATop.scala 40:30:@1388.4]
- wire [31:0] readerFrontend_io_xfer_address; // @[DMATop.scala 40:30:@1388.4]
- wire [31:0] readerFrontend_io_xfer_length; // @[DMATop.scala 40:30:@1388.4]
- wire readerFrontend_io_xfer_valid; // @[DMATop.scala 40:30:@1388.4]
- wire writerFrontend_clock; // @[DMATop.scala 42:30:@1391.4]
- wire writerFrontend_reset; // @[DMATop.scala 42:30:@1391.4]
- wire [31:0] writerFrontend_io_bus_a_address; // @[DMATop.scala 42:30:@1391.4]
- wire [31:0] writerFrontend_io_bus_a_data; // @[DMATop.scala 42:30:@1391.4]
- wire writerFrontend_io_bus_a_valid; // @[DMATop.scala 42:30:@1391.4]
- wire writerFrontend_io_bus_a_ready; // @[DMATop.scala 42:30:@1391.4]
- wire writerFrontend_io_bus_d_valid; // @[DMATop.scala 42:30:@1391.4]
- wire writerFrontend_io_bus_d_ready; // @[DMATop.scala 42:30:@1391.4]
- wire writerFrontend_io_dataIO_ready; // @[DMATop.scala 42:30:@1391.4]
- wire writerFrontend_io_dataIO_valid; // @[DMATop.scala 42:30:@1391.4]
- wire [31:0] writerFrontend_io_dataIO_bits; // @[DMATop.scala 42:30:@1391.4]
- wire writerFrontend_io_xfer_done; // @[DMATop.scala 42:30:@1391.4]
- wire [31:0] writerFrontend_io_xfer_address; // @[DMATop.scala 42:30:@1391.4]
- wire [31:0] writerFrontend_io_xfer_length; // @[DMATop.scala 42:30:@1391.4]
- wire writerFrontend_io_xfer_valid; // @[DMATop.scala 42:30:@1391.4]
- wire [31:0] csr_io_csr_0_dataOut; // @[DMATop.scala 44:19:@1394.4]
- wire csr_io_csr_0_dataWrite; // @[DMATop.scala 44:19:@1394.4]
- wire [31:0] csr_io_csr_0_dataIn; // @[DMATop.scala 44:19:@1394.4]
- wire [31:0] csr_io_csr_1_dataIn; // @[DMATop.scala 44:19:@1394.4]
- wire [31:0] csr_io_csr_2_dataOut; // @[DMATop.scala 44:19:@1394.4]
- wire csr_io_csr_2_dataWrite; // @[DMATop.scala 44:19:@1394.4]
- wire [31:0] csr_io_csr_2_dataIn; // @[DMATop.scala 44:19:@1394.4]
- wire [31:0] csr_io_csr_3_dataOut; // @[DMATop.scala 44:19:@1394.4]
- wire csr_io_csr_3_dataWrite; // @[DMATop.scala 44:19:@1394.4]
- wire [31:0] csr_io_csr_3_dataIn; // @[DMATop.scala 44:19:@1394.4]
- wire [31:0] csr_io_csr_4_dataOut; // @[DMATop.scala 44:19:@1394.4]
- wire csr_io_csr_4_dataWrite; // @[DMATop.scala 44:19:@1394.4]
- wire [31:0] csr_io_csr_4_dataIn; // @[DMATop.scala 44:19:@1394.4]
- wire [31:0] csr_io_csr_5_dataOut; // @[DMATop.scala 44:19:@1394.4]
- wire csr_io_csr_5_dataWrite; // @[DMATop.scala 44:19:@1394.4]
- wire [31:0] csr_io_csr_5_dataIn; // @[DMATop.scala 44:19:@1394.4]
- wire [31:0] csr_io_csr_6_dataOut; // @[DMATop.scala 44:19:@1394.4]
- wire csr_io_csr_6_dataWrite; // @[DMATop.scala 44:19:@1394.4]
- wire [31:0] csr_io_csr_6_dataIn; // @[DMATop.scala 44:19:@1394.4]
- wire [31:0] csr_io_csr_7_dataOut; // @[DMATop.scala 44:19:@1394.4]
- wire csr_io_csr_7_dataWrite; // @[DMATop.scala 44:19:@1394.4]
- wire [31:0] csr_io_csr_7_dataIn; // @[DMATop.scala 44:19:@1394.4]
- wire [31:0] csr_io_csr_8_dataOut; // @[DMATop.scala 44:19:@1394.4]
- wire csr_io_csr_8_dataWrite; // @[DMATop.scala 44:19:@1394.4]
- wire [31:0] csr_io_csr_8_dataIn; // @[DMATop.scala 44:19:@1394.4]
- wire [31:0] csr_io_csr_9_dataOut; // @[DMATop.scala 44:19:@1394.4]
- wire csr_io_csr_9_dataWrite; // @[DMATop.scala 44:19:@1394.4]
- wire [31:0] csr_io_csr_9_dataIn; // @[DMATop.scala 44:19:@1394.4]
- wire [31:0] csr_io_csr_10_dataOut; // @[DMATop.scala 44:19:@1394.4]
- wire csr_io_csr_10_dataWrite; // @[DMATop.scala 44:19:@1394.4]
- wire [31:0] csr_io_csr_10_dataIn; // @[DMATop.scala 44:19:@1394.4]
- wire [31:0] csr_io_csr_11_dataOut; // @[DMATop.scala 44:19:@1394.4]
- wire csr_io_csr_11_dataWrite; // @[DMATop.scala 44:19:@1394.4]
- wire [31:0] csr_io_csr_11_dataIn; // @[DMATop.scala 44:19:@1394.4]
- wire [31:0] csr_io_csr_12_dataIn; // @[DMATop.scala 44:19:@1394.4]
- wire [31:0] csr_io_csr_13_dataIn; // @[DMATop.scala 44:19:@1394.4]
- wire [31:0] csr_io_csr_14_dataOut; // @[DMATop.scala 44:19:@1394.4]
- wire csr_io_csr_14_dataWrite; // @[DMATop.scala 44:19:@1394.4]
- wire [31:0] csr_io_csr_14_dataIn; // @[DMATop.scala 44:19:@1394.4]
- wire [31:0] csr_io_csr_15_dataOut; // @[DMATop.scala 44:19:@1394.4]
- wire csr_io_csr_15_dataWrite; // @[DMATop.scala 44:19:@1394.4]
- wire [31:0] csr_io_csr_15_dataIn; // @[DMATop.scala 44:19:@1394.4]
- wire [3:0] csr_io_bus_addr; // @[DMATop.scala 44:19:@1394.4]
- wire [31:0] csr_io_bus_dataOut; // @[DMATop.scala 44:19:@1394.4]
- wire [31:0] csr_io_bus_dataIn; // @[DMATop.scala 44:19:@1394.4]
- wire csr_io_bus_write; // @[DMATop.scala 44:19:@1394.4]
- wire csr_io_bus_read; // @[DMATop.scala 44:19:@1394.4]
- wire ctl_clock; // @[DMATop.scala 46:19:@1397.4]
- wire ctl_reset; // @[DMATop.scala 46:19:@1397.4]
- wire [31:0] ctl_io_csr_0_dataOut; // @[DMATop.scala 46:19:@1397.4]
- wire ctl_io_csr_0_dataWrite; // @[DMATop.scala 46:19:@1397.4]
- wire [31:0] ctl_io_csr_0_dataIn; // @[DMATop.scala 46:19:@1397.4]
- wire [31:0] ctl_io_csr_1_dataIn; // @[DMATop.scala 46:19:@1397.4]
- wire [31:0] ctl_io_csr_2_dataOut; // @[DMATop.scala 46:19:@1397.4]
- wire ctl_io_csr_2_dataWrite; // @[DMATop.scala 46:19:@1397.4]
- wire [31:0] ctl_io_csr_2_dataIn; // @[DMATop.scala 46:19:@1397.4]
- wire [31:0] ctl_io_csr_3_dataOut; // @[DMATop.scala 46:19:@1397.4]
- wire ctl_io_csr_3_dataWrite; // @[DMATop.scala 46:19:@1397.4]
- wire [31:0] ctl_io_csr_3_dataIn; // @[DMATop.scala 46:19:@1397.4]
- wire [31:0] ctl_io_csr_4_dataOut; // @[DMATop.scala 46:19:@1397.4]
- wire ctl_io_csr_4_dataWrite; // @[DMATop.scala 46:19:@1397.4]
- wire [31:0] ctl_io_csr_4_dataIn; // @[DMATop.scala 46:19:@1397.4]
- wire [31:0] ctl_io_csr_5_dataOut; // @[DMATop.scala 46:19:@1397.4]
- wire ctl_io_csr_5_dataWrite; // @[DMATop.scala 46:19:@1397.4]
- wire [31:0] ctl_io_csr_5_dataIn; // @[DMATop.scala 46:19:@1397.4]
- wire [31:0] ctl_io_csr_6_dataOut; // @[DMATop.scala 46:19:@1397.4]
- wire ctl_io_csr_6_dataWrite; // @[DMATop.scala 46:19:@1397.4]
- wire [31:0] ctl_io_csr_6_dataIn; // @[DMATop.scala 46:19:@1397.4]
- wire [31:0] ctl_io_csr_7_dataOut; // @[DMATop.scala 46:19:@1397.4]
- wire ctl_io_csr_7_dataWrite; // @[DMATop.scala 46:19:@1397.4]
- wire [31:0] ctl_io_csr_7_dataIn; // @[DMATop.scala 46:19:@1397.4]
- wire [31:0] ctl_io_csr_8_dataOut; // @[DMATop.scala 46:19:@1397.4]
- wire ctl_io_csr_8_dataWrite; // @[DMATop.scala 46:19:@1397.4]
- wire [31:0] ctl_io_csr_8_dataIn; // @[DMATop.scala 46:19:@1397.4]
- wire [31:0] ctl_io_csr_9_dataOut; // @[DMATop.scala 46:19:@1397.4]
- wire ctl_io_csr_9_dataWrite; // @[DMATop.scala 46:19:@1397.4]
- wire [31:0] ctl_io_csr_9_dataIn; // @[DMATop.scala 46:19:@1397.4]
- wire [31:0] ctl_io_csr_10_dataOut; // @[DMATop.scala 46:19:@1397.4]
- wire ctl_io_csr_10_dataWrite; // @[DMATop.scala 46:19:@1397.4]
- wire [31:0] ctl_io_csr_10_dataIn; // @[DMATop.scala 46:19:@1397.4]
- wire [31:0] ctl_io_csr_11_dataOut; // @[DMATop.scala 46:19:@1397.4]
- wire ctl_io_csr_11_dataWrite; // @[DMATop.scala 46:19:@1397.4]
- wire [31:0] ctl_io_csr_11_dataIn; // @[DMATop.scala 46:19:@1397.4]
- wire [31:0] ctl_io_csr_12_dataIn; // @[DMATop.scala 46:19:@1397.4]
- wire [31:0] ctl_io_csr_13_dataIn; // @[DMATop.scala 46:19:@1397.4]
- wire [31:0] ctl_io_csr_14_dataOut; // @[DMATop.scala 46:19:@1397.4]
- wire ctl_io_csr_14_dataWrite; // @[DMATop.scala 46:19:@1397.4]
- wire [31:0] ctl_io_csr_14_dataIn; // @[DMATop.scala 46:19:@1397.4]
- wire [31:0] ctl_io_csr_15_dataOut; // @[DMATop.scala 46:19:@1397.4]
- wire ctl_io_csr_15_dataWrite; // @[DMATop.scala 46:19:@1397.4]
- wire [31:0] ctl_io_csr_15_dataIn; // @[DMATop.scala 46:19:@1397.4]
- wire ctl_io_irq_readerDone; // @[DMATop.scala 46:19:@1397.4]
- wire ctl_io_irq_writerDone; // @[DMATop.scala 46:19:@1397.4]
- wire ctl_io_sync_readerSync; // @[DMATop.scala 46:19:@1397.4]
- wire ctl_io_sync_writerSync; // @[DMATop.scala 46:19:@1397.4]
- wire ctl_io_xferRead_done; // @[DMATop.scala 46:19:@1397.4]
- wire [31:0] ctl_io_xferRead_address; // @[DMATop.scala 46:19:@1397.4]
- wire [31:0] ctl_io_xferRead_length; // @[DMATop.scala 46:19:@1397.4]
- wire ctl_io_xferRead_valid; // @[DMATop.scala 46:19:@1397.4]
- wire ctl_io_xferWrite_done; // @[DMATop.scala 46:19:@1397.4]
- wire [31:0] ctl_io_xferWrite_address; // @[DMATop.scala 46:19:@1397.4]
- wire [31:0] ctl_io_xferWrite_length; // @[DMATop.scala 46:19:@1397.4]
- wire ctl_io_xferWrite_valid; // @[DMATop.scala 46:19:@1397.4]
- wire queue_clock; // @[Decoupled.scala 294:21:@1400.4]
- wire queue_reset; // @[Decoupled.scala 294:21:@1400.4]
- wire queue_io_enq_ready; // @[Decoupled.scala 294:21:@1400.4]
- wire queue_io_enq_valid; // @[Decoupled.scala 294:21:@1400.4]
- wire [31:0] queue_io_enq_bits; // @[Decoupled.scala 294:21:@1400.4]
- wire queue_io_deq_ready; // @[Decoupled.scala 294:21:@1400.4]
- wire queue_io_deq_valid; // @[Decoupled.scala 294:21:@1400.4]
- wire [31:0] queue_io_deq_bits; // @[Decoupled.scala 294:21:@1400.4]
- TLULCSRTL_TL_TL csrFrontend ( // @[DMATop.scala 38:27:@1385.4]
- .clock(csrFrontend_clock),
- .reset(csrFrontend_reset),
- .io_ctl_a_opcode(csrFrontend_io_ctl_a_opcode),
- .io_ctl_a_size(csrFrontend_io_ctl_a_size),
- .io_ctl_a_source(csrFrontend_io_ctl_a_source),
- .io_ctl_a_address(csrFrontend_io_ctl_a_address),
- .io_ctl_a_data(csrFrontend_io_ctl_a_data),
- .io_ctl_a_valid(csrFrontend_io_ctl_a_valid),
- .io_ctl_a_ready(csrFrontend_io_ctl_a_ready),
- .io_ctl_d_opcode(csrFrontend_io_ctl_d_opcode),
- .io_ctl_d_size(csrFrontend_io_ctl_d_size),
- .io_ctl_d_source(csrFrontend_io_ctl_d_source),
- .io_ctl_d_data(csrFrontend_io_ctl_d_data),
- .io_ctl_d_valid(csrFrontend_io_ctl_d_valid),
- .io_ctl_d_ready(csrFrontend_io_ctl_d_ready),
- .io_bus_addr(csrFrontend_io_bus_addr),
- .io_bus_dataOut(csrFrontend_io_bus_dataOut),
- .io_bus_dataIn(csrFrontend_io_bus_dataIn),
- .io_bus_write(csrFrontend_io_bus_write),
- .io_bus_read(csrFrontend_io_bus_read)
- );
- TLULReaderTL_TL_TL readerFrontend ( // @[DMATop.scala 40:30:@1388.4]
- .clock(readerFrontend_clock),
- .reset(readerFrontend_reset),
- .io_bus_a_address(readerFrontend_io_bus_a_address),
- .io_bus_a_valid(readerFrontend_io_bus_a_valid),
- .io_bus_a_ready(readerFrontend_io_bus_a_ready),
- .io_bus_d_data(readerFrontend_io_bus_d_data),
- .io_bus_d_valid(readerFrontend_io_bus_d_valid),
- .io_bus_d_ready(readerFrontend_io_bus_d_ready),
- .io_dataIO_ready(readerFrontend_io_dataIO_ready),
- .io_dataIO_valid(readerFrontend_io_dataIO_valid),
- .io_dataIO_bits(readerFrontend_io_dataIO_bits),
- .io_xfer_done(readerFrontend_io_xfer_done),
- .io_xfer_address(readerFrontend_io_xfer_address),
- .io_xfer_length(readerFrontend_io_xfer_length),
- .io_xfer_valid(readerFrontend_io_xfer_valid)
- );
- TLULWriterTL_TL_TL writerFrontend ( // @[DMATop.scala 42:30:@1391.4]
- .clock(writerFrontend_clock),
- .reset(writerFrontend_reset),
- .io_bus_a_address(writerFrontend_io_bus_a_address),
- .io_bus_a_data(writerFrontend_io_bus_a_data),
- .io_bus_a_valid(writerFrontend_io_bus_a_valid),
- .io_bus_a_ready(writerFrontend_io_bus_a_ready),
- .io_bus_d_valid(writerFrontend_io_bus_d_valid),
- .io_bus_d_ready(writerFrontend_io_bus_d_ready),
- .io_dataIO_ready(writerFrontend_io_dataIO_ready),
- .io_dataIO_valid(writerFrontend_io_dataIO_valid),
- .io_dataIO_bits(writerFrontend_io_dataIO_bits),
- .io_xfer_done(writerFrontend_io_xfer_done),
- .io_xfer_address(writerFrontend_io_xfer_address),
- .io_xfer_length(writerFrontend_io_xfer_length),
- .io_xfer_valid(writerFrontend_io_xfer_valid)
- );
- CSRTL_TL_TL csr ( // @[DMATop.scala 44:19:@1394.4]
- .io_csr_0_dataOut(csr_io_csr_0_dataOut),
- .io_csr_0_dataWrite(csr_io_csr_0_dataWrite),
- .io_csr_0_dataIn(csr_io_csr_0_dataIn),
- .io_csr_1_dataIn(csr_io_csr_1_dataIn),
- .io_csr_2_dataOut(csr_io_csr_2_dataOut),
- .io_csr_2_dataWrite(csr_io_csr_2_dataWrite),
- .io_csr_2_dataIn(csr_io_csr_2_dataIn),
- .io_csr_3_dataOut(csr_io_csr_3_dataOut),
- .io_csr_3_dataWrite(csr_io_csr_3_dataWrite),
- .io_csr_3_dataIn(csr_io_csr_3_dataIn),
- .io_csr_4_dataOut(csr_io_csr_4_dataOut),
- .io_csr_4_dataWrite(csr_io_csr_4_dataWrite),
- .io_csr_4_dataIn(csr_io_csr_4_dataIn),
- .io_csr_5_dataOut(csr_io_csr_5_dataOut),
- .io_csr_5_dataWrite(csr_io_csr_5_dataWrite),
- .io_csr_5_dataIn(csr_io_csr_5_dataIn),
- .io_csr_6_dataOut(csr_io_csr_6_dataOut),
- .io_csr_6_dataWrite(csr_io_csr_6_dataWrite),
- .io_csr_6_dataIn(csr_io_csr_6_dataIn),
- .io_csr_7_dataOut(csr_io_csr_7_dataOut),
- .io_csr_7_dataWrite(csr_io_csr_7_dataWrite),
- .io_csr_7_dataIn(csr_io_csr_7_dataIn),
- .io_csr_8_dataOut(csr_io_csr_8_dataOut),
- .io_csr_8_dataWrite(csr_io_csr_8_dataWrite),
- .io_csr_8_dataIn(csr_io_csr_8_dataIn),
- .io_csr_9_dataOut(csr_io_csr_9_dataOut),
- .io_csr_9_dataWrite(csr_io_csr_9_dataWrite),
- .io_csr_9_dataIn(csr_io_csr_9_dataIn),
- .io_csr_10_dataOut(csr_io_csr_10_dataOut),
- .io_csr_10_dataWrite(csr_io_csr_10_dataWrite),
- .io_csr_10_dataIn(csr_io_csr_10_dataIn),
- .io_csr_11_dataOut(csr_io_csr_11_dataOut),
- .io_csr_11_dataWrite(csr_io_csr_11_dataWrite),
- .io_csr_11_dataIn(csr_io_csr_11_dataIn),
- .io_csr_12_dataIn(csr_io_csr_12_dataIn),
- .io_csr_13_dataIn(csr_io_csr_13_dataIn),
- .io_csr_14_dataOut(csr_io_csr_14_dataOut),
- .io_csr_14_dataWrite(csr_io_csr_14_dataWrite),
- .io_csr_14_dataIn(csr_io_csr_14_dataIn),
- .io_csr_15_dataOut(csr_io_csr_15_dataOut),
- .io_csr_15_dataWrite(csr_io_csr_15_dataWrite),
- .io_csr_15_dataIn(csr_io_csr_15_dataIn),
- .io_bus_addr(csr_io_bus_addr),
- .io_bus_dataOut(csr_io_bus_dataOut),
- .io_bus_dataIn(csr_io_bus_dataIn),
- .io_bus_write(csr_io_bus_write),
- .io_bus_read(csr_io_bus_read)
- );
- WorkerCSRWrapperTL_TL_TL ctl ( // @[DMATop.scala 46:19:@1397.4]
- .clock(ctl_clock),
- .reset(ctl_reset),
- .io_csr_0_dataOut(ctl_io_csr_0_dataOut),
- .io_csr_0_dataWrite(ctl_io_csr_0_dataWrite),
- .io_csr_0_dataIn(ctl_io_csr_0_dataIn),
- .io_csr_1_dataIn(ctl_io_csr_1_dataIn),
- .io_csr_2_dataOut(ctl_io_csr_2_dataOut),
- .io_csr_2_dataWrite(ctl_io_csr_2_dataWrite),
- .io_csr_2_dataIn(ctl_io_csr_2_dataIn),
- .io_csr_3_dataOut(ctl_io_csr_3_dataOut),
- .io_csr_3_dataWrite(ctl_io_csr_3_dataWrite),
- .io_csr_3_dataIn(ctl_io_csr_3_dataIn),
- .io_csr_4_dataOut(ctl_io_csr_4_dataOut),
- .io_csr_4_dataWrite(ctl_io_csr_4_dataWrite),
- .io_csr_4_dataIn(ctl_io_csr_4_dataIn),
- .io_csr_5_dataOut(ctl_io_csr_5_dataOut),
- .io_csr_5_dataWrite(ctl_io_csr_5_dataWrite),
- .io_csr_5_dataIn(ctl_io_csr_5_dataIn),
- .io_csr_6_dataOut(ctl_io_csr_6_dataOut),
- .io_csr_6_dataWrite(ctl_io_csr_6_dataWrite),
- .io_csr_6_dataIn(ctl_io_csr_6_dataIn),
- .io_csr_7_dataOut(ctl_io_csr_7_dataOut),
- .io_csr_7_dataWrite(ctl_io_csr_7_dataWrite),
- .io_csr_7_dataIn(ctl_io_csr_7_dataIn),
- .io_csr_8_dataOut(ctl_io_csr_8_dataOut),
- .io_csr_8_dataWrite(ctl_io_csr_8_dataWrite),
- .io_csr_8_dataIn(ctl_io_csr_8_dataIn),
- .io_csr_9_dataOut(ctl_io_csr_9_dataOut),
- .io_csr_9_dataWrite(ctl_io_csr_9_dataWrite),
- .io_csr_9_dataIn(ctl_io_csr_9_dataIn),
- .io_csr_10_dataOut(ctl_io_csr_10_dataOut),
- .io_csr_10_dataWrite(ctl_io_csr_10_dataWrite),
- .io_csr_10_dataIn(ctl_io_csr_10_dataIn),
- .io_csr_11_dataOut(ctl_io_csr_11_dataOut),
- .io_csr_11_dataWrite(ctl_io_csr_11_dataWrite),
- .io_csr_11_dataIn(ctl_io_csr_11_dataIn),
- .io_csr_12_dataIn(ctl_io_csr_12_dataIn),
- .io_csr_13_dataIn(ctl_io_csr_13_dataIn),
- .io_csr_14_dataOut(ctl_io_csr_14_dataOut),
- .io_csr_14_dataWrite(ctl_io_csr_14_dataWrite),
- .io_csr_14_dataIn(ctl_io_csr_14_dataIn),
- .io_csr_15_dataOut(ctl_io_csr_15_dataOut),
- .io_csr_15_dataWrite(ctl_io_csr_15_dataWrite),
- .io_csr_15_dataIn(ctl_io_csr_15_dataIn),
- .io_irq_readerDone(ctl_io_irq_readerDone),
- .io_irq_writerDone(ctl_io_irq_writerDone),
- .io_sync_readerSync(ctl_io_sync_readerSync),
- .io_sync_writerSync(ctl_io_sync_writerSync),
- .io_xferRead_done(ctl_io_xferRead_done),
- .io_xferRead_address(ctl_io_xferRead_address),
- .io_xferRead_length(ctl_io_xferRead_length),
- .io_xferRead_valid(ctl_io_xferRead_valid),
- .io_xferWrite_done(ctl_io_xferWrite_done),
- .io_xferWrite_address(ctl_io_xferWrite_address),
- .io_xferWrite_length(ctl_io_xferWrite_length),
- .io_xferWrite_valid(ctl_io_xferWrite_valid)
- );
- Queue queue ( // @[Decoupled.scala 294:21:@1400.4]
- .clock(queue_clock),
- .reset(queue_reset),
- .io_enq_ready(queue_io_enq_ready),
- .io_enq_valid(queue_io_enq_valid),
- .io_enq_bits(queue_io_enq_bits),
- .io_deq_ready(queue_io_deq_ready),
- .io_deq_valid(queue_io_deq_valid),
- .io_deq_bits(queue_io_deq_bits)
- );
- assign io_control_a_ready = csrFrontend_io_ctl_a_ready; // @[DMATop.scala 52:22:@1419.4]
- assign io_control_d_opcode = csrFrontend_io_ctl_d_opcode; // @[DMATop.scala 52:22:@1418.4]
- assign io_control_d_param = 3'h0; // @[DMATop.scala 52:22:@1417.4]
- assign io_control_d_size = csrFrontend_io_ctl_d_size; // @[DMATop.scala 52:22:@1416.4]
- assign io_control_d_source = csrFrontend_io_ctl_d_source; // @[DMATop.scala 52:22:@1415.4]
- assign io_control_d_sink = 1'h0; // @[DMATop.scala 52:22:@1414.4]
- assign io_control_d_denied = 1'h0; // @[DMATop.scala 52:22:@1413.4]
- assign io_control_d_data = csrFrontend_io_ctl_d_data; // @[DMATop.scala 52:22:@1412.4]
- assign io_control_d_corrupt = 1'h0; // @[DMATop.scala 52:22:@1411.4]
- assign io_control_d_valid = csrFrontend_io_ctl_d_valid; // @[DMATop.scala 52:22:@1410.4]
- assign io_read_a_opcode = 3'h4; // @[DMATop.scala 58:11:@1527.4]
- assign io_read_a_param = 3'h0; // @[DMATop.scala 58:11:@1526.4]
- assign io_read_a_size = 2'h2; // @[DMATop.scala 58:11:@1525.4]
- assign io_read_a_source = 10'h0; // @[DMATop.scala 58:11:@1524.4]
- assign io_read_a_address = readerFrontend_io_bus_a_address; // @[DMATop.scala 58:11:@1523.4]
- assign io_read_a_mask = 4'hf; // @[DMATop.scala 58:11:@1522.4]
- assign io_read_a_data = 32'h0; // @[DMATop.scala 58:11:@1521.4]
- assign io_read_a_corrupt = 1'h0; // @[DMATop.scala 58:11:@1520.4]
- assign io_read_a_valid = readerFrontend_io_bus_a_valid; // @[DMATop.scala 58:11:@1519.4]
- assign io_read_d_ready = readerFrontend_io_bus_d_ready; // @[DMATop.scala 58:11:@1508.4]
- assign io_write_a_opcode = 3'h0; // @[DMATop.scala 59:12:@1547.4]
- assign io_write_a_param = 3'h0; // @[DMATop.scala 59:12:@1546.4]
- assign io_write_a_size = 2'h2; // @[DMATop.scala 59:12:@1545.4]
- assign io_write_a_source = 10'h0; // @[DMATop.scala 59:12:@1544.4]
- assign io_write_a_address = writerFrontend_io_bus_a_address; // @[DMATop.scala 59:12:@1543.4]
- assign io_write_a_mask = 4'hf; // @[DMATop.scala 59:12:@1542.4]
- assign io_write_a_data = writerFrontend_io_bus_a_data; // @[DMATop.scala 59:12:@1541.4]
- assign io_write_a_corrupt = 1'h0; // @[DMATop.scala 59:12:@1540.4]
- assign io_write_a_valid = writerFrontend_io_bus_a_valid; // @[DMATop.scala 59:12:@1539.4]
- assign io_write_d_ready = writerFrontend_io_bus_d_ready; // @[DMATop.scala 59:12:@1528.4]
- assign io_irq_readerDone = ctl_io_irq_readerDone; // @[DMATop.scala 61:10:@1549.4]
- assign io_irq_writerDone = ctl_io_irq_writerDone; // @[DMATop.scala 61:10:@1548.4]
- assign csrFrontend_clock = clock; // @[:@1386.4]
- assign csrFrontend_reset = reset; // @[:@1387.4]
- assign csrFrontend_io_ctl_a_opcode = io_control_a_opcode; // @[DMATop.scala 52:22:@1428.4]
- assign csrFrontend_io_ctl_a_size = io_control_a_size; // @[DMATop.scala 52:22:@1426.4]
- assign csrFrontend_io_ctl_a_source = io_control_a_source; // @[DMATop.scala 52:22:@1425.4]
- assign csrFrontend_io_ctl_a_address = io_control_a_address; // @[DMATop.scala 52:22:@1424.4]
- assign csrFrontend_io_ctl_a_data = io_control_a_data; // @[DMATop.scala 52:22:@1422.4]
- assign csrFrontend_io_ctl_a_valid = io_control_a_valid; // @[DMATop.scala 52:22:@1420.4]
- assign csrFrontend_io_ctl_d_ready = io_control_d_ready; // @[DMATop.scala 52:22:@1409.4]
- assign csrFrontend_io_bus_dataIn = csr_io_bus_dataIn; // @[DMATop.scala 53:14:@1431.4]
- assign readerFrontend_clock = clock; // @[:@1389.4]
- assign readerFrontend_reset = reset; // @[:@1390.4]
- assign readerFrontend_io_bus_a_ready = io_read_a_ready; // @[DMATop.scala 58:11:@1518.4]
- assign readerFrontend_io_bus_d_data = io_read_d_data; // @[DMATop.scala 58:11:@1511.4]
- assign readerFrontend_io_bus_d_valid = io_read_d_valid; // @[DMATop.scala 58:11:@1509.4]
- assign readerFrontend_io_dataIO_ready = queue_io_enq_ready; // @[Decoupled.scala 297:17:@1405.4]
- assign readerFrontend_io_xfer_address = ctl_io_xferRead_address; // @[DMATop.scala 55:26:@1501.4]
- assign readerFrontend_io_xfer_length = ctl_io_xferRead_length; // @[DMATop.scala 55:26:@1500.4]
- assign readerFrontend_io_xfer_valid = ctl_io_xferRead_valid; // @[DMATop.scala 55:26:@1499.4]
- assign writerFrontend_clock = clock; // @[:@1392.4]
- assign writerFrontend_reset = reset; // @[:@1393.4]
- assign writerFrontend_io_bus_a_ready = io_write_a_ready; // @[DMATop.scala 59:12:@1538.4]
- assign writerFrontend_io_bus_d_valid = io_write_d_valid; // @[DMATop.scala 59:12:@1529.4]
- assign writerFrontend_io_dataIO_valid = queue_io_deq_valid; // @[DMATop.scala 50:9:@1407.4]
- assign writerFrontend_io_dataIO_bits = queue_io_deq_bits; // @[DMATop.scala 50:9:@1406.4]
- assign writerFrontend_io_xfer_address = ctl_io_xferWrite_address; // @[DMATop.scala 56:26:@1506.4]
- assign writerFrontend_io_xfer_length = ctl_io_xferWrite_length; // @[DMATop.scala 56:26:@1505.4]
- assign writerFrontend_io_xfer_valid = ctl_io_xferWrite_valid; // @[DMATop.scala 56:26:@1504.4]
- assign csr_io_csr_0_dataIn = ctl_io_csr_0_dataIn; // @[DMATop.scala 54:14:@1434.4]
- assign csr_io_csr_1_dataIn = ctl_io_csr_1_dataIn; // @[DMATop.scala 54:14:@1438.4]
- assign csr_io_csr_2_dataIn = ctl_io_csr_2_dataIn; // @[DMATop.scala 54:14:@1442.4]
- assign csr_io_csr_3_dataIn = ctl_io_csr_3_dataIn; // @[DMATop.scala 54:14:@1446.4]
- assign csr_io_csr_4_dataIn = ctl_io_csr_4_dataIn; // @[DMATop.scala 54:14:@1450.4]
- assign csr_io_csr_5_dataIn = ctl_io_csr_5_dataIn; // @[DMATop.scala 54:14:@1454.4]
- assign csr_io_csr_6_dataIn = ctl_io_csr_6_dataIn; // @[DMATop.scala 54:14:@1458.4]
- assign csr_io_csr_7_dataIn = ctl_io_csr_7_dataIn; // @[DMATop.scala 54:14:@1462.4]
- assign csr_io_csr_8_dataIn = ctl_io_csr_8_dataIn; // @[DMATop.scala 54:14:@1466.4]
- assign csr_io_csr_9_dataIn = ctl_io_csr_9_dataIn; // @[DMATop.scala 54:14:@1470.4]
- assign csr_io_csr_10_dataIn = ctl_io_csr_10_dataIn; // @[DMATop.scala 54:14:@1474.4]
- assign csr_io_csr_11_dataIn = ctl_io_csr_11_dataIn; // @[DMATop.scala 54:14:@1478.4]
- assign csr_io_csr_12_dataIn = ctl_io_csr_12_dataIn; // @[DMATop.scala 54:14:@1482.4]
- assign csr_io_csr_13_dataIn = ctl_io_csr_13_dataIn; // @[DMATop.scala 54:14:@1486.4]
- assign csr_io_csr_14_dataIn = ctl_io_csr_14_dataIn; // @[DMATop.scala 54:14:@1490.4]
- assign csr_io_csr_15_dataIn = ctl_io_csr_15_dataIn; // @[DMATop.scala 54:14:@1494.4]
- assign csr_io_bus_addr = csrFrontend_io_bus_addr; // @[DMATop.scala 53:14:@1433.4]
- assign csr_io_bus_dataOut = csrFrontend_io_bus_dataOut; // @[DMATop.scala 53:14:@1432.4]
- assign csr_io_bus_write = csrFrontend_io_bus_write; // @[DMATop.scala 53:14:@1430.4]
- assign csr_io_bus_read = csrFrontend_io_bus_read; // @[DMATop.scala 53:14:@1429.4]
- assign ctl_clock = clock; // @[:@1398.4]
- assign ctl_reset = reset; // @[:@1399.4]
- assign ctl_io_csr_0_dataOut = csr_io_csr_0_dataOut; // @[DMATop.scala 54:14:@1436.4]
- assign ctl_io_csr_0_dataWrite = csr_io_csr_0_dataWrite; // @[DMATop.scala 54:14:@1435.4]
- assign ctl_io_csr_2_dataOut = csr_io_csr_2_dataOut; // @[DMATop.scala 54:14:@1444.4]
- assign ctl_io_csr_2_dataWrite = csr_io_csr_2_dataWrite; // @[DMATop.scala 54:14:@1443.4]
- assign ctl_io_csr_3_dataOut = csr_io_csr_3_dataOut; // @[DMATop.scala 54:14:@1448.4]
- assign ctl_io_csr_3_dataWrite = csr_io_csr_3_dataWrite; // @[DMATop.scala 54:14:@1447.4]
- assign ctl_io_csr_4_dataOut = csr_io_csr_4_dataOut; // @[DMATop.scala 54:14:@1452.4]
- assign ctl_io_csr_4_dataWrite = csr_io_csr_4_dataWrite; // @[DMATop.scala 54:14:@1451.4]
- assign ctl_io_csr_5_dataOut = csr_io_csr_5_dataOut; // @[DMATop.scala 54:14:@1456.4]
- assign ctl_io_csr_5_dataWrite = csr_io_csr_5_dataWrite; // @[DMATop.scala 54:14:@1455.4]
- assign ctl_io_csr_6_dataOut = csr_io_csr_6_dataOut; // @[DMATop.scala 54:14:@1460.4]
- assign ctl_io_csr_6_dataWrite = csr_io_csr_6_dataWrite; // @[DMATop.scala 54:14:@1459.4]
- assign ctl_io_csr_7_dataOut = csr_io_csr_7_dataOut; // @[DMATop.scala 54:14:@1464.4]
- assign ctl_io_csr_7_dataWrite = csr_io_csr_7_dataWrite; // @[DMATop.scala 54:14:@1463.4]
- assign ctl_io_csr_8_dataOut = csr_io_csr_8_dataOut; // @[DMATop.scala 54:14:@1468.4]
- assign ctl_io_csr_8_dataWrite = csr_io_csr_8_dataWrite; // @[DMATop.scala 54:14:@1467.4]
- assign ctl_io_csr_9_dataOut = csr_io_csr_9_dataOut; // @[DMATop.scala 54:14:@1472.4]
- assign ctl_io_csr_9_dataWrite = csr_io_csr_9_dataWrite; // @[DMATop.scala 54:14:@1471.4]
- assign ctl_io_csr_10_dataOut = csr_io_csr_10_dataOut; // @[DMATop.scala 54:14:@1476.4]
- assign ctl_io_csr_10_dataWrite = csr_io_csr_10_dataWrite; // @[DMATop.scala 54:14:@1475.4]
- assign ctl_io_csr_11_dataOut = csr_io_csr_11_dataOut; // @[DMATop.scala 54:14:@1480.4]
- assign ctl_io_csr_11_dataWrite = csr_io_csr_11_dataWrite; // @[DMATop.scala 54:14:@1479.4]
- assign ctl_io_csr_14_dataOut = csr_io_csr_14_dataOut; // @[DMATop.scala 54:14:@1492.4]
- assign ctl_io_csr_14_dataWrite = csr_io_csr_14_dataWrite; // @[DMATop.scala 54:14:@1491.4]
- assign ctl_io_csr_15_dataOut = csr_io_csr_15_dataOut; // @[DMATop.scala 54:14:@1496.4]
- assign ctl_io_csr_15_dataWrite = csr_io_csr_15_dataWrite; // @[DMATop.scala 54:14:@1495.4]
- assign ctl_io_sync_readerSync = io_sync_readerSync; // @[DMATop.scala 62:11:@1551.4]
- assign ctl_io_sync_writerSync = io_sync_writerSync; // @[DMATop.scala 62:11:@1550.4]
- assign ctl_io_xferRead_done = readerFrontend_io_xfer_done; // @[DMATop.scala 55:26:@1502.4]
- assign ctl_io_xferWrite_done = writerFrontend_io_xfer_done; // @[DMATop.scala 56:26:@1507.4]
- assign queue_clock = clock; // @[:@1401.4]
- assign queue_reset = reset; // @[:@1402.4]
- assign queue_io_enq_valid = readerFrontend_io_dataIO_valid; // @[Decoupled.scala 295:22:@1403.4]
- assign queue_io_enq_bits = readerFrontend_io_dataIO_bits; // @[Decoupled.scala 296:21:@1404.4]
- assign queue_io_deq_ready = writerFrontend_io_dataIO_ready; // @[DMATop.scala 50:9:@1408.4]
-endmodule
diff --git a/hw/top_matcha/ip/dma/rtl/dma.sv b/hw/top_matcha/ip/dma/rtl/dma.sv
index f0b32d4..179d9e7 100644
--- a/hw/top_matcha/ip/dma/rtl/dma.sv
+++ b/hw/top_matcha/ip/dma/rtl/dma.sv
@@ -135,7 +135,7 @@
};
- DMATopTL_TL_TL u_fastvdma (
+ DMATop u_fastvdma (
.clock ( clk_i ),
.reset ( ~rst_ni ),
