diff --git a/hw/top_matcha/data/pins_nexus.xdc b/hw/top_matcha/data/pins_nexus.xdc
index f327a2e..b032041 100644
--- a/hw/top_matcha/data/pins_nexus.xdc
+++ b/hw/top_matcha/data/pins_nexus.xdc
@@ -179,25 +179,26 @@
 set_property -dict { PACKAGE_PIN BD11 IOSTANDARD LVCMOS18 } [get_ports { IOB9 }];              #FMC_HA05_N
 #MISC from PMOD3
 set_property -dict { PACKAGE_PIN BE15  IOSTANDARD LVCMOS18 } [get_ports { IOA0 }];             #FMC_HA06_P
-set_property -dict { PACKAGE_PIN BF15  IOSTANDARD LVCMOS18 } [get_ports { IOC6 }];             #FMC_HA06_N
-set_property -dict { PACKAGE_PIN BE14  IOSTANDARD LVCMOS18 } [get_ports { IOC7 }];             #FMC_HA07_P
+# set_property -dict { PACKAGE_PIN BF15  IOSTANDARD LVCMOS18 } [get_ports { IOC6 }];             #FMC_HA06_N
+# set_property -dict { PACKAGE_PIN BE14  IOSTANDARD LVCMOS18 } [get_ports { IOC7 }];             #FMC_HA07_P
 set_property -dict { PACKAGE_PIN BF14  IOSTANDARD LVCMOS18 } [get_ports { IOA1 }];             #FMC_HA07_N
 set_property -dict { PACKAGE_PIN BC15  IOSTANDARD LVCMOS18 } [get_ports { IOC9 }];             #FMC_HA08_P
 
 
 ## TI TUSB1T1105AMHX USB Transceiver "usbdev" testing, Bank 64 LVCMOS18
-#set_property -dict { PACKAGE_PIN AW23  IOSTANDARD LVCMOS18 } [get_ports { IO_UPHY_DP_TX }]; #USB0_VPO
-#set_property -dict { PACKAGE_PIN AW22  IOSTANDARD LVCMOS18 } [get_ports { IO_UPHY_DN_TX }]; #USB0_VMO
-#set_property -dict { PACKAGE_PIN AY22   IOSTANDARD LVCMOS18 } [get_ports { IO_UPHY_DP_RX }]; #USB0_VP
-#set_property -dict { PACKAGE_PIN BA22   IOSTANDARD LVCMOS18 } [get_ports { IO_UPHY_DN_RX }]; #USB0_VM
+set_property -dict { PACKAGE_PIN AW23  IOSTANDARD LVCMOS18 } [get_ports { IO_UPHY_VPO }]; #USB0_VPO
+set_property -dict { PACKAGE_PIN AW22  IOSTANDARD LVCMOS18 } [get_ports { IO_UPHY_VMO }]; #USB0_VMO
+set_property -dict { PACKAGE_PIN AY22  IOSTANDARD LVCMOS18 } [get_ports { IO_UPHY_VP }]; #USB0_VP
+set_property -dict { PACKAGE_PIN BA22  IOSTANDARD LVCMOS18 } [get_ports { IO_UPHY_VM }]; #USB0_VM
 ## USRUSB_SOFTCONN(not used, conneted to xxxxx as placeholder)
 #set_property -dict { PACKAGE_PIN AH33  IOSTANDARD LVCMOS18 } [get_ports { IO_UPHY_DPPULLUP }]; ## MOVED TO EXP1x10_J271_P15 to clear up PMOD4
 ## Roman added USB voltage sense pin to AY17 of Bank65  of Nexus FPGA in the latest revision board.
-#set_property -dict { PACKAGE_PIN AY17   IOSTANDARD LVCMOS18 } [get_ports { IO_UPHY_SENSE }]; #USB0_VBUS_SENSEB
-#set_property -dict { PACKAGE_PIN AU21  IOSTANDARD LVCMOS18 } [get_ports { IO_UPHY_OE_N }]; #USB0_OEB
-#set_property -dict { PACKAGE_PIN AV21   IOSTANDARD LVCMOS18 } [get_ports { IO_UPHY_D_RX }]; #USB0_RCV
-#set_property -dict { PACKAGE_PIN BA21  IOSTANDARD LVCMOS18 PULLTYPE PULLUP} [get_ports { IO_UPHY_SPD }]; #USB0_MODE
-#set_property -dict { PACKAGE_PIN AT21  IOSTANDARD LVCMOS18 PULLTYPE PULLUP} [get_ports { IO_UPHY_SUS }]; #USB0_CFG
+set_property -dict { PACKAGE_PIN BF7   IOSTANDARD LVCMOS18 } [get_ports { IOC6 }]; #USB0_VBUS_ENB
+set_property -dict { PACKAGE_PIN AY17  IOSTANDARD LVCMOS18 } [get_ports { IOC7 }]; #USB0_VBUS_SENSEB
+set_property -dict { PACKAGE_PIN AU21  IOSTANDARD LVCMOS18 } [get_ports { IO_UPHY_OEB }]; #USB0_OEB
+set_property -dict { PACKAGE_PIN AV21  IOSTANDARD LVCMOS18 } [get_ports { IO_UPHY_RCV }]; #USB0_RCV
+set_property -dict { PACKAGE_PIN BA21  IOSTANDARD LVCMOS18 PULLTYPE PULLUP} [get_ports { IO_UPHY_MODE }]; #USB0_MODE
+set_property -dict { PACKAGE_PIN AT21  IOSTANDARD LVCMOS18 PULLTYPE PULLUP} [get_ports { IO_UPHY_CFG }]; #USB0_CFG
 
 ## UART0 (Security Core UART0, default connect to FTDI CDBUS, late may map to SOM_FPGA_GPIO for in-system monitor)
 ## Bank 65, LVCMOS18
diff --git a/hw/top_matcha/data/top_matcha.hjson b/hw/top_matcha/data/top_matcha.hjson
index e5dd4f5..52fd83d 100644
--- a/hw/top_matcha/data/top_matcha.hjson
+++ b/hw/top_matcha/data/top_matcha.hjson
@@ -1406,10 +1406,10 @@
         'sensor_ctrl.ast_init_done'       : 'ast_init_done',
         'spi_device.sck_monitor'          : 'sck_monitor',
         'usbdev.usb_rx_d'                 : '',
+        'usbdev.usb_rx_enable'            : '',
         'usbdev.usb_tx_d'                 : '',
         'usbdev.usb_tx_se0'               : '',
         'usbdev.usb_tx_use_d_se0'         : '',
-        'usbdev.usb_rx_enable'            : '',
         'usbdev.usb_ref_val'              : '',
         'usbdev.usb_ref_pulse'            : '',
     },
@@ -1811,6 +1811,15 @@
           { name: 'IO_CLK_N',         type: 'AnalogIn0', bank: 'VCC', connection: 'manual', desc: 'Extra clock input for FPGA target'}
           { name: 'POR_BUTTON_N',     type: 'InputStd', bank: 'VCC', connection: 'manual', desc: 'Power-on reset button input'}
           { name: 'JTAG_SRST_N',      type: 'InputStd', bank: 'VCC', connection: 'manual', desc: 'JTAG header SRST, triggers POR'}
+          // USB
+          { name: 'IO_UPHY_VPO',       type: 'BidirStd', bank: 'VCC', connection: 'manual', desc: 'Manual UPHY signal for FPGA target'}
+          { name: 'IO_UPHY_VMO',       type: 'BidirStd', bank: 'VCC', connection: 'manual', desc: 'Manual UPHY signal for FPGA target'}
+          { name: 'IO_UPHY_VP',        type: 'BidirStd', bank: 'VCC', connection: 'manual', desc: 'Manual UPHY signal for FPGA target'}
+          { name: 'IO_UPHY_VM',        type: 'BidirStd', bank: 'VCC', connection: 'manual', desc: 'Manual UPHY signal for FPGA target'}
+          { name: 'IO_UPHY_OEB',       type: 'BidirStd', bank: 'VCC', connection: 'manual', desc: 'Manual UPHY signal for FPGA target'}
+          { name: 'IO_UPHY_RCV',       type: 'BidirStd', bank: 'VCC', connection: 'manual', desc: 'Manual UPHY signal for FPGA target'}
+          { name: 'IO_UPHY_MODE',      type: 'BidirStd', bank: 'VCC', connection: 'manual', desc: 'Manual UPHY signal for FPGA target'}
+          { name: 'IO_UPHY_CFG',       type: 'BidirStd', bank: 'VCC', connection: 'manual', desc: 'Manual UPHY signal for FPGA target'}
           // ChipWhisperer IO
           { name: 'IO_CLKOUT',        type: 'BidirStd', bank: 'VCC', connection: 'manual', desc: 'Manual clock output for SCA setup'}
           { name: 'IO_TRIGGER',       type: 'BidirStd', bank: 'VCC', connection: 'manual', desc: 'Manual trigger output for SCA setup'}
diff --git a/hw/top_matcha/ip/pinmux/doc/autogen/pinout_nexus.md b/hw/top_matcha/ip/pinmux/doc/autogen/pinout_nexus.md
index 47af80f..0019d28 100644
--- a/hw/top_matcha/ip/pinmux/doc/autogen/pinout_nexus.md
+++ b/hw/top_matcha/ip/pinmux/doc/autogen/pinout_nexus.md
@@ -86,6 +86,14 @@
 |   <p style="font-size:smaller">IO_CLK_N</p>    |  <p style="font-size:smaller">AnalogIn0</p>   |  <p style="font-size:smaller">VCC</p>   |    <p style="font-size:smaller">manual</p>    |         <p style="font-size:smaller">-</p>          |                          <p style="font-size:smaller">- / -</p>                           |     <p style="font-size:smaller">Extra clock input for FPGA target</p>     |
 | <p style="font-size:smaller">POR_BUTTON_N</p>  |   <p style="font-size:smaller">InputStd</p>   |  <p style="font-size:smaller">VCC</p>   |    <p style="font-size:smaller">manual</p>    |         <p style="font-size:smaller">-</p>          |                          <p style="font-size:smaller">- / -</p>                           |        <p style="font-size:smaller">Power-on reset button input</p>        |
 |  <p style="font-size:smaller">JTAG_SRST_N</p>  |   <p style="font-size:smaller">InputStd</p>   |  <p style="font-size:smaller">VCC</p>   |    <p style="font-size:smaller">manual</p>    |         <p style="font-size:smaller">-</p>          |                          <p style="font-size:smaller">- / -</p>                           |      <p style="font-size:smaller">JTAG header SRST, triggers POR</p>       |
+|  <p style="font-size:smaller">IO_UPHY_VPO</p>  |   <p style="font-size:smaller">BidirStd</p>   |  <p style="font-size:smaller">VCC</p>   |    <p style="font-size:smaller">manual</p>    |         <p style="font-size:smaller">-</p>          |                          <p style="font-size:smaller">- / -</p>                           |    <p style="font-size:smaller">Manual UPHY signal for FPGA target</p>     |
+|  <p style="font-size:smaller">IO_UPHY_VMO</p>  |   <p style="font-size:smaller">BidirStd</p>   |  <p style="font-size:smaller">VCC</p>   |    <p style="font-size:smaller">manual</p>    |         <p style="font-size:smaller">-</p>          |                          <p style="font-size:smaller">- / -</p>                           |    <p style="font-size:smaller">Manual UPHY signal for FPGA target</p>     |
+|  <p style="font-size:smaller">IO_UPHY_VP</p>   |   <p style="font-size:smaller">BidirStd</p>   |  <p style="font-size:smaller">VCC</p>   |    <p style="font-size:smaller">manual</p>    |         <p style="font-size:smaller">-</p>          |                          <p style="font-size:smaller">- / -</p>                           |    <p style="font-size:smaller">Manual UPHY signal for FPGA target</p>     |
+|  <p style="font-size:smaller">IO_UPHY_VM</p>   |   <p style="font-size:smaller">BidirStd</p>   |  <p style="font-size:smaller">VCC</p>   |    <p style="font-size:smaller">manual</p>    |         <p style="font-size:smaller">-</p>          |                          <p style="font-size:smaller">- / -</p>                           |    <p style="font-size:smaller">Manual UPHY signal for FPGA target</p>     |
+|  <p style="font-size:smaller">IO_UPHY_OEB</p>  |   <p style="font-size:smaller">BidirStd</p>   |  <p style="font-size:smaller">VCC</p>   |    <p style="font-size:smaller">manual</p>    |         <p style="font-size:smaller">-</p>          |                          <p style="font-size:smaller">- / -</p>                           |    <p style="font-size:smaller">Manual UPHY signal for FPGA target</p>     |
+|  <p style="font-size:smaller">IO_UPHY_RCV</p>  |   <p style="font-size:smaller">BidirStd</p>   |  <p style="font-size:smaller">VCC</p>   |    <p style="font-size:smaller">manual</p>    |         <p style="font-size:smaller">-</p>          |                          <p style="font-size:smaller">- / -</p>                           |    <p style="font-size:smaller">Manual UPHY signal for FPGA target</p>     |
+| <p style="font-size:smaller">IO_UPHY_MODE</p>  |   <p style="font-size:smaller">BidirStd</p>   |  <p style="font-size:smaller">VCC</p>   |    <p style="font-size:smaller">manual</p>    |         <p style="font-size:smaller">-</p>          |                          <p style="font-size:smaller">- / -</p>                           |    <p style="font-size:smaller">Manual UPHY signal for FPGA target</p>     |
+|  <p style="font-size:smaller">IO_UPHY_CFG</p>  |   <p style="font-size:smaller">BidirStd</p>   |  <p style="font-size:smaller">VCC</p>   |    <p style="font-size:smaller">manual</p>    |         <p style="font-size:smaller">-</p>          |                          <p style="font-size:smaller">- / -</p>                           |    <p style="font-size:smaller">Manual UPHY signal for FPGA target</p>     |
 |   <p style="font-size:smaller">IO_CLKOUT</p>   |   <p style="font-size:smaller">BidirStd</p>   |  <p style="font-size:smaller">VCC</p>   |    <p style="font-size:smaller">manual</p>    |         <p style="font-size:smaller">-</p>          |                          <p style="font-size:smaller">- / -</p>                           |     <p style="font-size:smaller">Manual clock output for SCA setup</p>     |
 |  <p style="font-size:smaller">IO_TRIGGER</p>   |   <p style="font-size:smaller">BidirStd</p>   |  <p style="font-size:smaller">VCC</p>   |    <p style="font-size:smaller">manual</p>    |         <p style="font-size:smaller">-</p>          |                          <p style="font-size:smaller">- / -</p>                           |    <p style="font-size:smaller">Manual trigger output for SCA setup</p>    |
 ## Pinmux Connectivity
diff --git a/hw/top_matcha/ip/pinmux/doc/autogen/targets.md b/hw/top_matcha/ip/pinmux/doc/autogen/targets.md
index 805c020..1f1fe18 100644
--- a/hw/top_matcha/ip/pinmux/doc/autogen/targets.md
+++ b/hw/top_matcha/ip/pinmux/doc/autogen/targets.md
@@ -8,4 +8,4 @@
 |  Target Name  |  #IO Banks  |  #Muxed Pads  |  #Direct Pads  |  #Manual Pads  |  #Total Pads  |                              Pinout / Pinmux Tables                               |
 |:-------------:|:-----------:|:-------------:|:--------------:|:--------------:|:-------------:|:---------------------------------------------------------------------------------:|
 |     ASIC      |      4      |      53       |       14       |       15       |      82       | [Pinout Table](../../../top_matcha/ip/pinmux/doc/autogen/pinout_asic/index.html)  |
-|     NEXUS     |      4      |      53       |       14       |       9        |      76       | [Pinout Table](../../../top_matcha/ip/pinmux/doc/autogen/pinout_nexus/index.html) |
+|     NEXUS     |      4      |      53       |       14       |       17       |      84       | [Pinout Table](../../../top_matcha/ip/pinmux/doc/autogen/pinout_nexus/index.html) |
diff --git a/hw/top_matcha/rtl/autogen/chip_matcha_nexus.sv b/hw/top_matcha/rtl/autogen/chip_matcha_nexus.sv
index fdf4f8b..6ece7be 100644
--- a/hw/top_matcha/rtl/autogen/chip_matcha_nexus.sv
+++ b/hw/top_matcha/rtl/autogen/chip_matcha_nexus.sv
@@ -52,6 +52,14 @@
   inout IO_CLK_N, // Manual Pad
   inout POR_BUTTON_N, // Manual Pad
   inout JTAG_SRST_N, // Manual Pad
+  inout IO_UPHY_VPO, // Manual Pad
+  inout IO_UPHY_VMO, // Manual Pad
+  inout IO_UPHY_VP, // Manual Pad
+  inout IO_UPHY_VM, // Manual Pad
+  inout IO_UPHY_OEB, // Manual Pad
+  inout IO_UPHY_RCV, // Manual Pad
+  inout IO_UPHY_MODE, // Manual Pad
+  inout IO_UPHY_CFG, // Manual Pad
   inout IO_CLKOUT, // Manual Pad
   inout IO_TRIGGER, // Manual Pad
 
@@ -245,6 +253,14 @@
   logic manual_in_io_clk_n, manual_out_io_clk_n, manual_oe_io_clk_n;
   logic manual_in_por_button_n, manual_out_por_button_n, manual_oe_por_button_n;
   logic manual_in_jtag_srst_n, manual_out_jtag_srst_n, manual_oe_jtag_srst_n;
+  logic manual_in_io_uphy_vpo, manual_out_io_uphy_vpo, manual_oe_io_uphy_vpo;
+  logic manual_in_io_uphy_vmo, manual_out_io_uphy_vmo, manual_oe_io_uphy_vmo;
+  logic manual_in_io_uphy_vp, manual_out_io_uphy_vp, manual_oe_io_uphy_vp;
+  logic manual_in_io_uphy_vm, manual_out_io_uphy_vm, manual_oe_io_uphy_vm;
+  logic manual_in_io_uphy_oeb, manual_out_io_uphy_oeb, manual_oe_io_uphy_oeb;
+  logic manual_in_io_uphy_rcv, manual_out_io_uphy_rcv, manual_oe_io_uphy_rcv;
+  logic manual_in_io_uphy_mode, manual_out_io_uphy_mode, manual_oe_io_uphy_mode;
+  logic manual_in_io_uphy_cfg, manual_out_io_uphy_cfg, manual_oe_io_uphy_cfg;
   logic manual_in_io_clkout, manual_out_io_clkout, manual_oe_io_clkout;
   logic manual_in_io_trigger, manual_out_io_trigger, manual_oe_io_trigger;
 
@@ -255,6 +271,14 @@
   pad_attr_t manual_attr_io_clk_n;
   pad_attr_t manual_attr_por_button_n;
   pad_attr_t manual_attr_jtag_srst_n;
+  pad_attr_t manual_attr_io_uphy_vpo;
+  pad_attr_t manual_attr_io_uphy_vmo;
+  pad_attr_t manual_attr_io_uphy_vp;
+  pad_attr_t manual_attr_io_uphy_vm;
+  pad_attr_t manual_attr_io_uphy_oeb;
+  pad_attr_t manual_attr_io_uphy_rcv;
+  pad_attr_t manual_attr_io_uphy_mode;
+  pad_attr_t manual_attr_io_uphy_cfg;
   pad_attr_t manual_attr_io_clkout;
   pad_attr_t manual_attr_io_trigger;
 
@@ -275,11 +299,19 @@
   padring #(
     // Padring specific counts may differ from pinmux config due
     // to custom, stubbed or added pads.
-    .NDioPads(23),
+    .NDioPads(31),
     .NMioPads(53),
     .DioPadType ({
       BidirStd, // IO_TRIGGER
       BidirStd, // IO_CLKOUT
+      BidirStd, // IO_UPHY_CFG
+      BidirStd, // IO_UPHY_MODE
+      BidirStd, // IO_UPHY_RCV
+      BidirStd, // IO_UPHY_OEB
+      BidirStd, // IO_UPHY_VM
+      BidirStd, // IO_UPHY_VP
+      BidirStd, // IO_UPHY_VMO
+      BidirStd, // IO_UPHY_VPO
       InputStd, // JTAG_SRST_N
       InputStd, // POR_BUTTON_N
       AnalogIn0, // IO_CLK_N
@@ -366,6 +398,14 @@
     .dio_pad_io ({
       IO_TRIGGER,
       IO_CLKOUT,
+      IO_UPHY_CFG,
+      IO_UPHY_MODE,
+      IO_UPHY_RCV,
+      IO_UPHY_OEB,
+      IO_UPHY_VM,
+      IO_UPHY_VP,
+      IO_UPHY_VMO,
+      IO_UPHY_VPO,
       JTAG_SRST_N,
       POR_BUTTON_N,
       IO_CLK_N,
@@ -457,6 +497,14 @@
     .dio_in_o ({
         manual_in_io_trigger,
         manual_in_io_clkout,
+        manual_in_io_uphy_cfg,
+        manual_in_io_uphy_mode,
+        manual_in_io_uphy_rcv,
+        manual_in_io_uphy_oeb,
+        manual_in_io_uphy_vm,
+        manual_in_io_uphy_vp,
+        manual_in_io_uphy_vmo,
+        manual_in_io_uphy_vpo,
         manual_in_jtag_srst_n,
         manual_in_por_button_n,
         manual_in_io_clk_n,
@@ -482,6 +530,14 @@
     .dio_out_i ({
         manual_out_io_trigger,
         manual_out_io_clkout,
+        manual_out_io_uphy_cfg,
+        manual_out_io_uphy_mode,
+        manual_out_io_uphy_rcv,
+        manual_out_io_uphy_oeb,
+        manual_out_io_uphy_vm,
+        manual_out_io_uphy_vp,
+        manual_out_io_uphy_vmo,
+        manual_out_io_uphy_vpo,
         manual_out_jtag_srst_n,
         manual_out_por_button_n,
         manual_out_io_clk_n,
@@ -507,6 +563,14 @@
     .dio_oe_i ({
         manual_oe_io_trigger,
         manual_oe_io_clkout,
+        manual_oe_io_uphy_cfg,
+        manual_oe_io_uphy_mode,
+        manual_oe_io_uphy_rcv,
+        manual_oe_io_uphy_oeb,
+        manual_oe_io_uphy_vm,
+        manual_oe_io_uphy_vp,
+        manual_oe_io_uphy_vmo,
+        manual_oe_io_uphy_vpo,
         manual_oe_jtag_srst_n,
         manual_oe_por_button_n,
         manual_oe_io_clk_n,
@@ -532,6 +596,14 @@
     .dio_attr_i ({
         manual_attr_io_trigger,
         manual_attr_io_clkout,
+        manual_attr_io_uphy_cfg,
+        manual_attr_io_uphy_mode,
+        manual_attr_io_uphy_rcv,
+        manual_attr_io_uphy_oeb,
+        manual_attr_io_uphy_vm,
+        manual_attr_io_uphy_vp,
+        manual_attr_io_uphy_vmo,
+        manual_attr_io_uphy_vpo,
         manual_attr_jtag_srst_n,
         manual_attr_por_button_n,
         manual_attr_io_clk_n,
@@ -897,6 +969,45 @@
 
 
 
+  ///////////////////
+  // USB for FPGA  //
+  ///////////////////
+  logic usb_rx_d;
+  logic usb_tx_d;
+  logic usb_tx_se0;
+  logic usb_dp_pullup_en;
+
+  // RCV
+  assign manual_attr_io_uphy_rcv = '0;
+  assign usb_rx_d = manual_in_io_uphy_rcv;
+
+  // OEB
+  assign manual_attr_io_uphy_oeb = '0;
+  assign manual_out_io_uphy_oeb = ~dio_oe[DioUsbdevUsbDp];
+  assign manual_oe_io_uphy_oeb = 1'b1;
+
+  // VP / VPO
+  assign manual_attr_io_uphy_vpo = '0;
+  assign manual_oe_io_uphy_vpo = 1'b1;
+  assign manual_out_io_uphy_vpo = dio_out[DioUsbdevUsbDp];
+  assign dio_in[DioUsbdevUsbDp] = manual_in_io_uphy_vp;
+
+  // VM / VMO
+  assign manual_attr_io_uphy_vmo = '0;
+  assign manual_oe_io_uphy_vmo = 1'b1;
+  assign manual_out_io_uphy_vmo = dio_out[DioUsbdevUsbDn];
+  assign dio_in[DioUsbdevUsbDn] = manual_in_io_uphy_vm;
+
+  // MODE
+  assign manual_attr_io_uphy_mode = '0;
+  assign manual_oe_io_uphy_mode = 1'b1;
+  assign manual_out_io_uphy_mode = 1'b1;
+
+  // CONFIG
+  assign manual_attr_io_uphy_cfg = '0;
+  assign manual_out_io_uphy_cfg = usb_dp_pullup_en;
+  assign manual_oe_io_uphy_cfg = 1'b1;
+
   //////////////////
   // PLL for FPGA //
   //////////////////
diff --git a/hw/top_matcha/rtl/autogen/top_matcha.sv b/hw/top_matcha/rtl/autogen/top_matcha.sv
index 42be2ab..bac7343 100644
--- a/hw/top_matcha/rtl/autogen/top_matcha.sv
+++ b/hw/top_matcha/rtl/autogen/top_matcha.sv
@@ -234,10 +234,10 @@
   input  prim_mubi_pkg::mubi4_t       ast_init_done_i,
   output logic       sck_monitor_o,
   input  logic       usbdev_usb_rx_d_i,
+  output logic       usbdev_usb_rx_enable_o,
   output logic       usbdev_usb_tx_d_o,
   output logic       usbdev_usb_tx_se0_o,
   output logic       usbdev_usb_tx_use_d_se0_o,
-  output logic       usbdev_usb_rx_enable_o,
   output logic       usbdev_usb_ref_val_o,
   output logic       usbdev_usb_ref_pulse_o,
 
diff --git a/util/topgen_matcha/templates/chiplevel.sv.tpl b/util/topgen_matcha/templates/chiplevel.sv.tpl
index 1fdcf86..1629cb6 100644
--- a/util/topgen_matcha/templates/chiplevel.sv.tpl
+++ b/util/topgen_matcha/templates/chiplevel.sv.tpl
@@ -824,6 +824,7 @@
     manual_in_otp_ext_volt
   };
 
+% if target["name"] != "nexus":
   ///////////////////////////////
   // Differential USB Receiver //
   ///////////////////////////////
@@ -863,6 +864,7 @@
     .usb_diff_rx_obs_o ( usb_diff_rx_obs       ),
     .input_o           ( usb_rx_d              )
   );
+% endif
 
   //////////////////////
   // Top-level design //
@@ -975,6 +977,45 @@
 ## FPGA shared                                                   ##
 ###################################################################
 % if target["name"] in ["nexus"]:
+  //////////////////////////////////////////////
+  // USB for FPGA (USB1T1105AMHX transceiver) //
+  //////////////////////////////////////////////
+  logic usb_rx_d;
+  logic usb_tx_d;
+  logic usb_tx_se0;
+  logic usb_dp_pullup_en;
+
+  // RCV
+  assign manual_attr_io_uphy_rcv = '0;
+  assign usb_rx_d = manual_in_io_uphy_rcv;
+
+  // OEB
+  assign manual_attr_io_uphy_oeb = '0;
+  assign manual_out_io_uphy_oeb = ~dio_oe[DioUsbdevUsbDp];
+  assign manual_oe_io_uphy_oeb = 1'b1;
+
+  // VP / VPO
+  assign manual_attr_io_uphy_vpo = '0;
+  assign manual_out_io_uphy_vpo = dio_out[DioUsbdevUsbDp];
+  assign manual_oe_io_uphy_vpo = 1'b1;
+  assign dio_in[DioUsbdevUsbDp] = manual_in_io_uphy_vp;
+
+  // VM / VMO
+  assign manual_attr_io_uphy_vmo = '0;
+  assign manual_out_io_uphy_vmo = dio_out[DioUsbdevUsbDn];
+  assign manual_oe_io_uphy_vmo = 1'b1;
+  assign dio_in[DioUsbdevUsbDn] = manual_in_io_uphy_vm;
+
+  // MODE
+  assign manual_attr_io_uphy_mode = '0;
+  assign manual_out_io_uphy_mode = 1'b1;
+  assign manual_oe_io_uphy_mode = 1'b1;
+
+  // CONFIG
+  assign manual_attr_io_uphy_cfg = '0;
+  assign manual_out_io_uphy_cfg = usb_dp_pullup_en;
+  assign manual_oe_io_uphy_cfg = 1'b1;
+
   //////////////////
   // PLL for FPGA //
   //////////////////