/*
 * Copyright 2023 Google LLC
 * Copyright lowRISC contributors
 *
 * Licensed under the Apache License, Version 2.0 (the "License");
 * you may not use this file except in compliance with the License.
 * You may obtain a copy of the License at
 *
 *      http://www.apache.org/licenses/LICENSE-2.0
 *
 * Unless required by applicable law or agreed to in writing, software
 * distributed under the License is distributed on an "AS IS" BASIS,
 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 * See the License for the specific language governing permissions and
 * limitations under the License.
 */


#include "sw/device/lib/dif/dif_dma.h"

#include <stddef.h>

#include "dma_regs.h"  // Generated.
#include "sw/device/lib/base/bitfield.h"
#include "sw/device/lib/base/macros.h"
#include "sw/device/lib/dif/dif_base.h"

dif_result_t dif_dma_read_config(const dif_dma_t *dma, uint32_t *config) {
  if (dma == NULL) {
    return kDifBadArg;
  }

  *config = mmio_region_read32(dma->base_addr, DMA_CONFIG_INFO_REG_OFFSET);
  return kDifOk;
}

dif_result_t dif_dma_enable_loop(const dif_dma_t *dma) {
  if (dma == NULL) {
    return kDifBadArg;
  }
  uint32_t reg = mmio_region_read32(dma->base_addr, DMA_CTRL_REG_OFFSET);

  mmio_region_write32(
      dma->base_addr, DMA_CTRL_REG_OFFSET,
      reg | 1 << DMA_CTRL_WTR_LOOP_BIT | 1 << DMA_CTRL_RDR_LOOP_BIT);
  return kDifOk;
}

dif_result_t dif_dma_begin(const dif_dma_t *dma) {
  if (dma == NULL) {
    return kDifBadArg;
  }

  uint32_t reg = mmio_region_read32(dma->base_addr, DMA_CTRL_REG_OFFSET);

  mmio_region_write32(
      dma->base_addr, DMA_CTRL_REG_OFFSET,
      reg | 1 << DMA_CTRL_WTR_START_BIT | 1 << DMA_CTRL_RDR_START_BIT |
          1 << DMA_CTRL_WTR_SYNC_DIS_BIT | 1 << DMA_CTRL_RDR_SYNC_DIS_BIT);
  return kDifOk;
}

dif_result_t dif_dma_configure_reader(const dif_dma_t *dma, uint32_t start_addr,
                                      uint32_t line_length, uint32_t line_count,
                                      uint32_t line_stride) {
  if (dma == NULL) {
    return kDifBadArg;
  }

  mmio_region_write32(dma->base_addr, DMA_RDR_START_ADDR_REG_OFFSET,
                      start_addr);
  mmio_region_write32(dma->base_addr, DMA_RDR_LENGTH_REG_OFFSET, line_length);
  mmio_region_write32(dma->base_addr, DMA_RDR_LINE_CNT_REG_OFFSET, line_count);
  mmio_region_write32(dma->base_addr, DMA_RDR_STRIDE_REG_OFFSET, line_stride);

  return kDifOk;
}

dif_result_t dif_dma_configure_writer(const dif_dma_t *dma, uint32_t start_addr,
                                      uint32_t line_length, uint32_t line_count,
                                      uint32_t line_stride) {
  if (dma == NULL) {
    return kDifBadArg;
  }

  mmio_region_write32(dma->base_addr, DMA_WTR_START_ADDR_REG_OFFSET,
                      start_addr);
  mmio_region_write32(dma->base_addr, DMA_WTR_LENGTH_REG_OFFSET, line_length);
  mmio_region_write32(dma->base_addr, DMA_WTR_LINE_CNT_REG_OFFSET, line_count);
  mmio_region_write32(dma->base_addr, DMA_WTR_STRIDE_REG_OFFSET, line_stride);

  return kDifOk;
}