Revision 1.1
Design Verification Methodology in Opentitan has been followed in matcha.
Currently, VCS is used as the major simulator for running DV tests in matcha.
At the root of shodan repo:
export ROOTDIR=`pwd` export proj_root=$ROOTDir/hw/matcha export titan_root=$ROOTDIR/hw/opentitan-upstream export PYTHONPATH=$ROOTDIR/hw/matcha/util:$titan_root/util:$titan_root/util/dvsim:$PYTHONPATH
cd $ROOTDIR/hw/matcha bazel build @kelvin_hw//hdl/chisel:kelvin.core # build kelvin RTL util/dvsim_match/dvsim.py \ hw/top_matcha/dv/chip_sim_cfg.hjson \ -i <test_name>
Use -v
option to dump out the debug messages from the simulation. For example:
util/dvsim_match/dvsim.py \ hw/top_matcha/dv/chip_sim_cfg.hjson \ -i <test_name> -v d
To dump waveforms from the simulation, use the -w
or --waves
option to pass the argument to dvsim.py. For example:
util/dvsim_match/dvsim.py \ hw/top_matcha/dv/chip_sim_cfg.hjson \ -i <test_name> \ -w fsdb
To debug with Verdi:
cd ${proj_root}/scratch/<branch>/chip_matcha_asic-sim-vcs/default verdi -dbdir ./simv.daidir
Sparrow HW DV Notes describes how to set up the bazel runs on EDACloud.
In an air-gapped environment like EDACloud, DV tests can be invoked from hw/matcha with bazel. Here is the sample bazel command:
bazel run //util/dvsim_matcha:dvsim.py \ --distdir=`pwd` \ -- hw/top_matcha/dv/chip_sim_cfg.hjson \ -i chip_sw_uart_tx_rx
initial begin $assertoff(0, tb.dut); end
`define STOP_COND 0 `define PRINTF_COND 0
at the top of the files:
hw/top_matcha/ip/ml_top/rtl/xbar_sram.v
to turn off the $fatal statements and the unwanted debug messages